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2. installation directory Config Section Code Datasheets DNMEG Daughtercard DNMEG Observation Daughtercard Documentation FPGA Reference Designs PCle Software Applications Schematics USB Software Applications Figure 2 DN7006K10PCIe 8T CD ROM Directory Structure A description of the CD ROM directory contents is listed in Table 1 Please visit The Dini Group website for the most recent revision of these documents Table 1 CD ROM Directory Contents CD ROM Directory Contents Directory Name Desctiption of Contents Config Section Code Configuration source code not intended to be used by the customet Datasheets Datasheets for all the components used on the boatd DN7006K10PCle 8T User Manual www dinigroup com 7 GETTING STARTED DNMEG_Intercon_Daughtercard The DNMEG Intercon is a daughter card that bridges the expansion signals between two 400 pin MEG Array connectors DNMEG Observation Daughtercard The DNMEG Obs Observation Daughter is a complete solution for observation of signals on the 400 pin MEG Array connector Documentation Contains this document and other project related documentation FPGA_Reference_Designs Contains the source and compiled programming files for the DN7006K10PCIe ST reference designs PCle Software Applications
3. 178 180 APPENDIX A USF KILE e REOR RERO EPOR AENEAN USER NO motae dt Pd ORDERING INFORMATION OPTIONAL EQUIPMENT Compatible Dini Group 2 ette ute dtt rea ee beet one eet iu 180 Memories Extenders IDEON ir a E EREEnRURURORDRE RERO ADU Compatible third party products COMPLIANCE DATA ii er E E E REN ERU PME O E QUERER RRE LOOT TATTA AEE E EE PCIe SIG Environmental Pete PERPE dos 9A TA Lead Free The USA Schedule B nu niber based on HTS 184 Export control classification number ECON n 184 List of Figures DN7006KTO0PCIe ST Emulation one e erdt 2 Figure 2 DN7006K10PCIe 8T CD ROM Directory Structure Figure 3 CompactFlash Directory Listing Figure 4 MSEL Configuration Resistors default FPP Figure 5 DN7006K10PCIe 8T Logic Emulation Board Block Diagram Figure 6 MCU EEPROM Interface Figure 7 MCU SRAM Figure 8 MCU Flash Figure 9 USB Connector Figure 10 MCU Configuration FPGA Serial Port Figure 11 Configuration PR
4. lt lt C DQ39 C DO Ct gt C 2040 c C DQ41 DIMMC DQ42 ci C DQ43 en ses DN7006K10PCle 8T User Manual www dinigroup com 102 HARDWARE DESCRIPTION seas D D D D D D D D D D D D D IMM IMM IMM IMM IMM IMM IMM IMM IMM IMM IMM IMM IMMC IMM IMM IMM IMM IMM IMM IMM IMM IMM IMM IMM IMM C_DQSOP 56 BA12 j40 29 56 AY15 140 70 56 18 140 129 56 AY18 140 131 C DQSIP C DQS2N cr se 56 AY17 40 146 56 AW17 40 148 56 BA28 40 167 DN7006K10PCle 8T User Manual www dinigroup com 103 HARDWARE DESCRIPTION IMM D D 25 AV18 IMM DN7006K10PCle 8T User Manual www dinigroup com 104 HARDWARE DESCRIPTION 25 AW11 J8 32 25 AW10 J8 30 25 AW27 18 166 25 AV27 18 164 IMM IMM IMM IMM IMM IMM IMM IMM IMM IMM IMM cc 25 AN16 25 BA13 25 14 25 16 25 18 25 AR18 25 AN24 25 AW24 C ER Dus Tle od Bon tal 1 59 DIMMD DM5 D DM6 D D D D c IMM IMM IMM IMM IMM IMM IMM IMM IMM IMM IMM IMM MM D 25 BB14 G 25 AT13 25 AV13 25 AP14 25 14 25 16 25 13 25 AU1
5. EEUU EE AE XI EEUU UH REA NE CUM ERRORS 18 3 PCIE AETEST APPLICATION 34 3 22 Running AETEST D Ede EI UR Ute BER RUN ERROR D 20 3 3 Compiling AETEST 3 3 1 Compiling AETest for Windows XP PROGRAMMING CONFIGURING THE 23 1 cp 23 PREPARING THE CONFIGURATION FLES E EE AEE E 24 2 1 Creating Configuration File 24 2 1 1 Format of main txt 3 3 1 3 2 Configuration MSEL Resistors 3 3 HyperTerminal Setup 3 4 Configuring the FPGA 3 4 1 Description of Menu Options 4 CONFIGURING AN FPGA H W USING entente 31 4 1 4 2 5 5 1 29 6 SETTING UP THE CLOCK FREQUENCIES ces
6. 56 18 56 25 56 26 56 AL17 56 AK17 56 AU19 56 16 56 15 56 AL24 56 15 56 AW23 56 AL23 56 AY20 56 AL18 56 AY23 56 AW20 56 AV25 56 AP25 56 AL16 56 AV15 56 AW11 56 AW10 56 AW27 56 AV27 56 BA9 DN7006K10PCle 8T User Manual www dinigroup com 100 J40 102 40 99 40 98 40 97 40 94 40 92 J J J J J HARDWARE DESCRIPTION DIMMC DM3 DIMMC_DM4 DIMMC DM7 D D D D D D D C DQ15 C 2016 IMM IMM IMM IMM IMM IMM IMM IMM IMMC IMM IMM IMM IMM IMM IMM IMM IMM IMM IMM DN7006K10PCle 8T User Manual c FPGA Pin 56 AY9 56 16 56 13 56 AT14 56 AV16 56 BB18 56 AR18 56 AN24 56 AW24 56 BB11 56 AY11 56 AY14 56 AU15 56 AW13 56 AW14 56 BB14 56 AW15 56 AT13 56 AV13 56 AP14 56 AN14 56 AR16 56 AR13 56 AU13 56 AU14 56 AR15 56 BB16 56 BB17 56 AU16 SODIMM Pin J40 80 j40 10 j40 26 140 52 140 67 40 36 40 38 40 43 40 45 40 55 40 57 40 17 o 5 1 J www dinigroup com 101 HARDWARE DESCRIPTION DIN DID DID DID DID DID DID DI 1 01061016 C DO31 56 AP20 740 123 TEE TEST DIN DIN DIN DIN DID DID DID C_DQ32 C DQ33 e C c MMC 0035 DIMMC_DQ36 C_DQ37
7. mme UC 01 20 016 1 DN7006K10PCle 8T User Manual www dinigroup com 134 HARDWARE DESCRIPTION Signal Name Virtex 5 FPGA Pin FPGA A Pin PCIE U24 AC13 U26 AA7 PCTE_PCLK_QP U24 AC12 U26 AA8 11 Miscellaneous FPGA IO Headers FPGA A C D and F provide easy access IO on 10 pin IDC headers placed along the bottom right edge of the PCB The IO levels need to conform to the VCCIO voltage for the IO bank on the FPGAs 11 1 1 FPGA IO Header Circuit See Figure 37 for the hardware implementation of the general purpose IO Note These signals are not buffered exercise extreme care to avoid static discharge into these pins J21 1 3 5 7 9 TSM 105 01 T DV Figure 37 Stratix III FPGA IO Header FPGA D 11 1 2 Connections between Stratix Ill FPGAs and 10 pin IO Headers The connection between the 5 FPGAs and the 10 pin IO Headers are shown in Table 33 Table 33 Connection between Stratix III FPGAs and 10 pin IO Headers Signal Name Stratix III FPGA Pin IO Header Pin FPGA A 10 pin IO Header 100 718 1 101 718 3 102 18 5 FPGA A IO3 118 7 FPGA A IO4 118 2 105 18 4 106 J18 6 U U U U U U U U
8. H 0 038400 Mhz 4 15787 624 4 15787 H 0 044100 Mhz 7 139971 7618 7 9997 0 048000 Mhz 7 9185 499 7 9185 0 050000 Mhz 1 969 23 6 9699 0 060000 Mhz 3 5773 199 3 11547 0 075000 Mhz 2 10777 319 2 10777 0 076810 Mhz 5 168383 7498 5 7015 H 0 096000 Mhz B 5613 249 5 5613 0 100000 Mhz 1 969 23 6 4849 H 0 150000 Mhz 0 4041 79 4 4041 H 0 176400 Mhz 3 72667 2516 3 3927 0 192000 Mhz 4 3157 124 4 3157 H 0 220000 Mhz 7 1377 74 4 2795 H 0 325000 Mhz 3 13857 479 3 2131 0 440000 Mhz 7 1377 74 4 1377 0 455000 Mhz 3 13857 479 6 1065 0 880000 Mhz 7 1377 74 0 1377 1 843199 Mhz 4 15791 624 3 375 2 457600 Mhz 4 15791 624 3 281 3 276800 Mhz 4 47487 1874 3 211 3 579545 Mhz 5 7909 351 2 225 3 686399 Mhz 4 15791 624 3 187 4 096000 Mhz 7 2303 124 7 107 4 194304 Mhz 6 36307 1790 6 115 H 4 433617 Mhz 6 49867 2462 0 273 H 4 915200 Mhz 7 2303 124 7 89 6 144000 Mhz 4 631 24 1 157 7 372799 Mhz 4 15791 624 3 93 8 192000 Mhz 7 2303 124 7 53 8 867238 Mhz 1 2153 52 T 49 DN7006K10PCle 8T User Manual www dinigroup com 75 HARDWARE DESCRIPTION H 9 216000 Mhz 7 2303 124 7 47 H 9 830400 Mhz 4 15871 624 4 61 10 160000 Mhz 2 507 14 6 47 H 10 245000 Mhz 3 23221 799 3 67 11 059200 Mhz 7 2303 124 7 39 11 228000 Mhz 5 5613 249 5 47 11 289600 Mhz 3 3611 124 1 85 12
9. pee 42 Stratix III FPGA Clocking Resources 72 4 3 Clock Multipliers x4 573 4 3 1 General Clock Multiplier 041 CLK 60 74 4 3 2 Connections between the FPGAs and Clock 78 44 Daughter Card DC Header Clocks egere teet te ERE ERAN 81 4 4 1 EXT SMA amp DCD Global Clocks U30 442 DCE amp DCF Global Clocks UE EAR HIBERNIA 4 4 3 Connection between FPGAs and External Daughter Card D E amp F Global Clocks sese 82 4 4 4 Secondary Daughter Card DC Header Clocks 2 4 4 5 Connection between FPGAs and the Secondary DC Header Clocks 84 454 ERCE Reference a ep 5 4 5 1 PCIe Reference Clock 85 452 Connection between FPGAs and the PCIe Reference Clock Buffer 4 6 Main Bus Clock CLK setis oro a de a 4 6 1 Main Bus Clock Circuit 4 6 2 Connection between FPGAs and the Main Bus Clock 87 4 7 External SMA Clock Inputs one per FPGA 4 7 1 External Clock Input Circuit FPGA nete tm RUP CREER rie OUO DER RES 88 4 7 2 Connection between Stratix III FPGAs and External SMA Connectors see esse eee 88 4 8 External Clock Test Points one per FPGA x dune e esii 89 4 8 1 External Clock Test Point Circuit FPGA c eerte a Em CER d e ae UR ete ee bets 89 4 8 2 Connection between Stratix III FPGAs and External Tes
10. 4 4 4 Secondary Daughter Card DC Header Clocks Two secondary bidirectional LVDS clocks are provided on the daughter card header Pin E1 and and they are connected to the clock inputs on the Stratix IIT FPGAs IO bank that is connected to the daughter card header see Figure 20 These clocks need to comply with the IO requirements of the Stratix III FPGA IO bank they are connected too DN7006K10PCle 8T User Manual www dinigroup com 83 HARDWARE DESCRIPTION P4 2 DCDOPTXO DCDOPRXO DCDONTXO D4 0 o RX LOP B4 DCDONRXO BO TX LON LON DCDOPTXI 6 Hx Lip A8 DCDOPRXI DCDONTXI D6 8 B6 _ DCDONRXI DCDOPDO C7 PO XA 0 RX LIN TX L2P 5 RX DCDONDO D8 5 DCDONRXG TXL2N 3 L2N DCDOPDG C9 9 9 8 L3P DCDONDG D10 3 BIO DCDONRYX3 TXL3N f L3N DCDOPTX4 E X 80 ar Lay ATi DCDOPRXE DCDONTX4 p12 L4 x3 4 0 RX B12 DCDONRX4 E E RX LAN DCDOPTX5 C13 i sr A13 DCDOPRX5 TXL5P 8 15 DCDONTX5 014 814 5 TXL5N 2 LSN DCDOPTX6 h ax Lap EATS DCDOPRXG DCDONTX6 8 2 Ley B16 DCDONRXS DCDOPTX7
11. DCE2NRX9 36 AD5 DCE2NTX0 36 AB5 DN7006K10PCle 8T User Manual www dinigroup com 164 HARDWARE DESCRIPTION Daughter Card SIGNAL Receptacle Bottom FPGA DCE2NTX1 25 026 36 12 DCE2NTX10 P5 F27 36 AD7 DCE2NTX11 P5 F39 36 AD13 DCE2NTX2 P5 D28 36 AC9 DCE2NTX3 5 030 36 AE6 DCE2NTX4 36 AF6 DCE2NTX5 36 AG5 DCE2NTX6 36 AD9 DCE2NTX7 36 AE9 DCE2NTX8 36 AD11 DCE2NTX9 36 AB7 DCE2PRX0 36 AC4 DCE2PRX1 36 AC1 DCE2PRX10 36 AD4 DCE2PRX11_GCB 36 AB4 DCE2PRX2 36 AE1 DCE2PRX3 36 AE3 DCE2PRX4 36 AG2 DCE2PRX5 36 AH2 DCE2PRX6 36 AF4 DCE2PRX7 36 AG4 DCE2PRX8 36 AE5 DCE2PRX9 36 AD6 DCE2PTXO 36 DCE2PTX1 36 AC13 DCE2PTX10 6 AD8 DCE2PTX11 36 AD14 DCE2PTX2 36 AC10 DN7006K10PCle 8T User Manual www dinigroup com 165 HARDWARE DESCRIPTION Daughter Card SIGNAL Receptacle Bottom DCE2PTX3 DCE2PTX4 DCE2PTX5 DCE2PTX6 DCE2PTX7 DCE2PTX8 DCE2PTX9 DCE3NRXO DCE3NRX1 DCE3NRX10 DCE3NRX11 DCE3NRX2 DCE3NRX3 DCE3NRX4 DCE3NRX5 DCE3NRX6 DCE3NRX7 DCE3NRX8 DCE3NRX9 DCE3NTX0 DCE3NTX1 DCE3NTX10 DCE3NTX2 DCE3NTX3 DCE3NTX4 DCE3NTX5 DCE3NTX6 DCE3NTX7 DN7006K10PCle 8T User Manual p5 C29 5 31 36 AE7 36 AF7 36 6 36 AD10 36 AE10 36 AD12 36 AB8 36 AN3 36 AP3 36 AU2 36 AY3 36 1 36 36 1 36 AV3 36 AW1 36 AT3 36 AU4 36 AR3 36 AJ12 36 11 36 6 36 AJ10 36 AK9 36 AK12 6 16 36 5 36 5 www dinigroup com 166 HARDWARE DESCR
12. RS232 FPGA RX RS232 FPGA 13 18 85232 FPGA RXD 9 R290 15232 12 RIOUT FN 17 85232 DNI P1 R20UT R2IN 412V 100 1 2 5R 18 3 4 P2 5VD R299 gund 45V LCD 7 eo K 9 10 RSe329HDN 24 P2 5VD R291 x SHDN 9 DNI 21 TSNF136 01 T DV 0381 0 tuF RS232 1 1 23 95232 ajel 1 MCU RS232_CPUMP2 1 03821 Q0 iuF RS232 CPUMP2 532 1 2 d 2 RS232 VPUMP 1 2 V 4 2 22 6 85232 VPUMP 5 6 1 2 v x IAX3388E C384 C380 C378 3 3 10 SOP65P638X110 24N O tuF 0 tuF TSMF T36 01 T DV P2 5VD 9 R293 4 7K RS232 FPGA TX R292 4 7K RS232 MCU RX Figure 31 MCU Configuration FPGA Serial Port There are two signals attached to the all the FPGAs Transmit Data 5232 TX e Receive Data 5232 FPGA TX and RX provide bi directional transmission of transmit and receive data No hardware handshaking is supported Since these signals are shared between all the FPGAs only FPGA can be in control of the bus at any particular time DN7006K10PCle 8T User Manual www dinigroup com 120 HARDWARE DESCRIPTION 7 1 2 Connections between FPGAs and 85232 Port The RS232 port is shared by all the FPGAs The connections between the FPGA and the RS232 Port are shown in Table 28 Table 28 Connections between FPGAS and the 5232 Port Signal Name F
13. ALERT TEMPA R631 ADDO 5 1 R632 7 NC ADDI 33 3 R59 00 NC VCC NC 16 4 7uF SOP63X600 16N Figure 32 Temperature Sensor A When the temperature drops below 80 the configuration circuitry will again allow the FPGA to configure When this occurs the following message will appear on the CONFIG RS232 port P2 An example test output is given below TEMPERATURE ALERT CURRENT TEMPERATURE 81 DEGREES C THRESHOLD TEMPERATURE 80 DEGREES C THE FPGA IS BEING CLEARED IN AN ATTEMPT TO PREVENT HEAT DAMAGE SOFTWARE WILL PREVENT RECONFIGURATION UNTIL THE TEMPERATURE DROPS A FULL DEGREE BELOW THE THRESHOLD TEMPERATURE TEMPERATURE ALERT CURRENT TEMPERATURE 79 DEGREES THRESHOLD TEMPERATURE 80 DEGREES C THE FPGA HAS DROPPED BELOW THE ALARM THRESHOLD AND MAY NOW BE RECONFIGURED The FPGA c
14. C MO q7 EVEN 11 ODD 11 Fag VICTOR C B10 VICTOR C EVEN 10 ODD 10 MCTOR C 51 EVEN 9 ODD 9 27 WICTOR C B8 MICTOR 53 EVEN 8 ODD 8 MICTOR A6 25 EVEN 7 ODD 7 26 C B6 MICTOR C 5 2721 EVEN E ODD_6 58 5 5g EVEN 5 ODD 5 50 VICTOR CE WCTOR T 31 EVEN 4 ODD 4 35 VICTOR CE M C 33 EVEN 3 ODD 3 34 V C 35 EVEN 2 ODD 2 36 V MICTOF C AD EVEN 1 ODD 1 C id EVEN 0 ODD 0 38 394 GND Loc is GND GND 41 GND 2 767004 2 Figure 38 38 Pin Mictor Header on C 12 1 2 FPGA to Mictor Header Table 34 shows the connections from the 38 pin Mictor header and the Stratix III FPGA Table 34 Connections between FPGAs and Mictor Headers Signal Name FPGA Pin Mictor Pin FPGA B U37 MICTOR A0 MICTOR B A1 MICTOR B A2 MICTOR B A3 MICTOR B A4 MICTOR B A5 MICTOR B A6 MICTOR B A7 MICTOR B MICTOR B B1 MICTOR B B2 C De ue ege ue DN7006K10PCle 8T User Manual www dinigroup com 138 HARDWARE DESCRIPTION Signal Name FPGA Pin Mictor Pin MICTOR B B3 3711 MICTOR B B4 37 R7 MICTOR B B5 37 R8 MICTOR B B6 37 M2 MICTOR B B7 37 M3 MICTOR B CLK A 37 V11 CLK B 37 U10 FPGA C U56 MICTOR A0 MICTOR C A1 MICTOR A2 MICTOR C A3 MICTOR A4 MICTOR A5 MICTOR A6 MICTOR
15. SY 89826LHY Figure 22 Main Bus Clock Buffer 4 6 2 Connection between FPGAs and the Main Bus Clock Buffer The connection between the FPGAs and the Bus clock buffer 035 are shown in Table 14 Table 14 Connection between FPGA and Main Bus Clock Buffers Signal Name Clock Buffer Pin FPGA Pin 48 35 60 26 42 48 35 61 26 41 MB48 BN 35 58 37 42 48 35 59 37 41 MB48 35 56 56 42 48 35 57 56 41 48 DN 35 54 25 42 48 DP 35 55 25 41 U U U U U U U U DN7006K10PCle 8T User Manual www dinigroup com 87 HARDWARE DESCRIPTION Signal Name Clock Buffer Pin FPGA Pin 35 52 36 AA42 MB48 EN 35 53 36 AA41 MB48 MB48 FN 35 50 55 AA42 MB48 FP 35 51 55 41 CLK MB48 35 44 24 10 48 35 45 24 E10 MB48 QSEN 35 46 143 118 48 QSEP 35 47 143 120 MB48 SN 35 62 U20 AA11 CL SP E 48 SP 35 63 U20 Y11 4 7 External SMA Clock Inputs one per FPGA Two SMA s are provided to allow for external differential clock FPGA x EXTp n input to each of the Stratix III FPGAs 4 7 4 External SMA Clock Input Circuit FPGA A Resistors R941 R951 can be preplace
16. The Stratix L family provides balanced logic memory and multiplier ratios for mainstream applications The Stratix E family is memory and multiplier rich for data centtic applications Modular I O banks with a common bank structure for vertical migration lend efficiency and flexibility to the high speed I O Package and die enhancements with dynamic on chip termination output delay and current strength control provide best in class signal integrity Based on a 1 1 V 65 nm all layer copper SRAM process the Stratix III family is a programmable alternative to custom ASICs and programmable processors for high performance logic digital signal processing DSP and embedded designs and architects Stratix III devices include optional configuration bit stream security through volatile or non volatile 256 bit Advanced Encryption Standard AES encryption Where ultra high reliability is required Stratix devices include automatic error detection circuitry DN7006K10PCle 8T User Manual www dinigroup com 57 HARDWARE DESCRIPTION to detect data corruption by soft errors in the configuration random access memory CRAM and user memory cells 2 1 Summary of Stratix Ill device features 337 500 equivalent logic elements LEs 20 491 Kbits of enhanced TriMatrix memory consisting of three RAM block sizes to implement true dual port memory and first in first out FIFO buffers High speed DSP blocks provide dedicated implem
17. 2 1 Compiling AETest usb AETest_usb can be compiled using Microsoft Visual Studio 6 or later or on any vetsion of Linux that supports the usbdevfs library DN7006K10PCle 8T User Manual www dinigroup com 18 INTRODUCTION TO THE SOFTWARE TOOLS A make file is provided but you must un comment one of the following lines to define which operating system you ate running In Windows you should run nmake ZDESTOS WIN ZDESTOS LINUX ZDESTOS SOLARIS 3 PCle AETEST Application AETEST utility program can test and verify the functionality of the DN7006K10PCIE 8T Logic Emulation board and provide data transfer to and from the User design All AETEST source code is included on the CD ROM shipped with your DN7006K10PCIE 8T Logic Emulation kit AETEST can be installed on a variety of operating systems including e Windows 2000 XP Vista Windows WDM linux 3 1 Functionality All communication to the board using this program is over PCI express In this way the basic functionality of PCI Express is tested The AETEST utility program contains the following tests DMA and BAR accesses over PCI Express When using the full function design for LXT DDR2 Memory Test Flash Test AETEST also provides the user with the following abilities e Recognize the DN7006K10PCIE 8T e Display Vendor and Device ID e Set PCle Device and Function Number Display all configured PCIe devices DN7006K10PCle 8T User Manu
18. 53 7 37 21 G1 53 8 37 21 CN 53 5 56 21 CLK G1 CP 53 6 56 BA21 CLK G1 DN 53 3 25 BB22 G1 DP 53 4 25 BA22 G1 EN 53 1 36 A22 CLK G1 EP 53 2 36 B22 CLK G1 EN 53 23 55 A22 G1 53 24 55 22 1 53 11 24 621 CLK G1 53 12 24 20 CLK G1 TN U U U U U U U U U U U U U U U 53 13 TP93 2 CLK G1 TP 53 14 TP93 1 LVDS Clock Multiplier CLK G2 Clocks provided for left and right side of the FPGAs CLK_G2_A_LN U50 58 U26 AA42 CLK G2 A LP U50 59 1726 41 02 050 56 U26 AA1 CLK G2 A RP DN7006K10PCle 8T User Manual U50 57 U26 AA2 www dinigroup com 79 HARDWARE DESCRIPTION Signal Name Clock Multiplier Pin FPGA Pin CLK G2 B LN 50 54 37 42 CLK G2 B LP 50 55 37 41 CLK G2 B RN 50 52 37 1 G2 B RP 50 53 37 2 G2 C LN 50 50 56 AA42 G2 C LP 50 51 56 41 G2 C RN 50 46 56 1 G2 C RP 50 47 56 AA2 CLK G2 D LN 50 44 25 AB42 CLK G2 D LP 50 45 25 AB41 CLK_G2_D_RN 50 42 25 AB1 CLK_G2_D_RP 50 43 25 AB2 CLK_G2_E_LN 50 40 36 AB42 CLK G2 E LP 50 41 36 ABA1 CLK G2 E RN 50 38 36 1 G2 RP 50 39 36 AB2 CLK G
19. 56 AW27 J40 166 56 AV27 140 164 DIMMD_CK1N 25 AW27 8 166 DIMMD 25 AV27 J8 164 SODIMM 39 FPGA 055 DIMMF 55 C26 J39 32 DIMMF 55 D26 139 30 DIMMF_CK1N 55 D10 39 166 DIMMF CK1P 55 E10 39 164 5 1 6 SODIMM connections to the Stratix lll FPGAs Table 20 shows the SODIMM connector pinouts and the connection to the Stratix III FPGAs Table 20 Connections between the Stratix III FPGAs and the SODIMMs Signal Name FPGA Pin SODIMM Pin SODIMM A J9 FPGA 026 DIMMA AU U26 H25 19 102 DN7006K10PCle 8T User Manual www dinigroup com 95 HARDWARE DESCRIPTION A2 _ 4 26 011 D _ D __ 7 _A8 _A9 26 G16 26 H16 26 D12 26 27 D D c I 21 I I I I I I I D D D D D D D 26 E10 26 M23 26 M22 26 A23 26 27 26 D16 26 A20 DN7006K10PCle 8T User Manual www dinigroup com 96 _CKIN 26 D10 a ec e c G HARDWARE DESCRIPTION FPGA Pin SODIMM Pin 26 H18 26 M18 26 A14 26 G13 26 B24 26 C25 26 K24 26 L24 26 C28 26 B27 26 25 26 25 26 618 26 F17 26 B16 26 A16 26 F23 26 G17 26 F 16 26 E16 26 A17 26 G20 26 F20 26 A18 26 H19 26 G19 26 F19 26 H24 26 A19 C eL pcc c U
20. EP3SL340 FPGA B EP3SL340 FPGA C EP3SL340 QSE Header QSE 060 01 L D A GEN1 2 5Gb s PCle x8 Figure 40 MainBus Interconnect 14 1 1 MainBus MB Header A QSE header J43 is provided for direct connection to the MainBus signals Samtec P N QSE 060 01 L D A see Figure 41 DN7006K10PCle 8T User Manual www dinigroup com 143 CLKBP CARD 00000000 gt lt lalo 0 51111161 5 555 5 2 02 02 Figure 41 MainBus Header HARDWARE DESCRIPTION J43 QSE 060 01 L D A BI MB2 MB3 N E ves MB8 MB zm MB12 MB10 11 MB13 12 MB13 ME MB14 15 MB17 MB18 MB16 MB17 MB19 MB20 MB18 MB19 MB21 MB22 MB20 MES MB23 MB24 MB22 23 25 26 MB24 MB25 MB27 MB28 MB26 27 29 MB30 28 29 MB31 MB32 MB30 MB33 MB34 PE MB35 MB36 MB34 MB35 MB37 MB38 2 MB39 MB38 MB39 n an es MBA MB42 MB43 MB44 MB45 MEAS MB46 MB47 MEAS MBED MB48 i MB49 ESE MB52 50 S MESI MB53 1822 MB52 53 m MB54 55 N MB60 5 MB61 861 mE MB62 8 MB63 AI 64 MB65 64 E MB65 PE MB66 MB67 WEES MB70 MB68 B 71 2 S 2 Mars MB74 a M
21. The JTAG Boundary Scan configuration interface is always available regardless of the Mode pin settings The JTAG Boundaty Scan configuration mode disables all other configuration modes to prevent conflicts between configuration interfaces Certain configuration pins are dedicated to configuration while others are dual purpose see datasheet Dual purpose pins serve both as configuration pins and as user I O after configuration Dedicated configuration pins retain their function after configuration The remainder of this section describes the functional blocks that entail the FPGA configuration environment 2 Preparing the Configuration Files Using the CompactFlash card is the preferred method to configure the FPGAs To control which bit file on the CompactFlash card is used to configure which FPGA a file named main txt must be created and copied to the root directory of the CompactFlash card The configuration process from the CompactFlash card cannot be performed without this file 2 1 Creating Configuration File main txt The main txt interface is used to control program the following features on the DN7006K10PCle 8T Logic Emulation Board e Basic Features o Configure FPGAs Setup Clock Frequencies and MUX Settings 5232 Monitor Verbose Level e Advanced Features o MainBus Read Write Transactions o Configuration Register Read Write Transactions Below is an example of a main txt file a description of
22. 37 um INTROREADY 715 1 E TIE TO VCC WAIT CF POWER ONA 10 516 CF_PDIAG sieeve WWE BVD1 PDIAG pMOS 3 BVD2 DASP REG vcc 500mA INPACK DMARQ VS1 GND 52 GND MI21 50PD SF EJR MI21 50PD SF EJR MOD R34 DNI 4 7K VS1 R27 VN DNEA7K CFV Figure 12 CompactFlash Connector Note Do not press down on the top of the CompactFLASH connector J5 if a CF card is not installed The metal case can short 3 3V to GND 3 3 2 CompactFlash connection to Spartan 3 Configuration FPGA Table 6 shows the connection between the CompactFlash connector and the Configuration FPGA Table 6 Connection between the CF connector and the Configuration FPGA Signal Name Configuration FPGA Connector CF_ATA_SEL U20 P18 J5 9 CF_CD1 U20 N21 J5 26 CF_CD2 U20 R18 J5 25 CF_CSO U20 N18 5 7 DN7006K10PCle 8T User Manual www dinigroup com 67 HARDWARE DESCRIPTION Signal Name Configuration FPGA Connector U20 P17 J5 32 CF_CSEL U20 P19 J5 39 DU U20 Y21 5 21 D1 U20 Y20 5 22 CF D2 U20 Y19 5 23 D3 U20 W22 5 2 D4 U20 Y22 5 3 D5 U20 V19 5 4 D6 U20 W19 5 5 D7 U20 W21 J5 6 CF_DASP U20 T19 5 45 U20 T20 5 44 U20 M21 5 43 INTRQ 120 118 15 37 CF_IOCS16 U20 T21 5 24 CF_IORD U20 R19 J5 34 CF_IORDY U20 T22 5
23. 55 D15 DIMMF_DQ49 ie 55 E24 DIMMF_DQ5 55 13 I I I I I D D D D D D D D D c 55 D13 55 F14 55 C14 55 B13 55 A12 55 K15 DIMMF DQ58 55 G14 sn c 55 G24 55 A26 55 24 55 25 55 25 55 28 55 828 e I I I lt lt lt DQS0P DIMMF DQSIN DQSIP DN7006K10PCle 8T User Manual www dinigroup com 111 _ _ _ _ _ _ _ _ _ MMF DQ57 55 14 _ _ _ _ _ _ _ _ _ _ HARDWARE DESCRIPTION 5 1 7 DIMMF_DQS6N FPGA Pin U55 B15 U55 C15 U55 B18 U55 C18 U55 C17 55 D17 55 A8 55 A9 55 B12 55 C12 55 E12 55 F12 55 H13 55 G23 U55 E25 U55 C20 U55 D14 55 E18 DDR2 PCB Trace Lengths SODIMM Pin 139 49 139 51 139 68 139 70 139 129 1 139 110 139 115 139 109 The DDR2 traces on the DN7006K10PCIe 8T Logic Emulation Board are routed to the following lengths refer to Table 21 Table 21 DDR2 PCB Trace Lengths Signal Name Routed Length mm Description DIMMA_CKON 70 05 Clock group DIMMA_AO 70 91 Control group DIMMA_DQO 70 06 Data byte group DIMMC_CKON 70 03 Clock group DIMMC 0 70 91 Control group DIMMC DN7006K10PCle 8T User Manual 70 00 www
24. CLK AN U31 11 1726 1 CLK AP 31 12 26 AB2 BN 31 9 37 1 EXTO BP 31 10 37 2 EXTO CN 31 7 56 1 EXTO 31 8 56 AB2 EXTO DN 31 5 25 1 CLK EXTO DP 31 6 25 AA2 EXTO EN 31 3 36 AA1 EXTO EP 31 4 36 AA2 EXTO DN7006K10PCle 8T User Gre Eu C 31 1 55 1 www dinigroup com 82 HARDWARE DESCRIPTION Signal Name Clock Buffer Pin FPGA Pin CLK EXTO FP 031 2 U55 AA2 031 13 U24 E11 CLK EXTO QP U31 14 U24 F12 FBN U31 23 U30 10 031 24 030 11 Daughter Card amp Zero Delay Global Clock Buffer CLK_EXT1 AN 046 11 U26 BB21 AP 046 12 U26 BA21 BN 46 9 U37 A21 BP 046 10 U37 B21 EXT1 CN U46 7 U56 A21 CLK EXT1 CP U46 8 U56 B21 CLK DN U46 5 U25 A22 DP 46 6 U25 B22 CLK EXT1 EN U46 3 U36 BB22 EP 46 4 U36 BA22 CLK U46 1 U55 BB22 46 2 U55 BA22 CLK U46 13 U24 E21 46 14 U24 E20 FBN 46 23 045 10 CLK_EXT1_FBP U46 24 U45 11
25. ETHF_TCK 58 6 59 5 ETHF_TX_CTL 58 31 55 D6 TXDO 58 30 55 D5 ETHF_TXD1 58 29 55 E6 ETHF_TXD2 58 28 55 F6 eee TXD3 58 27 55 10 Interface The PCI Express PCIe standard is a next generation evolution of the older PCI and PCI X parallel bus standards It is a high performance general purpose interconnect architecture designed for a wide range of computing and communications platforms It is a packet based point to point serial interface that is backward compatible with PCI and PCI X configurations device drivers and application software Table 31 shows the bandwidth for various lane configurations The effective bandwidth is lower than the raw bandwidth due to the overhead of the 8B 10B encoding and decoding used by the protocol Table 31 PCIe Bandwidth Raw Bandwidth per Direction Effective Bandwidth per Direction 2 5Gb s 2Gb s 5Gb s 4Gb s 10Gb s 8Gb s 20Gb s 16Gb s The Virtex 5 LXT and SXT platform FPGAs contain one PCI Express Endpoint block which implements Transaction Layer Data Link Layer and Physical Layer functions to provide complete PCI Express Endpoint functionality with minimal FPGA logic utilization Virtex 5 FPGA 024 is used to implement the PCIe Interface on the DN7006K10PClIe 8T Logic Emulation Board DN7006K10PCle 8T User Manual www dinigroup com 1
26. FPGA_A_IO7 J18 8 FPGA C 10 pin IO Header DN7006K10PCle 8T User Manual www dinigroup com 135 HARDWARE DESCRIPTION Signal Name Stratix III FPGA Pin IO Header Pin FPGA C IOO 56 BB28 38 1 FPGA C 101 56 AT22 138 3 C 102 56 22 138 5 103 56 AV22 38 7 FPGA C 104 56 AU22 138 2 105 56 AU21 38 4 FPGA C IO6 56 AV21 138 6 56 21 138 8 FPGA D 10 IO Header FPGA D 100 25 AK14 21 1 D IO1 25 AR9 121 3 FPGA D 102 25 AT9 J21 5 D IO3 25 AP9 J21 7 D 104 25 AP10 21 2 D IO5 25 AR12 21 4 106 25 12 121 6 D 107 25 11 121 8 D 108 25 28 J27 1 FPGA D IO9 25 22 J27 3 FPGA D 1010 25 AR22 J27 5 FPGA D 1011 25 AV22 J27 7 D IO12 25 AU22 J27 2 FPGA D 1013 25 AT16 27 4 D 1014 25 AW12 J27 6 FPGA D IO15 25 AR21 J27 8 FPGA F 10 pin IO Header FPGA F 100 32 1 F 101 32 3 102 132 5 DN7006K10PCle 8T User Manual www dinigroup com 136 HARDWARE DESCRIPTION Signal Name Stratix III FPGA Pin IO Header Pin FPGA F IO3 F FPGA F IO5 106 107 108 55 E9 132 7 55 11 132 2 55 611 32 4 55 132 6 55 86 132 8 55 9 13541 55 11 35 3 55 89 135 5 55 22 35 7 55 E2
27. The DN7006K10PCle 8T has been factory tested and pre programmed to ensure correct operation The user does not need to alter any jumpers or program anything to see the board work 1 2 Warnings DN7006K10PCle 8T User Manual Daughter Card Test Headers Over Voltage The 400 pin daughter card test headers are NOT 5V tolerant Take care when handling the board to avoid touching the components and daughter card connections due to ESD ESD Warning The board is sensitive to static electricity so treat the PCB accordingly The target markets for this product are engineers that are familiar with FPGAs and circuit boards However if needed the following web page has an excellent tutorial on the Fundamentals of ESD for those of you who are new to ESD sensitive products http www esda otg basics patt1 cfm Operating Temperature Avoid touching PTH012050WAZ power supply modules PSU1 PSU2 PSU3 PSU12 PSU13 and PSU 14 as they operate at high temperatures and may cause skin burns www dinigroup com 6 GETTING STARTED 2 Installing the Software For complete information regarding the USB Graphical User Interface GUI and installation instructions see the 058 Controller Manual available from The Dini Group website 2 1 Exploring the Customer CD The DN7006K10PCIe 8T CD ROM contains the following items the CD ROM does not auto install on the customer machine see Figure 2
28. 21 1 3 Daughter Cards Dini Group Daughter Cards connect to the MEG Array connector 400 pin using the standard Dini Group interface description DN7006K10PCle 8T User Manual www dinigroup com 181 HARDWARE DESCRIPTION DNMEG PCIE 8 lane PCIe express PHY card Host or downstream mode DDR2 module 4 FPGA LX40 LX160 DNMEG_ADC High speed Analog Digital Daughter Card Virtex 4 FPGA DDR2 memory module 250Msps 12 bit ADC 60dB SNR 10 bits 200kHz 75Mhz DNMEG 5 two versions Xilinx Virtex 5 LXT FPGA with high speed serial interfaces SMA SATA SEP 5 PCI Express DNMEG INTERCON Connects headers for A and B together DNMEG OBS Adjustable voltage tenth inch pitch headers User LEDs Iwo Mictor 38 connectors SMA global clock inputs for host board DN7006K10PCle 8T User Manual www dinigroup com 182 HARDWARE DESCRIPTION an DNMEG Obs 433V 4127 Power LEDs VO Voltage Control 1 24 3 40 pin Header 0 1 pin spacing Samtec 3 Rocket LO channels 10 Control 40 pin Header 21 2 Compatible third party products The following products have been shown to work with the DN7006K10PCIE 8T Standard DDR2 modules 256 MB 15 512 MB 15 1GB 25 2GB 64 4GB eventually http www ctucial com store listmodule DDRIT list html Xilinx Platform USB Cable required for JTAG FPGA programming firmware update ChipScope
29. 26 6 PCIE 2 24 AA22 26 Y1 PCIE EXTRA3 24 AE13 26 W1 PCIE EXTRA4 24 AD13 26 C2 PCIE EXTRA5 U U U U U U U U U U U U U U U 24 AD14 Lee E 26 1 PCIE EXTRA6 U24 AA25 R680 2 PCIE 7 U24 AB26 R687 2 PCIE 8 U24 G20 R571 2 PCIE IN INFOO U24 Y22 26 G5 PCIE IN INFO1 U24 Y23 26 N9 PCIE IN PERSTN U24 H11 26 U12 PCIE IN SOF U24 AC9 26 N3 PCIE U24 AA9 26 P3 PCIE IN U24 W26 PCIE IN TRN RSTN U24 G11 26 M2 PCIE IN VALID U24 U22 26 E3 PCIE OUT ALL VALID U24 U24 26 A6 PCIE OUT ALMOST FULL U24 P21 26 E9 PCIE OUT CCO DN7006K10PCle 8T User Manual U24 A20 U U U U U U26 D2 U U U U U 26 9 www dinigroup com 131 HARDWARE DESCRIPTION Signal Name Virtex 5 FPGA Pin FPGA A Pin PCIE OUT CCI 24 J21 26 U3 PCIE OUT CC2 24 W24 26 F11 PCIE OUT CHANO 24 P26 26 E7 PCIE OUT 1 24 R26 26 F10 PCIE OUT CHAN2 24 P25 26 D9 PCIE OUT CLK LOCK 24 R21 26 K10 PCIE OUT D00 24 C13 26 F7 PCIE OUT 1001 24 C14 26 Y7 PCIE OUT D02 24 B14 26 F8 PCIE OUT D03 24 A13 26 D7 PCIE OUT D04 24 A14 26 D8 PCIE OUT D05 24 A15 26 Y6 PCIE OUT D06 24 B15 26 M14 PCIE OUT 007 24 C16 26 M15 PCIE OUT D08 24 B16 26 Y3
30. 5 0V PSU13 P33VD 3 3 PSU4 25 2 5 Any ATX type power supply is adequate The Dini Group recommends a power supply rated for 300W Note that only a 6 pin PCI Express graphics cable should be used This connector easily confused with the now defunct AUX POWER connector also 6 pin and the 4 and 6 pin EPS motherboard connections The connector is keyed so the wrong connectors will have difficulty fitting properly into the board DN7006K10PCle 8T User Manual www dinigroup com 148 HARDWARE DESCRIPTION Figure 44 ATX Power Supply 16 2 1 External Power Connector Figure 45 indicates the connections to the external power connector This header is fully polarized to prevent reverse connection and is rated for 600VAC at contact An crowbar circuit utilizing Diode D1 is provided to protect the 12V supply 45558 0002 D1 45558 0002 MBRB4030T4G Note Reverse polarity protection 1OuF 0 1uF 16V 16V 20 20 CER CER Figure 45 External Power Connection Note Header J7 is not hot plug able Do not attach power while power supply is ON DN7006K10PCle 8T User Manual www dinigroup com 149 HARDWARE DESCRIPTION 17 Daughter Card Headers The DN7006K10PCle 8T have three 400 pin daughter card headers P5 and P6 placed on the bottom of PCB All signals on the DN7006K10PCIe headers are routed
31. Check Idcode mp Read Status Register perations 1 Programmed successfully PROGRESS END End Operation Elapsed time 3 sec Transcript Output Enar Warming Configuration Platform Cable LISB 6 MHz usb hs 5 Verify that the DONE blue LED DS44 is enabled indicating successful configuration of the FPGA 7 7 4 Configuring the PCle FPGA PROM using JTAG Cable Xilinx This section lists detailed instructions for programming the Xilinx Virtex 5 PCIE FPGA PROM sing the Xilinx ISE Version 9 2 04 tools Power the DN7006K10PCIe 8T Logic Emulation Board and verify that the Power LED DS25 is ON Note This User Manual will not be updated for every revision of the Xilinx tools so please be aware of minor differences 1 Connect Xilinx Platform Cable USB to the V5T header J1 on the DN7006K10PCIe 8T Logic Emulation Board 2 OpeniMPACT and create a new default project Select Configure devices using Boundary Scan J TAG from the iMPACT welcome menu DN7006K10PCle 8T User Manual www dinigroup com 52 PROGRAMMING CONFIGURING THE HARDWARE iMPACT Welcome to iMPACT Please select an action from the list below gt Configure devices using Boundary Scan JTAG Automatically connect to a cable and identify Boundary Scan chain v Prepare a PROM File Prepare a System ACE File Prepare a Boundary Scan File Configure devices using
32. DN7006K10PCIe 8T are routed point to point using dedicated LVDS routes The arrival times of the clock edges at each FPGA are phase aligned length matched on the PCB within about 100ps These clocks are all suitable for synchronous communication among FPGAs The connections between the FPGAs and the Clock Multipliers are shown in Table 10 Table 10 Connections between FPGAs and Clock Multipliers Signal Name Clock Multiplier Pin FPGA Pin General Clock Multiplier CLK G0 AN 43 9 26 BB22 FPGA A GO AP 43 10 26 BA22 CLK G0 BN 43 7 37 A22 FPGA B CLK GO BP 43 8 37 22 43 5 56 22 CLK GO CP 43 6 56 B22 CLK DN 43 3 25 A21 FPGA D CLK GO DP 43 4 25 B21 EN 43 1 36 21 FPGA E CLK GO EP DN7006K10PCle 8T User Manual 43 2 36 BA21 www dinigroup com 78 HARDWARE DESCRIPTION Signal Name Clock Multiplier Pin FPGA Pin 43 23 U55 BB21 FPGA CLK GO FP 43 24 U55 BA21 CLK 43 11 U24 D18 43 12 U24 E17 CLK GO TN 43 13 TP76 2 CLK GO TP 43 14 TP76 1 DDR2 Clock Multiplier G1 CLK G1 AN 53 9 26 A21 CLK G1 AP 53 10 26 B21 CLK G1 BN
33. FEXT echo and other types of ambient environment and system noise 9 1 Ethernet Interface An Ethernet MAC must be implemented on FPGA D U25 and FPGA F U55 The RGMII interface is used to interface the Ethernet PHY to the FPGAs 9 1 1 Serial Management Interface The EEDAT and EECLK signals are intended to connect the PHY to an EEPROM that would contain configuration settings for the device LED behavior MII timing Link speed duplex auto negotiation etc The MDIO interface is however connected directly to the FPGA The intent is for the user to implement an EEPROM using the FPGA In addition the FPGA can store data in the EEPROM DN7006K10PCle 8T User Manual www dinigroup com 123 HARDWARE DESCRIPTION 9 1 2 Ethernet LED s The VSC8601 device drives up to three LEDs directly All LED outputs are active low and are driven using 3 3V supply The Amber LED indicates Activity and the Green LED indicates link in Gigabit mode Discrete LEDs 12518 and DS114 located next to the RJ45 connectors indicates link in 100Mbit mode The 10Mb link LED is not configured 9 1 3 Timing The board is designed using a DCM in zero delay mode on the clock CLK125_ETH the interface will meet timing clocking all IOs on this clock Alternately use the CLK_ETH_RX to clock inputs and clock CLK_ETH_TX on the same clock as the rest of the transmit signals By default the VSC8601 s internal clock compensation mode is enabled This causes the tim
34. GND PRSNT1 12V 12V GND TCK TDI TDO TMS 43 3V 43 3V PERST REFCLK REFCLK GND PERnO 1x GND RSVD GND 1 PERn1 GND GND PERp2 PERn2 GND GND PERp3 PERn3 GND ax RSVD RSVD GND PERp4 PERn4 GND GND PERp5 PERn5 GND GND PERp6 6 GND GND PERp7 PERn7 GND PCI_EXPRESS X8 Figure 43 PCle Edge Connector 16 2 Stand Alone Operation An external ATX power supply is used to supply power to the DN7006K10PCIe 8T Logic Emulation Board in stand alone mode see Figure 45 The external power supply connects to Mini Fit PCI Express header J7 Molex P N 45558 0002 DN7006K10PCle 8T User Manual www dinigroup com PCIE PRSNTn TDIO PCIE P3 3V PCIE 5 PCIE REFCLKp PCIE PERpOr PCIE PERnOr PCIE PERptr 5 __ PCIE PERp2r 2 PCIE PCIE PERn3r PCIE PERp4r PERndr 5 PCIE PCIE PERp7r PCIE PERn7r 147 HARDWARE DESCRIPTION The user should connect the matching male power connector on the ATX power supply to this header 6 Pin PSU Adaptor for PCIe Video Cards supplied as part of this kit The DN7006K10PCIe 8T Logic Emulation Board has the following shared power supplies they are generated from the 12V supply on the external power connector J7 PSU1 P5 0V
35. PCIE OUT D09 24 B17 26 D6 PCIE OUT D10 24 A17 26 F9 PCIE OUT D11 24 A18 26 C6 PCIE OUT D12 24 A19 26 F6 PCIE OUT D13 24 B19 26 D5 PCIE OUT 114 24 C18 26 L13 PCIE OUT D15 24 B20 26 11 PCIE OUT D16 24 C19 26 C5 PCIE OUT D17 24 D19 26 E6 PCIE OUT D18 24 D21 26 G9 PCIE OUT D19 24 D20 26 U7 PCIE OUT D20 24 B21 26 15 PCIE OUT 021 24 C21 26 K13 PCIE OUT D22 24 B22 26 M13 c ec eG Emtec DN7006K10PCle 8T User Manual www dinigroup com 132 HARDWARE DESCRIPTION Signal Name Virtex 5 FPGA Pin FPGA A Pin PCIE OUT D23 24 A22 26 N14 PCIE OUT D24 24 A23 26 C4 PCIE OUT D25 24 B24 26 W8 PCIE OUT D26 24 C23 26 4 PCIE OUT D27 24 D24 26 H9 PCIE OUT D28 24 C24 26 A3 PCIE OUT D29 24 B25 26 W4 PCIE OUT D30 24 A25 26 B3 PCIE OUT D31 24 B26 26 A4 PCIE OUT D32 24 E26 26 U4 PCIE OUT D33 24 E25 26 B7 PCIE OUT D34 24 25 26 7 PCIE OUT 035 24 G26 26 12 PCIE OUT D36 24 H26 26 7 PCIE 037 24 G25 26 W9 PCIE_OUT_D38 24 24 26 W7 PCIE_OUT_D39 24 G24 26 C8 PCIE_OUT_D40 24 E23 26 R1 PCIE_OUT_D41 24 F23 26 R2 PCIE_OUT_D42 24 F22 26 W11 PCIE OUT D43 24 G22 26 W12 PCIE OUT D44 24 H22 26 Y10 PCIE OUT D45 24 H23 26 V1 PCIE OUT D46 24 J23 26 Y4 PCIE_OUT_D47 24 K21 26 W5 PCIE_OUT_D48 24 K22 26 K11 PCIE_OUT_D49 24 K23 26 L1 PCIE OUT D50 24 L23 26 1
36. 13 56 06 MainBus Write Dword 22 MainBus Read Dword MainBUs Memory Fill MainBus Memory Display PCI BAR Write Dword 6 PCI BAR Memory Display PCI BAR Memory Range Test set DDR2 config to test on FPGA set DDR2 config to test on FPGA test DDR2 on FPGA B test DDR2 on FPGA C full DDR2 memory test quick DDR2 test FPGA B quick DDR2 test FPGA C PCI BAR Read Dword Main Menu Q gt Quit PCI BASE ADDRESS 1 f 7666080 6888888 2 821121121519 4 30080888 5 T 2000000 Please select option PCI Test lt i gt RocketIO Test FPGA lt 2 gt LUDS Interconnect Test DIR ABC 3 1008 Interconnect Test DIR lt 4 gt Single Ended Interconnect Test Q gt Quit Enter Option Testing communication with QL5664 Testing communication with Conf igFPGA ERROR Write Read to BAR offset x300 wrote 2345 read Testing Complete FAIL press any Here is the board failing the PCIe test 3 3 Compiling AETEST 3 3 1 Compiling AETest for Windows XP AETest for Windows requires visual studio 6 or later to compile Open the provided make file and uncomment the lines ZDESTOS WIN Run nmake DN7006K10PCle 8T User Manual 22 PROGRAMMING CONFIGURING THE HARDWARE Chapter Programming Configuring the Hardware This chapter details the programming and configuration instructions for the DN7006K10PCIe 8T Logic Emulat
37. 15 determined by the daughter card designers part selection for the MEG Array receptacle DN7006K10PCle 8T User Manual www dinigroup com 178 HARDWARE DESCRIPTION Note that the components on the topside of the daughter card and DN7006KPClIe 8T face in opposite directions DN7006K10PCle 8T User Manual www dinigroup com 179 APPENDIX Chapter Appendix 19 Appendix A USF File See the Customer CD ROM for the QUARTUS Files 20 Ordering Information Request quotes by emailing sales dinigroup com For technical questions email support dinigroup com 21 Optional Equipment The following tools are suggested for use with the DN7006K10PCIe 8T Logic Emulation Board 21 1 Compatible Dini Group Products The Dini Group supplies standatd Daughter Cards and Memory modules that can be use with the DN7006K10PCIe 8T 21 1 1 Memories The Memory Module solutions from The Dini Group DNSODM200 SRAM Memory module for use in the 200 pin SODIMM sockets Standard memory configuration Two GS8320V32 memories 1M x 32 each Performance up to 175Mhz SDR Small EPROM Contact us about zero bus latency type parts DNSODM200 RLDRAM Reduced latency DRAM Micron 64 bit wide DN7006K10PCle 8T User Manual www dinigroup com 180 HARDWARE DESCRIPTION Compatible with the 200 pin SODIMM sockets Small EPROM DNSODM200 MICTOR DNSODM200 QUA
38. 17 0 16 8 os 0 L6N 17 DCDOPRX7 BO TXL7P 8 5 L7P DCDONTX7 018 8 818 DCDONRX7 BO TXL7N L7N 38 DCDOPTXS 80 a Lap 9 DCDOPRXB DCDONTX8 020 BOT 5 9 0 L8P B20 __DCDONRX8 TX LEN E RXL8N 75 ____ DCDOPDO 21 0 BO_TXLOP 5 o Es DCDONDO D22 z 2 9 RX LION amam DCDOPTXIO E7 b uw E13 DCDOPRX10 BO TXL10P 2 L10P Er DCDONTX10 F7 3 ri F13 DCDONRXIO TXL10N 5 L10N DCDOPTX11 Ed ewe 5 EH BO 111 5 M RX 111 a BO_RX_L11N_GCA PVIO DCDO a B0 VCCO pec Gis Section 2 of 6 2 2uF MEG Array 400 Stratix 3 6 3V 20 Figure 20 Secondary Daughter Card DC Header Clock 4 4 5 Connection between FPGAs and the Secondary DC Header Clocks The connection between the Stratix I FPGAs and the secondary DC header clocks ate shown in Table 12 Table 12 Connections between FPGAs and Secondary DC Header Clocks Signal Name FPGA Pin DC Header Pin Daughter Card D DCDOPRX11_GCA U25 AA4 P4 E1 DCDONRX11 GCA U25 AA3 P4 F1 DCD2PRX11 GCB U25 AB4 P4 E3 DCD2NRX11 GCB U25 AB3 P4 F3 Daughter Card E U36 AA4 p5 E1 DCEONRX11 GCA U36 AA3 P5 F1 DCE2PRX11_
39. 288000 Mhz 7 2303 124 7 35 14 318181 Mhz 3 2549 87 6 33 14 745599 Mhz 7 2303 124 7 29 16 384000 Mhz 4 383 14 6 29 16 934400 Mhz 5 14111 624 5 31 17 734475 Mhz 0 190485 3735 2 45 17 900000 Mhz 0 6085 119 4 33 H 18 432000 Mhz 7 2303 124 7 23 19 200000 Mhz 4 383 14 4 31 19 440000 Mhz 5 269 11 1 49 19 531250 Mhz 1 31249 767 1 49 H 19 660800 Mhz 4 15871 624 0 61 H 22 118400 Mhz 7 2303 124 7 19 24 576000 Mhz 7 2303 124 7 17 H 26 562500 Mhz 1 3909 95 0 45 32 768000 Mhz 4 383 14 1 29 33 330000 Mhz 7 605 31 1 29 H 38 880000 Mhz 1155 49 5 13 66 660000 Mhz 7 403 19 6 7 H 74 175824 Mhz 7 6749 363 7 5 76 800000 Mhz 4 383 14 4 7 71 760000 Mhz 5 575 24 4 7 98 304000 Mhz 4 383 14 1 9 DN7006K10PCle 8T User Manual www dinigroup com 76 HARDWARE DESCRIPTION 122 880000 Mhz 4 383 14 6 3 H 124 416000 Mhz 5 575 24 6 3 133 330000 Mhz 0 26665 479 6 3 H 155 520000 Mhz 5 575 24 4 3 156 256000 Mhz 4 9765 374 4 3 159 375000 Mhz 1 509 11 4 3 160 380000 Mhz T 485 24 4 3 161 130000 Mhz 0 10741 199 4 3 161 132800 Mhz 4 50353 1874 4 3 164 360000 Mhz 3 1173 39 1 5 166 630000 Mhz 0 33325 639 1 5 166 667000 Mhz 0 333333 6399 1 5 H 167 331600 Mhz 5 92961 3999 1 5 172 640000 Mhz 0 2157 39 1 5 173 370000 Mhz 3 11557 399 3 3 176 100000 Mhz 3 1175 39 3 3 176 840000 Mhz 3 8841 299 3 3 H 184 320000 Mhz 4 6
40. C A7 MICTOR MICTOR C A9 MICTOR A10 MICTOR A11 MICTOR A12 MICTOR C A13 MICTOR A14 MICTOR C A15 MICTOR MICTOR MICTOR B2 MICTOR B3 MICTOR 56 AU7 56 AT8 56 AW7 56 AV7 56 AW8 56 AU8 56 BB3 56 BB2 56 BB4 56 BA3 56 BA4 56 AY4 56 AU9 56 AT10 56 AW9 56 AV9 56 AR10 56 AP9 56 AT9 56 AR9 56 AK14 CICIO ere DN7006K10PCle 8T User Manual www dinigroup com 139 HARDWARE DESCRIPTION Signal Name FPGA Pin Mictor Pin MICTOR C B5 56 AL13 MICTOR C B6 56 AN13 MICTOR C B7 56 AM13 MICTOR C B8 56 AK15 MICTOR C B9 56 AL14 MICTOR C B10 56 AY5 MICTOR C B11 56 AW5 MICTOR C 12 56 AV6 MICTOR C B13 56 AUG MICTOR C B14 56 6 15 56 AW6 MICTOR_C_CLK_A 56 AU11 MICTOR C CLK B 56 AU10 13 Remote Slave SelectMAP Configuration In order to configure Dini Group Daughter Cards from the mother boatd a Slave SelectMAP configuration interface 8 bit configuration bus SELECTMAP D 15 0 is provided the Mictor header J42 In Slave SelectMAD is an output and must be supplied by the Configuration FPGA U20 13 1 1 Slave SelectMAP Mictor Header Figure 39 shows the pin assignments for the Slave SeleccMAP Mictor header J42 DN7
41. Card SIGNAL Receptacle Bottom FPGA DCD2PTX10 P4 E27 25 AD8 DCD2PTX11 P4 E39 25 AD14 DCD2PTX2 P4 C27 25 10 DCD2PTX3 25 7 DCD2PTX4 25 AF7 DCD2PTX5 25 AGG DCD2PTX6 25 AD10 DCD2PTX7 25 AE10 DCD2PTX8 25 AD12 DCD2PTX9 25 AB8 DCD3NRX0 25 AN3 DCD3NRX1 25 AP3 DCD3NRX10 25 AU2 DCD3NRX11 25 AY3 DCD3NRX2 25 1 DCD3NRX3 25 1 DCD3NRX4 25 1 DCD3NRX5 25 AV3 DCD3NRX6 25 AWA DCD3NRX7 25 AT3 DCD3NRX8 25 AU4 DCD3NRX9 25 AR3 DCD3NTX0 25 AJ12 DCD3NTX1 25 11 DCD3NTX10 25 6 DCD3NTX2 25 AJ10 DCD3NTX3 25 AK9 DCD3NTX4 25 AK12 DN7006K10PCle 8T User Manual www dinigroup com 159 HARDWARE DESCRIPTION Daughter Card SIGNAL Receptacle Bottom FPGA DCD3NTX5 P4 G34 25 AL6 DCD3NTX6 P4 G36 25 AN5 DCD3NTX7 P4 G38 25 5 DCD3NTX8 P4 G40 25 AL11 DCD3NTX9 P4 F31 25 AK7 DCD3PRXO 25 4 DCD3PRX1 25 AP4 DCD3PRX10 25 AU3 DCD3PRX11 25 AW3 DCD3PRX2 25 AP2 DCD3PRX3 25 1 DCD3PRX4 25 AU1 DCD3PRX5 P4 K33 25 AV4 DCD3PRX6 P4 K35 25 AW2 DCD3PRX7 25 AT4 DCD3PRX8 25 AU5 DCD3PRX9 25 AR4 DCD3PTX0 25 AJ13 DCD3PTX1 25 AH12 DCD3PTX10 25 AM7 DCD3PTX2 25 AK11 DCD3PTX3 25 AK10 DCD3PTX4 25 AK13 DCD3PTX5 25 AL7 DCD3PTX6 25 6 DCD3PTX7 25 AP6 DCD3PTX8 25 AL12 DCD3PTX9 25 AK8 DN7006K10PCle 8T User Manual www dinigroup com 160 HARDWARE DESCRIPTION EN ANTI SIGNAL Receptacle Bottom FPGA DCEONRX2 DCEONRX3 DCEONRX4 DCEONRX5 DCEONRX6 DCEONRX7 DCEONRX8 DCEONRX9 DCEONTXO DCEONTX1 DCEONTX10 DCE
42. Configuring the PCIe FPGA PROM using JTAG Cable Xilinx 222 7 7 5 Configuring the PCIe FPGA PROM using main txt 54 HARDWARE DESCRIPTION manec ineei reer e an E ER E ERE R EEE RS 55 1 OVERVIEW ALTERA STRATIX III FPGAS 2 1 S nimary Of Stratix IHT device features epi te ie pret e e a Er ER 58 3 STRATIX III FPGA CONFIGURATIO 59 3 1 Micro Controller Unit MCU 60 3 1 MCU EEPROM Interface 2 3 1 2 MCU SRAM 3 1 3 MCU Flashin nto tata bep RM er t le et ee E EA 3 1 4 MCU USB 2 0 Interface 3 9 15 5232 11 eie P ER te temm eumdem bien EE 3 2 Configuration ERE ERREUR vie riait 324 Configuration PROM FPGA Programming 2 322 Design Not s on the Configuration FPGA 3 3 Compact Flas m 3 3 1 CompactFlash Connector 3 3 2 CompactFlash connection to Spartan 3 Configuration FPGA 3 4 Stratix III Boundary Scan JTAG Interface 68 3 4 1 Sttatix IDEPGA Comme ctor inen OD enn neo p etra P GOD e eO 69 342 Stratix III FPGA connection to Configuration POA 69 3 5 Configuration MSEL Resistors 2 4 CLOCK GENERATIONS 4 1 Clock Methodology xi
43. DNI Sed TSM 136 01 T DV 0381 RS232 1 1 23 85232 voc 1 MCU 85232 2 ED RS232 CPUMP2 Ex 62 1 2 2 2 RS232 VPUMP 1 2 V x 2 us RS232 VPUMP 5 6 3 C384 C380 C378 10 SOP65P638X110 24N 0 10 0 tuF TSM 136 01 T DV P2 5VD R293 4 7K RS232 FPGA TX 8292 4 7K RS232 Figure 10 MCU Configuration FPGA Serial Port There are two signals attached to the MCU Transmit Data 5232 MCU TXD Receive Data 5232 MCU TXD and RXD provide bi directional transmission of transmit and receive data No hardware handshaking is supported 3 2 Configuration FPGA The Xilinx Spartan 3 XC381000 020 is needed to handle the counters and state machines associated with the high speed USB CompactFlash interface and the Quick Logic card FPGA contains 1M system gates 432K of BlockRAM and 391 user I O s Some of the Verilog soutce code for the Configuration ConfigFPGA v is proprietary The Configuration FPGA interfaces with the following signals Interface to the Micro Controller Data Bus MCU DYJO 7 DN7006K10PCle 8T User Manual www dinigroup com 63 HARDWARE DESCRIPTION Address Signals A 0 15 Control Signals RDn WRn MCU OEn MCU PSENn RESETn Si
44. EEPROM Connections e 19 Clocking Connections between Stratix III FPGAs and the DDR2 SDRAM SODIMMs e 20 Connections between the Stratix III FPGAs and the SODIMMs le 21 DDR2 PCB Trace Lengths e 22 Connections between Stratix III FPGA and the Serial Flash Devices ble 23 User LED s ble 24 FPGA DONE LED ble 25 Power Supply Status LED s ble 26 Power Supply Status LED s e 27 Miscellaneous LED s e 28 Connections between FPGAS and the RS232 Port e 29 Connection between Stratix III FPGAs and Temperature Sensors 30 Connection between Stratix III FPGAs and Ethernet PHYs de 31 PCIe e 32 Connection between Virtex 5 FPGA and Stratix III FPGA A 33 Connection between Stratix III FPGAs and 10 pin IO Headers e 34 Connections between FPGAs and Mictor Headers e 35 Slave SelectMAP Mictor connections to the FPGA e 36 Connection between Reset Buffers and FPGAs e 37 Daughter Card Reset i ble 38 FPGAto Daughter Header IO Connections sse oett tenete ne 1 ROM Directory Contents INTRODUCTION Chapter Introduction This User Manual accompames the DINZ006KTOPCIe S Logic Emulation Board For information regarding the
45. JMPR Note The GND pins of the VOUT ADJ trim resistors must be connected directly to 4 Y A 1 2 P2 5V A the converter GND pin with a trace The 32 jumper option may degrade performance p 7552 P TSM 103 01 T DV R442 R427 R450 R443 Adjust VOUT ADJ Trim Resistors 24 9K 21 5K lt 2 94K 5 23K OPEN DDR3 1 5V 3 5 DDR2 1 8V 4 DDR1 42 5V 1 3 SDR 3 0V Figure 27 VDD Switching Power Supply P SODIMM A 5 1 3 VTT Linear Power Supply 9 VTT x The National Semiconductor LP2996 linear regulator was designed to meet the SSTL 18 specifications for termination of DDR2 SDRAM SODIMMs The device contains a high speed operational amplifier to provide excellent response to load transients The output stage prevents shoot through while delivering 1 5A continuous current and transient peaks up to 3A see Figure 28 TP33 P SODIMM A P3 3VD P3 3VD 5 8 VIT A o 5 U79 P SODIMM 7 8 1 9 VIT A T 1 1 PVIN VIT 1 1 5 3 VITSNS A R481 oR C524 0530 C535 C546 C542 C550 VSENSE 330uF 47uF 2 2uF 47uF 2 2uF 2 2uF 8517 6 3 6 3V 6 3V 6 3V 6 3V 6 3V 1K 20 20 20 20 20 20 4 TANT CER GER VIT SDn A 2 P VREF SODIMM 1 9 C541 GND GND AL P2996
46. PSOP 8 6 3V LP2996MR 20 CER Figure 28 VTT Linear Power Supply P0 9V_VTT_A 5 1 4 Serial Presence Detect EEPROM Operation DDR2 SDRAM modules incorporate serial presence detect The SPD data is stored in a 256 byte EEPROM The first 128 bytes are programmed by Micron to identify the module type and various SDRAM organizations and timing parameters The remaining 128 bytes of storage are available for use by the customer System READ WRITE operations between the master system logic and the slave EEPROM device occur via a standard I2C bus using the DIMM s SCL clock and SDA data signals together with SA 1 0 which provide four unique DIMM EEPROM addresses Write protect WP is connected to VSS permanently disabling hardware write protect VDDSPD is connected to P SODIMM x to meet IO standards of the Stratix III FPGA IO Bank DN7006K10PCle 8T User Manual www dinigroup com 93 HARDWARE DESCRIPTION Table 18 Serial Presence Detect EEPROM Connections Signal Name FPGA DDR2 SODIMM SODIMM A J9 FPGA U26 J9 198 pull down with 4 7K DIMMA_SAO Not Connected R486 J9 200 pull down with 4 7K DIMMA SA1 Not Connected R487 DIMMA SCL U26 M20 U26 C21 9 197 pull up 4 7K R479 DIMMA_SDA U26 M19 U26 D21 J9 195 pull up 4 7K R478 SODIMM 40 FPGA 056 J40 198 pull down with 4 7K DIMMC_SAO Not Connected R1371 J40 200 pull down with 4 7K DIMMC 5 1 Not Connected R1370 DIMMC_SCL U56 AW21 U
47. Pro Synplicity Identify HW USB G http nuhorizons com Mictor Breakout MIC 38 BREAKOUT http www emulation com catalog off the shelf_solutions mictor DN7006K10PCle 8T User Manual www dinigroup com 183 HARDWARE DESCRIPTION 22 Compliance Data 22 1 Compliance 22 1 1 EMI Since the DN7006K10PCIE 8T is not intended for production systems it has not passed EMI testing Compliance is only done by special request 22 1 2 PCle SIG 22 2 Environmental 22 2 4 Temperature The DN7006K10PCle 8T is designed to operate within an ambient temperature range of 0 C to 55 22 3 Export Control 22 3 1 Lead Free The DN7006K10PCle 8T meets the requirements of EU Directive 2002 95 EC RoHS Specifically the DN7006K10PCIe 8T contains no homogeneous materials that a contains lead Pb in excess of 0 1 weight o 1000 ppm b contains mercury Hg in excess of 0 1 weight 1000 ppm contains hexavalent chromium Cr VI in excess of 0 1 weight 1000 ppm d contains polybrominated biphenyls PBB or polybrominated dimethyl ethers PBDE in excess of 0 1 weight 1000 ppm contains cadmium in excess of 0 01 weight 100 ppm No exemptions are claimed for this product 22 3 2 The USA Schedule B number based on the HTS 8471 60 7080 22 3 3 Export control classification number ECCN EAR99 DN7006K10PCle 8T User Manual www dinigroup com 184
48. RDO 23 uS 02 22 8200 3 Emo Roz 1 9 Tre 58 EMOTEN 2 2 eer Emor 20 02 TANG meo Heres H pa R E SR pg24 RXK C446 0 10 12 Mt DDO 30 44 ETHD REGEN 6446 244 ETHO CTE 6 CT PQSVD 25 a Dor baas 3 Emo o a 35 __ _ __ mans 8 25K ED 7 SD 052 0 ETHD MI SR WE 2 0K 1 BETTS Rate BEL 01810 UUCETHD TX 26 D CMODES 47 PLLMODE 14 PLLMODE ETAO WOT 15 5 ue x FILT emmo ner rur Tue ETH 5 00 9 5 Emms XEM 6 mer next SO RENE pod ETH QE T mst 2 0K 1 poowns m EHD RESET Ba RESET RATE x 886 cjus 7 Figure 33 Ethernet Circuit D 9 1 5 Connections between Stratix lll FPGAs and Ethernet
49. Ref sgn Meinbus Settings Info Production Tests Service Clear Log Scroll Log BOARD DN 7006k10PCIE8T USB to FPG communication is disabled Enable if you want to use reference design features 2 Click FPGA Configuration followed by Configure via USB individually and select the that needs to be configured this feature can also be invoked by right clicking on the selected FPGA FPGA Selection 3 Specify the file location for the FPGA programming file xxxx rb DN7006K10PCle 8T User Manual www dinigroup com 32 PROGRAMMING CONFIGURING THE HARDWARE Look in Documents 4 Computer My Recent amp JMy Network Places Documents Movies 4 File name My Network Files of type Raw Binary Files v Places Open as read only 5 Configuring an FPGA using JTAG This section lists detailed instructions for programming the Altera Stratix I FPGAs using Altera QUARTUS II Version 7 2 tools Before configuring the FPGAs ensure that the QUARTUS II software and the USB Blaster driver software are installed on the host computer Note This User Manual wil not be updated for every revision of the Altera 5 tools so please be aware of minor differences 5 1 Setup Before configuring the FPGA ensure the following steps have been completed 1 Attach an ATX Power Supply to the PCIe Power Header J7 on the DN
50. Strati lt I parts please reference the datasheet on the Altera website 1 DN7006K10PCle 8T LOGIC Emulation Kit The DN7006K10PCle 8T Stratix III Logic Emulation Board provides a hardware platform for developing and prototyping low power high performance logic intensive designs The board provides a wide range of peripherals and memory interfaces to facilitate the design and development of Stratix III designs The DN7006K10PCIe 8T can hosted in an 8 lane PCIe GEN1 system or operate in standalone mode using the USB CompactFLASH interface A single DN7006K10PCle 8T configured with 6 Altera Stratix UI FPGAs EP3SL340 can emulate up to 15 million gates of logic as measured by a reasonable ASIC gate counting standard and this number does not include embedded memories and multipliers resident in each FPGA One hundred percent 100 of the EP3SL340 s FPGA resources available to the user application The DN7006K10PCIe 8T achieves high gate density and allows for fast target clock frequencies by utilizing the largest FPGA from Altera s 5 family The DN7006K10PCle 8T is supplied with a full function fixed 8 lane PCIe mastet target Drivers and source for several operating systems included DN7006K10PCIE8T User Manual www dinigroup com 1 INTRODUCTION 2 DN7006K10PCle 8T Logic Emulation Board Features Figure 1 DN7006K10PCle 8T Logic Emulation Board DN7006K10PCIe 8T Stratix III Board features the follo
51. User Manual www dinigroup com 113 HARDWARE DESCRIPTION Signal Name FPGA Pin Serial Flash Pin FPGA C 56 Serial Flash U118 Flash CSN 56 8 118 4 Flash C RSTN 56 7 118 3 Flash C SCK 118 2 56 BB7 Flash_C_SI 118 1 56 Flash C SO 118 8 56 BB5 Flash WPN 118 5 56 FPGA D 025 Serial Flash 082 Flash D CSN U25 AW6 Flash_D_RSTN 25 AU6 Flash D SCK 25 AU7 Flash_D_SO 25 AW7 Flash_D_WPN 25 AY6 FPGA F 055 Serial Flash U121 Flash 55 4 Flash RSTN 55 N14 Flash 5 55 B3 Flash F SI 55 4 Flash F SO 55 A3 Flash WPN 55 U U Flash D SI U25 AT8 U U 6 LED Indicators The DN7006K10PCle 8T Logic Emulation board provides various LED S to indicate that status of the board The LED S are turned ON by driving GATE of the N MOSFET HIGH see Figure 30 P2 5VD Q55 150 LEDB A0 DS83 GREEN LED LEDB CO 3 2 8 BSS138 FPGA B LEDO Figure 30 LED Indicator DN7006K10PCle 8T User Manual www dinigroup com 114 HARDWARE DESCRIPTION 6 1 User LED s Numerous LED s Green are provided to the user as a design aid during debugging The LED s can be turned ON by driving the corresponding pin HIGH Table 23 describes the user LED S and their associated pin assignments on the Stratix III FPGAs Table 23 User LED s Signal Name FP
52. Utopia IV 10 Gigabit Ethernet XSLI Rapid I O and NPSI The only high density high performance FPGA with support for 256 bit AES volatile and non volatile security key to protect designs Robust on chip hot socketing and power sequencing support Integrated cyclical redundancy check CRC for configuration memory error detection with critical error determination for high availability systems support e Built in error correction coding ECC circuitry to detect and correct configuration or user memory error due to SEU events Nios H embedded processor support Support for multiple intellectual property megafunctions from Altera MegaCore functions and Altera Megafunction Partners Program AMPP 3 Stratix ll FPGA Configuration The Dini Group developed the CompactFlash Configuration Environment to address the need for a space efficient pre engineered high density configuration solution for systems with single or multiple FPGAs The technology is a groundbreaking in system programmable configuration solution that provides substantial savings in development effort and cost per bit over traditional PROM and embedded solutions for high capacity FPGA systems Stratix III devices are configured by loading application specific configuration data the bitstream into internal memory On the DN7006K10PCIe 8T this can be accomplished via the CompactFlash PCIe or USB interface using Fast Passive parallel FPP configuration option Because A
53. and add the line service mode 1 Save and close the file 3 Launch USBController select Service menu and ProgramV5TProm DN7006K10PCle 8T User Manual www dinigroup com 49 PROGRAMMING CONFIGURING THE HARDWARE 4 Open file Dialog will appear Specify the file location for the PROM programming CUST_CD DN7006K10PCIE8T FPGA_Reference_Designs Programmin g Files pcie_fpga pcie_dma LX50T and open the PROM fie v5t hex 2 5 The process takes about 10 15 minutes please leave the board and USBController alone The process bar is on the bottom of USBController window 6 When the execution is finished power cycle the board and verify that the CFG DONE blue LED 0544 15 enabled indicating successful configuration of the 7 7 3 Configuring the PCle FPGA using JTAG cable Xilinx This section lists detailed instructions for programming the Xilinx Virtex 5 PCle FPGA using the Xilinx ISE Version 9 2 0 tools Power the DN7006K10PClIe 8T Logic Emulation Board and verify that the Power LED 0525 is ON Note This User Manual will not be updated for every revision of the Xilinx tools so please be aware of minor differences 1 Connect the Xilinx Platform Cable USB to the JTAG V5T header J1 on the DN7006K10PCIe 8T Logic Emulation Board 2 Open iMPACT and create new default project Select Configure devices using Boundary Scan JTAG from the iMPACT welcome menu DN700
54. as differential 50 Ohm transmission lines length matching is done on the PCB for daughter card signals except within a differential pair because the Stratix III is capable of variable delay input using the built in deskewing circuitry Other connections on the daughter card connector system include three dedicated differential clock connections for inputting global clocks from an external source power connections bank power and a reset signal 17 1 Daughter Card clocking Refer to pat 4 4 Daughter Card DC Header Clocks in this User Manual 17 2 Daughter Card Header Pin Assignments The pin assignments of the DN7006K10PCle 8T daughter card headers were designed to reduce cross talk to manageable levels while operating at full speed of the Stratix III LVDS standards daughter card header is divided into four banks refer to Figure 46 The Stratix HI devices support source synchronous interfacing with LVDS signaling at up to 1 25Gbps The ground to signal ratio of the connector is 1 1 refer to Figure 46 General purpose IO 15 arranged in a GSGS pattern to allow high speed single ended or differential use These signals ate routed as loosely coupled differential signals meaning when used differentially they benefit from the noise resistant properties of a differential pair but when used in a single ended configuration they do not interfere with each other excessively DN7006K10PCle 8T User Manual www dinigroup com 1
55. dinigroup com Data byte group 112 HARDWARE DESCRIPTION Signal Name Routed Length mm Description DIMMD_CKON 70 14 Clock group DIMMD_AO 70 91 Control group DIMMD DQO 70 06 Data byte group DIMMF 70 05 Clock group DIMMF A0 70 91 Control group DIMMF DQO 70 16 Data byte group 5 2 Serial Flash The Atmel AT45DB161D provides 16Mbit 4096 pages of 512 528 bytes page of Serial Flash Memory The Flash memory is connected to the Stratix III FPGAs B C D and an SPI interface see Figure 29 The Flash does not require high input voltages for programming allowing for simple in system re programmability FLASH B SI r BN R938 33R FLASH_B_CSn FLASH_B_WPn FLASH_B_RSTn 1 2 4 5 3 7 AT45DB161D SO8 2 2uF AT45DB161D SU 2 5 6 3V Figure 29 Serial Flash 5 2 1 Connections between FPGAs and Serial Flash The Serial Flash is connected to a 2 5V IO Bank on the FPGA The connections between the Stratix III FPGA and the Serial Flash devices are shown in Table 22 Table 22 Connections between Stratix III FPGA and the Serial Flash Devices Signal Name FPGA Pin Serial Flash Pin FPGA 037 Serial Flash 099 Flash CSN U37 V12 99 4 Flash B RSTN U37 P3 99 5 Flash B 5 U37 V13 99 2 Flash B SI U37 P1 99 1 Flash B SO U37 N1 99 8 Flash U37 P4 99 5 DN7006K10PCle 8T
56. do O Install the software automatically Recommended Click Next to continue e Select Don t search I will choose the driver to install and click Next to continue DN7006K10PCle 8T User Manual www dinigroup com 9 GETTING STARTED Found New Hardware Wizard Please choose your search and installation options Search for the best driver in these locations Use the check boxes below to limit or expand the default search which includes local paths and removable media The best driver found will be installed Search removable media floppy CD ROM Include this location in the search C alteraN7 2NquartusNdriversSusb blasterx32 Choose this option to select the device driver from list Windows does not guarantee that the driver you choose will be the best match for your hardware Select Have Disk and direct the browse window to location USB_Software_Applications driver windows_wdm on the CD ROM Install From Disk Insert the manufacturer s installation disk and then make sure that the correct drive is selected below Copy manufacturer s files from JUSB Software Applications driver windows wd new window will display the list of compatible hardware click to continue DN7006K10PCle 8T User Manual www dinigroup com 10 GETTING STARTED Found New Hardware Wizard Select the device driver you want to install for this
57. hardware Select the manufacturer and model of your hardware device and then click Next If you have a disk that contains the driver you want to install click Have Disk Show compatible hardware DiniGroup USB Hosted Board This driver is not digitally signed Tell me why driver signing is important Found New Hardware Wizard Please wait while the wizard installs the software A DiniGroup USB Hosted Board gt Setting a system restore point and backing up old files in case your system needs to be restored in the future e After successful installation of the driver the following window will be displayed DN7006K10PCle 8T User Manual www dinigroup com 11 GETTING STARTED Found New Hardware Wizard Completing the Found New Hardware Wizard The wizard has finished installing the software for 29 DiniGroup USB Hosted Board Click Finish to close the wizard 3 BoardSetup The instructions in this section explain how to install the DN7006K10PClIe 8T Logic Emulation Board For the purpose of this demonstration the DN7006K10PClIe 8T will be configured in Stand Alone mode 3 1 Before Powering Up the Board Before powering up the board prepare the board as follows 1 Attach an ATX Power Supply to the PCIe Power Header J7 on the DN7006K10PCIe 8T Logic Emulation Board using the PCIe Graphics Power adaptor cable 2 Connect the USB Cable from the host computer to the USB C
58. in the log window DiNi Products USB Controlli Edit FPGA Configuration FP Des ius Settings Info Production Tests Service Refresh Enable USB gt FPGA Com Clear Log Scroll BOARD TYPE DN7006k10PCIE8T USB to FPGA communication is disabled Enable if you want to use reference design features DN7006K10PCle 8T User Manual www dinigroup com 48 PROGRAMMING CONFIGURING THE HARDWARE 5 Click FPGA Configuration followed by Configure via USB individually and select the that needs to be configured this feature can also be invoked by right clicking on the selected FPGA FPGA Selection 6 Specify the file location for the FPGA bitfile CUST_CD DN7006K10PCIE8T FPGA_Reference_Designs Programmin g Files pcie_fpga pcie_dma LX50T and open pcie_v5t bit Look in 15501 am _ 5 large bit My Recent Documents Desktop File name 5t bit E My Network Files of type Bit Files bit Cancel Open read only 7 7 2 Configuring the PCle FPGA PROM using USBController This section lists detailed instructions for programming the Xilinx Virtex 5 PROM using the USBController software Power DN7006K10PCle 8T Logic Emulation Board and verify that the Power LED DS25 is ON 1 Connect the USB Cable to the USB header J3 on the DN7006K10PCIe 8T Logic Emulation Board 2 Open USBController in
59. link in 1x 4x or 8x mode respectively DN7006K10PCle 8T User Manual www dinigroup com 20 INTRODUCTION TO THE SOFTWARE TOOLS ASIC Emulator PCI Controller Driver 99 Compiled Sep 18 2006 at 13 55 44 P gt PCI Menu M gt Memory Menu FPGAs stuffed A 1 gt Interconnect test 2 gt Read clock frequencies 4 MGT Menu 7 gt Production Tests Menu 9 Quit PCI BASE ADDRESS f 7000000 1 f 6666080 2 5 5000000 f 4666080 T 20000090 T 2000000 Please select option m This is the PCI menu It can help you debug a software problem detecting or communicating with the board ASIC Emulator PCI Controller Driver v9 Compiled Sep 18 2006 at 13 55 44 Display Vendor and Device ID Display all PCI information Write config dword Read config dword Display Config Registers x xFC Configure BAR s amp command reg from File Save BAR amp command reg configuration to File Load BAR from WDM driver s info Cas shown below Main Menu Quit PCI BASE ADDRESS 7668060 1 f 6666060 2 f 4666080 T 30009000 5 3 f58808088 2000000 Please select option This is the memory menu From here you can communicate with the User design in any of the FPGAs using Main Bus or directly to FPGA A DN7006K10PCle 8T User Manual 21 INTRODUCTION TO THE SOFTWARE TOOLS ASIC Emulator PCI Controller Driver 99 Compiled on Sep 18 2006 at
60. power cable is required for operation The only voltage that is required for operation is 12V All other voltages used on the board are regulated from this source Figure 45 indicates the connections to the PCIe power connector J7 This header is fully polarized to prevent reverse connection and is rated for 600V AC at 7A per contact A reverse polatity protection is provided by diode D1 45558 0002 D1 45558 0002 MBRB4030T4G Note Reverse polarity protection TP24 Silkscreen 12 O cub CER Figure 36 PCIe Power Connection Note Header J7 is not hot plug able Do not attach power while power supply is ON 10 1 5 Connection between Virtex 5 FPGA and Stratix lll FPGA The connection between the PCIe Virtex 5 FPGA and the Stratix III FPGA shown in Table 32 Table 32 Connection between Virtex 5 FPGA and Stratix III FPGA A Signal Name Virtex 5 FPGA Pin FPGA A Pin PCIE ALL VALID 24 24 26 17 PCIE IN ALMOST FULL 24 122 26 F3 PCIE IN 24 11 26 3 PCIE CC1 24 AC21 26 13 PCIE IN CC2 24 W23 26 U1 PCIE IN CHANO 24 R25 26 L7 PCIE IN 24 P24 26 8 DN7006K10PCle 8T User Manual www dinigroup com 128 HARDWARE DESCRIPTION Signal Name Virtex 5 FPGA Pin FPGA A Pin PCIE IN CHAN2 24 P23 26 G4 IN LOCK 24 AA23 26 L3 PCIE IN D00 24 AF12 26 7 PCIE IN D0
61. s DDR2 SDRAM memory output impedance is not larger than 21Q This is in keeping with SSTL 18 JEDEC specification JESD79 2 which combined with an on DIMM series resistor matches that of the transmission line resulting in optimal signal transmission to the receiver FPGA On the receiver FPGA side it is properly terminated with 500 which matches the impedance of the transmission line thus eliminating any ringing or reflection DN7006K10PCle 8T User Manual www dinigroup com 91 HARDWARE DESCRIPTION FPGA DDR2 DIMM DDR2 Component me Driver 1000 1 Rg 220 Receiver 1 509 Vggr 09 1000 Figure 26 Read Operation from DDR2 SDRAM Memory Using the Parallel OCT Feature of the Stratix HI Finally the loading seen by the FPGA during writes to the memory is different between a system using dual inline memory modules DIMMs versus a system using components The additional loading from the DIMM connector can reduce the edge rates of the signals arriving at the memory thus affecting available timing margin The DDR2 SDRAM SODIMM interface has bi directional and uni directional signals and the termination scheme is different for both types of signals see Table 17 Reference the JESD8 15a standard Stub Series Terminated Logic for 1 817 SSTL_18 for more information regarding output specifications Table 17 DDR2 Termination Signal Drivers at
62. to 100 MHz in the GUI log window 7 Updating the Firmware 7 1 Introduction The Dini Group may release periodic software updates as a result of bug fixes or added features The following parts of the design may be updated recommended update sequence Configuration FPGA Spartan PROM used to configure the Spartan FPGA MCU EEPROM used to load boot code into the MCU MCU Flash used to store MCU firmware code PCIe FPGA and SPI Serial Flash used to configure PCle FPGA DN7006K10PCle 8T User Manual www dinigroup com 38 PROGRAMMING CONFIGURING THE HARDWARE Please contact The Dini Group at support dinigroup com for software updates It is recommended to update all the devices for a given release of firmware since the software is not tested for backwards compatibility 7 2 MCU Startup Modes The DN7006K10PCle 8T Logic Emulation Board can load its code from two different locations MCU EEPROM Update Mode MCU Flash default mode In order to force the board to run startup code from EEPROM only hold down the LOG switch 52 during POWER ON ensure MCU LEDs turn ON DS19 DS20 DS21 and DS23 to ensure the board is in Update Mode If the board is connected to the serial port P2 the following message will be displayed MCU Flash be updated now 7 3 Updating the USBController The USBController software is available from The Dini Group website under do
63. 00 modules The interface is connected to IO Banks on the 5 FPGAs and uses 1 8V switching power supply fot and Vrr and ate powered from a separate linear power supply set at 0 9V DDR2 SDRAM modules ate available from Micron example part number for a 512MB 64Meg x 64 200 pin SODIMM SDRAM module is MT4GTF6464HY 53E Altera published a DDR2 application note please refer to 435 Design Guidelines for Implementing DDR and DDR2 SDRAM Interfaces in Stratix Devices 5 1 1 DDR2 Termination devices support both series and parallel on chip termination OCT resistors to improve signal integrity Another benefit of the Stratix III OCT resistors is eliminating the need for external termination resistors on the FPGA side This feature simplifies board design and reduces overall board cost It is possible to dynamically switch between the series and parallel OCT resistor depending on whether the Stratix III devices are performing write or a read operation The OCT features offer user mode calibration to compensate for any variation in voltage and temperature during DN7006K10PCle 8T User Manual www dinigroup com 90 HARDWARE DESCRIPTION normal operation to ensure that the OCT values remain constant The parallel and seties OCT features on the Stratix III devices are available in either 250 or 500 setting Refer to the Features chapter of the Stratix Device Handbook for inform
64. 006K10PCle 8T User Manual www dinigroup com 140 HARDWARE DESCRIPTION FPGA15_CS 1 MICTOR CLK E 5 148 1 CLK CLK 6 L8 FPGARD WRS 015 8 10 M DONE 10 12 FPGA 12 14 14 16 ____ 5 16 18 ____ 18 20 MB16 20 722 MB32 SELECTMAP D7 22 MB31 SELECTMAP 06 24 26 MB30 05 26 58 ___ 29 04 28 30 MB28 03 30 722 MB27 02 32 34 _ MB26 SELECTMAP 01 5 36 25 SELECTMAP DO 38 38 MB24 44 42 I 2 767004 2 767004 38B Figure 39 Slave SelectMAP Mictor Header 13 1 2 Slave SelectMAP Mictor connections to the FPGA Table 35 shows the connection between the Slave Select MAP Mictor header and Stratix III FPGA Table 35 Slave SelectMAP Mictor connections to the FPGA Signal Name Mictor Pin Configuration FPGA Pin CLK_48_MIC J42 6 20 J2 MICTOR_CLK_E 142 5 20 12 M CCLK j42 12 20 R2 FPGA M DONE 142 10 20 13 M 42 14 20 1 FPGA_RD WR j42 8 20 G20 FPGA14_CS 142 4 20 5 FPGA15_CS 42 2 20 84 MB16 142 21 20 W3 MB17 142 19 20 T2 18 742 17 20 4 19 42 15 20 W1 20 342 13 20 36 DN7006K10PCle 8T User Manual ww
65. 1 24 AE12 26 R10 PCIE IN 002 24 V8 26 T11 PCIE IN D03 24 V9 26 M1 PCIE IN D04 24 AF7 26 M5 PCIE IN D05 24 AD11 26 R8 PCIE IN D06 24 W9 26 N6 PCIE IN D07 24 W8 26 T10 PCIE IN D08 24 AD10 26 17 PCIE IN D09 24 Y7 26 P6 PCIE IN D10 24 8 26 N5 IN D11 24 AF9 26 U13 PCIE IN D12 24 AF10 26 N4 PCIE IN D13 24 7 26 N8 PCIE IN D14 24 8 26 14 PCIE IN 1015 24 AF8 26 P7 PCIE IN D16 24 U21 26 8 PCIE IN D17 24 V22 26 P9 PCIE IN D18 24 6 26 13 PCIE IN 019 24 AB7 26 U10 PCIE IN D20 24 AE8 26 18 PCIE IN 1021 24 AE7 26 M4 PCIE IN D22 24 AE6 26 V11 PCIE IN D23 24 5 26 1 PCIE IN 024 24 AE5 26 P1 PCIE IN D25 24 V21 26 L6 PCIE IN D26 DN7006K10PCle 8T User Manual cic ae eae GIE G 24 W21 oem Gh Ge eL e Er 26 D1 www dinigroup com 129 HARDWARE DESCRIPTION Signal Name Virtex 5 FPGA Pin FPGA A Pin PCIE IN D27 24 AD6 26 V12 PCIE IN D28 24 7 26 9 PCIE IN D29 24 AC8 26 PCIE IN D30 24 AD8 26 R5 PCIE IN D31 24 AD9 26 R4 PCIE IN D32 24 AC26 26 K1 PCIE
66. 1 Please enter filename 5 When the execution is finished power cycle the board Note Using the command line aeusb_wdm_cmd exe EEPROM lt filename tic gt 7 6 Updating the MCU Flash To protect against accidental erasure the MCU Flash firmware cannot be updated unless the board is put in Update Mode during POWER ON see par 7 2 You can either use USBController or AEtest_USB program to update MCU Flash firmware 7 6 4 Using USBController 1 Putthe board into Firmware Mode instruction 4 1 2 Run USBController exe Flash Update dialog will appear please select Yes DN7006K10PCle 8T User Manual www dinigroup com 45 PROGRAMMING CONFIGURING THE HARDWARE 3 Please select firmware hex we provide you this file 4 When finish please recycle power the board hit Hard Reset 53 on the boatd to boot from User Mode 7 6 2 Using AETest USB 1 Hold down switch S2 during POWER ON ensure the MCU LEDs turn 15519 DS20 0521 and 0523 to ensure the board is in Update Mode 2 Run aeusb_wdm exe aeusb linux from file location CUST CD NUSB Software Applications aetest usb and press any key to continue ASIC Emulator USB Controller Driver v61 Compiled Jun 24 2668 12 49 38 USB Menu MainBus Menu Firmware Menu Cbooted from eeprom gt Change Current Device Read Board Temperatures Read Clock Frequencies Read Clock Frequencie
67. 1 2 Conn ction between Reset and EPGAS RS E Ide E PESE POETS 145 16 POWER DISTRIBUTION 146 16 1 In System Operation 16 2 Stand Alone Operation npn ep RD UO DERIT ERE IER EGITTO EUER REG 147 16 2 1 External Power Cond ector e EO ERE RC EO OE ORE e OR ER ette 149 17 DAUGHTER CARD HEADERS 150 17 1 Daughter Card clocking 150 17 2 Daughter Card Header Pin Assignments 150 17 3 Special Pins on the Daughter Header 5 5 eiii scende miele a i E reti HERE e EROR 152 1731 GCAp n and EOD RD ORE SRI PEE et 152 17 3 2 Power Supply i nein POS E D GRO FIR PE RR ERE CERERI ES UTE EHE E c 152 17 3 3 17 4 17 5 17 6 17 7 18 18 1 18 2 18 3 19 20 21 21 1 21 1 1 21 1 2 21 1 3 21 2 22 22 1 22 1 1 22 1 2 22 2 22 2 1 22 3 22 3 1 22 32 22 3 3 Vocem Power E MM EEUU 152 Power and Reset FPGA to Daughter Card Header IO Connections 153 Insertion Removal of Daughter Card 174 MEG Array Specifications MECHANICAL Board HU 177 Standard Daughter Card Size RO EEA ANET A 178 Daughter Spacing
68. 2 135 2 55 22 35 4 55 622 35 6 55 15 35 8 109 FPGA 1010 FPGA 1011 1012 1013 1014 1015 Gy oa eG C IG 12 Mictor Headers The DN7006K10PCle 8T Logic Emulation Board provides two 38 pin Mictor Headers J19 J37 on FPGA B C to allow debug trace access however SignalTap is recommended as an on chip FPGA Logic Analyzer SignalTap inserts a logic analyzer bus analyzer and Virtual I O low profile software cores directly into the design allowing the user to view any internal signal or node including embedded hard or soft processors Signals are captured at or near operating system speed and brought out through the programming interface freeing up pins for the design Captured signals can then be analyzed through the included SignalTap Logic Analyzer DN7006K10PCle 8T User Manual www dinigroup com 137 HARDWARE DESCRIPTION 12 1 1 Mictor Header Circuit The Mictor header J37 is pinned out as shown in Figure 38 All the signals are routed matched length to 50mils J87 1 2 MICTOR LK A GND MICTOR LK B gt EVEN CLK ODD CLK 8 Y On MICTOR EB EVEN 000 19 10 814 13 E E MICTOR H EVEN 13 ODD 13 E VICTOR CE WCTOR C 15 EVEN 12 ODD 12 Fag MICTOR CE
69. 2 4 Configuration PROM FPGA Programming The Configuration FPGA U20 is programmed using Master Serial Mode with a Platform Flash PROM 074 In Master Serial mode the Spartan 3 FPGA configures itself The JTAG chain from the PROM is in a serial daisy chain with the Configuration FPGA allowing simultaneous JTAG programming option of both devices The Configuration FPGA is set to Master Serial Mode using discrete resistors R457 R473 and R459 At power up the Configuration FPGA provides configuration clock CFPGA_CCLK that drives the PROM A short access time after CEn CFPGA_DONE and OE CFPGA_INIT are enabled data is available on the PROM data 100 pin that is connected to the Configuration FPGA The programming header J2 as shown in Figure 11 is used to download the files to the Configuration PROM FPGA via a Xilinx Parallel IV cable R334 1K PROM_TMS PROM Figure 11 Configuration PROM FPGA Programming Header 3 2 2 Design Notes on the Configuration FPGA Oscillator X2 is a 24 MHz oscillator used to clock the Configuration FPGA and MCU This part is soldered down to the PWB and is not intended to be user configurable The clock signal is labeled 5 on the schematic The 24 MHz is used directly for the state machines in the Configuration FPGA for controlling the interface to the CompactFlash card The maximum DCLK clock frequency for Fast Passive Parallel FPP configuration is 100 MH
70. 2 F LN 50 36 55 42 G2 LP 50 37 55 41 CLK G2 F RN 50 34 55 1 CLK G2 F RP 50 35 55 AB2 CLK G2 50 60 24 F19 CLK G2 QP 50 61 24 E18 CLK G2 QSEN 50 30 143 112 G2 QSEP 50 31 143 114 CLK G2 TN 50 62 TP84 2 CLK G2 TP 50 63 TP84 1 GIP Clock Multiplier CLK GTP CLK GTP 114N U32 29 CLK GTP 114 U32 28 DN7006K10PCle 8T User Manual www dinigroup com 80 HARDWARE DESCRIPTION Signal Name Clock Multiplier Pin FPGA Pin GTP ON U32 34 U24 AB17 CLK_GTP_QP U32 35 U24 AC18 4 4 Daughter Card DC Header Clocks There are three daughter card headers on the DN7006K10PClIe 8T Logic Emulation Board The 400 pin MEG Array connectors on the bottom of the PCBA is used to interface to the Dini Group products e g DNMEG_AD DA Each of the daughter cards headers provides a LVDS clock that is buffered and distributed to the 5 FPGAs In addition two secondary clocks are provided on the daughter card header and connect to clock inputs on the FPGA bank 441 EXT SMA amp DCD Global Clocks 030 Two SMA s J14 J15 are provided to allow for an external differential clock CLK_USERp n input to the FPGAs via a Zero Delay C
71. 26 HARDWARE DESCRIPTION 10 1 1 Block Diagram The basic dataflow is indicated in the block diagram below see Figure 34 more information regarding the operation of the PCle interface reference PCIEST Dinigroup Board Family Full Design User Interface Manual available the Dini Group website FPGA D FPGA FPGA F EP3SL340 EP3SL340 EP3SL340 Configuration FPGA XC3S1000 MB 35 00 FPGAA FPGA B FPGAC EP3SL340 EP3SL340 EP3SL340 x64 x64 PCle Endpoint XC5VLX50T 2 5Gb s he PCle x8 Figure 34 PCIe Bus Diagram 10 1 2 Clocking See par 4 5 PCIe Reference Clocks for more information 10 1 3 Configuration The Virtex 5 FPGA U24 is programmed during startup using SPI Serial Flash U22 see Figure 35 The ISP Serial Flash is programmed JTAG J1 using the Xilinx IMPACT tool P3 3VD R536 DNI 4 7K FPGAQ MOSI FPGAQ CCLK SI SPIL RESEM 3 FPGAQ_FCSn 4 SO FPGAQ WP E WP GND FPGAQ DIN AT45DB642D 50 127 800 610 100 8 Figure 35 Virtex 5 SPI Serial Flash DN7006K10PCle 8T User Manual www dinigroup com 127 HARDWARE DESCRIPTION 10 1 4 PCle Power Connector The DN7006K10PCle 8T digital circuitry exceeds the maximum allowed power requirements for a PCle card 35W As a result an external
72. 3 DN7006K10PCle 8T User Manual www dinigroup com 105 ct pc psc D 0015 25 AW15 c HARDWARE DESCRIPTION D DQ36 DIMMD DQ37 D D D D D D D D DIMMD 1038 IMM IMM IMM IMM IMM IMM IMM IMM IMM IMM IMMD DQ39 IMM IMM IMM IMM IMM IMM IMM IMM IMM IMM DIMMD 1035 DN7006K10PCle 8T User Manual ex er De C3 25 AU14 25 AR15 25 BB16 25 BB17 25 AU16 25 AT17 25 BB15 25 BA16 25 AT15 25 AW16 25 AU17 25 AP20 25 AT19 25 BB20 25 AT20 25 AN20 25 AR19 25 BA19 25 BB19 25 BA10 25 AV19 25 AP18 25 AN19 25 AM19 25 AW18 25 AW19 25 AN18 25 AM18 25 AM25 www dinigroup com SODIMM Pin 18 56 18 58 18 61 18 63 18 73 1 L 8 124 8 126 8 134 8 136 J J 106 HARDWARE DESCRIPTION D EET 25 AN17 25 23 CT Ge oem oe DIMMD 0060 D 25 AU23 DIMMD DQ62 25 BA24 DN7006K10PCle 8T User Manual www dinigroup com 107 D D D D D D D D D D 25 12 25 12 25 AV12 25 AU12 25 BA15 25 AY15 25 BA18 D DQ6 c MM MM MM MM MM MM MM MM MM MM MM MM MM MM MM MM MM MM MM MM MM MM MM HARDWARE DESCRIPTION Signa
73. 3 PCIE OUT 051 24 L22 26 U6 ct epe ce cp enge 14224142 e EG Eee pete EG e He eG GS DN7006K10PCle 8T User Manual www dinigroup com 133 HARDWARE DESCRIPTION Signal Name Virtex 5 FPGA Pin FPGA A Pin PCIE OUT D52 24 M21 26 V4 PCIE OUT D53 24 N21 26 V5 PCIE OUT D54 24 25 26 12 PCIE OUT D55 24 26 26 T4 PCIE OUT D56 24 K26 26 K12 PCIE OUT D57 24 L24 26 Y12 PCIE OUT D58 24 K25 26 T6 PCIE OUT 1059 24 N26 26 AA12 PCIE OUT D60 24 M26 26 V3 PCIE OUT D61 24 M25 26 V2 PCIE OUT 1062 24 24 26 11 PCIE OUT D63 24 N24 26 W3 PCIE OUT EOF 24 D26 26 G8 PCIE OUT EXTRAO 24 R23 26 L12 PCIE OUT EXTRA1 24 R22 26 M12 PCIE OUT EXTRA2 24 U26 26 T1 PCIE OUT EXTRA3 24 U25 26 W6 PCIE_OUT_EXTRA4 24 N23 26 V9 PCIE_OUT_EXTRA5 24 N22 26 V10 PCIE_OUT_EXTRAG 24 M22 26 V8 PCIE OUT INFOO 24 125 26 B6 PCIE OUT INFO1 24 124 26 A5 PCIE OUT PRESENT 24 H21 26 T12 PCIE OUT SOF 24 C26 26 A2 PCIE OUT 24 D25 26 J10 PCIE OUT 24 123 26 G10 PCIE OUT VALID 24 AB25 26 G11 PCIE AN 24 F14 26 AA3 PCLK 24 F15 26 4 ct boe eue eom IE
74. 35 6 1 Ag nM 35 6 2 Configuring the Clock Multipliers using USBController eese esent tete tenente tete tete tnter tenete entree enne 36 6 3 Selecting a Clock Source using USBController 7 UPDATING THE 38 7 1 Introduction 38 Tiso MCU StartUp Modes 39 7 3 Updating the USBController 7 4 Updating the Configuration Firmware 7 41 Usm USBControllets REO UR OR NES 7 4 2 G Cables iii oven e CREER RC TORO RUBIO E ORO 7 4 3 Using AEtest USB x 7 Updating MCU oo eee RE e 7 5 1 Using USBGonttollet EE IND PORE 7 5 2 Using AETest USB 7 6 Updating the MCU Flash 7 6 1 Using USBController 7 62 Using AETest US Bees Acren CEPGAQQ and SPI Serial Flashers secu cett ERES E BERE NEXU INASRE 7 7 1 Configuring the PCIe FPGA using USBController 5 7572 Configuring the PCI FPGA PROM using USBController terreri tet eee eerie ena Ree e 49 1 53 Configuring the PCIe FPGA using JTAG cable 50 7 1 4
75. 42 U U CF_IOWR 20 P22 J5 35 CF_PDIAG 20 22 15 46 CF POWER 20 N17 R37 1 CF_RESET 20 P21 15 41 20 21 15 36 CFAO U20 N20 5 20 CFA1 U20 N19 5 19 CFA2 U20 N22 15 18 U U 3 4 Stratix Ill Boundary Scan JTAG Interface In boundary scan mode dedicated pins used for configuring the Stratix III devices The configuration is done entirely through the IEEE 1149 1 Access Port The FPGA JTAG interfaces to IO on the Configuration FPGA This allows DN7006K10PCle 8T User Manual www dinigroup com 68 HARDWARE DESCRIPTION manipulation of the data as required by the application and allows the JTAG chain to become an address on the existing bus The processor can then read from or write to the address representing the JTAG chain FPGAs that are not populated requires feed through resistor to maintain the daisy chain connection between FPGAs 3 4 1 Stratix lll FPGA JTAG Connector Figure 13 shows 10 the JTAG connector used to download the configuration files to the FPGAs P2 5VD P2 5VD P2 5VD P2 5VD R488 10K JTAG FPGA TCK JTAG FPGA TDO Figure 13 JTAG Connector 3 4 2 Stratix lll FPGA JTAG connection to Configuration FPGA Table 7 shows the connection between the Stratix III FPGA JTAG connector and the Configuration FPGA Table 7 Stratix III FPGA JTAG con
76. 5 nFB IN R818 100R 1CS8745B LQF P32 1CS8745BYLF Figure 18 External Daughter Card D Global Clock Input Circuit 4 4 2 DCE amp DCF Global Clocks U45 second Zero Delay Clock Buffer 045 captures the clock from Daughter Cards D amp E which in turn is buffered by and LVDS Buffer U46 before it s distributed as a global clock to the Stratix III FPGAs see Figure 19 DN7006K10PCle 8T User Manual www dinigroup com 81 HARDWARE DESCRIPTION pg34 CLK DCFp pg34 DCFn CLK pg32 CLK DCEp 2 DCEn pg5 SYNTH EXT CLKSEL 5 SYNTH 50 pg5 SYNTH 51 SYNTH S23 pg5 SYNTH PLLSEL pg5 SYNTH EXT MR EXT FBp En Ey n MBn pg41 A DNI CLK TP EXTin R1076 100R 1 88745 2 1CS8745BYLF Figure 19 Daughter Card D amp Global Clock Input Circuit 4 4 3 Clocks Connection between FPGAs and External Daughter Card D E amp F Global The connection between the FPGAs and the External Daughter Catd E amp F clocks are shown in Table 11 Table 11 Connections between FPGAs and External Daughter Card E amp Clocks Signal Name Clock Buffer Pin FPGA Pin SMA amp Daughter Card D Zero Delay Global Clock Buffer CLK
77. 50 HARDWARE DESCRIPTION ABCDEFGH4JK 1 1 2 2 3 H BE E IS E Clock outputs 6 6 Power SE 8 8 9 9 User IO 10 10 M veer 12 12 is E B 13 Ground 14 E 14 B 15 16 c 16 17 15 B BU 18 18 19 d 5 EIE 20 Eg 20 gt 21 22 22 88 B 23 24 24 25 2 1 25 26 26 27 MAN gt 27 28 28 29 5 2 29 30 S 31 S 5 32 32 Be 34 Eg 34 35 36 36 37 B 18 37 38 38 39 39 Figure 46 Daughter Card Header Bank Pin Assignments DN7006K10PCle 8T User Manual www dinigroup com HARDWARE DESCRIPTION 17 3 Special Pins on the Daughter Card Header 17 3 1 GCAp n and GCBp n The daughter card pin out defines two bidirectional differential clock pins These clock signals are intended to be used as differential clock signals These signals are routed to dedicated clock inputs on the Stratix III devices and can be used for source synchronous clocking 17 3 2 Vccio Power Supply On the Stratix III FPGA each IO bank has its own Veco pins is determined by the IO standard for that particular IO bank Since a daughter card will not always be present on a daughter connector a bias gen
78. 56 AL20 J40 197 pull up 4 7K R1378 DIMMC_SDA U56 AY21 U56 AL21 140 195 pull up 4 7K R1379 SODIMM D 8 FPGA D 025 8 198 pul down with 4 7K DIMMD 540 Not Connected R483 J8 200 pull down with 4 7K DIMMD_SA1 Not Connected R484 DIMMD_SCL U25 AW21 U25 AL20 J8 197 pull up 4 7K R475 DIMMD_SDA U25 AY21 U25 AL21 J8 195 pull up 4 7K R474 SODIMM 39 FPGA F 055 J39 198 pull down with 4 7K DIMMF_SAO Not Connected R1368 J39 200 pull down with 4 7K DIMMF SA1 Not Connected R1367 DIMMF SCL U55 M20 U55 C21 39 197 pull up 4 7K R1376 DIMMF_SDA 1755 19 055 021 39 195 pull up 4 7K R1377 5 1 5 Clocking Connections between FPGAs DDR2 SDRAM SODIMMs The clocking connections between the Stratix III FPGAs and the DDR2 SDRAM SODIMMs are shown in Table 19 DN7006K10PCle 8T User Manual www dinigroup com 94 HARDWARE DESCRIPTION Table 19 Clocking Connections between Stratix II FPGAs and DDR2 SDRAM SODIMMs Signal Name FPGA Pin DDR2 SODIMM SODIMM A J9 FPGA A 026 DIMMA_CKOP U26 D26 19 30 DIMMA 1726 26 19 32 DIMMA 026 010 19 166 CK1P U26 E10 19 164 SODIMM 40 FPGA 056 DIMMC CKON U DIMMC U DIMMC_CK1N U DIMMC_CK1P U SODIMM D 8 FPGA D 025 DIMMD CKON U25 AW11 J8 32 DIMMD_CKOP U25 AW10 J8 30 U U F U U U U 56 AW11 J40 32 56 AW10 J40 30
79. 6K10PCle 8T User Manual www dinigroup com 50 PROGRAMMING CONFIGURING THE HARDWARE iMPACT Welcome to iMPACT Please select an action from the list below gt Configure devices using Boundary Scan JTAG Automatically connect to a cable and identify Boundary Scan chain v Prepare a PROM File Prepare a System File Prepare a Boundary Scan File Configure devices using Slave Serial mode Cancel 3 iMPACT will identify the device in the JTAG chain Specify the file location for the PROM programming file CUST_CD DN7006K10PCIE8T FPGA_Reference_Designs Programmin g Files pcie_fpga pcie_dma LX50T and open the FPGA pcie_v5t bit 4 Right click on the XC5VLX50T and select Program Click to program the FPGA A Process Dialog box will indicate programming progress DN7006K10PCle 8T User Manual www dinigroup com 51 PROGRAMMING CONFIGURING THE HARDWARE iMPACT D DiniProducts WN_BITFILESWNMEG_V5T MainTest FX100T_REV2 default ipf Boundary Scan MAR File Edit View Operations Output Debug Window Help 20 Scan ag SlaveSerial 3 Configuration 3 SPI Configuration E SystemACE xc5vlx50t PROM File Formatter pcie v5t bit Processes Available Operations are gt Program gt Get Device ID gt Get Device Signature Usercode m
80. 7006K10PCIe 8T Logic Emulation Board using the PCle Graphics Power adaptor cable 2 Connect the USB Blaster Cable to the JTAG Stratix IIT header J3 on the DN7006K10PClIe 8T 3 Power up the board by turning ON the ATX power supply and verify the Power LED 0525 is ON indicating the presence of 12V located at the bottom left of the PCB by the PCIe edge connector 5 2 Configuring the FPGA To configure the Stratix III FPGAs perform the following steps DN7006K10PCle 8T User Manual www dinigroup com 33 PROGRAMMING CONFIGURING THE HARDWARE 1 Open QUARTUS II software and click the Programmer button The QUARTUS II Programmer window appears Ensure the USB Blaster is shown in the Hardware Setup menu and the Mode is set to JTAG 2 Click Auto Detect QUARTUS II will identify the devices in the JTAG chain The first device is FPGA A B C D E and Quartus Chaint cdf EPSLHO 00000000 00000000 00000000 System Processing fais mcs Waring Eme Fiag ee t S mm Help press F1 3 Select the FPGA to be configured and click Change File Specify the file location for the FPGA programming xxxx sof Select Programming File Look in 22 Desktop Documents gt 4 Comput
81. 71 24 3 3 H 195 312500 Mhz 2 6249 191 3 3 311 010000 Mhz 3 2961 99 4 1 Figure 17 shows one of the clock multiplier circuits LED 0584 15 used to indicate PLL Loss of Lock DN7006K10PCle 8T User Manual www dinigroup com 77 HARDWARE DESCRIPTION U39 4 aub SYNTH XB 00 C228 2 2 G0 6227 DNI 114 285000Mhz P2 5VD OSC 7 1400014 5 96326 600 600 90 37 CLKGO C244 Q 1uF CLKGOr 16 28 C1862 CKIN1 3 CKOUT1 759 CKIN1 CKOUTI 76287 0 1uF FPGA 1 12 INT C18 C236 0 tuF_CLK_FPGA_INTm3 CKIN2 35 _GOp2 R1019 DNI EKING Scr R1018 DNI SYNTH_RATE1_G0 15 KZ 91005 DND SER x R1012 VY DNI 1 RATES LoL 18 SYNTH LOL SYNTH LOL Gor SYNTH G0 gt CA R1068 pg5 SYNTH SCL ALL 2 SCL us pest 15 pg5 SYNTH SDA ALL SDA 800 R191 47 SYNTH 0 GO 24 zs 1059 47K SYNTH A1 1058 4 7 A2 GO 47K R1061 A 47K SYNTH DEC GO 19 R1065 47K SYN FINO 50 20 SYNTH SDI R1057 VA 75015 27 IIC ADDR 1101 000 Figure 17 Clock Multiplier Circuit 4 3 2 Connections between the FPGAs and Clock Multipliers All of the Global Clock Networks on
82. A D LED5 U25 AM13 LED5 DS58 FPGA D LED6 U25 AN13 LED6 DS57 FPGA D LED7 U25 AL13 LED7 DS56 FPGA D LED8 U25 AN11 LED8 0553 FPGA D LED9 U25 W40 LED9 DS49 FPGA D LED10 U25 AB32 LED10 0547 FPGA D LED11 U25 AB33 LED11 DS43 FPGA D LED12 U25 AT21 LED12 DS42 FPGA D LED13 U25 AU18 LED13 0541 FPGA E U36 FPGA E LEDO U36 AB32 LEDO DS71 FPGA E LED1 U36 AH13 LED1 DS68 FPGA E LED2 036 14 LED2 0566 055 FPGA F LEDO U55 M13 LEDO DS113 FPGA F LED1 U55 K13 LED1 05112 FPGA F LED2 DN7006K10PCle 8T User Manual U55 L13 LED2 DS111 www dinigroup com HARDWARE DESCRIPTION Signal Name FPGA Pin LED FPGA F LED3 U55 M15 LED3 DS110 FPGA_F_LED4 U55 M14 LED4 DS107 FPGA_F_LEDS U55 F8 LED5 DS105 FPGA F LED6 U55 F9 LED6 DS102 FPGA F LED7 U55 W40 LED7 DS100 FPGA LED8 U55 AB32 LED8 0598 FPGA F LED9 U55 AB33 LED9 0595 FPGA F LED10 U55 G21 LED10 0593 FPGA F LED11 U55 H21 LED11 DS91 FPGA F LED12 U55 E21 LED12 DS89 FPGA F LED13 U55 F21 LED13 DS87 6 2 Configuration DONE LED After the FPGAs has received all the configuration data successfully it releases the DONE pin which is pulled high by a pull up resistor A low to high transition on the DONE indicates confi
83. A PROM using USBController Configuring the PCIe FPGA using JTAG Cable Xilinx Configuring the PCIe FPGA PROM using JTAG Cable Xilinx Configuring the PCIe FPGA using main txt 7 7 4 Configuring the PCle FPGA using USBController This section lists detailed instructions for programming the Xilinx Virtex 5 FPGA using the USBController software available on the CD ROM Before configuring the FPGA ensure that the USBController and the USB driver software are installed on the host computer Note This User Manual will not be updated for every revision of the USBController software so please be aware of minor differences DN7006K10PCle 8T User Manual www dinigroup com 47 PROGRAMMING CONFIGURING THE HARDWARE Setup Before configuring the FPGA ensure the following steps have been completed 1 Attach an ATX Power Supply to the PCIe Power Header J7 on the DN7006K10PCle 8T Logic Emulation Board using the PCIe Graphics Power adaptor cable 2 Connect the USB Cable to the USB header J3 on the DN7006K10PClIe sT 3 Power up the board by turning ON the ATX power supply and verify the Power ON LED DS25 is ON indicating the presence of 12V located at the bottom left of the PCB by the PCIe edge connector Configuring the FPGA To configure the Xilinx Virtex 5 FPGA perform the following steps 4 Open USBController and verify that the board was correctly identified as a DN7006K10PCIE8T
84. B75 MarS MB76 MB77 MB78 MB76 77 79 78 79 MB81 EST MB82 MB83 MESE 85 BET WESS MB86 MB87 SS MB89 MB90 MB91 11553 BST MB92 MB93 94 MB95 MB96 MB97 MB98 MB99 MB100 MB101 MB102 103 P2 5VD POWER TO P2 5VD S ENG GND CARP GND rugs CLKCN CLKDP CLK_EXT1_MB SNE MB48 QSEn n CLK_EXT1_MBp CURB CLK MB48 QSEp Due to the complexity of the interconnect reference the board netlist on the Customer CD ROM to determine the connections DN7006K10PCle 8T User Manual www dinigroup com 144 HARDWARE DESCRIPTION 14 2 FPGA FPGA Multiple point to point busses routed as LVDS pairs exist between the Stratix III FPGAs see Figure 5 Due to the complexity of the interconnect routing reference the board netlist supplied on the Customer CD ROM to determine the connections 15 Power Monitors and Reset The LT6700 1 is configured as a simple window comparator to monitor the power supplies A Power FAULT will be indicated by the SYS_RSTn signal going active LOW and turning on the Reset LED DS1 The SYS_RSTn signal can also be activated by enabling the Reset Switch S1 See 6 4 Power Supply Status LED s for a description of the power supplies being monitored 15 1 1 Power Monitor Circuit The comparators have a built in 400mV reference and each one have one input available externally s
85. CHAE EA OF AG ie 092144 076156 xnens 092133 096156 S Odd 01 4200 600 75 _ 9104 Spe L t Oxo maneg ZHN 89 r a IH ess 29 Ww wos Inea asn PW ME di wo c 05740 7 4 wap 8 H 8 gn isan lose ovir TY lt o pessna TW ZEZSH Figure 5 DN7006K10PCle 8T Logic Emulation Board Block Diagram The DN7006K10PCle 8T provides six Altera Stratix III FPGAs EP3SL340 The architecture of the board maximizes interconnect by providing a number of dedicated busses between the FPGAs see block diagram The FPGAs can be configured via JTAG using the Altera USB Blaster Download Cable or by the Configuration FPGA Spartan using the Fast Passive Parallel FPP interface via the GUI USB The 56 www dinigroup com DN7006K10PCle 8T User Manual HARDWARE DESCRIPTION board can also configure a Daughter Card via the Mictor Interface Numerous clocking options exist to allow the user a flexible clocking sche
86. CLK MB48 Dp pg2 CLK MB48 Dn pg2 CLK MB48 Ep CLK MB48 En pg2 CLK MB48 Fp MB48 48 Fn 47 MB48 QSEp pg41 5 MB48 QSEn CLK MB48 CUCNE NC 100R 98 42 NCN 41 MB R961 100R Q10 45 NC On 910 735 R170 Q11 NCTin Q11 37 CIK MB 2 R962 1008 012 36 2 912 35 171 008 gu 34 NCT3n 31 14 R956 100R 014 30 CLK EIE 29 R163 100R 915 28 CLK MB NCi5n YN 015 727 6 R950 1008 916 VB 218 25 NCI R162 100R 017 24 017 23 CIK WE NCTS R945 100R Q18 22 S 018 21 NC19p 8159 1008 TP68 19 20 MBT P3 3VD NC 19 MB 20 R940 100R 020 8 CLK MB NC20n 2 15 CLK M ZEE R907 100R 921 P3 3VD Hg 17 C207 C208 C211 C223 C222 C210 32 2 2uF 2 2uF 24 eur 2 2uF 2 2uF 2 2uF vere 49 6 3V 6 3V 6 3 6 3 6 3V 6 3V voco 20 20 20 30 20 20 20 CER F CER F CER lt SY89826L TQFP64
87. D Clocks U30 o DCE amp DCF Clocks 045 e PCIe Reference Clocks REF e Main Bus Clock MB External SMA Clock Inputs per FPGA FPGA x EXTp n not shown in block diagram External Clock Test Points one per FPGA CLK not shown in block diagram The individual clock resources will be further explained in the following paragraphs 4 2 Stratix Illl FPGA Clocking Resources The dedicated clock inputs on the Stratix FPGAs are shown in the block diagram in Figure 16 DN7006K10PCle 8T User Manual www dinigroup com 72 HARDWARE DESCRIPTION General CLK Si5326 IN Multiplier CLK G1 IN DDR2 CLK Joan Multiplier LVDS Interconnect G2 IN CLK Multiplier CLK 48 Configuration 1 48 IN FPGA Spartan 3 CLK MB48 CLK REF P Virtex 5 REF CLK REF IN CLK REF N DAUGHTER CARD TOP MEG ARRAY Plug 400 Pin CLK EXTO xP 84520 1021 rome EXTO ARRAY Receptacle 400 Pin 74390 101LF External Differential _ Clock Input DAUGHTER CARD TOP MEG ARRAY Plug 400 Pin 84520 102LF EXT1 MEG ARRAY Receptacle 400 Pin CLK_EXT1_xN 74390 101LF Figure 16 Stratix III FPGA Dedicated Clock Inputs 4 3 Clock Multipliers x4 The 15326 is a jitter attenuating precision clock multiplie
88. DEN BERE RAI E Hayes 9 1 1 Serial Management Interface eene enn ono lebe REED GR EOD REPERI DE 123 9 1 2 Ethernet LED s 9 1 3 Timing L ite e te D EE DEED utes tree Hee n a EA 9 1 4 Ethernet EET 124 9 1 5 Connections between Stratix III FPGAs and Ethernet PHYs 124 10 PCIE INTERFACE 10 1 Block Diagram 10 1 25 locking T ERR RERO 10 13 DD PEE 10 1 4 PCIe Power Connector 10 1 5 Connection between Virtex 5 FPGA and Stratix III FPGA A eene nennen rne nnne tnnt nnne tenet netten innen 128 11 MISCELEANEQUS FPGA IO HEADERS geile e e eee IRIS e Re EARLIER XN e CI 135 1111 FPGA IO Header Circuit 135 11 1 2 Connections between FPGAs and 10 pin IO Headers 12 MICTOR HEADERS e ER Er RR 12 1 1 Mictor Header 12 1 2 0 Mictor Header Rt re NB EUR OBERE ED 13 REMOTE SLAVE SELECTMAP CONFIGURATION 18 41 Slave SelectMAP Mictor REESE YE GROS 13 52 Slave Sel ctMAP Mictor connections to the FPGA CREE RUE AERE 141 14 FPGA INTERCONNECT 14 1 MainBus MB etm oor snmmo o T Main Bus MIB S LT Te ete te Eo TR PEOR IRURE 143 14 2 145 15 POWER MONITORS AND RESET 145 15 1 1 Power Monitor 145 15
89. DMIC Provides 2 ot 4 Mictor 38 connectors Compatible with the DDR2 SODIMM sockets User LEDs Small EPROM DNSODM200 DDR1 DDR1 memory module compatible with the 200 pin SODIMM sockets Comes with 512 standard Allows use of standard PC2700 modules up to 1GB 175Mhz performance DNSODM200 SDR SDR memory module compatible with 200 pin SODIMM sockets Accepts PC133 modules up to 512MB User is required to install a Jumper Comes with 256 standard 75Mhz performance DNSODM200 FLASH Spansion S29WS064 memory x2 Each is 4Mx16 bit flash 16Mb SRAM memory 512k x 32 Compatible with DDR2 SODIMM sockets 66Mhz performance read burst Other SODIMMSs include access to the following interfaces USB 3 3V IO FPGA interconnect 21 1 2 Extenders The DNPCIEXT S3 5 is an extender card designed to aid in the debug and test of PCle based circuit boards This is an active extender card an Intel 21154 PCIe to PCIe Bridge is used to isolate the primary PCIe bus from the three secondary PCIe bus slots Since primary and secondary busses ate electrically isolated a much cleaner electrical signaling environment exists and a single host slot can be expanded to contain up to three plug in PCIe cards The primary PCIe frequency can range from 0 to 66 66MHz The secondary PCle frequency is configurable to be the primary frequency or one half the primary frequency DIP switches ate provided to force the primary secondary busses to 33MHz
90. DOPTX9 DCD1NRX0 DCD1NRX1 DN7006K10PCle 8T User Manual www dinigroup com 155 HARDWARE DESCRIPTION SIGNAL Receptacle Bottom DCDI1NTXO DCDINTX1 DCDI1NTX10 DCDINTX11 DCDINTX2 DCD1NTX3 DCD1NTX4 DCD1NTX5 DCD1NTX6 DCD1NTX7 DCD1NTX8 DCD1NTX9 DCD1PRX0 DCD1PRX1 DCD1PRX10 DCD1PRX11 DCD1PRX2 DCD1PRX3 DN7006K10PCle 8T User Manual www dinigroup com 156 HARDWARE DESCRIPTION NETTEN 3 SIGNAL Receptacle Bottom DCD1PRX7 P4 K17 DCD1PRX8 DCD1PRX9 DCD1PTX0 DCD1PTX1 DCD1PTX10 DCD1PTX11 DCD1PTX2 DCD1PTX3 DCD1PTX4 DCD1PTX5 DCD1PTX6 DCD1PTX7 DCD1PTX8 DCD1PTX9 DCD2NRX0 DCD2NRX1 DCD2NRX10 DCD2NRX11_GCB DCD2NRX2 DCD2NRX3 DCD2NRX4 DCD2NRX5 DCD2NRX6 DCD2NRX7 DN7006K10PCle 8T User Manual www dinigroup com 157 HARDWARE DESCRIPTION Daughter Card SIGNAL Receptacle Bottom FPGA DCD2NRXS P4 B38 25 AEA DCD2NRX9 P4 B40 25 AD5 DCD2NTXO P4 D24 25 AB5 DCD2NTX1 P4 D26 25 AC12 DCD2NTX10 P4 F27 25 AD7 DCD2NTX11 25 AD13 DCD2NTX2 25 AC9 DCD2NTX3 25 AE6 DCD2NTX4 25 AF6 DCD2NTX5 25 AG5 DCD2NTX6 25 AD9 DCD2NTX7 25 AE9 DCD2NTX8 25 AD11 DCD2NTX9 25 AB7 DCD2PRXO 25 DCD2PRX1 25 AC1 DCD2PRX10 25 AD4 DCD2PRX11_GCB 25 AB4 DCD2PRX2 25 AE1 DCD2PRX3 25 DCD2PRX4 25 AG2 DCD2PRX5 25 AH2 DCD2PRX6 25 AF4 DCD2PRX7 25 AG4 DCD2PRX8 25 AE5 DCD2PRX9 25 AD6 DCD2PTXO 25 AB6 DCD2PTX1 25 AC13 DN7006K10PCle 8T User Manual www dinigroup com 158 HARDWARE DESCRIPTION Daughter
91. DQ30 DN7006K10PCle 8T User Manual www dinigroup com 97 HARDWARE DESCRIPTION Signal Name oly cg 216 w C2 5 DIMMA DQ34 DIMMA 0035 DQ36 DQ37 DQ38 DIMMA_DQ39 DQ4 0040 0042 0043 0044 DN7006K10PCle 8T User Manual 2 pc FPGA Pin 26 B19 26 L19 26 K19 26 D19 26 D18 26 L18 26 K18 26 18 26 E19 26 F24 26 M16 26 M17 26 A11 26 B10 26 L15 26 L16 26 N17 26 A10 26 E15 26 D15 26 E24 26 13 26 213 26 214 26 14 26 B13 26 A12 26 K15 26 14 9 76 9 123 9 125 9 135 9 137 9 124 9 126 9 134 9 136 www dinigroup com SODIMM Pin 98 HARDWARE DESCRIPTION Signal Name FPGA Pin SODIMM Pin 26 G14 26 13 26 24 26 K14 26 J13 26 F13 26 G12 26 G24 26 A26 26 J24 26 A25 26 B25 26 A28 26 B28 26 B15 26 C15 26 B18 26 C18 26 C17 26 D17 26 A8 26 A9 26 B12 26 C12 26 E12 26 12 26 13 26 G23 26 E25 TT U gt DN7006K10PCle 8T User Manual www dinigroup com 99 HARDWARE DESCRIPTION Signal Name FPGA Pin SON U26 C20 DIMMA SIN U26 D14 U26 E18 SODIMM Pin 9 110 9 115 j9 109 SODIMM C 40 FPGA C 056 MMC I I I I I I I I I I I I I I cya EG
92. Data Signals AD 21 0 Control Signals AD 32 35 is actually ALE MB WR MB RD DONE Virtex 5 FPGA Interface Signals Clock Signals CLK 48 FB P N 5 Data Signals DIN SELECTMAP DJT 0 Control Signals FPGAQ_RDWR FPGAQ_PROG FPGAQ_CS FPGAQ_DONE FPGAQ_BUSY FPGAQ_INIT FPGAQ_FCSn FPGA_MSEL_QJ2 0 FPGAQ_CCLK Quick Logic Interface Signals DATA IN 15 0 DATA OUT 15 0 BYTE IN 4 0 0 ADDR OUT 0 ADDR IN 2 0 RDWRN OUT RD END CTRL32 CTRL32 OUTZ TAR RD FETCH N QL DMA FULL 1 FULL SPARTAN PRESENT SPARTAN FULL INZ OUTZ SP REQ PCIZ REQ PCIZ OL DETECT Q S PCI RESET RESET SYS RSTn SP IO LED Indicators Signals LED_S_GRN B 0 LEDS_USBACT LEDS_CFACT LEDS_HOSTACT LEDS_PCIACT LED_S_ERR_TEMP LED_S_ERR_CONFIG FAN Control Signals FAN TACH F A FAN TACH Mictot Signals 48 FPGA RD WRZ FPGA M DONE FPGA M CCLK FPGA 15 14 CS MICTOR CLK E TEMP Sensor Signals TEMP ALERTZ Reset Signals Daughter Card Reset RST DC OUT Push Button Reset BUTTON SZ DN7006K10PCle 8T User Manual www dinigroup com 65 HARDWARE DESCRIPTION 3
93. FPGA Termination at Termination at FPGA SODIMM SERIES 50 OHM No Termination ODT WITHOUT CALIBRATION Data Strobe DOS SERIES 50 OHM No Termination ODT WITHOUT CALIBRATION Data Mask DM SERIES 50 OHM No Termination ODT WITHOUT CALIBRATION DIFE Address BA SSTL 18 CLASS 1 560 Pull up to 0 9V Control RASn SSTL 18 CLASSI No Termination 560 Pull up to 0 9V CASn WEn CSn CKE DN7006K10PCle 8T User Manual www dinigroup com 92 HARDWARE DESCRIPTION 5 1 2 Vpp Switching Power Supply P SODIMM x The Texas Instruments PTH12050 DC DC Converter is used to create the Vpp supply for the DDR2 SDRAM SODIMM set to 1 8 see Figure 27 jumper 2 allows the user to change the voltage to the SODIMM and the VCCIO see table default jumper 3 5 1 8V TP22 P12V UA 9 PQSODIMM F2 PSU3 E 1 Pi2VFUSED P SODIMM A D P 100758 5 P SODIMM C37 7 C428 C427 C19 C26 TRACE gt C450 C449 C40 47uF Sh 150uF 1500 47uF 0 tuF DIMMAn 4 igi ssouF 330uF 47uF 2 2 16V 16V 16V 16V 16V 6 3V 6 3V 6 3V 6 3V 20 20 20 20 20 14 20 20 20 20 TANT TANT CER CER R13 TANT TANT CER DNI 0R PTH12080W DIPG T PTH12050WAZ Silkscreen Volt
94. GA A U26 FPGA A LEDO U26 AB32 LEDO DS54 FPGA A LED1 U26 B9 LED1 DS50 FPGA A LED2 U26 F21 LED2 DS46 FPGA B U37 FPGA B LEDO U37 N6 LEDO DS83 FPGA B LED1 U37 N5 LED1 DS82 FPGA B LED2 U37 T10 LED2 DS81 FPGA B LED3 U37 R9 LED3 DS79 FPGA B LEDA U37 M5 LEDA 0578 FPGA B LED5 937 4 LED5 0877 FPGA B LED6 U37 R10 LED6 DS76 FPGA B LED7 U37 P9 LED7 DS75 FPGA B LED8 U37 W40 LED8 0574 FPGA B LED9 U37 AB32 LED9 0572 FPGA B LED10 U37 AB33 LED10 DS70 FPGA B LED11 U37 D5 LED11 DS69 FPGA B LED12 U37 D8 LED12 DS67 FPGA C U56 FPGA C LEDO U56 AT11 LEDO DS109 FPGA C LED1 U56 AN11 LED1 DS106 FPGA C LED2 U56 W40 LED2 DS104 FPGA C LED3 U56 AB32 LED3 DS103 FPGA C 1 4 U56 AB33 LEDA 05101 DN7006K10PCle 8T User Manual www dinigroup com 115 HARDWARE DESCRIPTION Signal Name FPGA Pin LED FPGA C LED5 U56 AT21 LED5 DS99 FPGA C LED6 U56 AU18 LED6 DS96 FPGA C LED7 U56 AT16 LED7 DS94 FPGA C LED8 U56 AW12 LED8 DS92 FPGA C LED9 U56 D5 LED9 DS90 FPGA C LED10 U56 D8 LED10 DS88 FPGA D U25 FPGA D LEDO U25 AV6 LEDO DS64 FPGA D LED1 U25 AW5 LED1 DS63 FPGA D LED2 U25 AY5 LED2 DS62 FPGA D LED3 025 14 LED3 0561 FPGA D 1 4 U25 AK15 LED4 0559 FPG
95. GCB U36 AB4 P5 E3 DCE2NRX11_GCB U36 AB3 P5 F3 Daughter Card F DN7006K10PCle 8T User Manual www dinigroup com 84 HARDWARE DESCRIPTION Signal Name FPGA Pin DC Header Pin DCFOPRX11_GCA U55 AA4 P6 E1 DCFONRX11_GCA U55 AA3 P6 F1 DCF2PRX11 1755 4 P6 E3 DCF2NRX11 U55 AB3 P6 F3 4 5 PCle Reference Clocks buffered 027 clock network driven from the Virtex 5 FPGA 024 labeled is provided as a reference clock When the Dini Group PCI Express endpoint bitfile is loaded into the FPGA 024 and the board is linked to a motherboard over PCI Express this network will be driven with a 250 MHz LVDS clock which is equal to 2 5 times the PCI Express REFCLK in frequency When not installed in a PCI express slot this clock will be zero MHz 4 5 1 Reference Clock Circuit The PCIe clock buffer U27 is provided to distribute the clock network to the Stratix III FPGAs see Figure 21 REF Qp n is used as a feedback clock R759 100R U27 LVDS 1 CLK REFp REFn nae H CLK REF Fn pg2 24 GND Q7 GND 20 9 9 10585408 GER GER GER 65 640 120 24 Figure 21 PCIe Reference Clock Circuit 4 5 2 Connection between FPGAs and the PCle Reference Clock Buffer The connection between the FPGAs and the PCIe Reference Clock Buffer U27 are shown in Table 13 Table 13 Connec
96. IN D33 24 026 26 6 PCIE IN 034 24 AD25 26 G3 PCIE IN D35 24 AD24 26 G1 PCIE IN 036 24 AE25 26 K6 PCIE IN D37 24 AE26 26 2 PCIE IN D38 24 25 26 P12 PCIE IN D39 24 24 26 M7 PCIE IN D40 24 AF23 26 H3 PCIE_IN_D41 24 AE22 26 4 PCIE IN D42 24 AD23 26 PCIE IN 043 24 AC24 26 R14 PCIE IN D44 24 AC23 26 H1 PCIE IN D45 24 AC22 26 J4 PCIE IN D46 24 AB22 26 M6 PCIE IN D47 24 AE21 26 3 PCIE IN D48 24 AF20 26 P13 PCIE IN D49 24 AE20 26 G2 PCIE IN D50 24 AD19 26 R13 PCIE IN D51 24 AD20 26 N11 PCIE IN D52 24 22 26 5 PCIE IN 053 24 AD21 26 5 PCIE IN 054 24 AE18 26 K4 PCIE IN D55 24 AD18 26 K3 ea ea eye c ape 220 eye eG ea GG ee Se G sb Ge Pe DN7006K10PCle 8T User Manual www dinigroup com 130 HARDWARE DESCRIPTION Signal Name Virtex 5 FPGA Pin FPGA A Pin PCIE IN D56 24 AE17 26 K2 PCIE IN D57 24 AE16 26 R12 PCIE IN D58 24 AD16 26 N10 PCIE IN D59 24 AD15 26 M9 PCIE IN D60 24 15 26 E1 PCIE IN D61 24 AF15 26 R11 PCIE IN D62 24 AF14 26 F1 PCIE IN D63 24 AF13 26 F4 PCIE IN EOF 24 AB9 26 P4 PCIE IN EXTRAO 24 W25 26 AA5 PCIE IN EXTRA1 24 V23
97. IPTION Daughter Card SIGNAL Receptacle Bottom FPGA Domo com DCE3PTX8 P5 H39 DN7006K10PCle 8T User Manual www dinigroup com 167 HARDWARE DESCRIPTION SIGNAL Receptacle Bottom DCF SPAREO R1203 1 SPARE1 R1203 2 DCFONRXO 55 15 DCFONRX1 55 13 DCFONRX10 55 2 DCFONRX11 55 AA3 DCFONRX2 55 R1 DCFONRX3 55 U3 DCFONRX4 55 V1 DCFONRX5 55 Y1 DCFONRX6 55 W3 DCFONRX7 55 Y3 DCFONRX8 55 V4 DCFONRX9 55 T1 DCFONTXO 55 Y 12 DCFONTX1 55 W11 DCFONTX10 55 AA11 DCFONTX11 55 U6 DCFONTX2 55 V9 DCFONTX3 55 W9 DCFONTX4 55 V7 DCFONTX5 55 W7 DCFONTX6 55 W5 DCFONTX7 55 Y6 DCFONTX8 55 AA5 DCFONTX9 5 7 DCFOPRXO 55 16 DCFOPRX1 55 T4 DN7006K10PCle 8T User Manual www dinigroup com 168 HARDWARE DESCRIPTION Daughter Card SIGNAL Receptacle Bottom DCFOPRX10 P6 E13 DCFOPRX11 GCA P6 E1 DCFOPRX2 DCFOPRX3 DCFOPRX4 DCFOPRX5 DCFOPRX6 DCFOPRX7 DCFOPRX8 DCFOPRX9 DCFOPTXO DCFOPTX1 DCFOPTX10 DCFOPTX11 DCFOPTX2 DCFOPTX3 DCFOPTX4 DCFOPTX5 DCFOPTX6 DCFOPTX7 DCFOPTX8 DCFOPTX9 DCF1NRXO DCF1NRXI DCF1NRX10 DCF1NRX11 DCF1NRX2 DCF1NRX3 DN7006K10PCle 8T User Manual www dinigroup com 169 HARDWARE DESCRIPTION SIGNAL Receptacle Bottom DCF1NTXO DCFINTX1 DCF1NTXI10 DCFINTX11 DCFINTX2 DCFINTX3 DCFINTX4 DCFINTX5 DCF1NTX6 DCF1NTX7 DCFINTX8 DCFINTX9 DCF1PRX0 DCF1PRX1 DCF1PR
98. MULATION 1 2 DN7006K 10 8 LOGIC EMULATION BOARD FEATURES 22 3 PACKAGE CONTENTS 4 4 T Vc P 5 5 retinentur Sto a DU HS RECO D Tana 5 GETTING STARTED 6 1 BEFORE YOU BEGIN eee 6 1 1 Configuring the Programmable Components 6 1 2 be Bbc T 6 2 INSTALLING THE SOFTWARE cernitis 7 2 1 Exploring the Customer CD YA 2 2 Installing the Driver asigra eaaa IEE aaie 8 3 BOARD SETUD 12 3 1 Before Powering Up the Board 12 3 2 Powering Up the Board 212 4 RUNNING THE ONE SHOT TEST 13 INTRODUCTION TO THE SOFTWARE TOOLG cccssssssssssssssssssssssesscsssssseosssesssesssessssesesssssesessesesssessseesesssesosessesasssesssessesasessssessasesssesessesesesesesessosens 16 1 CONTROLLER cer beoe t E emanare aos 16 1 1 System Requiremenis nce AER RARE EE ONE TOR EAD 17 1 2 Getting Started with USBController 2417 1 2 1 Window 417 122 Basic Menu Operations 18 2 AETEST USB APPLICATION 18 21
99. OM FPGA Programming Header Figure 12 CompactFlash Connectot Figure 13 FPGA JTAG Connector Figure 14 MSEL Configuration Resistors default FPP Figure 15 Clocking Block Diagram Figure 16 Stratix III FPGA Dedicated Clock Inputs Figure 17 Clock Multiplier Circuit Figure 18 External Daughter Card D Global Clock Input Circuit Figure 19 Daughter Card D amp E Global Clock Input Circuit Figure 20 Secondary Daughter Card DC Header Clock Figure 21 PCIe Reference Clock Circuit Figure 22 Main Bus Clock Buffer Figure 23 Stratix III SMA Clock Input Circuit Figure 24 External Clock Test Point Circuit Figure 25 Write Operation Using Parallel ODT and 50 Series OCT of the Stratix III FPGA Device Figure 26 Read Operation from DDR2 SDRAM Memory Using the Parallel OCT Feature of the Figure 27 VDD Switching Power Supply P SODIMM Figure 28 VTT Linear Power Supply 9 VTT Figure 29 Serial Flash Figure 30 LED Indicator Figure 31 MCU Configuration FPGA Serial Port Figure 32 Temperature Sensor FPGA A Figure 33 Ethernet Circuit FPGA Figure 34 PCIe Bus Diagram Figure 35 Virtex 5 SPI Serial Flash Figure 36 PCIe Power Connection Figure 37 Stratix III IO Header FPGA D Figure 38 38 Pin Mictor Header on FPGA Figure 39 Slave Select MAP Mictor Header Figure 40 MainBus Interconnect F
100. ONTX11 DCEONTX2 DCEONTX3 DCEONTX4 DCEONTX5 DCEONTX6 DCEONTX7 DCEONTX8 DCEONTX9 DN7006K10PCle 8T User Manual www dinigroup com 161 HARDWARE DESCRIPTION ME SIGNAL Receptacle Bottom DCE0PRX11 DCEOPRX3 5 9 4 DCEOPRX5 DCEOPRX6 DCEOPRX9 DCEOPTXO DCEOPTX1 DCEOPTX10 DCEOPTX11 DCEOPTX2 DCEOPTX3 4 DCEOPTX5 DCEOPTX6 DCEOPTX7 8 DCEOPTX9 DCEA1NRXO DCE1NRX1 DCE1NRX10 DCE1NRX11 DCE1NRX2 DN7006K10PCle 8T User Manual www dinigroup com 162 HARDWARE DESCRIPTION SIGNAL Receptacle Bottom 1 DCE1NTX10 DCE1NTX11 DCE1INTX2 DCE1NTX3 DCE1NTX4 5 DCE1NTX6 DCE1NTX7 DCE1NTX8 DCE1NTX9 DCE1PRX0 DCE1PRX1 DCE1PRX10 DCE1PRX11 DCE1PRX2 DCE1PRX3 DCE1PRX4 DCE1PRX5 P5 K13 DCE1PRX6 P5 K15 DN7006K10PCle 8T User Manual www dinigroup com 163 HARDWARE DESCRIPTION moa Room SIGNAL Receptacle Bottom 7 36 J2 DCE1PRX8 36 K2 DCE1PRX9 36 K4 DCE1PTXO 36 18 DCEIPTX1 36 65 DCE1PTX10 36 M9 DCEIPTX11 36 P13 DCE1PTX2 36 N11 DCE1PTX3 36 6 DCE1PTX4 36 K6 DCE1PTX5 36 L7 DCE1PTX6 36 M7 DCE1PTX7 36 N9 DCE1PTX8 36 R12 DCE1PTX9 36 R14 DCE2NRX0 36 AC3 DCE2NRX1 36 AD1 DCE2NRX10 36 AD3 DCE2NRX11_GCB 36 AB3 DCE2NRX2 36 AF1 DCE2NRX3 36 AE2 DCE2NRX4 36 1 DCE2NRX5 36 DCE2NRX6 36 DCE2NRX7 36 AG3 DCE2NRX8 6
101. One Shot Test Test FPGA Q 1 Test R5232 Headers Test Ethernet Test External Clock Test The DDR Test will test all DDRs on the current testing board LVDS Frequency Mhz 400 Pick DDR Size Select DDR size 256 512 MB Run Rocket IO in loopback mode Ignore Make sure that your projects are up to date before running this test Please enter the path in which you keep the Dini Group Reference Design Bitfiles D DiniProducts DN_BITFILES Iterations Count 1 3 The FPGAs will now be configured and Shot Test will test the following functions of the boatd see transaction Log for more details e Single Ended Interconnect e LVDS Interconnect FLASH Test Clock Readback e Other Miscellaneous One Shot Tests DN7006K10PCle 8T User Manual www dinigroup com 14 GETTING STARTED 4 Successful testing of the DN7006K10PCIe 8T results in the following message being displayed ONE SHOT TEST PASSED OST Ran 1 times requested to run 1 failed 0 times One Shot Test Finished Execution Time 800 984 seconds DN7006K10PCle 8T User Manual www dinigroup com 15 INTRODUCTION TO THE SOFTWARE TOOLS Intr Chapter oduction to the Software Tools This chapter introduces the software tools that are shipped with the DN7006K10PClIe 8T Logic Emulation Board 1 USB Controller GUI The USBController is a powerful software ap
102. PGA Pin RS232_FPGA_RX 26 W40 FPGA 37 L3 FPGA B 56 AM12 FPGA C 25 AN10 FPGA D 36 AB33 FPGA E 55 B7 FPGA F 24 G15 FPGA Q RS232_FPGA_TX 26 AB33 FPGA A 37 LA FPGA 56 AR12 FPGA 25 AR10 FPGA D 36 W40 FPGA 55 A7 FPGA F 24 G16 FPGA Q 8 Temperature Sensors The MAX1617A is a precise digital thermometer that reports the temperature of both a remote sensor and its own package The remote sensor is a diode connected transistor typically a low cost easily mounted 2N3904 NPN type that replaces conventional thermistors or thermocouples Remote accuracy is 3 C for multiple transistor manufacturers with no calibration needed The remote channel can also measure the die temperature of other ICs such as microprocessors that contain an on chip diode connected transistor 811 Temperature Sensor Circuit Each FPGA is connected to a temperature sensor This sensor measures the temperature of the FPGA silicon die see Figure 32 The maximum recommended operating temperature of the FPGA is 85 degrees When the configuration circuitry measures the temperature of any FPGA above 80 degtees it will immediately un configure the FPGA and prevent it from re configuring DN7006K10PCle 8T User Manual www dinigroup com 121 HARDWARE DESCRIPTION P3 3VD P2 5VD STBY C576 P3 3VD pg5 FPGAA TEMP P 1000 34 DXP E T 5 FPGAA TEMP DXN TEMP
103. PHYs The connection between the Stratix III FPGAs and the Ethernet PHY s are shown in Table 30 DN7006K10PCle 8T User Manual www dinigroup com 124 HARDWARE DESCRIPTION Table 30 Connection between Stratix III FPGAs and Ethernet PHYs Signal Name Stratix III FPGA Pin Ethernet PHY Pin FPGA D Ethernet Interface ETHD EECLK ETHD EEDAT SCL SDA ETHD_INT ETHD_MDC ETHD_MDIO ETHD_RX_CTL ETHD RXDO RXD1 ETHD RXD2 ETHD RXD3 ETHD TCK ETHD TX CIL ETHD TXDO TXD1 ETHD TXD2 ETHD TXD3 FPGA F Ethernet Interface ETHF EEDAT ETHF IIC SCL SDA ETHEF_INT ETHF_MDC ETHF_MDIO ETHF_RX_CTL 25 BB4 25 BA3 25 AV7 25 AW8 25 AU8 25 BB3 25 BB2 25 6 25 5 25 BB6 25 BB7 25 AY8 59 7 25 AW9 25 BA7 25 AU11 25 AU10 25 AV9 Cc cec e OIG C Ea p em eu 58 10 58 9 120 6 120 5 55 68 55 10 55 19 55 5 gt Lee C pex DN7006K10PCle 8T User Manual www dinigroup com 125 HARDWARE DESCRIPTION Signal Name Stratix III FPGA Pin Ethernet PHY Pin RXDO 58 23 55 M12 ETHF_RXD1 58 22 55 L12 RXD2 58 21 55 J12 ETHF_RXD3 58 20 55 K12
104. Receptacle Bottom DCF2PTX4 DCF2PTX5 DCF2PTX6 DCF2PTX7 DCF2PTX8 DCF2PTX9 DCF3NRXO DCF3NRX1 DCF3NRX10 DCF3NRX11 DCF3NRX2 DCF3NRX3 DCF3NRX4 DCF3NRX5 DCF3NRX6 DCF3NRX7 DCF3NRX8 DCF3NRX9 DCF3NTXO DCF3NTX1 DCF3NTX10 DCF3NTX2 DCF3NTX3 DCF3NTX4 DCF3NTX5 DCF3NTX6 DCF3NTX7 DCF3NTX8 DN7006K10PCle 8T User Manual P6 C31 P6 C33 FPGA 55 AF7 55 6 55 AD10 55 AE10 55 AD12 55 8 55 3 55 AP3 55 AU2 55 AY3 55 1 55 55 1 55 AV3 55 AW1 55 AT3 55 AU4 55 AR3 55 AJ12 55 55 6 55 AJ10 55 AK9 55 AK12 55 AL6 5 5 55 5 55 AL11 www dinigroup com 173 HARDWARE DESCRIPTION Daughter Card SIGNAL Receptacle Bottom DCF3NTX9 DCF3PRX0 DCF3PRX1 DCF3PRX10 DCF3PRX11 DCF3PRX2 DCF3PRX3 DCF3PRX4 DCF3PRX5 DCF3PRX6 DCF3PRX7 DCF3PRX8 DCF3PRX9 55 7 55 AN4 55 AP4 55 AU3 55 AW3 55 AP2 55 AR1 55 1 55 4 55 AW2 55 AT4 55 05 55 4 55 AJ13 DCF3PTX1 DCF3PTX10 DCF3PTX2 DCF3PTX3 DCF3PTX4 DCF3PTX5 DCF3PTX6 DCF3PTX7 DCF3PTX8 DCF3PTX9 ZEE 17 6 Insertion Removal of Daughter Card Due to the high density MEG Array connectors the pins on the plug and receptacle of the MEG Array connectors are very delicate When plugging in a daughter card make sure to align the daughter card first before pressing on the connector Be absolutely certain DN7006K10PCle 8T User Manual www di
105. Slave Serial mode 3 iMPACT will identify the device in the JTAG chain Note The FPGA XC5VLX50T will be high lighted in the JTAG chain select Bypass since we intend to configure the FPGA with the PROM 4 Right click on the XC5VLX50T device and select Add SPI Flash Specify the file location for the PROM programming file CUST_CD DN7006K10PCIE8T FPGA_Reference_Designs Programmin g Files pcie_fpga pcie_dma LX50T open the PROM fie pcie v5t mcs 5 Select AT45DB642D in the drop down list of the FPGA SPI Flash Association window and click 6 Right click on the FLASH device and select Program A Process Dialog box will indicate programming progress DN7006K10PCle 8T User Manual www dinigroup com 53 PROGRAMMING CONFIGURING THE HARDWARE iMPACT D IDiniProductsDN BITFILESYONMEG V5TWainTestFX100T REV2Wdefault ipf Boundary Scan MAR Edit View Operations Output Debug Window Help JA KI 80529 9 Scan ag SlaveSerial 2 3 Configuration 3 SPI Configuration E SystemACE xc5vlx50t PROM File Formatter bypass Right click device to select operations 5 Available Operations are gt Program mp Verify mp Erase gt Blank Check m Readback Operations Boundary Scan 1 Programmed successfully PROGRESS END End O
106. Source and binary files for the application Schematics PDF vetsion of the board schematic A netlist that contains all nets on the board that connects to user IO on any USB Software Applications Source and binary files for USB Controller applications 2 2 Installing the USB GUI Driver When the DN7006K10PCle 8T power on and you connect it to a USB port for the first time the pop up window will ask you to install a driver The driver installation instructions for Windows XP system shown below e Select No not this time to search for software DN7006K10PCle 8T User Manual www dinigroup com 8 GETTING STARTED Found New Hardware Wizard Welcome to the Found New Hardware Wizard Windows will search for current and updated software by looking on your computer on the hardware installation CD or on the Windows Update Web site with your permission Read our privacy policy Can Windows connect to Windows Update to search for software Yes this time only Yes now and every time connect a device Click Next to continue Select Install from a list or specific location Advanced and click Next to continue Found New Hardware Wizard This wizard helps you install software for DiniGroup USB Hosted Board If your hardware came with an installation CD lt or floppy disk insert it now What do you want the wizard to
107. TEMP 20 4 LED 5 ERR CONFIGZ U20 Y5 Clock Multipliers LOL Indicators SYNTH LOL 60 U41 18 SYNTH LOL G1 U54 18 DN7006K10PCle 8T User Manual www dinigroup com 119 HARDWARE DESCRIPTION Signal Name Source SYNTH LOL G2 SYNTH LOL 7 RS232 Port An 232 serial port P1 P2 is provided for low speed communication with the MCU and FPGA logic The RS 232 standard specifies output voltage levels between 5V to 15V for logical 1 and 5V to 15V for logical 0 Input must be compatible with voltages in the range of 3V to 15V for logical 1 and 3V to 15V for logical 0 This ensures data bits are read correctly even at maximum cable lengths between DTE and specified as 50 feet The RS 232 standatd has two primary modes of operation Data Terminal Equipment and Data Communication Equipment DCE These can be thought of as host or PC for DTE and as peripheral for DCE The DN7006K10PCIe 8T operates in the mode only 7 1 1 RS232 Circuit Diagram Figure 31 shows the implementation of the serial port on the DN7006K10PCIe 8T Logic Emulation Boatd RS232 FPGA TX LH pem meur A 85232 FPGA TXD 15232 MCU TUN TIUS 85232 MCU TXD 9 19 R298 P amp OV 12
108. THE DINI GROUP LOGIC Emulation Source User Manual DN7006K10PCIe 8T LOGIC SOURCE DN7006K10PCle 8T User Manual Version 1 0 Date of Print February 2 2009 The Dini Group 7469 Draper Ave La Jolla CA92037 Phone 858 454 3419 Fax 858 454 1728 support dinigroup com www dinigroup com Copyright Notice and Proprietary Information Copyright 2008 The Dini Group rights reserved No part of this copyrighted work may be reproduced modified or distributed in any form or by any means without the prior written permission of The Dini Group Right to Copy Documentation The Dini Group permits licensee to make copies of the documentation for its internal use only Each copy shall include all copyrights trademarks disclaimers and proprietary rights notices Disclaimer The Dini Group has made reasonable efforts to ensure that the information in this document is accurate and complete However The Dini Group assumes no liability for errors or for any incidental consequential indirect or special damages including without limitation loss of use loss or alteration of data delays or lost profits or savings arising from the use of this document or the product which it accompanies Table of Contents 1 1 DN7006K 10PCIE 8T LOGIC E
109. X10 DCF1PRX11 DCF1PRX2 DCF1PRX3 DCF1PRX4 DCF1PRX5 DCF1PRX6 DCF1PRX7 DN7006K10PCle 8T User Manual www dinigroup com 170 HARDWARE DESCRIPTION Daughter Card SIGNAL Receptacle Bottom DCF1PRX8 P6 K19 55 K2 DCF1PRX9 P6 K21 55 K4 DCFIPTXO 55 8 DCFIPTX1 55 65 DCFIPTX10O 55 9 DCFIPTX11 55 13 DCFIPTX2 55 N11 DCFIPTX3 55 16 DCFIPTX4 55 K6 DCFIPTX5 55 17 DCFIPTX6 55 M7 DCFIPTX7 55 N9 DCFIPTX8 55 R12 DCFIPTX9 55 R14 DCF2NRX0 55 AC3 DCF2NRX1 55 AD1 DCF2NRX10 55 AD3 DCF2NRX11_GCB 55 AB3 DCF2NRX2 55 1 DCF2NRX3 55 AE2 DCF2NRX4 55 1 DCF2NRX5 55 1 DCF2NRX6 55 DCF2NRX7 55 AG3 DCF2NRX8 55 4 DCF2NRX9 5 AD5 DCF2NTX0 55 AB5 DCF2NTX1 55 12 DN7006K10PCle 8T User Manual www dinigroup com 171 HARDWARE DESCRIPTION Daughter Card SIGNAL Receptacle Bottom FPGA DCF2NTX10 P6 F27 55 AD7 DCF2NTX11 P6 F39 55 AD13 DCF2NTX2 P6 D28 55 AC9 DCF2NTX3 P6 D30 55 DCF2NTX4 P6 D32 55 AF6 DCF2NTX5 55 AG5 DCF2NTX6 55 AD9 DCF2NTX7 55 AE9 DCF2NTX8 55 AD11 DCF2NTX9 55 AB7 DCF2PRX0 55 AC4 DCF2PRX1 55 1 DCF2PRX10 55 AD4 DCF2PRX11_GCB 55 AB4 DCF2PRX2 55 1 DCF2PRX3 55 AE3 DCF2PRX4 55 AG2 DCF2PRX5 55 AH2 DCF2PRX6 55 4 DCF2PRX7 55 4 DCF2PRX8 55 AE5 DCF2PRX9 55 AD6 DCF2PTXO 55 AB6 DCF2PTX1 55 AC13 DCF2PTX10 55 AD8 DCF2PTX11 5 AD14 DCF2PTX2 55 AC10 DCF2PTX3 55 AE7 DN7006K10PCle 8T User Manual www dinigroup com 172 HARDWARE DESCRIPTION Daughter Card SIGNAL
110. al www dinigroup com 19 INTRODUCTION TO THE SOFTWARE TOOLS e Various loops for PCIe device function and ID numbers Write and Read Configuration DWORD for board settings Access to the Bus interface BAR Memory operations Configure Save BARs from to a file Configure FPGAs 3 2 Running AETEST The following images show a terminal session in Windows XP cx C dpalmerMKS AETest aetest aetest_wdm exe Symbolic link N N pcifftven_1 df dev_1864 amp subs ys 18641 0113 _00 481 f 8f GHC f bida27 6ac7 4d1f 9eb80 1daf1b7e7131 Got ConfigFPGA_id Found Device 41865 name DN8GQQKiGPCIE Uirtex4 PCI Express Board Compiled on Sep 18 2006 at 13 55 46 press any key The initial display of AETest shows the results of its scan of the PCIe bus If the driver for the DN7006K10PCIE 8T is not installed then the software will display a message that no device was found If this occurs and you are using windows look into the computer s hardware manager and see if PCI Device with Vendor ID 0x17DF appears If it does then there is a software or driver problem If it does not then there is a hardware problem Look on the board near the 6 pin PCI Express power connector There 1s a row of LEDs corresponding to the PCI Express status signals RED LEDs for LOS indicated the board is not linking with its link partner Yellow is activity Three green LEDs a valid
111. an safely operate as hot 120 degrees but timing is not guaranteed Use the temperature setting in the ISE place and route tool to make timing allowances for operating the FPGA out of range The temperature limit on the DN7006K10PCIe8T Logic Emulation Board can be disabled by a menu option in the configuration interface RS232 8 1 2 Connection between FPGAs and Temperature Sensors The connection between the Stratix III FPGAs and the Temperature Sensors are shown in Table 16 DN7006K10PCle 8T User Manual www dinigroup com 122 HARDWARE DESCRIPTION Table 29 Connection between Stratix III FPGAs and Temperature Sensors Signal Name Sensor Pin FPGAA TEMP P FPGAA TEMP N FPGAB TEMP P FPGAB TEMP N FPGAC TEMP P FPGAC TEMP N FPGAD TEMP P FPGAD TEMP N FPGAE TEMP FPGAE TEMP N FPGAF TEMP P FPGAF TEMP N FPGAF TEMP P FPGAF TEMP N 9 Ethernet PHYs The VSC8601 device is a low power Gigabit Ethernet GBe transceiver ideal for Gigabit LAN on Motherboard applications Vitesse s mixed and digital signal processing DSP architecture assures robust performance It supports both half duplex 10BASE T 100BASE TX and 1000BASE T communication speeds over Categoty 5 Cat5 unshielded twisted pair UTP cable at distances greater than 140m displaying excellent tolerance to NEXT
112. ash card before using them to configure each FPGA If the target FPGA annotated in the bit file header is not the same type as the FPGA the MCU detects on the board it will reject the file and flash the error LED Before this command is executed lt gt is set to the default value y If you want to encrypt of compress your bit files you will need to set lt y n gt to n VERBOSE LEVEL level During the configuration process there are three different verbose levels that can be selected for the serial port messages LevelO o Fatalerror messages o Bitfile errors e g bit file was created for the wrong part bit file was created with wrong version of Xilinx tools or bitgen options are set incorrectly Initializing message will appear before configuration DN7006K10PCle 8T User Manual www dinigroup com 25 PROGRAMMING CONFIGURING THE HARDWARE Instruction Function A single message will appear once the FPGA is configured Level 1 All messages that Level 0 displays Displays configuration type should be Select MAP Displays current FPGA being configured if the configuration type is set to Select MAP Displays a message at the completion of configuration for each FPGA configured Level 2 All messages that Level 1 displays Options that are found in main txt Bit file names for each FPGA as entered in main txt Maker ID device ID and size of Smart Media card All files found on Smart Me
113. ation about the OCT features On the DDR2 SDRAM there is a dynamic parallel on die termination ODT feature that can be turned on when the FPGA is writing to the DDR2 SDRAM memory and turn off when the FPGA is reading from the DDR2 SDRAM memory The ODT features are available in settings of 1500 750 and 500 500 setting is only available in DDR2 SDRAM with operating frequencies greater than 267MHz Refer to the respective memory data sheet for additional information about the available settings of the ODT and the output driver impedance features and the timing requirements for driving the ODT pin in DDR2 SDRAM Figure 25 illustrates the write operation to the DDRZ SDRAM with the ODT feature turned on and using 500 series OCT feature of the Stratix III FPGA device In this setup the transmitter FPGA is properly terminated with matching impedance to the transmission line thus eliminating any ringing or reflection The receiver DDR2 SDRAM memoty is also properly terminated when the dynamic ODT setting is at 750 FPGA DDR2 DIMM DDR2 Component Driver 1500 22 509 NN Receiver 0 9V Y Figure 25 Write Operation Using Parallel ODT and 50 Series OCT of the Stratix III FPGA Device Figure 26 illustrates the read operation from the DDRZ SDRAM memory using the parallel OCT feature of the Stratix III device In this setup the driver
114. ation of a differential clock input is gtven below alt_inbuf_diff io_standard LVDS inst ibat CLK_GON o CLK_G0_in The pin assignment in the QSF file set_location_assignment PIN_BB22 to CLK_GON set location assignment PIN_BA22 to global clock netwotks have a differential test point terminated by 100R resistor used to measure clock frequency The positive side of the differential signal is connected to pin 1 square and the negative side is connected to pin 2 circular of the test point DN7006K10PCle 8T User Manual www dinigroup com 70 HARDWARE DESCRIPTION x10
115. cification for this interface is in MainBus section Source clock n Sets clock to run from source n where n 1 corresponds to normal operation and 2 corresponds to bypass mode output Clock can be GO DN7006K10PCle 8T User Manual www dinigroup com 26 PROGRAMMING CONFIGURING THE HARDWARE 3 Configuring an FPGA using main txt This section lists detailed instructions for programming the Altera Stratix I FPGAs using main txt Before configuring the FPGAs ensure that the FPGA bitfiles and main txt has been copied to the root directory of the CompactFlash card see Figure 2 Removable Disk KIBS File Edit View Favorites Tools Help gt Search E Folders Address E 1 23 5 Type File and Folder Tasks lt E fpga_a rbf 14 330 REF File Mea El fpga_b rbf 14 330KB RBF Fie en Foga_c rbF 14 330 REF File Saoi folder to 2 d rbf 14 330 REF 2 il Share this folder e rbf 14 330 RBF File 8 14 330 REF File L Main txt 1KB Text Document Other Places 4 Computer 3 My Documents Figure 3 CompactFlash Directory Listing 3 1 Setup Before configuring the FPGA ensure the following steps have been completed 1 Attach an ATX Power Supply to the PCIe Power Header J7 on the DN7006K10PCIe 8T Logic Emulation Board usi
116. cted to the ground plane and can be used to ground test equipment The user must not short any power rails or signals to these metal bars they can conduct a lot of current Mounting holes are provided to allow the PCB to be mounted in a case KARA mmn mmu UL 84 WWW y d d y d hA Lnn nei n J 4 RE L eje oe Tun un nul EN ue ee e we VS CN ng KN A ee ete EMITE 4 wf Cy HHI xr m a 1 ET E H HHE H _ DN7006K10PCle 8T User Manual www dinigroup com 177 HARDWARE DESCRIPTION 18 2 Standard Daughter Card Size The DN7006K10PCIe 8T Logic Emulation Board provides mounting hole locations for a Daughter Card with the dimensions given below The DNMEG Obs Daughter Card product conforms to these dimensions 2 75 View Top Side 400 Pin Receptacle on Back P N 74390 101 1 4 1 950 0 500 73 18 3 Daughter Spacing With this host plate daughter card arrangement there is a limited Z dimension clearance for backside components on the daughter card This dimension
117. d with capacitors if AC coupling is required refer to Figure 23 J17 J20 is Amphenol SMA jacks P N 901 144 8RFX with an impedance rating of 500 Refer to the Alera Stratix Device Handbook for levels J17 901 144 8RFX 5 1 4 5 3 5 1 4 0 901 144 8RFX J20 Figure 23 Stratix III FPGA SMA Clock Input Circuit 4 7 2 gt Connection between Stratix Ill FPGAs and External SMA Connectors connection between the Stratix III FPGAs and the external 5 5 are shown in Table 15 Table 15 Connection between Stratix III FPGAs and External SMA Connectors Signal Name FPGA Pin FPGA EXTN U26 AB40 FPGA A U26 AB39 DN7006K10PCle 8T User Manual www dinigroup com 88 HARDWARE DESCRIPTION Signal Name FPGA Pin EXTN EXTP CCLK C EXTN EXTP D EXTN 37 40 37 39 56 40 56 39 25 40 25 39 36 40 36 39 55 40 55 39 D FPGA EXTN EXTP FPGA EXTN FPGA F C 4 8 External Clock Test Points one FPGA A two terminal header is provided to allow for an external differential clock x TPp n input to each of the Stratix III FPGAs 4 8 4 External Clock Test Point C
118. dia card If sanity check is chosen the bit file attributes will be displayed part package date and time of the bit file During configuration a will be printed out after each block 16 KB has successfully been transferred from the Smart Media to the current FPGA FPGA A lt filename gt For each FPGA the user would like to configure there must be one line e g FPGA A will be configured with the file named by lt filename gt CLOCK FREQUENCY lt clock gt lt number gt MHz The MCU will adjust the clock multiplier producing clock lt clock gt to the frequency lt number gt Valid clock names are GO G1 and G2 DCLK DC lt dc source gt lt n gt Mhz For valid combinations please see the diagram in par 4 4Daughter Card DC Header Clocks of this document MEMORY MAPPED Ox WORDADDR lt gt Writes to a configuration Register This command can be used to access features that do not have a main txt command Example applications include setting clock sources settings the EXTO or EXT1 clock buffers to zero delay mode or setting the clocks to frequencies lower than 31Mhz MAIN BUS 0x lt DWORDADDR gt Ox lt DWORDDATA gt Writes data in lt DWORDDATA gt to the address on the main bus interface at lt DWORDADDR gt This command only makes sense in the context of the Dini Group reference design unless your design implements a compatible controller on the main bus pins The Spe
119. e MAIN configuration file List files on Smart Media Display Smart Media text file Change RS232 PPC Ports Display FPGA Temperatures Set FPGA Temperature Alarm Threshold Read Temperature Sensor Reg Write Temperature Sensor Reg Disconnect Reconnect USB ENTER SELECTION lt gt Connected 0 02 26 Auto detect 19200 8 N 1 The HyperTerminal interface gives the user an easy method for handling and monitoring the DN7006K10PCIe 8T configuration DN7006K10PCle 8T User Manual www dinigroup com 29 PROGRAMMING CONFIGURING THE HARDWARE 3 4 1 Description of Main Menu Options Table 4 describes the Main Menu options found on the MCU HyperTerminal interface Table 4 HyperTerminal Main Menu Options Function Description Configure FPGAs Using main txt The FPGAs will be configured using Fast Passive Parallel FPP Interactive configuration menu This option takes you to a menu titled Interactive Configuration Menu and allows the FPGAs to be configured through a set of menu options instead of using the main txt file Check Configuration Status This option checks the status of the DONE pin and prints out whether or not the FPGAs have been configured along with the file name that was used for configuration Change MAIN configuration file By default the processor uses the file main txt to get the name of the bit fi
120. ee Figure 42 The comparators are configured as a simple window comparator to detect high low voltage thresholds 1 Pag VOC DNI P3 3VD 052 COPPERDOT RED P3 3VD BAD q R328 R320 15K DNI R309 R302 300R 1K 0 99VA_trip 3 1 1A FILT 1 21 tip 4 C2 qoe 1 1A BADn 8 25 LT6700 1 SOT95P280 6N Figure 42 Low Voltage Comparator Circuit 15 1 2 Connection between Reset Buffers and FPGAs The connection between the Reset Buffers and the FPGAs board are shown in Table 29 Table 36 Connection between Reset Buffers and FPGAs Signal Name Reset Buffer Pin FPGAs SYS_RSTn_SP_IO U18 7 U20 B16 SYS_RSTn_SP_PROG U18 5 U20 A2 via R407 SYS RSIn Q PROG U18 2 U24 J20 via R580 SYS RSIn Q IO U75 7 U24 F17 DN7006K10PCle 8T User Manual www dinigroup com 145 HARDWARE DESCRIPTION Signal Name Reset Buffer Pin FPGAs SYS RSIn MCU U75 5 amp 2 U72 99 and U71 12 16 Power Distribution The DN7006K10PCle 8T Logic Emulation Board supports a wide range of technologies from legacy devices like serial ports to DDR2 SDRAM Ethernet Transceivers and Transceivers on the Xilinx FPGA This wide range of technologies including the various FPGA power supplies requires a variety of power supplies These are provided on the DN7006K10PClIe 8T Logic Emulation Board using a combination of switching and linear power regulators 16 1 In Sy
121. entation of 9x9 12 12 18x18 36X36 multipliers at up to 550 MHz multiply accumulate functions and finite impulse response FIR filters I O GND PWR ratio of 8 1 1 along with on die and on package decoupling for robust signal integrity Programmable Power Technology which minimizes power while maximizing device performance Selectable Core Voltage available in low voltage devices L ordering code suffix enables selection of lowest power or highest performance operation Up to 16 global clocks 88 regional clocks and 116 peripheral clocks per device Up to 12 phase locked loops PLLs per device that support PLL reconfiguration clock switchover programmable bandwidth clock synthesis and dynamic phase shifting Memory interface support with dedicated DQS logic on all I O banks Support for high speed external memory interfaces including DDR DDR2 DDR3 SDRAM RLDRAM QDR II and QDR SRAM on up to 24 modular I O banks Up to 1 104 user I O pins arranged in 24 modular I O banks that support a wide range of industry I O standards Dynamic On Chip Termination OCT with auto calibration support on all I O banks High speed differential I O support with serializer deserializer SERDES and dynamic phase alignment DPA circuitry for 1 25 Gbps performance DN7006K10PCle 8T User Manual www dinigroup com 58 HARDWARE DESCRIPTION Support for high speed networking and communications bus standards including SPI 4 2 SFI 4 SGMII
122. er MyRecent 4 Network Places Documents Movies fpga a sof b sof c sof d sof fpga e sof f sof nts My Network File name Places Files of type Programming Files pof jam be ekp 4 Enable the Program Configure option and click Start to configure the FPGA A Process Dialog box will indicate programming progress DN7006K10PCle 8T User Manual www dinigroup com 34 PROGRAMMING CONFIGURING THE HARDWARE tan eng von as ooe Enable ISP to allow background progammng Hor H devices pns Checksum Usercode verte BEZ nmm pee e tron 00000000 SL 00000000 b Adi Fie B Change 7 Brie T Cep Ur Add Device System 20 Processing Waning A Gica Wareg Sigeressed 0 of 20 tJ EI For Help press F1 5 Verify that the FPGA DONE blue LED DS60 is enabled indicating successful configuration of the FPGA 6 Setting Up the Clock Frequencies This section lists detailed instructions for programming and configuring the clock sources on the DN7006K10PCie 8T Logic Emulation Board Before configuring the clocks ensure that the USBC
123. erator is used on the motherboard for each daughter card bank to keep Vecio pin on the FPGA within its recommended operating range The Daughter Card drives Voco to the required level for the particular IO standard The Voco impressed by the Daughter Card needs to satisfy the Vi of the FPGA on the host board are four Adjustable Linear Power Supplies 086 092 U84 and 085 the DN7006K10PClIe 8T per daughter catd header refer to Figure 47 Refer to the datasheet for the L T1963A from Linear Technology on how to adjust the output voltages R83 allows the user to remove the powers supply if a Veco of 3 3V is required since that voltage can be supplied the system P2 5VD P3 3VD o R85 R86 DNI oR R83 RESC2012N RESC2012N DNI DCDO DNI RESC2012N 4 086 C774 C773 0775 P3 3REGDCDO 8 1 4JuF IN OUT 5 SHDN C836 C837 4 7uF 4 7uF 3 2 2 GND1 4 REGDCDOBY E C755 1000pF 94 7 GND3 ADJ 2 REGDCDOADJ 2 2 1 22V LT1963CS8 R71 SOIC127P600 8N 4 7K Figure 47 Vcao Adjustable Linear Power Supply x4 17 3 3 Power Supply Vecpp 15 either 2 5V 3 0V or 3 3V For a 3 3V IO standard 3 3V For 3 0 IO standard 3 0 For 2 5V and below IO standards 2 5V Using these power pins to supply the pre driver power
124. gnals D 7 0 RDY 1 0 GPIF CTI 1 0 SCL SDA Interface to the CompactFlash Data Bus CF D O 7 Control Signals CFA 2 0 CD 2 1 CF INTRQ IORDY CF 5168 CF CS 1 0 2 SELZ CF CSELZ CF RESET IOWRZ IORDZ WE CF PDIAGZ POWER ON Banked Address to the SRAM Flash Upper Address Signals CFPGA_A 13 19 FPGA Configuration SelectMAP Signals Configuration Clock FPGA F A _CCLK Data Bus SELECTMAP D 7 0 Control Signals FPGA F A DONE FPGAJF A NSTATUS INIT ERR FPGA F A CSn RDWRn RSTn F A 8 2 0 FPGA Configuration JTAG JTAG Signals JTAG_FPGA_TCK JTAG FPGA TDI TMS SRAM Signals SRAM 5 MEM Flash Signals Flash_CS lash WDR Flash_RY BY Clock Multiplier Signals Control Signals SYNTH_SCL_ALL SYNTH_SDA_ALL _ 11 0 523 SYNTH_EXT 1 0 _S 1 0 SYNTH_EXT 1 0 CLKSEL SYNTH EXT 1 0 PLLSEL SYNTH EXT MR Clock Input Select Signals MUX_FPGA_CLK 2 0 MainBus Signals Clock Signals 48 FB P N DN7006K10PCle 8T User Manual www dinigroup com 64 HARDWARE DESCRIPTION
125. guration is complete and initialization of the device can begin DONE pin drives an N MOSFET and turns ON a blue LED when the DONE pin goes high Table 24 describes the DONE LED and its associated pin assignment on the FPGAs Table 24 FPGA DONE LED Signal Name FPGA Pin LED FPGAA DONE 26 21 0560 FPGAB DONE U37 AU38 0580 FPGAC DONE U56 AU38 05108 FPGAD DONE U25 AU38 0545 FPGAE DONE U36 AU38 0573 FPGAF DONE U55 AU38 0586 DONE U20 AB21 0524 FPGAQ DONE U24 K11 0544 6 3 Ethernet LED s Two Gigabit Ethernet Single Port MagJacks 11 2 from Bel Fuse contains two LED s that is controlled by the Ethernet PHY s connected to FPGA D and Table DN7006K10PCle 8T User Manual www dinigroup com 117 HARDWARE DESCRIPTION 26 describes the Ethernet LED s See the 1 5 8607 10 100 1000BASE T PHY with RGMII MAC Interface datasheet for more information on driving the LED s using the Simple Method or Enhanced Method Table 25 Power Supply Status LED s Signal Name Source Pin LED ETHD_ACT T1 13 LED1 ETHD_LINK1000 T1 15 LED2 ETHD LINK100 0518 12 13 LED1 ETHF LINK1000 12 15 LED2 ETHF LINK100 05114 6 4 Power Supply Status LED s The LT6700 1 is configured as a simple window comparator to monitor the power supplies A Power FAULT will be indicated by the SYS_RSTn signal going active LOW and turning o
126. hen reconnects USB to the MCU www dinigroup com 30 PROGRAMMING CONFIGURING THE HARDWARE 4 Configuring an FPGA H W using USBController This section lists detailed instructions for programming the Altera Stratix I FPGAs using the USBController software available on the CD ROM Before configuring the FPGAs that the USBController and the USB driver software ate installed on the host computer Note This User Manual will not be updated for every revision of the USBController software so please be aware of minor differences 4 1 Setup Before configuring the FPGA ensure the following steps have been completed 1 Attach an ATX Power Supply to the PCIe Power Header J7 on the DN7006K10PCIe 8T Logic Emulation Board using the PCle Graphics Power adaptor cable 2 Connect the USB Cable to the USB header J3 on the DN7006K10PClIe 8T 3 Dower up the board by turning ON the ATX power supply and verify the Power ON LED 0525 is ON indicating the presence of 12V located at the bottom left of the PCB by the PCIe edge connector 4 2 Configuring the FPGA To configure the Stratix III FPGAs perform the following steps 1 Open USBController and verify that the board was correctly identified as DN7006K10PCIE8T in the log window DN7006K10PCle 8T User Manual www dinigroup com 31 PROGRAMMING CONFIGURING THE HARDWARE DiNi Products USB Controller Edit FPGA Configuration FPGA
127. igFPGA DN7006K10PCIE8T and open the PROM file prom_fpl mcs gt 4 Right click XC18V04 device and select Program Click to program the PROM A Process Dialog box will indicate programming progress DN7006K10PCle 8T User Manual www dinigroup com 41 PROGRAMMING CONFIGURING THE HARDWARE iMPACT C Xilinx92i default ipf Boundary Scan BEE Elle Edit View Operations Output Debug Window Help XDN BRIG 22430 Flo GalBoundary Scan alSlaveSerial SalSeleciMAP alDesktop Configuration abDirect SPI Configuration E SystemACE xc3s1000 xc18v04 8 PROM File Formatter bypass prom flp mcs Right click device to select operations perations Boundary Scan Loading file E Config_Section_Code ConfigFPGA DNSOOOK1OPCIEST prom flp mcs done BATCH CMD set ttribute position 2 attr packageName value null i Enor Waming Transcript Configuration Platform Cable USB 6 MHz usb hs 5 Power cycle the DN7006K10PClIe 8T and verify that the CFG DONE blue LED 0524 is enabled indicating successful configuration of the 7 4 3 Using AEtest USB If you do not have cable you will need to use the following instructions to update your Spartan PROM firmware This update is depending AEtest USB and Flash firmwate version Please double check with us support din
128. igroup com to make sure that your current version MCU version AEtest USB supports this option and request xsvf file from us 1 Run aeusb wdm exe or aeusb linux from file location CUST CD NUSB Software Applications aetest usb and press any key to continue DN7006K10PCle 8T User Manual www dinigroup com 42 PROGRAMMING CONFIGURING THE HARDWARE _ ASIC Emulator USB Controller Driver v61 Compiled on Jun 24 2008 at 12 49 38 USB Menu MainBus Menu FPGA Configuration Menu Change Current Device Read Board Temperatures Read Clock Frequencies A Read Clock Frequencies D m Set Board Level Clocks Interconnect Test Menu Production Tests Menu Quit Please select option 2 Select option 3 FPGA Configuration Menu _wdm exe ASIC Emulator Flash Boot 61 Display Flash Version Check FPGA configuration status Configure FPGA via smartmedia Configure FPGA individually via USB Configure FPGA from configuration file Set PowerPC RS232 Multiplexing Clear All FPGAs Read PowerPC RS232 Multiplexing Load UST Prom with filename hex Toggle Sanity Check Main Menu 9 gt Quit Please select option 3 In the Flash Boot Menu please select option 9 Note the option menu is not displayed for security purposes 4 Select and enter the full path filename for the xsvf file 5 Verbose level is O The higher verbose level the slo
129. igure 41 MainBus Figure 42 Low Voltage Comparator Circuit Figure 43 PCIe Edge Connector Figure 44 ATX Power Supply Figure 45 External Power Connection Figure 46 Daughter Card Header Bank Pin Assignments Figure 47 Vccio Adjustable Linear Power Supply x4 Figure 48 VCCPD Voltage Select Circuit Figure 49 Daughter Card Header Power amp RESET List of Tables e 2 Main txt Command List e 3 Stratix III Configuration Schemes 4 HyperTerminal Main Menu Options e 5 FPGA configuration file size e 6 Connection between the CF connector and the Configuration e 7 Stratix III JTAG connection to Configuration e 8 Stratix III Configuration Schemes e 9 Clock Multiplier Frequency Parameters e 10 Connections between FPGAs and Clock Multipliers e 11 Connections between FPGAs and External Daughter Card amp Clock e 12 Connections between FPGAs and Secondary DC Header Clocks e 13 Connection between FPGA and PCIe Reference Clock Buffer 14 Connection between FPGA and Main Bus Clock Buffers 15 Connection between Stratix III FPGAs and External SMA Connectors 16 Connection between Stratix III FPGAs and External Test Points e 17 DDR2 Termination e 18 Serial Presence Detect
130. ing of the device to be based on a clock that is delayed 2ns from the clock on the external TX_CLK and CLK pins This makes synchronous operation of the interface possible The traces that connect the Ethernet PHYs to the FPGAs are all routed as match length 9 1 4 Ethernet Circuit The hardware implementation for FPGA D is shown in Figure 33 Please refer to the VSC8601 10 100 1000BASE T PHY with RGMII MAC Interface datasheet more information 115mA Pi2V D Paavo Y Paavo 450mA g nans 453R cis Cia Cla Sur r r BE 0 5 ATUF E cda ci iar 4 7uF 038 PL2V Dr 058 1000pF O uF 0 1uF I GREEN Z E 7 ege 3 27502707 578 42 ETHD AGT E si 2 333 acm 27 ETHD LINKTOUT gans mmo Ue 8 dria ETHD UINKTUD eiii Tuc 8 JH 13pF 8 18 4 139F s 47K 53 mpa 01 J 8 3D io CLKI25 49 osceN cukouT eves HS H22 Teer
131. ion Board 1 Introduction The Dini Group developed the CompactFlash Configuration Environment to address the need for a space efficient pre engineered high density configuration solution for systems with single or multiple FPGAs The technology is a groundbreaking in system programmable configuration solution that provides substantial savings in development effort and cost per bit over traditional PROM and embedded solutions for high capacity systems devices are configured by loading application specific configuration data the bitstream into internal memory On the DN7006K10PCle 8T this can be accomplished via the CompactFlash PCIe or USB interface using Fast Passive parallel FPP configuration option Because Altera FPGA configuration memory is volatile it must be configured each time it is powered up The bitstream is loaded into the device through special configuration pins These configuration pins serve as the interface for number of different configuration modes the following are supported on this board e Fast Passive Parallel FPP Fast Passive Parallel FPP with design security feature and or decompression enabled JTAG Boundaty Scan configuration mode DN7006K10PCle 8T User Manual www dinigroup com 23 PROGRAMMING CONFIGURING THE HARDWARE Remote Slave SelectMAP parallel configuration mode x8 using the Mictor interface used to configure daughter cards using seleccMAP
132. ircuit FPGA A External clock test point circuit for is shown see Figure 24 Refer to the Altera Stratix Device Handbook for IO levels Figure 24 External Clock Test Point Circuit 4 8 2 Connection between 111 FPGAs and External Test Points connection between the Stratix III FPGAs and the external Test Points are shown in Table 16 Table 16 Connection between Stratix III FPGAs and External Test Points Signal Name FPGA Pin Test Point TPN U26 AY22 TP48 2 CLK A TPP U26 AW22 TP48 1 CLK B TPN U37 AY22 TP82 2 DN7006K10PCle 8T User Manual www dinigroup com 89 HARDWARE DESCRIPTION Signal Name FPGA Pin Test Point CLK B 37 AW22 CLK_C_TPN 56 C22 CLK_C_TPP 56 D22 CLK_D_TPN 25 AY1 CLK_D_TPP 25 2 TPN 36 AY22 36 AW22 CLK F TPN 55 C1 U U U U U U U U U CLK TPP 55 C2 5 Memory This section describes the on board memory interfaces and provides signal name type and signal connectivity relative to the Stratix III devices The Dini Group also provides a number of SODIMM Daughter Cards that can be used in the SODIMM locations DDR2 SDRAM SODIMM Serial Flash 5 1 DDR2 SDRAM SODIMM The DN7006K10PCle 8T supports four 64 bit 200 SODIMM modules connected to the Stratix III FPGAs A C D and and allow addressing for up to 4GB DDR2 SDRAM PC2 4200 PC2 53
133. is provided by the 1Mb 8 Flash 071 To eliminate bus contention the device has separate Chip Enable Flash 58 Write Enable and Output Enable OE controls Device programming occurs by executing the program command sequence Address space above 2000H is banked through the Configuration The Flash interface is shown in Figure 8 DN7006K10PCle 8T User Manual www dinigroup com 61 HARDWARE DESCRIPTION FLASH MCU A1 25 2 24 DQO 23 bat 4 25 ea 5 21 20 d A7 19 MCU A8 18 x e 9 8 A10 7 9 6 21 A12 5 CFPGA A13 4 pan 14 3 A15 2 4 bus CFPGA A16 1 CFPGA A17 48 RTS CFPGA A18 17 CFPGA A19 16 9 BYTE FLASH 58 26 m s MEM 28 MEM WR 11 3 NONE FLASH 15 RY BY NC YS GND SYS MCU 12 AM29LV800B SOPT50X2000 48N Figure 8 MCU Flash 3 1 4 MCU USB 2 0 Interface Communication with the system is via the USB connector J3 which interfaces directly with the MCU The USB interface connector is a type B receptacle as shown in Figure 9 R326 8 25K VB M A USB VBUS MCU USB VBUS USB D 5 4058 SHLD GND SHIELD GND SHIELD 67068 1000 USB TYPE B 52 R301 OR DNI SOT23 3N Figure 9 USB Con
134. is website You can also directly access these resources using the provided URLs Resource Description URL User Manual This is the main source of technical information The manual should contain most of the answers to your questions Demonstration MEG Array Daughter Card header insertion and removal video Videos Dini Group The web page will contain the latest user manual application notes Web Site FAQ articles and any device errata and manual addenda Please visit and bookmark http www dinigroup com Data Book Pages from Stratix I Databook which contains device specific information on Altera device characteristics E Mail You may direct questions and feedback to the Dini Group using this e mail address support dinigroup com Phone Support Call us at 858 454 3419 during the hours of 8 00am to 5 00pm Pacific Time FAQ The download section of the web page may contain a document called DN7006K10PCIe 8T Frequently Asked Questions FAQ This document is periodically updated with information that may not be in the User s Manual DN7006K10PCle 8T User Manual www dinigroup com 5 GETTING STARTED Chapter Getting Started Congratulations on your purchase of the DN7006K10PCIe ST Stratix III Logic Emulation Board The remainder of this chapter describes how to start using the DN7006K10PCIe 8T Logic Emulation Board j Before You Begin 1 1 Configuring the Programmable Components
135. l Name FPGA Pin SODIMM Pin DIMM DIMMD WEN U25 AW26 SODIMM F 39 FPGA 055 DIMMF_AO MM DN7006K10PCle 8T User Manual www dinigroup com 108 HARDWARE DESCRIPTION sm D D D 55 24 55 C26 55 D26 55 D10 55 E10 55 M23 55 M22 55 A23 IMMF gt DIMMF DM2 55 D16 22 55 28 e DN7006K10PCle 8T User Manual www dinigroup com 109 Ct pc 55 25 55 25 55 G18 55 F17 alo HARDWARE DESCRIPTION I a I B I 2 I 1 I DIMM DIMM DIMM DIMM DIMMF_DQ31 DIMM DIMM DIMM DIMM MM MM MM MM MM MM MMF_DQ32 ct eS req c e 55 16 55 16 55 F23 55 617 55 16 55 516 55 A17 55 20 55 20 55 18 55 19 55 G19 55 F19 55 24 55 A19 55 19 55 119 55 K19 55 D19 55 D18 55 118 55 K18 55 18 55 E19 55 F24 55 M16 55 M17 55 11 55 810 DN7006K10PCle 8T User Manual SODIMM Pin 139 55 139 57 139 17 139 44 139 46 1 139 76 189 123 189 125 189 135 189 137 139 124 189 126 139 134 139 136 139 141 Go EN 39 143 189 151 189 153 www dinigroup com 110 HARDWARE DESCRIPTION I DIMMF_DQ48 55 E15 c
136. le to be used for configuration as well as options for the configuration process However a user can put several files that follow the format for main txt on the CompactFlash card that contain different options for the configuration process By selecting the main menu option 4 the user can select a file from a list of files that can be used in place of main txt If the power is turned off or the reset button S2 is pressed the configuration file is changed back to the default main txt List files on SmartMedia This option prints out a list of all the files found on the CompactFlash card Display Smart Media TXT File This option allows the user to list the contents of any text file on the CompactFlash card Change RS232 PPC Ports This option is not implemented The next 5 options are only available if the FPGAs ate configured with The Dini Group reference design Please see Appendix A for FPGA Address Maps 5 Display Temperatures Displays the current StratixIII FPGA temperatures Set FPGA Temperature Alarm Threshold Allows the user to change the temperature threshold Read Temperature Sensor Reg Allows the use to read the temperature sensor registers directly Write Temperature Sensor Reg Allows the use to write the temperature sensor registers directly Disconnect Reconnect USB DN7006K10PCle 8T User Manual Disconnect and t
137. lock Buffer U30 and a LVDS clock buffer U31 The second input port on the Zero Delay Clock Buffer U30 is used to buffer the global clock signal from Daughter Card D CLK_DCDp n Capacitors C1273 C1270 allows for AC coupling refer to Figure 18 J14 15 are Amphenol SMA jacks P N 901 144 8REX with an impedance rating of 50Q Refer to the Altera Stratix Device Handbook for IO levels P3 3VD o R844 C163 C177 5 11R 4 7uF P3 3VD 1 61275 030 4 7uF 9 28 R833 8825 212 5 VDD1 1 55 1008 1008 43 8 SYNTH o VDD2 VDDO2 16 H836 1 VDDO3 15 3 2077 pg30 CLK DCDp 5 CLKO pg30 d Qo 8 5 CLK USERpc CLK USERp 5 18 _ 1 CLK_USERnc TLK_USERN 6 Qi 37 4 CLK EXTO MBp 941 I S 1 nCLK1 21 CLK EXTO MBn pg4i 5 1270 7 02 739 X 57 DNI 1 SYNTH EXTO CLKSEL 1 CLKSEL nQ2 2 X Ps d 5 SINE 2 SELO 03 1 RB24 SYNTH EXTO 51 27 SEL TP 901 144 8RFX R832 100R Esmee 1 29 582 Q4 26 K EXTON 100R SEL3 04 ao SYNTH EXTO PLLSEL 1 SEL E pg5 SYNTH EXT MR 13 GND1 CLK EXTO FBj FB IN GND2 5
138. ltera FPGA configuration memory is volatile it must be configured each time it is powered up The bitstream is loaded into the device through special configuration pins These configuration pins serve as the interface for number of different configuration modes the following are supported on this board Fast Passive Parallel FPP Fast Passive Parallel FPP with design security feature and or decompression enabled JTAG Boundaty Scan configuration mode Remote Slave parallel configuration mode x8 using the Mictor interface used to configure daughter cards using select MAP DN7006K10PCle 8T User Manual www dinigroup com 59 HARDWARE DESCRIPTION The JTAG Boundary Scan configuration interface is always available regardless of the Mode pin settings The JTAG Boundaty Scan configuration mode disables all other configuration modes to prevent conflicts between configuration interfaces Certain configuration pins are dedicated to configuration while others are dual purpose see datasheet Dual purpose pins serve both as configuration pins and as user I O after configuration Dedicated configuration pins retain their function after configuration The remainder of this section describes the functional blocks that entail the FPGA configuration environment 3 1 Micro Controller Unit MCU The Cypress CY7C68013 U72 micro controller is used to control the configuration process The MCU contains an enha
139. m 087516 E 5 3 5 C C 2 a E 5 E E awodd E ERES k 4 9x10 3 4 5 3 3 E 5 8 8 2 amp o 8 5 E 4 LE 8 257 05 305 vos 110 o g S 8 E 5 5 1 4 37101 065 1101 06 ejpeideoeu 009 Log Log Log ea 89928891 80888801 85450 wwe N39 ua4Jna N39 indu SAAT SAAT 9 x sn Figure 15 Clocking Block Diagram 71 Inigroup com www d DN7006K10PCle 8T User Manual HARDWARE DESCRIPTION The clocking structures for the DN7006K10PCIe 8T include the following features e Clock Multipliers x4 o General Clock Mulaplier 041 GO o DDR2 Clock Multiplier U54 G1 o LVDS Interconnect Clock Multiplier 047 G2 o Clock Multiplier 32 GTP Daughter Card Header Clocks o EXTSMA amp DC
140. me Four highly configurable clock multipliers 515326 provide global clock networks PCle high speed serial interface is utilized with a dedicated Xilinx Virtex 5 FPGA using the GTP Transceivers Two Ethernet ports are provided External memory to the FPGA 15 realized using a 64 bit 200 pin SODIMM PC 4200 Three 400 pin MEG Array connectors on the bottom of the printed circuit board assembly PCBA are used to interface to the Dini Group products eg DNMEG Obs Daughter Card In standalone mode DN7006K10PCle 8T receives power from an external 12V ATX power supply An RS232 interface exists to allow communication with the application LED s are used to indicate configuration status power supply presence and numerous LED S are provided for the user 2 Altera Stratix4ll FPGAs The Stratix III family provides the most architecturally advanced high performance low power FPGAs in the market place Stratix III FPGAs lower power consumption through Altera s innovative Programmable Power Technology which provides the ability to turn on the performance where needed and turn down the power consumption everywhere else Selectable Core Voltage and the latest in silicon process optimizations are also employed to deliver the industrys lowest power high performance FPGAs Specifically designed for ease of use and rapid system integration the Stratix III FPGA family offers three family variants optimized to meet different application needs
141. n the Reset LED 051 The SYS_RSTn signal can also be activated by enabling the Reset Switch 51 Table 26 desctibes the power supply status LED and their associated voltage source Table 26 Power Supply Status LED s Signal Name Source Pin P12V 17 1 2 3 PZ5VD PSU4 10 11 P3 3VD PSU13 6 P5 0V PSU1 6 P1 1V_VCC_FPGAA PSU9 5 9 P1 1V_VCC_FPGAB PSU7 5 9 P1 1V_VCC_FPGAC PSU11 5 9 P1 1V_VCC_FPGAD PSU5 5 9 P1 1V_VCC_FPGAE PSU6 5 9 P1 1V_VCC_FPGAF PSU10 5 9 P_SODIMM_A PSU3 6 P_SODIMM_C PSU4 6 P_SODIMM_D PSU2 6 P_SODIMM_F PSU12 6 DN7006K10PCle 8T User Manual www dinigroup com 118 HARDWARE DESCRIPTION Signal Name Source Pin 1 2 5 U19 1 P1 0V Q PSU8 5 9 SYS RSIn U68 8 PCIE P3 B8 6 5 Miscellaneous LED s Table 26 describes the miscellaneous status LED s and their associated soutce Table 27 Miscellaneous LED s Signal Name Source FPGA Q U24 PCIE LINK STATUS LEDs LEDQ YELLOW ACT U24 W11 LEDQ RED LOS U24 Y10 LEDQ GREEN LINK U24 AA19 LEDQ GREEN 8LINK U24 AA17 LEDQ GREEN 4LINK U24 AA18 U U U U PCIE IN PERSTn 24 H11 U26 U12 PCIE DEBUG LEDO 24 F18 PCIE DEBUG 1 1 24 H19 PCIE DEBUG LED2 24 H18 PCIE DEBUG LED3 U24 G10 CONFIG FPGA U20 USB Temp Sensor LEDS 5 20 V10 LEDS 20 U6 LEDS_HOSTACT 20 11 LEDS_PCIACT 20 AB4 LED_S_ERR_
142. nced 8051 core USB 2 0 transceiver and a Serial Interface Engine SIE The CY7C68013 provides the following features 256 bytes of register RAM three flexible Timers 2 USARTs and an integrated compatible controller The MCU interfaces to the Configuration FPGA U20 via a dedicated 8 bit bus MCU_D8 MCU_D0 and the CompactFlash interfaces to the Configuration FPGA via additional 98 bit bus CF_D7 CF_DO The six Stratix FPGAs on the board interfaces to the Configuration FPGA via an 8 bit bus SELECTMAP_D7 SELECTMAP D0 used for Fast Passive Parallel FPP configuration scheme The amount of internal SRAM is not large enough to hold the FAT needed for CompactFlash so an external 128Kb x 8 SRAM 070 was added In addition a 1Mb x 8 Flash U71 was added to store the downloaded program code An external EEPROM X1 configures the MCU during power up The micro controller has the following responsibilities e Reading the CompactFlash card via the Configuration FPGA e Communicate to the system via the USB Interface Configuring the Stratix III Pro FPGAs 6 Executing DN7006K10PCIe 8T self tests e Drive status LED s 3 1 1 MCU EEPROM Interface During the power up sequence internal logic checks the I C compatible port for the connection of an EEPROM X1 whose first byte is either or 2 If found the MCU uses the VID PID DID values in the EEPROM in place of the internally stored values of it boot loads
143. nection to Configuration FPGA Signal Name Configuration FPGA Connector U20 5 10 1 U20 K6 710 9 U20 K5 10 3 JTAG FPGA TMS U20J6 10 5 3 5 Configuration MSEL Resistors The specific configuration mode is selected by setting the appropriate level on the dedicated Mode input pins MSEL 2 0 DN7006K10PCle 8T User Manual www dinigroup com 69 HARDWARE DESCRIPTION P2 5VD Figure 14 MSEL Configuration Resistors default FPP Select the configuration scheme by driving the Stratix III device MSEL pins either HIGH or LOW as shown in Table 8 Table 8 Stratix III Configuration Schemes Configuration Mode MSEL 2 0 Configuration Resistors Fast Passive Parallel FPP 000 R524 R492 R496 Installed FPP with design Security 001 R523 R492 R496 Installed feature and or decompression enabled Do leave MSEL R524 R492 R496 Installed pins floating 4 Clock Generation 4 1 Clock Methodology The DN7006K10PCIe 8T has a flexible and configurable clocking scheme Figure 15 is a block diagram showing the clocking resources and connections All of the Global Clock Networks on the DN7006K10PCIe 8T are routed point to point using dedicated LVDS routes Since LVDS is a low voltage swing differential signal using a single ended input buffer in the FPGA will not work An example Verilog implement
144. nector 3 1 5 RS232 Interface An 5232 serial port P1 P2 is provided for low speed communication with the MCU and FPGA logic The RS 232 standard specifies output voltage levels between 5V to DN7006K10PCle 8T User Manual www dinigroup com 62 HARDWARE DESCRIPTION 15V for logical 1 and 5V to 15V for logical 0 Input must be compatible with voltages in the range of 3V to 15V for logical 1 and 3V to 15V for logical 0 This ensures data bits are read correctly even at maximum cable lengths between DTE and specified as 50 feet The RS 232 standard has two primary modes of operation Data Terminal Equipment DTE and Data Communication Equipment DCE These can be thought of as host or PC for DTE and as peripheral for DCE The DN7006K10PCIe 8T operates in the DCE mode only Figure 10 shows the implementation of the serial port on the DN7006K10PCIe 8T U60 5232 FPGA TX 7 21 RS232 FPGA TXD RS MCU TX TUN TOUT 25 85232 TXD 8 R298 2 2 RS232 FPGA RX RS232 FPGA RX 13 18 RS232 FPGA RXD 9 R290 RS232 MCU HX 12 RIOUT RIIN 717 RS232 DNI P1 R20UT 1 5 SE tout 3 x LCD P2 svD che reu EE GND 45V LC 7 8 3 RS232SHDNH 24 _ P2 5VD R291 x SHDN 9
145. ng the PCle Graphics Power adaptor cable 2 Connect the RS232 Cable to the RS232 MCU header P2 on the DN7006K10PClIe 8T this is not required but allows the user to observe the configuration process 3 2 Configuration MSEL Resistors Fast Passive Parallel FPP is the default configuration mode for DN7006K10PCIe 8T The configuration mode is selected by setting the appropriate level on the dedicated Mode input pins MSEL 2 0 on the FPGAs Figure 4 MSEL Configuration Resistors default FPP DN7006K10PCle 8T User Manual www dinigroup com 27 PROGRAMMING CONFIGURING THE HARDWARE Select the configuration scheme by driving the Stratix III device MSEL pins either HIGH or LOW as shown in Table 8 Table 3 Stratix III Configuration Schemes Configuration Mode MSEL 2 0 Configuration Resistors Fast Passive Parallel FPP 000 R524 R492 R496 Installed Factory Default FPP with design Security 001 R523 R492 R496 Installed feature and or decompression enabled Do leave MSEL R524 R492 R496 Installed pins floating 3 3 HyperTerminal Setup Connect the RS232 Serial cable to a COM port on the Host Computer and configure HyperTerminal to the following settings COM1 Properties Port Settings Bits per second Data bits Parity lor Stop bits Flow control 3 4 Configuring the FPGA To configure the 5 FPGAs perform the following s
146. nigroup com 174 HARDWARE DESCRIPTION that both the small and the large keys at the narrow ends of the headers line up BEFORE applying pressure to mate the connectors DN7006K10PCle 8T User Manual www dinigroup com 175 HARDWARE DESCRIPTION 17 7 MEG Array Specifications Manufacturer Part Number RoHS Compatible Number Of Positions Lead Free Contact Area Mating Force Unmating Force Insulation Resistance Withstanding Voltage Current Rating Contact Resistance Temperature Range Trademark Approvals and Certification Product Specification Pick up Cap Housing Material Contact Material Durability Mating Cycles DN7006K10PCle 8T User Manual FCI 84520 102LF Bottom Plug P4 P5 P6 yes 400 0 76 um 30 pin gold over 0 76 um 30 pin nickel 30 grams per contact average 20 grams per contact average 1000 M ohms 200 VAC 0 45 amps 20 to 25 m ohms max initial 10 m ohms max increase after testing 40 C to 85 C UL and CSA GSe 12 100 from FCI websit yes LCP Copper Alloy 50 www dinigroup com 176 HARDWARE DESCRIPTION 18 Mechanical 18 1 Board Dimensions The DN7006K10PCIe 8T Logic Emulation Board measures approximately 250mm 336mm This exceeds the PCI Express Specification for a Standard size card Two bus bars MP1 and MP2 are installed to prevent flexing of the PWB They are conne
147. ntents Before using the kit or installing the software be sure to check the contents of the kit and inspect the board to verify that you received all of the items If any of these items are missing contact The Dini Group before you proceed The DN7006K10PClIe 8T Logic Emulation Board kit includes the following 256 CompactFLASH Card e USB FLASH Memory Card Reader e USB 2 0 Cable RS232 089 to IDC Header Cable RS232 Serial Cable 6ft F F 6 Pin PSU Adaptor for PCIe Video Cards Daughter Card Mounting Hardware Screw Machine M3x5mm x8 o Nut HEX x8 Spacer CD ROM containing o USB Application Program usbcontroller exe o PCIe Program aetest exe o Stratix III Reference Designs Verilog o User Manual pdf format Schematic pdf format o Component Datasheets pdf format Optional items that support development efforts not provided DN7006K10PCle 8T User Manual www dinigroup com 4 INTRODUCTION Altera Quartus II Software Y Altera USB Blaster Download Cable DDR2 SODIMMs Available upon request 4 Inspect the Board Place the board on an anti static surface and inspect it to ensure that it has not been damaged during shipment Verify that all components are on the board and appear intact 5 Additional Information For additional information please visit http www dinigroup com The following table lists some of the resources you can access from th
148. onnector J3 Ensure the USB Controller driver has been installed 3 If the kit contains Memory SODIMMs populate the SODIMM sockets J8 19 J39 and J40 with the required modules Do not insert the SODIMM module with the board powered 3 2 Powering Up the Board Power up the board by turning ON the ATX power supply and verify the Power ON LED 0525 is ON indicating the presence of 12 located at the bottom left of the PCB by the PCIe edge connector DN7006K10PCle 8T User Manual www dinigroup com 12 GETTING STARTED 4 Running the One SHOT Test The Dini Group provides USB Controller application the CD ROM 5 Software Applications NUSBController USBController exe 1 Open USBController exe and verify that the board was correctly identified as a DN7006K10PCIE8T in the log window DiNi Products USB Controller File Edit FPGA Configuration FPGA Reference Design Mainbus SettingsfInfo Production Tests Service Refresh Enable USB gt FPGA Scroll Log DN7006k10PCIEST communication is disabled Enable if you want to use reference design features Sekrat menu is now on 2 Click on Production Tests button and select the One Shot Test option Configure the Shot Test as follows ensute that the path to the bitfiles are correct DN7006K10PCle 8T User Manual www dinigroup com 13 GETTING STARTED One Shot Test Dialog This will test Main
149. ontroller and the USB driver software are installed on the host computer Note This User Manual will not be updated for every revision of the USBController software so please be aware of minor differences 6 1 Setup Before configuring the clock sources ensure the following steps have been completed 1 Attach ATX Power Supply to the PCIe Power Header J7 on DN7006K10PCIe 8T Logic Emulation Board using the PCle Graphics Power adaptor cable 2 Connect the USB Cable to the USB header J3 on the DN7006K10PClIe 8T 3 Power up the board by turning ON the ATX power supply and verify the Power ON LED 0525 is ON indicating the presence of 12V located at the bottom left of the PCB by the PCIe edge connector DN7006K10PCle 8T User Manual www dinigroup com 35 PROGRAMMING CONFIGURING THE HARDWARE 6 2 Configuring the Clock Multipliers using USBController To configure the clock multipliers perform the following steps 1 Open USBController and verify that the board was correctly identified as a DN7006K10PCIE8T in the log window DiNi Products USB Controller Clear Log Scroll Log BOARD TYPE DN7006k10PCIEST USB to FPG communication is disabled Enable if you want to use reference design features 2 Click Settings Info followed by Setup Clock Frequencies and select the clock source that needs to be configured See par 4 2 Stratix III FPGA Clocking Resources F
150. peration Elapsed time 41 sec Transcript Output Enar Warming Configuration Platform Cable LISB 6 MHz usb hs 7 Power cycle DN7006K10PCle 8T and verify that the DONE blue LED 0524 is enabled indicating successful configuration of the FPGA 7 7 5 Configuring the PCle FPGA PROM using main txt To configure the PCle FPGA using main txt on the CompactFlash card refer to Configuring an FPGA using main txt in this User Manual Add a line to the main txt file FPGA bitfilename bit DN7006K10PCle 8T User Manual www dinigroup com 54 HARDWARE DESCRIPTION Chapter Hardware Description This chapter describes the hanbvare features of the DIN7OO6K10PCle8T Logic Emulation Board 1 Overview The DN7006K10PCIe 8T Logic Emulation Board provides for a comprehensive collection of peripherals to use in creating a system around the Altera Stratix HI FPGA A high level block diagram of the DN7006K10PCIe 8T Logic Emulation Board is shown in Figure 5 followed by a brief description of each section DN7006K10PCle 8T User Manual www dinigroup com 55 HARDWARE DESCRIPTION DDR2 SODIMM 4GB Max 0082 SODIMM 468 Max 8 45 05 ZN39 8 8 49 IN39 aw 9 jurodpua ssaidx3 294 092133 075158 xnens 092133 076156 5 092133 075158 xnens 092144 076156
151. plication for interfacing between USB Enabled Dini Group products and a host system It allows the user to program the boatd s FPGAs access global memory registers read and program clocks run tests and more USBController can be used to run vatious production tests on the boards to ensure that they are working properly It can also be used for setting up board features ie when running a custom design etc All USBController source code is included on the CD ROM shipped with the DN7006K10PCIe 8T Logic Emulation Kit The USBController application contains the following functionality DN7006K10PCle 8T User Manual Configure FPGA s over USB Configure FPGA s via CompactFLASH Clear FPGA s Reconfigure FPGA s Reset FPGA s Read Write to from MainBus Address Space Retrieve Board MCU Spartan Version Serial Number www dinigroup com 16 INTRODUCTION TO THE SOFTWARE TOOLS Read FPGA Temperatures Setup Clock Frequencies Update Firmware MCU and Spartan Run Production Tests 1 1 System Requirements USB Controller can be installed on Windows 2000 XP system with USB 2 0 capability 1 2 Getting Started with USBController Once USBController is installed DN7006K10PCle 8T is powered ON and the USB cable is plugged in the user can open USBController The USBController application should immediately find the DN7006K10PCIe 8T If USBController does not find the DN7006K10PCIe 8T
152. r for applications requiring sub 1 ps jitter performance The 515326 accepts dual clock inputs ranging from 2 kHz to 710 MHz and generates two clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1 4 GHz The two outputs are divided down separately from a DN7006K10PCle 8T User Manual www dinigroup com HARDWARE DESCRIPTION common source The device provides virtually any frequency translation combination across this operating range The 515326 input clock frequency and clock multiplication ratio are programmable through an 12 or SPI interface configured for 120 The 515326 is based on Silicon Laboratories 3td generation DSPLL technology which provides any rate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components The DSPLL loop bandwidth is digitally programmable providing jitter performance optimization at the application level Please refer to the Any rate Precision Clocks 512316 525322 512323 472325 515326 512362 572306 512367 512368 Family Reference Manual from Silicon Laboratories for the 515326 for programming information 4 3 4 General Clock Multiplier U41 GO One of the outputs of the Clock Multiplier 041 is buffered 043 and distributed as general reference clock for the FPGAs while the o
153. requency Modifier For which clock do you want to modif Frequency 28 62 REF 3 Enter the desired clock output frequency in MHZ DN7006K10PCle 8T User Manual www dinigroup com 36 PROGRAMMING CONFIGURING THE HARDWARE Enter output frequency Enter Frequency in Mhz 100 4 Ensure the clock was set to 100 MHz in the GUI log window 6 3 Selecting a Clock Source using USBController To select an external source to drive a global clock multiplier perform the following steps 1 Open USBController and verify that the board was correctly identified as a DN7006K10PCIE8T in the log window DiNi Products USB Controller Clear Log Scroll Log BOARD TYPE DN 7006k10PCIE8T USB to FPGA communication is disabled Enable if you want to use reference design features 2 Click Settings Info followed by Global Clock Muxes Setup and select the clock source See par 4 2 Stratix III FPGA Clocking Resources DN7006K10PCle 8T User Manual www dinigroup com 37 PROGRAMMING CONFIGURING THE HARDWARE DN7006k10PCIEBT Clock Muxes Setup Unchanged Synthesizer Step Clock Config Register bit 2 Unchanged Synthesizer Step Clock Config Register OxDF23 bit 1 Unchanged Synthesizer Unchanged C sma C Daughtercard EXT 1 Unchanged C Daughtercard B top C Daughtercard B bottom Cancel 3 Ensure clock was set
154. s Set Board Level Clocks Interconnect Test Menu Production Tests Menu Quit A C D F Please select option ASIC Emulator EEPROM Boot v61 Display Flash Version Update EEPROM from lt filename gt iic file Update Flash from lt firmware gt hex file Update 15326 Register values Boot From Flash Main Menu 9 Quit Please select option DN7006K10PCle 8T User Manual www dinigroup com 46 PROGRAMMING CONFIGURING THE HARDWARE 4 Please select option 2 Update Flash from lt firmware gt hex file and enter the name of the file including the path This process should take approximately 2 minutes to execute D DiniProducts AETEST_USB aetest_usb aeusb_wdm exe ASIC Emulator EEPROM Boot v61 Display Flash Version Update EEPROM from lt filename gt iic file Update Flash from lt firmware gt hex file Update 15326 Register values Boot From Flash Main Menu 9 gt Quit Please select option 2 Please enter filename 5 When the execution is finished power cycle the board Note Using the command line aeusb_wdm_cmd exe Flash lt filename hex gt aeusb linux cmd exe Flash lt gt 7 7 PCle FPGA Q and SPI Serial Flash To configure the PCI Express FPGA also referred to as 5 FPGA Q and LX50T the following options ate provided Configuring the PCle FPGA using USBController Configuring the PCIe FPG
155. stem Operation The primary source of power for the DN7006K10PCIe 8T is the PCI Express graphics power connector All other voltages on the board are generated from this supply During In System operation DN7006K10PClIe 8T be powered from the PCI Express Edge Connector however the board will exceed the available power from the system fuse F5 needs to be installed for this option to be available see Figure 43 DN7006K10PCle 8T User Manual www dinigroup com 146 HARDWARE DESCRIPTION F5 DNI FUSE 0429 8477 PCIE LED DS26 RED 453R P12V_PCIE F4 DNI FUSE 0429 P3 3V PCIE PCIE WAKEnr R42 PCIE_WAKEn DNI B13 B14 PCIE_PRSNTn1 B18 PCIE PETnOr PCIE PETpir B19 Ti nir PCIE 2 PCTE PETn2r PCIE PETp3r PCIE PETn3r 031 OD 00 00 UJ 00 00 OD 00 00 QDI DO PCIE PRSNTn4 B31 B32 PCIE_PETp4r B33 PETn4r PCIE PETp5r PCIE 5 PCIE PCIE PETp7r PCIE PETn7r 00 05 00 00 05 00 00 09 Co 5 Ch A Go 0 0114 B47 PCIE_PRSNTn8 B49 WAKE GND PETRO GND PRSNT2 GND 1 1 GND GND PETp2 2 GND GND PETp3 PETn3 GND RSVD PRSNT 2 GND PETp4 PETn4 ra PETn6 GND GND PETp7 7 GND 2
156. sure the board is in Update Mode 2 Run aeusb_wdm exe aeusb linux from file location CUST CD NUSB Software Applications aetest usb and press any key to continue D WiniProducts AETEST_USB aetest_usb aeusb_wdm exe ASIC Emulator USB Controller Driver v61 Compiled on Jun 24 2668 12 49 38 USB Menu MainBus Menu Firmware Menu Cbooted from eeprom Change Current Device Read Board Temperatures Read Clock Frequencies A C Read Clock Frequencies Set Board Level Clocks Interconnect Test Menu Production Tests Menu Quit Please select option 3 Select option 3 FPGA Configuration Menu DN7006K10PCle 8T User Manual www dinigroup com 44 PROGRAMMING CONFIGURING THE HARDWARE ASIC Emulator EEPROM Boot v61 Display Flash Version Update EEPROM from lt filename gt iic file Update Flash from lt file Update 15326 Register values Boot From Flash Main Menu 9 Quit Please select option 4 Select option 1 Update EEPROM from lt filename gt iic file and enter the name of the file including the path This process should take approximately 2 minutes to execute ASIC Emulator EEPROM Boot v61 Display Flash Version Update EEPROM from lt filename gt iic file Update Flash from lt firmware gt hex file Update 15326 Register values Boot From Flash Main Menu 9 gt Quit Please select option
157. t Points 89 5 MEMORY niet O 90 51 DDR2 SDRAM SODIMM 90 5 1 1 DDRZ Terminatioi 90 5 12 Vpr switching Power Supply P SODIMM 3 93 5 1 3 VTT Linear Power Supply PO 9V VTT T 5 1 4 Serial Presence Detect a NE EH et ta e eee Pr ieri 5 1 5 Clocking Connections between Stratix III FPGAs and DDR2 SDRAM SODIMMS 94 5 1 6 SODIMM connections to the Stratix III FPGAs 5 517 DORZ PCB Trace Lenss 3 2 NAP E 352 4 Connections between Stratix III FPGAs and Serial Flash 6 LED INDICATORS 114 6 1 User LED Ss associe 115 6 2 Configuration DONE eicit e EO RERO PEU ERR EUH PEERS 117 6 3 B H DE ENA E IEA O AOE EEEE 117 6 4 Power Supply Status LED s 23 6 5 Miscellanegus LEDY pc 119 7 ES 120 7 1 1 RS232 Circuit 120 7 1 2 Connections between FPGAs and RS232 Port 121 8 TEMPERATURE 8 50 5 121 8 1 1 MEDICO T E 121 8 1 2 Connection between FPGAs and Temperature 5 0506 122 9 ETHERNET PHYS 9 1 Ethernet Interface E
158. teps 1 Insert the CompactFlash card into the CompactFlash socket 5 DN7006K10PCle 8T User Manual www dinigroup com 28 PROGRAMMING CONFIGURING THE HARDWARE 2 Open a HyperTerminal Window on the Host Computer 3 Power up the board by turning ON the ATX power supply and verify the Power ON LED 0525 is ON indicating the presence of 12V located at the bottom left of the PCB by the PCIe edge connector 4 Monitor the configuration process in the HyperTerminal window DN7006K10PCle 8 File Edit View Cal Transfer Help 28 FPGAS STUFFED 16RESETTING CF DONE CONFIGURRTION FILES FPGR 8 FPGR R RBF FPGA B FPGR B RBF FPGA D FPGR D RBF FPGA E FPGR E RBF FPGR F FPGR F RBF PTIONS Message level set to default 2 Sanity check is set to default CONFIGURING Sanity check passed lt gt Connected 0 01 40 Auto detect 19200 8 N 1 5 After successful configuration process DN7006K10PCIe 8T Main will be displayed DN7006K10PCle 8 mj File Edit View Call Transfer Help MAIN MENU MCU v57 CONFIG v3D SERIAL 0806015 Configure FPGAs using MAIN TXT Interactive configuration menu Check configuration status Chang
159. ter card Section 1 of 6 MEG Array 400 Stratix 3 Figure 49 Daughter Card Header Power amp RESET The RST DCDn signal is routed from the Configuration FPGA 020 an open drain buffer U76 and can be used as a RESET to the Daughter Catd refer to Table 37 Table 37 Daughter Card Reset Signal Name OD Buffer Daughter Card Header RST DCDn U76 7 4 2 RST DCEn U76 5 5 2 RST_DCFn U76 2 2 17 5 FPGA to Daughter Card Header IO Connections Table 38 lists the input output interconnect between the Stratix III FPGAs and the daughter card headers DN7006K10PCle 8T User Manual www dinigroup com 153 HARDWARE DESCRIPTION Table 38 FPGA to Daughter Card Header IO Connections SIGNAL Receptacle Bottom FPGA DCDONRXO 25 15 DCDONRX5 25 1 DCDONRX6 25 573 DCDONRX7 25 Y3 DCDONRX8 25 4 DCDONRX9 25 11 DCDONTXO 25 12 DCDONTX1 25011 DCDONTX10 25 11 DCDONTX11 25 06 DCDONTX2 25 V9 DCDONTX3 25 579 EX pcm Dc EE DN7006K10PCle 8T User Manual www dinigroup com 154 GI eee Se 1 e U Ge Er EE ci HARDWARE DESCRIPTION SIGNAL Receptacle Bottom Depos coii DCDOPRX10 P4 E13 DCDOPRX11 GCA DCDOPRX2 DCDOPRX3 DCDOPRX4 DCDOPRX5 DCDOPRX6 DCDOPRX7 DCDOPRX8 DCDOPRX9 DCDOPTXO DCDOPTX1 DCDOPTX10 DCDOPTX11 DCDOPTX2 DCDOPTX3 DCDOPTX4 DCDOPTX5 DCDOPTX6 DCDOPTX7 DCDOPTX8 DC
160. the EEPROM contents into internal RAM 0 2 The EEPROM interface is shown in Figure 6 DN7006K10PCle 8T User Manual www dinigroup com 60 HARDWARE DESCRIPTION R369 4 7 24LC64 SOCKE DIP8 SDA pg7 SCL MCU Figure 6 MCU EEPROM Interface 3 1 2 MCU SRAM External Memory expansion for the MCU is provided as 128k x 8 SRAM 070 Writing to the device is accomplished by taking Chip Enable 5 and Write Enable inputs low Reading from the device is accomplished by taking the Chip Enable and the Output Enable MEM OE low while forcing Write Enable high The contents of the memory location specified by the address pins will on the IO pins Address space above 2000H 15 banked through the Configuration FPGA The SRAM interface is shown in Figure 7 MCU A0 1 MCU 2 4 51 2 3 02 MCU A3 4 53 4 13 MCU_D4 14 8 05 15 06 MCU A7 16 N 07 A8 17 9 18 10 19 20 21 8 CFPGA 1329 L 1430 D 9 1531 9 1632 2 VCC g MEM WR 12 MEM 28 eu _ 5 5 GND 7 1019 33 122 5010127 1176 120 32 Figure 7 MCU SRAM 3 1 3 MCU Flash Program memory
161. the options that can be set and the format this file needs to follow 2 1 1 Format of main txt The main txt file contains list of commands separated by newline characters A list of valid main txt commands is given below DN7006K10PCle 8T User Manual www dinigroup com 24 PROGRAMMING CONFIGURING THE HARDWARE comment SANITY CHECK lt gt VERBOSE LEVEL level FPGA lt gt FPGA B lt filename gt FPGA C lt filename gt FPGA D lt filename gt FPGA E lt filename gt FPGA F lt filename gt CLOCK FREQUENCY lt clock gt lt number gt MHz CLOCK FREQUENCY lt clock gt lt number gt MHz CLOCK FREQUENCY lt clock gt lt number gt MHz MEMORY MAPPED 0x lt WORDADDR gt lt gt SOURCE G0 2 DCLK DC2 100MHZ MAIN BUS 0x lt DWORDADDR gt 0x lt DWORDDATA gt Table 2 describes the function of each of the available main txt commands Table 2 Main txt Command List Instruction Function comment Comments are allowed with the following rules e All comments must start at the beginning of the line e All comments must begin with e Ifa comment spans multiple lines then each line should start with Commented lines will be ignored during configuration and are only for the user s purpose SANITY CHECK y n If lt gt is set to y then the MCU will examine the headers in the bit files on the CompactFl
162. the user will get the following alert USBController The DiNi product was not Found Please check the Following 1 Your USB cable is firmly plugged into the computer and the board 2 Your board is powered on 3 The device driver For the board is loaded 4 The device is not presently configuring itself From the media card 1 2 1 Main Window If the USBController finds the DN7006K10PCIe 8T and the USB cable was plugged into the PC before power was turned on to the DN7006K10PCIe 8T the following screen will be displayed DN7006K10PCle 8T User Manual www dinigroup com 17 INTRODUCTION TO THE SOFTWARE TOOLS DiNi Products USB Controller File Edit FPGA Configuration FPGA Reference Design Mainbus Settings Info Production Tests Service Refresh Enable USB gt FPGA Com Clear Log Scroll Log BOARD TYPE DN 7006k10PCIE8T USB to FPGA communication is disabled Enable if you want to use reference design features Sekrat menu is now on 1 2 2 Basic Menu Operations Please refer to the USB Controller Manual on the CD ROM for a complete description all the USBController functions 2 AETest USB Application The command line USB controller program is called USB It provides subset of the features available on USB Controller and is cross platform This program is a convenient place to start if you are going to be writing a custom IO controller for USB to communicate with the DN7006K10PCIe 8T
163. ther output is connected to the CKIN2 input on the DDR CLK Multiplier 054 The clock multiplier 041 can use either oscillator X2 or the Stratix III FPGA clock output signals multiplexed as a reference input The clock multiplier U41 must be programmed via the I2C interface Signal SYNTH RSTn is provided to reset the clock multiplier Note Three clock multipliers 041 047 and 054 are on the I2C chain driven from the Configuration FPGA 020 Provided on the CompactFlash card is a table giving the command to set a clock to any of a large number of intermediate frequencies see Table 9 The main txt syntax is Source G1 1 lt a gt b c lt d gt lt e gt Where lt a gt lt b gt lt gt lt 4 gt and lt e gt are arbitrary parameters given in the table The correct value of the five parameters for selected frequencies is given below Table 9 Clock Multiplier Frequency Parameters Frequency p nga 0 003000 Mhz 7 29395 1599 7 146969 H 0 005000 Mhz 1 969 23 6 96999 H 0 010000 Mhz 1 969 23 6 48499 H 0 015734 Mhz 6 44035 2178 3 44035 H 0 024000 Mhz 5 22453 999 5 22453 H 0 032000 Mhz 3 10825 374 3 21651 0 032768 Mhz 7 63915 3478 7 13455 DN7006K10PCle 8T User Manual www dinigroup com 74 HARDWARE DESCRIPTION
164. tion between FPGA and PCIe Reference Clock Buffer Signal Name Clock Buffer Pin FPGA Pin CLK REF AN U27 11 U26 A22 DN7006K10PCle 8T User Manual www dinigroup com 85 HARDWARE DESCRIPTION Signal Name Clock Buffer Pin FPGA Pin REF AP U27 12 26 B22 REF BN U27 9 37 22 REF BP U27 10 37 22 U27 7 56 BB22 REF CP U27 8 56 BA22 REF DN U27 5 25 BB21 CLK REF DP U27 6 25 BA21 CLK REF EN U27 3 36 A21 CLK REF EP U27 4 36 B21 REF FN U27 1 55 A21 CLK REF FP U27 2 55 B21 U U U CLK REF QN 27 23 24 E16 24 D16 27 24 27 13 51 2 CLK REF _ CLK REP TP 027 14 TP51 1 4 6 Main Bus Clock CLK MB A Main Bus clock CLK MB48p n is a 48MHz clock provided by the Configuration 020 and distributed to the rest of the board with a LVDS clock buffer U35 4 6 1 Main Bus Clock Circuit The Main Bus clock buffer U35 is provided to distribute the clock network to the Stratix III FPGAs see Figure 22 DN7006K10PCle 8T User Manual www dinigroup com 86 HARDWARE DESCRIPTION U35 63 CLK MB48 Sp 62 CLK MB48 Sn CLK MB48 Ap pg2 CLK MB48 An pg2 Bp CLK MB48 Bn pg2 MB48 Cp pg2 LVDS CLK LVDS CLK pg40 CLK MB48p pg40 CLK MB48n LVPECL CLK LVPECL CLK CLK MB48 Cn pg2
165. to the output buffers increases the performance of the output pins There four circuits one for each IO bank that selects the appropriate voltage based on the voltage refer to Figure 48 DN7006K10PCle 8T User Manual www dinigroup com 152 HARDWARE DESCRIPTION PVIO DCDO DCDO P12V R704 P12V cup R706 A A P12y FIL 4 53 C1014 1K 0 1uF VTRIP DCDO 2 1V 16V 20 U89 CER R705 3 5 68R OUTA DCDO lM05mV VTRIP 2 2V 4 P2 5VD 6 OUTB 9 3 8 OUTB R703 GND 1K LT6700 1 R725 SOT95P280 6N 4 7K Figure 48 VCCPD Voltage Select Circuit 17 4 Power and Reset The 3 3V 5V and 12V power rails can be supplied to the DN7006K10PCIe 8T Daughter Card Headers if the fuses are installed refer to Figure 49 Each pin on the MEG Array connector is rated to tolerate 1A of current without thermal overload P12V m 1387 FUSE 0429 P12VDCD Ai 5 Global GCCp 55 T A 42V 2 Clock GCCn DCDn 4 7uF F8 FUSE 0429 P5 0VDCD Uw P3 3VD A 3 F6 FUSE 0429 P3 3VDCD wava 55 G2 93V 2 48 8V 3 3 dN DH 2 pg45 RST_DCDn lt lt lt Ba ee required on daugh
166. tom of USBController window When the execution is finished power cycle the board Using JTAG cable Xilinx This section lists detailed instructions for programming the Xilinx Spartan 3 Configuration FPGA using the Xilinx ISE Version 9 2 041 tools Power the DN7006K10PCIe 8T Logic Emulation Board and verify that the Power LED 0525 is ON Note This User Manual will not be updated for every revision of the Xilinx tools so please be aware of minor differences Connect the Xilinx Platform Cable USB to the JTAG_PROM header 12 on the DN7006K10PClIe 8T Logic Emulation Board Open iMPACT and create new default project Select Configure devices using Boundary Scan J from the iMPACT welcome menu DN7006K10PCle 8T User Manual www dinigroup com 40 PROGRAMMING CONFIGURING THE HARDWARE iMPACT Welcome to iMPACT Please select an action from the list below gt Configure devices using Boundary Scan JTAG Automatically connect to a cable and identify Boundary Scan chain v Prepare a PROM File Prepare a System ACE File Prepare a Boundary Scan File Configure devices using Slave Serial mode 3 iMPACT will identify the devices in the JTAG chain Note The FPGA 351000 will be high lighted in the JTAG chain select Bypass since we intend to configure the FPGA with the PROM Specify the file location for the PROM programming file CUST_CD Config_Section_Code Conf
167. w dinigroup com 141 HARDWARE DESCRIPTION Signal Name Mictor Pin Configuration FPGA Pin MB21 J42 11 20 T1 MB22 142 9 20 6 MB23 142 7 20 02 MB24 142 38 20 V4 MB25 142 30 20 26 142 34 20 4 MB27 142 32 20 N3 MB28 142 30 20 5 MB29 142 28 2044 MB30 J42 26 20 M5 MB31 142 24 20 04 MB32 142 22 20 4 142 20 20 05 MB34 J42 18 20 M3 MB35 142 10 20 6 SELECTMAP DO 142 37 20 22 SELECTMAP D1 142 35 20 17 SELECTMAP 02 142 33 20 18 SELECTMAP D3 J42 31 20 J19 SELECTMAP_D4 J42 29 20 J21 SELECTMAP_D5 J42 27 20 J22 SELECTMAP_D6 J42 25 20 K17 SELECTMAP D7 142 23 20 K18 14 FPGA Interconnect 14 1 MainBus MB MainBus MB 95 0 is 96 bit bus that is routed to all the FPGAs and is used to transfer data between the Configuration FPGA PCle FPGA and all the 5 FPGAs see Figure 40 If the user prefers to use the MainBus please contact support dinigroup com for more information regarding the interface and available soutce code DN7006K10PCle 8T User Manual www dinigroup com 142 HARDWARE DESCRIPTION Configuration FPGA 81000 35 00 EP3SL340 FPGA A EP3SL340 x64 x64 PCIe Endpoint XC5VLX50T p fs FPGA E EP3SL340
168. wer the program runs 6 The progress will start from 0 to 100 This will take long time to complete 10 minutes Please do not interrupt the process 7 When the execution is finished power cycle the board Note Using the command line aeusb_wdm_cmd exe XSVF lt filename xsvf gt or aeusb_linux_cmd exe XSVF lt filename xsvf gt DN7006K10PCle 8T User Manual www dinigroup com 43 PROGRAMMING CONFIGURING THE HARDWARE 7 5 Updating MCU EEPROM To protect against accidental erasure the EEPROM firmware cannot be updated unless the board is put in Update Mode during POWER ON see par 7 2 Hither USBController or AEtest USB can be used to update the EEPROM code 7 5 4 Using USBController 1 Hold down switch S2 during POWER ON ensure the MCU LEDs turn ON 15519 12520 DS21 and 0523 to ensure the board is in Update Mode 2 Open USBController ini and add this line service mode 1 save and close the file 3 Run USBController Update Flash dialog will appear please select NO because we are doing update EEPROM 4 Go to Service menu select Program EEPROM This Process will take about 1 minute Please hit OK 5 Select file EEPROM_FLP tic When USBController completes the update please power cycle power the board 7 5 2 Using AETest USB 1 Hold down RST switch S2 during POWER ON ensure the MCU LEDs turn 0519 DS20 0521 and 0523 to en
169. wing e Altera Stratix III FPGAs FF1760 2 3 4 Speed Grade EP3SL340 FPGA to FPGA interconnect Single ended and LVDS o 600MHz Chip to Chip Source Synchronous Clocking for LVDS Flexible Clock Resources o FPGA Clock Multipliers 515326 x3 General Clock Network DN7006K10PCle 8T User Manual www dinigroup com 2 INTRODUCTION LVDS Clock Network DDR2 Clock Network o Transceiver Clock Multiplier 515326 x1 o External FPGA Clock LVDS Input via SMA s x1 o Multple clocks from the Daughter Card Headers P4 P5 P6 o Global clocks from Spartan and Virtex 5 FPGAs O Clock Test Points x6 FPGA Configuration Stratix I1T JIAG Boundaty Scan configuration mode Fast Passive Parallel FPP using the Spartan Configuration FPGA CompactFLASH USB and PCIe configuration options Memory o DDR2 512MB 64Meg x 64 200 SODIMM PC2 4200 support up to 4GB x4 Serial FLASH Memory 16Mbit 4096 pages of 512 528 bytes page e High Speed Transceiver Virtex 5 GEN 1 x8 User LED s Onboard Distributed Power Supplies Daughter Card Headers x3 LVDS MEG Array 400 pin e Full support for Embedded Logic Analyzers SignalTap Logic Analyzer Shared RS232 Port 10 pin Header DN7006K10PCle 8T User Manual www dinigroup com 3 INTRODUCTION Stand Alone operation requires an external 12V ATX power supply with PCIe power connector 3 Package Co
170. wnloads 7 4 Updating the Configuration FPGA PROM Firmware The Configuration FPGA PROM code can be updated by using one of the following three methods USBController e JTAG Cable Xilinx USB 7 4 4 Using USBController This section lists detailed instructions for programming the Xilinx Spartan 3 Configuration FPGA using the USBController software Power the DN7006K10PCIe 8T Logic Emulation Board and verify that the Power LED DS25 is ON Note This update is dependent on USBController and FLASH firmware version Please verify with support dinigroup com to make sure that your version of MCU code and USBController supports this option and request a xsvf file DN7006K10PCle 8T User Manual www dinigroup com 39 PROGRAMMING CONFIGURING THE HARDWARE Ti 7 4 2 Connect the USB Cable to the USB header J3 on the DN7006K10PClIe 8T Logic Emulation Board Open USBController inr and add the line service 1 Save and close the file Launch USBController select Service menu and Program Update Spartan A warning message will appear to ensure that you want to update Spartan If you do hit Yes button Open file Dialog will appear Please select the xsvf file that we provide you After selecting file there will be debug level dialog Please select debug level 0 The process takes about 10 15 minutes please leave the board and USBController alone The process bat is on the bot
171. z resulting in a maximum data rate of 200Mbps 3 3 CompactFlash The configuration bit file for the FPGAs is copied to a CompactFlash card using the USB 2 0 Card Reader Writer supplied as part of the kit The approximate file size for each possible FPGA option is shown below in Table 5 Note that several BIT files can put 256MB CF card The DN7006K10PCIe 8T is shipped with one 256MB 3 3V CompactFlash card The DN7006K10PCIe 8T supports card densities up to 1GB Table 5 FPGA configuration file size Stratix III Bitstream Length DN7006K10PCle 8T User Manual www dinigroup com 66 HARDWARE DESCRIPTION Device EP3SL340 3 31 CompactFlash Connector Figure 12 shows J5 the CompactFlash connector used to download the configuration files to the J5 CFAO 20 00 IDE Pin Name poo 21 85 09 19 22 CFA2 348 01 001 23 02 18 23 D2 0025 03 A03 GND 003 3 A04 GND D04 4 CF DS ___ 4 05 05 DOS P5 A06 GND 006 l6 A07 GND 007 A08 GND opt 008 X A09 GND X A10 GND opt D10 757 X D11 508 50 012 3 51 013 30 x 014 X SEL opt D15 X CSEL P3 3VD P3 3VD RESET RESET cpi 26 CF 25 CF CD e PMV65XP R37 IOWR 4 7

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