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phyCARD-L Hardware Manual

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4. MM dE E ad pomo T n O00 dur on a B m 0 LB x1 EB B E oo oo 2 Ooo ain b oo B um D n s 8888 02 j 00000000 lt lt B8 Suum C D E Figure 9 JTAG interface at X1 top view PHYTEC Messtechnik GmbH 2010 L 751e 1 49 phyCARD L PCA A LI xxx DB ma nn e a a BB 00 a a a a Er El B pm 00 uu po g O E of gg oa oo oo oo Ll oo E ga OU aug ne a o a a A C Li LIT B5 2
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6. ti oo mi n BB n n J6 a D n LP COELO OH E LE m on cd E nu Dur I uu L s nn nn 52265992 20 F 7 nm un EH n a i A Jeg 00 gan GJ3 uu n E TEE E aa oo EDU s a LJ CI LJ 00000000 ES if oo 9 L 5 BL E Eo e 1000000 L m rn 2 005000 N TN VET ED gi H 4 N M lt Figure 6 Jumper locations top view 18 PHYTEC Messtechnik GmbH 2010 L 751e 1 Jumpers c _
7. serene Description 255 Designator Section Stereo Microphone input connector 15359 2 Stereo Line out connector X3 Stereo Line In connector 17 3 9 5 Camera Interface RJ45 17 3 8 X6 Display data connector 472 41 7 Dual USB Host connector P g X8A Expansion connector 0 17 3 13 X9A Expansion connector 1 X10 Ethernet connector 745 with speed and 17 3 4 link led X26 Secure Digital MultiMedia Card slot 17 3 14 X27 phyCARD Connector for mounting the If phyCARD L X28 Wall adapter input power jack to supply main board power 9 36 V X29 USB On The Go connector 17 3 6 xa Display Backlight supply voltage IAS connector X33 USB Host connector I6 for X34 CPLD JTAG connector internal use only Pl Serial Interface DB 9F as Table 28 phyBASE Connectors and Pin Headers 72 PHYTEC Messtechnik GmbH 2010 L 751e 1 The phyCARD L on the phyBASE Note The signal levels of the and SPI interface are shifted from VCC LOGIC 1 8V at the phyCARD Connector to VCC3V3 3 3 V by level shifters on the phyCARD Carrier Board Ensure that all module connections are not to exceed their expressed maximum voltage or current Maximum signal input values are indicated in the corresponding controller User s Manual Data Sheets As damage from improper connections varies according to use and application it is the user s responsibility to take
8. 72 1722 2 WITCHES is ed aque ni aaa 73 123 GB BIDS a a pa 76 1 274 TUMPES tara aga aa a Ng a A AG Ta NANG NG Hb ema 77 17 3 Functional Components the phyBASE Board 80 17 3 1 phyCARD L SBC Connectivity 27 80 17 3 2 Power Supply X28 ou o iade eet 81 17 3 3 RS 232 Connectivity PL caeci 84 17 3 4 Ethernet Connectivity X10 eerte 85 17 3 5 USB Host Connectivity X6 X7 X8 X9 X33 86 17 3 6 USB OTG Connectivity 29 88 17 3 7 Display Touch Connectivity X32 89 17 3 7 1 Display Data Connector 6 90 17 3 7 2 Display Power Connector X32 92 17 3 7 3 Touch Screen Connectivity 93 17 3 8 Camera Interface X5 95 17 3 9 Audio Interface X1 X2 96 ca te e OR Od e 98 LES Lee e bat tate 99 17 3 12 User programmable 99 17 3 13 Expansion connectors X8A 9 100 17 3 14 Secure Digital Memory Card MultiMedia Card X26 103 17 3 15 Boot Mode Selection
9. 23 0 85 p UNIES CHIRON 80 T GA 81 Technical Specifications HE 59 D OA scd atado eb 88 MERE SF MN s9 U BG Je UAM E 86 E 20 32 KG T S 86 89 poe T MEER M 41 a a a A NG aa 86 40 pM PN 86 LUKE 39 86 a a ties 21 54 phyCARD Connector 9 11 20 58 Physical Dimensions 59 eene 38 Phytec Display Interface 89 USB Pin Description 9 Transceiver 39 16 86 88 107 Deyice 39 PoP 3l 39 Power Consumption 60 USB OT I aec m s 39 Power Management 27 112 PHYTEC Messtechnik GmbH 2010 1 751 1 Index V VDD eet 23 Voltage 26 Voltage Regulator 24 notare 24 W Weight 60 93 94 96 97 P ap INE 49 KD e 88 Messtechnik GmbH 2010 L 751e 1 113 phyCARD L PCA A L1 xxx 114 PHYTEC Messtechnik GmbH 2010 L 751e 1 Suggestions for Improvement Document phyCARD L
10. phyCARD L Hardware Manual Document No SBC Prod No SBC PCB No CB Prod No CB PCB No L 751e 1 PCA A L1 xxx 1334 2 PBA A 01 1333 2 Edition December 2010 A product of a PHYTEC Technology Holding company phyCARD L PCA A L1 xxx In this manual are descriptions for copyrighted products that are not explicitly indicated as such The absence of the trademark TIM and copyright symbols does not imply that a product is not protected Additionally registered patents and trademarks are similarly not expressly indicated in this manual The information in this document has been carefully checked and is believed to be entirely reliable However PHYTEC Messtechnik GmbH assumes no responsibility for any inaccuracies PHYTEC Messtechnik GmbH neither gives any guarantee nor accepts any liability whatsoever for consequential damages resulting from the use of this manual or its associated product PHYTEC Messtechnik GmbH reserves the right to alter the information contained herein without prior notification and accepts no responsibility for any damages which might result Additionally PHYTEC Messtechnik GmbH offers no guarantee nor accepts any liability for damages arising from the improper usage or improper installation of the hardware or software PHYTEC Messtechnik GmbH further reserves the right to alter the layout and or design of the hardware without prior notification and accepts no liability
11. 41 25 DAS eiae dnte 25 hu RR PP 25 25 2 PAUSE ER 25 3 24 Audio 96 Block 4 Boot Configuration 30 Boots decode 29 C Camera Interface 57 D DDR 31 Debug 49 Dimensions 60 Display Interface 53 E 31 32 EEPROM Write Protection 34 va ac ACE The xi oec hri 5 F Fast Ethernet Controller 4 POAtufes os costes 2 69 jn RTT EE 4 G General Purpose I Os 47 GND Connection 67 H Humidity sett es 60 I EEPROM 32 PC 44 MemoLy 20 2 20 PEN CIE 39 Jl E 20 33 TED ed mss etn 21 e riter ru 21 48 Jl s esee i ats 21 48 Jii NS 21 48 E E a a 20 33 rcr 20 33 20 34 a 20 58 05 21 JO emer
12. o cete Gi babe oen Phe d 43 Str ae Pe 44 6 rn trac ut ov 44 9 7 Synchronous Serial Interface 561 2 2 1 1 45 10 General Purpose I OS 00000000000000 00000000000000 0000000000 00000000000000 47 11 Debug Interface X1 49 PHYTEC Messtechnik GmbH 2010 L 751e 1 1 phyCARD L PCA A L1 xxx 12 13 14 15 16 17 LVDS Display Interface o0000000000000000000 00000000000000 0000000000000000 53 12 1 Signal configuration eee tei eitis 54 12 2 LVDS Display Interface pixel mapping 54 LVDS Cam ra Interface PE o Sena aor Fa parre 57 13 1 Signal configuration J6 sse 58 Technical Specifications 59 Component Placement Diagram 2 63 Hints for Integrating and Handling the phy CARD L 65 16 1 Integrating the phyCARD M seen 65 16 2 Handling the phy C eth oerte 67 The phyCARD L on the 0 4 2 eere eren nen 69 17 1 Concept of the phyBASE 70 17 2 Overview of phyBASE Peripherals 71 17 2 1 Connectors and Pin
13. 106 Figure 34 Carrier Board Physical 1 108 List of Tables Table 1 Abbreviations and Acronyms used in this Manual viii Table 2 BUS ss asat tet aana pana 12 Table3 Pinout of the phyCARD Connector 2 16 Table Ac J rmpersettlligs oi etie o HEP Dott en udine is 21 Table 5 Power Management Pins nete een Rees 27 RADIO TRO d i cp 28 Table 7 Boot Modes of OMAP35x 30 Table 8 Compatible NAND Flash 32 Table9 U10 EEPROM address via J1 J2 and J3 33 Table 10 EEPROM write protection states via J5 34 Table 11 Location of SD MMC Card interface signals 35 Table 12 Location of the UART signals uere exeo 38 Table 13 Location of the USB OTG 5 39 Table 14 Location of the USB Host 15 40 Table 15 Location of the Ethernet 41 Table 16 Software Reset of the Ethernet Controller 43 Table 17 Interface Signal Location 2 44 PHYTEC Messtechnik GmbH 2010 L 751e 1 Contents Table 18 Table 19 Table 20 Table 21 Table 22 T
14. Internally generated voltages 1V15 5 Core Power Supply OMAP35x MPU amp IVA Power Supplies OMAP35x PLL Power Supply OMAP35x MMC Power Supply OMAP35x 32kHz and 26MHz oscillators EEPROM USB Transceivers Ethernet controller Display LVDS Transmitter 1V2 1V8 1V8 1V8 12C1 X nRESET IN VDD 3V3 VSTBY Figure 8 VDD BKUP VDD BKUP TPS65023 Power Supply Diagram 1 15 1V2 1V8 SYS nIRQ X nRESET OUT VDD MPU 1 2V OMAP35xx MPU IVA VDD CORE 1 15 V OMAP35xx VDD CORE VDD 10 1 8V OMAP35xx EEPROM 32KHZ 26MHZ ETHERNET VDD PLL1 1 8V OMAP35xx VDDS DPLL VDD MMC 1 8V OMAP35xx VDDS MMC PHYTEC Messtechnik GmbH 2010 L 751e 1 25 phyCARD L PCA A L1 xxx 4 4 Supply Voltage for external Logic The voltage level of the phyCARDs logic circuitry is VDD IO 1 8V which is generated on board In order to allow connecting external devices to the phyCARD L without the need of another voltage source in addition to the primary supply this voltage is brought out at pins 2 5 and X2B5 of the phyCARD Connector Use of level shifters supplied with VDD IO allows converting the signals according to the needs on the custom target hardware Alternatively signals can be connected to an open drain circuitry with a pull up resistor attached to VDD IO 26 PHYTEC Messtechnik GmbH 2010 1 751 1 Power Management 5 Po
15. X2A7 of the phyCARD Connector Jumper 110 connects the reset input of the Ethernet controller with GPIO 64 This allows to also reset the Ethernet controller by software J10 is not mounted To enable software reset of the Ethernet controller 110 must be closed The following configurations are possible Software reset of the Ethernet controller 110 Software reset disabled open Software reset possibel via GPIO 64 closed Table 16 Software Reset of the Ethernet Controller 943 MAC Address In a computer network such as a local area network LAN the MAC Media Access Control address is a unique computer hardware number For a connection to the Internet a table is used to convert the assigned IP number to the hardware s MAC address In order to guarantee that the MAC address is unique all addresses are managed in a central location PHYTEC has acquired a pool of MAC addresses The MAC address of the phyCARD L is located on the bar code sticker attached to the module This number is a 12 digit HEX value An EEPROM at U13 is used to store the MAC address Defaults are in bold blue text PHYTEC Messtechnik GmbH 2010 1 751 1 43 phyCARD L PCA A L1 xxx 9 5 Interface The Inter Integrated Circuit interface is a two wire bidirectional serial bus that provides a simple and efficient method for data exchange among devices The OMAP35x contains three identical and independent
16. nu U19 BB 8 m U20 UU gong E 00 o Cc x1 a 5 S QOD Gl 4 19 B J12 1 JH Ji4cuu uu 5g o gt jama nn U18 i o0 cao c ci c ng EL 4 20 oo n WE gg CL ccm nn uu oa nu i s uu 00 nn gt 3 623 D 3 oo 23 B ali Hiram 5895 9900 B Bras LL im un E U28 8 20 J ee 2 2 Oooo 55 64 1 Cc 1 BOS oie D BER 1 cV um oon NI 5 E dE iE CM c r Eti oe oe aa oa mo E ng n 00000000 0000000000000007 5 na 0 1 1B Lang 1 xf U14 ngih pes saa ej ID GC OCC CD OO LO a a a Figure 3 Bottom view of the phyCARD L connector side 6 PHYTEC Messtechnik GmbH 2010 L 751e 1 Introduction 1 3 Minimum Requirements to Operate the phy CARD L Basic operation of the phyCARD L only requires supply of a 3V3 input voltage with 1 5 A load and the corresponding GND connection These supply pins are located at the phyCARD Connector X2
17. PHYTEC Messtechnik GmbH 2010 L 751e 1 Preface The support section of our web site provides product specific information such as errata sheets application notes FAQs etc http www phytec de de support faq faq phyCARD L html Declaration of Electro Magnetic Conformity of the PHYTEC phyCARD L PHYTEC Single Board Computers henceforth products are designed for installation in electrical appliances or as dedicated Evaluation Boards ie for use as a test and prototype platform for hardware software development in laboratory environments Caution PHYTEC products lacking protective enclosures are subject to damage by ESD and hence may only be unpacked handled or operated in environments in which sufficient precautionary measures have been taken in respect to ESD dangers It is also necessary that only appropriately trained personnel such as electricians technicians and engineers handle and or operate these products Moreover PHYTEC products should not be operated without protection circuitry if connections to the product s pin header rows are longer than 3 m PHYTEC products fulfill the norms of the European Union s Directive for Electro Magnetic Conformity only in accordance to the descriptions and rules of usage indicated in this hardware manual particularly in respect to the pin header row connectors power connector and serial interface to a host PC Implementation of PHYTEC products into target devices as well a
18. SPI connector selection 17 3 12 User programmable GPIOs Two GPIOO IRQ and GPIOI IRQ of the three GPIO Interrupt signals available at the X Arc bus are freely available They are mapped to the expansion connectors X8A and X9A 16 or to the display data connector X6 pin 5 depending in the configuration at DIP Switch S3 see Table 44 The third GPIO Interrupt signal GPIO2 1207 is used to connect the interrupt output of the touch screen controller at U28 to the phyCARD L 9 GPIOO IRQ GPIO 144 and IRQ 4 GPIO 145 of the OMAP35x both GPIOs be assigned to other inputs by changing jumpers J11 and J12 refer to section 10 8 GPIO2 IRQ 4 GPIO 147 of the OMAP35x or GPIO 146 depending on jumper J13 refer to section 10 PHYTEC Messtechnik GmbH 2010 L 751e 1 99 phyCARD L PCA A L1 xxx 17 3 13 Expansion connectors X8A X9A gt 55 49555 O 9222 95229 2 1 O Figure 29 Expansion connector XSA X9A The expansion connectors X8A and X9A provide an easy way to add other functions and features to phyBASE Standard interfaces such as USB SPI and as well as different supply voltages and GPIO are available at the pin header rows The pinout of the expansion connectors in shown in Table 46 As can be seen in Figure 29 the location of the connectors allows to expan
19. uC 144 or GPIO 1511 GPIO2 2 connected X2A47 X GPIO2 IRQ2 PWM I O VDD IO uC GPIO 147 GPIO 146 IRQI connected X2B47 X GPIOI IRQI I O VDD IO to uC GPIO 145 or GPIO 149 Table 20 Location of GPIO and IRQ pins As can be seen in the table above the voltage level is VDD IO which is 1 8 V In other words VDD IO is not identical with the supply voltage of the phyCARD L To avoid mismatch of the different voltage levels external devices connected to these pins should be supplied by VDD IO available at X2A5 and X2B5 refer to section 4 4 Alternatively an open drain circuit with a pull up resistor attached to VDD IO can be connected to the GPIOs of the phyCARD L Please refer to the chapter GPIOs in the phyCARD Design In Guide for more information about how to integrate the GPIO pins in your design 1 be selected by jumper refer to section 3 PHYTEC Messtechnik GmbH 2010 1 751 1 47 phyCARD L PCA A L1 xxx Three jumpers J11 J12 and J13 allow to choose different GPIOs of OMAP35x to be connected to the GPIO IRQ pins of the X Arc bus The following table shows the possible configurations Jil allows to connect GPIO 149 to the pin of the X Arc bus X2B47 instead of GPIO 145 GPIO1 IRQI connects to GPIO 149 connects to 145 J12 J12 allows to connect GPIO 151 to the GPIOO IRQO of
20. 104 17 3 16 System Reset Button 51 eerte 105 at UZ ot edm e uro monte 106 PELD dt 12595 107 PHYTEC Messtechnik GmbH 2010 L 751e 1 Contents 17 3 19 Carrier Board Physical Dimensions 108 IS Revisi n HIStory ore ERRARE eU nagane Na ME nana EHE 109 Index wei aceti ae hod Ov e aan ga aan D 111 List of Figures Figure 1 Block Diagram of the phyCARD L eee 4 Figure2 view of the phyCARD L controller side 5 Figure 3 Bottom view of the phyCARD L connector 51 6 Figure 4 Pinout of the phyCARD Connector top view with cross SECO uM ID IN E 10 Figure 5 Typical jumper pad numbering 17 Figure 6 Jumper locations top view eene 18 Figure 7 Jumper locations bottom 19 Figure 8 Power Supply tontos 25 Figure 9 JTAG interface at X1 top view 49 Figure 10 JTAG interface at X1 bottom 50 Figure 11 Physical t e vae e 39 Figure 12 phyCARD L component placement top view 63 Figure 13 phyCARD L component placement bottom view 64 Figure 14 Footprint of the phyCARD L eene nenen an anane anna 66
21. B o o o a am o a a oo oo 00 nna o 5d Do oo EB WA qq U oo o aha aapa JAYA YAA AA YAA AA AJA YA die gg DU LE mod ES oo ES ES ES ES Ep a a Figure 10 JTAG interface at bottom view Pin 1 of the JTAG connector X1 is on the connector side of the module Pin 2 of the JTAG connector is on the controller side of the module Note The JTAG connector X1 only populates phyCARD L modules with order code PCA A L1 D JTAG connector is not populated on phyCARD modules with order code PCA A L1 We recommend integration of a standard 2 mm pitch pin header connector in the user target circuitry to allow easy program updates via the JTAG interface 50 PHYTEC Messtechnik GmbH 2010 L 751e 1 Debug
22. Figure 31 Boot Mode Selection Jumper JP1 The boot mode jumper JP1 is provided to configure the boot mode of the phyCARD L after a reset By default the boot mode jumper is open configuring the phyCARD L for booting from the Flash device Closing jumper JP1 at 1 2 results in start of Peripheral boot of the OMAP35x Please refer to the phyCARD L Data Sheet as well as the OMAP35x Reference Manual for Information on how to use the boot strap mode 104 PHYTEC Messtechnik GmbH 2010 L 751e 1 The phyCARD L on the phyBASE Jumper Setting Description JP1 Jumper JP1 selects the boot device of the phyCARD L open Memory Boot NAND USB UART3 MMCI 142 Peripheral Boot USB UART3 MMCI NAND other settings must not be used with the phyCARD L 17 3 16 System Reset Button S1 Reset Figure 32 System Reset Button S1 The phyCARD Carrier Board is equipped with a system reset button at S1 Pressing the button will not only reset the phyCARD mounted on the phyBASE but also the peripheral devices such as the USB Hub etc 2 please see section 6 for more information on the different boot modes PHYTEC Messtechnik GmbH 2010 L 751e 1 105 phyCARD L PCA A L1 xxx 17 3 17 RTC at U3 LO r Ici Figure 33 with Battery Buffer For real time or time driven applications the phyBASE 1s equipped with an RTC 8564 Real Time Clock at U3 This RTC device provides
23. High Speed USB transceiver High Speed USB HOST transceiver Auto HDX FDX 10 100MBit Ethernet interface with HP Auto MDI MDI X support Additional 1 Kbit EEPROM connected to the Ethernet controller to store MAC address Single supply voltage of 3 3V max 1 5 A with on board power management All controller required supplies generated on board controller required supplies generated on board 4 Channel LVDS 24Bit LCD Interface Support of standard 20 pin debug interface through JTAG connector One interfaces One SPI interfaces SD MMC card interface with DMA SSI Interface AC 97 LVDS Camera Interface 3 GPIO IRQ ports 2 Power State outputs to support applications requiring a power management 1 Wake Up input the OMAP35x does not feature AC 97 interface The AC 97 interface of the phyCARD L 18 emulated with the multi channel buffered Serial Port McBSP Thus it is only available with the BSP coming with the phyCARD L PHYTEC Messtechnik GmbH 2010 L 751e 1 3 phyCARD L PCA A L1 xxx 1 4 Block Diagram 10 600 MHz Clock external 26MHz Oscillator OMAP35xx SYS_BOOTO 4 2 SYS BOOTS EN ARM Cortex A
24. SPI and GPIO connector 422 92 LVDS power connector X32 signal description 92 Selection of the touch screen controller 94 PHY TEC camera connector 95 Selection of the audio codec asa ato eure to evapo 97 connective 98 EC addresses in 086 Genes keora naa nn dk apakah na at m lash 98 SPEconnector selection oda Ves aen aka aa 99 SPI and GPIO connector selection eee 101 PHYTEC expansion connector X8A 9 102 PHYTEC Messtechnik GmbH 2010 L 751e 1 phyCARD L PCA A L1 xxx PHYTEC Messtechnik GmbH 2010 L 751e 1 Conventions Abbreviations and Acronyms Conventions Abbreviations and Acronyms This hardware manual describes PCA A L1 Single Board Computer in the following referred to as phyCARD L The manual specifies the phyCARD L s design and function Precise specifications for the Texas Instruments OMAP35x microcontrollers can be found in the enclosed microcontroller Data Sheet User s Manual Conventions The conventions used in this manual are as follows Signals that are preceded by n or e g nRD RD or RD or that have a dash on top of the signal name e g RD are designated as active low signals That is their active state is when they are driven low or are
25. X Arc bus features an SD MMC interface On the phyCARD L the interface signals extend from the controllers first Multimedia Card Secure Digital Secure Digital I O MMC SD SDIO Host Controller MMC1 to the phyCARD Connector Table 11 shows the location of the different interface signals on the phyCARD Connector The MMC SD SDIO Host Controller is fully compatible with the SD Memory Card Specification 2 0 and SD I O Specification 1 1 with 1 and 4 channel s refer to the OMAP35x Reference Manual for more information Due to compatibility reasons a card detect signal X SDIO CD is added to the SD MMC Card Interface This signal connects to port GPIO_ 126 of the OMAP35x Pin Signal SL Description SD MMC Data line both X2A31 X SDIO DO 10 VDD IO SD MMC Data line both X2A32 X SDIO D2 I O VDD IO SD MMC Clock for MMC SD SDIO SD MMC Data line both in 1 bit and 4 bit mode SD MMC Data line both in 1 bit and 4 bit mode SD MMC Command for MMC SD SDIO SD MMC Card Detect for MMC SD SDIO Table 11 Location of SD MMC Card interface signals X2A33 X SDIO O VDD IO X2B31 X SDIO DI I O VDD IO X2B32 X SDIO D3 I O VDD IO X2B33 JK SDIO CMD O VDD IO X2B46 X SDIO CD I VDD IO PHYTEC Messtechnik GmbH 2010 L 751e 1 35 phyCARD L PCA A L1 xxx Note The signal level of the SD MMC card interfa
26. the following features Serial input output bus address OxA2 write 0x A3 read Power consumption Bus active 400 kHz lt mA Bus inactive CLKOUT inactive 275 nA Clock function with four year calendar Century bit for year 2000 compliance Universal timer with alarm and overflow indication 24 hour format Automatic word address incrementing Programmable alarm timer and interrupt functions 106 PHYTEC Messtechnik GmbH 2010 L 751e 1 The phyCARD L on the phyBASE The Real Time Clock is programmed via the bus address 0xA2 0xA3 Since the phyCARD L is equipped with an internal controller the protocol is processed very effectively without extensive processor action refer also to section 0 The Real Time Clock also provides an interrupt output that extends to the Wakeup signal at X27A48 An interrupt occurs in the event of a clock alarm timer alarm timer overflow and event counter alarm It has to be cleared by software With the interrupt function the Real Time Clock can be utilized in various applications If the RTC interrupt is to be used as a software interrupt via a corresponding interrupt input of the processor Note After connection of the supply voltage the Real Time Clock generates no interrupt The RTC must be first initialized see RTC Data Sheet for more information Use of a coin cell at allows to buffer the RTC 17 3 18 PLD at U25 The phyBASE is e
27. 1 bit and 4 bit mode 33A X SDIO VCC LOGIC SD MMC Clock for MMC SD SDIO 34A GND Power Ground 0V 35A X SPI CSO VCC LOGIC SPI Chip select 0 36A X SPI RDY VCC LOGIC SPI Data ready in Master mode 37A X SPI CLK LOGIC SPI Clock 38A GND Power Ground 0V 39A X UART TXD LOGIC Serial transmit signal UART 40A X UART RTS VCC LOGIC Request to send 41A GND Power Ground 0V 42A X AC97 HDA INT SEL I O VCC LOGIC AC 97 Interrupt Input 43A X 97 SDOUT O VCC LOGIC AC 97 Transmit Output 44 97 SDIN I LOGIC AC 97 Receive Input 45A GND Power Ground 0V 46A X_GPIOO IRQO VCC_LOGIC GPIOO IRQO port GPIO 144 GPIO_1517 47A X_GPIO2 IRQ2 PWM VCC_LOGIC GPIO2 IRQ2 PWM uC port 147 1462 48 nWKUP LOGIC Wakeup Interrupt Input uC port GPIO 146 GPIO 27 49A GND Power Ground 0V 50A X CONFIGO I VCC LOGIC Boot Mode Input 0 the OMAP35x does not feature an AC 97 interface The AC 97 interface of the phyCARD L is emulated with the multi channel buffered Serial Port McBSP Thus it is only available with the BSP coming with the phyCARD L can be selected by jumper refer to section 3 14 PHYTEC Messtechnik GmbH 2010 1 751 1 Pin Description Pin R
28. 54 JUNO et DUE 51 JTAG Interface 49 JTAG Emulator Adapter 51 L LAN ec 43 LINK iecoris 85 PHYTEC Messtechnik GmbH 2010 L 751e 1 phyCARD L PCA A L1 xxx LVDS Power Supply 7 Camera Signals 20 58 R Display Signals 21 54 aaa Pha an aaa 43 43 43 RS 232 1 38 MAC Address 43 106 N Interrupt 107 NAND 2 SD MMC Interfaces 35 SDRAM ya a ise 31 Operating Temperature 60 Serial Interfaces 37 Operating Voltage 60 SMT Connector 9 P SPEED EBD 85 SPI Interface nC thee 44 PD tuk 89 SSI 45 phyBASE Standby 24 1 72 Storage Temperature 60 Eom UR 84 Supply Voltage 23 71 System Configuration 29 Pin 72 System 31 SWILCHES 73 System
29. Document number L 751e 1 December 2010 How would you improve this manual Did you find any mistakes in this manual page Submitted by Customer number Name Company Address Return to PHYTEC Technologie Holding AG Postfach 100403 D 55135 Mainz Germany Fax 49 6131 9221 33 PHYTEC MesstechnikGmbH 2010 L 751e 1 Published by ELG PHYTEC Messtechnik GmbH 2010 Ordering No L 751e 1 Printed in Germany
30. Figure 15 phyBASE Overview of Connectors LEDs and Buttons 71 Figure 16 Typical jumper numbering scheme 77 Figure 17 phyBASE jumper locations esee 78 Figure 18 phyCARD L SBC Connectivity to the Carrier Board 80 Figure 19 Power os NG 81 Figure 20 Connecting the Supply Voltage at 28 82 Figure 21 RS 232 connection interface at connector 1 84 Figure 22 RS232 connector P1 signal 85 Figure 23 Ethernet interface at connector 10 85 Figure 24 Components supporting the USB host interface 86 PHYTEC Messtechnik GmbH 2010 L 751e 1 i phyCARD L PCA A L1 xxx Figure 25 USB interface at connector 29 88 Figure 26 Universal LVDS interface at connector 89 Figure 27 Camera interface at connectors 95 Figure 28 Audio interface at connectors X2 96 Figure 29 Expansion connector ASA 100 Figure 30 50 Card interface at connector 26 103 Figure 31 Boot Mode Selection Jumper 104 Figure 32 System Reset Button 105 Figure 33 with Battery Buffer re
31. Fs a 5 a Ben meg a J10 B og J25 cJ3 BE 20 A x g 2 pen 0781 meg msn a aag 925 5 5 de B B rej QOO00000000000 m J4 amem Gal ban ah PES E 0 Ea E Ue E Ua SS o 000000000 he 5 men _ neg 00000000000000 207 f N ali Ju Jg xn g T N A M Figure 12 phyCARD L component placement top view PHYTEC Messtechnik GmbH 2010 1 751 1 63 phyCARD L PCA A LI xxx
32. TXCLK can be found in the table below Signal I O SL Description X2A9 X DIS LVDS TX0 lo Lvps LVDS chanel 0 pos output 2 10 DIS LVDS o Lvps LVPS chanel 0 E neg output 2 11 DIS LVDS 2 mE 7 pos output SOA OS EDS zer neg output 2 14 DIS LVDS TXCLK Lvps LVDS Clock pos Hu output 30415 X DIS LVDS TXCLK YE gt as de output X2B9 X DIS LVDS TX1 o MAI pos output X2B10 x Dis EVbs TXie O DP chanel a neg output X2B11 X DIS LVDS TX3 Ds chanel nup n pos output X2BI2 X DIS LVDS TX3 o Lvps LYD5 chanel 3 n neg output Table 23 Display Interface Signal Location To assists the implementation of a power managment the LVDS Transmitters SHTDN input is connected to GPIO 26 of the PHYTEC Messtechnik GmbH 2010 L 751e 1 53 phyCARD L PCA A L1 xxx OMAP35x Therefore the LVDS Transmitter can be turned off by software 12 1 Signal configuration J7 J7 selects rising or falling edge strobe for the LVDS Transmitter at U7 used for the display connectivity of the phyCARD L 1 2 falling edge strobe used for the LVDSj 10k 0805 display signals 243 rising edge strobe used for the LVDS display signals 12 2 LVDS Display Interface pixel mapping The phyCARD specification de
33. The USB Host connectivity of the phyCARD L is achieved with an SMSC USB3320 High Speed USB transceiver at U23 supporting high speed full speed and low speed data rates The USB3320 functions as the transceiver for the first High Speed Host Controller HSUSBI of the OMAP35x An external USB Standard A for USB host connector is all that is needed to interface the phyCARD L USB Host functionality The applicable interface signals D D PSW FAULT can be found on the phyCARD Connector Pin Signal I O SL Description USB HOST Power X2B23 X USBH O VDD 3V3 switch output open drain USB HOST over current X2B24 X USBH VDD 3V3 input signal USB HOST transceiver X2B27 X USBH DM cable interface D USB HOST transceiver X2B28 X USBH DP 10 cable interface D Table 14 Location of the USB Host signals 40 PHYTEC Messtechnik GmbH 2010 1 751 1 Serial Interfaces 9 4 Ethernet Interface Connection of the phyCARD L to the world wide web or a local area network LAN is possible using the on board FEC Fast Ethernet connected to the GPMC interface of the OMAP35x The FEC operates with a data transmission speed of 10 or Controller at U12 It is 100 Mbit s 9 4 1 Ethernet Controller U12 With an Ethernet controller mounted at U12 the phyCARD L has been designed for use in 10 and 100Base T networks The 10 100Base T interf
34. VDD 3V3 X2 2 IB 2B 3B Connect all 3 3V VCC input pins to your power supply and at least the matching number of GND pins Corresponding GND X2 8A 13A 8B 138 Please refer to section 2 for information on additional GND Pins located at the phyCARD Connector X2 Caution We recommend connecting all available 3 V3 input pins to the power supply system on a custom carrier board housing the phyCARD L and at least the matching number of GND pins neighboring the 3 V3 pins In addition proper implementation of the phyCARD L module into a target application also requires connecting all GND pins neighboring signals that are being used in the application circuitry Please refer to section 4 for more information PHYTEC Messtechnik GmbH 2010 1 751 1 7 phyCARD L PCA A L1 xxx 8 PHYTEC Messtechnik GmbH 2010 L 751e 1 Pin Description 2 Pin Description Please note that all module connections are not to exceed their expressed maximum voltage or current Maximum signal input values are indicated in the corresponding controller manuals data sheets As damage from improper connections varies according to use and application it is the user s responsibility to take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals As Figure 4 indicates all X Arc bus signals extend to one surface mount technology SMT connec
35. also possible to enter OFF state with the help of the phyCARD s X nPWR OFF signal GPIO 133 of the OMAP35x To enter OFF state signal X nPWR OFF must be active low SUSPEND state can be entered using signal X nSUSP RAM at pin X2A26B of the phyCARD Connector GPIO 134 of the OMAP35x X nSUSP RAM must be active low for at least 500 ms PHYTEC Messtechnik GmbH 2010 L 751e 1 83 phyCARD L PCA A LI xxx 17 3 3 RS 232 Connectivity P1 RS232 Figure 21 R 232 connection interface at connector P1 Connector Pl is a DB9 sub connector and provides a connection interface to UART3 of the OMAP35x The TTL level signals from the phyCARD L are converted to RS 232 level signals As defined in the specification of the X Arc bus the serial interface allows for a 5 wire connection including the signals RTS and CTS for hardware flow control Figure 22 below shows the signal mapping of the RS 232 level signals at connector P1 The RS 232 interface is hard wired and no jumpers must be configured for proper operation 84 PHYTEC Messtechnik GmbH 2010 L 751e 1 The phyCARD L on the phyBASE 1 6 2 Pin 2 TxD RS232 7 Pin 7 RTS RS232 3 Pin 3 RxD RS232 8 Pin 8 CTS RS232 9 5 Pin 5 GND Figure 22 RS232 connector signal mapping 17 3 4 Ethernet Connectivity X10 Ethernet Figure 23 Ethernet interface at connector X10 The Ethernet interface of the phyCARD is accessible at 5 connector X10 on
36. an 97 compliant audio interface the Wolfson WM9712L audio touch codec must be chosen to process the audio signals LEDs 045 AC 97 and 046 HDA indicate which audio interface is active For the phyCARD L LED D45 should be on Audio devices can be connected to 3 5 mm audio jacks at X1 X2 and X3 Audio outputs X2 Line output Line OUTL Line OUTR Audio Inputs 1 Microphone Inputs MICI MIC2 X3 Line Input Line INL Line INR Please refer to the audio codec s reference manual for additional information regarding the special interface specification Since the OMAP35x does not support the AC 97 protocol the AC 97 interface on the phyCARD L is software emulated The emulation is part of the BSP delivered with the phyCARD L PHYTEC Messtechnik GmbH 2010 L 751e 1 97 phyCARD L PCA A L1 xxx 17 3 10 Connectivity The interface of the X Arc bus is available at different connectors on the phyBASE The following table provides a list of the connectors and pins with connectivity Connector Location Camera interface X5 pin 4 SDA pin 5 SCL Display data connector X6 pin 8 SDA pin 7 PC SCL Expansion connector X8A pin 7 FC SDA pin 8 SCL Expansion connector 2 X9A pin 7 FC SDA pin 8 SCL Table 42 connectivity To avoid any conflicts when connecting external devices to the phyBASE the addresses of the on b
37. and features of controller signals and port pins PHYTEC Messtechnik GmbH 2010 L 751e 1 11 phyCARD L PCA A LI xxx yo gt In 2 In D In Out In Out Out Out 2 Out a Out Out Camera Out PC i Bi 9 Out 9 Out Out Out o In 5 Bi P gt Bi In Bi gt Bi 7 Out n In UART 1 um Bi z Out Slin lt 2 Bi GPIO 1 Ei In Boot Opt In Table 2 Signal Pin Pin Signal VCC 1A 1B VCC VCC 2A 2B VCC 3B VCC GND 4 4B GND LOGIC 5A 5B VCC LOGIC 6A 6B VSTBY nRESET IN 7A 7B nRESET OUT GND 8A 8B GND LVDS_TX0 9B LVDS_TX1 LVDS TXO 10A 10B LVDS TX1 LVDS 11 LVDS_TX3 LVDS TX2 12A 12B LVDS GND 13A 13 GND LVDS TXCLK 14A 14B LVDS TXCLK 15A 15B 16 1eB 17A 178 GND 18A 18B GND 19A 19B 20A 20B 21A 21B 22A 22B 23A 23B 24A 24B 25A 25B 26A 26B 27 27B 28A 28B 29A 29B GND 30A 30B GND 31A 31B 32A 32B 5010 33A 338 GND 34A 34B GND 35A 35B 36A 36B 37A 37B GND 38A 38B GND 39A 39B 40A 40B 41B GND _ HDA SEL AC97 INT 42A 42B AC97 HDA BIT CLK AC97 HDA SDATA OUT 43 43B AC97 HDA SYNC AC97 HD
38. appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals 17 2 2 Switches The phyBASE is populated with some switches which are essential for the operation of the phyCARD L module on the Carrier Board Figure 15 shows the location of the switches and push buttons See Button Description Section 51 System Reset Button system reset signal 173 16 generation S2 Power Button powering on and off main i 17 32 supply voltages of the Carrier Board Table 29 phyBASE push buttons descriptions 51 Issues a system reset signal Pressing this button will toggle the nRESET IN pin X2A7 of the phyCARD microcontroller LOW causing the controller to reset S2 Issues a power on off event Pressing this button less than 2 seconds will toggle the PWR KEY pin of the phyBASE CPLD LOW causing the CPLD to turn on the supply voltages Pressing this button for more than 2 seconds causes the CPLD to turn off the supply voltages PHYTEC Messtechnik GmbH 2010 L 751e 1 73 phyCARD L PCA A L1 xxx Additionally a DIP Switch is available at S3 The following table gives an overview of the functions of the DIP switch Note The following table describes only settings suitable for the phyCARD L Other settings must not be used with the phyCARD L Button Setting Description See Section S3 1 63 2 0 0 0 1 Dep
39. directly to the phyCARD Connector without conversion to RS 232 level External 5 232 transceivers must be attached by the user if RS 232 levels are required 38 PHYTEC Messtechnik GmbH 2010 L 751e 1 Serial Interfaces 92 USB OTG Transceiver 016 The phyCARD L 15 populated with an NXP 15 1504 USB Go High Speed transceiver at U16 which is capable of high speed full speed and low speed data transmission The ISP1504 functions as the transceiver for the OMAP35x High Speed USB OTG Controller HSUSBO An external USB Standard A for USB host USB Standard B for USB device or USB mini AB for USB OTG connector is all that is needed to interface the phyCARD L USB functionality The applicable interface signals can be found on the phyCARD Connector as shown in Table 13 Pin Signal I O SL Description USB OTG Power X2A23 X USBOTG VDD 3V3 switch output open drain USB OTG over X2A24 X USBOTG I VDD 3V3 current input signal 2 26 USBOTG VBUS I 5 USB VBUS Voltage USB transceiver 2 27 USBOTG DM cable interface D USB transceiver X2A28 X USBOTG DP yo cable interface D USB on the go X2A29 X USBOTG UID I transceiver cable ID resistor connection Table 13 Location of the USB OTG signals PHYTEC Messtechnik GmbH 2010 L 751e 1 39 phyCARD L PCA A L1 xxx 9 3 USB Host Transceiver 015
40. driving low 0 indicates a logic zero or low level signal while a I represents a logic one or high level signal Tables which describe jumper settings show the default position in bold blue text Text in blue italic indicates a hyperlink within or external to the document Click these links to quickly jump to the applicable URL part chapter table or figure References made to the phyCARD Connector always refer to high density molex connector on the undersides of the phyCARD L Single Board Computer Abbreviations and Acronyms Many acronyms and abbreviations are used throughout this manual Use the table below to navigate unfamiliar terms used in this document Abbreviation Definition BSP Board Support Package Software delivered with the Development Kit including an operating system Windows or Linux preinstalled on the module and Development Tools CB Carrier Board used in reference to the phyBASE Development Kit Carrier Board PHYTEC Messtechnik GmbH 2010 1 751 1 vil phyCARD L PCA A L1 xxx Abbreviation Definition DFF D flip flop EMB External memory bus EMI Electromagnetic Interference GPI General purpose input GPIO General purpose input and output GPO General purpose output IRAM Internal RAM the internal static RAM on the Texas Instruments OMAP35x microcontroller J Sol
41. expansion 0 X8A 17 3 12 i SS1 GPIO1 gt expansion 1 X9A 173 13 0 1 SSO GPIOO gt expansion 0 8 SSI GPIOI gt display data connector 1 SSO GPIOO gt expansion 1 9 SS1 GPIO1 gt display data connector Table 30 phyBASE DIP Switch 53 descriptions 1 Default settings are in bold blue text PHYTEC Messtechnik GmbH 2010 L 751e 1 73 phyCARD L PCA A L1 xxx 17 2 3 LEDs The phyBASE is populated with numerous LEDs to indicate the status of the various USB Host interfaces as well as the different supply voltages Figure 15 shows the location of the LEDs Their function is listed in the table below LED Color Description Sun D16 yellow USBI amber led D17 yellow USB2 amber led D18 yellow USB3 amber led D19 yellow USB4 amber led 020 yellow USB5 amber led D21 yellow USB6 amber led D22 yellow USB7 amber led 023 green USBI green led 17 22 D24 green USB2 green led D25 green USB3 green led D26 green USB4 green led D27 green USB5 green led D28 green USB6 green led D29 green USB7 green led D30 red USB HUB global led D37 green 5V supply voltage for peripherals on the phyBASE D38 green supply voltage of the phyCARD D39 Men NE voltage for peripherals on the 17 32 D40 green 3V3 standby voltage of the phyBASE D41 green standby voltage of the phyCARD 045 y
42. multimaster high speed modules The interface of the third module is available on the phyCARD Connector Whereas the first module connects the on board PMIC U1 refer to section 4 3 and the second module connects to the on board EEPROM refer to section 7 2 The following table lists the port on the phyCARD Connector Pin Signal ISL Description X2A17 X DC 0 VDD IO Clock Output 2 17 IX DC SDA VDD IO I C Data Table 17 Interface Signal Location 9 6 SPIInterface The Serial Peripheral Interface SPI interface is a four wire bidirectional serial bus that provides a simple and efficient method for data exchange among devices 6 pins of the X Arc bus are designated to the SPI interface refer to Table 2 In addition to the four standard signals a second chip select and the SPI ready signal are provided at the X Arc bus The later signal allows to also use SPI devices with 5 wire protocol The OMAP35x contains four SPI modules The interface signals of the first module McSPI1 are made available on the phyCARD Connector This module is Master Slave configurable The OMAP35x does not provide the SPI ready signal Because of that a third chip select signal McSPII CS2 is attached to pin X2A36 instead The following table lists the SPI signals on the phyCARD Connector 44 PHYTEC Messtechnik GmbH 2010 L 751e 1 Serial Interfaces Pin Sig
43. signals which codec is supported by the phyCARD Use of this pin as an input enables to attach an external interrupt to GPIO 160 Since the OMAP35x does not support AC97 protocol the AC97 interface on phyCARD L 1s software emulated The emulation is spart of the BSP delivered with the phyCARD L PHYTEC Messtechnik GmbH 2010 L 751e 1 45 phyCARD L PCA A L1 xxx X AC97 HDA nRST is connected to GPIO 156 of the OMAP35x allowing to perform a software reset for the device attached to the interface Please also read the phyCARD Design In Guide for more information about how to use the AC 97 interface Pin Signal I O SL Description X2A42 X AC97 HDA INT SEL I O VDD IO AC 97 Interrupt Input X2A43 X 97 SDOUT O VDD IO AC 97 Transmit Output X2A44 X AC97 HDA SDIN I VDD IO AC 97 Receive Input X2B42 X AC97 HDA BITCLK VDD 10 AC 97 Clock X2B43 X 97 SYNC JO VDD IO AC97 SYNC X2B44 X AC97 HDA nRST IO AC 97 Reset Table 19 SSI Interface Signal Location 46 PHYTEC Messtechnik GmbH 2010 1 751 1 General Purpose I O 10 General Purpose I Os The X Arc bus provides 3 GPIO IRQ signals Table 20 shows the location of the GPIO IRQ pins on the phyCARD Connector as well as the corresponding ports of the OMAP35x Pin Signal SL Description GPIOO IRQO connected X2A46 X 0 VO VDD 10
44. the X Arc bus 2 46 instead of GPIO 144 GPIOO IRQO connects to GPIO 151 connects to GPIO 144 J13 J13 allows to connect GPIO 146 to the OR GPIO2 IRQ2 PWM pin of the X Arc bus 0402 X2A47 instead of GPIO 147 GPIO2 IRQ2 PWM connects to GPIO 146 mE GPIO2 IRQ2 PWM connects to 14 00 Table 21 Possible GPIO configurations 48 PHYTEC Messtechnik GmbH 2010 L 751e 1 Debug Interfaces 11 Debug Interface X1 The phyCARD L is equipped with a interface for downloading program code into the external flash internal controller RAM or for debugging programs currently executing The JTAG interface extends to a 2 0 mm pitch pin header at X1 on the edge of the module PCB Figure 9 and Figure 10 show the position of the debug interface JTAG connector X1 on the phyCARD L module
45. the phyCARD L 66 PHYTEC Messtechnik GmbH 2010 L 751e 1 Hints for Handling 16 2 Handling the phyCARD L e Modifications on the phyCARD Module Removal of various components such as the microcontroller and the standard quartz is not advisable given the compact nature of the module Should this nonetheless be necessary please ensure that the board as well as surrounding components and sockets remain undamaged while de soldering Overheating the board can cause the solder pads to loosen rendering the module inoperable Carefully heat neighboring connections in pairs After a few alternations components can be removed with the solder iron tip Alternatively a hot air gun can be used to heat and loosen the bonds Caution If any modifications to the module are performed regardless of their nature the manufacturer guarantee is voided e Integrating the phyCARD into a Target Application Successful integration in user target circuitry greatly depends on the adherence to the layout design rules for the GND connections of the phyCARD module As a general design rule we recommend connecting all GND pins neighboring signals which are being used in the application circuitry For maximum EMI performance all GND pins should be connected to a solid ground plane Note Please refer to the phyCARD Design In Guide LAN 051 for additional information layout recommendations and example circuitry PHYTEC Messtechnik GmbH 2010
46. usually assigned a single designator for its position X1 for example In this manner the phyCARD Connector comprises a single logical unit regardless of the fact that it could consist of more than one physical socketed connector The following figure illustrates the numbered matrix system It shows a phyCARD L with SMT phyCARD Connectors on its underside defined as dotted lines mounted on a Carrier Board In order to facilitate understanding of the pin assignment scheme the diagram presents a cross view of the phyCARD module showing these phyCARD Connectors mounted on the underside of the module s PCB JTAG Figure 4 Pinout of the phy CARD Connector top view with cross section insert 10 PHYTEC Messtechnik GmbH 2010 L 751e 1 Pin Description Table 2 shows the pinout of the X Arc bus with the functional grouping of the signals while Table 3 provides an overview of the pinout of the phyCARD Connector with signal names and descriptions specific to phyCARD L It also provides appropriate signal level interface voltages listed in the SL Signal Level column and the signal direction The Texas Instruments OMAP35x is a multi voltage operated microcontroller and as such special attention should be paid to the interface voltage levels to avoid unintentional damage to the microcontroller and other on board components Please refer to the Texas Instruments OMAP35x Reference Manual for details on the functions
47. 011 2 3 2 3 1 2 1010 000 2 3 1 2 2 3 1010 001 2 3 1 2 1 2 1010 110 1 2 2 3 2 3 1010 111 1 2 2 3 1 2 1010 100 1 2 1 2 2 3 1010 101 1 2 1 2 1 2 Table 9 U10 EEPROM PC address via J1 J2 and J3 i l Defaults are in bold blue text PHYTEC Messtechnik GmbH 2010 L 751e 1 33 phyCARD L PCA A L1 xxx 7 2 2 EEPROM Write Protection Control 15 Jumper J5 controls write access to the EEPROM 010 device Closing this jumper at 2 3 allows write access to the device while removing this jumper will cause the EEPROM to enter write protect mode thereby disabling write access to the device As an additional option the write protect function of the EEPROM can be controlled by software via GPIO 112 To utilize this feature jumper J5 must be closed at 1 2 The following configurations are possible EEPROM Write Protection State J5 Write access allowed 2 3 Write protect is software controlled 142 GPIO_112 Write protected open Table 10 EEPROM write protection states via J5 7 3 Memory Model There is no special address decoding device on the phyCARD L which means that the memory model is given according to the memory mapping of the OMAP35x Please refer to the OMAP35x Reference Manual for more information on the memory mapping Defaults are in bold blue text 34 PHYTEC Messtechnik GmbH 2010 L 751e 1 SD MMC Card Interfaces 8 SD MMC Card Interfaces
48. 134 27B X USBH DM I O USB HOST transceiver cable interface D 28B X USBH DP USB HOST transceiver cable interface 29B X nPWR OFF OC VCC LOGIC Power Off Open Collector Output uC port GPIO 133 30B GND Power Ground 0V 31B X SDIO DI IO LOGIC SD MMC Data line both in 1 bit and 4 bit mode PHYTEC Messtechnik GmbH 2010 L 751e 1 15 phyCARD L PCA A L1 xxx 32B X SDIO D3 VCC LOGIC SD MMC Data line both in 1 bit and 4 bit mode 33B X SDIO CMD VCC LOGIC SD MMC Command for MMC SD SDIO 34B GND Power Ground 0V 35B X SPI CSI VCC LOGIC SPI Chip select 1 36B X SPI MOSI VCC LOGIC SPI Master data out slave data in 37B X SPI MISO VCC LOGIC SPI Master data in slave data out 38B GND Power Ground 0V 39B X UART RXD I VCC LOGIC Serial data receive signal UART 40B X UART CTS I VCC LOGIC Clear to send UART 41B GND Power Ground 0V 42B X AC97 HDA BITCLK VCC LOGIC AC 97 Clock 43B X 97 SYNC LOGIC 97 SYNC 44B X AC97 HDA nRST VCC LOGIC 97 Reset 45B GND Power Ground 0V 46B X SDIO CD I VCC LOGIC SD MMC Card Detect for MMC SD SDIO uC port GPIO_ 126 47B X GPIOI IRQI IO LOGIC GPIOI IRQI nC port GPIO 145 GPIO 149 48B X RESERVED IO LOGIC Hardware Introspection Interface for internal use only 49B GN
49. 3 3 3V power supply 5 GND Ground 6 GND Ground 7 SDA Data 8 DC SCL Clock S PHYWIRE ys 10 GND Ground T SPI SS SLOTO X8A SPI chip select expansion port 0 SPI SS SLOTI X9A SPI chip select expansion port 1 12 MOSI SPI master output slave input 13 SCLK SPI clock output 14 MISO SPI master input slave output 15 8 RDY SPI data ready input master mode only 16 SLOTO IRQ X8A Interrupt input expansion port 0 SLOTI IRQ X9A Interrupt input expansion port 1 17 GND Ground 18 GND Ground 19 USB3 D X8A USB3 Data D USBA D X9A USB4 Data D 20 USB3 USB3 Data D USB4 D X9A USB4 Data D Table 46 PHYTEC expansion connector X9A 102 PHYTEC Messtechnik GmbH 2010 L 751e 1 The phyCARD L on the phyBASE 17 3 14 Secure Digital Memory Card MultiMedia Card X26 Figure 30 SD MM Card interface at connector X26 The phyCARD Carrier Board provides a standard SDHC card slot at X26 for connection to SD MMC interface cards It allows easy and convenient connection to peripheral devices like SD and MMC cards Power to the SD interface 15 supplied by sticking the appropriate card into the SD MMC slot The card slot X26 connects to the phyCARD L via a level shifter to ensure the correct voltage for the SD MMC cards PHYTEC Messtechnik GmbH 2010 L 751e 1 103 phyCARD L PCA A L1 xxx 17 3 15 Boot Mode Selection JP1 JP1 De 6922
50. 8 2 2 Gbit core SDRC Package on piii LPS eee Package C cates 0 i DSP 2 Gbit 3 EE GPMC APO 2 NAND Flash ig General Purpose i 1 32KB L1 SRAM ARM Memory Controller 64MB to 1GB NAND Flash 112KB L1 SRAM DSP NG Ethernet Controller 46 256KB L2 SRAM ARM EEPROM 1Kbit CO CDU DEN KN i B H 96KB L2 SRAM DSP USB1 Host HORE Transceiver USB OTG 64KB RAM USBO OTG e Transceiver GPIO GPIO_134 2 GPIO_133 GPIO GPIO_146 1 15 2 41V2 Power Management 1 SYS nRESPWRON 7 41V8 RESET Logic 6 43V 2 2 C Memory 32KByte A MMC SD SDIO1 4 GPIO 144 147 3 24 BitL VDS Transmitter 10 10 Bit LVDS Deserializer Ht Card Edge Connector Figure 1 Block Diagram of the phyCARD L Boot Configuration Input 10 100 Mbit Ethernet High Speed USB Host USB OTG Power State Output Wake Up Input VLogic Output 1 8 VSTBY 3V3 Power 3V3 Reset Input Reset Output Master Interface AC 97 Bus SPI Interface UART TTL SD MMC Card Interface 3 GPIO IRQ LVDS Display Interface LVDS Camera Interface JTAG Debug Test Port PHYTEC Messtechnik GmbH 2010 L 751e 1 Introduction 1 3 View of the phyCARD L
51. A SDATA IN 44A 44B 97 nRESET GND 45A 45B GND 46 2 47 48 for internal use only 49B GND 50B X Arc Bus pinout Out Out Bi Out In Out In Out Out Bi Out Out In Bi Bi In T 145 ONIN IS gt 2 j j VQOH Z460V SD MMC GPIO Boot Opt 12 PHYTEC Messtechnik GmbH 2010 1 751 1 Pin Description Note SL is short for Signal Level V and is the applicable logic level to interface a given pin Those pins marked as have a range of applicable values that constitute proper operation Please refer to the phyCARD Design In Guide LAN 051 for layout recommendations and example circuitry Pin Row X2A Pin Signal UO SL Description VDD 3V3 I Power 3 3V Primary Voltage Supply Input 2A 3V3 I Power 3 3V Primary Voltage Supply Input VDD 3V3 I Power 3 3V Primary Voltage Supply Input 4 GND Ground 0V 5A Power VCC Logic Output 6 X FEEDBACK Power Feedback Output to indicate the supply voltage required 3V3 or 5V X nRESET IN I VCC LOGIC Active low Reset In GND Power Ground 0V 9A X DIS LVDS TX0 LVDS LVDS Chanel 0 positive Output 10A DIS LVDS TXO LVDS LVD
52. ARD L PCA A L1 xxx 22 PHYTEC Messtechnik GmbH 2010 1 751 1 Power Requirements 4 Power The phyCARD L operates off of a single power supply voltage The following sections of this chapter discuss the primary power pins on the phyCARD Connector X2 in detail 4 1 Primary System Power VDD 3V3 The phyCARD L operates off of a primary voltage supply with a nominal value of 3 3V On board switching regulators generate the 1 15V 1 2V and 1 8V voltage supplies required by the OMAP35x MCU and on board components from the primary 3 3V supplied to the SBC For proper operation the phyCARD L must be supplied with a voltage source of 3 3V 5 with 1 5 A load at the VCC pins on the phyCARD Connector X2 VDD 3V3 2 2 1B 2B 3B Connect all 3 3 input pins to your power supply and at least the matching number of GND pins Corresponding GND X2 8A 13A 4B 8B 138 Please refer to section 2 for information on additional GND Pins located at the phyCARD Connector X2 Caution As a general design rule we recommend connecting all GND pins neighboring signals which are being used in the application circuitry For maximum EMI performance all GND pins should be connected to a solid ground plane PHYTEC Messtechnik GmbH 2010 1 751 1 23 phyCARD L PCA A L1 xxx 4 2 Standby Voltage VSTBY For applications requiring a standby mode a secondary voltage source of 3 3V can be attac
53. C3V3 3V3 supply voltage for peripherals on the phyBASE D40 green VCC3V3STBY 3V3 standby voltage of the phyBASE 041 VSTBY standby voltage of the phyCARD Table 33 LEDs assembled on the Carrier Board Note For powering up the phyCARD the following actions have to be done 1 Plug in the power supply connector power LEDs should light up and the phyCARD puts serial output to serial line 0 at P1 2 For powering down the phyCARD L button S2 should be pressed for a minimum time of 2000 ms 3 Press button S2 for a maximum time of 1000 ms All power LEDs should light up and the phyCARD puts serial output to serial line 0 at P1 82 PHYTEC Messtechnik GmbH 2010 1 751 1 The phyCARD L on the phyBASE Three different power states are possible RUN OFF and SUSPEND During RUN all supply voltages except VSTBY are on This means that the phyCARD L is supplied by VCC PHYCARD e In OFF state all supply voltages are turned off Only the standby voltage VCC3V3STBY of the phyBASE itself is still available to supply the PLD the RTC and to provide a high level voltage for the Reset and Power switch e SUSPEND mode only the standby voltage VSTBY for the phyCARD L and the standby voltage VCC3V3STBY of the phyBASE itself are generated This means the phyCARD L is supplied only by VSTBY The RUN and OFF state can be entered using the power button S2 as described in the gray box above It is
54. D Power Ground 0V 50B X CONFIGI I VCC LOGIC Boot Mode Input 1 Table 3 Pinout of the phy CARD Connector X2 the OMAP35x does not feature AC 97 interface The AC 97 interface of the phyCARD L is emulated with the multi channel buffered Serial Port McBSP Thus it is only available with the BSP coming with the phyCARD L can be selected by jumper refer to section 3 16 PHYTEC Messtechnik GmbH 2010 L 751e 1 Jumpers 3 Jumpers For configuration purposes the phyCARD L has 14 solder jumpers some of which have been installed prior to delivery Figure 5 illustrates the numbering of the solder jumper pads while Figure 6 and Figure 7 indicate the location of the solder jumpers on the board 10 solder jumpers are located on the top side of the module opposite side of connectors and 4 solder jumpers are located on the bottom side of the module connector side Table 4 below provides a functional summary of the solder jumpers which can be changed to adapt the phyCARD L to your needs It shows their default positions and possible alternative positions and functions A detailed description of each solder jumper can be found in the applicable chapter listed in the table Note Jumpers not listed should not be changed as they are installed with regard to the configuration of the phyCARD L 1 0 2 9 1 5 9 2 e g J9 e g J2 Figure 5 Typical jumper pad numbering scheme If manual jumper modification is
55. Interfaces See the following for details on the JTAG signal pin assignment Signal LE UE Signal A B VSUPPLY 2 1 TREF VDD IO VDD IO via 100 Ohms GND 4 3 X JTAG nTRST GND 5 X JTAG TDI GND 7 X JTAG TMS GND 10 9 X JTAG TCK GND 12 11 X JTAG RTCK GND 14 13 X JTAG TDO GND 16 15 SYS nRESPWRON GND 18 17 X JTAG EMUO GND 20 19 X JTAG EMUI 10k Ohm pulldown Table 22 JTAG connector signal assignment Note Row A ison the controller side of the module and row B ison the connector side of the module PHYTEC offers a JTAG Emulator adapter order code JA 002 for connecting the phyCARD L to a standard emulator The JTAG Emulator adapter extends the signals of the module s JTAG connector to a standard ARM connector with 2 mm pin pitch The JA 002 therefore functions as an adapter for connecting the module s non ARM compatible JTAG connector to standard Emulator connectors PHYTEC Messtechnik GmbH 2010 L 751e 1 5 phyCARD L PCA A L1 xxx 52 PHYTEC Messtechnik GmbH 2010 1 751 1 LVDS Display Interface 12 LVDS Display Interface phyCARD L uses a SN65LVDS83B 4 Channel 24 Bit LVDS Transmitter U7 to generate LVDS Signals from the parallel TTL Display Interface Thus you can connect a LVDS Display to the phyCARD L The location of the applicable interface signals X DIS LVDS 0 3 X DIS LVDS 0 3 X DIS LVDS TXCLK and X DIS LVDS
56. L 751e 1 67 phyCARD L PCA A L1 xxx 68 PHYTEC Messtechnik GmbH 2010 L 751e 1 The phyCARD L on the phyBASE 17 The phyCARD L on the phyBASE PHYTEC phyBASE Boards are fully equipped with all mechanical and electrical components necessary for the speedy and secure start up and subsequent communication to and programming of applicable PHYTEC Single Board Computer SBC modules phyBASE Boards are designed for evaluation testing and prototyping of PHYTEC Single Board Computers in laboratory environments prior to their use in customer designed applications The phyBASE supports the following features for the phyCARD L modules e Power supply circuits to supply the modules and the peripheral devices e Support of different power modes of appropriate phyCARDs Full featured 4 line RS 232 transceiver supporting data rates of up to 120 kbps hardware handshake and RS 232 connector Seven USB Host interfaces USB OTG interface 10 100 Mbps Ethernet interface Complete audio and touch screen interface LVDS display interface with separate connectors for data lines and display backlight supply voltage Circuitry to allow dimming of a backlight LVDS camera interface with for camera control Secure Digital Card Multi Media Card Interface Two expansion connectors for PHYTEC Extension Boards PEBs or customer prototyping purposes featuring one USB one and one SPI interface as well as one GPIO IRQ at either connect
57. L component placement bottom view 64 PHYTEC Messtechnik GmbH 2010 L 751e 1 Hints for Handling 16 Hints for Integrating and Handling the phy CARD L 16 1 Integrating the phy CARD M Besides this hardware manual much information is available to facilitate the integration of the phyCARD M into customer applications l 2 the design of the stamdard phyBASE Carrier Board can be used as a reference for any customer application many answers to common questions can be found at http www phytec de de support faq faq phycard m html or http www phytec eu europe support faq faq phycard m html a Design In Guide can be downloaded from the same web side It provides recommendations as to development of customized Carrier Board target hardware in which the phyCARD M and other phyCARDs can be deployed the link Carrier Board within the category Dimensional Drawing leads to the layout data as shown in Figure 14 It is available in different file formats different support packages are available to support you in all stages of your embedded development Please visite http www phytec de de support support pakete html or http www phytec eu europe support support packages html or contact our sales team for more details PHYTEC Messtechnik GmbH 2010 L 751e 1 65 phyCARD L PCA A LI xxx OO jut R Ref Des 10 45mm alle MaBe mit Toleranz von 0 1mm Figure 14 Footprint of
58. NAND Flash Ethernet 600 MHz CPU frequency at 20 These specifications describe the standard configuration of the phyCARD L as of the printing of this manual 60 PHYTEC Messtechnik GmbH 2010 L 751e 1 Technical Specifications Connectors on the phyCARD Manufacturer Molex Number of pins per contact rows 100 2 rows of 50 pins each Molex part number lead free 52885 1074 receptacle Two different heights are offered for the receptacle sockets that correspond to the connectors populating the underside of the phyCARD OMAP35x The given connector height indicates the distance between the two connected PCBs when the module is mounted on the corresponding carrier board In order to get the exact spacing the maximum component height 2 5 mm on the bottom side of the phyCORE must be subtracted Component height 6 mm Manufacturer Molex Number of pins per contact row 100 2 rows of 50 pins each Molex part number lead free 55091 1075 1074 header Component height 10 mm Manufacturer Molex Number of pins per contact row 100 2 rows of 50 pins each Molex part number lead free 53553 1079 header Please refer to the corresponding data sheets and mechanical specifications provided by Molex www molex com PHYTEC Messtechnik GmbH 2010 L 751e 1 61 phyCARD L PCA A L1 xxx 62 PHYTEC Messtechnik GmbH 2010 1 751 1 Component Placement Diagram 15 Component Placement Diagram
59. ONFIGO is left open 2 CONFIGI must not be used and should be left open It is provided for future features resistor array on the phyCARD L is used to preconfigure SYS BOOT 4 0 Customer specific assembly allows to choose other boot modes Please contact our sales team 30 PHYTEC Messtechnik GmbH 2010 L 751e 1 System Memory 7 System Memory The phyCARD L provides three types of on board memory e PoP memory device 256 MByte NAND Flash and 256 MByte LP DDR SDRAM NAND Flash 64MByte upto 1 GByte as an alternative e 4 KB up to 32 KByte The following sections of this chapter detail each memory type used on the phyCARD L 7 1 LP DDR SDRAM and NAND Flash The system memory of the phyCARD L is comprised of SDRAM and NAND Flash in a PoP Package On Package MCP Multi Chip Package or a combination of SDRAM in a POP package and NAND Flash in a VFBGA package The PoP memory devices are connected to the special SDRC and GPMC interfaces of the OMAP35x processor configured for 32 bit access and operating at the maximum frequency of 200MHz The SDRAM LPDDR memory is accessed via the SDRAM controller SDRC of the OMAP35x Typically the LP DDR SDRAM initialization is performed by a boot loader or operating system following a power on reset and must not be changed at a later point by any application code When writing custom code independent of an operating system or boo
60. S Chanel 0 negative Output DIS LVDS 2 LVDS LVDS Chanel 2 positive Output 12 DIS LVDS TX2 LVDS LVDS Chanel 2 negative Output GND Power Ground 0V 14A X_DIS_LVDS_TXCLK O LVDS LVDS Clock positive Output 15A X DIS LVDS TXCLK O LVDS LVDS Clock negative output 16A CAM LVDS MCLK VCC3V3 Clock Output for Camera Interface 17A X 2 SCL VCC LOGIC Clock Output 18A GND Power Ground 0V 19A X ETH SPEED VCC3V3 Ethernet Speed Indicator Open Drain 20A X 1 Transmit positive output normal Receive positive input reversed 21 ETH TX 1 Transmit negative output normal Receive negative input reversed 22A GND Power Ground 0V 23A X USBOTG PWR USB OTG Power switch output open drain 24A X USBOTG OC I VCC3V3 USB OTG over current input signal 25A GND Power Ground 0V 26A X USBOTG VBUS I 5V USB VBUS Voltage PHYTEC Messtechnik GmbH 2010 1 751 1 13 phyCARD L PCA A L1 xxx 27 X USBOTG DM Lo USB transceiver cable interface D 28A X USBOTG DP USB transceiver cable interface D 29 X USBOTG UID I USB on the go transceiver cable ID resistor connection 30A GND Power Ground 0V X SDIO VCC LOGIC SD MMC Data line both in 1 bit and 4 bit mode 32A X SDIO D2 VCC LOGIC SD MMC Data line both in
61. SE 17 3 7 Display Touch Connectivity X6 X32 es 5 fl Figure 26 Universal LVDS interface at connector The various performance classes of the phyCARD family allow to attach a large number of different displays varying in resolution signal level type of the backlight pinout etc In order not to limit the range of displays connectable to the phyCARD the phyBASE has no special display connector suitable only for a small number of displays The new concept intends the use of an adapter board e g phyBASE LCD interface LCD 014 to attach a special display or display family to the phyCARD A new Phytec Display Interface PDI was defined to connect the adapter board to the phyBASE It consists of two universal connectors which provide the connectivity for the display adapter They allow easy adaption also to any customer display The display data connector at X6 combines various interface signals like LVDS USB etc required to hook up a display The display power connector at X32 provides all supply voltages needed to supply the display and a backlight PHYTEC Messtechnik GmbH 2010 L 751e 1 89 phyCARD L PCA A L1 xxx 17 3 7 1 Display Data Connector X6 The display data connector at X6 40 pin FCC connector 0 5mm pitch combines various interface signals Pin Signal n
62. VDS Clock 4 I2C SDA Data 5 SCL Clock 6 RXCLK LVDS Clock 7 VCC_CAM Power supply camera 3 3V 8 GND Ground Table 40 PHYTEC camera connector X5 PHYTEC Messtechnik GmbH 2010 L 751e 1 95 phyCARD L PCA A L1 xxx 17 3 9 Audio Interface X1 X2 X3 es Figure 28 Audio interface at connectors X1 X2 X3 Depending on the audio standard supported by the phyCARD the AC 97 HDA interface on the X Arc bus connects either to a Wolfson WM 9712L audio touch controller U1 or a Cirrus Logic CS4207 U17 Audio CODEC on the Carrier Board The Wolfson audio touch controller processes AC 97 compliant signals while signals according to the HDA standard are handled by the Cirrus Logic CS4207 Audio CODEC Switches 1 and 2 of DIP Switch S3 select which codec is used to process the audio signals Table 41 shows the different options 96 PHYTEC Messtechnik GmbH 2010 L 751e 1 The phyCARD L on the phyBASE Button Setting Description S3 1 0 0 Auto Detection based on the high level of the 53 2 HDA SEL AC INT signal generated on the phyCARD the Wolfson audio touch contrl U1 is selected to process AC 97 compliant audio signals and the signals from a touch screen 0 1 Wolfson audio touch contrl U1 is selected to process AC 97 compliant audio signals and the signals from a touch screen Table 41 Selection of the audio codec As the phyCARD L features
63. a asongan nasag aana agen 9 pd i n e oid re P D 17 23 4 1 Primary System Power VDD 3 23 4 2 Standby Voltage VS TBY ue rette oe 24 43 On board Voltage Regulator 1 24 4 4 Supply Voltage for external Logic sees 26 5 Power Management eet 00000000000000 00000 e0 27 6 System Configuration and Booting 0000000000000000000000 0000000000000000 29 7 System MEMO Yoodnesossscstabid reves INE osen eu Uus 31 71 LP DDR SDRAM and 31 T 2c PC EEPROM UTO onc tie the eu 32 7 2 1 Setting the EEPROM Lower Address Bits J3 J2 J1 33 7 2 2 EEPROM Write Protection Control J5 34 T3 Memory MO siesta pa due Pawan aana debeas 34 8 SD MMC Card Interfaces etes rp 00000000000000 00000000000000 00000000 35 9 Serial 37 9 1 Universal Asynchronous Interface esses 38 9 2 USB OTG Transceiver U T6 iate iecit ie etui ter 39 9 3 USB Host Transceiver 157 40 9 4 Ethernet Interface oO OR d eee 41 94 11 Ethernet Controller 012 41 9 4 2 Software Reset of the Ethernet Controller J10 43 OAS
64. able 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 SPI Interface Signal Location sees 45 SSI Interface Signal Location denotat o o ep petto 46 Location of GPIO and IRQ pins 2 47 Possible GPIO 48 JTAG connector signal assignment 51 Display Interface Signal 59 Pixel mapping of 18 bit LVDS display interface 54 Pixel mapping of 24 bit LVDS display interface 55 Camera Interface Signal Location sess 57 LVDS signal configuration J6 sse 58 phyBASE Connectors and Pin 72 phyBASE push buttons descriptions sss 73 phyBASE DIP Switch S3 75 phyBASE LEDS deseriptions eee 76 phyBASE jumper 79 LEDs assembled on the Carrier 82 Distribution of the USB hub s 04 87 Universal USB pin header X33 signal description 87 Display data connector signal description 9
65. ace with its LED signals extends to phyCARD Connector X2 Pin Signal SL Description 2 19 ETH SPEED O VDD 3V3 Ethernet Speed Indicator Open Drain X2A20 X ETH O I VDD 3V3 Transmit positive output normal Receive positive input reversed X2A21 X ETH TX I VDD 3V3 Transmit negative output normal Receive negative input reversed X2B19 ETH LINK VDD 3V3 Ethernet Speed Indicator Open Drain 2 20 X ETH I O VDD 3V3 Receive positive input normal Transmit positive output reversed X2B21 X ETH RX I O VDD 3V3 Receive negative input normal Transmit negative output reversed Table 15 Location of the Ethernet signals PHYTEC Messtechnik GmbH 2010 L 751e 1 41 phyCARD L PCA A L1 xxx The Ethernet controller s integrated PHY supports HP Auto MDIX technology eliminating the need for the consideration of a direct connect LAN cable or a cross over patch cable It detects the TX and RX pins of the connected device and automatically configures the PHY TX and RX pins accordingly The Ethernet controller also features an Auto negociation to automatically determine the best speed and duplex mode The Ethernet controller is connected to chip select CS5 of the General Purpose Memory Controller GPMC Please refer to the OMAP35x Reference Manual for more informat
66. ame Description 1 SCLK SPI 1 clock 2 SPI MISO SPI 1 Master data in slave data out 3 MOSI SPI 1 Master data out slave data in 4 SPII SS DISP SPI 1 Chip select display 5 DISP IRQ Display interrupt input 6 VCC3V3 Power supply display 7 DC SCL Clock Signal 8 SDA Data Signal 9 GND Ground 10 LS BRIGHT PWM brightness output 11 VCC3V3 Power Supply Display 12 PWR KEY Power on off Button 13 DISP ENA Display enable signal aia a 15 GND Ground 16 USB2 USB2 data 17 USB2 D USB2 data 18 GND Ground 19 TXOUTO LVDS data channel 0 negative output 20 TXOUTO LVDS data channel 0 positive output 21 GND Ground 22 TXOUTI LVDS data channel 1 negative output 23 TXOUTI1 LVDS data channel 1 positive output 24 GND Ground 20 LEDs D17 and D24 signal use of the USB interface 90 PHYTEC Messtechnik GmbH 2010 L 751e 1 The phyCARD L on the phyBASE 25 TXOUT2 LVDS data channel 2 negative output 26 TXOUT2 LVDS data channel 2 positive output 27 GND Ground 28 TXOUT3 LVDS data channel 3 negative output 29 TXOUT3 LVDS data channel 3 positive output 30 GND Ground 31 TXCLKOUT LVDS clock channel negative output 32 TXCLKOUT LVDS clock channel positive output 33 GND Ground 34 TP Touch 35 TP X Touch 36 TP Y Touch 37 TP Y Touch 38 TP WP Touch 39 GND Ground 40 LS ANA Light sensor Analog Input Table 36 Display da
67. amera 10k signals 0805 2 3 fallng edge strobe used for the LVDS camera signals Table 27 LVDS signal configuration J6 58 PHYTEC Messtechnik GmbH 2010 L 751e 1 Technical Specifications 14 Technical Specifications The physical dimensions of the phyCARD L are represented in Figure 11 The module s profile is max 11 4 mm thick with a maximum component height of 5 0 mm on the bottom connector side of the PCB and approximately 5 0 mm on the top microcontroller side The board itself is approximately 1 4 mm thick 4 60mm i 4mm gt 52mm phyCARD L E E EE D L Figure 11 Physical dimensions Note To facilitate the integration of the phyCARD M into your design the footprint of the phyCARD M 15 available for download see section 16 1 PHYTEC Messtechnik GmbH 2010 L 751e 1 59 D2 7mm phyCARD L PCA A L1 xxx Additional specifications Dimensions 60 mm x 60 mm Weight approximately 16 g with all optional components mounted on the circuit board Storage temperature 40 C to 125 C Operating temperature 0 C to 70 C commercial 20 C to 85 C industrial Humidity 95 r F not condensed Operating voltage VCC 3 3V Power consumption 1 t b d watts Conditions VCC 33 V VSTBY 0 V 256MB LP DDR RAM 256MB
68. andom Lock Deserializer U8 to receive LVDS Signals from a LVDS Camera Interface The LVDS Deserializer converts the LVDS signal to a 10 bit wide parallel data bus and separate clock which can be used as inputs for the OMAP35x Camera Sensor Interface The 10 bit wide data bus consists of 8 color information bits and 2 sync bits HSYNC VSYNC The following table shows the location of the applicable interface signals X CAM LVDS MCLK X CAM LVDS nLOCK X CAM LVDS RAT X CAM LVDS RX on phyCARD Connector Pin Signal SL Description X2A16 X LVDS MCLK o VDD 10 Clock output for x Camera Interface LVDS Receive 2 14 CAM LVDS RAT LVDS Input for Camera LVDS Receive X2BI5 X CAM LVDS RX LVDS negative Input for Camera Lock output for X2B16 CAM LVDS nLOCK O VDD IO Camera Interface Table 26 Camera Interface Signal Location To assists the implementation of a power managment the Deserializer s REN input is connected to GPIO 167 of the OMAP35x Therefore the LVDS Deserializer can be turned off by software PHYTEC Messtechnik GmbH 2010 L 751e 1 57 phyCARD L PCA A L1 xxx 13 1 Signal configuration J6 76 selects rising or falling edge strobe for the LVDS Deserializer at U8 used for the display connectivity of the phyCARD L Position Description Type 1 2 rising edge strobe used for LVDS c
69. ations for the controller populating the board can be found in the applicable controller Reference Manual or datasheet The descriptions in this manual are based on the Texas Instruments OMAP35x No description of compatible microcontroller derivative functions 1s included as such functions are not relevant for the basic functioning of the phyCARD L The phyCARD L offers the following features Subminiature Single Board Computer 60 x 60 mm achieved through modern SMD technology e Populated with the Texas Instruments OMAP35x microcontroller CBB package with 515 balls and package on package PoP memory option Improved interference safety achieved through multi layer technology and dedicated ground pins X Arc bus including commonly used interfaces such as Ethernet USB UART SPI audio display and camera connectivity both LVDS available at one 100 pin high density 0 635 mm Molex connector enabling the phyCARD L to be plugged like a big chip into target application Max 600 MHz core clock frequency Boot from NAND Flash PoP memory device with 256 MByte NAND Flash and 256 MByte LP DDR SDRAM Please contact PHY TEC for more information about additional module configurations 2 PHYTEC Messtechnik GmbH 2010 L 751e 1 Introduction 1 alternatively up to 1 GByte NAND Flash VFBGA up to 32kB EEPROM Serial interface with 4 lines TTL allowing simple hardware handshake
70. aution Please pay special attention to the Signal Level SL column in the following tables Some of the serial interfaces signal level is VDD IO which is 1 8V and which is not identical with the voltage level of the primary supply voltage of the phyCARD L When connecting these interfaces to external devices level shifters supplied with VDD IO X245 and X2B5 at one of the supply rails should be used 5 Since the OMAP35x does not support AC 97 protocol the AC 97 interface on the phyCARD L is software emulated The emulation is part of the BSP delivered with the phyCARD L PHYTEC Messtechnik GmbH 2010 L 751e 1 37 phyCARD L PCA A L1 xxx Please refer to phyCARD Design In Guide LAN 051 for more information about using the serial interfaces of the phyCARD L in customer applications 91 Universal Asynchronous Interface The phyCARD L provides a high speed universal asynchronous interface with up to 3 6 Mbit s and hardware flow control RTS and CTS signals The following table shows the location of the signals on the phyCARD Connector Signal I O SL Description Serial transmit signal X2A39 X UART TXD O VDD IO UART 3 X2A40 X UART RTS O vpp _ Request to send gt UART 3 Serial data receive X2B39 X UART VDD IO signal UART 3 X2B40 X UART CTS I VDD IO Clear to send UART 3 Table 12 Location of the UART signals The signals extend from UART3 of the OMAP35x
71. ce is 1 8V Thus integration of an SD MMC card slot on custom target hardware requires level shifters supplied with VDD IO X2A5 and X2B5 at one of the supply rails Please refer to the chapter SD MMC in the phyCARD Design In Guide for more information about connecting an SD MMC Card slot to the phyCARD L 36 PHYTEC Messtechnik GmbH 2010 L 751e 1 Serial Interfaces 9 Serial Interfaces The phyCARD L provides seven serial interfaces some of which are equipped with a transceiver to allow direct connection to external devices 1 High speed UART TTL derived UART3 of the OMAP35x with up to 3 6 Mbit s and hardware flow control RTS and CTS signals 2 High speed USB OTG interface consisting of OMAP35x USB interface and an additional USB transceiver 3 High speed USB HOST interface based on the OMAP35x USB Host interface and an additional USB transceiver 4 enabled 10 100 Ethernet interface implemented with an Ethernet controller attached to the OMAP35x GPMC interface 5 interface derived from third port of the OMAP35x 6 Serial Peripheral Interface SPI interface extended from the first SPI module of the OMAP35x 7 Synchronous Serial Interface SSI with AC 97 support originating from the synchronous serial interface McBSP of the OMAP35x The following sections of this chapter detail each of these serial interfaces and any applicable configuration jumpers C
72. compliant audio signals 0 1 Wolfson audio touch contrl U1 is selected to process the signals from a touch screen and the AC 97 compliant audio signals Table 39 Selection of the touch screen controller As the phyCARD L features an AC 97 compliant audio interface Wolfson WM9712L audio touch codec must be chosen to process the touch screen signals The touch screen data is then available at the AC 97 interface An interrupt output GPIO2 IRQ or the pendown signal of the WM9712L selected by jumper Jl refer to section 17 2 4 is connected to AC 97 interrupt HAD SEL AC INT pin X2A42 The default configuration selects the pendown signal to be attached to pin X2A42 of the phyCARD Connector To use the interrupt jumper J1 must be closed at 2 3 instead 2 Since the OMAP35x does not support the AC 97 protocol the AC 97 interface on the phyCARD L is software emulated The emulation is part of the BSP delivered with the phyCARD L 94 PHYTEC Messtechnik GmbH 2010 1 751 1 The phyCARD L on the phyBASE 17 3 8 Camera Interface X5 De Figure 27 Camera interface at connectors X5 The phyCARD L has a camera interface This interface extends from the phyCARD Connector to the RJ45 socket X5 on the Board The table below shows the pinout of connector X5 Pin Signal Name Description 1 RXIN LVDS Input 2 RXIN LVDS Input 3 RX CLK L
73. d the functionality without expanding the physical dimensions Mounting wholes can be used to screw the additional PCBs to the phyBASE 7 PHYTEC offers variaty of expansion boards PEBs to add new features such as CAN additional GPIOs or Ethernet etc Please visit our web side or contact our sales team 100 PHYTEC Messtechnik GmbH 2010 L 751e 1 The phyCARD L on the phyBASE The expansion connectors share the SPI interface and the GPIOs of the X Arc bus with the display data connector X6 Therefore switches 7 and 8 of DIP Switch S3 must be configured to map the signals to the desired connector Button Setting Description S3 7 0 0 550 0 IRQ gt expansion 0 X8A S3 8 SSI GPIO1 IRQ gt expansion 1 X9A 0 1 SSO GPIOO gt expansion 0 X8A SS1 GPIO1 IRQ gt display data connector X6 1 SSO GPIOO gt expansion 1 X9A SSI GPIOI IRQ gt display data connector X6 Table 45 SPI and GPIO connector selection GPIOO IRQ GPIO 144 and 1 GPIO 145 of the OMAP35x both GPIOs can be assigned to other inputs by changing jumpers J11 and J12 refer to section 10 PHYTEC Messtechnik GmbH 2010 L 751e 1 101 phyCARD L PCA A L1 xxx Pin Signal Name Description 1 VCCSV 5V power supply 2 VCCS5V 5V power supply 3 VCC3V3 3 3V power supply 4 VCC3V
74. der jumper these types of jumpers require solder equipment to remove and place JP Solderless jumper these types of jumpers can be removed and placed by hand with no special tools PCB Printed circuit board PEB PHYTEC Extension Board POR Power on reset RTC Real time clock SBC Single Board Computer used in reference to the PCA A L X phyCARD A L1 Single Board Computer SMT Surface mount technology Sx User button Sx e g 51 S2 etc used in reference to the available user buttons or DIP Switches on the Carrier Board Sx y Switch y of DIP Switch Sx used in reference to the DIP Switch on the Carrier Board VSTBY SBC standby voltage input Table 1 Abbreviations and Acronyms used in this Manual Note The BSP delivered with the phyCARD L usually includes drivers and or software for controlling all components such as interfaces memory etc Therefore programming close to hardware at register level is not necessary in most cases For this reason this manual contains no detailed description of the controller s registers or information relevant for software development Please refer to the OMAP35x Reference Manual if such information is needed to connect customer designed applications viii PHYTEC Messtechnik GmbH 2010 L 751e 1 Preface Preface As a member of PHYTEC s new phyCARD product family the phyCARD L is one of a series of PHYTEC Single Board Computers SBCs that can be populated with different c
75. e power management into your design Caution According to the specification for the phyCARD family writing custom software to utilize pins X nSUSP RAM and X nPWR OFF requires them to be configured as Open Collector Output Use of the power management features of the PMIC at U1 allows for a higher granularity in control of the power consumption To implement power management with the PMIC it can be programmed an interface TPS65023 can be accessed at address 0x90 0x91 write read Please refer to TPS65023 User s Guide for more information 28 PHYTEC Messtechnik GmbH 2010 1 751 1 Start Up System Configuration 6 System Configuration and Booting Although most features of the OMAP35x microcontroller are configured and or programmed during the initialization routine other features which impact program execution must be configured prior to initialization via pin termination The system start up configuration includes Clock PLL configuration Boot device select and boot sequence configuration During the reset cycle the operational system boot mode of the OMAP35x processor is determined by the configuration of the seven external input pins SYS BOOTY 6 0 Six external pins SYS 5 0 are used to select interfaces or devices for booting Where SYS 5 switches between memory 0 and peripheral 1 booting and SYS 4 0 define the booting sequence of the interface
76. ellow SSI interface compliant with the AC 97 standard 1739 D46 green SSI interface compliant with the HDA standard Table 31 phyBASE LEDs descriptions 76 PHYTEC Messtechnik GmbH 2010 L 751e 1 The phyCARD L on the phyBASE Note Detailed descriptions of the assembled connectors jumpers and switches can be found in the following chapters 17 2 4 Jumpers The phyCARD Carrier Board comes pre configured with 2 removable jumpers JP and 3 solder jumpers J The jumpers allow the user flexibility of configuring a limited number of features for development constraint purposes Table 32 below lists the 5 jumpers their default positions and their functions in each position Figure 16 depicts the jumper pad numbering scheme for reference when altering jumper settings on the development board Figure 17 provides a detailed view of the phyBase jumpers and their default settings In this diagrams a beveled edge indicates the location of pin 1 Before making connections to peripheral connectors it is advisable to consult the applicable section in this manual for setting the associated jumpers HE 1 2 e g e g Jl e g JP2 Figure 16 Typical jumper numbering scheme Table 32 provides a comprehensive list of all Carrier Board jumpers The table only provides a concise summary of jumper descriptions For a detailed description of each jumper see the applicable chapter listing in the right
77. ending on the audio standard supported by the phyCARD the audio and touch panel signals are either processed by the Wolfson audio touch contrl at U1 AC 97 or the Cirrus Logic Audio CODEC at U17 HDA and a dedicated touch contrl at U28 Switches 1 and 2 of DIP Switch S3 select which device processes the audio and touch panel signals Auto Detection based on the high level of the SEL AC INT signal generated on phyCARD the Wolfson audio touch contrl U1 is selected to process AC 97 compliant audio signals and the signals from a touch screen Wolfson audio touch contrl U1 is selected to process AC 97 compliant audio signals and the signals from a touch screen TAA 17 3 9 S3 3 S3 4 0 0 Switches 3 and 4 of DIP Switch S3 configure the address for the communication between CPLD and phyCARD CPLD Address 0x80 S3 5 Switch 5 of DIP Switch S3 selects the interface used for the communication between CPLD and phyCARD communication selected S3 6 Switch 6 of DIP Switch S3 turns the SPI Multiplexer on or off SPI multiplexer off 74 PHYTEC Messtechnik GmbH 2010 L 751e 1 The phyCARD L on the phyBASE Switches 7 and 8 of DIP Switch S3 map the two slave select signals of the SPI interface and the two GPIO IRQ signals GIOO IRQ IRQ to two of the three available connectors 17 3 7 1 S3 7 LXI S3 8 0 0 SS0 GPIOO gt
78. er 17 3 7 3 at U1 is connected to AC 97 interrupt GPIO2 output of the Audio Touch controller at Ul connected to AC 97 interrupt 2 3 Jumper J2 configures the address of LED dimmer at U21 17 35 72 closed C device address of LED dimmer set to 0xC0 173 10 open device address of LED dimmer set to 0 2 J2 Jumper 13 configures the address of the touch screen controller at U28 7373 17 3 10 1 2 device address set to 0x88 2 3 device address set to 0x82 Table 32 phyBASE jumper descriptions please see section Fehler Verweisquelle konnte nicht gefunden werden for more information on the different boot modes Default settings are in bold blue text PHYTEC Messtechnik GmbH 2010 L 751e 1 79 phyCARD L PCA A L1 xxx 17 3 Functional Components on the phyBASE Board This section describes the functional components of the phyBASE Carrier Board supporting the phyCARD L Each subsection details a particular connector interface and associated jumpers for configuring that interface 17 3 1 phyCARD L SBC Connectivity X27 x 5 9 8 t lt Figure 18 phyCARD L SBC Connectivity to the Carrier Board Connector X27 on the Carrier Board provides the phyCARD Single Board Computer connectivity The connector is keyed for proper insertion of the SBC Figure 18 above shows the location of connec
79. fines the pixel mapping of the LVDS display interface The pixel mapping equates to the OpenLDI respectively Intel 24 0 standard Thus you can connect 18 bit as well as 24 bit LVDS displays to the phyCARD Table 24 and Table 25 show the recommended pixel mapping of the LVDS display For further information please see the phyCARD Design Guide Note Make sure that the LVDS display you want to use provides the same pin mapping as the phyCARD Normally this is only important for 24 bit LVDS displays because due to the organization of the LVDS pixel mapping all common 18 bit LVDS displays should work 18 bit LVDS Display 1 2 3 4 5 7 CLK 1 1 0 0 0 1 1 0 GO R5 R4 R3 R2 R1 RO AI Bl BO G5 G4 G3 G2 Gl A2 DE VSYNC HSYNC B5 B4 B3 B2 A3 0 0 0 0 0 0 0 Table 24 Pixel mapping of 18 bit LVDS display interface 54 PHYTEC Messtechnik GmbH 2010 1 751 1 LVDS Display Interface 24 bit LVDS Display 1 2 3 4 5 6 7 1 1 0 0 0 1 1 0 G2 R7 R6 R5 4 R3 R2 AI B3 B2 G7 G6 G5 G4 G3 A2 DE VSYNC HSYNC B7 B6 B5 B4 A3 0 Bl BO Gl GO RI RO Table 25 Pixel mapping of 24 bit LVDS display interface PHYTEC Messtechnik GmbH 2010 L 751e 1 92 phyCARD L PCA A L1 xxx 56 PHYTEC Messtechnik GmbH 2010 L 751e 1 LVDS Camera Interface 13 LVDS Camera Interface phyCARD L uses a DS92LV1212A l channel 10 Bit LVDS R
80. for doing so Copyright 2010 PHYTEC Messtechnik GmbH D 55129 Mainz Rights including those of translation reprint broadcast photomechanical or similar reproduction and storage or processing in computer systems in whole or in part are reserved No reproduction may occur without the express written consent from PHYTEC Messtechnik GmbH EUROPE NORTH AMERICA Address PHYTEC Technologie Holding PHYTEC America LLC Robert Koch Str 39 203 Parfitt Way SW Suite G100 D 55129 Mainz Bainbridge Island WA 98110 GERMANY USA Ordering 49 800 0749832 1 800 278 9913 Information order phytec de sales phytec com Technical 49 6131 9221 31 1 800 278 9913 Support support phytec de support phytec com Fax 49 6131 9221 33 1 206 780 9135 Web Site http www phytec de http www phytec com 1 Edition December 2010 PHYTEC Messtechnik GmbH 2010 L 751e 1 Contents List of BIBUEES DIU d PUN iii Eist f Tables acute xin stie inti on rbi iv Conventions Abbreviations and 8 1 1 vii Prela6e oie anan genah iang Hii RM iN edid ix 1 Introduction o edis e Rep te P 1 Mel Block ettet ee Bu e V 4 12 View of the phyCARD L este decet rettet ett 5 1 3 Minimum Requirements to Operate the phyCARD L 7 2 Pin Descrip asian cio cine ananeng aan
81. hand column of the table If manual modification of the solder jumpers is required please ensure that the board as well as surrounding components and sockets remain undamaged while de soldering Overheating the board can cause the solder pads to loosen rendering the board inoperable Carefully heat neighboring connections in pairs After few alternations PHYTEC Messtechnik GmbH 2010 L 751e 1 77 phyCARD L PCA A L1 xxx components can be removed with the solder iron tip Alternatively a hot air gun can be used to heat and loosen the bonds 5100 J28 Figure 17 phyBASE jumper locations The following conventions were used in the Jumper column of the jumper table Table 32 J solder jumper JP removable jumper 78 PHYTEC Messtechnik GmbH 2010 L 751e 1 The phyCARD L on the phyBASE See Jumper Setting Description Section Jumper 1 1 selects the boot device of the phyCARD L open Memory Boot NAND USB UART3 MMCI 17 3 15 142 Peripheral Boot USB UART3 MMCI NAND other settings must not be used with the phyCARD L Jumper JP2 connects the input voltage to connector X32 as supply voltage for a backlight JP2 7 3 7 2 open VCC12V Backlight disabled VCC12V Backlight connected to power supply closed Only 12V DC power supplies allowed Jumper Jl selects the function of the AC 97 interrupt Jl 1 2 Pendown signal of the Audio Touch controll
82. hed to the phyCARD L at pin X2B6 This voltage source 15 supplying the core and on chip peripherals of the OMAP35x e g on chip memory multimedia accelerator USB controller etc as well as the PoP memory devices SDRAM NAND Flash while the primary system power VDD 3V3 is removed Applications not requiring a standby mode can connect the VSTBY pin to the primary system power supply 3 3V or can leave it open 4 3 On board Voltage Regulator U1 The phyCARD L provides an on board switching regulator U1 to source the four different voltages 1 15V 1 2V and 1 8V required by the processor and on board components Figure 6 presents a graphical depiction of the powering scheme The switching regulator has a single input voltage rail VDD BKUP as can be seen in Figure 8 VDD BKUP is supplied from the primary voltage input pins VDD 3V3 and the secondary voltage input pin VSTBY Not all devices on the phyCARD L are supplied from the switching regulator Some such as the Ethernet Controller the LVDS Transmitter etc are directly connected to the primary voltage input pins VDD 3V3 The following list summarizes the relation between the different voltage rails and the devices on the phyCARD L External voltages VDD 3V3 and VSTBY optional e VDD 3V3 Ethernet Controller LVDS Transmitter LVDS Deserializer e VDD 3V3 or VSTBY VDD BKUP Voltage Regulator 24 PHYTEC Messtechnik GmbH 2010 1 751 1 Power Requirements
83. ion on how to configure the address space for CS5 etc In order to connect the module to an existing 10 100Base T network some external circuitry is required The required 49 9 Ohm 1 termination resistors on the analog signals ETH TAH are already populated on the module Connection to an external Ethernet magnetics should be done using very short signal traces The TPI TPI and TPO TPO signals should be routed as 100 Ohm differential pairs The same applies for the signal lines after the transformer circuit The carrier board layout should avoid any other signal lines crossing the Ethernet signals An example for the external circuitry is shown in the phyCARD s Design Guide If you are using the applicable Carrier Board for the phyCARD L part number PBA A 01 the external circuitry mentioned above is already integrated on the board refer to section 17 3 4 Caution Please see the datasheet of the Ethernet controller as well as the phyCARD s Design Guide LAN 051 when designing the Ethernet transformer circuitry 42 PHYTEC Messtechnik GmbH 2010 1 751 1 Serial Interfaces 9 4 2 Software Reset of the Ethernet Controller J10 The Ethernet controller at U12 can be reset either by hardware or software reset The reset input of the Ethernet controller 15 permanently connected to the global reset signal of the phyCARD L which can be performed by either the on board switching regulator at Ul or
84. ith ST 24W32C non volatile 4 KByte EEPROM with an PC interface at U10 This memory can be used to store configuration data or other general purpose data This device is accessed through PC port 2 on the OMAP35x The control registers for PC port 2 are mapped between addresses 0x4807 2004 and 0 4807 2054 Please see the OMAP35x Reference Manual for detailed information on the registers See the manufacturer s data sheet for interfacing and operation 32 PHYTEC Messtechnik GmbH 2010 1 751 1 System Memory Three solder jumpers are provided to set the lower address bits J1 J2 and J3 Refer to section 7 2 1 for details on setting these jumpers Write protection to the device is accomplished via jumper J5 Refer to section 7 2 2 for further details on setting this jumper 7 2 11 Setting the EEPROM Lower Address Bits 43 J2 J1 The 4 KB PC EEPROM populating U10 on the phyCARD L module has the capability of configuring the lower address bits A0 A1 and A2 The four upper address bits of the device are fixed at 10107 see ST 24W32C data sheet The remaining three lower address bits of the seven bit PC device address are configurable using jumpers J1 J2 and J3 J3 sets address bit 0 J2 address bit Al and Jl address bit A2 Table 9 below shows the resulting seven bit PC device address for the eight possible jumper configurations U10 PC Device Address Jl J2 J3 1010 010 243 243 243 1010
85. jor advantage is the forgone risk of potential system hardware redesign steps caused by processor or other critical component discontinuation Just use one of PHYTEC s other phyCARD SBCs thereby ensuring an extended product life cycle of your embedded application PHYTEC Messtechnik GmbH 2010 L 751e 1 ix phyCARD L PCA A L1 xxx Production ready Board Support Packages BSPs and Design Services for our hardware will further reduce your development time and risk and allow you to focus on your product expertise Take advantage of PHYTEC products to shorten time to market reduce development costs and avoid substantial design issues and risks With this new innovative full system solution you will be able to bring your new ideas to market in the most timely and cost efficient manner For more information go to http www phytec com services Ordering Information The part numbering of the phyCARD has the following structure PCA A L1 xxxxxx Generation A First generation Performance class S small middle L large XL largest Controller No of specified performance class Assembly options depending on model In order to receive product specific information on changes and updates in the best way also in the future we recommend to register at http www phytec de de support registrierung html You can also get technical support and additional information concerning your product X
86. nal SL Description X2A35 X SPI CS0 VDD IO Chip select 0 X2B35 X SPI CS1 IO Chip select 1 X2A36 X SPI RDY IO Chip select 2 X2A37 X SPI VDD IO clock X2B36 SPI MOSI I O VDD IO McSPI1 Master data out slave data in X2B37 SPI MISO I O VDD IO McSPI1 Master data in slave data out Table 18 Interface Signal Location 9 77 Synchronous Serial Interface SSI The multi channel buffered Serial Port McBSP interface of the phyCARD L is a full duplex serial interface that allows to communicate with a variety of serial devices such as standard codecs digital signal processors DSPs microprocessors peripherals and popular industry audio codecs that implement the inter IC sound bus standard 1 5 and Intel AC 97 standard The OMPA35x provides five instances of the MCBSP module On the phyCARD L McBSP2 is brought out to the phyCARD Connector With reference to the X Arc bus specification the main purpose of this interface is to connect to an external codec such as AC 97 Four signals extend from the OMAP35x McBSP module to the phyCARD Connector X AC97 HDA SDOUT X 97 SDIN X 97 BITCLK X 97 SYNC X 97 INT SEL and X AC97 HDA nRST are two additional pins assisting the functionality of this interface X AC97 HDA INT SEL is used as input and output As output it
87. nd 4 VCCS5V 5V power supply display 5 GND Ground 6 VCCS5V 5V power supply display 7 GND Ground 8 VCCS5V 5V power supply display 9 GND Ground 10 LS BRIGHT PWM brightness output 11 VCCI2V BL 12V Backlight power supply 12 VCCI2V BL 12V Backlight power supply Table 38 LVDS power connector X32 signal description 2 GPIOO IRQO 4 GPIO 144 and 1 1801 GPIO 145 of the OMAP35x both GPIOs be assigned to other inputs by changing jumpers J11 and J12 refer to section 10 92 PHYTEC Messtechnik GmbH 2010 1 751 1 The phyCARD L on the phyBASE The PWM signal at pin 10 can be used to control the brightness of a display s backlight It 15 generated by an LED dimmer The LED dimmer is connected to the bus at address 0xCO write and read To make VCC12V BL available at X32 jumper JP2 must be closed Caution There is no protective circuitry for the backlight Close jumper JP2 only if a 12 V power supply is connected to X28 as primary supply for the phyBASE 17 3 7 3 Touch Screen Connectivity As many smaller applications need a touch screen as user interface provisions are made to connect 4 or 5 wire resistive touch screens to the display data connector X6 pins 34 38 refer to Table 36 Two touch screen controllers are available on the phyCARD Carrier Board The Wolfson WM9712L audio touch codec at Ul allows connecting 4 and 5 wire touch panels whereas STMPE811 touch panel co
88. ntroller at U28 is suitable for 4 wire touch panels only Because of the dual functionality of the Wolfson audio touch controller the choice which controller is chosen to handle the signals from the touch screen is pegged to the audio standard supported by the phyCARD For phyCARDs supporting the AC 97 standard the Wolfson WM9712L audio touch controller processes the touch panel signals For phyCARDs delivering HDA compliant audio signals the dedicated touch panel controller at U28 STMPE811 must be selected Switches 1 and 2 of DIP Switch S3 select which controller 15 used to process the touch panel signals The different configurations are shown in Table 39 2 Default address Jumper 12 allows to select a 2 write and OxC3 read alternatively refer to Table 32 PHYTEC Messtechnik GmbH 2010 L 751e 1 93 phyCARD L PCA A L1 xxx Button Setting Description S3 1 Depending on the audio standard supported by the e 2 phyCARD the audio and touch panel signals are either E processed by the Wolfson audio touch contrl at Ul AC 97 or the Cirrus Logic Audio CODEC at 017 HDA and a dedicated touch contrl at U28 Switches 1 and 2 of DIP Switch S3 select which device processes the audio and touch panel signals 0 0 Auto Detection based on the high level of the HDA SEL AC INT signal generated on the phyCARD the Wolfson audio touch contrl U1 is selected to process the signals from a touch screen and the AC 97
89. oard devices must considered Some of the addresses can be configured by jumper Table 43 lists the addresses already in use The table shows only the default address Please refer to section 17 2 4 for alternative address settings Device Address used write read Jumper LED dimmer U21 0 0 1 J2 RTC U3 0xA2 0x A3 A D converter U22 0 8 OxC9 Touch screen controller 0x88 0x89 J3 U28 CPLD U25 0x80 0x81 S3 3 53 4 Table 43 PC addresses use 98 PHYTEC Messtechnik GmbH 2010 L 751e 1 The phyCARD L on the phyBASE 17 3 11 SPI Connectivity The SPI interface of the X Arc bus is available at the expansion connectors X8A and X9A as well as at the display data connector X6 refer to sections 17 3 7 1 and 17 3 13 to see the pinout Due to the X Arc bus specification only two slave select signals are available Because of that the CPLD maps the SPI interface to two of the connectors depending on the configuration of switches 7 and 8 of DIP Switch S3 The table below shows the possible configurations Button Setting Description S3 7 0 0 550 0 IRQ gt expansion 0 X8A S3 8 SSI GPIO1 expansion 1 X9A 0 1 SSO GPIOO gt expansion 0 X8A SS1 GPIO1 IRQ gt display data connector X6 SSO GPIOO gt expansion 1 X9A SSI GPIO1 IRQ gt display data connector X6 Table 44
90. ontrollers and hence offers various functions and configurations PHYTEC supports a variety of 8 16 and 32 bit controllers in two ways 1 the basis for Rapid Development Kits which serve as a reference and evaluation platform 2 insert ready fully functional phyCARD OEM modules which can be embedded directly into the user s peripheral hardware design Implementation of an OEM able SBC subassembly as the core of your embedded design allows you to focus on hardware peripherals and firmware without expending resources to re invent microcontroller circuitry Furthermore much of the value of the phyCARD module lies in its layout and test PHYTEC s new phyCARD product family consists of a series of extremely compact embedded control engines featuring various processing performance classes while using the newly developed X Arc embedded bus standard The standardized connector footprint and pin assignment of the X Arc bus makes this new SBC generation extremely scalable and flexible This also allows to use the same carrier board to create different applications depending on the required processing power With this new SBC concept it is possible to design entire embedded product families around vastly different processor performances while optimizing overall system cost In addition future advances in processor technology are already considered with this new embedded bus standard making product upgrades very easy Another ma
91. oo NS guj 2 B ue ol lo md 2 el 5 F on co Hg d N i D Sci ggg pue M V m Figure 2 view of the phyCARD L controller side PHYTEC Messtechnik GmbH 2010 L 751e 1 5 phyCARD L PCA A LI xxx go 5 TERS i p o a a oo Po on pak UU
92. or DIP Switch to configure various interface options e Jumper to configure the boot options for the phyCARD L module mounted with battery supply backup PHYTEC Messtechnik GmbH 2010 L 751e 1 69 phyCARD L PCA A L1 xxx 17 1 Concept of the phyBASE Board The phyBASE Carrier Board provides a flexible development platform enabling quick and easy start up subsequent programming of the phyCARD Single Board Computer module The Carrier Board design allows easy connection of additional expansion boards featuring various functions that support fast and convenient prototyping and software evaluation The Carrier Board is compatible with all phyCARDs This modular development platform concept following components e the phyCARD L module populated with the OMAP35x processor and all applicable SBC circuitry such as DDR SDRAM Flash PHYs and transceivers to name a few e the phyBASE which offers all essential components and connectors for start up including a power socket which enables connection to an external power adapter interface connectors such as DB 9 USB and Ethernet allowing for use of the SBC s interfaces with standard cable The following sections contain specific information relevant to the operation of the phyCARD L mounted on the phyBASE Carrier Board Note Only features of the phyBASE which are supported by the phyCARD L are described Jumper settings and configurations which are not
93. ors whereas Table 35 shows the pinout of USB host connector X33 USB hub port Connector Connector Type USBI USBS 33 9 pin header row see table below 40 pin FCC pins 16 D and USB2 X6 17 20 pin header row pins 19 D 557 and 20 DH 20 pin header row pins 19 D and 20 DH USB6 bottom USBA USB7 top USBA Table 34 Distribution of the USB hub s U4 ports Pin number Signal name Description 1 0585 0585 Power Supply 3 05 5 D USB5 Data 3 USB5 USBS Data 2 USBI VBUS USBI Power Supply 4 USBI D USBI Data 6 USB1 D USB1 Data 7 8 GND Ground 9 10 NC Not connected Table 35 Universal USB pin header X33 signal description PHYTEC Messtechnik GmbH 2010 L 751e 1 87 phyCARD L PCA A L1 xxx 17 3 6 USB Connectivity X29 Figure 25 USB interface at connector X29 The USB interface of the phyCARD is accessible at connector X29 USB Mini AB on the Carrier Board This interface is compliant with USB revision 2 0 No jumper settings are necessary for using the USB OTG port The phyCARD supports the On The Go feature The Universal Serial Bus On The Go is a device capable to initiate the session control the connection and exchange Host Peripheral roles between each other 88 PHYTEC Messtechnik GmbH 2010 1 751 1 The phyCARD L on the phyBA
94. ow X2B Pin Signal SL Description 1B VCC_3V3 Power 3 3V Primary Voltage Supply Input 2B VCC_3V3 Power 3 3V Primary Voltage Supply Input 3B VCC_3V3 Power 3 3V Primary Voltage Supply Input 4B GND Power Ground 0V 5B VDD_IO Power VCC Logic Output 6B VSTBY Power Standby Voltage Input 7B X nRESET OUT VCC LOGIC Active low Reset output 8B GND Power Ground 0V 9B X DIS LVDS 1 LVDS LVDS Chanel 1 positive Output 10B X DIS LVDS TXI LVDS LVDS Chanel 1 negative Output 11B X DIS LVDS LVDS LVDS Chanel 3 positive Output 12B X DIS LVDS TX3 LVDS LVDS Chanel 3 negative Output 13B GND Power Ground 0V 14B X CAM LVDS RAT LVDS LVDS Receive positive Input for Camera 15B X CAM LVDS RX LVDS LVDS Receive negative Input for Camera 16 X LVDS nLOCK 0 VCC3V3 Lock Output for Camera Interface 17B X DC SDA VCC LOGIC Data 18B GND Power Ground 0V 19B X ETH LINK VCC3V3 Ethernet Link Indicator Open Drain 20B X ETH RAT Receive positive input normal Transmit positive output reversed 21B X ETH RX Receive negative input normal Transmit negative output reversed 22B GND Power Ground 0V 23B X USBH PWR USB HOST Power switch output open drain 24B X USBH OC I VCC3V3 USB HOST over current input signal 25B GND Ground 0V 26B X nSUSP RAM OC VCC LOGIC Suspend to RAM Open Collector Output uC port
95. pin high density pitch 0 635 mm connector allowing the phyCARDs to be plugged like a big chip into a target application The reduced complexity of the phyCARD SBC as well as the smaller number of interface signals greatly simplifies the SBC carrier board design helping you to reduce your time to market As independent research indicates that approximately 70 96 of all EMI Electro Magnetic Interference problems stem from insufficient supply voltage grounding of electronic components in high frequency environments approximately 20 Yo of all pin header connectors on the X Arc bus are dedicated to Ground This improves EMI and EMC characteristics and makes it easier to design complex applications meeting EMI and EMC guidelines using phyCARD boards even in high noise environments PHYTEC Messtechnik GmbH 2010 L 751e 1 1 phyCARD L PCA A L1 xxx phyCARD boards achieve their small size through modern SMD technology and multi layer design In accordance with the complexity of the module 0402 packaged SMD components and laser drilled microvias are used on the boards providing phyCARD users with access to this cutting edge miniaturization technology for integration into their own design The phyCARD L is a subminiature 60 x 60 mm insert ready Single Board Computer populated with the Texas Instruments OMAP35x microcontroller Its universal design enables its insertion in a wide range of embedded applications Precise specific
96. quipped with a Lattice LC4256V PLD at 025 This PLD device provides the following features e Power management function section 17 3 2 e Signal mapping for sound devices WM9712L and AD1986A section 17 3 9 Configuration the sound device AD1986A for HDA or AC 97 e Signal mapping SPI chipselect and interrupt to the expansion or display connectors sections 17 3 11 and 17 3 12 e Touch Signal mapping to WM9712L or STMP811 section 9 connected to GPIO 146 of the OMAP35x on the phyCARD L PHYTEC Messtechnik GmbH 2010 L 751e 1 107 phyCARD L PCA A L1 xxx 17 3 19 Carrier Board Physical Dimensions 172mm 185mm call E uis te O 6 5mm Figure 34 Carrier Board Physical Dimensions Please contact us if a more detailed dimensioned drawing is needed to integrate the phyBASE into a customer application 108 PHYTEC Messtechnik GmbH 2010 L 751e 1 Revision History 18 Revision History changes in this manual 15 06 2010 Manual First draft Preliminary documentation L 751e 0 Describes the phyCARD L with phyBASE Baseboard 06 12 2010 Manual New edition with adaptions to new L 751e 1 PCB 1334 2 of the phyCARD L and 1333 2 of the phyBASE PHYTEC Messtechnik GmbH 2010 L 751e 1 109 phyCARD L PCA A L1 xxx 110 PHYTEC Messtechnik GmbH 2010 L 751e 1 Index Index 1 100 41 10
97. required please ensure that the board as well as surrounding components and sockets remain undamaged while de soldering Overheating the board can cause the solder pads to loosen rendering the module inoperable Carefully heat neighboring connections in pairs After a few alternations components can be removed with the solder iron tip Alternatively a hot air gun can be used to heat and loosen the bonds PHYTEC Messtechnik GmbH 2010 1 751 1 17 phyCARD L PCA A LI xxx Please pay special attention to the TYPE column to ensure you are using the correct type of jumper 0 Ohms 10k Ohms etc The jumpers are either 0805 package or 0402 package with a 1 8W or better power rating
98. rs J solder jumper have the following functions Jumper Description Type Chapter J3 2 23 J2 and Jl define the slave addresses A0 to A2 J1 of the serial memory U10 on the 2 bus In the 0402 high nibble of the address memory devices have the slave ID OxA The low nibble is build from A2 Al AO and the RAW bit 7 2 1 all 2 3 AO 0 Al 1 A2 0 gt 0 4 0x5 W R are selected as the low nibble of the EEPROM s address other please refer to Table 9 to find alternative addresses settings resulting from other combinations of jumpers J3 J2 and J1 J5 J5 connects pin 7 of the serial memory at U10 OR either to GND or to GPIO 112 of the OMAP35x 0402 On many memory devices pin 7 enables disables the activation of a write protect function It is not guaranteed that the standard serial memory populating the phyCARD L will have this write protection function 722 Please refer to the corresponding memory data Tus sheet for more detailed information 2 3 EEPROM 010 is not write protected 1 2 protection of EEPROM 10 software controlled via GPIO 112 EEPROM U10 is write protected EE J6 76 selects rising or falling edge strobe for the LVDS Deserializer at U8 used for the display 0805 connectivity of the phyCARD L 1 2 edge strobe used for the LVDS camera 154 signals 2 3 falling edge strobe used for the LVDS camera signals 20 PHYTEC Me
99. s user modifications and extensions of PHYTEC products is subject to renewed establishment of conformity to and certification of Electro Magnetic Directives Users should ensure conformance following any modifications to the products as well as implementation of the products into target systems PHYTEC Messtechnik GmbH 2010 L 751e 1 phyCARD L PCA A L1 xxx xli PHYTEC Messtechnik GmbH 2010 L 751e 1 Introduction 1 Introduction The phyCARD L belongs to PHYTEC s phyCARD Single Board Computer module family The phyCARD SBCs represent the continuous development of PHYTEC Single Board Computer technology Like its mini micro and nanoMODUL predecessors the phyCARD boards integrate all core elements of a microcontroller system on a subminiature board and are designed in a manner that ensures their easy expansion and embedding in peripheral hardware developments PHYTEC s phyCARD family introduces the newly developed X Arc embedded bus standard Apart from processor performance a large number of embedded solutions require a corresponding number of standard interfaces Among these process interfaces are for example Ethernet USB UART SPI audio display and camera connectivity The X Arc bus exactly meets this requirement As well the location of the commonly used interfaces as the mechanical specifications are clearly defined All interface signals of PHYTEC s new X Arc bus are available on a single 100
100. s or devices The settings of these pins control where the system 1s boot from They are accessible via boot pins X CONFIG 1 0 X2B50 and X2A50 of the phyCARD L The boot mode input X CONFIGO 2 50 is connected to SYS 5 and allows to choose memory or peripheral boot If left open SYS BOOT S5 is low If X CONFIGO is connected to high or low level SYS 5 is the inverse of the input level The boot mode input X CONFIGI X2B50 is attached to SYS 4 0 It is provided for future features and must not be used It should be left open A resistor array on the phyCARD L is used to preconfigure SYS 4 0 The SYS BOOTT 6 pin is used to select whether the internal oscillator is bypassed It is fixed to high oscillator bypassed in the phyCARD L PHYTEC Messtechnik GmbH 2010 1 751 1 29 phyCARD L PCA A L1 xxx The following table shows the different boot modes applicable for the phyCARD L Boot Mode Select Boot Mode Select Boot Mode Device SYS BOOT 5 SYS BOOT 4 0 X CONFIGO X CONFIGI 0 _ Memory Boot NAND USB UART3 MMCI open 1 01111 Peripheral Boot X CONFIG0 0 USB UART3 MMCI NAND Table 7 Boot Modes of OMAP35x module The standard phyCARD L module with 256MB NAND Flash comes with a boot configuration of 001111 so the system will boot from the NAND Flash Duetoa circuitry on the phyCARD L SYS BOOT 5 is low if X C
101. sstechnik GmbH 2010 L 751e 1 Jumpers Jumper Description Type Chapter 7 onm 2 J7 selects rising or falling edge strobe for the LVDS Transmitter at 07 used for the display 0805 connectivity of the phyCARD L 1 2 falling edge strobe used for the LVDS display signals 2 3 rising edge strobe used for the LVDS display signals J10 connects the reset input of the Fast Ethernet OR Controller 012 with GPIO 64 Thereby it 15 0805 possible to perform a reset of the Ehernet Controller not only by hardware but also by software Software reset of the Ethernet Controller disabled closed Software reset of the Ethernet Controller possible via GPIO 64 Jil allows to connect GPIO 149 to OR GPIOI IRQI pin of the X Arc bus X2B47 0402 instead of GPIO 145 142 1 connects to 149 aM 2 3 connects to 145 aM J12 12 allows to connect GPIO 151 to the OR pin of the X Arc bus X2A46 0402 instead of GPIO 144 1 2 GPIOO IRQO connects to GPIO 151 2 3 connects to 144 13 JI3 allows to connect GPIO 146 to OR GPIO2 IRQ2 PWM of the X Arc bus 0402 X2A47 instead of GPIO 147 1 2 GPIO2 IRQ2 PWM connects to 146 243 GPIO2 IRQ2 PWM connects to 147 Table 4 Jumper settings PHYTEC Messtechnik GmbH 2010 L 751e 1 21 phyC
102. suitable for the phyCARD L are not described in the following chapters 70 PHYTEC Messtechnik GmbH 2010 L 751e 1 The phyCARD L on the phyBASE 17 2 Overview of the phyBASE Peripherals The phyBASE is depicted in Figure 15 It is equipped with the components and peripherals listed in Table 28 Table 29 Table 30 and Table 31 For a more detailed description of each peripheral refer to the appropriate chapter listed in the applicable table Figure 15 highlights the location of each peripheral for easy identification lt 829 o nnnnnn Beans ti H N m N AQAA gt lt n 5 8 2 8 2 a f m E 5 7 5 o le d 58895 e 3 gt lt D tc L D 8 LO ea 7 p O0000000000000 x 28 E 5 2 x 5 ul 2 pa D MC 5 8 OUT i 9 9 gii g Figure 15 Overview of Connectors LEDs and Buttons PHYTEC Messtechnik GmbH 2010 L 751e 1 71 phyCARD L PCA A L1 xxx 17 21 Connectors and Pin Header Table 28 lists all available connectors on the phyBASE Figure 15 highlights the location of each connector for easy identification
103. t loader SDRAM must be initialized by accessing the appropriate SDRAM configuration registers on the OMAP35x controller Refer to the OMAP35x Reference Manual for accessing and configuring these registers 1 Please contact PHYTEC for more information about additional module configurations PHYTEC Messtechnik GmbH 2010 1 751 1 31 phyCARD L PCA A L1 xxx As well the NAND Flash memory in the PoP package as the discrete NAND Flash at U20 are connected to the GPMC bus This chip select signal is used for boot operation The discrete NAND Flash is an alternative to the PoP NAND Flash It can not be added as extension memory Use of Flash as non volatile memory on the phyCARD L provides an easily reprogrammable means of code storage The following Flash devices can be used on the phyCARD L Manufacturer NAND Flash P N Density POP MT29C2G48MAKLCJI 6 IT 256 MByte NAND MT29F2GIG6ABDHC ET Table 8 Compatible NAND Flash devices MICRON Additionally any POP memory parts that are footprint and functionally compatible with the devices listed above may also be used with the phyCARD L These Flash devices are programmable with 1 8 V No dedicated programming voltage 15 required As of the printing of this manual these NAND Flash devices generally have a life expectancy of at least 100 000 erase program cycles and a data retention rate of 10 years 7 2 PC EEPROM 010 The phyCARD L is populated w
104. ta connector signal description The connection of the SPI interface and the display interrupt input to the X Arc bus is shared with the SPI interfaces and the interrupt inputs on the expansion connectors X8A and X9A Because of that these signals have to be mapped to the display data connector by configuring switches 7 and 8 of DIP Switch S3 Table 57 shows the required settings The default setting does not connect the SPI interface and the GPIO Interrupt pin of the X Arc bus to the display data connector PHYTEC Messtechnik GmbH 2010 L 751e 1 91 phyCARD L PCA A L1 xxx Button Setting Description S3 7 0 0 550 0 gt expansion 0 X8A S3 8 SS1 GPIO1_IRQ gt expansion 1 X9A 0 1 SS0 GPIOO_IRQ gt expansion 0 X8A SS1 GPIO1_IRQ gt display data connector X6 1 SSO GPIOO IRQ gt expansion 1 X9A SSI GPIO1 IRQ gt display data connector X6 Table 37 SPI and GPIO connector selection The Light sensor Analog Input at pin 40 extends to an A D converter which is connected to the I C bus at address 0 8 write and 0 9 read 17 3 7 2 Display Power Connector X32 The display power connector X32 AMP microMatch 8 188275 2 provides all supply voltages needed to supply the display and a backlight Pin number Signal name Description 1 GND Ground 2 VCC3V3 3 3V power supply display 3 GND Grou
105. the Carrier Board Due to its characteristics this interface is hard wired and can not be configured via jumpers The LEDs for LINK green and SPEED yellow indication are integrated in the connector PHYTEC Messtechnik GmbH 2010 L 751e 1 85 phyCARD L PCA A L1 xxx 17 3 5 USB Host Connectivity X6 X7 X8 X9 X33 Front x H USB Host X33 USB Host 922558 ES 025 DD 216 ABICO CERO 1 X6 Figure 24 Components supporting the USB host interface The USB host interface of the phyCARD is accessible via the USB hub controller U4 on the Carrier Board The controller supports control of input USB devices such as keyboard mouse or USB key The USB hub has 7 downstream facing ports Two ports extend to standard USB connectors at X7 dual USB A Two more ports connect to 9 pin header row X33 These interfaces are compliant with USB revision 2 0 The remaining ports are accessible at the display data connector X6 and the expansion connectors X8A and X9A These three interfaces provide only the data lines DH and D They do not feature a supply line Vbus 86 PHYTEC Messtechnik GmbH 2010 L 751e 1 The phyCARD L on the phyBASE LEDs 016 to D30 signal use of the USB host interfaces Table 31 shows the assignment of the LEDs to the different USB ports Table 54 shows the distribution of the seven downstream facing ports to the different connect
106. tor 0 635 mm lining on side of the module referred to as phyCARD Connector This allows the phyCARD L to be plugged into any target application like a big chip The numbering scheme for the phyCARD Connector is based on a two dimensional matrix in which column positions are identified by a letter and row position by a number Pin 1A for example is always located in the upper left hand corner of the matrix The pin numbering values increase moving down on the board Lettering of the pin connector rows progresses alphabetically from left to right refer to Figure 4 The numbered matrix can be aligned with the phyCARD L viewed from above phyCARD Connector pointing down or with the socket of the corresponding phyCARD Carrier Board user target circuitry The upper left hand corner of the numbered matrix pin 1A is thus covered with the corner of the phyCARD L marked with 1A The numbering scheme 15 always in relation to the as viewed from above even if all connector contacts extend to the bottom of the module The numbering scheme is thus consistent for both the module s phyCARD Connector as well as the mating connector on the phyBASE Carrier Board or target hardware thereby considerably reducing the risk of pin identification errors PHYTEC Messtechnik GmbH 2010 L 751e 1 9 phyCARD L PCA A L1 xxx Since the pins are exactly defined according to the numbered matrix previously described the phyCARD Connector is
107. tor X27 along with the pin numbering scheme as described in section 2 80 PHYTEC Messtechnik GmbH 2010 L 751e 1 The phyCARD L on the phyBASE 17 3 2 Power Supply X28 X28 3a go enn ON OFF 039 037 n 10 D40 Figure 19 Power adapter Caution Do not use a laboratory adapter to supply power to the Carrier Board Power spikes during power on could destroy the phyCARD module mounted on the Carrier Board Do not change modules or jumper settings while the Carrier Board is supplied with power Permissible input voltage at X28 9 36 V DC unregulated The required current load capacity of the power supply depends on the specific configuration of the phyCARD mounted on the Carrier Board as well as whether an optional expansion board is connected to the Carrier Board An adapter with a minimum supply of 2 0 is recommended PHYTEC Messtechnik GmbH 2010 L 751e 1 81 phyCARD L PCA A L1 xxx Polarity _ Center Hole 49 36 VDC 25mm pne 2 2000 mA 3 VA GND Figure 20 Connecting the Supply Voltage at X28 No jumper configuration 1s required in order to supply power to the phyCARD module The phyBASE 15 assembled with a few power LEDs whose functions are described in the following table LEDs Color Description D37 green VCCSV 5V supply voltage for peripherals on the phyBASE 038 VCC PHYCARD supply voltage of phyCARD D39 green VC
108. wer Management The phyCARD L was designed to support applications requiring a power management Three pins of the X Arc bus are designated for this purpose X nPWR OFF and X nSUSP RAM are output pins which can be used to indicate the power status of the phyCARD L whereas X nWKUP is an input pin to apply a wake up signal to the phyCARD L All three pins lead 10 GPIOs of the OMAP35x Thus their functionality can be programmed to your needs The following table shows the location of the power management pins on the phyCARD Connector and the corresponding GPIOs of the OMAP35x Pin Signal I O SL Description X2A48 X nWKUP I VDD_IO Wakeup Interrupt Input uC port GPIO 146 X2B26 X nSUSP VDD IO Suspend to RAM Open Collector Output uC port GPIO_ 134 X2B29 X nPWR OFF OC VDD_IO Power Off Open Collector Output uC port GPIO_ 133 Table 5 Power Management Pins With the two output signals X nPWR OFF pin X2B29 and X nSUSP RAM X2B26 three different power states can be defined PHYTEC Messtechnik GmbH 2010 L 751e 1 27 phyCARD L PCA A L1 xxx Bou Power On Standby Off Signal X nSUSP RAM High Low x X nPWR OFF High High Low VDD 3V3 On Off Off VSTBY X On Off X don t care Table 6 Power States Please refer to the chapter Power Management in the phyCARD Design In Guide for more information about the implementation of th

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