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RX210 Group Renesas Peripheral Driver Library User`s Manual

1. IPR register definitions PDL_INTC_REG_IR_IICO_EEIl PDL_INTC_REG_IR_SCI7_TEI PDL_INTC_REG_IR_IICO_RXI PDL_INTC_REG_IR_SCI8_ERI PDL_INTC_REG_IR_TPUO_TGIA PDL_INTC_REG_IR_SCI8_RXI PDL_INTC_REG_IR_TPUO_TGIB PDL_INTC_REG_IR_SCI8_TXI PDL_INTC_REG_IR_TPUO_TGIC PDL_INTC_REG_IR_SCI8_TEl PDL_INTC_REG_IR_TPUO_TGID PDL_INTC_REG_IR_SCI9 ERI PDL_INTC_REG_IR_TPUO_TCIV PDL_INTC_REG_IR_SCI9_RXI PDL_INTC_REG_IR_TPU1_TGIA PDL_INTC_REG_IR_SCI9_TXI PDL_INTC_REG_IR_TPU1_TGIB PDL_INTC_REG_IR_SCI9 TEI PDL_INTC_REG_IR_TPU1_TCIV PDL_INTC_REG_IR_SCI10_ ERI PDL_INTC_REG_IR_TPU1_TCIU PDL_INTC_REG_IR_SCI10_RXI PDL_INTC_REG_IR_TPU2_TGIA PDL_INTC_REG_IR_SCI10_TXI PDL_INTC_REG_IR_TPU2_TGIB PDL_INTC_REG_IR_SCI10_TEI PDL_INTC_REG_IR_TPU2_TCIV PDL_INTC_REG_IR_SCI11_ERI PDL_INTC_REG_IR_TPU2_TCIU PDL_INTC_REG_IR_SCI11_RXI PDL_INTC_REG_IR_TPU3_TGIA PDL_INTC_REG_IR_SCI11_TXI PDL_INTC_REG_IR_TPU3_TGIB PDL_INTC_REG_IR_SCI11_TEI PDL_INTC_REG_IR_TPU3_TGIC PDL_INTC_REG_IR_SCI12_ERI PDL_INTC_REG_IR_T
2. PDL_INTC_REG_IPR_CMPB_CMPB1 PDL_INTC_ REG _IPR_MTU4_TCIV PDL_INTC_REG_IPR_RTC_COUNTUP PDL_INTC_ REG _IPR_MTU5_TGIU PDL INTC REG IPR ICU IRQO PDL INTC REG IPR MTU5 TGIV PDL INTC REG IPR ICU IRQ1 PDL INTC REG IPR MTU5 TGIW PDL_INTC REG _IPR_ICU IRQ2 PDL_INTC_REG_IPR POE_OEI1 PDL_INTC REG _IPR_ICU_ IRQ3 PDL_INTC REG IPR POE_OEI2 PDL_INTC REG _IPR_ICU IRQ4 PDL_INTC_ REG IPR _TMRO CMIA PDL_INTC REG IPR ICU IRQ5 PDL_INTC REG IPR TMRO CMIB PDL INTC REG IPR ICU IRQ6 PDL_INTC REG IPR TMRO OVI PDL_INTC REG _IPR_ICU IRQ7 PDL_INTC_ REG IPR _TMR1_CMIA PDL_INTC REG _IPR_LVD LVD1 PDL_INTC_ REG _IPR_TMR1_CMIB PDL_INTC_ REG _IPR_LVD LVD2 PDL_INTC_REG_IPR_TMR1_OVI PDL_INTC REG IPR CMPA CMPA 1 PDL_INTC REG IPR TMR2 CMIA PDL_INTC REG IPR CMPA CMPA2 PDL_INTC REG IPR TMR2 CMIB PDL_INTC_ REG IPR RTC ALM PDL_INTC_ REG IPR _TMR2_ OVI PDL_INTC_ REG _IPR_ RTC PRD PDL_INTC_REG_IPR_TMR3_CMIA PDL_INTC_REG_IPR_S12AD0_S12ADI PDL_INTC_ REG _IPR_TMR3_CMIB PDL INTC REG IPR S12AD0 GBADI PDL_INTC RE
3. PDL_SCI_PIN_SCI7_RXD7_P92 RXD7 PDL SCI PIN SCI7 SMISO7 P92 SMISO7 PDL SCI PIN SCI7 SSCL7 P92 SSCL7 PDL_SCI_PIN_SCI7_TXD7_P90 TXD7 PDL_SCI_PIN_SCI7_SMOSI7_P90 SCI7 SMOSI7 PDL_SCI_PIN_SCI7_SSDA7_P90 SSDA7 PDL_SCI_ PIN SCI7 SCK7 P91 SCK7 PDL_SCI_ PIN SCI7_CTS7 P93 CTS7 PDL_SCI_PIN SCI7_RTS7_P93 RTS7 PDL_SCI_PIN SCI7_SS7_P93 SS7 Valid when n 8 PDL SCI PIN SCI8 RXD8 PC6 RXD8 PDL_SCI_PIN_SCI8_SMISO8_PC6 SMISO8 PDL_SCI_PIN SCI8 SSCL8 PC6 SSCL8 PDL_SCI_PIN_SCI8_TXD8 PC7 TXD8 PDL_SCI_ PIN SCI8 SMOSI8 PC7 SCI8 SMOSI8 PDL SCI PIN SCI8 SSDA8 PC7 SSDA8 PDL_SCI_PIN_SCI8_SCK8 PC5 SCK8 PDL_SCI_PIN SCI8 CTS8 PC4 CTS8 PDL_SCI_PIN_SCI8_RTS8_PC4 RTS8 PDL SCI PIN SCI8 SS8 PC4 SS8 Valid when n 9 PDL_SCI_PIN SCI9_RXD9_PB6 or RXD9 PDL_SCI_PIN_SCI9_RXD9_PK3 PDL_SCI_PIN_SCI9 SMISO9 PB6 or PDL SCI PIN SCI9 SMISO9 PK3 SMISO9 PDL_SCI_PIN_SCI9 SSCL9 PB6 or SSCL9 PDL_SCI PIN_SCI9 SSCL9 PK3 PDL_SCI_PIN_SCI9 TXD9 PB7 or TXD9 PDL_SCI_PIN_SCI9 TXD9 PK2 PDL_SCI_PIN_SCI9_SMOSI9_PB7 or
4. Description 2 4 PDL_INTC_VECTOR_TGIA3 f Compare match or Input capture A PDL_INTC_VECTOR TGIB3 a Compare match or Input capture B PDL_INTC_VECTOR_TGIC3 Unit channel Compare match or Input capture C PDL_INTC_VECTOR_TGID3 3 Compare match or Input capture D PDL_INTC_VECTOR_TCIV3 Overflow PDL_INTC_VECTOR_TGIA4 Compare match or Input capture A PDL_INTC_ VECTOR TGIB4 AS Compare match or Input capture B PDL_INTC_VECTOR_TGIC4 Unit channel Compare match or Input capture C PDL_INTC_VECTOR_TGID4 4 Compare match or Input capture D PDL_INTC_VECTOR_TCIV4 Overflow PDL_INTC_VECTOR_TGIU5 Multi function Compare match or Input capture U PDL_INTC_VECTOR_TGIV5 Timer Pulse Compare match or Input capture V PDL_INTC_VECTOR_TGIW5 ral channel Compare match or Input capture W PDL_INTC_VECTOR_TPUO_TGIOA Compare match or Input capture A PDL_INTC_VECTOR_TPUO_TGIOB Timer Pulse Compare match or Input capture B PDL_INTC_VECTOR_TPUO_TGIOC Unit Channel Compare match or Input capture C PDL_INTC_VECTOR_TPUO_TGIOD 0 Compare match or Input capture D PDL_INTC_VECTOR_TPUO_TCIOV Overflow PDL_INTC_VE
5. PDL_INTC_REG_IPR_TPU1_TCIV PDL_INTC_REG_IPR_TPU4_TCIV PDL_INTC_REG_IPR_TPU1_TCIU PDL_INTC_REG_IPR_TPU4_TCIU PDL_INTC_REG_IPR_TPU2_TGIA PDL_INTC_REG_IPR_TPUS_TGIA PDL_INTC_REG_IPR_TPU2_TGIB PDL_INTC_REG_IPR_TPU5_TGIB PDL_INTC_REG_IPR_TPU2_TCIV PDL_INTC_REG_IPR_TPU5_TCIV PDL_INTC_REG_IPR_TPU2_TCIU PDL_INTC_REG_IPR_TPU5_TCIU DTCER register definitions PDL_INTC_REG_DTCER_ICU_SWINT PDL_INTC_REG_DTCER_S12AD0_S12ADI PDL_INTC_REG_DTCER_CMTO_CMI PDL_INTC_REG_DTCER_S12AD0_GBADI PDL_INTC_REG_DTCER_CMT1_CMI PDL_INTC_REG_DTCER_TMRO_CMIA PDL_INTC_REG_DTCER_CMT2_CMI PDL_INTC_REG_DTCER_TMRO_CMIB PDL_INTC_REG_DTCER_CMT3_CMI PDL_INTC_REG_DTCER_TMR1_CMIA PDL_INTC_REG_DTCER_SPIO_SPRI PDL_INTC_REG_DTCER_TMR1_CMIB PDL_INTC_REG_DTCER SPIO_SPTI PDL_INTC_REG_DTCER_TMR2_CMIA PDL_INTC_REG_DTCER_CMPB_CMPBO PDL_INTC_REG_DTCER_TMR2_CMIB PDL_INTC_REG_DTCER_CMPB_CMPB1 PDL_INTC_REG_DTCER_TMR3_CMIA PDL_INTC_REG_DTCER_ICU_IRQO PDL_INTC_REG_DTCER_TMR3_CMIB PDL_INTC_REG_DTCER_ICU_IRQ1 PDL_INTC_REG_DTCER_DMAC_DMACOI PDL_INTC_REG_DTCER_ICU_IRQ2 PDL_INTC_REG_DTCER_DMAC_DMAC1I PDL_INTC_REG_DTCER_ICU_IRQ3 PDL_INTC_REG_DTCER_DMAC_DMAC2I
6. PDL_INTC_VECTOR_CMPA2 PDL_INTC_VECTOR_FRDYI memory Ready PDL_INTC_VECTOR_SWINT Meche Software interrupt PDL_INTC_VECTOR_CMTO PDL_INTC_VECTOR_CMT1 Compare Pompa male PDL_INTC_VECTOR_CMT2 match timer P PDL_INTC_VECTOR_CMT3 PDL_INTC_VECTOR_FERRF Clock Frequency error PDL_INTC_VECTOR_MENDF frequency Measurement end accuracy PDL_INTC_VECTOR_OVFF measurement overflow PDL_INTC_VECTOR_SPEIO Error PDL_INTC_VECTOR_SPRIO RSPI channel Receive buffer full PDL_INTC_VECTOR_SPTIO 0 Transmit buffer empty PDL_INTC_VECTOR_SPIIO Idle PDL_INTC_VECTOR_DOPCF oe Condition detection operation Aa Comparator A Voltage detection PDL_INTC_VECTOR_CMPBO PDL_INTC_VECTOR_CMPB1 Comparator B Comparison result change PDL_INTC_ VECTOR CUP PDL_INTC_ VECTOR ALM PDL_INTC_VECTOR_PRD Real time clock Carry Alarm Periodic PDL_INTC_VECTOR_IRQO PDL_INTC_VECTOR_IRQ1 PDL_INTC_VECTOR_IRQ2 PDL_INTC_VECTOR_IRQ3 PDL_INTC_VECTOR_IRQ4 PDL_INTC_VECTOR_IRQ5 PDL_INTC_VECTOR_IRQ6 PDL_INTC_VECTOR_IRQ7 External interrupt pin Valid edge or level detected PDL_INTC_VECTOR_S12ADI0 Conversion completed PDL_INTC_VECTOR_GBADI TDITADC Group B scan completed PDL_INTC_VECTOR_ELSR18l
7. PDL MTU2 OUT BUFFER P_PHASE_1_HIGH MTIOC3B PDL_MTU2_OUT_BUFFER_N_PHASE_1_LOW or piTioc3p PDL MTU2 OUT BUFFER N PHASE_1_HIGH PDL_MTU2_OUT_BUFFER P_PHASE_2 LOWor yrocaa PDL _MTU2 OUT BUFFER P_PHASE_2 HIGH PDL_MTU2_OUT_BUFFER N_PHASE_2 LOWor mocac PDL _MTU2 OUT BUFFER N PHASE_2_HIGH PDL_MTU2_OUT_BUFFER P_PHASE_3 LOWor roca PDL_MTU2 OUT BUFFER P PHASE 3 HIGH PDL_MTU2_OUT_BUFFER_N_PHASE_3 LOWor riocap PDL_MTU2_OUT BUFFER N PHASE 3 HIGH Set the transfer timing In complementary PWM modes PDL_MTU2_OUT_BUFFER_TRANSFER_DISABLE or PDL_MTU2_OUT_BUFFER_TRANSFER_CREST or PDL_MTU2_OUT_BUFFER_TRANSFER_TROUGH or trough or PDL_MTU2_OUT BUFFER TRANSFER BOTH Disable or enable on detection of crest both In Reset synchronised PWM mode PDL_MTU2_OUT_BUFFER_TRANSFER_DISABLE or PDL_MTU2_ OUT BUFFER TRANSFER CLEAR Disable or enable on counter clear Buffer transfer to temporary transfer control Applicable for complementary PWM modes PDL_MTU2_BUFFER_TRANSFER_DISABLE or PDL_MTU2_BUFFER_TRANSFER_ENABLE or PDL_MTU2_BUFFER_TRANSFER_LINK Disable transfers enable without linking to interrupt skipping or enable and link to interrupt skipping brushless_DC_motor_control Brushless DC motor control settings All settings are optional If multiple selections are required use to separate each select
8. Type Defined in Description Range bool stdbool h Boolean O false to 1 true double C Floating point 64 bits uint8_t Unsigned 8 bits O to 255 uint16 t stdint h Unsigned 16 bits 0to2 1 int32_t Signed 32 bits 2 to 27 1 uint32_t Unsigned 32 bits 0 to 27 1 3 2 General definitions 3 2 1 PDL_NO_FUNC Used as a parameter when there is no applicable function 3 2 2 PDL_NO_PTR Used as a parameter when there is no applicable data location 3 2 3 PDL_NO_DATA Used as a parameter when there is no applicable data value 3 2 4 PDL_MCU_GROUP The MCU group supported by this build of the driver library It is defined as RX210 A usage example is Hif PDL MCU GROUP RX210 error Wrong RPDL tendif 3 2 5 PDL_VERSION The version number of the RPDL library The number is stored in BCD format xx xx For example 0100h is v1 00 A usage example is const uintl6 t rpdl version number PDL VERSION 3 2 6 Bit definitions The definitions BIT_n and INV_BIT_n where n 0 to 31 are available to the user R20UT0708EE0211 Rev 2 11 Page 3 1 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 4 Library Reference 4 1 API List by Peripheral Function Table 4 1 lists the Renesas Embedded APIs by peripheral function Table 4 1 Renesas Embedded API List Category Number Name Description Clock
9. Transfer method Parameter PDL_NO_FUNC This function will continue until the required number of Polling er bytes has been sent Interrupts The function to be called when the last byte has been sent DMAC Either the function to be called when each byte is sent or PDL_NO_FUNC if the callback function specified in R_DMAC_Create will be used DTC The function to be called at the interval specified in R_DTC_Create Return value Category Reference R20UT0708EE0211 Rev 2 11 Aug 01 2014 True if all parameters are valid and the operation completed without errors False if a parameter was out of range or if the channel was already transmitting or if an error occurred during transmission SCl R_SCI_Control R_SCI_GetStatus Page 4 219 RENESAS RX210 Group 4 Library Reference Remarks The compiler adds a null character to the end of string constants If a callback function is specified transmission interrupts are used Please see the notes on callback function usage in 6 If polling mode is used the TXI and TEND flags will be used to manage the data transmission If the SCI channel s control registers are directly modified by the user this function may lock up The maximum number of characters to be transmitted is 65535 Acallback function is executed by the interrupt processing function This means that no other interrupt can be process
10. Configure main clock operation using an external 20 0 MHz clock ICLK 20 MHz PCLKD 20 MHz PCLKB 20 MHz FCLK 20 MHz BCLK not used BCLK pin not used R CGC Set PDL CGC CLK_MAIN PDL CGC BCLK DISABLE PDL _CGC_ MAIN RESONATOR 20E6 20E6 20E6 20E6 20E6 PDL NO_ DA PDL _NO DAI Use the main clock to check the LOCO accuracy 110 R_CAC Create PDL CAC REFERENCE MAIN PDL CAC REFERENCE RISING PDL CAC REFERENCE DIV 8192 PDL CAC MEASURE LOCO PDL CAC MEASURE DIV 1 PDL CAC LIMIT TOLERANCE PDL NO DATA PDL NO DATA 10 10 CAC frequency error 15 CAC measurement complete 6 CAC overflow 10 R20UT0708EE0211 Rev 2 11 Aug 01 2014 ENESAS Page 5 10 RX210 Group 5 Usage Examples void CAC frequency error void Handle the frequency error void CAC_measurement_complete void uint8 t Status_flags uint16 t upper limit uint16 t lower limit uint16_t counter R_CAC_GetStatus amp Status_ flags supper limit amp lower limit amp counter y Clear the measurement flag and stop the CAC R_CAC Control PDL_CAC_DISABLE PDL CAC CLEAR MEASUREMENT PDL NO DATA PDL NO DATA PDL NO DATA y void CAC overflow void Handle the overflow error Figure 5 6 Example of Clock Frequ
11. PDL_MPC_REG P31PFS PDL_MPC_REG PD2PFS PDL_MPC_ REG P32PFS PDL_MPC_REG PD3PFS PDL_MPC_REG P33PFS PDL_MPC_REG PD4PFS PDL_MPC_REG P34PFS PDL_MPC_REG PD5PFS PDL_MPC_REG P40PFS PDL_MPC_REG _PD6PFS PDL_MPC_REG P41PFS PDL_MPC_REG PD7PFS PDL_MPC_ REG P42PFS PDL_MPC_REG PEOPFS PDL_MPC_ REG P43PFS PDL_MPC_REG_PE1PFS PDL_MPC_REG P44PFS PDL_MPC_REG_PE2PFS PDL_MPC_REG P45PFS PDL_MPC_REG PE3PFS PDL_MPC_REG P46PFS PDL_MPC_REG_PE4PFS PDL_MPC_ REG P47PFS PDL_MPC_REG_PE5PFS PDL_MPC_REG_P54PFS PDL_MPC_REG_PE6PFS PDL_MPC_REG_ P55PFS PDL_MPC_REG_PE7PFS PDL_MPC_REG PAOPFS PDL_MPC_REG_PHOPFS PDL_MPC_REG_PA1PFS PDL_MPC_REG PH1PFS PDL_MPC_REG PA2PFS PDL_MPC_REG PH2PFS PDL_MPC_REG_PA3PFS PDL_MPC_REG_PH3PFS PDL_MPC_REG_PA4PFS PDL_MPC_REG_ PJ1PFS PDL_MPC_REG PA5PFS PDL_MPC_REG PJ3PFS PDL_MPC_REG_PAGPFS PDL_MPC_REG PFCSE PDL_MPC_REG PA7PFS PDL_MPC_REG_PFAOEO R20UT0708EE0211 Rev 2 11 Aug 01 2014 PDL_MPC_REG _PFAOE1 PDL_MPC_REG_PFBCRO PDL_MPC_REG PFBCR1 RENESAS Page 4 46 RX210 Group 1 R_MPC_Read Synopsis Prototype Description Return value Cate
12. PDL_MTU2_U_IC_PWM_LOW_TROUGH or PDL_MTU2_U_IC_PWM_LOW_CREST or PDL_MTU2_U_IC_ PWM LOW BOTH or Input capture at trough crest or both for low pulse width measurement PDL_MTU2_U_IC_PWM_HIGH_ TROUGH or PDL_MTU2_U_IC_PWM_HIGH_CREST or PDL_MTU2_U_IC_PWM_HIGH BOTH Input capture at trough crest or both for high pulse width measurement e Input capture compare match control for register TGRV PDL_MTU2_V_CM or Compare match PDL_MTU2_V_IC_RISING_EDGE or PDL_MTU2_V_IC_FALLING_EDGE or PDL_MTU2_V_IC_BOTH EDGES or Input capture at MTICnV rising edge Input capture at MTICnV falling edge Input capture at MTICnV both edges PDL_MTU2_V_IC_PWM_LOW_TROUGH or PDL_MTU2_V_IC_PWM_LOW_CREST or PDL_MTU2_V_IC_PWM_LOW_BOTH or Input capture at trough crest or both for low pulse width measurement PDL_MTU2_V_IC_PWM_HIGH_TROUGH or PDL_MTU2_V_IC_PWM_HIGH_CREST or PDL_MTU2_V_IC_PWM_HIGH BOTH Input capture at trough crest or both for high pulse width measurement e Input capture compare match control for register TGRW PDL_MTU2_W_CMor Compare match PDL_MTU2_W_IC_RISING_EDGE or PDL_MTU2_W_IC_FALLING_EDGE or PDL_MTU2_W_IC_BOTH_EDGES or Input capture at MTICnW rising edge Input capture at MTICnW falling edge Input capture at MTICnW both edges PDL_MTU2_W_IC_PWM_LOW_TROUGH or PDL_MTU2_W_IC_PWM_LOW_CREST or PDL_MTU2
13. b15 b1 bO 0 0or1 Pin PE1 open drain control b15 b2 bi b0 0 0to3 Port not open drain control b15 b8 b7 b0 0 Register Port open drain control b15 b8 b7 b0 Register ODR1 Register ODRO True if all parameters are valid and exclusive otherwise false I O port None Ensure that the specified register is valid for the selected port or port pin R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS eee RX210 Group 4 Library Reference Program example RPDL definitions include r pdl io port h RPDL device specific definitions tinclude r pdl_ definitions h void func void uintl6 t result Read the direction register for port C R_IO_PORT_ReadControl PDL_IO PORT C PDL IO PORT DIRECTION result i Read the output type for pin P13 R IO PORT ReadControl PDL IO PORT 1 3 PDL IO PORT TYPE amp result 5 R20UT0708EE0211 Rev 2 11 Aug 01 2014 REN ESAS Page 4 37 RX210 Group 4 Library Reference 3 R_IO_PORT_ModifyControl Synopsis Prototype Description Return value Category References Remarks R20UT0708EE0211 Rev 2 11 Aug 01 2014 Modify an I O port s control registers bool R_IO_PORT_ModifyControl uint16_t data1 Port or port pin selection uint8_t data2 Control register and l
14. e ABCS selection required for asynchronous mode PDL_SCI_CYCLE_BIT_16 or PDL_SCI CYCLE BIT 8 Select 16 or 8 base clock cycles for one bit period CKS selection required if the on chip baud rate generator is selected as the data clock source PDL_SCI_PCLK_DIV_1 or PDL_SCI_PCLK_DIV_4 or Select the internal clock signal PCLKB 1 4 16 or 64 as PDL_SCI_PCLK_DIV_16 or the baud rate generator clock source PDL_SCI_PCLK_DIV_64 BRR setting required if the on chip baud rate generator is selected as the data clock source The BRR register value between 0 and 255 data4 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter may be zero if the following functions will not be used with a callback function R_SCI_Send R_SCI_Receive R_SCI_SPI_Transfer R_SCI_IIC_Write and R_SCI_IIC_Read True if all parameters are valid exclusive and achievable otherwise false R20UT0708EE0211 Rev 2 11 Aug 01 2014 Category SCl Reference R_CGC_Set R_SCI_Set R_SCI_Send R_SCI_Receive R_SCI_ Control Remarks e Function R_CGC_Set must be called with the current clock source selected before using this function Function R_SCI_Set must be called before any use of this function SCI5 cannot be configured for IIC mode if the ELC event PDL_ELC_LINK_EVENT_SCI5_RECEIVE_DATA_FULL is being used This function will re
15. The interrupt pin input can be unfiltered or sampled using the peripheral clock PCLKB divided by 1 8 32 or 64 For the NMI signal this selection is ignored if the NMI pin is not enabled Options which only apply to the IRQ pins Input sense selection PDL_INTC_LOW or PDL_INTC_FALLING or PDL_INTC_RISING or PDL_INTC_BOTH Select Low level Falling edge Rising edge or Falling and rising edge detection e DMAC DTC trigger control Not enabled if low level detection is selected PDL_INTC_DMAC_DTC_TRIGGER_DISABLE or PDL_INTC_DMAC_TRIGGER_ENABLE or PDL_INTC_DTC_TRIGGER_ENABLE Disable or enable activation of the DMAC or DTC when a valid edge transition is detected on a valid IRQn pin Options which only apply to the NMI Pin enable and input sense selection PDL_INTC_FALLING or PDL_INTC_RISING Enable the NMI pin and select falling or rising edge detection Required only if the NMI pin is to be used Internal detection control PDL_INTC_OSD_DISABLE or PDL_INTC_OSD_ENABLE Disable or enable the NMI signal when the oscillation stop detection interrupt occurs PDL_INTC_WDT_DISABLE or PDL_INTC_WDT ENABLE Disable or enable the NMI signal when a WDT underflow interrupt occurs PDL_INTC_IWDT_DISABLE or PDL_INTC_IWDT_ENABLE Disable or enable the NMI signal when an IWDT underflow interrupt occurs PDL_INTC_LVD1
16. Prototype Description Return value Category Reference Remarks Program example Shutdown an SPI channel bool R_SPI_Destroy uint8_t data Channel selection Shutdown the selected SPI channel data Select channel SPIn where n 0 only True if all parameters are valid otherwise false SPI None The SPI channel is put into the power down state RPDL definitions include r pdl spi h RPDL device specific definitions tinclude r pdl definitions h void func void Shutdown SPI channel 0 R_SPI Destroy 0 y R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 259 RENESAS RX210 Group 4 R_SPI_Command Synopsis Configure an SPI command Prototype bool R_SPI_Command uint8_t data1 uint8_t data2 uint32_t data3 uint8_t data4 Description 1 2 data1 Select the options for a command 4 Library Reference Channel selection Command selection I Command options II Extended timing control Select channel SPIn where n 0 only data2 Select command n where n 0 to 7 data3 Select the command options If multiple selections are required use to separate each selection The default settings are shown in bold Clock phase and polarity Idle clock Data sampling edge
17. b15 b14 b8 Start type 0 0 Cold 1 Warm b7 b6 b5 b4 b3 b2 b1 bO Reset detection flags 0 not detected 1 detected Exit from deep Voltage monitor i software standby Software WDT IWDT gt 1 0 1 Power on data3 Where the OFSO register contents shall be stored Specify PDL_NO_PTR if they are not required data4 Where the OFS1 register contents shall be stored Specify PDL_NO_PTR if they are not required True MCU registers None e Ifa reset detection flag is set to 1 it shall be automatically cleared to 0 by this function RENESAS eii RX210 Group Program example RPDL definitions include r pdl_mcu h RPDL device specific definitions include r pdl definitions h void func void uint1l6 t mode status Read the MCU mode status registers R_MCU_GetStatus amp mode_ status PDL NO PTR PDL NO PTR PDL NO PTR 4 Library Reference R20UT0708EE0211 Rev 2 11 Aug 01 2014 2tENESAS Page 4 52 RX210 Group 3 R_MCU_OFS Synopsis Prototype Description 1 2 R20UT0708EE0211 Rev 2 11 Aug 01 2014 Configure the device start up operation R_MCU_OFS uint32_t data1 uint32_t data2 uint32_t data3 uint32_t data4 4 Library Reference II WDT configuration options II WDT configuration options LVD configuration options II CGC configuration options Sel
18. 7 Re enable IRQ1 as a DTC trigger R_DTC Control PDL_DTC_TRIGGER_IRQ1 PDL NO PTR PDL NO PTR PDL NO PTR PDL NO DATA PDL NO DATA Figure 5 11 Example of DTC use R20UT0708EE0211 Rev 2 11 Page 5 22 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 9 2 Chain transfer operation Figure 5 12 shows an example of Data Transfer Controller operation using chain transfer of blocks Address space destination_string_3 destination_string_2 destination_string_1 1 Renesas RX210 DTC example Using chain transfer Transfer 1 is triggered by a software interrupt and copies data from ROM into RAM On completion of transfer 1 transfer 2 is started On completion of transfer 2 transfer 3 is started Peripheral driver function prototypes include r pdl dtc h include r pdl intc h RPDL device specific definitions include r pdl definitions h Required for this example include lt string h gt Reserve an area for the DTC vector table pragma address dtc vector table 0x00001000 uint32 t dtc vector table 256 Reserve three contiguous groups of 16 bytes full address mode for the transfer data areas uint32 t dtc_sw transfer data 4 3 const char source string 1 Renesas RX210 const char source string 2 DTC example const char source string 3 using chain transfer volatile char destina
19. R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference Operation data1 PDL_ELC_PORT_CONTROL data2 e Selecta port group PDL_ELC PORT _BorPDL_ELC_PORT E Select the port group to control data3 Set configuration To set multiple options at the same time use to separate each value e _Input Group edge control PDL_ELC_PORT_GROUP_INPUT_RISING_EDGE or PDL_ELC_PORT_GROUP_INPUT_ FALLING EDGE or PDL_ELC_ PORT GROUP_INPUT_ANY_EDGE If an input port group select the edge that will cause an event Input Group port buffer control PDL_ELC_PORT_GROUP_INPUT_BUFFER_ENABLE or PDL_ELC_PORT_GROUP_INPUT_BUFFER_DISABLE Enable or disable overwriting of the port data buffer by an input port group e Output Group output control PDL_ELC_PORT_GROUP_OUTPUT_0 or PDL_ELC_PORT_GROUP_OUTPUT_1 or PDL_ELC_PORT_GROUP_OUTPUT_TOGGLE or PDL_ELC_PORT_GROUP_OUTPUT_BUFFER or PDL_ELC_PORT_GROUP_OUTPUT_ROTATE If an output port group configure the output when an event occurs Operation data1 PDL_ELC_SINGLE_PORT data2 Single port configuration PDL_ELC_SINGLE_PORT_0 or PDL_ELC_SINGLE_PORT_1 or PDL_ELC_SINGLE_PORT_2 or PDL_ELC_SINGLE_PORT_3 Select the single port to define configure data3 Set configuration A pin selection and a single port control value must both
20. bool result Write OxFF to register MPC1 result R_MPC Write 1 OxFF i if result false Handle th rror here Keep trying to send a string if the channel is busy do result R SCI Send 2 Renesas RX NULL PDL_NO_FUNC 7 whil result false For clarity the return value is not checked in the examples used in this manual The RPDL API is implemented using function macros To avoid the possibility of parameters being evaluated more than once do not use operators or function calls within the RPDL API parameter list R20UT0708EE0211 Rev 2 11 Page 4 4 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 4 2 1 Clock Generation Circuit 1 R_CGC_Set Synopsis Prototype Description 1 2 Configure the clock generation circuit bool R_CGC_Set uint8_t data1 Clock selection uint32_t data2 Configuration options double data3 1 Clock frequency double data4 II System clock frequency double data5 Peripheral module clock D frequency double data6 Peripheral module clock B frequency double data7 Flash interface clock frequency double data8 External bus clock frequency uint16_t data9 Sub clock stabilization time Set a clock source frequencies and options data1 Clock source selection e Clock source selection PDL_CGC_CLK_LOCO or Sel
21. PDL_MTU2_REGISTER_TGRF General register E Valid for n 0 General register F Valid for n 0 PDL_MTU2_REGISTER_TADCOBRA ADC start request cycle set buffer A Valid for n 4 ADC start request cycle set buffer B PDL_MTU2_REGISTER_TADCOBRB Valid forn 4 R20UT0708EE0211 Rev 2 11 Page 4 136 Aug 01 2014 RENESAS RX210 Group Description 2 2 4 Library Reference Forn 5 Return value Category Reference PDL_MTU2_REGISTER_COUNTER_U Timer counter U register TCNTU PDL_MTU2_REGISTER_COUNTER_V Timer counter V register TCNTV PDL_MTU2_REGISTER_COUNTER_W Timer counter W register TCNTW PDL_MTU2_REGISTER_TGRU General registerU PDL_MTU2_REGISTER_TGRV General register V PDL_MTU2_REGISTER_TGRW General register W TCNT_TCNTU_value For n 0 to 4 The timer counter TCNT value For n 5 The timer counter TCNTU value This will be ignored if the register is not selected TGRA_TCNTV_value For n 0 to 4 The register TGRA value For n 5 The timer counter TCNTV value This will be ignored if the register is not selected TGRB_TCNTW_value For n 0 to 4 The register TGRB value For n 5 The timer counter TCNTW value This will be ignored if the register is not selected TGRC_TGRU_value For n 0 3 or 4 The register TGRC value For n 5 The register TGRU value This will be ignored if the regis
22. Select the alarm date counters to be updated using values supplied in parameters data5 and data6 PDL_RTC_UPDATE_ALARM_YEAR All four can be selected using PDL_RTC_UPDATE_ALARM_MONTH PDL_RTC_UPDATE_ALARM_DATE PDL_RTC_UPDATE_ALARM_DAY Parameter data5 is used for the day of the PDL_RTC_UPDATE_ALARM_DOW week data3 The new day of the week and time Ignored if not selected above See R_RTC_Create for the format data4 The new year month and day Ignored if not selected above See R_RTC_Create for the format data5 The new alarm day of the week and time Ignored if not selected above See R_RTC_Create for the format data6 The new alarm year month and day Ignored if not selected above See R_RTC_Create for the format Page 4 192 RENESAS RX210 Group Description 3 4 R20UT0708EE0211 Rev 2 11 Aug 01 2014 data7 Configure the Error Adjustment options To set multiple options at the same time use to separate each value If no change is required specify PDL_NO_DATA Auto Error Adjustment 4 Library Reference PDL_RTC_ERROR_AUTO_ADJUST_DISABLE or PDL_RTC_ERROR AUTO ADJUST ENABLE Enable or disable automatic error adjustment Auto Error Adjustment Period PDL_RTC_ERROR_AUTO ADJUST _PERIOD_60S or PDL_RTC_ERROR AUTO ADJUST PERIOD 10S Select the automatic error adjustment period Auto Error Adjustment Addit
23. Sleep mode return clock source switching PDL_LPC_SLEEP_RETURN_SWITCH_DISABLE or PDL_LPC_SLEEP_RETURN_SWITCH_HOCO or PDL_LPC_SLEEP_RETURN SWITCH MAIN Control clock source switching at cancellation of sleep mode R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS Page 4 68 RX210 Group 4 Library Reference Description 2 5 Flash HOCO software standby control R20UT0708EE0211 Rev 2 11 Aug 01 2014 PDL_LPC_SOFTCUT_POR or Power is supplied to flash memory and HOCO in software standby mode The voltage detection circuit LVD is active and the low power consumption function by the power on reset circuit POR is disabled PDL_LPC_SOFTCUT_HOCO_POR or Power is supplied to flash memory but not supplied to HOCO in software standby mode The voltage detection circuit LVD is active and the low power consumption function by the power on reset circuit POR is disabled PDL_LPC_SOFTCUT_FLASH_HOCO_POR or Power is not supplied to flash memory or HOCO in software standby mode The voltage detection circuit LVD is active and the low power consumption function by the power on reset circuit POR is disabled PDL_LPC_SOFTCUT_LVD or Power is supplied to flash memory and HOCO in software standby mode The voltage detection circuit LVD is stopped and the power consumption reduction function by the power on reset circuit POR is enabled PDL_LPC_SOFTCUT_
24. Callback function for Rx void SCIrx void data_received true Callback function for Tx void SCItx void data_sent true 5 Usage Examples Figure 5 29 Example of SCI Asynchronous operation using interrupts R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS Page 5 55 RX210 Group 5 Usage Examples 5 17 3 SCI Asynchronous Using DMAC This shows the setting of SCI channel 0 and transmission of data using the DMAC Peripheral driver function prototypes include r pdl_sci h include r pdl_cgc h include r pdl dmac h RPDL device specific definitions include r pdl definitions h include lt stddef h gt include lt string h gt const uint8 t string Hello from Renesas RX210 SCI DMAC r n void main void uint8 t SCI status Initialise the system clocks NOTE The code to initialise the system clock using R CGC Set is omitted here Set pin options R SCI Set 0 PDL SCI PIN SCIO RXDO P21 PDL SCI PIN SCIO TXDO P20 i Set up SCIO Async 8N1 19200 baud R_SCI Create 0 PDL SCI _ASYNC PDL SCI 8N1 19200 L de Configure channel 3 of DMAC to be triggered by SCIO Tx R_DMAC Create 3 PDL DMAC REPEAT PDL DMAC SOURCE ADDRESS PLUS PDL DMAC DESTINATION ADDRESS FIXED PDL DMAC SIZE 8 PDL_DMAC_TRIGGER_SCIO_TX string Source const char SCIO TDR Destination
25. RENESAS Pe RX210 Group 4 Library Reference 2 R_CAC_Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example Stop the clock accuracy circuit bool R_CAC_Destroy void No parameter is required Disable and shutdown the Clock frequency accuracy measurement circuit True Clock frequency accuracy measurement circuit None The CAC module is halted to reduce the current consumption RPDL definitions tinclude r pdl_cac h RPDL device specific definitions tinclude r pdl_definitions h void func void Disable the CAC R_CAC_Destroy R20UT0708EE0211 Rev 2 11 Page 4 64 Aug 01 2014 RENESAS RX210 Group 3 R_CAC_Control Synopsis Prototype Description 1 2 R20UT0708EE0211 Rev 2 11 Aug 01 2014 Control the clock accuracy circuit bool R_CAC_Control uint8_t data1 Control options uint32_t data2 Operation changes uint16_t data3 Upper limit value uint16_t data4 Lower limit value 4 Library Reference Modify the Clock frequency accuracy measurement circuit operation data1 Control options All selections are optional If multiple selections are required use to separate each selection If no selections are required specify PDL_NO_DATA e Flag clearing
26. R_BSC_GetStatus Read the External Bus Controller status flags DMA Controller R_DMAC_ Create Configure the DMA controller R_DMAC_Destroy Disable a DMA channel R_DMAC Control Control the DMA controller AJOIN D O AVINI Po Or BY OO PO PB PO Ff CO DO DO CO D O OO NJ Oo BY Cr gt R_DMAC_GetStatus Check the status of the DMA channel R20UT0708EE0211 Rev 2 11 Aug 01 2014 2tENESAS Page 4 1 RX210 Group 4 Library Reference Data Transfer R_DTC_Set Set the Data Transfer Controller options R_DTC Create R_DTC_Destroy Configure the DTC for a transfer Shutdown the Data Transfer Controller Multi function Timer pulse unit Controller R_DTC_Control Control the Data Transfer Controller R_DTC_GetStatus Check the status of the Data Transfer Controller R_ELC_Create Initialise the ELC module Event Link R_ELC_Destroy Disable the ELC module Controller R_ELC_Read Read an ELC port data buffer R_ELC_ Write Write to an ELC port data buffer R_ELC_Control Configure the ELC module R_MTU2_Set Configure the Multi function Timer Pulse Units R_MTU2_Create Configure a MTU channel R_MTU2_Destroy Disable a Multi function Timer Pulse Unit R_MTU2_ControlChannel Control an MTU channel R_MTU2 ControlUnit
27. Real time Clock R_RTC_Create Configure the Real time clock R_RTC_Destroy Shut down the Real time clock R_RTC_Control Modify the Real time clock operation A Oojn d0 aj0 nN R_RTC_Read Read the Real time clock status flags and counters al R_RTC_CreateWarm Reconfigure RTC interrupt setting at warm start up R_SCI_IIC_Read Perform an SCI IIC master read R_SCI_lIC_ReadLastByte 1 R_WDT_Set Configure the Watchdog timer operation Watchdog Timer 2 R_WDT_Control Control the Watchdog operation 3 R_WDT_Read Read the Watchdog timer status and registers Independent 1 R_IWDT_Set Configure the Independent Watchdog operation Watchdog Timer 2 R_IWDT_Control Control the Independent Watchdog operation 3 R_IWDT_Read Read the watchdog timer status and counter 1 R_SCI_Set Configure the SCI pin selection 2 R_SCI_Create SCI channel setup 3 R_SCI_Destroy Shut down a SCI channel 4 R_SCI_Send Send a string of characters Serial 5 R_SCI_Receive Receive a string of characters Communication 6 R_SCI_SPI_Transfer Perform an SCI SPI transfer Interface 7 R_SCI_IIC_Write Perform an SCI IIC master write 8 9 Finish an SCI master read if using DMAC or DTC R_SCI_Control Control the SCI channel ala ajo R_SCl_GetStatus Check the status of an SCI channel R20UT0708EE0211 R
28. Remarks Program example Complete a DMAC or DTC based read process bool R_IIC_MasterReceiveLast uint8_t data1 Channel selection uint8_t data2 Data storage address Read one data byte with NACK and stop data1 Select channel IICn where n 0 data2 The storage location for the data byte True if all parameters are valid and the function completed otherwise false C R_IIC_GetStatus un function must only be used to terminate a Read process that has used the DMAC or e Use R_IIC_GetStatus to determine if the transfer was successful e Please specify one byte less in the Transfer Count when using with the DMAC or DTC RPDL definitions tinclude r pdi iic h RPDL device specific definitions tinclude r pdl definitions h uint8 t data array 5 void func void Read 1 byte on channel 0 and stop R_IIC MasterReceiveLast 0 amp data_array 4 i R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 248 RENESAS RX210 Group 4 Library Reference 7 R_IIC_SlaveMonitor Synopsis Prototype Description Monitor the bus bool R_IIC_SlaveMonitor uint8_t data1 Channel selection uint16_t data2 Channel configuration uint8_t data3 Receive data start address uint16_t data4 Receive threshold void func Callback function uint8_t data5 Interrupt priority level Monitor th
29. Category Reference Remarks Program example Stop the External Bus Controller bool R_BSC_Destroy uint8_t data Area selection Disable an external bus area data Select the external bus area CSn where n 0 to 3 to be disabled True Bus Controller R_BSC_Control ME an error interrupt request will not be disabled by this function Use R_BSC_Control to isable it e Multifunction Pin Control registers are modified by this function e This function is not required when using packages with less than 100 pins RPDL definitions tinclude r pdl_bsc h RPDL device specific definitions tinclude r pdl_definitions h void func void Disable the CS3 area R_BSC_Destroy 3 R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENES Page 4 88 RX210 Group 4 Library Reference 5 R_BSC_Control Synopsis Modify the External Bus Controller operation Prototype bool R_BSC_Control uint8_t data Control options Description Control the BSC operation data Control the BSC operation e Start stop operation PDL_BSC_ENABLE or Enable or disable BSC operation PDL_BSC_DISABLE Ignored for packages with less than 100 pins Error clearing PDL_BSC_ERROR_CLEAR Clear the bus error status registers e Disable bus error interrupt request PDL_BSC_DISABLE_BUSERR_IRQ Disable bus er
30. L NO DATA L NO DATA L NO FUNC L NO DATA L NO FUNC L NO DATA Oooo UU O l g g o a g g t NMI Callback function static void Callback NMI void uint8 t status Read the NMI status R_INTC_GetExtInterruptStatus PDL_INTC_NMI amp status y Did an LVD1 trigger occur if status BIT 6 0 Clear the LVD monitor 1 flag R_LVD Control PDL LVD CLEAR DETECTION PDL NO DATA Clear the NMI LVD1 flag R_INTC ControlExtInterrupt PDL INTC NMI PDL INTC CLEAR LVD1 FLAG Figure 5 5 Example of Voltage Detection Circuit use R20UT0708EE0211 Rev 2 11 Page 5 9 Aug 01 2014 ztENESAS RX210 Group 5 Usage Examples 5 5 Clock Frequency Accuracy Measurement Circuit Figure 5 6 shows an example of clock frequency measurement usage The main clock is used as the reference to measure the LOCO frequency Peripheral driver function prototypes include r pdl_cac h include r pdl_cgc h PDL device specific definitions include r pdl definitions h Callback functions void CAC_frequency error void void CAC measurement complete void void CAC overflow void void main void Configure the LOCO settings R CGC Set L 060 CLK Loco L CGC BCLK DISABLE PDL_CGC_NOT_SUB E3 E3 L NO DATA E3 E3 L NO DATA L NO DATA DEUORRRTDRR Y
31. Page 4 120 RENESAS RX210 Group 4 Library Reference Program example include r pdl elc h RPDL device specific definitions tinclude r pdl_definitions h void func void Create link between event CMT Channel 1 and module SinglePort 0 R_ELC Control PDL ELC CREATE LINK PDL ELC LINK MODULE SINGLE PORT 0 PDL ELC LINK EVENT CMT CHANNEL 1 COMPARE MATCH 1 dF Configure SinglePort 0 as PB 0 Toggle output on event R_ELC Control PDL ELC SINGLE PORT PDL ELC SINGLE PORT 0 PDL ELC PIN PORT B O PDL ELC PIN OUTPUT TOGGLE 5 Enable all Links R ELC Control PDL ELC ENABLE PDL NO DATA PDL NO DATA i R20UT0708EE0211 Rev 2 11 Page 4 121 Aug 01 2014 RENESAS RX210 Group 4 2 14 Multi Function Timer Pulse Unit 1 R_MTU2 Set Synopsis Prototype Description 1 2 R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference Configure the Multi function Timer Pulse Unit bool R_MTU2_Set uint8_t data1 Channel selection uint32_tdata2 Configuration for a channel Set up the global MTU options data1 The channel number n where n 0 to 5 data2 Pin configuration for the channel Use to separate each selection Valid when n 0 PDL_MTU2_PIN_0A_P34 or PDL_MTU2 PIN 0A PB3 Select the P34 or PB3 p
32. uint16_t data1 uint32_t data2 uint32_t data3 Setup and then control the ELC d ata1 Operation selection 4 Library Reference 11 Operation to perform Operation specific configuration 11 Operation specific configuration PDL_ELC_ENABLE or Enable the linkage of all configured events PDL_ELC_DISABLE or Disable the linkage of all events PDL_ELC_CREATE_LINK or Create a link between an event and a module This function must be called for each link required PDL_ELC_REMOVE_LINK or Remove a link previously created PDL_ELC_TIMER_OPERATION or Configure the operation of a timer when triggered by an event PDL_ELC_PORT_GROUP or Define a port group by selecting the pins within a port that make up the group PDL_ELC_PORT_CONTROL or Input and output control options for a port group PDL_ELC_SINGLE_PORT or Selection of a single port and configuration of it when used as an event generator and or a triggered module PDL_ELC_SOFTWARE_EVENT or Generate a software event PDL_ELC_TRIGGER Set DTC trigger from ELC Interrupts options NOTE The specification of parameters data2 and data3 depends on the operation specified in parameter data1 Hence see the section below relating to the specific operation required Operation data1 PDL_ELC_ENABLE data2 data3 Not used Specify PDL_NO_DATA Not used Specify PDL_NO_DATA Operation data1
33. RPDL definitions tinclude r pdl_iic h RPDL device specific definitions tinclude r pdl_definitions h volatile uint8 t data_array 5 void func void Monitor channel 0 using polling R_IIC SlaveMonitor 0 PDL NO DATA data_array 5 PDL NO FUNC 0 R20UT0708EE0211 Rev 2 11 Page 4 250 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 8 R_IIC_SlaveSend Synopsis Write data to a master device Prototype bool R_IIC_SlaveSend uint8_t data1 Channel selection uint8_t data2 Data start address uint16_tdata3 Data count Description Transmit data on the specified channel data1 Select channel IICn where n 0 data2 The start address of the data to be sent data3 The number of bytes available to be sent Return value True if all parameters are valid exclusive and achievable otherwise false If this function is not called from the R_IIC_SlaveMonitor callback function it will complete when a stop condition is detected Category C Reference R_IIC_SlaveMonitor Remarks e Use this function in conjunction with R_IIC_SlaveMonitor Ifthe master requires more data than is supplied and polling or interrupt based transfers are used this function shall loop back to the start of the data The transmitted byte count will also be reset to 0 Program example R
34. Reference Remarks Program example Enable the ELC module bool R_ELC_Create void func1 ELC Interrupt1 callback function uint8_t data1 ELC Interrupt1 Interrupt priority level void func2 ELC Interrupt2 callback function uint8_t data2 ELC Interrupt2 Interrupt priority level Enable the ELC module and provide callback function registration func1 The function to be called when an ELC Interrupt1 ELSR18l occurs Specify PDL_NO_FUNC if not required data1 The interrupt priority level for Interrupt If using Interrupt1 select between 1 lowest priority and 15 highest priority otherwise set to 0 func2 The function to be called when an ELC Interrupt2 ELSR191 occurs Specify PDL_NO_FUNC if not required data2 The interrupt priority level for Interrupt2 If using Interrupt2 select between 1 lowest priority and 15 highest priority otherwise set to 0 True if all parameters are valid otherwise false Event Link Controller R_ELC_Control e Call this function before using any other ELC function e If using ELC Interrupts use this function to register the callback functions and R_ELC_Control to create a link tinclude r pdl_elc h RPDL device specific definitions tinclude r pdl_definitions h void Interrupt2 CallBack void void func void Enable the module and setup an Interrupt2 callback R_ELC Create PDL_NO_ FUNC 0
35. 1 5 Acronyms and abbreviations ADC API BCD Bit bps BSC CGC CMT CPU CRC DAC DC DMA DMAC DOC DSP DTC EEPROM ELC GSM HEW HOCO C IIC INTC 1 0 IWDT kB LOCO LPC LSB MCU MPC MSB MTU NMI OFS PDG PGA PLL POE PWM RAM ROM RPDL RSPI SCI SMBus SPI WDT Analog to Digital Converter Application Programming Interface Binary Coded Decimal Binary digit Bits per second BusState Controller Clock Generation Circuit Compare Match Timer Central Processing Unit Cyclic Redundancy Check Digital to Analog Converter Direct Current Direct Memory Access DMA Controller Data Operation Circuit Digital Signal Processing Data Transfer Controller Electrically Erasable and Programmable ROM Event Link Controller Global System for Mobile communications High performance Embedded Workbench High speed On Chip Oscillator Inter Integrated Circuit C Interrupt Controller Input Output Independent WDT Kilo Byte 1024 bytes Low speed On Chip Oscillator Low Power Consumption Least Significant Bit Microcontroller Unit Multifunction Pin Controller Most Significant Bit Multi function Timer pulse Unit Non Maskable Interrupt Option Function Select Peripheral Driver Generator Programmable Gain Amplifier Phase Locked Loop Port Output Enable Pulse Width Modulation Random Access Memory Read Only Memory Renesas Peripheral Driver Library Renesas SPI Serial Communications Interface System Manage
36. Host Address detection control PDL_IIC_HOST_ADDRESS_DISABLE or Disable or enable detection of the SMBus host PDL_IIC_HOST_ADDRESS ENABLE address data4 Slave address 0 Ignored if slave address 0 detection is disabled data5 Slave address 1 Ignored if slave address 1 detection is disabled data6 Slave address 2 Ignored if slave address 2 detection is disabled data7 Transfer rate control Either The maximum bit rate in bits per second For Master mode the clock division values will be calculated using a 50 duty cycle For Slave mode the rate will be used to calculate the clock stretching period Or b31 b30 b13 b12 b8 b7 b5 b4 bO 4 7 Bit rate high level register 7 Bit rate low level register ICBRH value ICBRL value R20UTO708EE0211 Rev 2 11 Page 4 239 Aug 01 2014 RENESAS RX210 Group 4 Library Reference Description 3 3 Return value Category Reference data8 Rise and fall time compensation If the transfer rate is specified in bits per second the high level and low level durations can be adjusted to allow for application dependent rise and fall times If unsure use 0 b31 b16 b15 bO The SCL rise time in nanoseconds The SCL fall time in nanoseconds Valid from O to 65535 Valid from O to 65535 True if all parameters are valid exclusive and achievable otherwise f
37. PDL_MTU2_D_OC_DISABLED or PDL_MTU2_D_OC_LOW or PDL_MTU2_D_OC_LOW_CM_HIGH or PDL_MTU2_D_OC_LOW_CM_INV or PDL_MTU2_D_OC_HIGH_CM_LOW or PDL_MTU2_D_OC_HIGH or PDL_MTU2_D_OC_HIGH_CM_ INV or MTIOCHND output disabled MTIOCHND output low MTIOCnD initial output low goes high at compare match MTIOCHKD initial output low toggles at compare match MTIOCnD initial output high goes low at compare match MTIOCHND output high MTIOCHKD initial output high toggles at compare match PDL_MTU2_D_IC_RISING_EDGE or PDL_MTU2_D_IC_FALLING EDGE or PDL_MTU2_D IC BOTH EDGES or Input capture at MTIOCnD rising edge Input capture at MTIOCnD falling edge Input capture at MTIOCnD both edges PDL_MTU2_D_IC_COUNT Input capture at channel n 1 up count or down count Valid only for n 0 RENESAS Page 4 130 RX210 Group 4 Library Reference Description 7 9 TGR_U_V_W_ operation Configure the input capture compare match control for general registers TGRU TRGV and TGRW Valid forn 5 The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Input capture compare match control for register TGRU PDL_MTU2_U_CM or Compare match PDL_MTU2_U_IC_RISING_EDGE or PDL_MTU2_U_IC_FALLING EDGE or PDL_MTU2_U_IC_ BOTH EDGES or Input capture at MTICnU rising edge Input capture at MTICnU falling edge Input capture at MTICnU both edges
38. y Configure PLL operation The PLL will be set to 100 MHz ICLK 50 MHz PCLKD 50 MHz PCLKB 25 MHz FCLK 25 MHz BCI 25 MHz BCLK pin 12 5 MHz R CGC Set R20UT0708EE0211 Rev 2 11 Page 5 2 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples PDL CGC CLK PLL PDL CGC BCLK DIV 2 100E6 50E6 50E6 25E6 25E6 25E6 PDL_NO_DATA y Allow time for the main clock oscillator to stabilise This example uses the CMT timer to generate a 100 us delay R_CMT CreateOneShot 0 PDL NO DATA 100E 6 PDL NO FUNC 0 i Select the PLL as the clock source R_CGC_Control PDL_CGC_CLK_PLL PDL_NO_DATA PDL CGC RTC TO BE USED Figure 5 1 Example of Clock configuration and control R20UT0708EE0211 Rev 2 11 Page 5 3 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 2 Interrupt control Figure 5 2 shows an example of external interrupt use Pin IRQ1 DS is used to detect a falling edge and generates an interrupt Pin IRQ3 DS is used to detect a falling edge and is polled Pin IRQ4 on port 3 is used to detect a low level signal and generates an interrupt Further interrupts are prevented until the signal has returned to the high level Peripheral driver function prototypes include r pdl intc h include r pdl_io port h RPDL device specific definitions include r pdl defi
39. If a callback function is specified reception interrupts are used Please see the notes on callback function usage in 6 If the previous transfer did not issue a Stop condition a Repeated Start condition shall be generated The last byte to be read shall be completed with a NACK signal If no callback function is specified this function will operate in polling mode The status flags will be used to manage the data reception If the 12C channel s control registers are directly modified by the user this function may lock up If an error occurs during this polling process the function will terminate If the DMAC or DTC is used use R_IIC_MasterReceiveLast to complete the transfer Use R_IIC_GetStatus to determine if the transfer was successful False will be returned if the DMAC channel has not been allocated using R_DMAC_ Create RPDL definitions include r pdl_iic h RPDL device specific definitions tinclude r pdl_definitions h volatile uint8 t data_array 5 void func void Read 5 bytes from device OxAA on channel 0 using polling R_IIC MasterReceive 0 PDL NO DATA OxAA data_array 5 PDL NO FUNC 0 R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 247 2tENESAS RX210 Group 4 Library Reference 6 R_IIC_MasterReceiveLast Synopsis Prototype Description Return value Category Reference
40. RPDL device specific definitions include r pdl definitions h void func void Set analog channel ANOOO R_ADC_12 Set PDL ADC 12 PIN AN000 P40 R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 271 RENESAS RX210 Group 4 Library Reference 2 R_ADC_12 CreateUnit Synopsis Prototype Description 1 4 Configure the 12 bit ADC unit bool R_ADC_12_CreateUnit uint8_t data1 Unit selection uint32_t data2 Unit specific options uint32_t data3 Options for Group A uint32_t data4 Options for Group B double data5 double data6 double data7 Sampling time for temperature sensor and internal reference voltage Sampling time for sample and hold circuit II Pre charging or discharging time for disconnection detection void func1 Callback function for Group A uint8_t data8 Interrupt priority for Group A void func2 Callback function for Group B uint8_t data9 Set the ADC mode and operating condition data1 Interrupt priority for Group B Select the ADC unit to be configured This must always be 0 data2 Conversion options To set multiple options at the same time use to separate each value The default settings are shown in bold Input source PDL_ADC_12_INPUT_AN or PDL_ADC_12_INPUT_TS or PDL_ADC_12_INPUT_REF Select input from analog channels the temperature sensor or the i
41. Wait for the ADC result while ADC end Shut down TS R_TS Destroy Shut down ADC R_ADC_12_Destroy 0 di void ADC_12 callback void ADC_end true Read ADC result R_ADC_12 Read 0 PDL NO PTR amp ts result y Figure 5 53 Example of Temperature Sensor R20UT0708EE0211 Rev 2 11 Page 5 99 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 24 Comparator A Figure 5 54shows an example of Comparator A usage Peripheral driver function prototypes include r pdl cgc h include r pal cpa h include r pdl intc h include r pal io port h include r pdl lpc h PDL device specific definitions include r pdl definitions h void NMI handler cpa void void CPAO handler void void CPA1 handler void uint8 t FlagsNonMASKABLE false void main void uint8 t FlagsStatus Configure main clock operation using an external 20 0 MHz clock ICLK 20 MHz PCLKD 20 MHz PCLKB 20 MHz FCLK 20 MHz BCLK not used BCLK pin not used R_CGC_Set PDL CGC CLK MAIN PDL CGC BCLK DISABLE PDL CGC_ MAIN RESONATOR PDL CGC NOT SUB 20E6 20E6 20E6 20E6 20E6 PDL NO_ DA PDL _NO DA i Configure PLL operation The PLL will be set to 50 MHz ICLK 25 MHz PCLKD 25 MHz PCLKB 25 MHz FCLK 25 MHz BCLK 25 MHz BCLK pin 12 5 MHz R_CGC_Set PDL_CGC_CLK PLL P
42. de Generate the 2s delay before enabling RTC by R_CGC Control R_CMT CreateOneShot R20UT0708EE0211 Rev 2 11 Page 5 50 Aug 01 2014 ztENESAS RX210 Group 5 Usage Examples PDL_NO_DATA 2 0 PDL_NO_FUNC i Select the HOCO as the clock source R_CGC_Control PDL _CGC_CLK HOCO PDL NO DATA PDL CGC RTC TO BE USED i void Alarm handler void uint8 t flags uint32 t time uint32 t date uint8 t buffer 50 Read time R_RTC_Read PDL_RTC_READ CURRENT amp flags amp time amp date sprintf char buffer Time d d d d d d r n int time amp OxF00000 gt gt 20 int time amp Ox0F0000 gt gt 16 int time 0x00F000 gt gt 12 int time amp Ox000F00 gt gt 8 int time amp 0Ox0000F0 gt gt 4 int time amp 0x00000F gt gt 0 R SCI Send RSK_SCI CHANNEL PDL NO DATA buffer 0 PDL NO FUNC Configure the clock R_RTC Control PDL_NO_DATA PDL RTC UPDATE ALARM TIME PDL NO DATA PDL NO DATA time 0x10 Alarm in another 10 seconds PDL NO DATA PDL NO DATA Error Adjust PDL NO DATA Capture PDL NO DATA Capture PDL NO_ DATA Capture PDL NO DATA Periodic enter deep software standby mode if true bDeepStdbyEnter bDeepStdbyEnter true Figure 5 26 Example of usi
43. Description Return value Category Reference Remarks Program example Configure the SPI pin selection bo Set up the global SPI options Serial Peripheral Interface ol R_SPI_Set uint32_t data data Configure the SPI input and output pins Use to separate each selection Settings for RSPCKA MOSIA and MISOA are compulsory Pin selection Pin selection PDL_SPI_RSPCKA_PAS or PDL_SPI_RSPCKA_PBO or PDL_SPI_RSPCKA PC5 Select the RSPCKA pin PDL_SPI_MOSIA_P16 or PDL_SPI_MOSIA_PA6 or PDL_SPI_MOSIA_PC6 Select the MOSIA pin PDL_SPI_MISOA_P17 or PDL_SPI_MISOA_PA7 or PDL_SPI_MISOA_PC7 Select the MISOA pin PDL_SPI_SSLAO_PA4 or PDL_SPI_SSLAO PC4 Select the SSLAO pin optional PDL_SPI_SSLA1 PAO or PDL_SPI_SSLA1_PCO Select the SSLA1 pin optional PDL_SPI_SSLA2_PA1 or PDL_SPI_SSLA2 PC1 Select the SSLA2 pin optional PDL_SPI_SSLA3_PA2 or PDL_SPI_SSLA3_PC2 Select the SSLA3 pin optional True if all parameters are valid otherwise false SPI R_SPI_Create VO Before calling R_SPI_Create call this function to configure the relevant pins Pins which are not used for the SPI functions may be omitted RPDL definitions include r pdl spi h RPDL device specific definitions tinclude r pdl_definitions h id func void Configure the appli
44. ENESAS C 0 D ae 0 lt Y S C D Renesas Peripheral Driver Library User s Manual RX210 Group All information contained in these materials including products and product specifications represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp without notice Please review the latest information published by Renesas Electronics Corp through various means including the Renesas Electronics Corp website http www renesas com ee Rev 2 11 Aug 2014 10 11 12 Notice Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information Renesas Electronics has used reasonable care in preparing the information included in this document but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics does not assume any liability for infringement of patents co
45. R SPI Set PDL SPI_RSPCKA PA5 PDL_SPI_MOSIA PA6 PDL SPI_MISOA PA7 PDL SPI SSLAO PA4 PDL SPI_SSLA1 PAO PDL SPI _SSLA2 PA1 PDL SPI_SSLA3 PA2 Configure the master SPI channel R_SPI Create MASTER CHANNEL PDL SPI MODE SPI MASTER PDL SPI PIN SSLO LOW PDL SPI PIN SSL PDL SPI PIN SSL2 LOW PDL SPI PIN SSL PDL SPI FRAME 4 R20UT0708EE0211 Rev 2 11 Page 5 92 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples PDL NO DATA 2E6 y Prepare the transfer with slave 0 R_SPI Command MASTER CHANNEL 0 PDL SPI CLOCK MODE 0 PDL SPI LSB FIRST PDL SPI ASSERT SSLO PDL SPI LENGTH 8 PDL NO DATA y Prepare the transfer with slave 1 R_SPI_ Command MASTER CHANNE 1 PDL SPI CLOCK EO PDL SPI LSB FIRST PDL SPI ASSERI Ll PDL SPI LENGTH 9 PDL NO DATA y Prepare the transfer with slave 2 R_SPI Command MASTER CHANNEL 2 PDL SPI CLOCK MODE 0 PDL SPI LSB FIRST PDL SPI ASSERT_SSL2 PDL SPI LENGTH 15 PDL NO DATA Prepare the transfer with slave 3 R_SPI_ Command MASTER CHANNEL 3 PDL SPI CLOCK MODE 0 PDL SPI LSB FIRST PDL SPI ASSERT_SSL3 PDL SPI LENGTH 24 PDL NO_ DATA Transfer all the data once R_SPI Transfer MASTER CHANNEL PDL NO DATA master tx data master rx data 1 PDL NO FUNC
46. data_sent true Figure 5 37 Example of SCI in IIC mode using DMAC R20UT0708EE0211 Rev 2 11 Page 5 70 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 17 11 SCI in IIC Mode using DTC This shows the setting of SCI channel 9 in IIC mode and then a read from an IIC EEPROM using the DTC PDL functions include r pdl sci h include r pdl cgc h include r pdl dtc h PDL device specific definitions tinclude r pdl definitions h static void CallbackRx void SCI IIC Channel define CHANNEL _SCI_TIC 9 TIC Slave address of EEPROM define S AVE ADDRESS OxA0 Address in EEPROM where we will write a byte define EEPROM ADDRESS 0x01 FLag 7 volatile uint8 t data received Reserve an area for the DTC vector table pragma address dtc_vector table 0x00001000 uint32 t dtc vector table 256 void main void Data Buffer volatile uint8 t IIC Buffer 10 DTC needs to write dummy data to SCI TDR when reading uint8 t IIC Dummy value OxFF Reserve 16 bytes full address mode for the transfer data areas uint32 t dtc iicl tx transfer data 4 uint32 t dtc iicl rx transfer data 4 Initialise the system clocks NOTE The code to initialise the system clock using R CGC Set is omitted here Set Channel 9 pin options R SCI Set 9 PDL SCI PIN SCI9 SSCL9 PB6 PDL SCI PIN SCI9
47. include r pdl definitions h void func void Start the ADC conversion process R_ADC_ 12 Control PDL ADC 12 0 ON i R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 280 RENESAS RX210 Group 4 Library Reference 6 R_ADC_12_Read Synopsis Prototype Description Return value Category Reference Read the ADC conversion results bool R_ADC_12_Read uint8_t data1 ADC unit selection uint16_t data2 Pointer to the address where the results are to be stored uint16_t data3 Pointer to the address where the result is to be stored Reads the conversion values for an ADC unit data1 Select the ADC unit to be configured This must always be 0 data2 Specify a pointer to an array with 16 members where the converted values for analog input channels are to be stored data3 Specify a pointer to the address where the converted value for temperature sensor internal reference voltage diagnostic result or double trigger result is to be stored Refer to hardware manual Section 32 2 5 for the format of self diagnostic result True if a valid unit is selected otherwise false 12 bit ADC R_ADC_12_CreateUnit R_ADC_12_CreateChannel Remarks Program example R20UT0708EE0211 Rev 2 11 Aug 01 2014 From 1 to 16 valid conversion results will be read and stored to data2 The number depends on t
48. 4 Reading a pin or 8 bit port value 5 Writing to a pin or 8 bit port 6 Comparing a pin or 8 bit port with a supplied value 7 Modifying a pin or 8 bit port using a logical operation 8 Waiting until a pin or 8 bit port matches a supplied value 9 Configuring the pins that are not available on smaller packages to the required state R20UT0708EE0211 Rev 2 11 Page 2 5 Aug 01 2014 2tENESAS RX210 Group 2 Driver 2 6 Multifunction Pin Controller Driver The driver functions support access to the Multifunction Pin Controller MPC registers which select the mode of operation for the I O pins The other driver functions modify the MPC registers automatically For peripherals that are not supported by the driver library these functions support 1 Reading from an MPC register 2 Writing to an MPC register 3 Modifying an MPC register R20UT0708EE0211 Rev 2 11 Page 2 6 Aug 01 2014 RENESAS RX210 Group 2 Driver 2 7 MCU Operation Driver The driver functions support access to the registers which select the mode of operation for the microcontroller These functions support 1 Controlling the MCU operation and on chip ROM 2 Reading the MCU status flags 3 Setting the MCU start up options R20UT0708EE0211 Rev 2 11 Page 2 7 Aug 01 2014 RENESAS RX210 Group 2 Driver 2 8 Voltage Detection Circuit Driver The driver function supports configuration of VDET1 and VDET2 voltage detection c
49. Assembly Link Library Standard Library RTOS Alo Debug El Category z E E All Loaded Projects 3 8 Optimize level C source file 2 y Details C source file i Assembly source file Speed or size Linkage symbol file Optimize for size y Y Inter module optimization 6 external variables Options C C cpu rx200 dbl_size 8 include PROJDIRJSAPDL include PROJDIR output obj CONFIGDIR ASIFILELEAF obj debug goptimize nologo R20UT0708EE0211 Rev 2 11 Page 1 11 Aug 01 2014 RENESAS RX210 Group 1 Introduction ii Linker Select the Link Library tab Use the key sequence Y O O to show the optimisation options If the Eliminate dead code option is not enabled from the Optimize drop down list select Custom and enable the option RX Standard Toolchain Configuration C C Assembly Link Library Standard Library aros gt Debug a Category Optimize y TJ All Loaded Projects i ipdl_lib_test Show entries for o C source file Optimize items y C source file Assembly source file Optimize mr e Eliminated size Linkage symbol file Eliminate dead code JOptimize branches Use short disp imm Options Link Library noprelink rom D R D_1 R_1 D_2 R_2 nomessage list CONFIGDIRAS PROJECTNAME map optimize symbol_delete R20UT0708EE0211 Rev 2 11 Page 1 12 Aug 01
50. Configure WDT with a 25 to 75 window generate NMI on timeout R WDT Set PDL WDT_ TIMEOUT 1024 PDL WDT PCLK DIV 2048 PDL WDT WIN START 75 PDL WDT WIN END 25 PDL WDT TIMEOUT_NMI i Main program loop while 1 Refresh the watchdog R_WDT_Control PDL_WDT RESET COUNTER i User code is omitted here static void NMI_handler void uintl6 t Status Read the WDT status R_WDT_ Read amp Status Me Has an underflow occurred Status amp BIT 14 0x0u Handle the watchdog underflow here Has a refresh error occurred Status amp BIT 15 0x0u Handle the watchdog refresh error here Figure 5 15 Example of Watchdog Timer use R20UT0708EE0211 Rev 2 11 Page 5 27 Aug 01 2014 ztENESAS RX210 Group 5 Usage Examples 5 13 8 bit Timer 5 13 1 Periodic operation Timer channel 0 is configured to provide pulses on pin TMOO with a pulse width of 500us and an on time of 200us Peripheral driver function prototypes include r pdl_tmr h include r pdl cgon include r pdl intc h RPDL device specific definitions include r pdl definitions h void main void Initialise the system clocks Prepare the main clock settings R_ CGC Set PDL_CGC_CLK_MAIN PDL _CGC_BCLK_DIV_2 PDL CGC MAIN EXTERNAL PDL_CGC_NOT_SUB 20E6 20E6 20E6 20E6 2
51. Description 1 5 Configure the MCU low power conditions bool R_LPC_Create uint32_t data1 Configuration options uint32_t data2 Select deep standby interrupt uint32_t data3 Select deep standby interrupt uint16_t data4 Main oscillator waiting time uint16_t data5 Sub clock oscillator waiting time uint16_t data6 PLL waiting time uint16_t data7 HOCO oscillator waiting time Load the registers that control module or CPU operation data1 Select the required settings If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Software and Deep Software Standby mode output port control PDL_LPC_EXT_BUS_ON or Leave the external bus address and control signals PDL LPC EXT BUS HI Z active or set them to the high impedance state e 1 0 port retention control PDL_LPC_IO_SAME or PDL_LPC_IO_DELAY Select whether I O port retention is cancelled when deep software standby mode is ended or when CPU operation has resumed e Operating power control PDL_LPC_HIGH_SPEED_MODE or PDL_LPC_MIDDLE_SPEED_MODE_1A or PDL_LPC_MIDDLE_SPEED_MODE_1B or PDL_LPC_MIDDLE_SPEED_MODE_2A or PDL_LPC_MIDDLE_SPEED_MODE_2B or PDL_LPC_LOW_SPEED_MODE 1 or PDL_LPC_ LOW SPEED MODE 2 Select the operating power control mode MCU Version restriction see remarks
52. Error Adjustment 1 Capture 0 configuration II Capture 1 configuration II Capture 2 configuration Periodic configuration Description 1 4 data1 Change the clock operation To set multiple options at the same time use to separate each value If no change is required specify PDL_NO_DATA R20UT0708EE0211 Rev 2 11 Aug 01 2014 12 or 24 hour mode Change clock settings and update the time or date PDL_RTC_24_HOUR_MODE or PDL_RTC_12 HOUR_MODE Select 12 or 24 hour mode Alarm control PDL_RTC_ALARM_HOUR_DISABLE or PDL_RTC_ALARM_HOUR_ENABLE PDL_RTC_ALARM_MINUTE_DISABLE or PDL_RTC_ALARM MINUTE ENABLE PDL_RTC_ALARM_SECOND_ DISABLE or PDL_RTC_ALARM SECOND ENABLE All three can be controlled using PDL_RTC_ALARM_TIME_DISABLE or PDL_RTC_ALARM_TIME_ENABLE PDL_RTC_ALARM_YEAR_DISABLE or PDL_RTC_ALARM_YEAR ENABLE PDL_RTC_ALARM_MONTH_DISABLE or PDL_RTC_ALARM_MONTH_ENABLE PDL_RTC_ALARM_DAY_DISABLE or PDL_RTC_ALARM_DAY_ENABLE PDL_RTC_ALARM_DOW_DISABLE or PDL_RTC_ALARM DOW ENABLE All four can be controlled using PDL_RTC_ALARM_DATE_DISABLE or PDL_RTC_ALARM_DATE_ENABLE Clock output control RTC counting will be stopped temporarily during the writing of RTCOE bit PDL_RTC_OUTPUT_DISABLE or PDL_RTC_OUTPUT_ ENABLE Disable or enable the 1 Hz clock output on the R
53. OK to return to the main HEW window R20UT0708EE0211 Rev 2 11 Page 1 7 Aug 01 2014 RENESAS RX210 Group 1 Introduction 5 Include the new source files Use the key sequence Alt P Ato open the Add files to project lt your project gt window Double click on the RPDL folder From the Files of type drop down list select C source file C Use the key sequence Ctrl A to select all of the files as shown below Add files to project rpdl_lib_test Look in RPDL e ej Ed Interrupt_ADC_12 c E Interrupt_DOC c E Interrupt_RTC c Interrupt_BSC c Interrupt_ELC c Interrupt_SCTI c Interrupt_CAC c Interrupt_ITC c Interrupt_SPI c Interrupt_CMT c Sl Interrupt_INTC c Interrupt_TMR c Interrupt _CPA_LYD c E Interrupt_MTU2 c Interrupt_TPU c Interrupt _CPB c E Interrupt_not_RPDL c r_pdl_configuration c El Interrupt_DMAC c Interrupt_POE c File name Interrupt_ADC_12 c Interrupt_BSC c Intern Add Files of type C source file C y Cancel V Relative Path Hide Project Files Click on Add Click on OK to return to the main HEW window 6 Peripherals that are not required If a peripheral module is not required the interrupt handler file does not need to be included If the unused interrupts still require entries in the interrupt vector table edit the file Interrupt_not_RPDL c to uncomment the define for the unused peripherals For example define RPDL A
54. PDL_TPU_TGRD_DTC_TRIGGER_DISABLE or Enable activation of the DTC when a PDL_TPU_TGRD_DTC_TRIGGER_ENABLE TGRD compare match occurs data3 Configure the counter operation If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Counter clock source selection PDL_TPU_CLK_PCLK_DIV_1 or PDL_TPU_CLK_PCLK_DIV_4 or PDL_TPU_CLK_PCLK_DIV_16 or PDL_TPU_CLK PCLK DIV 64 or The internal clock signal PCLK 1 4 16 or 64 PDL_TPU_CLK_PCLK_DIV_256 or PCLK 256 Valid for n 1 3 and 5 PDL_TPU_CLK_PCLK_DIV_1024 or PCLK 1024 Valid for n 2 3 and 4 PDL_TPU_CLK_PCLK_DIV_4096 or PCLK 4096 Valid for n 3 PDL_TPU_CLK_TCLKA or TCLKA pin input Valid for n 0 to 5 PDL_TPU_CLK_TCLKB or TCLKB pin input Valid for n 0 1 and 2 PDL_TPU_CLK_TCLKC or TCLKC pin input Valid for n 0 2 4 and 5 PDL_TPU_CLK_TCLKD or TCLKD pin input Valid for n O and 5 PDL_TPU_CLK_TPU The overflow underflow signal from TPU n 1 Valid for n 1 and 4 Counter clock edge selection PDL_TPU_CLK_FALLING or PDL_TPU_CLK_RISING or PDL_TPU_CLK_ BOTH The clock signal shall be counted on falling rising or both edges Counter clearing PDL_TPU_CLEAR_DISABLE or Clearing is disabled PDL_TPU CLEAR CM Aor
55. Page 4 282 RENESAS RX210 Group 4 Library Reference 2 R_DAC_10_Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example Disable a DAC channel bool R_DAC_10_Destroy uint8_t data Channel selection Disable the channel output data1 Disable selection To set multiple options at the same time use to separate each value PDL_DAC 10 CHANNEL_O Disable channel 0 PDL_DAC 10 CHANNEL_1 Disable channel 1 True if the parameter is valid otherwise false DAC None Once both channels are disabled the module is put into the power down state RPDL definitions include r pdl dac 10 h RPDL device specific definitions include r pdl definitions h void func void Shut down both DAC channels R_DAC_10 Destroy PDL DAC 10 CHANNEL 0 PDL DAC 10 CHANNEL 1 y R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 283 RENESAS RX210 Group 4 Library Reference 3 R_DAC_10 Write Synopsis Prototype Description Return value Category Reference Remarks Program example Write data to a DAC channel bool R_DAC_10_Write uint8_t data1 Channel selection uint16_t data2 Output value uint16_tdata3 Output value Writ
56. Program example data4 4 Library Reference Extended timing control If multiple selections are required use to separate each selection The default settings are shown in bold For Slave mode select PDL_NO_DATA e Extended timing selection PDL_SPI_CLOCK_DELAY_MINIMUM or PDL_SPI_CLOCK_DELAY_EXTENDED the assertion Select the minimum or extended delay between RSPCK oscillation of the SSL pin and the start of e SSL negation delay PDL_SPI_SSL_DELAY_MINIMUM or PDL_SPI_SSL_DELAY_EXTENDED Select the minimum or extended delay between the end of RSPCK oscillation and the negation of the active SSL pin e Next access delay PDL_SPI_NEXT_DELAY_MINIMUM or PDL_SPI_NEXT_DELAY_ EXTENDED frame Select the minimum or extended delay between the end of one frame and the start of the next True if all parameters are valid otherwise false SPI R_SPI_Create For Slave mode operation configure command 0 When Clock synchronous Slave mode is used avoid selecting mode 0 or mode 2 When bit rate register SPBR is set to 0 PDL_SPI_DIV_1 cannot be selected unless using device with 768 Kbytes or more of flash memory or with 144 or more pins e If parity is enabled while in Master mode both the frame data length and data transfer format should be the same for each command RPDL definitions include r pdl spi h RPDL device specific definitions t
57. Real time clock PDL functions include r pdl cgc h include r pal cmth include r pdl_rtc h PDL device specific definitions include r pdl definitions h void main void volatile uint32 t date time Prepare the main clock settings ICLK 20 MHz PCLKD 20 MHz PCLKB 20 MHz FCLK 20 MHz R_CGC_Set PDL_CGC_CLK MAIN PDL CGC_BCLK DISABLE PDL CGC MAIN RESONATOR 20E6 20E6 20E6 20E6 20E6 PDL NO DAJ PDL NO DAJ i Configure the sub clock settings R_CGC_ Set PDL CGC CLK SUB CLOCK PDL CGC_BCLK DISABLE PDL CGC SUB CLOCK CL STANDARD 32768 32768 32768 32768 32768 PDL NO DATA PDL CGC_SUB 2 i Generate the 2s delay before enabling RTC by R_CGC_Control R_CMT CreateOneShot 0 PDL_NO_DATA 2 PDL_NO_FUNC 0 y Select RTC to be used R CGC Control PDL_CGC_CLK MAIN PDL_NO_DATA PDL CGC RTC TO B 7 If Cold start is detected the RTC clock should be re started R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS Page 5 33 RX210 Group 5 Usage Examples R_RTC_Create PDL NO DATA PDL NO DATA 0x02140710 MON 14 07 10 0x20140317 20140317 PDL NO DATA PDL NO DATA PDL NO DATA PDL NO DATA PDL NO DATA PDL NO DATA PDL NO FUNC PDL NO DATA PDL NO FUNC PDL NO DATA i while 1 R_RTC_Read PDL_RTC_
58. e If using this function to perform a full duplex transfer then the transfer mode for transmit and receive can be set independently If using the polling transfer mode for only one direction this function must not be called from an interrupt handler so that interrupts can still be serviced for the non polling transfer direction Page 4 226 RENESAS RX210 Group Program example R20UT0708EE0211 Rev 2 11 Aug 01 2014 PDL functions include r pdl_sci h RPDL device specific definitions include r pdl definitions h void func void Wait while send 5 characters on channel 0 R_SCI_SPI Transfer 0 PDL NO DATA 5 112345 PDL_NO_FUNC PDL_NO_DATA PDL_NO_FUNC PDL_NO_FUNC RENESAS 4 Library Reference Page 4 227 RX210 Group 7 R_SCI_IIC_Write Synopsis Prototype Description 1 2 R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference Perform an IIC master write on an SCI channel bool R_SCI_IIC_Write uint8_tdata1 Channel selection uint16_t data2 Channel configuration uint16_t data3 Slave Address uint16_tdata4 Number of bytes to transfer uint8_t data5 Buffer void func Callback function Perform an IIC master write data1 Select channel SCIn where n 0 to 12 data2 Control options The default options are shown in bold Specify PDL_NO_DATA to use the
59. if id received true Receive data ID 0x01 by polling R_SCI_Receive 9 PDL_NO_DATA receive data 10 PDL_NO_FUNC SCIEr void SCIrx void data_received true void SCIEr void error happen true Figure 5 33 Example of SCI Reception code in Asynchronous Multi Processor mode R20UT0708EE0211 Rev 2 11 Page 5 63 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 17 7 SCI Transmission in Asynchronous Multi Processor mode This shows the setting of SCI channel 9 and the Multi Processor mode transmission of data using interrupts and polling PDL functions include r pdl sci h include r pdl cgc h PDL device specific definitions tinclude r pdl definitions h void SCItx void uint8 t send data0 n rWelcome to the Renesas RX210 n r uint8 t send data testing ASYNC MP mode bool tx_end void main void Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Set pins R_SCI_ Set 9 PDL SCI PIN SCI9 RXD9 PB6 PDL SCI PIN SCI9 TXD9 PB7 7 Configure the RS232 port specify Async MP mode R SCI Create 9 PDL SCI _8N1 PDL SCI _ASYNC MP 9600 Async MP mode data Transmission by CPU ISR E The receiving side must be ready before this ID is transmitted Send Target Station ID 0x0A by internal polling
60. Cleared after a TGRA compare match occurs PDL TPU CLEAR CM Bor Cleared after a TGRB compare match occurs PDL_TPU_CLEAR_CM_C or Cleared after a TGRC compare match occurs Valid for n 0 and 3 PDL_TPU_CLEAR_CM Dor Cleared after a TGRD compare match occurs Valid for n 0 and 3 PDL_TPU_CLEAR_CM_SYNC Cleared by counter clearing on another channel configured for synchronous operation ENESAS Page 4 306 RX210 Group Description 3 5 4 Library Reference Buffer operation valid for channels O and 3 R20UT0708EE0211 Rev 2 11 Aug 01 2014 PDL_TPU_BUFFER_AC_DISABLE or PDL_TPU_BUFFER_AC_ENABLE Disable or enable buffer operation for registers TGRA and TGRC PDL_TPU_BUFFER_BD_DISABLE or PDL_TPU_BUFFER_BD ENABLE Disable or enable buffer operation for registers TGRB and TGRD ADC trigger control PDL_TPU_ADC_TRIG_DISABLE or PDL_TPU_ADC_TRIG_ENABLE Disable or enable ADC conversion start requests on a TGRA input capture compare match data4 Configure the operation for general registers A and B If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Input capture output compare control for register TGRA PDL_TPU_A_OC_DISABLED or PDL_TPU_A_OC_LOW or PDL_TPU_A_OC_LOW_CM HIGH or PDL_TPU_A_OC_LO
61. Figure 5 49 Example of multiple slave Serial Peripheral Interface use R20UT0708EE0211 Rev 2 11 Page 5 93 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 20 CRC calculator Figure 5 50 shows an example of CRC usage The payload and CRC checksum have been received from a remote unit The CRC calculator is used to check that the payload is correct Peripheral driver function prototypes P P include r padl crc h RPDL device specific definitions include r pdl definitions h define LSB 0 void main void uintl6 t crc result Configure the CRC to use the CCITT polynomial R_CRC Create if LSB PDL CRC POLY CRC GGI L_CRC_LSB FIRS else PDL CRC POLY CRC CCIT L_CRC_MSB FIRS fendif Write the payload data R CRC Write OxF0 i Write the first half of the CRC checksum R_CRC_Write 0x8F Y Write the second half of the CRC checksum R_CRC Write OxF7 y Read the CRC calculation result R CRC Read PDL NO DATA amp crc result Shutdown the CRC unit R_CRC_Destroy Figure 5 50 Example of CRC calculation R20UT0708EE0211 Rev 2 11 Page 5 94 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 21 12 bit Analog to Digital Converter Figure 5 51 shows an example of ADC_12 usage Peripheral driver function prototypes include r pdl cgc h include r pdl cmt h
62. Interrupt2_CallBack 5 R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 111 RENESAS RX210 Group 2 R_ELC_Destroy Synopsis Prototype Description Return value Category Reference Disable the ELC module bool R_ELC_Destroy void No parameter is required Disable all links and enable the ELC module stop state True Event Link Controller R_ELC_ Create Remarks Program example include r pdl elc h RPDL device specific definitions include r pdl definitions h void func void R_ELC Destroy R20UT0708EE0211 Rev 2 11 Aug 01 2014 2tENESAS 4 Library Reference Page 4 112 RX210 Group 3 R_ELC_ Read Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference Read the ELC port buffer bool R_ELC_Read uint8_t data1 II Port uint8_t data2 Storage Read the ELC port buffer for the specified port data1 Port selection PDL_ELC_PORT_B or PDL_ELC_PORT_E Select the port whose buffer should be read data2 Address where the port buffer value will be stored True if all parameters are valid and exclusive otherwise false Event Link Controller R_ELC_Create
63. NOTE No clocks pulses will be generated until R_SCI Send is called data received false R_SCI Receive MASTER CHANNEL PDL_NO_DATA rx buffer DATA LENGTH SCI Rx Callback PDL_NO_FUNC Dummy send so the Slave Tx and Master Rx will happen R_SCI_ Send MASTER CHANNEL PDL_NO DATA Dummy A DATA LENGTH PDL_NO_FUNC y Wait for the Rx to finish while data received false Check we got the data we expected if 0 strncmp const char rx buffer Slave 5 while 1 Process the received data here Callback function for Rx static void SCI Rx Callback void data_received true Callback function for Tx static void SCI Tx Callback void data_sent true Figure 5 32 Example of Synchronous Full Duplex operation R20UT0708EE0211 Rev 2 11 Page 5 61 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 17 6 SCI Reception in Asynchronous Multi Processor mode This shows the setting of SCI channel 9 and the Multi Processor mode reception of data using interrupts and polling PDL functions include r pdl sci h include r pdl cgc h include r pdl io port h PDL device specific definitions tinclude r pdl definitions h void SCIrx void void SCIEr void define NUM_DATA 50 volatile uint8_t data received volatile uint8 t error happen vo
64. PDL ELC LINK EVENT MTU2_CHANNEL_1_OVERFLOW or PDL ELC LINK EVENT PDL ELC LINK EVENT MTU2_CHANNEL_1_UNDERFLOW or MTU2_CHANNEL_2_COMPARE_MATCH_2A or PDL ELC LINK EVENT MTU2_CHANNEL_2_COMPARE_MATCH_2B or PDL ELC LINK EVENT MTU2_CHANNEL_2_OVERFLOW or PDL ELC LINK EVENT MTU2_CHANNEL_2_UNDERFLOW or PDL ELC LINK EVENT MTU2_CHANNEL_3_COMPARE_MATCH_3A or PDL ELC LINK EVENT MTU2_CHANNEL_3_COMPARE_MATCH_3B or PDL ELC LINK EVENT MTU2_CHANNEL_3_COMPARE_MATCH_3C or PDL ELC LINK EVENT MTU2_CHANNEL_3_COMPARE_MATCH_3D or PDL ELC LINK EVENT MTU2_CHANNEL_3_OVERFLOW or PDL ELC LINK EVENT MTU2_CHANNEL_4 COMPARE_MATCH_4A or PDL ELC LINK EVENT MTU2_CHANNEL_4 COMPARE_MATCH_4B or PDL ELC LINK EVENT MTU2_CHANNEL_4 COMPARE_MATCH_4C or PDL ELC LINK EVENT MTU2_CHANNEL_4 COMPARE_MATCH_4D or PDL ELC LINK EVENT MTU2_CHANNEL_4 OVERFLOW or PDL ELC LINK EVENT MTU2_CHANNEL_4 UNDERFLOW or PDL ELC LINK EVENT CMT_CHANNEL_1_COMPARE_MATCH_1 or PDL ELC LINK EVENT TMR_CHANNEL_0_COMPARE_MATCH_AO or PDL ELC LINK EVENT TMR_CHANNEL_0_COMPARE_MATCH_BO or PDL ELC LINK EVENT TMR_CHANNEL_0_OVERFLOW or PDL ELC LINK EVENT TMR_CHANNE
65. PDL_SPI_PIN_SSLO_LOW or Select active low or active high PDL_SPI_PIN_SSLO_HIGH or for output signal SSLO PDL_SPI_PIN_SSL1_LOW or Select active low or active high PDL_SPI_PIN_SSL1_HIGH or for output signal SSL1 PDL_SPI_PIN_SSL2_LOW or Select active low or active high PDL_SPI_PIN_SSL2_ HIGH or for output signal SSL2 PDL_SPI_PIN_SSL3_LOW or Select active low or active high PDL_SPI_PIN_SSL3_HIGH or for output signal SSL3 PDL_SPI_PIN_MOSI_IDLE_LAST or a PDL SPI PIN MOSI IDLE LOW or ee output state when no SSLn pin is PDL_SPI_PIN_MOSI_IDLE_HIGH R20UT0708EE0211 Rev 2 11 Page 4 256 Aug 01 2014 RENESAS RX210 Group 4 Library Reference Description 2 3 R20UT0708EE0211 Rev 2 11 Aug 01 2014 data3 Configure the data format If multiple selections are required use to separate each selection The default settings are shown in bold Buffer size PDL_SPI_BUFFER_64 or Select a buffer size of 64 bits up to four 16 bit frames or PDL_SPI_BUFFER_128 128 bits up to four 32 bit frames Frame configuration selection refer to Table 30 4 in the hardware manual Number of Number of frames in Number of Selection command each command transfer transfers transfer frames PDL_SPI_FRAME_1_1 or 1 1 1 PDL_SPI_FRAME_1_2 or 1 2 2 PDL_SPI_FRAME_1_3 or 1 3 3 PDL_SPI_FRAME_1_4 or 1 4 4 PDL_SPI_FRAME_2_1 or 2 1 2 PDL_SPI_FRAME_2_2 or 2 2 4 PDL_SPI_FRAME_3 or 3 1 3 PDL_SPI_FRA
66. R_ SCI Send 9 Ox0A00 PDL SCI MP ID CYCL PDL_NO PTR 0 PDL NO FUNC i tx_end false Send data to Target Station ID 0x0A using interrupts R_SCI_Send 9 PDL NO DATA send data0 0 SCIC while tx_end false Async MP mode data Transmission by polling R20UT0708EE0211 Rev 2 11 Page 5 64 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples NOTE The receiving side must be ready before this ID is transmitted Send Target Station ID 0x01 by internal polling R_SCI_ Send 9 0x0100 PDL SCI MP ID CYCLE PDL_NO PTR 0 PDL NO FUNC y Send data to Target Station ID 0x01 by polling R_ SCI Send 9 PDL_NO_DATA send_data 0 PDL_NO_FUNC i void SCItx void tx_end true Figure 5 34 Example of SCI Transmission code in Asynchronous Multi Processor mode R20UT0708EE0211 Rev 2 11 Page 5 65 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 17 8 SCI in SPI Mode This shows the setting of SCI channel 6 in to SPI master mode and the transmission of data using interrupts PDL functions include r pdl_sci h include r pdl_cgc h PDL device specific definitions include r pdl definitions h static void SCItx void volatile bool data_sent false void main void Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitte
67. R_WDT_Set PDL WDT PCLK DIV 128 PDL_WDT TIMEOUT 8192 PA PDL WDT TIMEOUT RESET PDL WDT WIN START 50 PDL WDT WIN END 25 R20UT0708EE0211 Rev 2 11 Page 4 200 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 2 R_WDT_Control Synopsis Prototype Description Return value Category Reference Remarks Control the Watchdog operation bool R_WDT_Control uint8_t data Control selection Modify the operation of the Watchdog timer data Configure the timer channel e Counter update PDL_WDT_RESET_COUNTER Refresh the counter True if all parameters are valid and exclusive otherwise false Watchdog Timer R_WDT_Set R_WDT_Set must be called first to configure the timer unless using Initial Setting Memory Program example using R_MCU_OFS to enable the WDT from reset RPDL definitions tinclude r pdl_wdt h RPDL device specific definitions tinclude r pdl_definitions h void func void Prevent the watchdog timer from overflowing R_WDT_ Control PDL_WDT RESET COUNTER y R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 201 2tENESAS RX210 Group 4 Library Reference 3 R WDT Read Synopsis Prototype Description Return value Category Refe
68. Renesas Electronics Europe Limited Dukes Meadow Millboard Road Bourne End Buckinghamshire SL8 5FH U K Tel 44 1628 585 100 Fax 44 1628 585 900 Renesas Electronics Europe GmbH Arcadiastrasse 10 40472 D sseldorf Germany Tel 49 211 6503 0 Fax 49 211 6503 1327 Renesas Electronics China Co Ltd Room 1709 Quantum Plaza No 27 ZhiChunLu Haidian District Beijing 100191 P R China Tel 86 10 8235 1155 Fax 86 10 8235 7679 Renesas Electronics Shanghai Co Ltd Unit 301 Tower A Central Towers 555 Langao Road Putuo District Shanghai P R China 200333 Tel 86 21 2226 0888 Fax 86 21 2226 0999 Renesas Electronics Hong Kong Limited Unit 1601 1613 16 F Tower 2 Grand Century Place 193 Prince Edward Road West Mongkok Kowloon Hong Kong Tel 852 2265 6688 Fax 852 2886 9022 9044 Renesas Electronics Taiwan Co Ltd 13F No 363 Fu Shing North Road Taipei 10543 Taiwan Tel 886 2 8175 9600 Fax 886 2 8175 9670 Renesas Electronics Singapore Pte Ltd 80 Bendemeer Road Unit 06 02 Hyflux Innovation Centre Singapore 339949 Tel 65 6213 0200 Fax 65 6213 0300 Renesas Electronics Malaysia Sdn Bhd Unit 906 Block B Menara Amcorp Amcorp Trade Centre No 18 Jin Persiaran Barat 46050 Petaling Jaya Selangor Darul Ehsan Malaysia Tel 60 3 7955 9390 Fax 60 3 7955 9510 Renesas Electronics Korea Co Ltd 12F 234 Teheran ro Gangnam Ku Seoul 135 920 Korea Tel 82 2 558 3737 Fax 82 2 5
69. Specify PDL_NO_PTR if no data shall be processed by this function e g if the DMAC or DTC shall be used to process the received data data5 The number of bytes that must be received before the function completes or the callback function is called If the DMAC or DTC shall be used to handle the received data specify PDL_NO_DATA func Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Transter Parameter method Polling PDL_NO_FUNC This function will continue until the required number of bytes has been received or another event occurs Interrupts The function to be called when bus activity has stopped Either the function to be called when each byte is received or PDL_NO_FUNC Return value R20UT0708EE0211 Rev 2 11 Aug 01 2014 DMA if the callback function specified in R_DMAC_Create will be used DTC The function to be called at the interval specified in R_DTC_Create data6 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid exclusive and achievable otherwise false Page 4 246 RENESAS RX210 Group 4 Library Reference Category Reference C R_IIC_Create R_IIC_GetStatus R_IIC_MasterReceiveLast Reference Program example
70. Target MCU Figure 1 2 System configuration with middleware taking direct control of some peripherals The library is packaged as a A binary file containing all of the peripheral driver functions b Header files containing the information that the user needs to call any of the functions from their own application code and c Interrupt handlers supplied as source code For best use of this library it is required that the user will have the following documents as a minimum i The hardware schematic ii The MCU hardware manual iii This RPDL API User s manual The binary file is produced using the Renesas RX C tool chain It should be usable by another linker that conforms to the Renesas Application Binary Interface RPDL has not been designed to be compatible for use with an RTOS The coding standards and naming conventions are specified by Renesas R20UT0708EE0211 Rev 2 11 Page 1 1 Aug 01 2014 RENESAS RX210 Group 1 Introduction 1 1 Tool chain requirements This RPDL library has been built and tested using the C C Compiler Package for RX Family V 1 02 Release 01 It cannot be used with older versions of the tool chain The latest version of the tool chain can be downloaded from the Renesas Web site Home Products Software and Tools Coding Tools C C Compilers and Assemblers C C Compiler Package for RX Family 1 2 Compiler options when you use this product 1 The options which must be specif
71. func1 The function to be called at the pulse width interval Use PDL_NO_FUNC if not required func2 The function to be called at the periodic interval Use PDL_NO_FUNC if not required data5 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for both parameters functand func2 True if all parameters are valid and exclusive otherwise false Timer TMR R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 163 2tENESAS RX210 Group Reference Remarks R_CGC_Set R_TMR_CreateChannel R_TMR_CreateUnit 4 Library Reference Function R_CGC_Set must be called with the current clock source selected before using this function This function is an alternative to R_TMR_CreateChannel and R_TMR_CreateUnit Please use R_TMR_Set to select the output TMOn pin as required This function will return false if a pin is enabled but is not set properly If a callback function is specified this function will enable the relevant interrupt Please see the notes on callback function use in 6 The timing limits depend on the peripheral module clock PCLKB fecixe MHz Equation 12 5 12 8 1 Timer resolution ON 80ns 83 3ns 125ns Ff rcuxr 2 Periodmin A 160ns 166 7ns 250ns Frcea 2 Periodmax_CHANNEL 167 7ms 174 8ms 262ms Jeorge 92 Periodma
72. r pdl_definitions h uint8 t Flags uint8 t Counter uint8 t CompareMatchA uint8 t CompareMatchB void func void Read the status flags and registers for TMRO R_TMR_ReadChannel 0 amp Flags amp Counter amp CompareMatchA amp CompareMatchB Page 4 175 2tENESAS RX210 Group 4 Library Reference 11 R_TMR_ReadUnit Synopsis Prototype Description Read from timer unit registers bool R_TMR_ReadUnit uint8_t data1 Unit selection uint8_t data2 A pointer to the data storage location uint16_t data3 A pointer to the data storage location uint16_t data4 A pointer to the data storage location uint16_t data5 A pointer to the data storage location Read any of the timer s counter compare or status flag registers data1 The unit number n where n 0 or 1 data2 The status flags shall be stored in the format below A flag will be set to 1 if the condition has been detected Specify PDL_NO_PTR if the flags are not to be read The unit 0 status flags shall be stored in the format Return value Category Reference Remarks R20UT0708EE0211 Rev 2 11 Aug 01 2014 b7 b6 b5 b4 b3 b2 b1 bO TMRO TMR1 0 Compare Compare 0 Compare Compare Oyen match B match A dead match B match A The unit 1 status flags shall be stored in the f
73. 1 uintl6 t strlen char string PDL_NO_DATA PDL NO DATA PDL NO DATA PDL NO FUNC 0 de Enable DMAC R_DMAC Control 3 L DMAC ENABLE PDL NO PTR PDL NO PTR PDL NO DATA PDL NO DATA PDL NO DATA R20UT0708EE0211 Rev 2 11 Page 5 56 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples L NO DAI L NO DAI de Start transmission R_SCI_ Send 0 L SCI DMAC TRIGGER ENABLE PDL NO PTR PDL NO DATA No data as using DMAC PDL NO FUNC de BRR KKK KK KKK KKK KK KKK KKK KK KK KK KK KK KK KK KK KK KK KK KK KK KK KKK KKK KKK KKK KK KK KK KKK IMPORTANT The SCI module does not know when the DMAC has finished therefore we must tell it using the R_SCI_ Control function KKK KKK KKK KK KK KK KEK KKK KKK KK RARA KK KEK KK KK KK KK KEKE KKK KK KEKE KKK AAA KARA A A KK KK Wait for the SCI transmission to end do R_SCI_GetStatus 0 amp SCI_status PDL NO PTR PDL NO PTR PDL NO PTR i While the Transmit status BIT 2 is not reporting idle while SCI_ status amp 0x04 0 Stop the SCI R_SCI Control 0 PDL SCI _STOP_TX i Figure 5 30 Example of SCI Asynchronous operation using interrupts R20UT0708EE0211 Rev 2 11 Page 5 57 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 17 4 Synchronous Transmission and Reception This shows the configuration of SCI channel 6 as the clock master an
74. 2014 RENESAS Pae ders RX210 Group 4 Library Reference 4 2 9 Register Write Protection 1 R_RWEP_Control Synopsis Prototype Description Return value Category References Remarks Program example Control register write protection bool R_RWP_Control uint16_t data II Configuration selection Control register write protection data Write enable control To set multiple options at the same time use to separate each value e Register write control PDL_RWP_ENABLE_CGC_WRITE or Enable or disable writing to CGC PDL_RWP_DISABLE_CGC_WRITE registers PDL_RWP_ENABLE_MODE_RESET_WRITE or Enable or disable writing to Mode Low PDL RWP DISABLE MODE RESET WRITE power Reset and two CGC registers PDL_RWP_ENABLE_LVD_WRITE or Enable or disable writing to LVD PDL_RWP_DISABLE_LVD_WRITE registers PDL_RWP_ENABLE_MPC_WRITE or Enable or disable MPC Register PDL_RWP_DISABLE_MPC_WRITE access PDL_RWP_ENABLE_VRCR_WRITE or Enable or disable VRCR Register PDL_RWP_DISABLE_VRCR_WRITE access True if the parameter is valid otherwise false RWP To allow for nested function calls the access to the enabling disabling of register protection is implemented using a reference counting method Hence a call to disable a register access may only decrement a reference counter and not actually apply
75. Control a Multi function Timer Pulse Unit R_MTU2 ReadChannel Read from MTU channel registers R_MTU2 ReadUnit Read from MTU registers R_POE Set Configure the Port Output Enable module R_POE Create Configure the Port Output Enable event handling A O nN X O O BAjO N O1 Bj O0O N d1 B w0 DN R_TMR_ControlChannel Write to timer channel registers R_TMR_ControlUnit Write to timer unit registers R_TMR_ControlPeriodic ei R_POE Control Control the Port Output Enable module R POE GetStatus Check the status of the Port Output Enable module 1 R_TMR_Set Configure the optional TMR pins 2 R_TMR_CreateChannel Configure a TMR timer channel 3 R_TMR_CreateUnit Configure a TMR timer unit 4 R_TMR_CreatePeriodic Select periodic operation 5 R_TMR_CreateOneShot Configure and use a one shot timer 8 bit Timer 6 R_TMR_Destroy Disable a TMR timer unit 7 8 9 Control periodic operation R_TMR_ReadChannel Read from timer channel registers ala lo R_TMR_ReadUnit Read from timer unit registers Compare Match Timer R_CMT_Create Configure a CMT channel R_CMT_CreateOneShot Configure a CMT channel as a one shot event R_CMT_Destroy Disable a CMT unit R_CMT_Control Control CMT operation R_CMT_Read Read CMT channel status and registers
76. Description Put the CRC calculator into the Power down state with minimal power consumption Return value True Category CRC Reference R_CRC_Create Remarks None Program example RPDL definitions include r pdl crc h RPDL device specific definitions tinclude r_pdl definitions h void func void Shut down the CRC R_CRC_Destroy R20UT0708EE0211 Rev 2 11 Page 4 268 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 3 R_CRC_Write Synopsis Write data into the CRC calculation register Prototype bool R_CRC_Write uint8_t data 1 The data to be used for the calculation Description Write the data into the data input register data The data to be written into the register Return value True Category CRC Reference R_CRC_Create Remarks None Program example RPDL definitions include r pdl crc h RPDL device specific definitions include r pdl definitions h void func void Write FOh into the CRC calculation register R_CRC_Write OxFO y R20UT0708EE0211 Rev 2 11 Page 4 269 Aug 01 2014 RENESAS RX210 Group 4 R_CRC_Read Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT0708EE0211 Rev 2 11 Aug
77. Ensure that the specified functions are valid for the selected port pin The data direction and mode registers may be modified by other driver Create functions Take care to not overwrite existing settings e Pin P35 is fixed as an input and cannot be modified RENESAS ae RX210 Group Program example 4 Library Reference RPDL definitions include r pdl io port h RPDL device specific definitions tinclude r pdl_ definitions h void func void Set the lower 4 bits on port P1 to output R IO PORT ModifyControl PDL IO PORT 1 PDL IO PORT DIRECTION PDL IO PORT OR Ox0F 5 Enable the pull up on pin PA3 R_1O PORT ModifyControl PDL IO PORT A 3 PDL IO PORT PULL UP PDL IO PORT OR 1 5 R20UT0708EE0211 Rev 2 11 Page 4 39 Aug 01 2014 2tENESAS RX210 Group 4 Library Reference 4 R_IO_PORT_Read Synopsis Prototype Description Return value Category Reference Remarks Program example Read data from an I O port bool R_IO_PORT_Read uint16_t data1 Port or port pin selection uint8_t data2 Pointer to the variable in which the value shall be stored Gets the value of an I O port or I O port pin data1 Use either one of the following definition values from 4 2 3 One port definition or One port pin definition da
78. For repeat mode valid between 0 and 255 0 256 transfers data6 The size of each block transfer Valid between 0 and 255 0 256 units Ignored in normal or repeat mode True if all parameters are valid and exclusive otherwise false Data Transfer Controller R_DTC_Set R_DTC_Control If address increment or decrement is selected the address changes according to the number of bytes 1 2 or 4 in each transfer Before calling this function call R_DTC_Set e Call this function before configuring the peripherals that will be involved in the data transfer e Call this function once for each peripheral that will trigger a transfer and for each chained transfer e For chain transfers each transfer data area in the chain must be contiguous When all calls to this function are complete call R_DTC_Control to start the DTC Page 4 104 ENESAS RX210 Group 4 Library Reference Program example RPDL definitions include r pdl dtc h RPDL device specific definitions include r pdl definitions h Reserve 16 bytes data area Use a 32 bit type to make the address a multiple of 4 uint32 t dtc_cmt0O transfer data 4 void func void Configure the DTC for CMTO R_DTC_Create R20UT0708EE0211 Rev 2 11 Aug 01 2014 PDL _DTC_ NORMAL PDL DTC SOURCE ADDRESS FIXED PDL DTC DESTINATION ADDRESS PLUS PDL _DTC_TRIGGER_CMT
79. Library Reference uint32_t data9 II Source address extended repeat area uint32_t data10 Destination address extended repeat area void func Callback function uint8_t data11 Interrupt priority level Set up a DMA channel data1 The channel number n where n 0 to 3 data2 Configure the operation of channel DMAn If multiple selections are required use to separate each selection The default settings are shown in bold Transfer mode selection PDL_DMAC_NORMAL or Normal or PDL_DMAC_REPEAT or Repeat or PDL_DMAC_BLOCK Block mode PDL_DMAC_SOURCE or PDL_DMAC_DESTINATION If Repeat or Block mode is selected the source or destination side can be selected as the Repeat or Block area This selection is optional Address direction selection PDL_DMAC_SOURCE_ADDRESS FIXED or Leave the source address unchanged PDL_DMAC_SOURCE_ADDRESS_ PLUS or increment it decrement it or modify it by PDL_DMAC_SOURCE_ADDRESS_MINUS or the value specified in parameter data8 PDL_DMAC_SOURCE_ADDRESS_OFFSET Address offset is valid only for n 0 PDL_DMAC_DESTINATION_ADDRESS_FIXED or PDL_DMAC_DESTINATION_ADDRESS_PLUS or PDL_DMAC_DESTINATION_ADDRESS_MINUS or PDL_DMAC_DESTINATION_ADDRESS_OFFSET Leave the destination address unchanged increment it decrement it or modify it by the value specified in parameter data8 Address offset is valid only for n 0 Transfer data s
80. PDL SCI PIN SCI2_RXD2 P52 PDL_SCI_PIN_SCI2_SMISO2 P12 or PDL_SCI_PIN_SCI2_SMISO2 P52 SMISO2 PDL SCI PIN_SCI2_SSCL2_P12 or ae PDL_SCI_PIN SCI2 SSCL2 P52 PDL_SCI_PIN_SCI2_TXD2 P13 or aoe PDL_SCI_PIN SCI2 TXD2 P50 PDL_SCI_PIN_SCI2_SMOSI2_P13 or Scl2 See PDL_SCI_PIN_SCI2_SMOSI2_P50 PDL SCI PIN SCl2 SSDA2 P13 or cana PDL SCI PIN SCI2 SSDA2 P50 PDL_SCI_PIN_SCI2_SCK2 P51 SCK2 PDL SCI PIN SCI2 CTS2 P54 CTS2 PDL_SCI_PIN SCI2_RTS2 P54 RTS2 PDL SCI PIN SCI2 SS2 P54 SS2 RENESAS Page 4 208 RX210 Group Description 3 6 Valid when n 3 4 Library Reference R20UT0708EE0211 Rev 2 11 Aug 01 2014 PDL_SCI_PIN_SCI3_RXD3_P16 or PDL_SCI PIN SCI3_RXD3 P25 RAD3 PDL_SCI_PIN_SCI3_SMISO3_P16 or PDL_SCI_PIN_SCI3_SMISO3_P25 SMISOS PDL_SCI_PIN_SCI3_SSCL3_P16 or ame PDL_SCI_PIN_SCI3_SSCL3_P25 PDL_SCI_PIN_SCI3_TXD3_P17 or ad PDL_SCI PIN SCI3_TXD3 P23 PDL_SCI_PIN_SCI3_SMOSI3_P17 or SCI3 Seen PDL_SCI_PIN_SCI3_SMOSI3_P23 PDL_SCI_PIN_SCI3_SSDA3_P17 or ae PDL_SCI_PIN_SCI3_SSDA3_P23 PDL_SCI_PIN_SCI3_SCK3_P15 or ane PDL_SCI_PIN_SCI3_SCK3_P24 PDL SCI PIN SCI3_CTS3 P26 CTS3 PDL_SCI_PIN_SCI3_RTS3_P26 RTS3 PDL_SCI_PIN_SCI3_SS3_P26
81. PDL_ELC_DISABLE data2 data3 RENESAS Not used Specify PDL_NO_DATA Not used Specify PDL_NO_DATA Page 4 115 RX210 Group Description 2 6 R20UT0708EE0211 Rev 2 11 Aug 01 2014 Operation data1 PDL_ELC_CREATE_LINK etl Module Selection 4 Library Reference PDL_ELC_LINK_MODULE_MTU2_CHANNEL_1 or PDL_ELC_LINK_MODULE_MTU2_CHANNEL_2 or PDL_ELC_LINK_MODULE_MTU2_CHANNEL_ 3 or PDL_ELC_LINK_MODULE_MTU2_CHANNEL_4 or PDL_ELC_LINK_MODULE_CMT_CHANNEL_1 or PDL_ELC_LINK_MODULE_TMR_CHANNEL_0 or PDL_ELC_LINK_MODULE_TMR_CHANNEL_2 or PDL_ELC_LINK_MODULE_ADC12 or PDL_ELC_LINK_MODULE_DAC_CHANNEL_0 or PDL_ELC_LINK_MODULE_INTERRUPT_1 or PDL_ELC_LINK_MODULE_INTERRUPT_2 or PDL_ELC_LINK_MODULE_OUTPUT_PORT_B_GROUP or PDL_ELC_LINK_MODULE_OUTPUT_PORT_E_GROUP or PDL_ELC_LINK_MODULE_INPUT_PORT_B_GROUP or PDL_ELC_LINK_MODULE_INPUT_PORT_E_GROUP or PDL_ELC_LINK_MODULE_SINGLE_PORT_0 or PDL_ELC_LINK_MODULE_SINGLE_PORT_1 or PDL_ELC_LINK_MODULE_SINGLE_PORT_2 or PDL_ELC_LINK_MODULE_SINGLE_PORT_3 or PDL_ELC_LINK_MODULE_CLOCK_SOURCE or PDL_ELC_LINK MODULE_POE2 Select the module that will be triggered by the event 2tENESAS Page 4 116 RX210 Group Description 3 6 data3 Event selection 4 Library Reference PDL ELC LINK EVENT MTU2_CHANNEL_1_COMPARE_MATCH_1A or PDL ELC LINK EVENT MTU2_CHANNEL_1_COMPARE_MATCH_1B or
82. PDL_INTC_REG_DTCER_ICU_IRQ4 PDL_INTC_REG_DTCER_DMAC_DMAC3I PDL_INTC_REG_DTCER_ICU_IRQ5 PDL_INTC_REG_DTCER_SCIO_RXI PDL_INTC_REG_DTCER_ICU_IRQ6 PDL_INTC_REG_DTCER_SCIO_TXI PDL_INTC_REG_DTCER_ICU_IRQ7 PDL_INTC_REG_DTCER_SCI1_RXI PDL_INTC_REG_DTCER_ELC_ELSR18l PDL_INTC_REG_DTCER SCI1_TXI PDL_INTC_REG_DTCER _ELC _ELSR19I PDL_INTC_REG_DTCER SCI2_RXI PDL_INTC_REG_DTCER_MTUO_TGIA PDL_INTC_REG_DTCER_SCI2_TXI PDL_INTC_REG_DTCER_MTUO_TGIB PDL_INTC_REG_DTCER_SCI3_RXI PDL_INTC_REG_DTCER _MTUO_TGIC PDL_INTC_REG_DTCER_SCI3_TXI PDL_INTC_REG_DTCER_MTUO_TGID PDL_INTC_REG_DTCER _SCI4_RXI PDL_INTC_REG_DTCER_MTU1_TGIA PDL_INTC_REG_DTCER _SCI4_TXI PDL_INTC_REG_DTCER_MTU1_TGIB PDL_INTC_REG_DTCER_SCI5_RXI PDL_INTC_REG_DTCER_MTU2_TGIA PDL_INTC_REG_DTCER_SCI5_TX PDL_INTC_REG_DTCER_MTU2_TGIB PDL_INTC_REG_DTCER_SCI6_RXI PDL_INTC_REG_DTCER_MTU3_TGIA PDL_INTC_REG_DTCER_SCI6_TXI PDL_INTC_REG_DTCER_MTU3_TGIB PDL_INTC_REG_DTCER_SCI7_RXI PDL_INTC_REG_DTCER_MTU3_TGIC PDL_INTC_REG_DTCER_SCI7_TXI PDL_INTC_REG_DTCER_MTU3_TGID PDL_INTC_REG_DTCER_SCI8_RXI PDL_INTC_REG_DTCER_MTU4 TGIA PDL_INTC_REG_DTCER _SCI8_TXI PDL_INTC_REG_DTCER_MTU4_TGIB PDL_INTC_REG_DTCER_SCI9_RXI PDL_INTC_REG_DTCER_MTU4_TGIC PDL_INTC_REG_DTCER_SCI9_TXI PDL_INTC_REG_DTCER_MTU4_TGID PDL_INTC_REG_DTCER_SCI10_RXI PDL_INTC_REG_DTCER_MTU4_TCIV PDL_INTC_REG_DTCER_SCI10_TXI PDL_INTC_REG_DTCER_MTU5_TGIU PDL_INTC_REG_DTCER_SCI11_RXI PDL_INTC_REG_DTCER_MTU5_TGIV PDL_INTC_REG_DTCER_SCI11_TXI PDL_INTC_REG_DTCER_MTU5_TGIW PDL_IN
83. PDL_LPC_MAIN_2048 or PDL_LPC_MAIN_4096 or PDL_LPC_MAIN_16384 or PDL_LPC_MAIN_32768 or PDL_LPC_MAIN_65536 or PDL_LPC_MAIN_524288 PDL_LPC_MAIN_131072 or PDL_LPC_MAIN_262144 or Select the oscillation settling time ofthe main clock oscillator before the CPU resumes after exiting from software standby mode When updating this value the main clock oscillator must be stopped data5 Select the sub clock oscillator waiting times If no selections are required specify PDL_NO_DATA e Deep Software Standby waiting time PDL_LPC_SUB_2 or PDL_LPC_SUB 4 or PDL_LPC_SUB_8 or PDL_LPC_SUB_16 or PDL_LPC_SUB_32 or PDL_LPC_SUB_64 or PDL_LPC_SUB_512 or PDL_LPC_SUB_1024 or PDL_LPC_SUB_2048 or PDL_LPC_SUB_4096 or PDL_LPC_SUB_16384 or PDL_LPC_SUB_32768 or PDL_LPC_SUB_65536 or PDL_LPC_SUB_131072 or PDL_LPC_SUB_262144 or PDL_LPC_SUB 524288 Select the oscillation settling time of the sub clock oscillator before the CPU resumes after exiting from software standby mode When updating this value the sub clock oscillator must be stopped data6 Select the PLL waiting times If no selections are required specify PDL_NO_DATA e Deep Software Standby waiting time PDL_LPC_PLL_16 or PDL_LPC_PLL_32 or PDL_LPC_PLL_64 or PDL_LPC_PLL_512 or PDL_LPC_PLL_1024 or PDL_LPC_PLL_2048 or PDL_LPC_PLL_4096 or PDL_LPC_PLL_16384 or PDL_LPC_PLL_32768 or PDL_LPC_PLL_65536 or PDL_LPC_PLL_131072 or PDL_LPC_PLL_2
84. PDL_TMR_CLK_EXT_BOTH or The external clock signal TMCIn is used Select rising falling or both edges detected PDL_TMR_CLK_PCLK_DIV_1 or PDL_TMR_CLK_PCLK_DIV_2 or PDL_TMR_CLK_PCLK_DIV_8 or PDL_TMR_CLK_PCLK_DIV_32 or PDL_TMR_CLK_PCLK_DIV_64 or PDL_TMR_CLK_PCLK_DIV_1024 or PDL_TMR_CLK_PCLK_DIV_8192 or The internal clock signal PCLKB 1 2 8 32 64 1024 or 8192 PDL_TMR_CLK_TMR1_OVERFLOW or PDL_TMR_CLK_TMR3_OVERFLOW or The overflow signal from TMR n 1 Valid for n 0 or 2 PDL_TMR_CLK_TMRO_CM_Aor PDL_TMR_CLK_TMR2_CM_A The compare match A signal from TMR n 1 Valid for n 1 or 3 Counter clearing PDL_TMR_CLEAR_DISABLE or Clearing is disabled PDL_TMR_CLEAR_CM_Aor Cleared after a compare match A occurs PDL_TMR_CLEAR_CM_B or Cleared after a compare match B occurs PDL_TMR_CLEAR_RESET_RISING or Cleared by a rising edge on the external reset pin TMRIn PDL_TMR_CLEAR_RESET_HIGH high Cleared when the external reset pin TMRIn is Compare Match A DTC trigger control PDL_TMR_CM_A_DTC_TRIGGER_DISABLE or PDL_TMR_CM A DTC TRIGGER ENABLE Disable or enable activation of the DTC when a Compare Match A occurs Compare Match B DTC trigger control PDL_TMR_CM_B_DTC_TRIGGER_DISABLE or PDL_TMR CM B DTC TRIGGER ENABLE Disable or enable activation of the DTC when a Compare Match
85. RX210 Group 5 Usage Examples R IO PORT Write PDL IO PORT 1 5 0 on LED1 Configure CMT channel 0 for 1kHz operation but not start CMT first R_CMT Create 0 PDL_CMT FREQUENCY PDL CMT STOP 1E3 CMTO_ handler 7 Configure CMT channel 1 in 0 1sec period and start CMT R_CMT Create 1 PDL_CMT_PERIOD 1E 1 CMT1_handler 7 Change the frequency to 10kHz R_ CMT Control 0 PDL CMT FREQUENCY 10E3 MT Read 0 PDL NO PTR PDL_NO_PTR MT Read 1 Flags Counter RC RC Wait for 1s CMT CreateOneShot 0 PDL NO DATA 1 PDL NO FUNC 0 Control 0 PDL_CMT_START 0 now start CMTO Control 1 PDL_CMT_STOP 0 now stop CMT1 void CMTO handler void Invert the port pin R_IO PORT odify PDL IO PORT 1 4 PDL IO PORT XOR 1 void CMT1_ handler void Toggle the LED state R_IO PORT Modify PDL IO PORT 1 5 PDL IO PORT _XOR 1 Figure 5 19 Example of Compare Match Timer use R20UT0708EE0211 Rev 2 11 Page 5 32 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 15 Real time Clock 5 15 1 Use case of RTC configuration and use case These examples show initialization procedure of simple RTC use case 1 Configuration CGC and RTC counting by sub clock only RTC count source Figure 5 20 shows an example of sub clock used as count source and main clock used as system clock before using the
86. R_MTU2_Create_structure data2 R_MTU2_Create_structure members uint32_t channel_mode uint32_t counter_operation uint32_t ADC_trigger_operation uint16_t buffer_operation uint32_t TGR_A_B_ operation uint32_t TGR_C_D_ operation uint32_t TGR_U_V_W_operation uint16_t noise_filter_operation uint16_t TCNT_TCNTU_value uint16_t TGRA_TCNTV_value uint16_t TGRB_TCNTW_value uint16_t TGRC_TGRU_value uint16_t TGRD_TGRV_value uint16_t TGRE_TGRW_value uint16_t TGRF_TADCORA_value uint16_t TADCORB_value uint16_t TADCOBRA_value uint16_t TADCOBRB_value void func1 void func2 void func3 void func4 uint8_t interrupt_priority_1 void func5 void func6 void func7 void func8 uint8_t interrupt_priority_2 Set up a 16 bit MTU2 channel data1 The channel number n where n 0 to 5 channel_mode Configure the channel mode If multiple selections are required use to separate each selection The default settings are shown in bold 4 Library Reference Channel selection A pointer to the structure 1 Configuration selection Configuration selection Configuration selection 1 Configuration selection Configuration selection Configuration selection Configuration selection Configuration selection Register value Register value Register value Register value Register value Register value Register value Register value Register value
87. Reference None Remarks None Program example RPDL definitions include r pdl_ rwp h RPDL device specific definitions tinclude r pdl_definitions h void func void uint8 t PRCR_value uint8 t PWPR_value Read the protection registers R_RWP_GetStatus amp PRCR_value amp PWPR_value y R20UT0708EE0211 Rev 2 11 Page 4 80 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 4 2 10 Bus Controller 1 R_BSC Set Synopsis Prototype Description Return value Category Reference Remarks Program example Configure the internal bus operation bool R_BSC_Set uint16_tdata Bus priority selection Configure the priority of the internal and external buses data Bus priority control If multiple selections are required use to separate each selection The default settings are shown in bold Bus to be accessed Priority PDL BSC PRIORITY RAM CPU RAM Fixed o internal main bus PDL_BSC_PRIORITY_ROM_MB20r poy e toggled with the CPU PDL_BSC_PRIORITY_ROM_CPU i PDL_BSC_PRIORITY_PB1_MB2 or Peripheral 1 PDL_BSC_PRIORITY_PB1_MB1 PUL Boe RORY Pee MB2 0f Peripheral 2 Fixed to internal main bus PDL_BSC PRIORITY _PB2_MB1 al M PDL_BSC_PRIORITY PB6_MB20r oo a pl with internal PDL BSC_PRIORITY_PB6 MB1 PDL BSC PRIORITY EB_MB2 or PDL BSC_PRIORITY_EB_MB1 Externa
88. Register value 1 Callback function 1 Callback function 1 Callback function 1 Callback function 1 Interrupt priority level 1 Callback function 1 Callback function 1 Callback function 1 Callback function 1 Interrupt priority level Operation mode Valid for n 0 to 4 unless stated otherwise PDL_MTU2_ MODE NORMAL or Normal operation PDL_MTU2_MODE PWM1 or Pulse Width Modulation PWM mode 1 PDL_MTU2_MODE_PWM2 or Valid for n 0 1 and 2 Pulse Width Modulation PWM mode 2 PDL_MTU2_MODE_PHASE1 or PDL_MTU2_MODE_PHASE2 or PDL_MTU2_MODE_PHASE3 or PDL_MTU2 MODE _PHASE4 or Phase counting mode 1 2 3 or 4 Valid for n 1 and 2 PDL_MTU2_ MODE PWM_RS or Reset synchronised PWM mode Valid for n 3 PDL_MTU2_MODE_PWM_COMP1 or PDL_MTU2_MODE_PWM_COMP2 or PDL_MTU2 MODE PWM_COMP3 configuring channel 4 Complementary PWM mode 1 2 or 3 Valid for n 3 Select Normal operation when RENESAS Page 4 125 RX210 Group 4 Library Reference Description 2 9 Synchronous mode Valid for n 0 to 4 PDL_MTU2_SYNC_DISABLE or PDL_MTU2_ SYNC ENABLE clearing Disable or enable synchronous pre setting DMAC DTC event trigger control Valid for n 0 to 4 unless stated otherwise PDL_MTU2_TGRA_DMAC_DTC_TRIGGER_DISABLE or PDL_MTU2_TGRA_DMAC_TRIGGER_ENABLE or PDL_MTU2_TGRA_DT
89. bool R_DMAC_Control uint8_t data1 Channel number uint16_tdata2 Control options void data3 Source start address void data4 Destination start address uint16_t data5 Transfer count uint16_t data6 Repeat or Block size int32_t data7 1 Address offset uint32_t data8 Source address extended repeat area uint32_t data9 Destination address extended repeat area Change the state of a DMA controller channel data1 The channel number n where n 0 to 3 data2 Control the channel operation If multiple selections are required use to separate each selection Enable suspend control PDL_DMAC_ENABLE Enable re enable DMA transfers PDL_DMAC_SUSPEND Suspend DMA transfers e Software trigger control PDL_DMAC_START or Start a DMA transfer PDL_DMAC_START_RUN or Start DMA transfers until stopped PDL_DMAC_STOP Stop software triggered transfers Transfer end interrupt flag control PDL_DMAC_CLEAR_DTIF Clear the Transfer End flag PDL_DMAC_CLEAR_ESIF Clear the Transfer Escape End flag The values to be modified PDL_DMAC_UPDATE_SOURCE Source address using parameter data3 PDL DMAC UPDATE DESTINATION Destination address using parameter data4 PDL DMAC UPDATE COUNT Transfer count using parameter data5 PDL_DMAC_UPDATE_SIZE Repeat or Block size using parameter data6 PDL_DMAC_UPDATE_OFFSET Ad
90. include r pdl adc 12 h RPDL device specific definitions include r pdl definitions h void main void uintl6 t ADC 12 result 16 Prepare the main clock settings R_ CGC Set PDL_CGC_CLK_MAIN PDL _CGC_BCLK_DIV_2 PDL CGC MAIN EXTERNAL PDL_CGC_NOT_SUB 20E6 20E6 20E6 20E6 20E6 PDL NO DAT PDL NO DAT Configure PLL operation The PLL will be set to 100 MHz R_CGC_Set PDL CGC CLK PLL PDL CGC BCLK DIV 2 100E6 50E6 50E6 25E6 25E6 25E6 PDL_NO DATA 7 Allow time for the main clock oscillator to stabilise Generate the 100 us delay R_CMT_CreateOneShot 0 PDL NO DATA 100E 6 PDL NO FUNC 0 de Select the PLL as the clock source R_CGC_Control PDL_CGC_CLK_PLL PDL NO DATA PDL NO DATA de Configure analog input for ANO15 R_ADC_12 Set PDL ADC 12 PIN ANO15 PE7 Configure ADC for single scan R_ADC_12 CreateUnit 0 R20UT0708EE0211 Rev 2 11 Page 5 95 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples PDL ADC 12 SCAN SINGLE PDL ADC 12 ADSSTR_CALCULATE PDL_ADC_12 ADSHCR_CALCULATE PDL NO DATA PDL NO DATA 5E 6 3E 6 0 PDL NO FUNC 0 PDL NO FUNC 0 Configure ADC on AN015 R_ADC_12 CreateChannel 0 15 PDL ADC 12 CH SAMPLE AND HOLD ENABLE 5E 6 Start ADC R_ADC_12 Control PDL_ADC_12
91. otherwise false Clock frequency accuracy measurement circuit R_CAC_Create e If signal selection or limit value changes are required the measurement operation must be disabled The Disable operation is executed at the start of this function The Enable operation is executed at the end Therefore both options can be selected together with operation changes in one function call e Ifthe Disable and or Enable operation is selected this function will wait for the operation to complete before continuing To prevent lockup ensure that an enable disable operation is not also performed from a callback function at the same time Ifthe CACREF input is selected the digital filter setting used in R_CAC_Create will be retained RPDL definitions tinclude r pdl_cac h RPDL device specific definitions tinclude r pdl_definitions h void func void Clear the measurement complete flag without stopping R_CAC Control PDL_CAC_CLEAR MEASUREMENT PDL NO DATA PDL NO DATA PDL NO DATA R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENES Page 4 66 RX210 Group 4 R_CAC_GetStatus Synopsis Prototype Description Read the clock accuracy circuit status bool R uint8_t data1 uint16_t data2 uint16_t data3 uint16_t data4 CAC_GetStatus Read the status limit and counter registers data1 The stat
92. uintl6 t RxChars Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Set the CPU s Interrupt Priority Level to 0 R_INTC Write PDL INTC REG IPL 0 y Select the IIC I Opins R_TIC Set PDL_IIC_PIN SDA PDL IIC PIN SCL i Select IIC mode at 100kHz 300ns rise time 200ns fall time R_IIC_ Create 0 PDL IIC MODE IIC PDL IIC INT PCLK DIV 8 PDL NO DATA PDL NO DATA PDL NO DATA PDL NO DATA 100E3 300 lt lt 16 200 y Send the lower address and 3 bytes to the EEPROM using polling if R_IIC_MasterSend 0 PDL NO DATA EPROM ADDRESS eeprom data array 1 4 PDL NO FUNC R20UT0708EE0211 Rev 2 11 Page 5 75 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 0 false Read the channel and transfer status R_IIC_GetStatus 0 amp status_flags amp TxChars PDL NO PTR i Review the flags and transmit count to decide on the next action else Wait for 5ms while the EEPROM updates R_CMT_CreateOneShot 0 0 5E 3 PDL_NO_FUNC Figure 5 41 Configure the I C channel and write 3 data bytes to the first locations R20UT0708EE0211 Rev 2 11 Page 5 76 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 2 Reception IIC channel 1 will be configured for Master operation and used to read four bytes from a slave d
93. 0 PDL TPU PIN AO PAO PDL TPU PIN B0 P17 i Configure channel 0 for dual waveform A and B output R_TPU_Create 0 0 PDL TPU CLK PCLK DIV 1 PDL TPU CLEAR CM B PU A OC LOW CM INV PDL TPU B OC HIGH CM INV L NO FUNC L NO FUNC L NO FUNC L NO FUNC L NO FUNC L NO FUNC Read the status flags and registers A and D for channel 0 R_TPU Read 0 amp Flags PDL NO PTR amp General A PDL_NO PTR PDL NO PTR amp General D di Modify channel 0 R_TPU_ControlChannel 0 PDL_TPU_COUNTER OxFFDD PDL_NO_DATA PDL NO DATA PDL NO DATA R20UT0708EE0211 Rev 2 11 Page 5 107 Aug 01 2014 ztENESAS RX210 Group 5 Usage Examples PDL_NO_DATA i Shutdown the TPU R TPU Destroy a y Figure 5 57 Example of Timer Pluse Unit use The counter is reset when it reaches 399 The 0 value is a valid state so the output toggle frequency is 50 MHz 400 PS Counter value TIOCBO TIOCAO Figure 5 58 Example of TPU operation R20UT0708EE0211 Rev 2 11 Page 5 108 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 28 Multi Function Timer Pulse Unit This show an example of using the Multi Function Timer Pusle Unit Peripheral driver function prototypes include r pdl mtu2 h include r pdl_cgc h include r pdl_cmt h RPDL device specific definitions include r pdl def
94. 0 ON Read ADC result R_ADC_12 Read 0 ADC_12_result PDL NO PTR Shut down ADC R_ADC_12 Destroy 0 Figure 5 51 Example of ADC_12 R20UT0708EE0211 Rev 2 11 Page 5 96 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 22 10 bit Digital to Analog Converter Figure 5 52 shows an example of DAC_10 usage Peripheral driver function prototypes include r pal dace _10 h RPDL device specific definitions include r pdl definitions h void main void Test align right default R_DAC_10 Create PDL DAC 10 CHANNEL 0 PDL DAC 10 CHANNEL 1 Ox3ff 0x0 y Write new data to both DAC channels R_DAC_10 Write PDL DAC 10 CHANNEL 0 PDL DAC 10 CHANNEL 1 0x0367 0x100 hz Shut down both DAC channels R_DAC_10 Destroy PDL DAC 10 CHANNEL O PDL DAC 10 CHANNEL 1 i Test align left R_DAC_10 Create PDL DAC 10 CHANNEL O PDL DAC 10 CHANNEL 1 OxffcO 0x0 y Write new data to both DAC channels R_DAC_10 Write PDL DAC 10 CHANNEL 0 PDL DAC 10 CHANNEL 1 0x0 OxffcO y Shut down both DAC channels R_DAC_ 10 Destroy PDL DAC 10 CHANNEL O PDL DAC 10 CHANNEL 1 PDL DAC 10 ALIGN LEFT Figure 5 52 Example of DAC_10 R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS Page 5 97 RX210 Group 5 Usage Examples 5 23 Temperature Sensor Figure 5 53 shows an example o
95. 0 or 1 PDL_TMR_OUTPUT_IGNORE_CM_A or PDL_TMR_OUTPUT_LOW_CM Aor PDL_TMR_OUTPUT_HIGH_CM_Aor PDL_TMR_OUTPUT_INV_CM_A No change if a compare match A occurs O is output if a compare match A occurs 1 is output if a compare match A occurs The output toggles if a compare match A occurs PDL_TMR_OUTPUT_IGNORE_CM_B or PDL_TMR_OUTPUT_LOW_CM Bor PDL TMR OUTPUT HIGH CM B or PDL_TMR_OUTPUT_INV_CM_B No change if a compare match B occurs 0 is output if a compare match B occurs 1 is output if a compare match B occurs The output toggles if a compare match B occurs data4 The 16 bit counter value data5 The 16 bit compare match A value data6 The 16 bit compare match B value func1 The function to be called when an overflow occurs Use PDL_NO_FUNC if not required func2 The function to be called when a Compare match A occurs Use PDL_NO_FUNC if not required func3 The function to be called when a Compare match B occurs Use PDL_NO_FUNC if not required data7 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for all parameters func1 func2 and func3 True if all parameters are valid and exclusive otherwise false R20UT0708EE0211 Rev 2 11 Aug 01 2014 Category Timer TMR Reference R_TMR_Set Remarks Please use R_TMR_Set to select the input TMCIn TMRIn and outp
96. 0 port R_IO_PORT_Set e lf an invalid port or pin is specified the operation of the function cannot be guaranteed e This function waits for the I O port or port pin value to match the comparison data If the I O port s control registers are directly modified by the user this function may lock up The input buffer for the specified port or pin must be switched on see R_IO_PORT_Set RPDL definitions include r pdl io port h RPDL device specific definitions tinclude r pdl definitions h void func void Wait until pin P05 reads as 0 R_IO PORT Wait PDL IO PORT 0 5 0 Wait until port 6 reads as 0x55 R_IO PORT Wait PDL IO PORT 6 0x55 R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS id RX210 Group 4 Library Reference 9 R_IO_PORT_NotAvailable Synopsis Prototype Description Return value Category References Remarks Program example Configure I O port pins that are not available bool R_IO_PORT_NotAvailable void No parameter is required Set the port pins that are not available on smaller packages to the recommended state True I O port All pins that are not available on the selected package will be configured for CMOS type low level output RPDL definitions include r pdl io port h RPDL device specific definitions include r pdl de
97. 0 to 12 data2 Control options The default options are shown in bold Specify PDL_NO_DATA to use the defaults e DMAC DTC trigger control PDL_SCI_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_SCI_DMAC_TRIGGER_ENABLE or DMAC or DTC when a data byte is PDL_SCI_DTC_TRIGGER_ENABLE received e Continuous receive mode valid only in asychronuous mode PDL_SCI_RX_CONTINUOUS_DISABLE or Disable or enable continuous receive when PDL_SCI_RX_CONTINUOUS_ ENABLE an interrupt is used as the receive method e ID reception control valid only in Multi processor mode Use the upper byte as the station ID PDL SCL Mr ID CYCLE The valid ID range is 0 to 255 data3 The start address of the storage area for the expected data Specify PDL_NO_PTR if no data shall be processed by this function e g if the DMAC or DTC shall be used to process the received data or for ID cycle in Multi processor mode data4 The number of bytes that must be received before the function completes or the callback function is called Specify 0 for the ID cycle in Multi processor mode If the DMAC or DTC shall be used to handle the received data specify PDL_NO_DATA func1 Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Transfer Parameter method Polling PDL_NO_FUNC This function will continue until the required numbe
98. 0x11 0x22 0x33 0x44 0x55 const uint8 t eeprom data array 2 ARRAY 2 SIZE EEPROM MEMORY ADDRESS LOW 0x66 Ox77 0x88 0x99 OxAA OxBB OxCC OxDD Ox OxFF m B m Dy E E F F F uint8 t i Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Select IIC Pins R_IIC Set PDL IIC PIN S DA PDL IIC PIN SCL Configure the DTC controller R_DTC Set PDL DTC ADDRESS FULL R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS aoe RX210 Group 5 Usage Examples tc vector table t up a DTC channel for IIC transmission Create DTC NORMAL DTC SOURCE ADDRESS PLUS DTC DESTINATION ADDRESS FIXED DTC SIZE 8 DTC IRQ COMPLETE A DTC_TRIGGER_IICO TX dtc_iicl tx transfer data eeprom data_array 1 uint8 t amp RIICO ICDRT ARRAY 1 SIZE PDL NO DATA i Set up a DTC channel for IIC reception This will read back the bytes previously written except the last one which will be read using R_IIC MasterReceiveLast R_DTC Create PDL DTC NORMAL PDL DTC SOURCE ADDRESS FIXED PDL DTC DESTINATION ADDRESS PLUS PDL DTC SIZE 8 PDL DTC_IRQ COMPLETE PDL_DTC_TRIGGER_IICO RX dtc_iicl rx transfer data uint8 t amp RIICO ICDRR data_storage ARRAY 1 SIZE 2 Array size written sub address byte last
99. 12 CreateChannel Configure 12 bit ADC analog channels Shut down the ADC unit R_ADC_12_Destroy R_ADC_12_ Control Start or stop the ADC unit R_ADC 12 Read Read the ADC conversion results 10 bit Digital to Analog converter R_ DAC 10 Create Configure the 10 bit DAC module R_DAC 10 Destroy Disable a DAC channel R_DAC_10 Write Write data to a DAC channel Temperature R_TS_Create Configure the Temperature Sensor R_TS_Destroy Shut down the Temperature Sensor SENSO R_TS_Control Control the Temperature Sensor operation R_CPA Create Configure the Comparator A module Comparator A R_CPA_Control Control the Comparator A module R_ CPA GetStatus Check the status of the Comparator A module Comparator B R_CPB_Create Configure a Comparator B channel R_CPB_GetStatus Disable a Comparator B channel R_CPB_Destroy Read the Comparator B channel status Data Operation Circuit R_ DOC Create Configure the Data Operation Circuit R_DOC_Destroy Disable the Data Operation Circuit R_DOC_Control Control the Data Operation Circuit 16 bit Timer Pulse Unit R_DOC_Read Read the Data Operation Circuit result R_DOC Write Write data to the Data Operation Circuit R_TPU_Set Select the I O pins for the TPU R_TPU_Create Configure a TPU channel R_T
100. 2 1 1 i Invert pin P21 R_IO PORT Modify PDL IO PORT 2 1 PDL IO PORT XOR T y And the value on port 4 with 55h R IO PORT Modify PDL IO PORT 4 PDL IO PORT AND 0x55 7 Read the control registers for port P1 R_IO_ PORT _ ReadControl PDL IO PORT 1 PDL IO PORT DIRECTION amp direction Set the lower 4 bits on port P1 to output R_IO_PORT ModifyControl PDL IO PORT 1 PDL IO PORT DIRECTION PDL IO PORT OR R20UT0708EE0211 Rev 2 11 Aug 01 2014 ztENESAS Page 5 6 RX210 Group 5 Usage Examples Ox0F y Enable the pull up on pin PA3 R_IO_PORT_ModifyControl PDL IO PORT A 3 PDL IO PORT PULL_UP PDL IO PORT OR Figure 5 3 Example of I O Port Operations R20UT0708EE0211 Rev 2 11 Page 5 7 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 4 Voltage Detection Circuit 5 4 1 Maskable interrupts This shows an example of Voltage detection circuit usage If the supply voltage drops below 2 8V the callback function is called Peripheral driver function prototypes include r pdl lvd h PDL device specific definitions include r pdl definitions h static void Callback LVD void void main void Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Setup VDET2 to call a function if VCC drops below 2 8V R_
101. 2014 RENESAS RX210 Group 1 Introduction b Set the floating point precision The wide range of possible internal clock frequencies requires double precision floating point number storage Select the CPU tab Click on the Details button to open the CPU details window Use the drop down menu to select Double precision CPU details Detail PIC FID Round to Precision of double Sign of char Sign of bit field unsigned v Bit field order Right z Width of divergence of function 24 bit F Denomalized number allower as a result Replace from int with short enum size is made the smallest Pack struct union and class Use try throw and catch of C Use dynamic_cast and typeid of C r The saved and restored code of the accumulator in interrupt function Click on OK to close the window Click on OK to return to the main HEW window 10 Build the project No further configuration should be required Simply build the project R20UT0708EE0211 Rev 2 11 Page 1 13 Aug 01 2014 RENESAS RX210 Group 1 Introduction 11 Using library with debug information RPDL library with debug information should be chosen in order to step in the RPDL source code for debugging Unzip the RPDL source zip file e g RPDL_RX210_CS x xx_source zip into a folder e g C my_project_folder Set a breakpoint at the RPDL API to be debugged When the program breaks at the RPDL
102. 3 2 3 PDO NO DATA sario aia 3 1 3 2 4 PDE MCUMGROW PR ig Seka Serta a a a A n oran 3 1 3 2 5 PDL VERSION arado oia 3 1 3 2 6 BITC TIMITONS a o ole piaserae et ois eS cee 3 1 Library Reference iii Sebati vec rseal etal cede lead ceeasad eens hal eth AERE tues 4 1 4 1 APLList Dy Peripheral FUNCUION cocoa ita deta eesti ean 4 1 4 2 Description of Each AP iniiai Ad ad tddi 4 4 4 2 1 Clock Generation Circ it siiski an aiui td a dada 4 5 1 REEGO edita A E A 0 ed ie en ete ede 4 5 2 R CGC Control nuca Ad a a eee ented 4 9 3 R CGE GetStatusscei4 2 aa hide A Mined Pees eee ed 4 12 4 2 2 Interrupt Control Unitaire a anti 4 13 1 R INTG SetExt nterr pt o metiri da ii iadaa rad a ast nese de 4 13 2 R_INTC_CreateExtlnterrupt 00 2 2 2 ccccccccce cece eeeeeecceeceeeeeceeeaaaceeceeeeeseseaaaeaeeeeeeeseeenaeeeeeeeeeeeeenaees 4 15 3 R_INTC_CreateSoftwarelnterrupt 0 ccccceeeeceeceecececeeeeeceaeeeeeeeseseceaeaeeeeeeesesenceaeeeeeeeeeeeeeaees 4 17 4 R_INTC_CreateFastlnterrupt cccccccececeeeeeeccceeceeeeeeesecaeaeeeeeeesesenaeaeeeeeeesesencueaeeeeeeeseteneaees 4 18 5 R_INTC_CreateExceptionHandlers cccececceccececeeeeeeeceecaeeeeeeeeeseneaeaeeeeeeeseseccaeaeeeeeeeeeeenaees 4 22 6 RNTC ControlExtlintertu ptt citada ai tia 4 23 7 R_INTC_GetExtinterruptStatuS sehe e a e a E E aa 4 25 SJ IRANTO Read Ae e e E E E E aaa E N E N aa 4 30 9 IRANTO Wiite aa ia da 4 31 AOD RANTE MOYA lo aaa e 4
103. 3 PORT D 4 PDL_POE_3_PORT_B_3or Pin POE3 input selection PDL_POE_8 _PORT_1_7 or PDL_POE_8_PORT_3_0 or PDL_POE_8 PORT_D_3or PDL POE 8 PORT E 3 Pin POE8 input selection R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS Page 4 148 RX210 Group Description 2 2 Return value Category Reference Remarks Program example R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference data3 Configure pin output control If multiple selections are required use to separate each selection All settings are optional Specify PDL_NO_DATA if none are required High impedance request detection If a request is detected on pin POE8 place the MTU PREPO PAN 2 REGLA EMABLE channel 0 I O pins in the high impedance state PDL_POE_HI_Z REQ MTIOCOA PDL POE HI Z REQ MTIOCOB Select the MTU channel 0 I O pins that shall be PDL POE HI Z REQ MTIOCOC controlled by the high impedance request software PDL POE HI_Z REQ MTIOCOD control or the oscillation stop detection flag Select the MTIOCOA MTIOCOB MTIOCOC MTIOCOD MTIOC3B MTIOC3D MTIOC4A PDL_POE_HI_Z_REQ_OSTSTE MTIOC4B MTIOC4C and MTIOC4D pins in high impedance on detection that oscillation has stopped Output short detection PDL POE SHORT 3 4 HI Z If a short is detected place the all the selected MTU i A
104. 32 4 2 3 VOR A o ta E er rrr rece 4 33 H HRSIOSBORT Sd eels O nasa e 4 35 2 gt RO PORT ReadGontrol tocarte iia nina aii aaa E 4 36 3 RA10 PORT ModityControl corista ies ida ile 4 38 4 RJO PORT SRA a A iaa tee anew 4 40 5 RJO PORTA Wte sta il leia aa 4 41 6 ROO PORT Compare arstina A A eaa IA 4 42 odcrkron Ngaron o N gano ao Naron a Nora ooo Nro Nora oo a Nao Nwon R1Os PORT Moda A at ia 4 43 AOF PORT Wal 0 o aan a aa a a e Read 4 44 R10 PORT NotAvailable nsn n id I ae ee 4 45 Multifunction Pin Controller 0 ccccccccecceceeceeeeeeeeeceneeeeeeeeeceeecaaeeeeeeeeesececaaeeeseeeeesessenieeeeeeeeeees 4 46 Ro MPC Read incite ti 1 Tie a arene aad ee lee ae i AAR 4 47 RuMPG Write sree ai a a a nae I eer ie ee ee 4 48 RuiMPC Modify sti it et ies een Tied na nde avd i ae ae nee ae i ei 4 49 MCU operation tin neni ieee A ee ede ine nen ee ae eee 4 50 R MCU Controli a a ened ei aia eeu 4 50 ROMCU GetStatusS ic cic scence a a anit Lee ned seer ine enti deni 4 51 RoMCU OFS iti iis ine ie re ie nav ae ieee ee eine 4 53 Voltage Detection CirCuit cc ccecccccceeeccceedeeenceedenenededeenseesersneeesebsneeesebenededdensesdeensdeddbenededebened 4 56 A ni aep ite neki ead asi ates ate ad ee A 4 56 ES O deate Ladecentiaddadts a a a aai 4 59 RIV DS GetStatuSsretcsetcctabiieie edshestaddiecenaddcceadahaahats eaaa E a ee Ea E bana aa ai a aea Enea 4 60 Clock Frequency Accuracy Measurement Circuit ooooooocccnnnnocinonaccccn
105. 5 6 1 Software Standby Moda ears n EAEE E AEEA E A 5 12 5 6 2 Deep Software Standby Mode ooooooccccnnonccccononccccononcccnnnoncncnonncncnanonnnn nano nn cn naar nc nc naar nccr naar nnnnnnns 5 13 5 12 Bus Controller titi O NS A tb eed 5 15 5 8 DMA controller ein e a Al detente 5 18 5 9 Data Transfer Controller voomiocioniccincci i EAA E EASE EAE EEEE A SESE APEA 5 21 5 9 1 Block transfer MOG sodien enisi nied cave ehaceesi A ESEN EPEA SELE dd 5 21 5 9 2 Chain transfer operation c ccccccceceeeeeeeeeeececeeeeeeceacaece aae aea dadai raae e aaa dan aa aeaiia Te aai 5 23 5 10 POR OUIput Enable A A ie Ma 5 24 5 17 Event LNK ControllOr siira iaa t ee iniciada labrada aadagenstaavensuadedaenagevadeaes 5 26 9 12 Watchdog TIMO s ieira enera EREA aA EE EE EA 5 27 5 13 86 bit TIMO sceri aiir EENE NEE AAE PEA EENES EE ANAE AAAA TEANA ANANE EAA EANAN E 5 28 1al PEO operato a eneee Aaen Rs 5 28 5 14 Compare Match TIME nseni ii a a lesan A EAE a 5 31 Ob nET ila eE olo EEEE A E E et asa E EA A E E E 5 33 5 15 1 Use case of RTC configuration and use case oooonccccinocccccononcccnononcncnnnoncnnnnnnncncnnnnncnnnnnnncncnnns 5 33 1 Configuration CGC and RTC counting by sub clock only RTC count source 5 33 2 Configuration CGC and RTC counting by sub clock both RTC count source and System clock 5 35 3 Usensng capture Pii aeria T S a T A eels tea ae ade Di 5 37 5 15 2 Initialization in case of RTC
106. ADC_trigger_operation Configure the ADC trigger operation If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults ADC conversion trigger control Valid for n 0 to 4 unless stated otherwise PDL_MTU2_ADC_TRIG_TGRA_ENABLE PDL_MTU2_ADC_TRIG_TGRA_DISABLE or Disable or enable ADC start requests on a TGRA compare match or input capture PDL_MTU2_ADC_TRIG_TROUGH_DISABLE or PDL_MTU2_ADC_TRIG_TROUGH_ENABLE Disable or enable ADC start requests on a TCNT underflow Valid for n 4 in complementary PWM mode Control ADC trigger interrupt skipping Valid for n 4 in complementary PWM mode PDL_MTU2_ADC_TRIG_A_TROUGH_INT_SKIP_DISABLE or PDL_MTU2_ADC_TRIG_A_TROUGH_INT_SKIP_ENABLE Disable or link interrupt skipping to ADC trigger TRGnAN on a TCNT underflow PDL_MTU2_ADC_TRIG_B_TROUGH_INT_SKIP_DISABLE or PDL_MTU2_ADC_TRIG_B_TROUGH_INT_SKIP_ENABLE Disable or link interrupt skipping to ADC trigger TRGnBN on a TCNT underflow PDL_MTU2_ADC_TRIG_A_CREST_INT_SKIP_DISABLE or PDL_MTU2_ADC_TRIG_A_CREST_INT_SKIP_ENABLE Disable or link interrupt skipping to ADC trigger TRGnAN on a TGRA compare match PDL_MTU2_ADC_TRIG_B_CREST_INT_SKIP_DISABLE or PDL_MTU2_ADC_TRIG_B_CREST_INT_SKIP_ENABLE Disable or link interrupt skipping to ADC trigger TRGnBN on a TGRA compare match e Co
107. Build the Projects ri cncdebauncacs desta dens T EES AIREA 1 13 11 Using library with debug information oooooooocccnnnnnnnincoconccnnnncnonnnonnnncnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnns 1 14 1 3 3 Header file in ClUSIOM niiit neie tene sn cded eng aaa aaa aa a edu added RARE dana TAA EDA EREET Ate 1 15 1 3 4 Header TIS ONC oa tt a A Te tac ARA ona ded AA AAA RA 1 15 1 3 5 Recommended initialisation code ooooononooccnnnndnninnococcccnnnncnnnnonononnnnnnnnnnn nn ttnn nnanet ttnn nn nn nn nnnnannns 1 16 1 Initialisation of pins that are not available oooooooooocnnnnnnnicococonnnnnncccononccnnnnnnnnnno o nncnnnnnnnnnnnnnnncnn 1 16 2 Initialisation of the sub clock oscillator if NOt USCO oooooonnnnicnnnnanicinnnanoccnnn oran nr rccnnn nor cnnnnnnnns 1 16 1 4 Document struct r rair asa hoed a d a ae oa aa EE aaan aa ea ara Eaa r aR sdana easa 1 17 1 5 Acronyms and abbreviations nea a EA EEA AEE A AEEA EAEE EEA 1 18 2 1B aV E O 2 1 ZN COVOIVIEW a A AA ce A atid leaa a ed res 2 1 2 2 Control Functions SUMMANY ui A dao ad 2 1 2 3 Clock Generation Circuit DrivVer oooonnnnnnncnnnnnnninnnococccononcnnnnnnnnnccnnnnncnnnnn rn nn cnn nn nene rn nn cnn nena 2 3 24 Interrupt Control DVE a a a a a aa a a aae rn nn nn rra 2 4 2 55 VOPOrt Driverraren le a ti Ai AE a sats 2 5 2 6 Multifunction Pin Controller Driver eyci tanani a sa a eiaa a a a a aa i aaa 2 6 21 MCU Operation Drivers ici a id cb a 2 7 2 8 Voltag
108. Configuration selection uint8_t data2 II Pin selection uint32_t data3 Current time uint32_t data4 Current date uint8_t data5 II Capture 0 configuration uint8_t data6 Capture 1 configuration uint8_t data7 Capture 2 configuration uint16_t data8 Periodic configuration uint32_t data9 Alarm time uint32_t data10 Alarm date void func II Callback function uint8_t data11 Interrupt priority level void func2 Callback function uint8_t data12 1 Interrupt priority level Set up and start the Real time clock data1 Configure the clock options To set multiple options at the same time use to separate each value The default settings are shown in bold Specify PDL_NO_DATA to use the defaults if not enabling the alarm 12 or 24 hour mode PDL_RTC_24 HOUR_MODE or PDL RTC 12 HOUR MODE Select 12 or 24 hour mode Alarm enabling PDL_RTC_ALARM_HOUR_ENABLE PDL_RTC_ALARM_MINUTE_ENABLE PDL_RTC_ALARM_SECOND_ENABLE PDL_RTC_ALARM_YEAR_ENABLE PDL_RTC_ALARM_MONTH_ENABLE All four can be enabled using PDL_RTC_ALARM_DAY_ENABLE PDL_RTC_ALARM_DATE_ENABLE PDL_RTC_ALARM_DOW_ENABLE All three can be enabled using PDL_RTC_ALARM_TIME_ENABLE e Clock output control PDL_RTC_OUTPUT_DISABLE or Disable or enable the 1 Hz clock output PDL_RTC_OUTPUT_ENABLE on the RTCOUT pin data2 Specify pins that will be used If
109. DATA DL NO FUNC DL NO DATA TU UN PUD UO R20UT0708EE0211 Rev 2 11 Page 4 276 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 3 R_ADC_12 CreateChannel Synopsis Prototype Description Return value Category Reference Configure 12 bit ADC analog channels bool R_ADC_12_CreateChannel uint8_t data1 ADC unit selection uint8_t data2 Analog channel selection uint16_t data3 Channel configuration double data4 II Sampling time Channel specific control Used to complement R_ADC_12_CreateUnit to configure 12 bit ADC analog channels if analog channels are selected as the input source data1 Select the ADC unit This must always be 0 data2 Select the analog input channel This must be from 0 to 15 data3 Channel options To set multiple options at the same time use to separate each value The default settings are shown in bold Group selection PDL_ADC_12_CH_GROUP_Aor Assign the channel to Group A or PDL_ADC 12 CH_GROUP_B Group B e Value addition control PDL_ADC_12_CH_VALUE_ADDITION_DISABLE or PDL_ADC 12 CH_VALUE ADDITION_ENABLE Enable or disable value addition Double trigger control PDL_ADC_12_CH_DOUBLE_TRIGGER_DISABLE or PDL_ADC_12_CH_DOUBLE_TRIGGER_ENABLE Enable or disable double trigger Sample and hold circuit control PDL_ADC_12_CH_SAMPLE_AND_HOL
110. EVENT DMAC_CHANNEL_2_TRANSFER_END or PDL ELC LINK EVENT DMAC_CHANNEL_3_TRANSFER_END or PDL ELC LINK EVENT DTC_TRANSFER_END or PDL ELC LINK EVENT OSCILLATION_STOP_DETECTION or PDL ELC LINK EVENT INPUT_PORT_GROUP_B or PDL ELC LINK EVENT INPUT_PORT_GROUP_E or PDL ELC LINK EVENT SINGLE_INPUT_PORT_0 or PDL ELC LINK EVENT SINGLE_INPUT_PORT_1 or PDL ELC LINK EVENT SINGLE_INPUT_PORT_2 or PDL ELC LINK EVENT SINGLE_INPUT_PORT_3 or PDL ELC LINK EVENT SOFTWARE_EVENT Select the event that will trigger the module R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS Page 4 117 RX210 Group Description 4 6 4 Library Reference Operation data1 PDL_ELC_REMOVE_LINK etl Module Selection PDL_ELC_LINK_MODULE PDL_ELC_LINK_MODULE PDL_ELC_LINK_MODULE PDL_ELC LINK_ MODULE _ PDL_ELC_LINK_MODULE _ PDL_ELC_LINK MODULE PDL_ELC_LINK MODULE _ PDL_ELC_LINK_MODULE_ PDL_ELC_LINK_MODULE PDL_ELC_LINK_MODULE PDL_ELC_LINK_MODULE PDL ELC LINK MODULE PDL ELC LINK MODULE PDL_ELC_LINK_MODULE PDL_ELC_LINK_MODULE PDL_ELC_LINK_MODULE PDL_ELC_LINK_MODULE PDL_ELC_LINK_MODULE PDL_ELC_LINK_MODULE PDL ELC LINK MODULE PDL_ELC_LINK_MODULE _ MTU2_CHANNEL_1 or MTU2_CHANNEL_2 or MTU2_CHANNEL_3 or MTU2_CHANNEL_4 or CMT_CHAN
111. IO PORI L IO PORT XOR 1 void NMI_ handler cpa void uint8 t irq status Read the IR flag and pin state for IRQ5 R_INTC_GetExtInterruptStatus PDL _INTC_NMI amp irq status y FlagsNonMASKABLE false Figure 5 54 Example of Comparator A R20UT0708EE0211 Rev 2 11 Page 5 102 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 25 Comparator B Figure 5 55shows an example of Comparator B usage PDL functions include r pdl_cgc h include r pdl_io port h include r pdl cpb h PDL device specific definitions include r pdl definitions h void CPB handlerl void void main void uint8 t Flags Prepare the main clock settings R CGC Set PDL CGC _ CLK MAIN PDL CGC BCLK DISABLE PDL CGC MAIN EXTERNAL PDL CGC NOT SUB 20E6 20E6 20E6 20E6 20E6 PDL _NO DAJ PDL NO DAI y Allow 100us for the main clock to stabilise R_CMT CreateOneShot 0 PDL NO DATA 100E 6 PDL_NO_FUNC 0 i Select the PLL as the clock source R_CGC_Control PDL_CGC_CLK_MAIN PDL NO DATA PDL NO DATA R_IO PORT Set PDL IO PORT 1 4 PDL IO PORT OUTPUT Off LEDO R IO PORT Write PDL_IO PORT 1 4 1 Create Comparator B Channel 0 R_CPB Create 0 PDL CPB IRQ ELC FALLING EDGE PDL CPB PCLK DIV 8 CPB handlerl 7 i Read Comparator B status flag R_CPB GetStatus a
112. If Cold start is detected the RTC clock should be re started R_RTC_Create PDL _NO DATA PDL NO DATA 0x02140710 MON 14 07 10 0x20140317 20140317 PDL _NO DATA PDL NO DATA R20UT0708EE0211 Rev 2 11 Page 5 35 Aug 01 2014 RENESAS RX210 Group lol 2l2l2 2 2 laz EEE es EEE UU UUUUYOU Zz i while 1 R_RTC_Read PDL _RTC RI EAD_CURRI PDL NO PT amp time amp date R 5 Usage Examples ENT Figure 5 21 Example of configuration CGC and RTC counting by sub clock R20UT0708EE0211 Rev 2 11 Aug 01 2014 Both RTC count source and System clock RENES Page 5 36 RX210 Group 5 Usage Examples 3 Use using capture pin Figure 5 22 shows an example of using the RTC with a capture pin The sub clock is used as RTC count source and HOCO is used as system clock PDL funetions include r pdl cgc h include r pdl cmt h include r pdl _rtc h PDL device specific definitions include r pdl definitions h uint8 t flags uint32 t time uint32 t date void main void volatile bool bDetected false Prepare the LOCO settings R CGC Seti PDL CGC_CLK_LOCO PDL CGC_BCLK DISABLE PDL CGC SUB CLOCK CL STANDARD 125E3 125E3 125E3 125E3 125E3 PDL_NO_DAJ PDL NO DAJ Prepare the Sub clock settings R_CGC_Set PDL CGC CLK SUB CLOCK PDL CGC BCLK DI
113. Library Reference Remarks e If using the Initial Setting Memory using R_MCU_OFS to enable the WDT from reset this function will have no effect If configuring to use a NMI handler then R_INTC_CreateExtInterrupt must be used to enable the NMI for WDT The timing limits depend on the frequency of the peripheral module clock PCLKB nx cycles Frcuks Period n x cycles or Frequency PCLKB Where n 4 64 128 512 2048 or 8192 cycles 1024 4096 8192 16384 Example periods are given below for feciks 32MHz Time out cycles 1024 4096 8192 16384 Period pPcLk 4 128 us 512 ps 1 024 ms 2 048 ms Period PcLk 64 2 048 ms 8 192 ms 16 38 ms 32 76 ms Period pcLk 128 4 096 ms 16 38 ms 32 77 ms 65 54 ms Period pcik 512 16 38 ms 65 54 ms 131 07 ms 262 14 ms Period pcik 2048 65 536 ms 262 14 ms 524 3 ms 1 049s Period pcLk 8192 262 14 ms 1 049s 2 0978 4 194s Program example RPDL definitions tinclude r pdl_wdt h RPDL device specific definitions tinclude r pdl_definitions h void func void Configure the watchdog timer for PCLKB 4 Timeout cycles 4096 no windowing and reset operation R_WDT_Set PDL WDT_PCLK_DIV 4 PDL_WDT TIMEOUT 4096 PDL WDT TIMEOUT RESET Configure the watchdog timer for PCLKB 128 Timeout cycles 8192 windowing 50 to 25 and reset operation
114. Multi Processor Clock Synchronous Smart Card Interface Simple C Simple SPI 000000 Disabling channels that are no longer required Transmitting data with polling or interrupt mode automatically selected Transfer data in SPI mode Transmitting data in Simple C mode Receiving data in Simple I C mode Completing the reception of data in Simple 1 C mode Receiving data with polling or interrupt mode automatically selected 10 Control the channel operation 11 Reading the status flags Note The Clock Generation Circuit must be configured before configuring any serial channel R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS PRIS anea RX210 Group 2 Driver 2 24 C Bus Interface Driver The driver functions support the use of the 12C module providing the following operations 1 Selection of the 12C pins for use 2 Configuration for use including e Automatic clock setting using transfer rate as an input e Automatic interrupt control 3 Disabling the module that is no longer required and enabling low power mode 4 Transmitting data in Master mode 5 Receiving data in Master mode 6 Completing the reception of data in Master mode 7 Monitoring the bus and handling the reception of data in Slave mode 8 Transmitting data in Slave mode 9 Control of the unit including bus lock up recovery support 10 Reading the status of the module Note The Clock Generation Circuit must be configured befo
115. PDL NO DATA PDL LPC CANCEL RTCA ENABLE PDL NO DATA R20UT0708EE0211 Rev 2 11 Page 5 49 Aug 01 2014 ENESAS RX210 Group 5 Usage Examples L NO DAJ L NO DAJ L NO DAJ de R_RTC_Read PDL RTC READ CURRENT PDL NO PTR amp time amp date de enter deep standby mode after alarm in 10sec while bDeepStdbyEnter false Enter deep software standby mode An internal reset will occur if false R LPC Control PDL LPC MODE DEEP SOFTWARE STANDBY while 1 while 1 static void SetClocks void Prepare the LOCO settings R_CGC_Set PDL CGC CLK LOCO PDL CGC _ BCLK DISABLE PDL CGC SUB CLOCK CL STANDARD 125E3 125E3 125E3 125 3 125 3 PDL NO DAT PDL NO DAT y Configure the HOCO settings R CGC Set PDL CGC_CLK_HOCO L CGC HOCO 50000 PDL CGC BCLK DISABLE RI El AMO L NO DATA A tE Da L NO DATA L NO DATA D OAO OG a TUNNYDWO UW Dt i Sub clock R_CGC_Set PDL_CGC_CLK_SUB_CLOCK PDL _CGC_BCLK DISABLE 32768 Frequency of selected clock source 32768 Frequency of System clock ICLK 32768 Frequency of Peripheral B clock PCLKA 32768 Frequency of Peripheral B clock PCLKB 32768 Frequency of Flash memory clock FCLK PDL NO DATA Frequency of External bus clock PDL_CGC_SUB 2 Sub clock stabilization time
116. PDL_CAC_MEASURE_MAIN or PDL_CAC_MEASURE_SUB_CLOCK or PDL_CAC_MEASURE_HOCO or PDL_CAC_MEASURE_LOCO or PDL_CAC_MEASURE_IWDTLOCO Select the main clock oscillator sub clock oscillator high speed on chip oscillator low speed on chip oscillator or IWDT low speed on chip oscillator for measurement Measured clock division selection PDL_CAC_MEASURE_DIV_1 or PDL_CAC_MEASURE_DIV_4 or PDL_CAC_MEASURE_DIV_8 or PDL_CAC MEASURE DIV_32 Divide the clock to be measured by 1 4 8 or 32 ENESAS Page 4 65 RX210 Group 4 Library Reference Description 2 2 Limit value calculation Return value Category References Remarks Program example PDL_CAC_LIMIT_TOLERANCE or Parameters data3 and data4 will contain either PDL_CAC_LIMIT_REGISTER the tolerance or the limit register values data3 If selected in parameter data2 specify either a the maximum positive deviation for the measured clock as a percentage or b the upper count limit for the measured clock where the maximum value is 65535 If not required specify PDL_NO_DATA data4 If selected in parameter data2 specify either a the maximum negative deviation for the measured clock as a percentage or b the lower count limit for the measured clock where the maximum value is 65535 If not required specify PDL_NO_DATA True if all parameters are valid and exclusive
117. PDL_NO_DATA PDL NO DATA R20UT0708EE0211 Rev 2 11 Page 5 18 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples PDL NO DATA DMACO transfer end handler 7 i Configure channel 1 R_DMAC Create 1 PDL DMAC_BLOCK PDL DMAC SOURCE ADDRESS PLUS PDL DMAC DESTINATION ADDRESS PLUS PDL DMAC SIZE_ PDL DMAC TRIGGER SW source string 2 destination_string 2 1 uint16 t strlen source string 2 PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_FUNC 0 y Set IRQ pin to P31 R_INTC SetExtInterrupt PDL_INTC_IRQ1 PORT 3 1 Enable the SW1 IRQ1 interrupt R_INTC_CreateExtInterrupt PDL INTC _IRQ1 PDL INTC FALLING PDL INTC _ DMAC TRIGG PDL NO FUNC 0 Enable channel 0 AC Control 0 p DMAC L NO P L NO PI ggygg000g Enable and start channel 1 AC Control 1 p DMAC PDL DMAC START L NO P L NO PI Y YUUUUUYO y Read the status for channel 0 R_DMAC GetStatus 0 amp StatusValue amp SourceAddr amp DestAddr amp TransferCount amp SizeCount R20UT0708EE0211 Rev 2 11 Page 5 19 Aug 01 2014 ztENESAS RX210 Group 5 Usage Examples while 1 void DMACO transfer end handler void Invert the port pin R IO PORT Modify PDL IO PORT 1 5 P
118. PDL_NO_FUNC if not required data12 The periodic interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func2 True if all parameters are valid and exclusive otherwise false Real time clock R_CGC_Set R_CGC_Control R_MCU_OFS R_RTC_Read The check for days in the month allows for leap years If entering software standby or deep software standby mode soon after starting the RTC use R_RTC_Read first to confirm that the values are correct e If capture is enabled for a capture pin that has not been selected this function will return false e Before calling this function the count source must be enabled and stable Refer to R_CGC_Set and R_CGC_Control for sub clock and stabilization time configuration e This function is called to use RTC after setting option PDL_CGC_RTC_TO_BE_USED in R_CGC_Control at cold start e This module is not available on the 48 pin package RPDL definitions tinclude r pdl_rtc h RPDL device specific definitions tinclude r pdl definitions h void alarm function void void func void Configure the clock for an alarm at 12 noon every day Using default 24 hour mode R_RTC_Create PDL RTC ALARM HOUR ENABLE PDL RTC ALARM MINUTE ENABLE PDL RTC ALARM SECOND
119. PDL_SPI_CLOCK_MODE_0 or Low Rising PDL_SPI_CLOCK_MODE_1 or Falling PDL_SPI_CLOCK_MODE_2 or Hiah Rising PDL_SPI_CLOCK_MODE_3 9 Falling e Clock division PDL_SPI_DIV_1 or PDL_SPI_DIV_2 or PDL_SPI_DIV_4 or PDL_SPI_DIV_8 Use the bit rate specified for R_SPI_Create 1 2 4 or 8 Ignored in Slave mode SSL assertion PDL_SPI_ASSERT_SSLO or PDL_SPI_ASSERT_SSL1 or PDL_SPI_ASSERT_SSL2 or PDL_SPI_ASSERT_SSL3 The SSL pin to be asserted during the frame transfer Ignored in Slave mode SSL negation PDL_SPI_SSL_NEGATE or PDL_SPI_SSL_KEEP Negate or retain the SSL signal after the frame transfer Ignored in Slave mode Frame data length PDL_SPI_LENGTH 8 or PDL_SPI_LENGTH 9 or PDL_SPI_LENGTH_10 or PDL_SPI_LENGTH_11 or PDL_SPI_LENGTH_12 or PDL_SPI_LENGTH_13 or PDL_SPI_LENGTH_14 or PDL_SPI_LENGTH_15 or PDL_SPI_LENGTH_16 or PDL_SPI_LENGTH_20 or PDL_SPI_LENGTH_24 or PDL_SPI_LENGTH 32 The number of bits in the frame transfer If a buffer size of 64 bits was selected when R_SPI_Create was called the number of bits must not exceed 16 Data transfer format PDL_SPI_MSB_FIRST or PDL_SPI_LSB_FIRST Select least or most significant bit first R20UT0708EE0211 Rev 2 11 Aug 01 2014 2tENESAS Page 4 260 RX210 Group Description 2 2 Return value Category Reference Remarks
120. PDL_TPU_PIN_B2 P15 or PDL_TPU_PIN B2 PA7 Select the P15 or PA7 pin for TIOCB2 Valid when n 3 PDL_TPU_PIN_A3_P21 or PDL_TPU_PIN_A3_PBO Select the P21 or PBO pin for TIOCA3 PDL_TPU_PIN_B3 P20 or PDL_TPU_PIN B3 PB1 Select the P20 or PB1 pin for TIOCB3 PDL_TPU_PIN_C3_P22 or PDL_TPU_PIN_C3 PB2 Select the P22 or PB2 pin for TIOCC3 PDL_TPU_PIN_D3 P23 or PDL_TPU_PIN_D3 PB3 Select the P23 or PB3 pin for TIOCD3 Valid when n 4 PDL_TPU_PIN_A4_P25 or PDL_TPU PIN A4 PB4 Select the P25 or PB4 pin for TIOCA4 PDL_TPU_PIN_B4_P24 or PDL_TPU_PIN_B4 PB5 Select the P24 or PB5 pin for TIOCB4 Valid when n 5 PDL_TPU_PIN_A5 P13 or PDL_TPU_PIN A5 PB6 Select the P13 or PB6 pin for TIOCAS PDL_TPU_PIN_B5 P14 or PDL_TPU_PIN_B5 PB7 Select the P14 or PB7 pin for TIOCB5 RENESAS Page 4 303 RX210 Group Return value Category Reference 4 Library Reference e Valid when n 0 1 2 3 4 5 PDL_TPU_PIN_CLKA P14 or PDL_TPU_PIN_CLKA _PC2 Select the P14 or PC2 pin for TCLKA e Valid when n 0 1 2 5 PDL_TPU_PIN_CLKB_P15 or PDL_TPU_PIN_CLKB_PA3 or Select the P15 PA3 or PC3 pin for TCLKB PDL_TPU_PIN_CLKB_PC3 e Valid when n 0 2 4 5 PDL_TPU_PIN_CLKC_P16 or PDL_TPU_PIN_CLKC_PB2 or Select the P16 PB2 or PCO pin for TCLKC PDL_TPU_PIN_CLKC_PCO PDL_TPU_PIN C
121. PORT D_ 7 Port pin PD PDL_IO PORTE 0 Port pin PEo PDL_IO PORT E 1 Port pin PE PDL_IO PORT E 2 Port pin PE gt PDL_IO PORT E 3 Port pin PE PDL_IO PORT E 4 Port pin PE PDL_IO PORT E 5 Port pin PEs PDL_IO PORT E 6 Port pin PEs PDL_IO_PORT_E 7 Port pin PE PDL_IO PORT F 5 Port pin PFs PDL_IO PORT_H_0_ Port pin PHo PDL_IO PORT_H_1 Port pin PH PDL_IO PORT H 2 Port pin PH2 PDL_IO_PORT_H_3 Port pin PHa PDL_IO PORT J 1 Port pin PJ PDL_IO_PORT_J_3 Port pin PJs PDL_IO PORT J 5 Port pin PJs PDL_IO PORT K2 Port pin PK PDL_IO_PORT_K_3 Port pin PK PDL_IO PORT K 4_ Port pin PK PDL_IO PORT_K_5 Port pin PKs PDL IO PORT LO Port pin PLo PDL IO PORT _L_1 Port pin PL R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS Note Refer to the hardware manual for the port pins which are available on the device that you have selected 4 Library Reference Page 4 34 RX210 Group 4 Library Reference 1 RIO PORT Set Synopsis Configure an I O port Prototype bool R_IO_PORT_Set uint16_t data1 Port pin selection uint16_tdata2 Configuration Description Set the operating conditions for I O port pins data1 Select the port pins to be configured from 4 2 3 Do not use any whole port definitions Multiple pins on the same port may be specified using to separate each pin data2 Choose the pin settings Us
122. REG IPR MTU1 TGIB PDL_INTC_ REG IPR FCU_ FRDY I PDL_INTC_ REG _ IPR MTU1_TCIV PDL_INTC_REG_IPR_ICU_SWINT PDL_INTC REG _IPR_MTU1_TCIU PDL_INTC_REG_IPR_CMTO CMI PDL_INTC_REG_ IPR MTU2_TGIA PDL_INTC REG IPR CMT1 CMI PDL_INTC REG IPR MTU2 TGIB PDL_INTC_ REG _IPR_CMT2_ CMI PDL_INTC_ REG _IPR_MTU2_TCIV PDL_INTC_REG_IPR_CMT3_CMI PDL_INTC_ REG _IPR_MTU2_TCIU PDL_INTC_REG_IPR_CAC_FERRF PDL_INTC_REG_IPR_MTU3_TGIA PDL INTC REG IPR CAC MENDF PDL INTC REG IPR MTU3 TGIB PDL_INTC REG IPR CAC OVFF PDL_INTC REG IPR MTU3 TGIC PDL_INTC REG _IPR_SPIO SPEI PDL_INTC_ REG _ IPR MTU3_TGID PDL_INTC_ REG _IPR_ SPIO SPRI PDL_INTC_ REG IPR MTU3_TCIV PDL_INTC REG _IPR_ SPIO SPTI PDL_INTC REG _ IPR MTU4 _TGIA PDL_INTC REG IPR SPIO SPIl PDL INTC REG IPR MTU4 TGIB PDL INTC REG IPR DOC DOPCF PDL_INTC REG IPR MTU4 TGIC PDL_INTC_REG_IPR_CMPB_CMPBO PDL_INTC_REG_IPR_MTU4_TGID R20UTO708EE0211 Rev 2 11 Page 4 27 Aug 01 2014 RENESAS RX210 Group 4 Library Reference
123. R_CMT Create 1 PDL_CMT FREQUENCY 1E3 PDL NO FUNC 0 Enable the module no ELC interrupts required R_ELC Create PDL NO FUNC PDL NO DATA PDL NO FUNC PDL NO DATA Create link between event CMT Channel 1 and module SinglePort 0 R ELC Control y PDL_ELC_CREATE LINK PDL ELC LINK MODULE SINGLE PORT 0 PDL ELC LINK EVENT CMT CHANNEL 1 COMPARE MATCH 1 Configure SinglePort 0 as PB _0 Toggle output on event R_ELC Control PDL ELC SINGLE PORT PDL ELC SINGLE PORT 0 PDL ELC PIN PORT B 0 PDL ELC PIN OUTPUT TOGGLE Enable All Links R_ELC Control PDL ELC ENABLE PDL NO DATA PDL NO DATA PB_0 will be toggling while 1 R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS Figure 5 14 Example of Event Link Controller Page 5 26 RX210 Group 5 Usage Examples 5 12 Watchdog Timer Here the watchdog is configured to generate an NMI interrupt when the counter underflows Notice how the NMI is enabled for WDT interrupts Peripheral driver function prototypes include z pdl intc h include r pdl wdt h PDL device specific definitions include r pdl definitions h static void NMI handler void void main void Enable the NMI interrupt for WDT R_INTC_CreateExtInterrupt PDL_INTC_NMI PDL INTC WDT ENABLE NMI_handler 7
124. R_SCI_Send RSK_SCI_CHANNEL PDL NO DATA r nRTC Start in Warm start mode Control to change time r n 0 PDL NO FUNC Warm wake up Read time R RTC Read PDL RTC READ CURRENT amp flags time amp date sprintf char buffer RTC Time before changing d d d d d d r n int time 0xF00000 gt gt 20 int time 0x0F0000 gt gt 16 int time 0x00F000 gt gt 12 4 j 0x000F00 gt gt 8 0x0000F0 gt gt 4 0x00000F gt gt 0 R SCI Send RSK_SCI CHANNEL PDL NO DATA buffer 0 PDL NO FUNC Configure the clock R_RTC Control PDL_RTC_CLOCK_ START DATA DATA DATA DATA DATA DATA Error Adjust DATA Capture DATA Capture DAT Capture DAT Periodic pan Li z Li zZ L zZ L Zaz zZ eee iii ici E ggggyvyvyvyvyyyl E W p o t o m t o a AU Ze 7 R_RTC CreateWarm Alarm handler Alarm handler 15 Alarm priority PDL NO FUNC Periodic Hander PDL_NO DATA Periodic priority i R_RTC Read PDL_RTC_READ CURR PDL NO PTR amp time amp date y Configure the clock R_RTC Control P DATA UPDATE ALARM TIMI DATA DATA 0x10 Alarm in another 10 seconds DATA DATA Error Adjust DATA Capture DATA Capture DATA Capture DATA Periodic pe E Bl O Z2
125. SMOSI9 PDL SCI PIN SCI9 SMOSI9 PK2 SCI9 PDL_SCI_PIN_SCI9 SSDA9 PB7 or SSDA9 PDL_SCI_PIN_SCI9 _ SSDA9 PK2 PDL_SCI_PIN_SCI9 SCK9 P60 or SCK9 PDL_SCI_PIN_SCI9 _SCK9 PB5 PDL_SCI_PIN SCI9_CTS9 P61 or CTS PDL SCI PIN SCI9 CTS9 PB4 PDL_SCI_PIN SCI9_RTS9 P61 or RTS9 PDL_SCI_PIN_SCI9 RTS9 PB4 PDL_SCI_PIN_SCI9 SS9 P61 or ss9 PDL_SCI_PIN SCI9 SS9 PB4 Valid when n 10 PDL_SCI_PIN SCI10 RXD10 P81 RXD10 PDL_SCI_PIN_SCI10_SMISO10_P81 SMISO10 PDL_SCI_PIN_SCI10_SSCL10_P81 SSCL10 PDL_SCI_PIN_SCI10_TXD10_P82 TXD10 PDL_SCI PIN SCI10 SMOSI10 P82 SC110 SMOSI10 PDL SCI PIN SCI10 SSDA10 P82 SSDA10 PDL_SCI_PIN_SCI10_SCK10_P80 SCK10 PDL_SCI_PIN_SCI10_CTS10_P83 CTS10 PDL_SCI_PIN_SCI10_RTS10_P83 RTS10 PDL SCI PIN SCI10 SS10 P83 ss10 RENESAS Page 4 211 RX210 Group Description 6 6 Valid when n 11 4 Library Reference Return value Category Reference Remarks Program example R20UT0708EE0211 Rev 2 11 Aug 01 2014 PDL_SCI_PIN_SCI11_RXD11_P76 RXD11 PDL_SCI PIN SCI11_ SMISO11 P76 SMISO11 PDL SCI PIN SCI11 SSCL11 P76 SSCL11 PDL_SCI_PIN_SCI11_TXD11_P77 TXD11 PDL_SCI_PIN_SCI11_SMOSI11_P77 scl SMOSI11 PDL_SCI_PIN_SCI11_SSDA11_P77 SSDA11 PDL_SCI PIN SCl
126. TGRB Valid for n 0 to 4 If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Input capture output compare control for register TGRA PDL_MTU2_A_OC_DISABLED or PDL_MTU2_A_ OC LOW or PDL_MTU2_A_OC_LOW_CM _HIGH or PDL_MTU2_A_OC_LOW_CM_INV or PDL_MTU2_A_OC_HIGH_CM_LOW or PDL_MTU2_A_OC_HIGH or PDL_MTU2_A_OC_HIGH_CM_INV or MTIOCnA output disabled MTIOCnA output low MTIOCnA initial output low goes high at compare match MTIOCnA initial output low toggles at compare match MTIOCnA initial output high goes low at compare match MTIOCnA output high MTIOCnA initial output high toggles at compare match PDL_MTU2_A_IC_RISING_EDGE or PDL_MTU2_A_IC_FALLING EDGE or PDL_MTU2_ A IC_BOTH EDGES or Input capture at MTIOCnA rising edge Input capture at MTIOCnA falling edge Input capture at MTIOCnA both edges PDL_MTU2_A_IC_COUNT or Input capture at channel n 1 up count or down count Valid only for n 0 PDL_MTU2_A_IC_CM_IC Input capture at channel n 1 TGRC compare match or input capture Valid only for n 1 Input capture output compare control for register TGRB PDL_MTU2_B_OC_DISABLED or PDL_MTU2_B OC LOW or PDL_MTU2_B OC _LOW_CM HIGH or PDL_MTU2_B_OC_LOW_CM_INV or PDL_MTU2_B_OC_HIGH_CM_LOW or PDL_MTU2_B_OC_HIGH or PDL_MTU2_B_OC
127. The MPC registers are modified by other driver functions Take care to not overwrite existing settings Refer to the hardware manual for valid values for each register RPDL definitions include r pdl mpc h RPDL device specific definitions include r pdl definitions h void func void Write data to register PDIPFS R MPC Write PDL_MPC_REG_PD1PFS OxFF 7 R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS id RX210 Group 4 Library Reference 3 R_MPC Modify Synopsis Prototype Description Return value Category References Remarks Program example Modify an MPC register bool R_MPC_Modify uint8_t data1 MPC register selection uint8_t data2 Logical operation uint8_t data3 Modification value Write the value to an MPC register data1 One of the definition values from 84 2 4 data2 The logical operation to be applied to the register contents PDL_MPC_AND or PDL_MPC_OR or Select between AND amp OR or Exclusive OR PDL_MPC_XOR data3 The value to be used for the modification True if a valid MPC register is specified otherwise false MPC registers None The MPC registers are modified by other driver functions Take care to not overwrite existing settings Refer to the hardware manual for valid values for each re
128. The standard load capacitance is for the case the sub clock resonator is not fitted PDL_CGC_SUB_CLOCK_CL_LOW or Adjust the drive level for a crystal with low or PDL_CGC_SUB_CLOCK_CL_STANDARD standard load capacitance R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS iia RX210 Group Description 2 2 R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference data3 The frequency of the selected clock source in Hertz data4 The desired frequency of the System clock ICLK in Hertz data5 The desired frequency of the Peripheral module D clock PCLKD in Hertz If the 12 bit ADC will not be used specify PDL_NO_DATA data6 The desired frequency of the Peripheral module B clock PCLKB in Hertz data7 The desired frequency of the Flash memory interface clock FCLK in Hertz data8 The desired frequency of the External Bus clock BCLK in Hertz If the external bus will not be used specify PDL_NO_DATA data9 Select the sub clock oscillator stabilization times If no selections are required specify PDL_NO_DATA Sub clock oscillator waiting time Compulsory option if PDL_CGC_CLK_SUB_CLOCK is selected ignore for 48 pin package Make sure to set the option whether Sub clock is used or not based on the actual board situation PDL_CGC_SUB _ 2 or PDL_CGC_SUB 4 or PDL_CGC_SUB 8 or PDL_CGC_SUB_16 or PDL_CGC_SUB_32 or PDL_CGC_SUB_64 or PDL_CGC_SUB_512 or
129. VREFHO_HALF or PDL ADC 12 SELF DIAGNOSTIC VREFHO FULL or PDL_ADC_12_SELF_DIAGNOSTIC_VREFHO_ROTATED Disable the self diagnostic function or enable and use the voltage on pin VREFHO x 0 X Y x 1 or automatically rotated voltage Result register clearing PDL_ADC_12_RETAIN_RESULT or PDL_ADC 12 CLEAR RESULT Retain or clear the value in each result register after it has been read Disconnection detection assist function control PDL_ADC_12_DDA_DISABLE or PDL_ADC_12_DDA_PRECHARGE or PDL_ADC_ 12 DDA DISCHARGE Disable the Disconnection detection assist function or enable and set it to pre charge or discharge mode Sampling time calculation for temperature sensor internal reference voltage or self diagnosis PDL_ADC_12_ADSSTR_CALCULATE or PDL_ADC_12_ADSSTR_SPECIFY Select whether parameter data5 is used to calculate the ADSSTR value or contains the value to be stored in register ADSSTR Sampling time calculation for sample and hold circuit PDL_ADC_12 ADSHCR_CALCULATE or PDL ADC 12 ADSHCR_SPECIFY Select whether parameter data6 is used to calculate the ADSHCR value or contains the value to be stored in register ADSHCR Pre charging or discharging time calculation for disconnection detection PDL_ADC_12_ADDISCR_CALCULATE or PDL_ADC_12 ADDISCR_SPECIFY Select whether parameter data7 is used to calculate the ADDISCR value or contains the value
130. an EEPROM using two DMAC channels R20UT0708EE0211 Rev 2 11 Page 5 87 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 18 4 Slave mode In this example the MCU behaves as a slave device on channel 0 It will respond to 7 bit address 0001001b or 10 bit address 0010010010b Peripheral driver function prototypes include r pal iic h include r pdl cgc h include r pal intc h include r pdl cmt h RPDL device specific definitions include r pdl definitions h Define the size of the virtual memory define STORAGE SIZE 0x100 define RX_ BUFFER SIZE STORAGE SIZE 1 define MCU_ADDRESS 0 0x12 lt lt 1 define MCU_ADDRESS 1 0x0124 lt lt 1 static void StoreData uint16_t count void slave event handler void volatile uint8_t data storage index 0 volatile uint8 t data storage STORAGE SIZE volatile uint8 t Rx Buffer RX BUFFER SIZE void main void Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Select the IIC I O pins R_TIC Set PDL_IIC_PIN SDA PDL IIC PIN SCL i Select IIC mode at 100kHz 300ns rise time 200ns fall time R_IIC_Create 0 PDL IIC MODE IIC PDL IIC_INT PCLK DIV 8 PDL IIC SLAVE 0 ENABLE 7 PDL IIC SLAVE 1 ENABLE 10 MCU_ADDRESS _0 MCU ADDRESS 1 PDL NO DATA 100E3 300 lt lt 16 200 all _data_read
131. as normal but then any further data will continue to be received re using the original buffer data3 Hence this function does not need to be repeadedly called to continue reception Page 4 223 RENESAS RX210 Group Program example PDL functions include r pdl_sci h 4 Library Reference RPDL device specific definitions include r pdl definitions h volatile uint8 t SCIlReceiveBuffer 10 SCI channel 1 receive data handler void SCI1RxFunc void SCI channel 1 error handler void SCIlErrFunc void void func void uint8 t temp Wait for 1 character to b R_SCI_Receive di 0 received on channel 0 PDL_NO_DATA amp temp 1 r PDL_NO_FUNC PDL_NO_FUNC Start the reception of 9 characters on channel 1 R_SCI Receive R20UT0708EE0211 Rev 2 11 Aug 01 2014 1 PDL_NO_DATA SCIlReceiveBuffer 9 SCIIRxFunc SCIlErrFunc RENESAS Page 4 224 RX210 Group 4 Library Reference 6 R_SCI_SPI_Transfer Synopsis Prototype Description 1 2 R20UT0708EE0211 Rev 2 11 Aug 01 2014 Perform an SPI transfer on an SCI channel bool R_SCI_SPI_Transfer uint8_tdatal Channel selection uint16_t data2 Channel configuration uint16_t data3 Number of bytes to transfer uint8_t data4 Data transmit buffer void func1 Callback function Tra
132. at least 1 5 PCLKD cycles This function brings the converter unit out of the power down state Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed e Function R_CGC_Set must be called with the current clock source selected before using this function Allow ius to elapse from the completion of this function to the start of the first conversion When the internal reference voltage is to be converted the disconnection detection assist function is not available Diagnostic mode can not be selected if the internal reference voltage is selected For more details of trigger sources please refer to the RX210 hardware manual Only select the TPU as a trigger if the device has a TPU Only device packages with 144 pins or more incorporate a TPU e Make sure sampling time calculated or specified for channel 0 and self diagnosis are the same Page 4 275 2tENESAS RX210 Group 4 Library Reference Program example RPDL definitions include r pdl_ ade 12 h RPDL device specific definitions include r pdl definitions h ADC callback function void ADCIntFunc void void func void Set up the ADC in single mode R_ADC_ 12 CreateUnit L_ADC_12 SCAN SINGLE L ADC 12 GP_TRIGGER_MTU_TRGOAN L NO DATA r D D D DL NO DATA D D D L NO DATA NO
133. be specified use to separate each value Pin selection Select the pin that will be assigned to the single port PDL_ELC_PIN_PORT_B_0 or PDL_ELC_PIN_PORT_B_1 or PDL_ELC_PIN_PORT_B_2or PDL_ELC_PIN_PORT_B_3or PDL_ELC_PIN_PORT_B _4or PDL_ELC_PIN_PORT_B_5or PDL_ELC_PIN_PORT_B _6or PDL_ELC_PIN_PORT_B_7 or PDL_ELC_PIN_PORT_E O or PDL_ELC_PIN_PORT_E 1or PDL_ELC_PIN_PORT_E_2or PDL_ELC_PIN_PORT_E_3 or PDL_ELC_PIN_PORT_E_4 or PDL_ELC_PIN_PORT_E_5or PDL_ELC_PIN_PORT_E_6or PDL_ELC PIN_PORT_E 7 Single port control PDL_ELC_PIN_OUTPUT_0 or PDL_ELC_PIN_OUTPUT_1 or PDL_ELC_PIN_OUTPUT_TOGGLE or PDL_ELC_PIN_EVENT_RISING_EDGE or PDL_ELC_PIN_EVENT_FALLING_EDGE or PDL_ELC PIN_EVENT_ANY_EDGE Select the single port operation If the pin is being used as an output pin then the output can be configured If the pin is being used as an input pin the edge that will cause an event can be configured ENESAS Page 4 119 RX210 Group Description 6 6 Return value Category Reference Remarks R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference Operation data1 PDL_ELC_SOFTWARE_EVENT data2 Not used Specify PDL_NO_DATA data3 Not used Specify PDL_NO_DATA Operation data1 PDL_ELC_TRIGGER data2 e DTC Trigger setup If multiple selections are required use to
134. byte PDL NO DATA i Select IIC mode at 100kHz 300ns rise time 200ns fall time R_IIC_ Create IIC CHANNEL PDL IIC MODE IIC PDL IIC INT PCLK DIV 8 0 0 0 0 100E3 300 lt lt 16 200 y Enable the DTC R_DTC Control PDL DTC_START PDL NO PTR PDL NO PTR PDL NO PTR PDL NO DATA PDL NO DATA Write the data into the EEPROM write eeprom data Prepare the next data to write to the EEPROM R_DTC_Control PDL DTC UPDATE SOURCE PDL DTC UPDATE COUNT dtc_iicl tx transfer data eeprom data array 2 PDL_NO_PTR ARRAY 2 SIZE PDL NO DATA R20UT0708EE0211 Rev 2 11 Page 5 84 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples Write the data into the EEPROM write eeprom data Clear the data storage area for i 0 i lt 20 i data_storage i 0x00 Reset the EEPROM sub address to 0 using polling R_IIC_MasterSend IIC CHANNEL PDL_11C_STOP_DISABLE EEPROM_ADDRESS eeprom data array 1 1 PDL_NO_FUNC 0 i Read data from the EEPROM using the DTC read_eeprom data Prepare to read the next data R_DTC_Control PDL DTC UPDATE DESTINATION PDL DTC UPDATE COUNT dtc_iicl rx transfer data PDL NO PTR amp data_storage ARRAY 1 SIZE 1 ARRAY 2 SIZE 2 Array size written sub address byte last byte PDL NO DATA Read data from the EEPROM using t
135. callback function and priority setting of alarm and periodic interrupt at warm start up R20UTO708EE0211 Rev 2 11 Page 2 20 Aug 01 2014 2tENESAS RX210 Group 2 Driver 2 21 Watchdog Timer Driver The driver functions support the use of the watchdog timer providing the following operations 1 Configuring the timer for use including Clock selection Time out period Window position Reset or NMI Interrupt selection when timer overflows 2 Control of the timer including e Counter refresh to prevent timeout 3 Reading the timer status including counter value R20UT0708EE0211 Rev 2 11 Page 2 21 Aug 01 2014 RENESAS RX210 Group 2 Driver 2 22 Independent Watchdog Timer Driver The driver functions support the use of the independent watchdog timer providing the following operations 1 Configuring the timer for use 2 Refreshing the timer to prevent the reset operation 3 Reading the timer status and counter register R20UT0708EE0211 Rev 2 11 Page 2 22 Aug 01 2014 RENESAS RX210 Group 2 Driver 2 23 Serial Communication Interface Driver The driver functions support the use of the serial communication SCI channels providing the following operations 1 2 9 Selection of the SCI pins for use Configuration for use including Automatic baud rate clock calculations Automatic interrupt control Automatic I O pin configuration Supporting the following modes Asynchronous
136. can be processed until a callback function has completed e This function unless configured not to will by default automatically start a transfer by generating a Start condition and finish with a Stop condition However if using DMAC or DTC the Stop condition will not be generated automatically so use the R_SCI_IIC_ReadLastByte or R_SCI_Control function to manually generate a stop The last byte of a master read will automatically be NACK d However if using DMAC or DTC this will not happen If a NACK is required then use the DMAC DTC to read all the data except for the last byte and then use function R_SCI_IIC_ReadLastByte to read the last byte Ifa callback function is specified and the interrupt priority level is zero this function will return false PDL functions tinclude r pdl _sci h RPDL device specific definitions tinclude r _pdl definitions h define CHANNEL SCI_1IC 9 define SLAVE ADDRESS OxA0 Buffer for IIC data uint8 t IIC Buffer 10 void func void Wait while read 10 bytes R_SCI_ TIC Read CHANNEL SCI_IIC PDL_NO_DATA SLAVE_ADDRESS 10 IIC Buffer PDL_NO_FUNC Page 4 231 RENESAS RX210 Group 4 Library Reference 9 R_SCI_IIC_ReadLastByte Synopsis Prototype Description Read the last byte of an IIC read transfer bool R_SCI_IIC_ReadLastByte uint8_tdata1 Channel s
137. configuring and controlling the timer 21 Serial Communication Interface These driver functions are used to configure the serial channels and manage the transmission and or reception of data across them 22 C Bus Interface These driver functions are used for controlling the I C bus channels 23 Serial Peripheral Interface These driver functions are used for controlling the SPI channels 24 CRC calculator These driver functions are used for controlling the calculator 25 12 bit Analog to Digital Converter These driver functions are used for configuring the 12 bit ADC units controlling the units and reading the conversion results 26 10 bit Digital to Analog converter These driver functions are used for configuring the DAC module and setting the output voltages 27 Temperature sensor These driver functions are used for configuring the Temperature sensor module 28 Comparator A These driver functions are used for configuring the Comparator A module 29 Comparator B These driver functions are used for configuring the Comparator B module 30 Data Operation Circuit These driver functions are used for configuring the Data Operation Circuit module 31 Timer Pulse Unit These driver functions are used for configuring and controlling the 16 bit Timer Pulse R20UT0708EE0211 Rev 2 11 Page 2 2 Aug 01 2014 RENESAS RX210 Group 2 Driver 2 3 Clock Generation Circuit Driver The driver functions sup
138. contents PDL_INTC_AND or PDL_INTC_OR or Select between AND amp OR or Exclusive OR PDL_INTC_XOR data3 The value to be used by the logical operation Return value True if the parameter is within range otherwise false Category Interrupt control Reference None Remarks e This function uses an interrupt routine to modify the IPL bits If the user has disabled interrupts cleared the bit in the PSW register in their own code this function will lock up For register select one of the registers listed in the tables starting on page 4 26 Program example RPDL definitions include r pdl_intc h RPDL device specific definitions tinclude r pdl_definitions h void func void Set bits 6 and 4 in IERO9 to 1 R_INTC_Modify PDL INTC REG IEROQ PDL INTC OR 0x50 R20UT0708EE0211 Rev 2 11 Page 4 32 Aug 01 2014 RENESAS RX210 Group 4 2 3 I O Port 4 Library Reference 1 0 Port functions may operate on a complete port or on individual port pins The available definitions are listed below I O port definitions PDL_IO PORT_0 Port PO PDL_IO PORTA PortPA PDL_IO PORT 1 Port P1 PDL_IO PORT B PortPB PDL_IO PORT 2 Port P2 PDL_IO PORT C PortPC PDL_IO PORT 3 Port P3 PDL_IO PORT D PortPD PDL_IO POR
139. count limit for the measured clock where the maximum value is 65535 func1 The function to be called if a frequency error is detected Specify PDL_NO_FUNC if not required data6 The frequency error interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func1 func2 The function to be called when the measurement has ended Specify PDL_NO_FUNC if not required data7 The measurement complete interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func2 func3 The function to be called if the measurement counter overflows Specify PDL_NO_FUNC if not required data8 The counter overflow interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func3 True if all parameters are valid and exclusive and the selected clocks have been set otherwise false Clock frequency accuracy measurement circuit R_CGC Set RENESAS Padeda RX210 Group 4 Library Reference Remarks Program example R20UT0708EE0211 Rev 2 11 Aug 01 2014 If the external input CACREF pin is selected the Multifunction Pin Control registers are modified to enable the selected pin Before u
140. da 4 225 TD ORV SCIENCE We a eas a Net ene hes A E E E E 4 228 Bye RS CHIC Read ie thos cate iene Nak ta tea ce cite le ia 4 230 9 R_SCI_IIC_ReadLastByte a ae ae a aea aaae raa TAa a a r A aaa a naa AEn ea a aaea e a eaaa FE 4 232 10 IR SCL Control main a add A A a ee eee 4 233 11 RSC GetStatU Ss a ieee eves A ees edhe dee ee 4 235 4 2 22 PC BusiInt rfacS ini naaa a aaa a td 4 237 1 RAE E E E E A E A A E 4 237 2 ROIC Creates a cad A aa Ta eaa eed dia 4 238 3 RIC Destroy noscu neei ie CA ad Aaa 4 243 4 PORENGES o M A A A ed 4 244 5 RIC ESC CA 4 246 6 MIC ESC TERCERA 4 248 7 RIC SlaveMonitor sii A A ed 4 249 8 RiAllC SlaveSend cnica A a in ad aed A da 4 251 9 ROCCA Oli Hee cide eval E sa tee tel vee da ro Me dale as dl Sat o eg 4 252 10 RICA GEtStatus a a a ariba 4 253 4 2 23 Serial Peripheral Interface oooononniocccnnnnnnnnonoccccconnnnnnnnnononnnnnnnnnnnnnnnnnnnnnn nano nn nn cnn rn nnnnnnnnnnnnn 4 255 A eee ee es it eel ee ee i eel 4 255 2 Re SPI Create iii nets nent ni nee ee ee a 4 256 3 JROSPL_DeStrOy vto A a sendin A 4 259 4 Re SPI Command vic neste einai Lee eee a a 4 260 5 Ro SPI Transtetic c sa cence sean ie nde se ne eee eee 4 262 6 CR SPI Control fic ain eee ae RL eae eee ee ice a 4 264 Te Re SPD GetStatus aise iii a A seed nid seein eee ene nian 4 266 42 24 CRG calculator nic cai aie een i a ier ee ene HL eee ete ee ae ere 4 267 1 R CRC Create vine E nee eel 4 267 2 RCR Dest
141. data2 uint16_t data3 uint16_t data4 uint16_t data5 uint16_t data6 uint16_t data7 Channel selection 11 A pointer to the data storage location 11 A pointer to the data storage location 11 A pointer to the data storage location 11 A pointer to the data storage location 11 A pointer to the data storage location 11 A pointer to the data storage location Read any of the timer s counter compare or status flag registers data1 The channel number n where n 0 to 5 data2 The status flags shall be stored in the format below 4 Library Reference The input capture compare match flags A to D will be set to1 if the condition has been detected Specify PDL_NO_PTR if the flags are not to be read For n Oor3 b7 b6 b5 b4 b3 b2 b1 bO Overflow Input capture compare match 0 0 detection detection 0 V D C B A For n 1 2 40r5 b7 b6 b5 b4 b3 b2 b1 bO Underflow Overflow Input capture compare match Co ntdirecti n 0 detection detection detection 0 Counter counts down Al NE 0 0 B A 1 Counter counts up data3 A pointer to where the counter value shall be stored Specify PDL_NO_PTR if it is not required data4 Where the general register A value shall be stored Specify PDL_NO_PTR if it is not required data5 Where the general register B value shall be stored Specify PDL_NO_PTR if it is not required data6 Where the gene
142. definitions include r pdl iic h RPDL device specific definitions include r pdl definitions h void func void Shutdown IIC channel 0 R_IIC Destroy 0 R20UT0708EE0211 Rev 2 11 Page 4 243 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 4 R_IIC_MasterSend Synopsis Prototype Description 1 2 R20UT0708EE0211 Rev 2 11 Aug 01 2014 Write data to a slave device bool R_IIC_MasterSend uint8_t data1 Channel selection uint16_t data2 Channel configuration uint16_t data3 Slave address uint8_t data4 Data start address uint16_t data5 Data count void func Callback function uint8_t data6 Interrupt priority level Transmit data on the specified channel data1 Select channel IICn where n 0 data2 Configure the channel If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Start Repeated Start condition control PDL_IIC_START_ENABLE or Choose whether or not to issue a Start or Repeated Start PDL_IIC_START_DISABLE condition at the beginning of the transfer e Stop condition control PDL_IIC_STOP_ENABLE or Choose whether or not to issue a Stop condition at the end PDL_IIC_STOP_DISABLE of the transfer Slave address size override Specify this option
143. disable the DTC trigger Some peripheral channels and port pins are not available on some device packages Please check the hardware manual The event signals selected by PDL_ELC_LINK_EVENT_SCI5_RECEIVE_DATA_FULL and PDL_ELC_LINK_EVENT_SCI5_TRANSMIT_DATA_EMPTY depend on the SCI5 operation mode Please refer to section 28 12 in the RX210 hardware manual EventPDL_ELC_LINK_EVENT_SCI5_RECEIVE_DATA_FULL cannot be used if SCI5 is configured for IIC Mode This function will return false if this condition is detected Event PDL_ELC_LINK_EVENT_SPI_TRANSMIT_END is not generated by the SPI module if it is in slave mode using clock synchronous operation This function will return false if this condition is detected e Ifa timer event link is no longer required use PDL_ELC_TIMER_EVENT_DISABLE to disable the event During software standby mode the voltage detection even triggers can be generated but they will not cause a trigger until software standby mode is exited During deep software standby mode voltage detection event triggers cannot be generated To enable the voltage detection event triggers enable the LVD first then enable the LVD event link function at the ELC To disable this function disable the LVD event link function at the ELC first then disable the LVD Event PDL_ELC_LINK_EVENT_SPI_ERROR cannot be used if multi master configuration SPI operation and master mode are selected for the RSPI
144. enabled using R_BSC_Control Do not set the PLL if in low speed operating mode 1 or 2 If using MCU version B then the PLL power will be enabled when setting the PLL Note This may automatically perform a temporary change to Middle Speed Operating Mode 1A while this is performed If setting the ICLK gt 32MHz then High speed operating mode must be set first See R_LPC_Control function If using MCU version A the main clock can not be selected as the system clock The oscillation accuracy of the sub clock is affected when an on chip debugger emulator is connected and the sub clock drive setting is low Make sure PCLKB clock frequency 2 RTC count source clock frequency When RTC is not to be used call R_CGC_Control with option PDL_CGC_RTC_NOT_USE after calling this function to configure the RTC count source Sub clock oscillator is not available for 48 pin package RENESAS ca RX210 Group Program example RPDL definitions include r pdl_cgc h RPDL device specific 4 Library Reference definitions include r pdl definitions h void func void Configure sub clock operation using a 32 768 KHz crystal ICLK 32 768 KHz PCLKD 32 768 KHz PCLKB 32 768 KHz FCLK BCLK not used BCLK pin not used R_ CGC Set PDL_CGC_CLK_SUB_ CLOCK PDL CGC BCLK DISABLE PDL CGC SUB CLOCK CL LOW 32768 32768 32768 32768 PDL NO DATA
145. false Monitor the channel Any data received will be stored in the receive buffer R_IIC SlaveMonitor 0 PDL NO DATA Rx Buffer 4 slave_event_handler void slave_event_handler void R20UT0708EE0211 Rev 2 11 Page 5 88 Aug 01 2014 RENESAS RX210 Group uint32 t status flags 0 uintl6 t tx count 0 uintl6 t rx count 0 bool bStartMonitor true Read the channel status R_IIC_GetStatus 0 status flags tx count rx count y Has the master just completed a write if rx count 0 StoreData rx count Start monitoring again bStartMonitor true Has the master just completed a read else if tx_count 0 Increment the current index by the amount the master read data_storage index tx_count Start monitoring again bStartMonitor true Is the master starting a read Check this by seeing if in transmit mode else if 0 status flags amp BIT 6 Send data to master based on current address R_IIC_SlaveSend 0 amp data_storage data_storage index uint16_t STORAGE SIZE data storage index i 5 Usage Examples Don t start monitoring again until the R_IIC_SlaveSend completes bStartMonitor false true bStartMonitor Continue monitoring R_IIC SlaveMonitor 0 PDL NO DATA Rx_Buffer RX_BUFFER_SIZE slave_event_handler 7 The master has sent us dat
146. for the TMR functions may be omitted tinclude r pdl_tmr h RPDL device specific definitions tinclude r pdl_definitions h void func void Configure the applicable TMR pins R TMR Set 0 PDL TMR TMRO TMOO PB3 PDL TMR TMRO TMCIO PB1 PDL TMR TMRO TMRIO PA4 R20UT0708EE0211 Rev 2 11 Page 4 156 Aug 01 2014 RENESAS RX210 Group 2 R_TMR_CreateChannel Synopsis Prototype Description 1 2 R20UT0708EE0211 Rev 2 11 Aug 01 2014 Configure a timer TMR channel bool R_TMR_CreateChannel uint8_t data1 uint32_t data2 uint8_t data3 uint8_t data4 uint8_t data5 uint8_t data6 void func1 void func2 void func3 uint8_t data7 II Channel selection II Configuration selection II Configuration selection Register value Register value Register value II Callback function Callback function Callback function Interrupt priority level Set up an 8 bit timer TMR channel data1 The channel number n where n 0 1 2 or 3 data2 Configure the channel If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Counter clock source selection 4 Library Reference PDL_TMR_CLK_OFF or The clock input is disabled PDL_TMR_CLK_EXT_RISING or PDL_TMR_CLK_EXT_FALLING or
147. full or 24 bit short address mode data2 The first address of the area of on chip RAM where the DTC vector table shall be stored The address must be on a 4 kB boundary i e having the format xxxxx000h True if all parameters are valid and exclusive otherwise false Data Transfer Controller R_DTC_Create Remarks Program example e Before calling R_DTC_Create call this function RPDL definitions tinclude r pdl_dtc h RPDL device specific definitions tinclude r pdl definitions h Reserve an area for the DTC vector table pragma address dtc vector table 0x00001000 uint32 t dtc vector table 256 void func void Configure the controller R_DTC Set PDL_DTC_ADDRESS_ SHORT dtc_vector table i R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 101 RENESAS RX210 Group 2 R_DTC_Create Synopsis Prototype Description 1 3 R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference Configure the Data Transfer Controller for a transfer bool R_DTC_Create uint32_t data1 uint32_t data2 void data3 void data4 uint16_t data5 uint8_t data6 Configuration selection Transfer data start address Source start address Destination start address Transfer count Block size Configure DTC activation for one trigger source data1 Configuration
148. function is not required for the source address data10 The destination address extended repeat value The value can be any power of 2 from 2 to 27 Specify PDL_NO_DATA if the extended repeat function is not required for the destination address func The function to be called when a DMA transfer completes Specify PDL_NO_FUNC if not required data11 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid and exclusive otherwise false DMA controller None e If another peripheral will be used to trigger a DMA transfer call this function before calling the Create function for the peripheral Some peripheral channels are not available on some device packages Please check the hardware manual Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed RENESAS di RX210 Group 4 Library Reference Program example RPDL definitions include r pdl dmac h RPDL device specific definitions include r pdl definitions h void func void Configure DMA channel 2 R_DMAC Create 2 PDL DMAC NORMAL PDL DMAC SOURCE ADDRESS PLUS PDL DMAC DESTINATION ADDRESS PLUS PDL DMAC SIZE 8 PDL DMAC_TRIGGER_IRQO voi
149. function is specified and the interrupt priority level is zero this function will return false R20UT0708EE0211 Rev 2 11 Page 4 220 Aug 01 2014 RENESAS RX210 Group 4 Library Reference Program example RPDL definitions include r pdl_sci h RPDL device specific definitions include r pdl definitions h void func void uint8 t data_store 100 Send a string on channel 1 R_SCI_ Send 1 PDL NO DATA Renesas RX 0 PDL_NO_FUNC Send 50 bytes of binary data on channel 1 R_SCI_ Send 1 PDL_NO_DATA data_store 50 PDL_NO_FUNC Send the ID byte 0x0A shifted into the upper byte R_SCI_ Send 2 PDL SCI MP ID CYCLE 0x0A00 PDL NO PTR 0 PDL NO_ FUNC R20UT0708EE0211 Rev 2 11 Page 4 221 Aug 01 2014 RENESAS RX210 Group 5 R_SCI_Receive Synopsis Prototype Description Return value R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference Receive data on a SCI channel bool R_SCI_Receive uint8_tdata1 Channel selection uint16_t data2 Channel configuration and Station ID of receiving device uint8_t data3 Data start address uint16_t data4 Receive threshold void func1 Callback function void func2 Callback function Enable SCI reception and acquire any incoming data data1 Select channel SCln where n
150. if 10 bit address mode is to be PDL_IIC_10 BIT SLAVE_ADDRESS used instead of 7 bit mode when the slave address is lt FFh e DMAC DTC trigger control PDL_IIC_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_IIC_DMAC_TRIGGER_ENABLE or DMAC or DTC when a data byte is PDL_IIC_DTC_ TRIGGER _ ENABLE transmitted data3 The address of the slave device Ignored if the Start condition is disabled data4 The start address of the data to be sent If the DMAC or DTC shall be used to transfer the data specify PDL_NO_PTR data5 The number of bytes to be sent If the DMAC or DTC shall be used to transfer the data specify PDL_NO_DATA func Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Transfer method Parameter PDL_NO_FUNC This function will continue until the required number of Polling bytes has been sent or another event occurs Interrupts The function to be called when bus activity has stopped DMAC Either the function to be called when each byte is sent or PDL_NO_FUNC if the callback function specified in R_DMAC_Create will be used The function to be called at the interval specified in R_DTC_Create This DTC function will in addition also be called when the last byte has been transmitted Page 4 244 ENESAS RX210 Group 4 Library Reference Description 2 2 R
151. iic r pdl cge r pdl_cmt h ah h include r pdl _dtc h RPDL device specific definitions tinclude r pdl definitions h SetClocks void write eeprom data void static void read eeprom data void void iic tx end handler void void iic rx end handler void static void static void ER 0x00 ER 0x00 EPROM_M define define define EPROM_M EPROM M EPROM A ORY_ADDRESS_UPP ORY _ ADDRESS LOW DRESS 0x00A0 EMORY ADDRESS UPP define IIC CHANNEL 0 The Tx callback must process the following states typedef enum IIC TX STATE pal IIC TX STATI IIC TX STAT IIC TX STAT IIC TX STAT _ FINISHED WAIT DTC WAIT LAST BYTI El El Ed Ti ceo d static IIC_TX STATE g TIC Tx 5 tate IIC_TX STATE FINISH volatile uint8 t g_IIC_Rx busy volatile uint8_t data storage 20 Reserve an area for the DTC vector table 0x00002000 pragma address dtc_vector table uint32 t dte vector table 256 Reserve 16 bytes full address mode for the transfer data areas uint32 t dtc_iicl tx transfer data 4 uint32 t dtc_iicl rx transfer data 4 void main void define ARRAY 1 SIZE 6 5 Data 1 address define ARRAY 2 SIZE 11 10 Data 1 address const uint8 t eeprom _data_array 1 ARRAY 1 SIZE EEPROM MEMORY ADDRESS LOWER
152. instructions These instructions are issued by the API interrupt handlers so there should be no need for the user s code to use these instructions 2 Use the wait intrinsic function with caution This instruction is used by some API functions as part of power management so there should be no need for the user s code to use this instruction More information on the processor modes can be found in 1 4 of the RX Family software manual 6 2 Interrupts and DSP instructions The accumulator ACC register is modified by the following instructions i DSP MACHI MACLO MULHI MULLO MVTACHI MVTACLO and RACW ii Multiply and multiply and accumulate EMUL EMULU FMUL MUL and RMPA The accumulator ACC register is not pushed onto the stack by the API interrupt handlers If DSP instructions are being utilised in the users code callback functions which are called by the API interrupt handlers should either a Avoid using instructions which modify the ACC register b Take a copy of the ACC register and restore it before exiting the callback function R20UT0708EE0211 Rev 2 11 Page 6 1 Aug 01 2014 RENESAS RX210 Group Revision History Revision History RX210 Group User s Manual Description Date Summary Jan 30 2012 First issue Removed the statement regarding testing Updated the batch file Copy Utility usage notes including screen shots R_CGC_Control Updated the remark for avoiding changing the HOCO
153. of RWP operation R20UT0708EE0211 Rev 2 11 Page 5 111 Aug 01 2014 RENESAS RX210 Group 5 30 MCU Operation This shows an example of MCU usage It detects if a Cold start has occurred Peripheral driver function prototypes include r pdl mcu h PDL device specific definitions include r pdl definitions h void main void R20UT0708EE0211 Rev 2 11 Aug 01 2014 uint1l6 t mode status uintl6_t reset status Read the MCU status registers R_MCU_GetStatus amp mode_ status amp reset status PDL NO PTR PDL NO PTR Cold start if reset_ status amp BIT 8 0 Set the warm start indicator R_MCU Control PDL MCU WARM START 7 Reset the ey R_MCU Control PDL _MCU_RESET START i Figure 5 61 Example of MCU operation 5 Usage Examples Page 5 112 2tENESAS RX210 Group 6 RX specific notes 6 RX specific notes 6 1 Interrupts and processor mode The RX CPU has two processor modes supervisor and user The API driver functions will be executed by the CPU in user mode However any callback functions which are called by the API interrupt handlers will be executed by the CPU in supervisor mode This means that the privileged CPU instructions RTFI RTE and WAIT can be executed by the callback function and any function that is called by the callback function The user must 1 Avoid using the RTFI and RTE
154. or Exclude or include pin MTIOC n 1 B in the TGRB input capture conditions for channel n RENESAS Page 4 129 RX210 Group Description 6 9 R20UT0708EE0211 Rev 2 11 Aug 01 2014 TGR_C_D_ operation Configure the operation for general registers TGRC and TGRD Valid for n 0 3 and 4 If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Input capture output compare control for 4 Library Reference register TGRC PDL_MTU2_C_OC_DISABLED or PDL_MTU2_C_OC_LOW or PDL_MTU2_C_OC_LOW_CM_HIGH or PDL_MTU2_C_OC_LOW_CML_INV or PDL_MTU2_C_OC_HIGH_CM_LOW or PDL_MTU2_C_OC_HIGH or PDL_MTU2_C_OC_HIGH_CM_INV or MTIOCnC output disabled MTIOCnC output low MTIOCnC initial output low goes high at compare match MTIOCnC initial output low toggles at compare match MTlOCnC initial output high goes low at compare match MTIOCnC output high MTIOCnC initial output high toggles at compare match PDL_MTU2_C_IC_RISING_EDGE or PDL_MTU2_C_IC_FALLING EDGE or PDL_MTU2_C_IC BOTH EDGES or Input capture at MTIOCnC rising edge Input capture at MTIOCnC falling edge Input capture at MTIOCnC both edges PDL_MTU2_C_IC_COUNT Input capture at channel n 1 up count or down count Valid only for n 0 Input capture output compare control for register TGRD
155. or Input capture or compare match on MTU channel n n 0 to 4 Receive buffer full on SCI unit n n 0 to 12 R20UT0708EE0211 Rev 2 11 Page 4 92 Aug 01 2014 RENESAS RX210 Group Description 3 3 Return value Category Reference Remarks R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference PDL_DMAC_TRIGGER_SCI5 TX or PDL_DMAC_ TRIGGER SCI6_TX or PDL_DMAC TRIGGER SCI7_TXor PDL_DMAC_TRIGGER_SCI8_TX or PDL_DMAC_TRIGGER_SCI9_TX or PDL_DMAC_TRIGGER_SCH10_TX or PDL_DMAC_TRIGGER_SCIH11_TX or PDL_DMAC_TRIGGER_SCI12_TX or PDL_DMAC_TRIGGER_IICO_RX or Receive buffer full on I2 C channel 0 PDL_DMAC_TRIGGER_IICO_TX Transmit buffer empty on C channel 0 data4 The source start address data5 The destination start address data6 The number of transfers to take place For normal mode valid between 0 and 65535 0 free running mode For repeat and block mode valid between 0 and 1023 0 1024 transfers data7 The repeat or block size for each transfer For repeat and block mode valid between 0 and 1023 0 1024 units Ignored in normal mode data8 The address offset value The range is from 16 777 215 to 16 777 216 This value is ignored if the offset function is not selected data9 The source address extended repeat value The value can be any power of 2 from 2 to 2 Specify PDL_NO_DATA if the extended repeat
156. or a callback function name depending on the required transfer method Transfer Parameter method PDL_NO_FUNC This function will continue until the required number of bytes Pollin 9 has been transferred or an error occurs Interrupts The function to be called when the transfer has completed or an error detected Either the function to be called when each byte is transferred or PDL_NO_FUNC Return value Category Reference DMAG if the callback function specified in R_ DMAC_Create will be used DTC The function to be called at the interval specified in R_DTC_Create In Polling Mode True if all parameters are valid and the operation completed OK false if a parameter was out of range or an error was detected In Non Polling mode True if all parameters are valid false if a parameter was out of range SCI R_DMAC_Create R_DTC_Create R_SCI_Control Remarks Program example R20UT0708EE0211 Rev 2 11 Aug 01 2014 The maximum number of characters to be transmitted is 65535 e Wait until a transmission on the same channel is complete before calling this function e Callback functions are executed by the interrupt processing function This means that no other interrupt can be processed until a callback function has completed This function unless configured not to will by default automatically start a transfer by generating a Start c
157. parameters are valid and exclusive otherwise false Multi function Timer Pulse Unit R_MTU2_Set R_MTU2_ControlChannel R_MTU2_ControlUnit R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 133 RENESAS RX210 Group 4 Library Reference Remarks Program example R20UT0708EE0211 Rev 2 11 Aug 01 2014 i i VO If an external clock input pin MTCLKx or I O pin MTIOCnx is made active this function will configure that pin for input or output and disable other functions on that pin The alternative pins are assigned using function R_MTU2_Set Either R_MTU2_ControlChannel or R_MTU2_ControlUnit must be used to start the timers If a callback function is specified this function will enable the relevant CPU interrupt Please see the notes on callback function usage in 86 Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed If the channel is configured for phase counting mode the counter clock source setting is ignored If buffer operation is selected for registers TGRA and TGRC input capture output compare is not valid for register TGRC If buffer operation is selected for registers TGRB and TGRD input capture output compare is not valid for register TGRD If synchronous mode is required at least two channels must be enabled for synchronous operation
158. pin POEn POE3 POE2 POE1 POEO 0 0 No request 1 Requested True Port Output Enable R_POE_Control e Use R_POE_Control to clear the flags RPDL definitions include r pdl poe h RPDL device specific definitions tinclude r pdl_definitions h void func void uintl6 t StatusFlags Read the POE status R_POE GetStatus amp StatusFlags i R20UT0708EE0211 Rev 2 11 Page 4 154 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 4 2 16 8 bit Timer 1 R_TMR_Set Synopsis Configure the optional TMR pins Prototype bool R_TMR_Set uint8_t data1 Channel selection uint32_t data2 Configuration Description Set up the global TMR options data1 The channel number n where n 0 1 2 or 3 data2 Configure the TMR input and output pins for the channel Use to separate each selection e Valid when n 0 PDL_TMR_TMRO_TMOO_P22 or PDL_TMR_TMRO_TMOO_PB3 or Select the pins for TMOO PDL_TMR_TMRO_TMOO_PH1 PDL_TMR_TMRO_TMCIO_P01 or PDL_TMR_TMRO_TMCIO_P21 or PDL_TMR_TMRO_TMCIO_PB1 or PDL_TMR_TMRO_TMCIO_PH3 PDL_TMR_TMRO_TMRIO_P0O or PDL_TMR_TMRO_TMRIO_P20 or PDL_TMR_TMRO_TMRIO_PA4 or PDL_TMR_TMRO_TMRIO_PH2 Select the pins for TMCIO Select the pins for TMRIO Valid when n 1 PDL_TMR_TMR1_TMO1_P17 or PDL_TMR_TMR1_TMO1_P26 PDL_TMR_TMR1_TMCI1_ P02 or PD
159. power state R_MCU_OFS Updated the 2 85V detection level to 2 80V R_LVD_Create Modified and moved the remark for avoiding detection voltage re use Feb 28 2012 R_POE_Create Updated the Program Example R_CMT_CreateOneShot Updated the comment in DMAC DTC trigger control R_RTC_Create Corrected typing errors in the Time Capture Noise Filter Control definitions R_CPB_Create Renamed data4 to data3 Updated the CMT usage example 1 15 Initialisation Added note about setting RTC if not using it 2 33 Added TPU module 4 798 74 R_CGC_Set R_CGC_Control and R_LPC_Control Added remarks regarding PLL power control if using MCU version B 4 78 74 R_CGC_Set and R_LPC_Control Added remarks saying high speed mode must be used if ICLK gt 32MHz 4 7 628 71 R CGC_Set R_CAC_ Create and R_LPC_Create Added remarks regarding MCU version A main clock restriction 4 9 R_CGC_Control Added remark Restriction when HOCO power can be changed R_CGC_Control Added remark Do not use if ROM Program Erase modes set or if a power transition is in progress R_INTC_SetExtInterrupt Added PDL_INTC_IRQ4_PORT_F_5 R_INTC_CreateFastInterrupt Added vectors for TPU and extra SCI channels R_INTC_Read Write Modify Added TPU and extra SCI and IER options Apr 29 2013 10_Port Added port and pin definitions for 144 pin packages R_IO_PORT_ReadControl correct typo error b7 b1 to b7 bO R_IO_PORT_ModifyControl correct typo error b7 b
160. processing is allocated to only one interrupt handler Open the file r_pdl_user_definitions h and edit the definition FAST_INTC_VECTOR to give it the same value as the interrupt vector used in parameter data1 For example define FAST_INTC_VECTOR PDL_INTC_VECTOR_IRQ2 This will direct the compiler to generate the instructions required for a fast interrupt vector e This function uses an interrupt routine to modify the FINTV register If the user has disabled interrupts set the I bit in the PSW register to 0 in their own code this function will lock up RPDL definitions include r pdl intc h RPDL device specific definitions include r pdl definitions h void func void Assign the fast interrupt to the handler for pin IRQ3 R_INTC_CreateFastInterrupt PDL_INTC_VECTOR_IRQ3 y Remember to edit r pdl user definitions h see remark 2 RENES Page 4 21 RX210 Group 4 Library Reference 5 R_INTC_CreateExceptionHandlers Synopsis Prototype Description Return value Category Reference Remarks Program example Assign handlers for the fixed vector interrupts bool R_INTC_CreateExceptionHandlers void func1 Callback function void func2 II Callback function Register the user functions to be called by the fixed vector and software interrupts func1 The function to be called
161. register R_MPC_Modify Modify a PFC register R_MCU_Control Control the operation of the MCU MCU operation R_MCU_GetStatus Read the MCU status R_MCU_OFS Configure the device start up operation Voltage Detection Circuit R_LVD_Create Configure the voltage detection circuit R_LVD_Control Control the voltage detection circuit R_LVD_GetStatus Check the status of the voltage detection module Clock Frequency R_CAC Create Configure the clock accuracy circuit Accuracy R_CAC Destroy Stop the clock accuracy circuit Measurement R_CAC_Control Control the clock accuracy circuit Circuit R_CAC_GetStatus Read the clock accuracy circuit status R_LPC_Create Configure the MCU low power conditions Low Power R_LPC_Control Select a low power consumption mode Consumption R_LPC WriteBackup Write to the Backup registers R_LPC_ReadBackup Read from the Backup registers R_LPC_GetStatus Read the status flags Register Write R_RWP_Control Control register write protection Protection R_RWP_GetStatus Get the status of the register protection Bus Controller R_BSC_Set Configure the internal bus operation R_BSC_Create Configure the external bus controller R_BSC_CreateArea Configure an external bus area R_BSC_Destroy Stop the Bus Controller R_BSC Control Modify the External Bus Controller operation
162. registers and will therefore be read back as zero The year returned will be in the range 0 to 99 The hundreds and thousands units are not stored After reading a capture time the event detected flag will be automatically cleared This module is not available on the 48 pin package Program example RPDL definitions tinclude r pdl_rtc h RPDL device specific definitions tinclude r pdl_definitions h uint8 t Flags uint32 t CurrentTime void func void Read the current time and flags R_RTC_Read PDL_RTC_READ CURRENT amp Flags amp CurrentTime PDL_NO PTR y R20UT0708EE0211 Rev 2 11 Page 4 197 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 5 R_RTC_CreateWarm Synopsis Prototype Description Return value Category Reference Reconfigure RTC interrupt setting at warm start up bool R_RTC_CreateWarm void func Callback function uint8_t data1 Interrupt priority level void func2 II Callback function uint8_t data2 Interrupt priority level Reconfigure RTC interrupt setting at warm start up func1 The function to be called when an alarm occurs Specify PDL_NO_FUNC if not required data1 The alarm interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is spe
163. separate each selection PDL_ELC_INTERRUPT_1_TRIGGER_DTC_ENABLE or PDL_ELC_INTERRUPT_1_TRIGGER_DTC_DISABLE Enable or disable a DTC trigger PDL_ELC_INTERRUPT_2_TRIGGER_DTC_ENABLE or from an ELC Interrupt PDL_ELC_INTERRUPT_2_TRIGGER_DTC_DISABLE data3 Not used Specify PDL_NO_DATA True if all parameters are valid and exclusive otherwise false Event Link Controller R_ELC_Create R_TMR_ControlChannel Each time this function is called a particular control operation is performed Call this function as many times as is required to complete the necessary configuration If using an event to start the 8 Bit Timer then to stop it use function R_TMR_ControlChannel with PDL_TMR_ELC_COUNT_STOP selected If another peripheral or port will be used to generate an event or to be triggered by an event then that peripheral or port must be configured accordingly before calling this function Only the following events can be selected to trigger an ELC Interrupt PDL_ELC_LINK_EVENT_INPUT_PORT_GROUP_B or PDL_ELC_LINK_EVENT_INPUT_PORT_GROUP_E or PDL_ELC_LINK_EVENT_SINGLE_INPUT_PORT_0 or PDL_ELC_LINK_EVENT_SINGLE_INPUT_PORT_1 or PDL_ELC_LINK_EVENT_SINGLE_INPUT_PORT_2 or PDL_ELC_LINK_EVENT_SINGLE_INPUT_PORT_3 or PDL_ELC_LINK_EVENT_SOFTWARE_EVENT An ELC interrupt can trigger the DTC or the DMAC but not both at the same time If triggering the DTC use PDL_ELC_TRIGGER to enable the DTC trigger If using the DMAC use PDL_ELC_TRIGGER to
164. should be put into a stable state Please refer the program in Section 5 15 2 MCU overview Change to Controlling the MCU operation and on chip ROM R_CGC_Set Delete RTC Count Source selection Revise description of the sub clock oscillator drive ability R_CGC_Set Revise description data9 sub clock stabilization times R_CGC_Set Revise remarks gt Change description Old Call this function once for each clock source that will be used New Call this function once to set the clock frequency for whether it is used as system clock or RTC count source gt Add remark When RTC is not to be used call R_CGC_Control with option PDL_CGC_RTC_NOT_USE after calling this function to configure the RTC count source Revise the Program example R_CGC_Control Revise description of RTC initialization control R_CGC_Control Revise remarks gt Delete remark RENESAS Revision History 4 RX210 Group 01 Aug 2014 Revision History Description 4 198 4 229 4 231 4 232 4 245 4 248 4 251 4 310 5 2 3 5 33 5 51 5 75 76 5 88 89 90 5 112 R20UT0708EE0211 Rev 2 11 Aug 01 2014 a If a clock source will be selected using parameter data1 first call R_CGC_Set to configure the clock source b If PDL_CGC_NOT_SUB see R_CGC_Set is selected sub clock cannot be chosen as system clock and the option PDL_CGC_RTC_NOT_USE will be forced gt Add remark a Calling R_RTC_Creat
165. successful Sub clock oscillator is not available for 48 pin package RPDL definitions include r pdl_cgc h RPDL device specific definitions include r pdl definitions h void func void uintl6 t Status flags R_CGC_GetStatus amp Status flags i R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS PEE RX210 Group 4 2 2 1 R_INTC_SetExtInterrupt Interrupt Control Unit Synopsis Prototype Description uint32_t data data Allocate the pins for signals IRQO to IRQ7 All selections are optional If multiple selections are required use to separate each selection Select the external interrupt pins bool R_INTC_SetExtinterrupt Pin selection Assign the external interrupt pins 4 Library Reference PDL_INTC_IRQO_PORT_3_0 or PDL_INTC_IRQO_PORT_D_0 or PDL_INTC_IRQO_PORT_H_1 PDL_INTC_IRQ1_PORT_3_1 or PDL_INTC_IRQ1_PORT_D_1 or PDL_INTC_IRQ1_PORT_H 2 PDL INTC IRQ2 PORT 3 20r PDL INTC IRQ2 PORT 1 2or PDL INTC IRQ2 PORT D2 PDL INTC IRQ3 PORT 3 30r PDL INTC IRQ3 PORT 1 3o0r PDL_ INTC IRQ3 PORT D 3 PDL_INTC_IRQ4_PORT_B_1 or PDL_INTC_IRQ4_PORT_1_4 or PDL_INTC_IRQ4_PORT_3_4 or PDL_INTC_IRQ4_PORT_D_4 or PDL_INTC_IRQ4 PORT F_5 PDL INTC IRQ5 PORT A_4
166. the PGA operation and A D conversion R20UT0708EE0211 Rev 2 11 Page 2 29 Aug 01 2014 RENESAS RX210 Group 2 Driver 2 30 Comparator A Driver Comparator A compares a reference input voltage and an analog input voltage The driver functions support the use of Comparator A1 and comparator A2 that share the voltage detection circuit with voltage monitor 1 and voltage monitor 2 Either comparator A1 and comparator A2 or voltage monitor 1 and voltage monitor 2 can be selected to use the voltage detection circuit Providing the following operations 1 Configuring two Comparator A including Individual Reference and ComparisonInput Select Comparison result monitor Comparison result output Interrupt or reset mode selection Reset Negation selection Non maskable or maskable interrupt Digital filter function and sample frequency Compares whether the analog input voltage has passed through the reference input voltage by Rising or falling 2 Controlling two Comparator A e Enable disable comparator A 3 Reading the status flag R20UT0708EE0211 Rev 2 11 Page 2 30 Aug 01 2014 RENESAS RX210 Group 2 Driver 2 31 Comparator B Driver The driver functions support the use of two comparator B channels providing the following operations 1 Configuring a channel for use including e Individual channel power control e Automatic interrupt control e Filter frequency selection e Disabling ch
167. the current destination address shall be stored Ignored if data1 is set to PDL_NO_PTR If this value is not required specify PDL_NO_PTR data5 Where the current transfer count shall be stored Ignored if data1 is set to PDL_NO_PTR If this value is not required specify PDL_NO_PTR data6 Where the current block size count shall be stored Ignored if data1 is set to PDL_NO_PTR If this value is not required specify PDL_NO_PTR True if all parameters are valid and exclusive otherwise false Data Transfer Controller R_DTC_Create The start address of the transfer data area is the same as that declared in R_DTC_Create Page 4 109 RENESAS RX210 Group 4 Library Reference Program example RPDL definitions include r pdl _dtc h RPDL device specific definitions include r pdl definitions h Declared in the R DTC Create example uint32 t dtc cmt0 transfer datal void func void 1 uint1l6 t StatusValue uint32 t SourceAddr Read the status and current source address for the CMTO transfer R_DTC_GetStatus dtc_cmt0 transfer data StatusValue amp SourceAddr PDL _NO PTR PDL_NO PTR PDL_NO PTR R20UT0708EE0211 Rev 2 11 Page 4 110 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 4 2 13 Event Link Controller 1 R_ELC_Create Synopsis Prototype Description Return value Category
168. the high impedance state of the MTUO outputs data2 Event flag control If multiple selections are required use to separate each selection All settings are optional Specify PDL_NO_DATA if no control is required PDL_POE_FLAG_POEO_CLEAR PDL_POE_FLAG_POE1_CLEAR PDL_POE_FLAG POE2_ CLEAR PDL_POE_FLAG_POE3_CLEAR PDL_POE_FLAG_POE8 CLEAR PDL_POE_FLAG_OSTSTF_CLEAR PDL_POE FLAG_SHORT_3 4 CLEAR Select the flags to be cleared data3 Interrupt control If multiple selections are required use to separate each selection All settings are optional Specify PDL_NO_DATA if no control is required e High impedance request response PDL_POE_IRQ HI Z 0 3 DISABLE PDL_POE_IRQ_HI Z 0 3 ENABLE Control interrupts on detection of any high impedance request on pins POEO to POE3 PDL POE _IRQ_HI Z 8 DISABLE PDL_POE_IRQ_HI_Z 8 ENABLE Control interrupts on detection of a high impedance request on pin POES Output short detection response PDL_POE_IRQ SHORT 3 4 DISABLE PDL_POE_IRQ SHORT 3 4 ENABLE Control interrupts on detection of a short on any MTU channel 3 or 4 two phase output pair True if all parameters are valid and exclusive otherwise false Port Output Enable R_POE Create Remarks R20UT0708EE0211 Rev 2 11 Aug 01 2014 Call R_POE_Create before using
169. then read 2 bytes R20UT0708EE0211 Rev 2 11 Page 5 78 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 18 2 Master mode with DMAC In the following example data is written to an EEPROM in two bursts DMAC channel 3 is used to handle the data transfer The same EEPROM address locations are then read out in two bursts DMAC channel 2 is used to handle the data transfer Peripheral driver function prototypes include r pdl_iic h include r pdl_cgc h include r pdl_cmt h include r pdl dmac h RPDL device specific definitions tinclude r pdl definitions h static void write eeprom data void static void read eeprom data void void iic tx dmac end handler void void iic rx dmac end handler void define EEPROM MEMORY ADDRESS UPPER 0x00 define EEPROM MEMORY ADDRESS LOWER 0x00 define EEPROM ADDRESS 0x00A0 EEPROM MEMORY ADDRESS UPP volatile uint8 t bus_busy volatile uint8 t data_storage 20 void main void const uint8 t eeprom data array 1 EEPROM MEMORY ADDRESS LOWER 0x01 0x02 0x03 0x04 0x05 const uint8 t eeprom data array 2 EEPROM MEMORY ADDRESS LOWER 5 0x06 0x07 0x08 0x09 Ox0A Ox0B 0x0C 0x0D Ox0E 0x0F uint8 t i Initialise the system clocks NOTE The code to initialise the system clock usi
170. to be stored in register ADDISCR Valid unless PDL_ADC_12_DDA_DISABLE is selected R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS Page 4 273 RX210 Group Description 3 4 R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference data3 data4 Options for two ADC groups in group scan mode In other operating modes only data3 is valid applying to all the working ADC channels To set multiple options at the same time use to separate each value Trigger source selection Valid only if PDL_ADC_12_SYNC_TRIGGER_ENABLE is selected while PDL_ADC_12_INPUT_TS is not selected for data2 The two groups should not share the same trigger source PDL_ADC_12 GP_TRIGGER_MTU_TRGOAN or TRGA input capture compare match A from MTUO TRGB input capture compare match B from MTUO TRGA input capture compare match or MTU4 TCNT underflow trough in complementary PWM mode from MTUO to MTU4 PDL_ADC 12 GP_TRIGGER_MTU_TRGOEN or TRGE compare match from MTUO PDL_ADC 12 GP_TRIGGER_MTU_TRGOFN or _ TRGF compare match from MTUO MTU4 TADCORA and MTU4 TCNT PDL_ADC_12_GP_TRIGGER_MTU_TRG4AN or compare match interrupt skipping function 1 MTU4 TADCORB and MTU4 TCNT PDL_ADC_12_GP_TRIGGER_MTU_TRG4BN or compare match interrupt skipping function 1 MTU4 TADCORA and MTU4 TCNT compare match and MTU4 TADCORB and MTU4 TCNT compare match interrupt skipping function 1 PDL_ADC_12_GP_TRIGGER_ELC
171. using RTC with a capture pin R20UT0708EE0211 Rev 2 11 Page 5 38 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 15 2 Initialization in case of RTC is not used 1 Initialize RTC with providing sub clock use case sub clock is available Figure 5 23 shows an example of initialization in case of RTC is not used and sub clock is available PDL functions include r pdl cgc h include r pdl cmt h PDL device specific definitions include r pdl definitions h void main void Prepare the LOCO settings R_CGC_Set PDL CGC_CLK LOCO PDL_CGC_BCLK_DISABLI 125E3 125E3 125E3 125E3 125E3 PDL NO DA PDL NO DAJ Prepare the HOCO settings p PDL_CGC_BCLK_DISABLI TA p 5 5 E 2 2 P P y the Sub clock settings PDL CGC CLK SUB CLOCK L CGC BCLK DISABLE PDL CGC SUB CLOCK CL STANDARD TA PCIKB clock sub clock when sub clock is source clock rA L_CGC_SUB_32768 WVoWWWWW uy i Wait for the Subclock stabilisation time 2 seconds minimum NOTE As curently running from the Sub clock the R_CMT CreateOneShot max time limit is gt 2 Secs R_CMT CreateOneShot 0 PDL NO DATA 2 0 PDL_NO_FUNC 0 Select the HOCO as the clock source R CGC Control R20UT0708EE0211 Rev 2 11 Page 5 39 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples CGC_C
172. void uint16 t StatusFlags Read the POE status R_ POE GetStatus amp StatusFlags POEO request if StatusFlags amp BIT 0 0x0u Prevent further interrupts and try to clear the flag R_POE Control PDL NO DATA PDL POE FLAG POEO CLEAR PDL POE IRQ HI Z 0 3 DISABL POE8_handler void uintl6 t StatusFlags Read the POE status R_POE GetStatus amp StatusFlags y Prevent further interrupts and try to clear the flag R POE Control PDI PDL POE FLAG POE8 CLEAR PDL POE IRQ HI Z 8 DISABL Figure 5 13 Example of Port Output Enable function R20UT0708EE0211 Rev 2 11 Page 5 25 Aug 01 2014 RENESAS RX210 Group 5 11 Event 5 Usage Examples Link Controller In this example the Event Link Controller links the Compare Match Timer with an I O pin Peripheral driver function prototypes include include include include include ry pdl cgon r pdl_cmt h r pdl io port h r pdl elc h RPDL device specific definitions r pdl definitions h void main void Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_ Set is omitted here Set pin B 0 as an output pin R_IO PORT Set PDL IO PORT B 0 PDL IO PORT OUTPUT Configure CMT channel 1 for 1kHz operation
173. where you wish RPDL for RX210 to be installed c my_project_folder Creating the destination directory c my_project_folder RPDL Copying the generic files Copying the files for little endian support 1 file s copied 1 file s copied Please enter a number to select the device pin package 48 Pins 64 69 Pins 80 Pins 100 Pins 144 145 Pins Select the pin package option by pressing a number and then press Enter oy EE Es Renesas RPDL for RX210 copy utility Please enter a number to select the endian option 1 little endian 2 big endian 1 Please enter the path where you wish RPDL for RX210 to be installed c my_project_folder Creating the destination directory c my_project_folder RPDL Copying the generic files Copying the files for little endian support 1 file s copied 1 file s copied Please enter a number to select the device pin package 48 Pins 64 69 Pins 80 Pins 100 Pins 144 145 Pins 2 Please enter a number to select the device MCU version Note there is only MCU version B in 69 Pins Press any key to continue 4 wj Note there is only MCU version B in 69 Pins Select 2 for the 69 pins package for MCU version R20UT0708EE0211 Rev 2 11 l Page 1 4 Aug 01 2014 EN RX210 Group 1 Introduction olx Please enter a number to select the endian option 1 little endian 2 big endian 1 Please enter the path
174. 01 2014 4 Library Reference Read the CRC calculation result bool R_CRC_Read uint8_t data1 Control uint16_t data2 Data storage location Reads and stores the CRC calculation result data1 Control the behaviour of the CRC unit The default setting is shown in bold Specify PDL_NO_DATA to use the default Result register clearing PDL_CRC_CLEAR_RESULT or PDL CRC RETAIN RESULT Clear or retain the value in the result register data2 The address of the location where the result shall be stored For the 8 bit polynomial the results are stored in the lower order byte True CRC R_CRC_Create R_CRC_Write None RPDL definitions include r pdl_crc h RPDL device specific definitions include r pdl definitions h void func void uintl6 t CRCresult Read the CRC result and retain it R_CRC_ Read PDL_CRC_RETAIN RESULT amp CRCresult RENESAS Page 4 270 RX210 Group 4 Library Reference 4 2 25 1 R_ADC_12 Set 12 bit Analog to Digital Converter Synopsis Select the I O pins for the 12 bit ADC Prototype bool R_ADC_12_Set uint32_t data ADC unit selection Description Select the I O pins for the12 bit ADC data Select the pin set options To set multiple options at the same time use to separate each value e Pin selection PDL_ADC 12 PIN_ANOOO_P40 Select
175. 0211 Rev 2 11 Aug 01 2014 Page 4 286 RENESAS RX210 Group 4 Library Reference 3 R_TS_Control Synopsis Prototype Description Return value Category Reference Remarks Program example Control the Temperature Sensor operation bool R_TS_Control uint8_t data PGA control Start PGA operation data Operating condition PGA control PDL_TS_PGA_START or PDL_TS_PGA_STOP Start orstop POA True if successful false if TS not enabled TS R_TS_Create e Must call R_TS_Create to enable TS module before calling this function RPDL definitions include r_pdl_ts h RPDL device specific definitions include r pdl definitions h void func void Start PGA and A D Conversion R_TS Control PDL TS PGA_START R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS Page 4 287 RX210 Group 4 Library Reference 4 2 28 Comparator A 1 R_CPA_Create Synopsis Configure the Comparator A module Prototype bool R_CPA_Create uint8_t data1 II Comparator A channel selection uint16_t data2 Configuration for Comparator A void func Callback function pointer for Comparator A uint8_t data3 Interrupt priority Description Set up Comparator A enable the interrupt register and callback functions Return value Ca
176. 0E6 PDL NO DAT PDL NO DAT Configure PLL operation The PLL will be set to 100 MHz R CGC Set PDL CGC CLK PLL PDL CGC BCLK DIV 2 100E6 50E6 50E6 25E6 25E6 25E6 PDL_NO_DATA i Allow time for the main clock oscillator to stabilise Generate the 100 us delay R_CMT CreateOneShot 0 PDL NO DATA 100E 6 PDL NO FUNC 0 dF Select the PLL as the clock source R_CGC_Control PDL_CGC_CLK_PLL PDL NO DATA PDL NO DATA de Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL INTC REG IPL 0 R20UT0708EE0211 Rev 2 11 Page 5 28 Aug 01 2014 ztENESAS RX210 Group 5 Usage Examples Configure TMRO input and output pins R TMR Set 0 PDL TMR TMRO TMOO PB3 PDL TMR TMRO TMCIO PB1 PDL TMR TMRO TMRIO PA4 y Configure TMRO for 500us pulse width 200us on time R_TMR CreatePeriodic PDL_TMR_TMRO PDL TMR PERIOD PDL TMR_OUTPUT_HIGH 500E 6 200E 6 PDL NO FUNC PDL NO FUNC 0 The same operation using frequency and duty cycle R_TMR CreatePeriodic PDL_TMR_TMRO PDL_TMR_ FREQUENCY PDL TMR OUTPUT HIGH 2E3 40 PDL_NO_FUNC PDL_NO_FUNC Figure 5 16 Example of Pulse Output code R20UT0708EE0211 Rev 2 11 Page 5 29 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples For full flexibility the R_TMR_CreateChannel function
177. 1 PDL_BSC_WIDTH 8 PDL_BSC_ WRITE BYTE 0 oN ss gt ss lt OOO OO 0 0 0 0 O 010 O i Configure area 2 R_BSC_CreateArea 2 PDL_BSC_WIDTH 16 PDL_BSC_WRITE SINGLE 0 sw NON SONOS 0 0 0 0 0 0 0 0 0 0 0 0 0 i Configure area 3 R_BSC_CreateArea 3 PDL BSC WIDTH 16 157 Loy 7 7 Configure the bus controller R_BSC Create PDL BSC _CS0_ P24 PDL BSC_CS1_PC6 PDL BSC_CS2 P26 PDL_BSC_CS3 P27 PDL BSC WAIT P55 PDL BSC ALE ENABLE PDL BSC _A9 DISABLE PDL BSC RCV SRRS ENABLE PDL BSC _ ERROR ILLEGAL ADDRESS ENABLE PDL BSC ERROR TIME OUT ENABLE BSC _ error handler R20UT0708EE0211 Rev 2 11 Page 5 16 Aug 01 2014 ENESAS RX210 Group 5 Usage Examples de Enable the bus controller R_BSC_Control PDL BSC ENABLE i Write to external areas cs0 location 8 0x23u csl location 8 OxAAu cs2 location 16 0x3344u cs3 location 16 OxAA55u Disable area CS1 R BSC Destroy y void BSC error handler void Clear the error signals R BSC Control PDL BSC_ERROR_CLEAR y Figure 5 9 Example of Bus Controller use R20UT0708EE0211 Rev 2 11 Page 5 17 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 8 DMA controller The following example shows the use of triggers by software and IRQ pin edge detection Channel 0 will co
178. 1 to b7 bO R_MCU_GetStatus Removed some bits from data1 parameter that are not in use R_LVD_Create added remarks R_CAC_Create PDL_CAC_CACREF_FILTER_DISABLE is now a default R_CAC_Create Added remarks that callbacks must clear flags as interrupt is level based R_CAC_Control Added remark abot avoiding lockup by not enabling disabling from a callback whilst also doing from main R_LPC_Create and R_LPC_Control Added Middle Speed Modes 2A and 2B and renamed Middle Speed A and B to 1A and 1B R_LPC_Create Added remark that flash power control is automatic with MCU Version B R_LPC_Control Added remark about controlling SCK in standby mode if using SCI Smart Card mode R_RWP_Control Added VRCR access R20UT0708EE0211 Rev 2 11 Revision History 1 Aug 01 2014 2tENESAS RX210 Group Revision History Description 18 June 2013 This page R20UT0708EE0211 Rev 2 11 Aug 01 2014 R_BSC_Set Changed description of priority options to include toggle R_DMAC_Create Added TPU triggers and additional SCI channel triggers R_DTC_Create Corrected Trigger selection name R_DTC_Create Added TPU triggers and additional SCI channel triggers R_ELC_Control Added remark Restriction when SPI generates Transmit end event R_MTU2_Create Revised restriction for buffer operation R_MTU2_ControlUnit Update PDL_MTU2_BDCM_OPS_XXX comment R_RTC_Create Added PDL_RTC_NOT_TO_USE option R_RTC_Create Added r
179. 1 R_CGC_Set Configure the clock generation circuit Generation 2 R_CGC_Control Modify the clock generation circuit operation Circuit 3 R_CGC_GetStatus Read the clock status register 1 R_INTC_SetExtInterrupt Select the external interrupt pins 2 R_INTC_CreateExtInterrupt Configure an external interrupt signal 3 R_INTC_CreateSoftwarelnterrupt Enable use of the software interrupt 4 R_INTC_CreateFastInterrupt Assign handlers for the fixed vector interrupts Interrupt control 5 R_INTC_CreateExceptionHandlers Ee interrupt processing for one unit 6 R_INTC_ControlExtInterrupt External interrupt control 7 R_INTC_GetExtInterruptStatus Read the external interrupt status 8 R_INTC_Read Read an interrupt register 9 R_INTC_Write Update an interrupt register 10 R_INTC_Modify Modify an interrupt register R_IO_PORT_Set Configure an I O port R_IO_PORT_ReadControl Read an I O port s control registers R_IO_PORT_ModifyControl Modify an I O port s control registers R_IO_PORT_Read Read data from an I O port 1 O port R_IO_PORT_Write Write data to an 1 O port R_IO_PORT_Compare Check the pin states on an I O port R_IO_PORT_Modify Modify the pin states on an I O port R_IO_PORT_Wait Wait for a match on an I O port R_IO_PORT_NotAvailable Configure I O port pins that are not available Multifunction Pi R_MPC_Read Read a PFC register o pres e i R_MPC_Write Write to a PFC
180. 11_SCK11_ P75 SCK11 PDL SCI PIN SCl11_CTS11_ P74 CTS11 PDL_SCI_PIN_SCI11_RTS11_P74 RTS11 PDL_SCI_PIN SCl11_SS11_P74 SS11 Valid when n 12 PDL SCI PIN SCI12 RXD12 PE2 RXD12 PDL_SCI_PIN_SCI12_SMISO12_PE2 SMISO12 PDL_SCI_PIN_SCI12_SSCL12 _PE2 SSCL12 PDL_SCI_PIN_SCI12_TXD12_PE1 TXD12 PDL_SCI PIN SCI12 SMOSI12 PE1 sci2 SMOSI12 PDL SCI PIN SCI12 SSDA12 PE1 SSDA12 PDL_SCI_PIN_SCI12_SCK12 PEO SCK12 PDL_SCI_PIN_SCI12_CTS12_PE3 CTS12 PDL_SCI_PIN_SCI12_RTS12_PE3 RTS12 PDL_SCI PIN SCl12 SS12 PE3 ss12 True if all parameters are valid and exclusive otherwise false SCI R_SCI_Create Before calling R_SCI_Create call this function to configure the required pins This function configures each specified SCI pin It also disables the alternative modes on those pins Please refer to the Multifunction Pin Controller MPC section in the RX210 Hardware Manual for details of SCI pin selection Not all pins are available on all device package sizes tinclude r pdl _sci h void func void Configure RXD1 and TXD1 pins R_SCI_Set 1 PDL SCI PIN SCI1 RXD1 P15 y PDL SCI PIN SCI1 TXD1 P16 RENESAS Page 4 212 RX210 Group 2 R_SCI_Create Synopsis Prototype Description 1 4 R20UT0708EE0211 Rev 2 11 Aug 01 2014 SCI channel setup bool R_SCI_Create 4 Library Reference uint8_t data1 Channel selection uint32_t data2 Channel c
181. 12 bit ADC unit providing the following operations 1 2 6 I O pin configuration Unit specific configuration for use including e Automatic clock setting using sampling time as an input e Automatic interrupt control Channel specific configuration for use including e Double trigger control e Sample and hold control e Sampling time control Disabling the unit when no longer required and enabling low power mode Control the ADC unit including e CPU sleep option Reading the conversion results with support for polling or interrupts Note The Clock Generation Circuit must be configured before configuring the ADC unit R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS di RX210 Group 2 Driver 2 28 10 bit Digital to Analog Converter Driver The driver functions support the use of the DAC module providing the following operations 1 Configuring a channel for use including e Independent or linker operation e Data alignment 2 Disabling channels that are no longer required and enabling low power mode 3 Writing data to a channel R20UTO708EE0211 Rev 2 11 L2 _ Page 2 28 Aug 01 2014 RENESAS RX210 Group 2 Driver 2 29 Temperature Sensor Driver The driver functions support the use of the Temperature Sensor module providing the following operations 1 Configuring and enabling the Temperature Sensor 2 Disabling the Temperature Sensor and enabling low power mode 3 Controlling
182. 14_ DISABLE Disable the output of the A14 signal PDL_BSC_A15 DISABLE Disable the output of the A15 signal PDL_BSC_A16_DISABLE Disable the output of the A16 signal PDL_BSC_A17_DISABLE Disable the output of the A17 signal PDL_BSC_A18 DISABLE Disable the output of the A18 signal PDL_BSC_A19 DISABLE Disable the output of the A19 signal PDL_BSC_A20 DISABLE Disable the output of the A20 signal PDL_BSC_A21_DISABLE Disable the output of the A21 signal PDL_BSC_A22_ DISABLE Disable the output of the A22 signal PDL_BSC_A23_ DISABLE Disable the output of the A23 signal RENESAS Page 4 82 RX210 Group Description 2 2 4 Library Reference data3 e Recovery cycle insertion control The controls are disabled by default Specify PDL_NO_DATA to use the defaults If multiple selections are required use to separate each selection Ignored for packages with less than 100 pins specify PDL_NO_DATA Bus access Bus type Current Next ASA PDL_BSC_RCV_SRRS_ENABLE Read Same PDL_BSC_RCV_SRRD_ENABLE Read Different PDL_BSC_RCV_SRWS_ENABLE Write Same PDL_BSC_RCV_SRWD_ENABLE Separate Different PDL_B
183. 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func Return value True if all parameters are valid otherwise false Category Interrupt control Reference R_INTC_Write Remarks e Please see the notes on callback function use in 6 Specifying PDL_NO_FUNC for the callback function allows the software interrupt to be used as a DTC trigger Use R_INTC_Write to generate the software interrupt Program example RPDL definitions include r pdl_intc h RPDL device specific definitions include r pdl_definitions h Declaration of callback function void CallBackFunc void void func void Configure the software interrupt handler R_INTC_CreateSoftwareInterrupt PDL_NO_DATA CallBackFunc 7 i R20UT0708EE0211 Rev 2 11 Page 4 17 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 4 R_INTC_CreateFastinterrupt Synopsis Prototype Description 1 4 Enable faster interrupt processing for one interrupt bool R_INTC_CreateFastinterrupt The interrupt to be selected uint8_t data data Choose the interrupt vector to be processed using the fast interrupt process Name Module Interrupt cause PDL_INTC_VECTOR_BUSERR External bus Error illegal access or timeout PDL_INTC_VECTOR_FIFERR Flash Error
184. 16_t TCDR_value uint16_t TCBR_value Modify a timer unit s registers data1 The unit number n where n 0 simultaneous_control 1 Control selection II Register selection Register value Register value Register value Simultaneous stop start control All selections are optional If multiple selections are required use to separate each selection Specify PDL_NO_DATA if no change is required e Counter stop control PDL_MTU2 STOP C PDL_MTU2 STOP CH_ 0 1 2 PDL_MTU2_STOP_CH_3 H H PDL_MTU2_STOP_CH H H PDL_MTU2_STOP_CH 4 Stop the count operation for the selected channels Counter start control PDL_MTU2_START_C PDL_MTU2_START_C PDL_MTU2_START_C HO H1 PDL_MTU2 START CH 2 H3 H4 PDL _MTU2_ START C Start the count operation for the selected channels RENESAS Page 4 139 RX210 Group Description 2 4 R20UT0708EE0211 Rev 2 11 Aug 01 2014 output_control The output control settings to be modified All settings are optional If multiple selections are required use to separate each selection Output control To apply output control make sure the operation of t Select one option for each output 4 Library Reference he corresponding channel is stopped PDL_MTU2_OUT_P_PHASE_1 ENABLE or PDL_
185. 2 zZ BSg9gget gggsy wW o w i o eA o a t Bee QO 0 0 0 0 0 y else If Cold start is detected the RTC clock should be re started R_SCI_Send RSK_SCI_CHANNEL PDL NO DATA r nRTC Start in Cold start mode Initailize RTC r n 0 PDL NO FUNC R20UT0708EE0211 Rev 2 11 Page 5 43 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples if R_RTC Create RTC ALARM TIME ENABLE PDL RTC ALARM DATE ENABLE L_NO_ DATA FF114250 Automatic day of week 11 42 50 20131118 18 Nov 2013 L NO DATA Capture 0 L NO DATA Capture 1 L NO DATA Capture 2 PDL NO DATA Periodic OxFF114300 Alarm in 10 seconds 0x20131118 18 Nov 2013 Alarm _ handler 15 PDL_NO_FUNC PDL_NO_DATA false UUU X UNI p p 0 0 P P P R_SCI_Send RSK_SCI_CHANNEL PDL NO DATA r nRTC Create error in Cold start mode r n 0 PDL NO FUNC while 1 after the complete initialization Set the warm start indicator R_MCU Control PDL MCU WARM START This call should cancel the settings made in above call to R_LPC Create Allow RTC interval interrupt signal wake us up from deep software standby R_LPC Create PDL LPC HIGH SPEED MODE PDL NO DATA PDL NO DATA PDL LPC CANCEL RTCA ENABLE PDL NO DATA PDL NO DATA PDL NO DATA 7 R_RTC_Read PDL RTC READ CURRE
186. 2_DISABLE or PDL_LPC_CANCEL_LVD2_FALLING or PDL_LPC_CANCEL_LVD2_RISING Prevent or allow an edge on the LVD2 pin to cancel deep software standby mode PDL_LPC_CANCEL_RTCI_DISABLE or PDL_LPC_CANCEL_RTCI_ENABLE Prevent or allow the RTC interval interrupt signal to cancel deep software standby mode PDL_LPC_CANCEL_RTCA_DISABLE or PDL_LPC CANCEL _RTCA ENABLE Prevent or allow the RTC alarm interrupt signal to cancel deep software standby mode PDL_LPC_CANCEL_NMI_DISABLE or PDL_LPC_CANCEL_NMI_FALLING or PDL_LPC_CANCEL_NMI_RISING Prevent or allow an edge on the NMI pin to cancel deep software standby mode PDL_LPC_CANCEL_IICD_DISABLE or PDL_LPC_CANCEL_IICD_FALLING or PDL_LPC_CANCEL_IICD_RISING Prevent or allow an edge on the IIC SDA pin to cancel deep software standby mode PDL_LPC_CANCEL_lICC_DISABLE or PDL_LPC_CANCEL_IICC_FALLING or PDL_LPC_CANCEL_lICC_RISING Prevent or allow an edge on the IIC SCL pin to cancel deep software standby mode RENESAS Page 4 70 RX210 Group Description 4 5 R20UT0708EE0211 Rev 2 11 Aug 01 2014 data4 4 Library Reference Select the main clock oscillator waiting time If no selections are required specify PDL_NO_DATA e Software Standby waiting time PDL_LPC_MAIN_2 or PDL_LPC_MAIN_4 or PDL_LPC_MAIN_8 or PDL_LPC_MAIN_16 or PDL_LPC_MAIN_32 or PDL_LPC_MAIN_256 or PDL_LPC_MAIN_512 or PDL_LPC_MAIN_1024 or
187. 3 6V lt AVCCO lt 4 5V PDL_TS_PGA_GAIN_3 or 4 5V lt AVCCO lt 5 5V True if all parameters are valid and exclusive otherwise false TS R_ADC_12_CreateUnit e R_ADC_12_CreateUnit must be called to configure the temperature sensor as the target of Program example A D conversion before use this function RPDL definitions include r pdl ts h RPDL device specific definitions tinclude r pdl definitions h void func void Set PGA gain and enable TS R TS Create PDL_TS PGA GAIN 2 R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 285 RENESAS RX210 Group 4 Library Reference 2 R_TS_Destroy Synopsis Prototype Description Return value Category Reference Shut down the Temperature Sensor bool R_TS_Destroy void No parameter is required Put the Temperature Sensor into the Power down state with minimal power consumption True if successful false if PGA still in operation TS R_TS_Create R_TS_Control Remarks Program example e IfR_TS_Control is called must wait for A D conversion to finish before calling this function RPDL definitions include r pdl ts h RPDL device specific definitions tinclude r pdl_ definitions h void func void Shut down the Temperature Sensor R_TS Destroy R20UT0708EE
188. 4 RENESAS Page 4 299 RX210 Group Program example RPDL definitions include r pdl doc h RPD void func void L device specific definitions include r pdl definitions h 4 Library Reference Change to subtraction mode with initial value 500 R_DOC Control R20UT0708EE0211 Rev 2 11 Aug 01 2014 PDL_DOC_MODE SUBTRACT PDL DOC DATA UPDATE 500 RENESAS Page 4 300 RX210 Group 4 R_DOC_Read Synopsis Prototype Description Return value Category References Remarks Program example R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference Read the Data Operation Circuit result bool R_DOC_Read uint8_t data1 uint16_t data2 II Pointer to status storage location II Pointer to value storage location Read the DOC status and output data1 The status flags shall be stored in the format below Specify PDL_NO_PTR if this information is not required b7 b1 bO Flag see remarks data2 This meaning of this parameter depends upon the Operation Mode as specified in the table below Specify PDL_NO_PTR if this information is not required Operation Mode Description Comparison The set comparison value Addition The addition result Subtraction The subtraction result True DOC
189. 4 Library Reference Program example RPDL definitions include r pdl_mtu2 h RPDL device specific definitions include r pdl definitions h void func void Allocate a copy of the structure for the selected channel R_MTU2 ControlChannel structure ch3 parameters Set the control options for channel 3 ch3 parameters control setting PDL MTU2_ START ch3 parameters register selection PDL MTU2 REGISTER COUNTER PDL _MTU2_REGISTER_TGRB ch3 parameters TCNT TCNTU_ value OxFFDD ch3 parameters TGRB TCNTW value 0x0020 Modify the operation of channel 3 R_MTU2 ControlChannel 3 amp ch3 parameters y R20UT0708EE0211 Rev 2 11 Page 4 138 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 5 R_MTU2_ControlUnit Synopsis Prototype Description 1 4 R20UT0708EE0211 Rev 2 11 Aug 01 2014 Control a Multi function Timer Pulse Unit bool R_MTU2_ControlUnit uint8_t data1 Unit selection R_MTU2_ControlUnit_structure data2 A pointer to the structure R_MTU2_ControlUnit_structure members uint16_t simultaneous_control 1 Control selection uint32_t output_control uint32_t buffer_control Control selection Control selection uint16_t brushless _DC_motor_control Control selection uint32_t general_control uint8_t register_selection uint16_t TDDR_value uint
190. 4 Library Reference 5 R_TMR_CreateOneShot Synopsis Prototype Description Return value Category Reference Configure and use a one shot timer bool R_TMR_CreateOneShot uint8_tdata1 8 bit channel or 16 bit unit timer selection uint32_t data2 Configuration selection double data3 II Period void func Callback function uint8_t data4 Interrupt priority level Set up a TMR timer channel or unit for one shot operation and start the timer data1 PDL_TMR_TMRO or PDL_TMR_TMR1 or PDL_TMR_TMR2 or PDL_TMR_TMR3 or PDL_TMR_UNITO or PDL_TMR_UNIT1 The channel n n 0 1 2 or 3 or unit n n 0 or 1 to be configured data2 Configure the timer Use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Output pin control For the duration of the one shot period generate a PDL_TMR_OUTPUT_HIGH or high level output PDL_TMR_OUTPUT_LOW or low level output or PDL_TMR_OUTPUT_OFF no output on pin TMOn For 16 bit operation the pin shall be TMO2 when n 1 e DTC trigger control PDL_TMR_PULSE_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_TMR_PULSE_DTC_TRIGGER_ENABLE DTC when the one shot period ends Control the CPU during the one shot operation PDL_TMR_CPU_ON or Allow the CPU to run normally while the one shot operates Sto
191. 5 4 2 30 Data Operation Circuit 2 0 0 ccc irane eaa i eeaeee aaiae a EEE aaia a aeaaaee akai anea aiaa aa Eaa 4 296 A D AES DOLORE ET I ae 4 296 2 R DOG DESO ion e N EE pea eee A 4 298 e e ABIDE Ke E ca E Ne EA ET E E EEE EEA E 4 299 Ay RDO G Read ni ET 4 301 9 RUDO MIMO it E EEE E AE EI A EE EEA A E 4 302 4 2 31 16 bit Timer Pulse UNE e a a ree ae aa ra a aa aaa aaaea a aoe aa Aaa Eaa 4 303 RETRO Sd E E EA E E er E EES 4 303 2 RAE d OEE A E E A N bio lta 4 305 3 R TIPU DESTO a A A a 4 311 4 AR TPU CONO C hae ci a A Gee ad a ica 4 312 5 ReTPUControlUnitscc i A A ee WR aaka 4 314 6 R TIPU Reads oen emetic A ae ed ied teed eed oe 4 315 Usage Exaimples siiccicestih ccc dde 5 1 DT Clock Generation Circuit a e e a Meet bi a a lg bead daa vady beete la a Med Sted eae 5 2 5 2 Interrupt control s 0cceiee arta te tie ae ued ene een eee 5 4 SRS PERENE B o aes 8 eit ae tas haa Sack ee nd ate see a oa aaa eg aa cata cee aaa A A AA cet dens ins eae Raat ts 5 6 5 4 Voltage Detection Circ it rnaraneh cece henii a eaae ee a a a eead e a eai a a 5 8 5 4 1 MaskKable INterr piS nirera o o a aaa a a cee tt ieee i a 5 8 5 4 2 N n maskableiNt rr ptS iaso aaae aende a aeaa iar 5 9 5 5 Clock Frequency Accuracy Measurement Circuit ooooconnccccnnnocccccononcccnononcncnnnanc conan nn nn canon cnc nana ncccnnns 5 10 5 6 Low Power CONSUM PION e a a er a arr cn nens cnn nn nen n nn rra nn nn mn nnnnnnnnrnnnnmnnnennnninnnss 5 12
192. 5 17 6 SCI Reception in Asynchronous Multi Processor mode oooonocccccnnocccccononcccnononcncnanancccnanancncnno 5 62 5 17 7 SCI Transmission in Asynchronous Multi Processor Mode ooccccococccccnconccccononcncnnnancccnanncninno 5 64 9 1 9 SCM IMS PLM OG sii A iaa 5 66 STE SCM INC MO Cries osa iaa Aa ii 5 67 5 17 10 SCl in lIC Mode using DMAC C esien A naar nn cr nn ana ncr nana ncncinns 5 69 SAn i SCKIN NEC Mode USING DO Ear ii iia 5 71 5 187 O Bus interfacet an A cas tied used A ded Ana 5 74 5 18 1 Mastenm Ode cj satirs sie tras A nen a A demas A 5 74 1 Configuration and tranSMiSSiON oooonnnccnnnnnncccnnnoccccnnnrnccn nono a rca rca 5 75 2 REGOPUUON Ss ss di a a A A a 5 77 3 Repeated Ma iaa ARA dep date 5 78 5 18 2 Master mode with DMAC cccccccececsecceceeeeeeeeeeeaeceeeeeeeeeceaaeaeeeeeeeseseeaaeeeeeeeeesecsncieeeeeeeettees 5 79 5 18 3 Master mode with DTC oooononcccconoccccnnnanccnnonanccnnnnnnccnnnnnnecrnnnnne crean crean creencia creanme crias 5 83 0 10 47 Slave MOGs ermita A A ia 5 88 5 19 Serial Peripheral Interface ccccccceceeeceeece cece cece ee ceceenaeceeeeeeesecaanaeceeeeeeesensaeeeceseeeseeennieeeeeeeeeeess 5 91 5 19 1 Master operation with multiple Slaves ooooooocnnnninicncccnnnnnnoconononncnnnnnnnnnnononocnnnnnnnnnnnnn nn cnnnnnnnnns 5 91 9 20 CREA id a 5 94 5 21 12 bit Analog to Digital Converter ococoonnncccnnnncccccnnoncccnononcccnnnoncncnnnnnncc canon cn
193. 553 Valid when n 4 PDL_SCI_PIN_SCI4_RXD4_PBO or isa PDL_SCI_PIN_SCI4_RXD4_PK4 PDL_SCI_PIN_SCI4_SMISO4_PBO or PDL_SCI_PIN_SCI4_SMISO4_PK4 SMISO4 PDL_SCI_PIN_SCI4_SSCL4_PBO or ae PDL_SCI PIN SCI4_SSCL4 PK4 PDL_SCI_PIN_SCI4_TXD4_PB1 or PDL_SCI_PIN_SCI4_TXD4_PK5 PDL_SCI_PIN_SCI4_SMOSI4_PB1 or PDL_SCI_PIN_SCI4_SMOSI4_PK5 m SMOSI4 PDL_SCI_PIN_SCI4_SSDA4_PB1 or a PDL SCI_PIN_SCI4_SSDA4 PK5 PDL_SCI_PIN_SCI4_SCK4_P70 or ad PDL_SCI_PIN_SCI4_SCK4_PB3 PDL_SCI_PIN_SCI4_CTS4_PB2 or ae PDL_SCI_PIN_SCI4_CTS4_PE6 PDL_SCI_PIN_SCI4_RTS4_PB2 or cas PDL SCI PIN SCI4_RTS4 PEG PDL_SCI_PIN_SCI4_SS4_PB2 or SN PDL_SCI_PIN_SCI4_SS4_PE6 Page 4 209 RENESAS RX210 Group Description 4 6 Valid when n 5 4 Library Reference R20UT0708EE0211 Rev 2 11 Aug 01 2014 PDL_SCI_PIN_SCI5_RXD5_PA2 or PDL_SCI_PIN_SCI5_RXD5_PA3 or PDL_SCI_PIN_SCI5_RXD5_PC2 PDL_SCI_PIN_SCI5_SMISO5_PA2 or PDL_SCI_PIN_SCI5_SMISO5_PA3 or PDL_SCI_PIN_SCI5_SMISO5_PC2 PDL_SCI_PIN_SCI5_SSCL5_PA2 or PDL_SCI_PIN_SCI5_SSCL5_PA3 or PDL_SCI PIN_SCI5_SSCL5_PC2 PDL_SCI_PIN_SCI5_TXD5_PA4 or PDL_SCI PIN_SCI5_TXD5_PC3 PDL_SCI_PIN_SCI5_SMOSI5_PA4 or PDL_SCI_PIN_SCI5_SMOSI5_PC3 PDL_SCI_PIN_SCI5_SSDA5_PA4 or PDL_SCI PIN_SCI5_SSDA5 PC3 PDL_SCI_PIN_SCI5_SCK5_PA1 or PDL_SCI_PIN_SCI5_SCK5_PC1 or PDL_SCI_PIN_SCI5_SCK5_PC4 PDL_SCI_PIN_SCI5_CTS5_PA6 or PDL_
194. 58 5141 O 2014 Renesas Electronics Corporation All rights reserved Colophon 3 0 RX210 Group ENESAS Renesas Electronics Corporation R20UTO708EE0211
195. 6 7 kbps 83 6 kbps 217 kbps 57 8 kbps PCLKB 128 1 52 kbps to 1 5 kbps to 3 89 kbps to 116 975 bps to 45 9 kbps 44 2 kbps kbps 30 0 kbps R20UT0708EE0211 Rev 2 11 Page 4 241 Aug 01 2014 RENESAS RX210 Group 4 Library Reference Program example RPDL definitions include r _pdl iic h RPDL device specific definitions include r pdl definitions h void func void Select IIC mode at 100kHz 100ns rise and fall times R_IIC_Create 0 PDL IIC MODE IIC PDL IIC INT PCLK DIV 8 PDL NO DATA PDL NO DATA PDL NO DATA PDL NO DATA 10053 100 lt lt 16 100 di Select IIC mode with two slave addresses R_IIC_Create 0 PDL IIC MODE IIC PDL IIC SLAVE 0 ENABLE 7 PDL IIC SLAVE 1 ENABLE 7 0x0020 0x0056 PDL NO DATA 100E3 300 lt lt 16 200 de R20UT0708EE0211 Rev 2 11 Page 4 242 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 3 R_IIC_Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example Disable an C channel bool R_IIC_Destroy uint8_t data Channel selection Shut down the selected 1 C module data Select channel IICn where n 0 True if the parameter is valid otherwise false C R_IIC_Create The l C module is put into the power down state RPDL
196. 62144 or PDL_LPC_PLL_524288 or PDL_LPC PLL_4194304 PDL_LPC_PLL_1048576 or PDL_LPC_PLL_2097152 or Select the oscillation settling time of the PLL before the CPU resumes after exiting from software standby mode When updating this value the PLL circuit must be stopped RENESAS Page 4 71 RX210 Group Description 5 5 Return value Category References Remarks R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference data7 Select the HOCO oscillator waiting times If no selections are required specify PDL_NO_DATA Deep Software Standby waiting time PDL_LPC_HOCO_3072 or PDL_LPC_HOCO_5120 or PDL_LPC_HOCO_7168 or PDL_LPC_HOCO_9216 or PDL_LPC_HOCO_11264 or PDL_LPC_HOCO_13312 or PDL_LPC_HOCO_15360 or PDL_LPC_HOCO_17408 or Select the oscillation settling time of the HOCO oscillator before the CPU resumes after exiting from software standby mode PDL_LPC_HOCO_19456 or i F j PDL LPC HOCO 21504 or pio gd this value the HOCO oscillator must be PDL_LPC_HOCO_23552 or PDL_LPC_HOCO_25600 or PDL_LPC_HOCO_27648 or PDL_LPC_HOCO_29696 or PDL_LPC_HOCO_31744 or PDL_LPC_HOCO_33792 True if all parameters are valid and exclusive otherwise false LPC R_LPC_Control R_CGC_Control R_CGC_Set e If PDL_LPC_IO_DELAY is specified use R_LPC_Control with the PDL_LPC_IO_RELEASE option to cancel the I O port state retention The IRQn DS pin
197. 6384 Timeout period specified in cycles of the divided clock as specified in the Clock Selection below e Clock division PDL_MCU_OFS WDT_CLOCK PCLK 4 or PDL_MCU_OFS WDT_CLOCK PCLK_64 or PDL_MCU_OFS WDT_CLOCK PCLK 128 or PDL_MCU_OFS WDT_CLOCK PCLK 512 or PDL_MCU_OFS_WDT_CLOCK_PCLK_2048 or PDL_MCU_OFS WDT_CLOCK PCLK_ 8192 The selected clock The PCLKB 4 64 128 512 2048 or 8192 e Window end position PDL_MCU_OFS_WDT_WIN_END_75 or The window end position specified as a PDL_MCU_OFS_WDT_WIN_END_50 or percentage of the down counter 0 is when PDL_MCU_OFS_WDT_WIN_END_25 or the down counter would underflow Selecting PDL_MCU_OFS_WDT_WIN_END 0 0 is equivalent to no window end position e Window start position PDL_MCU_OFS_WDT_WIN_START_25 or PDL_MCU_OFS_WDT_WIN_START_50 or PDL_MCU_OFS_WDT_WIN_START_75 or PDL_MCU_OFS_WDT_WIN_START_100 The window start position specified as a percentage of the down counter 0 is when the down counter would underflow Selecting 100 is equivalent to no window start position Underflow action PDL_MCU_OFS_WDT_NMI or Select an NMI or reset when the WDT PDL_MCU_OFS_WDT_RESET down counter underflows data3 Select the post reset LVD configuration settings If multiple selections are required use to separate each selection e Auto start control PDL_MCU_OFS_LVD_0_DISABLE or Disable or
198. 9200 L y Set flag to wait on R20UT0708EE0211 Rev 2 11 Page 5 58 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples data received false Setup a read on channel slave R_SCI Receive SLAVE CHANNEL PDL_NO_DATA rx buffer 5 SCI9RxFunc PDL_NO_FUNC y Send the data from the master R_SCI_ Send MASTER CHANNEL PDL_NO DATA 123 45 5 PDL_NO_FUNC y Wait for channel slave to receive while data_received false Process the received data here SCI channel 9 receive complete handler static void SCI9RxFunc void Set flag data_received true Figure 5 31 Example of Synchronous Transmission and Reception code R20UT0708EE0211 Rev 2 11 Page 5 59 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 17 5 Synchronous Full Duplex Operation This shows the configuration of SCI channel 6 as a clock master with both Rx and Tx data pins enabled Data is received at the same time as data is transmitted Peripheral driver function prototypes include r pal sci h include r pdl cgc h include r pdl intc h RPDL device specific definitions include r pdl definitions h SCI channel selection define MASTER CHANNEL 6 define SLAVE CHANNEL 9 define DATA LENGTH 5 Rx complete flag volatile uint8 t data
199. A companion function R_MTU2_Create_load_defaults can be used to load the default values into the structure If the channel operation mode will be changed ensure that the timer is stopped use R_MTU2_ControlChannel or R_MTU2_ControlUnit if noise filter is enabled wait for 2 cycles of the selected noise filter clock before starting the timer use R_MTU2_ControlChannel or R_MTU2_ControlUnit RPDL definitions nclude r pdl mtu2 h RPDL device specific definitions nclude r pdl definitions h id func void Allocate a copy of the structure for the selected channel R_MTU2 Create structure ch4 parameters Load the defaults R_MTU2 Create load defaults amp ch4 parameters Set the non default options for channel 4 ch4 parameters channel mode PDL MTU2 MODE NORMAL A PDL_MTU2 SYNC ENABLE PDL MTU2 TGRA DTC TRIGGER ENABLE ch4 parameters counter operation PDL MTU2 CLK PCLK DIV 4 ch4 parameters buffer operation PDL MTU2 BUFFER AC CM A ch4 parameters TGR_C_D operation PDL MTU2 C OC HIGH CM LOW ch4 parameters TCNT_TCNTU_value 0 ch4 parameters TGRA_TCNTV value 199 ch4 parameters TGRB TCNTW value 99 ch4 parameters TGRC_TGRU_ value 50 ch4 parameters TGRD TGRV_value 100 ch4 parameters TGRE TGRW value 0 ch4 parameters TGRF TADCORA value 0 R_MTU2 Create 4 amp ch4 parameters y Page 4 134 RENES
200. API press F11 key to step in the function A pop up window will appear to request for the location of the corresponding RPDL source file Look in C3 my_project_folder e e FE RPDL me RPDL_RX210_CS x xx_source File name R_CRC_Witedll c Files of type Source File c y Cancel Select the folder where you unzip the RPDL source file and open the source file under respective module folder Once the correct source file is selected user could step in to the file and step through the function R20UT0708EE0211 Rev 2 11 Page 1 14 Aug 01 2014 RENESAS RX210 Group 1 Introduction 1 3 3 Header file inclusion The RPDL folder contains a header file iodefine_RPDL h This file is included by the RPDL source files and will also be included by any user generated files that call RPDL functions The main HEW project folder may contain the header file iodefine h This file is normally used if access to the I O registers in the MCU is required For any user generated files that call RPDL functions there is no need to include this file iodefine h 1 3 4 Header file order The file r_pdl_definitions h must be included and placed after any peripheral specific header file For example Peripheral driver function prototypes and definitions include r pdl_cgc h include r pdl_cmt h PDL device specific definitions tinclude r pdl definitions h R20UT0708EE0211 Rev 2 11 P
201. AS RX210 Group 4 Library Reference 3 R_MTU2_Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example Disable a Multi function Timer Pulse Unit bool R_MTU2_Destroy uint8_t data Unit selection Shut down a timer pulse unit data The multi function timer pulse unit n where n 0 Unit O comprises channels 0 to 5 True if the unit selection is valid otherwise false Multi function Timer Pulse Unit None e The unit is put into the stop state to reduce power consumption tinclude r pdl_mtu2 h void func void Shutdown MTU2 channels 0 to 5 R_MTU2 Destroy 0 R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 135 RENESAS RX210 Group 4 Library Reference 4 R_MTU2_ControlChannel Synopsis Prototype Description 1 2 Control an MTU channel bool R_MTU2_ControlChannel uint8_t data1 R_MTU2_ControlChannel_structure data2 Channel selection A pointer to the structure R_MTU2_ControlChannel_structure members uint8_t control_setting 1 Control settings uint16_t register_selection Register selection uint16_t TCNT_TCNTU_value Register value uint16_t TGRA_TCNTV_value Register value uint16_t TGRB_TCNTW_value Register value uint16_t TGRC_TGRU_value Register value uint16_t TGRD_TGR
202. ATA L NO DATA L NO DATA L NO DATA y Write the data into the EEPROM write eeprom data Clear the data storage area for i 0 i lt 20 i data _storage il 0x00 Reset the EEPROM sub address to 0 using polling R_IIC_MasterSend 0 PDL IIC _ STOP DISABLE EEPROM ADDRESS eeprom data_array 1 1 PDL_NO FUNC 0 de Read data from the EEPROM on channel 1 using the DMAC read eeprom data Prepare the next data R_DMAC Control 2 L DMAC SUSPEND PDL DMAC UPDATE DESTINATION PDL DMAC UPDATE COUNT L NO PTR D DL data_storage 5 0 1 DL NO DATA D D D L NO DATA W u o g a e ot L NO DATA L NO DATA R20UT0708EE0211 Rev 2 11 Page 5 80 Aug 01 2014 ztENESAS RX210 Group 5 Usage Examples Read data from the EEPROM on channel 1 using the DMAC read eeprom data static void write eeprom data void bus_busy true Send data to the EEPROM on channel 1 using the DMAC R_IIC_MasterSend 0 PDL IIC DMAC_ TRIGGER ENABLE EEPROM_ADDRESS PDL_NO_PTR 0 PDL NO FUNC 0 i while bus_busy true Wait for 5ms while the EEPROM updates R_CMT CreateOneShot 0 0 5E 3 PDL_NO_FUNC 0 de static void read eeprom data void bus_busy true Read data from the EEPROM on channel 1 using the DMAC R_IIC MasterReceive 0 PDL _IIC_DMAC TRIGGER ENABLE EEPR
203. B occurs RENESAS Page 4 157 RX210 Group Description 2 2 data3 Configure the output control If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Output control for pin TMOn 4 Library Reference PDL_TMR_OUTPUT_IGNORE_CM_A or PDL_TMR_OUTPUT_LOW_CM_Aor PDL_TMR_OUTPUT_HIGH_CM_Aor PDL_TMR_OUTPUT_INV_CM_A No change if a compare match A occurs O is output if a compare match A occurs 1 is output if a compare match A occurs The output toggles if a compare match A occurs PDL_TMR_OUTPUT_IGNORE_CM_B or PDL_TMR_OUTPUT_LOW_CM Bor PDL_TMR_OUTPUT_HIGH_CM_B or PDL_TMR_OUTPUT_INV_CM_B No change if a compare match B occurs O is output if a compare match B occurs 1 is output if a compare match B occurs The output toggles if a compare match B Return value occurs data4 The counter value data5 The compare match A value data6 The compare match B value func1 The function to be called when an overflow occurs Use PDL_NO_FUNC if not required func2 The function to be called when a Compare match A occurs Use PDL_NO_FUNC if not required func3 The function to be called when a Compare match B occurs Use PDL_NO_FUNC if not required data7 The interrupt priority level Select between 1 lowest priority and 15 hi
204. C Mode b7 b6 b5 b4 b3 b2 b1 bO Reception error detection RxD pin level Framing Parity Transmit P NA to SPI Overrun Async Mode Async Mode status 0 0 mode Only Only 0 No error 0 No error 0 No error 0 Active 0 Low 1 Detected 1 Detected 1 Detected 1 Idle 1 High Smart card mode b7 b6 b5 b4 b3 b2 b1 bO Error detection RxD pin Transmit status 0 Overrun Error signal Parity 0 level 0 No error 0 No error 0 No error 0 Active 0 Low 1 Detected 1 Detected 1 Detected 1 Idle 1 High IIC Mode b7 b1 bO ACK NACK flag This is updated every time an ACK or NACK is received 0 ACK received 1 NACK received data3 The storage location for the last byte that was received Specify PDL_NO_PTR if this information is not required data4 The storage location for the number of characters that are have been transmitted in the current transmission Specify PDL_NO_PTR if this information is not required NOTE If using DMAC or DTC specify PDL_NO_PTR as this information is not available data5 The storage location for the number of characters that are have been received in the current reception process Specify PDL_NO_PTR if this information is not required NOTE If using DMAC or DTC specify PDL_NO_PTR as this information is not available True if all parameters are valid and the operation completed false if a param
205. CL SDA NACK condition condition Arbitration lost Timeout b7 b6 b5 b4 b3 b2 b1 bO Transmission Mode Address detection 0 Not detected 1 detected 0 Active 0 Receive i Slave 1 Idle 1 Transmit SMBus host Device ID General call gt 1 0 data3 The address for storing the number of bytes that are have been transmitted in the current transfer Specify PDL_NO_PTR if this information is not required data4 The address for storing for the number of bytes that are have been received in the current transfer Specify PDL_NO_PTR if this information is not required True if all parameters are valid otherwise false Category C Reference R_IIC_Create Remarks The flags are not modified by this function The event detection flags are cleared when a new R20UT0708EE0211 Rev 2 11 Aug 01 2014 transfer is started Page 4 253 RENESAS RX210 Group 4 Library Reference Program example RPDL definitions include r pdl iic h RPDL device specific definitions include r pdl definitions h void func void uint32_t status_flags uintl6 t tx count Read the status of channel 0 R_IIC_GetStatus 0 amp status_flags amp tx_count PDL NO PTR R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS Page 4 254 RX210 Group 4 Library Reference 4 2 23 1 R_SPI_Set Synopsis Prototype
206. CTOR_TPU1_TGI1A E Compare match or Input capture A PDL_INTC_VECTOR_TPU1_TGI1B ee Compare match or Input capture B PDL_INTC_VECTOR_TPU1_TCI1V 1 Overflow PDL_INTC_VECTOR_TPU1_TCI1U i Underflow PDL_INTC_VECTOR_TPU2_TGI2A Timer Pulse Compare match or Input capture A PDL_INTC_VECTOR_TPU2_TGI2B Unit Channel Compare match or Input capture B PDL_INTC_VECTOR_TPU2_TCI2V 2 Overflow PDL_INTC_VECTOR_TPU2_TCI2U i Underflow PDL_INTC_VECTOR_TPU3_TGI3A Compare match or Input capture A PDL_INTC_VECTOR_TPU3_TGI3B Timer Pulse Compare match or Input capture B PDL_INTC_VECTOR_TPU3_TGI3C Unit Channel Compare match or Input capture C PDL_INTC_VECTOR_TPU3 TGI3D 3 Compare match or Input capture D PDL_INTC_VECTOR_TPU3_TCI3V Overflow PDL_INTC_VECTOR_TPU4_TGI4A Timer Pulse Compare match or Input capture A PDL_INTC_VECTOR_TPU4_TGI4B Unit Channel Compare match or Input capture B PDL_INTC_VECTOR_TPU4_TCI4V 4 i Overflow PDL_INTC_VECTOR_TPU4_TCI4U Underflow PDL_INTC_VECTOR_TPU5_TGI5A Timer Pulse Compare match or Input capture A PDL_INTC_VECTOR_TPU5_TGI5B Unit Channel Compare match or Input capture B PDL_INTC_VECTOR_TPU5_TCI5V 5 Overflow PDL_INTC_VECTOR_TPU5_TCI5U i Underflow PDL_INTC_VECTOR_OEI1 Port Output Input level sampling or output level PDL_INTC_VECTOR_OEI2 Enable comparison detection PDL_INTC_VECTOR_CMIAO 8 bit timer Compare match A PDL_INTC_VECTOR_CMIBO TMR Compare match B PDL_INTC_VECTOR_OVIO channel 0 Overflow PDL_INTC_VECTOR_CMIA1 8 bit timer Compare
207. CV 2tENESAS Valid between 0 and 15 Page 4 85 RX210 Group Description 2 2 Return value Category Reference Remarks R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference data4 The number of write recovery cycles WRCV Valid between 0 and 15 data5 The number of wait cycles used for second and subsequent accesses during a page read sequence CSPRWAIT Valid between 0 and 7 data6 The number of wait cycles used for second and subsequent accesses during a page write sequence CSPWWAIT Valid between 0 and 7 data7 The number of wait cycles for the first access during a normal or page read sequence CSRWAIT Valid between 0 and 31 data8 The number of wait cycles for the first access during a normal or page write sequence CSWWAIT Valid between 0 and 31 data9 The number of cycles that the CS signal is left asserted after the read strobe is negated CSROFF Valid between 0 and 7 data10 The number of cycles that the CS signal is left asserted after the write strobe is negated CSWOFF Valid between 0 and 7 data11 The number of cycles that the data output is left asserted after the write strobe is negated WDOFF Valid between 0 and 7 data12 The number of wait cycles to be inserted into a multiplexed address output cycle AWAIT Valid between 0 and 3 data13 The number of cycles before the read strobe is asser
208. C_TRIGGER_ENABLE TGRA compare match or input capture PDL_MTU2_TGRB_DTC_TRIGGER_DISABLE or PDL_MTU2_TGRB_DTC_TRIGGER_ENABLE TGRB compare match or input capture PDL_MTU2_TGRC_DTC_TRIGGER_DISABLE or PDL_MTU2_TGRC_DTC_TRIGGER_ENABLE TGRC compare match or input capture Valid for n 0 3 and 4 PDL_MTU2_TGRD_DTC_TRIGGER_DISABLE or PDL_MTU2_TGRD_DTC_TRIGGER ENABLE TGRD compare match or input capture Valid for n 0 3 and 4 PDL_MTU2_TCIV_DTC_TRIGGER_DISABLE or PDL_MTU2_TCIV_DTC_ TRIGGER ENABLE Counter overflow or underflow Valid for n 4 DTC event trigger control Valid for n 5 PDL_MTU2_TGRU_DTC_TRIGGER_DISABLE or PDL_MTU2 TGRU_DTC TRIGGER ENABLE TGRU compare match or input capture PDL_MTU2_TGRV_DTC_TRIGGER_DISABLE or PDL_MTU2_TGRV_DTC_TRIGGER_ENABLE TGRV compare match or input capture PDL_MTU2_TGRW_DTC_TRIGGER_DISABLE or PDL_MTU2_TGRW_DTC_TRIGGER_ENABLE TGRW compare match or input capture counter_operation Configure the counter operation If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults TCNT counter clock source selection Valid for n O to 4 unless stated otherwise Not effective for n 1 and 2 in Phase Counting Mode PDL_MTU2_CLK_PCLK_DIV_1 or PDL_MTU2_CLK_PCLK_DIV_4 or PDL_MTU2_CLK_PCLK_DIV
209. Capture DATA Capture DATA Periodic sleep mode if tru bEntersl bEnterSl pMode pMode true ENT Sdsd sdsd dsd r n gt gt gt gt gt gt gt gt gt gt gt gt amp flags 20 16 12 8 4 0 CHANNEL PDL NO DATA buffer Alarm in another 10 seconds PDL NO FUNC 5 Usage Examples Figure 5 25 Example of using RTC is used and wake up from sleep mode R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS Page 5 46 RX210 Group 5 Usage Examples 2 Wake up from deep standby mode Figure 5 26 shows an example of using the RTC wake up from deep standby mode The HOCO is used as system and and sub clock as RTC count source include lt stdio h gt include lt string h gt PDL functions include r pdl cgc h include r pal lpc h include r pdl cmth include r pdl mcu h include r pdl _rtc h include r pdl sci h PDL device specific definitions include r pdl definitions h define RSK_SCI CHANNEL 0 static void SetClocks void static void Alarm handler void volatile bool bDeepStdbyExit false volatile bool bDeepStdbyEnter false void main void uint32 t status flags uintl6 t status 0 uint8 t flags uint32 t time uint32 t date uint8 t buffer 50 Sets system clock SetClocks If this is us exiting from deep sleep if SYSTEM RSTSRO BIT D
210. Channel selection Channel configuration and Target Station ID Data start address Data count Callback function Transmit data on the specified serial channel data1 Select channel SCIn where n 0 to 12 data2 Control options The default options are shown in bold Specify PDL_NO_DATA to use the defaults e DMAC DTC trigger control PDL_SCI_DMAC_DTC_TRIGGER_DISABLE or PDL_SCI_DMAC_TRIGGER_ENABLE or PDL_SCI_DTC_TRIGGER_ENABLE Disable or enable activation of the DMAC or DTC when a data byte is transmitted e _ID transmission control valid only in Multi processor mode Transmit the upper byte as the ID byte dd ee re The valid ID range is 0 to 255 data3 The start address of the data to be sent Specify PDL_NO_PTR for the ID cycle in Multi processor mode If the DMAC or DTC shall be used to transfer the data specify PDL_NO_PTR data4 For sending binary data set this to the number of bytes to be sent The valid range is 1 to 65535 Set this to 0 for transmission of a null terminated character string For the ID cycle in Multi processor mode specify 0 If the DMAC or DTC shall be used to transfer the data specify PDL_NO_DATA func Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Use R_SCI_Control to terminate this operation early R_SCI_GetStatus can be used to find out how many characters have been transmitted
211. D Cleared by TGRD compare match or input capture Valid for n 0 3 and 4 R20UT0708EE0211 Rev 2 11 Aug 01 2014 2tENESAS Page 4 126 RX210 Group 4 Library Reference Description 3 9 e Counter clock source selection Valid for n 5 R20UT0708EE0211 Rev 2 11 Aug 01 2014 PDL_MTU2_CLKU_PCLK_DIV_1 or PDL_MTU2_CLKU_PCLK_DIV_4 or PDL_MTU2_CLKU_PCLK_DIV_16 or PDL_MTU2 CLKU_PCLK DIV 64 Counter TCNTU is supplied by the internal clock signal PCLKB 1 4 16 or 64 PDL_MTU2_CLKV_PCLK_DIV_1 or PDL_MTU2_CLKV_PCLK_DIV_4 or PDL_MTU2_CLKV_PCLK_DIV_16 or PDL_MTU2_CLKV_PCLK_DIV_64 Counter TCNTV is supplied by the internal clock signal PCLKB 1 4 16 or 64 PDL_MTU2_CLKW_PCLK_DIV_1 or PDL_MTU2_CLKW_PCLK_DIV_4 or PDL_MTU2_CLKW_PCLK_DIV_16 or PDL MTU2 CLKW_PCLK_DIV_64 Counter TCNTW is supplied by the internal clock signal PCLKB 1 4 16 or 64 e Counter clearing U V and W counters Valid for n 5 PDL_MTU2_CLEAR_TGRU_DISABLE or PDL_MTU2_CLEAR_TGRU_ENABLE Disable or enable clearing of TCNTU by TGRU compare match or input capture PDL_MTU2_CLEAR_TGRV_DISABLE or PDL_MTU2_CLEAR_TGRV_ENABLE Disable or enable clearing of TCNTV by TGRV compare match or input capture PDL_MTU2_CLEAR_TGRW_DISABLE or PDL_MTU2_CLEAR_TGRW_ENABLE Disable or enable clearing of TCNTW by TGRW compare match or input capture
212. D1 R_IO_PORT Set PDL IO PORT 1 5 PDL IO PORT OUTPUT Set the DIC options R_DTC_ Set PDL NO DATA dtc vector table Configure the DTC for IRQI1 R_DTC Create PDL DTC BLOCK PDL DTC DESTINATION PDL DTC SOURCE ADDRESS PLUS PDL DTC DESTINATION ADDRESS PLUS PDL DTC SIZE 8 PDL DTC_IRQ COMPLETE PDL DTC _TRIGGER_IRQI dtc_irgl transfer data source string 1 destination string 1 1 uint8 t strlen char source string 1 Set IRQ1 pin to P31 R20UT0708EE0211 Rev 2 11 Page 5 21 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples ExtInterrupt PDL INTC IRQ1 PORT 3 1 the SW1 IRQ1 interrupt TC CreateExtInterrupt PDL INTC_IRQI1 PDL INTC FALLING PDL_INTC_DTC_TRIGG IRQ1 handler 7 Start the DIC R_ DTC Control PDL DTC START PDL NO PTR PDL NO PTR PDL NO PTR PDL NO DATA PDL NO DATA 7 while 1 void IRQ handler void uintl6 t StatusValue uint32 t SourceAddr uint32 t DestAddr uintl6 t TransferCount Read the status and current source address for the IRQ1 transfer R_DTC_GetStatus dtc_irgl transfer data StatusValue amp SourceAddr amp DestAddr TransferCount PDL_NO_DATA Invert the port pin R IO PORT Modify PDL IO PORT 1 5 PDL IO PORT XOR BR
213. DC 12 not_used Becomes define RPDL ADC 12 not_used The file Interrupt_INTC c must be included 7 Peripherals that are not supported by RPDL The file Interrupt_not_RPDL c also contains handlers for the peripherals that are not supported by RPDL This allows the user to add handler code for these peripherals while supporting the Fast Interrupt feature see R_INTC_CreateFastInterrupt R20UT0708EE0211 Rev 2 11 Page 1 8 Aug 01 2014 RENESAS RX210 Group 1 Introduction 8 Avoid conflicts with standard project files If the files intprg c or vecttbl c are included in the project remove or exclude them a Removal Use the key sequence Alt P R to open the Remove Project Files window Select the files and click on Remove Remove Project Files Project files Interrupt_DMAC c DX rpdl_lib_te A X rpdl_lib_te Cancel X rpdl_lib_te X rpdl_lib_te Remove XArpdi_lib_te RArpdl_lib_te X pdl_lib_te Remove All lt rpdl_lib_te XArpdl_lib_te X rpdl_lib_te X rpdl_lib_te X rpdl_ lib_ te rpdl_lib_te t_pdl_configuration c Pound lib_te resetprg c X rpdl_lib_te rpdl_lib_test c PArpdl_lib_te sbrk c Arpdl_lib_te 7 v R20UT0708EE0211 Rev 2 11 Page 1 9 Aug 01 2014 RENESAS RX210 Group b Exclusion Select the two files and use the key sequence Alt B to exclude them is rpdl_lib_test High performance Embedded Workshop File Edit View Project Build Debug Setup T
214. DELAY_7 or PDL_SPI_NEXT_DELAY_8 The number of bit clock periods plus two cycles of the peripheral clock between the end of one frame and the start of the next frame Ignored in Slave mode ENESAS Page 4 257 RX210 Group 4 Library Reference Description 3 3 Return value Category Reference data5 The format must be either The maximum required bit rate Or b31 b30 to b8 b7 b0 1 0 The SPBR register value Ifonly Slave mode will be used specify PDL_NO_DATA True if all parameters are valid otherwise false SPI R_CGC_Set R_SPI_Set R_SPI_Command Remarks Program example e Function R_CGC_Set must be called with the current clock source selected before using this function e Function R_SPI_Set must be called before any use of this function The actual bit rate will be reduced if division gt 1 is specified in R_SPI_Command RPDL definitions include r pdl spi h RPDL device specific definitions tinclude r pdl definitions h void func void Configure SPI channel 0 R_SPI_ Create 0 F PDL SPI MODE SPI MASTER PDL SPI PIN SSLO_LOW PDL SPI FRAME 1 1 PDI 2 L NO DATA E6 R20UT0708EE0211 Rev 2 11 Page 4 258 Aug 01 2014 2tENESAS RX210 Group 4 Library Reference 3 R_SPI_ Destroy Synopsis
215. DL CGC BCLK DIV 2 50E6 25E6 25E6 25E6 25E6 25E6 PDL_NO_DATA Configure the LOCO settings R CGC Set PDL CGC CLK LOCO DL CGC _BCLK_ DISABLE 25E3 25E3 DL_NO_DATA 2 2 D D 5E3 5E3 L NO DATA DORR DPR YD L NO DATA R20UT0708EE0211 Rev 2 11 Page 5 100 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples Allow 100us for the main clock to stabilise R_CMT CreateOneShot 0 PDL NO DATA 100E 6 PDL_NO_FUNC 0 Select the PLL as the clock source R CGC Control PDL CGC CLK MAIN PDL NO DATA PDL NO DATA R_IO PORT Set PDL IO PORT 1 4 PDL IO PORT OUTPUT R_IO PORT Set PDL IO PORT 1 5 PDL IO PORT OUTPUT R IO PORT Set PDL IO PORT 1 6 PDL IO PORT OUTPUT r R IO PORT Write PDL IO PORT 1 4 1 off LEDO R IO PORT Write PDL IO PORT_1 5 0 on LED1 R_IO PORT Write PDL IO PORT 1 6 0 on LED2 Monitoring Comparison A channel 0 Results R_CPA_Create 0 PDL NO DATA PDL NO FUNC 0 y get status LVDiDET LVDiMON do R_CPA _GetStatus amp FlagsStatus if FlagsStatus amp 0x01 0x01 break while 1 comparator A channel 1 interrupts using Digital Filter Enable the LOCO clock R_CGC_ControlAll PDL_CGC_CLK LOCO PDL_CGC_LOCO_ENABLE PDL_NO_DATA Configure the NMI pin Non Maskable Interrupt for Comparator A channel 1
216. DL IO PORT XOR L y Stop all channels R_DMAC Control 0 U L DMAC SUSPEND L NO PTR L NO PTR L NO DATA L NO DATA L NO DATA L NO DATA L NO DATA mM MO YY U U He ey at en eee ee y Stop channel 0 R_DMAC Destroy 0 Figure 5 10 Two examples of DMAC use R20UT0708EE0211 Rev 2 11 Page 5 20 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 9 Data Transfer Controller 5 9 1 Block transfer mode Figure 5 11 shows an example of Data Transfer Controller usage with a single block transfer Peripheral driver function prototypes include r padl dtc h include r pdl cgc h include r pdl io port h include r pdl_intc h RPDL device specific definitions include r pdl definitions h Required for this example include lt string h gt Reserve an area for the DTC vector table pragma address dtc vector table 0x00001000 uint32 t dtc vector table 256 Reserve 16 bytes for the IRO1l triggered transfer data area uint32 t dtc_irgl transfer data 4 Data source and destination declarations const char source string 1 Renesas RX210 volatile uint8 t destination string 1 Callback function prototype void IRQ handler void void main void Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG IPL 0 y Enable control of LE
217. DL_INTC_VECTOR_RXI12 Data received PDL_INTC_VECTOR_TXI12 Start of next data transfer PDL_INTC_VECTOR_TEI12 SCI channel End of data transfer PDL_INTC_ VECTOR SCIXO 12 Extended serial mode Break field PDL_INTC VECTOR SCIX1 Extended serial mode Control field PDL_INTC_VECTOR_SCIX2 Extended serial mode Bus collision PDL_INTC_VECTOR_SCIX3 Extended serial mode Valid edge R20UT0708EE0211 Rev 2 11 Page 4 20 Aug 01 2014 RENESAS 4 Library Reference RX210 Group 4 Library Reference Description 4 3 PDL_INTC_VECTOR_ICEEIO 12C bus Transfer error or event generation PDL_INTC_VECTOR_ICRXIO interfac Data received PDL_INTC_VECTOR_ICTXIO channel 0 Start of next data transfer PDL_INTC_VECTOR_ICTEIO End of data transfer Return value Category Reference Remarks Program example R20UT0708EE0211 Rev 2 11 Aug 01 2014 True Interrupt control The fast interrupt
218. DO_P20 or a PDL_SCI_PIN_SCIO_TXD0O_P32 PDL_SCI_PIN_SCIO_SMOSIO_P20 or PDL_SCI_PIN_SCIO_SMOSIO_P32 on SNOSI PDL_SCI_PIN_SCIO_SSDAO_P20 or SSA PDL_SCI_PIN_SCIO_SSDAO_P32 PDL_SCI_PIN_SCIO_SCKO_P22 or pea PDL_SCI_PIN_SCIO_SCK0_P34 PDL_SCI_PIN_SCIO_CTSO_P23 or a PDL_SCI_PIN SCIO_CTSO_PJ3 PDL_SCI_PIN_SCIO_RTSO_P23 or mE PDL_SCI_PIN_SCIO_RTSO_PJ3 PDL_SCI_PIN_SCIO_SS0_P23 or ES PDL_SCI_PIN_SCIO_SS0_PJ3 Page 4 207 RX210 Group Description 2 6 Valid when n 1 4 Library Reference R20UT0708EE0211 Rev 2 11 Aug 01 2014 PDL SCI PIN_SCI1 RXD1 P15 or ee PDL SCI PIN SCI1_RXD1 P30 PDL_SCI_PIN_SCI1_SMISO1 P15 or PDL SCI PIN SCI1_ SMISO1 P30 SMISO1 PDL_SCI_PIN_SCI1_SSCL1_P15 or eae PDL_SCI_PIN SCI1_SSCL1 P30 PDL SCI PIN SCI1_TXD1_P16 or PDL SCI PIN SCI1_TXD1 P26 PDL_SCI_PIN_SCI1_SMOSI1_P16 or ie PDL_SCI_PIN_SCI1_SMOSI1_P26 PDL_SCI_PIN SCI1_SSDA1 P16 or Se aan PDL SCI PIN SCI1_SSDA1 P26 PDL_SCI_PIN SCI1_SCK1_P17 or a PDL_SCI_PIN_SCI1_SCK1_P27 PDL SCI PIN SCI1_CTS1 P14 or ae PDL SCI PIN SCI1 CTS1_ P31 PDL SCI PIN SCI1_RTS1 P14 or PDL_SCI_PIN SCI1_RTS1 P31 PDL SCI PIN SCI1_SS1_P14 or PDL SCI PIN SCI1_SS1 P31 Valid when n 2 PDL SCI PIN SCI2_RXD2 P12 or os
219. D_DISABLE or PDL_ADC_12_CH_SAMPLE_AND HOLD ENABLE Enable or disable sample and hold circuit For channels 0 1 and 2 only Sampling time calculation PDL_ADC_12_CH_ADSSTR_CALCULATE or PDL_ADC_12_CH_ADSSTR_SPECIFY Select whether parameter data4 is used to calculate the ADSSTR value or contains the value to be stored in register ADSSTR data4 The data to be used for the sampling state register value calculations If PDL_ADC_12_CH_ADSSTR_SPECIFY is selected for data3 the value should not be less than 12 or more then 255 Data use Parameter type The timer period in seconds or double The value to be put in register ADSSTR uint8_t True if a valid unit is selected otherwise false 12 bit ADC R_ADC 12 CreateUnit R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 277 RENESAS RX210 Group 4 Library Reference Remarks Program example If analog channels are used as the input sources call this function after calling R_ADC_12_CreateUnit Function R_CGC_Set must be called with the current clock source selected before using this function Make sure no more than 1 channel is configured with the parameter of PDL_ADC_12_CH_DOUBLE_TRIGGER_ENABLE Channels 8 15 share the same ADSSTR register Once set sampling time for each of them the same setting applies to all the other channels A later setting overwrites the previous one If AVCCO is less than 2 7V ch
220. ELAY or Select no action a reset PDL_LVD_INTERRUPT_NMI_DETECT_RISE or on low voltage detection PDL_LVD_INTERRUPT_NMI_DETECT_FALL or or an interrupt when a PDL_LVD_INTERRUPT_NMI_DETECT_RISE_AND_FALL or specified voltage event is PDL_LVD_INTERRUPT_MI_DETECT_RISE or detected PDL_LVD_INTERRUPT_MI_DETECT_FALL or PDL_LVD_INTERRUPT_MI_DETECT_RISE_AND FALL e Digital Filter PDL_LVD_FILTER_DISABLE or PDL_LVD_FILTER_LOCO_DIV_1 or PDL_LVD_FILTER_LOCO_DIV_2 or Configure the digital filter PDL_LVD_FILTER_LOCO_DIV_4 or PDL_LVD _FILTER_LOCO DIV_8 Pin selection PDL_LVD_VDET2_PIN_VCC or Monitor VCC or the PDL_LVD_VDET2_PIN_CMPA2 CMPAZ pin data4 Monitor 2 voltage detection level Specify PDL_NO_DATA if not required PDL_LVD_VOLTAGE_LEVEL_415 or PDL_LVD_VOLTAGE_LEVEL_400 or PDL_LVD_VOLTAGE_LEVEL_385 or PDL_LVD_VOLTAGE_LEVEL_370 or PDL_LVD_VOLTAGE_LEVEL_355 or PDL_LVD_VOLTAGE_LEVEL_340 or PDL_LVD_VOLTAGE_LEVEL_325 or PDL_LVD_VOLTAGE_LEVEL_310 or PDL_LVD_VOLTAGE_LEVEL_295 or PDL_LVD_VOLTAGE_LEVEL_280 or PDL_LVD_VOLTAGE_LEVEL_265 or PDL_LVD_VOLTAGE_LEVEL_250 or PDL_LVD_VOLTAGE_LEVEL_235 or PDL_LVD_VOLTAGE_LEVEL_220 or PDL_LVD_VOLTAGE_LEVEL_205 or PDL_LVD_VOLTAGE_LEVEL_190 Set the voltage detection level For example PDL_LVD_VOLTAGE_LEVEL_415 4 15V Required only if the monitor is enabled and the VCC pin is selected func1 The function to be called when a Monitor 1 ma
221. ENABLE PDL _NO_DATA OxFF114200 Automatic day of week 11 42 00 0x20100916 16 Sep 2010 PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA 0x00120000 Alarm at 12 noon PDL_NO_DATA alarm function 15 PDL NO FUNC PDL NO DATA i R20UT0708EE0211 Rev 2 11 Page 4 189 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 2 R_RTC_Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example Shut down the Real time clock bool R_RTC_Destroy void Stop the RTC counter and disable the sub clock to the RTC True RTC None This module is not available on the 48 pin package RPDL definitions tinclude r pdi _rtc h RPDL device specific definitions tinclude r pdl definitions h void func void Shutdown the RTC R_RTC_Destroy R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 190 RENESAS RX210 Group 3 R_RTC_Control Synopsis Prototype bool R_RTC_Control uint32_t data1 uint16_t data2 uint32_t data3 uint32_t data4 uint32_t data5 uint32_t data6 uint16_t data7 uint8_t data8 uint8_t data9 uint8_t data10 uint16_t data11 4 Library Reference Modify the Real time clock operation Control selection Update selection Current time Current date Alarm time 1 Alarm date
222. ER LOCO DIV 1 PDL CPA INTERRUPT RESET ENABLBE PDL CPA IRQ CROSS CVREFA PDL CPA MASKABLE INTERRUPT CPAi handler 7 Page 4 289 RENESAS RX210 Group 4 Library Reference 2 R_CPA_Control Synopsis Prototype Description Return value Category Reference Remarks Program example Control the Comparator A module bool R_CPA_Control uint8_t data1 1 Comparator selection uint8_t data2 II Settings for Comparator Control Comparator A1 or A2 data1 The comparator A channel number n where n 0 to 1 data2 Disable the Comparator A e Comparator circuit option Valid for interrupt and reset mode PDL_CPA_LVD_CIRCUIT_DISABLE Disable comparator A circuit True if all parameters are valid and exclusive otherwise false Comparator A R_CPA_Create R_LVD_Create and R_LVD_Control This function should not be called before R_CPA_Create Do not use VDET1 module and Comparator A channel 0 VDET2 and comparator A channel 1 at same time because they share the same registers See R_LVD_Create and R_LVD_Control Do not use Comparator Ain deep software standby mode with PDL_LPC_DEEPCUT_ENABLE The LVDi reset or LVDi non maskable interrupt should not be generated during flash memory programming erasure RPDL definitions include r pdl cpa h RPDL de
223. ER_TGIA1 or PDL_DTC_TRIGGER_TGIA2 or PDL_DTC_TRIGGER_TGIA3 or PDL_DTC TRIGGER _TGIA4 or Compare match or input capture A on MTU channel n n 0 to 4 PDL_DTC_TRIGGER_TGIBO or PDL_DTC_ TRIGGER TGIB1 or PDL_DTC TRIGGER TGIB2 or PDL_DTC TRIGGER TGIB3 or PDL_DTC_TRIGGER_TGIB4 or Compare match or input capture B on MTU channel n n 0 to 4 PDL_DTC_TRIGGER_TGICO or PDL_DTC_TRIGGER_TGIC3 or PDL_DTC_TRIGGER_TGICA4 or Compare match or input capture C on MTU channel n n 0 3 or 4 PDL_DTC_TRIGGER_TGIDO or PDL_DTC_TRIGGER_TGID3 or PDL_DTC_TRIGGER_TGID4 or Compare match or input capture D on MTU channel n n 0 3 or 4 PDL_DTC_TRIGGER_TGIU5 or Compare match or input capture U on MTU channel 5 PDL_DTC_TRIGGER_TGIV5 or Compare match or input capture V on MTU channel 5 PDL_DTC_TRIGGER_TGIW5 or Compare match or input capture W on MTU channel 5 PDL_DTC_TRIGGER_TCIV4 or Counter over or underflow on MTU channel 4 PDL_DTC_TRIGGER_TPU_TGIOA or PDL_DTC TRIGGER TPU_TGIOB or PDL_DTC_TRIGGER_TPU_TGIOC or PDL_DTC_TRIGGER_TPU_TGIOD or Input capture compare match signals on TPU channel 0 PDL_DTC_TRIGGER_TPU_TGI1A or PDL_DTC TRIGGER TPU_TGI1B or Input capture compare match signals on TPU channel 1 PDL_DTC TRIGGER TPU_TGI2A
224. ETECT_RISE or detected PDL_LVD_INTERRUPT_MI_DETECT_FALL or PDL_LVD_INTERRUPT_MI_DETECT_RISE_AND FALL e Digital Filter PDL_LVD_FILTER_DISABLE or PDL_LVD_FILTER_LOCO_DIV_1 or PDL_LVD_FILTER_LOCO_DIV_2 or Configure the digital filter PDL_LVD_FILTER_LOCO_DIV_4 or PDL_LVD FILTER_LOCO DIV_8 data2 Monitor 1 voltage detection level Specify PDL_NO_DATA if not required PDL_LVD_VOLTAGE_LEVEL_415 or PDL_LVD_VOLTAGE_LEVEL_400 or PDL_LVD_VOLTAGE_LEVEL_385 or PDL_LVD_VOLTAGE_LEVEL_370 or PDL_LVD_VOLTAGE_LEVEL_355 or PDL_LVD_VOLTAGE_LEVEL_340 or Set the voltage detection level PDL_LVD_VOLTAGE_LEVEL_325 or PDL_LVD_VOLTAGE_LEVEL_310 or For example PDL_LVD_VOLTAGE_LEVEL_415 PDL_LVD_VOLTAGE_LEVEL_295 or 4 15V PDL_LVD_VOLTAGE_LEVEL_280 or PDL_LVD_VOLTAGE_LEVEL_265 or Required only if the monitor is enabled PDL_LVD_VOLTAGE_LEVEL_250 or PDL_LVD_VOLTAGE_LEVEL_235 or PDL_LVD_VOLTAGE_LEVEL_220 or PDL_LVD_VOLTAGE_LEVEL_205 or PDL_LVD_VOLTAGE_LEVEL_190 R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS ee RX210 Group Description 2 2 R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference data3 Monitor 2 voltage detection configuration If the monitor is not required specify PDL_NO_DATA otherwise use to separate each selection Operation PDL_LVD_MONITOR_ONLY or PDL_LVD_RESET_NEGATION_VCC_MORE_THAN_VDET or PDL_LVD_RESET_NEGATION_AFTER_D
225. Event link Interrupt 1 PDL_INTC_VECTOR_ELSR19I controller Interrupt 2 PDL_INTC_VECTOR TGIAO PDL_INTC_VECTOR TGIBO PDL_INTC_VECTOR_TGICO PDL_INTC_VECTOR_TGIDO PDL_INTC_VECTOR TCIVO PDL_INTC_ VECTOR TGIEO PDL_INTC_VECTOR_TGIFO Multi function Timer Pulse Unit channel 0 Compare match or Input capture A Compare match or Input capture B Compare match or Input capture C Compare match or Input capture D Overflow Compare match E Compare match F PDL_INTC_VECTOR_TGIA1 PDL_INTC_VECTOR TGIB1 PDL_INTC_ VECTOR TCIV1 PDL_INTC_ VECTOR TCIU1 Multi function Timer Pulse Unit channel 1 Compare match or Input capture A Compare match or Input capture B Overflow Underflow PDL_INTC_VECTOR_TGIA2 Multi function Compare match or Input capture A PDL_INTC_VECTOR_TGIB2 Timer Pulse Compare match or Input capture B PDL_INTC_VECTOR_TCIV2 Unit channel Overflow PDL_INTC_VECTOR_TCIU2 2 Underflow R20UTO708EE0211 Rev 2 11 Page 4 18 Aug 01 2014 RENESAS RX210 Group 4 Library Reference
226. Frequency of System clock ICLK 32768 Frequency of Peripheral B clock PCLKA 32768 Frequency of Peripheral B clock PCLKB 32768 Frequency of Flash memory clock FCLK PDL _NO DATA Frequency of External bus clock PDL_CGC_SUB 2 Sub clock stabilization time i Wait for the Subclock stabilisation time 2 seconds minimum NOTE As curently running from the LOCO the R_CMT CreateOneShot max time limit is gt 2 Secs R20UT0708EE0211 Rev 2 11 Page 5 45 Aug 01 2014 RENESAS RX210 Group R_CMT CreateOneShot 0 PDL NO DATA 2 0 PDL_NO_FUNC 0 Select the HOCO as the clock source R_CGC Control PDL_CGC_CLK_HOCO PDL_NO_DATA PDL CGC RTC TO BE USED y void Alarm handler void uint8 t flags uint32 t time uint32 t date uint8 t buffer 50 Read time R_RTC_Read PDL_RTC_READ_CURRI sprintf char buffer Time int time amp OxF00000 int time Ox0F0000 int time 0x00F000 int time amp 0x000F00 int time amp 0x0000F0 int time 0x00000F R_SCI_Send RSK_SCI_ Configure the clock R_RTC Control Ee hg to T ae E BSggggerT gggs W E i L NO DATA L RTC UPDATE ALARM TIME T enter into L NO DATA L NO DATA ime 0x10 DATA DATA Error Adjust DATA Capture DATA
227. G IPR TMR3 OVI PDL_INTC_ REG IPR ELC ELSR18I PDL_INTC_REG_ IPR DMAC_DMACOI PDL_INTC_ REG _IPR_ ELC ELSR19I PDL_INTC_REG_ IPR DMAC_DMAC 1I PDL_INTC_REG_IPR_MTUO_TGIA PDL_INTC_REG_IPR_DMAC_DMAC2I PDL INTC REG IPR MTUO TGIB PDL_INTC REG IPR DMAC DMACQ3I PDL INTC REG IPR MTUO TGIC PDL INTC REG IPR _IICO EEI PDL_INTC_REG_IPR_MTUO_TGID PDL_INTC_REG_IPR_IICO_RXI PDL_INTC_ REG _IPR_MTUO_TCIV PDL_INTC_REG_IPR_IICO_TXI PDL_INTC_REG_IPR_MTUO_TGIE PDL_INTC_REG_IPR_IICO_TEI PDL INTC REG IPR MTUO TGIF PDL_INTC_REG_IPR_SCIO_ERI PDL_INTC_REG_IPR_SCI7_ERI PDL_INTC_REG_IPR_SCIO_RXI PDL_INTC_REG_IPR_SCI7_RXI PDL_INTC_REG_IPR_SCIO TXI PDL_INTC_REG_IPR_SCI7_TXI PDL INTC REG IPR SCIO TEI PDL INTC REG IPR _SCI7 TEI PDL INTC REG IPR _SCI1 ERI PDL INTC REG IPR _SCI8 ERI PDL_INTC_REG_IPR_SCI1_RXI PDL_INTC_REG_IPR_SCI8_RXI PDL_INTC_REG_IPR_SCI1_TXI PDL_INTC_REG_IPR_SCI8_TXI PDL_INTC_REG_IPR_SCI1_TEI PDL_INTC REG _IPR_SCI8 TEI PDL_INTC REG IPR _SCI2 ERI PDL INTC REG IPR SCI9 ERI PDL_INTC REG IPR SCI2 RXI PDL_ INTC REG IPR SCI9 RXI PDL_INTC_REG_IPR_SCI2_TXI PDL_INTC_REG_IPR_SCI9 TXI PDL_INTC_REG_IPR_SCI2_TEI PDL_INTC_REG_IPR_SCI9 TEI PDL_INTC_REG_IPR_SCI3_ERI PDL_INTC_REG_IPR_SCI10_ERI PDL INTC REG IPR SCI3 RXI PDL INTC REG IPR SCI10 RXI PDL INTC REG IPR SCI3 TXI PDL_INTC REG IPR SCI10 TXI PDL_INTC REG IPR_SCI3 TEI PDL_INTC_REG_IPR_SCI10_ TEI PDL_INTC_ REG _IPR_SCIl4 ERI PDL_INTC_ REG _IPR_SCI11_ERI PDL_INTC REG _IPR_SCI4 RXI PDL_INTC_REG_IPR_SCI11_RXI PDL INTC REG IPR _SCI4 T
228. G IR MTU4 TCIV PDL_INTC REG IR CMT1 CMI PDL INTC REG IR MTU5 TGIU PDL_INTC_ REG _IR_CMT2_ CMI PDL_INTC_ REG _IR_MTU5 TGIV PDL_INTC_ REG _IR_CMT3_ CMI PDL_INTC_ REG _IR_MTU5 TGIW PDL_INTC_REG_IR_CAC_FERRF PDL_INTC_ REG IR POE OEl1 PDL INTC REG IR CAC MENDF PDL INTC REG IR POE OEl2 PDL_INTC REG IR CAC OVFF PDL_INTC REG IR TMRO CMIA PDL_INTC_ REG _IR_SPIO SPEI PDL_INTC_ REG _IR_TMRO CMIB PDL_INTC_ REG _IR_ SPIO SPRI PDL_INTC_ REG _IR_TMRO OVI PDL_INTC REG _IR_SPIO SPTI PDL_INTC_ REG _IR_TMR1_CMIA PDL_INTC REG IR SPIO SPII PDL INTC REG IR TMR1 CMIB PDL_INTC REG IR DOC DOPCF PDL INTC REG IR TMR1 OVI PDL_INTC_REG_IR_CMPB_CMPBO PDL_INTC_REG_IR_TMR2_CMIA PDL_INTC_ REG _IR_CMPB_CMPB1 PDL_INTC_REG_IR_TMR2_CMIB PDL_INTC_REG_IR_RTC_COUNTUP PDL_INTC_REG_IR_TMR2_OVI PDL INTC REG IR ICU IRQO PDL_INTC REG IR TMR3 CMIA PDL_INTC REG IR ICU IRQ1 PDL_INTC REG IR TMR3 CMIB PDL_INTC_ REG _IR_ICU_ IRQ2 PDL_INTC_ REG _IR_TMR3_ OVI PDL_INTC_ REG _IR_ICU_ IRQ3 PDL_INTC_REG IR DMAC_DMACOI PDL_INTC REG _IR_ICU IRQ4 PDL_INTC_REG IR DMAC DMAC1I PDL_INTC REG IR_ICU IRQ5 PDL INTC REG IR DMAC DMAC2I PDL_INTC REG IR_ICU IRQ6 PDL INTC REG IR DMAC DMAC3I PDL_INTC REG _IR_ICU_ IRQ7 PDL_INTC_ REG _IR_SCIO ERI PDL_INTC REG _IR_LVD LVD1 PDL_INTC_ REG _IR_SCIO RXI PDL_INTC_ REG _IR_LVD LVD2 PDL_INTC_ REG _IR_SCIO TXI PDL_INTC REG IR CMPA_CMPA1 PDL INTC REG IR SCIO TEI PDL_INTC_REG_IR_CMPA_CMPA2 PDL_INTC_REG_IR_SCI1_ERI PDL_INTC_REG_IR_RTC_ALM PDL_INTC_REG_IR_SCI1_RXI PDL_INTC_REG_IR_RTC_
229. GE or PDL_TPU_B_IC_FALLING_EDGE or PDL_TPU_B_IC_BOTH_EDGES or Input capture at TIOCBn or TIOCAn rising edge Input capture at TIOCBn or TIOCAn falling edge Input capture at TIOCBn or TIOCAn both edges See below for TIOCBn or TIOCAn pin selection PDL_TPU_B_IC_TPU_COUNT_CLK or Input capture at TPU n 1 count clock count up or count down Invalid if TPU n 1 uses PCLK 1 Valid for n O and 3 PDL_TPU_B_IC_TPU_CM_IC Input capture at TPU n 1 TGRC compare match or input compare Valid for n 1 and 4 TGRB input capture input selection PDL_TPU_B_IC_TIOCB or PDL_TPU_B_IC TIOCA Input capture using pin TIOCBn or TIOCAn 2tENESAS Page 4 307 RX210 Group Description 4 5 R20UT0708EE0211 Rev 2 11 Aug 01 2014 data5 4 Library Reference Configure the operation for general registers C and D valid for n 0 and 3 If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Input capture output compare control for register TGRC PDL_TPU_C_OC_DISABLED or PDL_TPU_C_OC_LOW or PDL_TPU_C_OC_LOW_CM_HIGH or PDL_TPU_C_OC_LOW_CM_INVo PDL_TPU_C_OC_HIGH_CM_LOW or PDL_TPU_C_OC_HIGH or PDL_TPU_C_OC_HIGH_CM_INV or TIOCCn output disabled TIOCCn output low TIOCCn initial output low goes high at compare match TIOCCH initia
230. HOCO_LVD or Power is supplied to flash memory but not supplied to HOCO in software standby mode The voltage detection circuit LVD is stopped and the power consumption reduction function by the power on reset circuit POR is enabled PDL_LPC_SOFTCUT_FLASH_HOCO_LVD Power is not supplied to flash memory or HOCO in software standby mode The voltage detection circuit LVD is stopped and the power consumption reduction function by the power on reset circuit POR is enabled Deep software standby control PDL_LPC_DEEPCUT_DISABLE or PDL_LPC_DEEPCUT_ENABLE At deep software standby mode both LVD and POR can be operated or LVD operates and POR operates in the low power consumption operation mode RENESAS Page 4 69 RX210 Group Description 3 5 R20UT0708EE0211 Rev 2 11 Aug 01 2014 data2 Select the interrupt to cancel deep software standby mode The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Deep software standby cancel control 4 Library Reference PDL_LPC_CANCEL_IRQO_DISABLE or PDL_LPC_CANCEL_IRQO_FALLING or PDL_LPC_CANCEL_IRQO_RISING Prevent or allow an edge on the IRQO DS pin to cancel deep software standby mode PDL_LPC_CANCEL_IRQ1_DISABLE or PDL_LPC_CANCEL_IRQ1_FALLING or PDL_LPC_CANCEL_IRQ1 RISING Prevent or allow an edge on the IRQ1 DS pin to cancel deep software standby mode PDL_LPC_CANCEL_IRQ2_D
231. IC Buffer 5 r r Setup DMAC to write data to IIC Configure channel 3 of DMAC to be triggered by SCI9 Tx R_DMAC Create 3 PDL DMAC REPEAT PDL_DMAC_SOURCE_ADDRESS PLUS PDL DMAC DESTINATION ADDRESS FIXED PDL DMAC SIZE 8 PDL_DMAC_ IRQ PDL DMAC TRIGGER SCI9 TX IIC Buffer Source uint8 t amp SCI9 TDR Dest 1 R20UT0708EE0211 Rev 2 11 Page 5 69 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 6 Data length Address in EEPROM 5 Data PDL_NO_DATA PDL_NO_DATA PDL NO DATA Callback Callback done function 7 Interrupt priority Enable DMAC channel 3 R_DMAC Control 3 p DMAC_ENABLE L NO PTR L NO PTR L NO DATA L NO DATA L NO DATA L NO DATA L NO DATA TT TI UUUUUUUOUS UT y Clear flag data_sent false Start IIC Write R_SCI_IIC Write CHANNEL SCI_IIC PDL _SCI_IIC_DMAC TRIGGER ENABLE SLAVE ADDRESS PDL_NO DATA No data length as using DMAC PDL NO DATA No buffer as using DMAC PDL NO FUNC i Wait for write to complete while false data_sent Because using DMAC need to manually send a stop to end the transfer R_SCI Control CHANNEL SCI_IIC PDL SCI IIC STOP i Callback done static void Callback void
232. IC_ RESET Carry out an internal reset of the 1 C module the settings are preserved True if all parameters are valid exclusive and achievable otherwise false Program example Category C Reference R_IIC_Create Remarks None RPDL definitions tinclude r pdl_iic h RPDL device specific definitions tinclude r pdl definitions h void func void Issue a Stop condition on channel 0 R_TIC Control 0 PDL IIC_ STOP R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 252 RENESAS RX210 Group R_IIC_GetStatus Synopsis Prototype Description Return value 4 Library Reference Read the status for an C channel bool R_IIC_GetStatus uint8_t data1 Channel selection uint32_t data2 Status flags uint16_t data3 Transmitted bytes uint16_t data4 Received bytes Read the status registers for the selected 12C channel data1 Select channel IICn where n 0 data2 The status flags shall be stored in the format below Specify PDL_NO_PTR if this information is not required b31 b18 b17 b16 Buffer status 0 Transmit Receive 0 Full 0 Empty 1 Empty 1 Full b15 b14 b13 b12 b11 b10 b9 b8 Bus state Pin level Event detection 0 Not detected 1 detected 0 Idle Stop Start A 1 Busy S
233. IIC MODE _SMBUS Choose between 1 C Bus or SMBus mode Internal reference clock PDL_IIC_INT_PCLK_DIV_1 or PDL_IIC_INT_PCLK_DIV_2 or PDL_IIC_INT_PCLK_DIV_4 or PDL_IIC_INT_PCLK_DIV_8 or PDL_IIC_INT_PCLK_DIV_16 or PDL_IIC_INT_PCLK_DIV_32 or PDL_IIC_INT_PCLK_DIV_64 or PDL_IIC_INT_PCLK_DIV_128 The reference clock source derived from PCLKB used inside the C module Timeout detection control PDL_IIC_TIMEOUT_BOTH PDL_IIC_TIMEOUT_DISABLE or PDL_IIC_TIMEOUT_LOW or PDL_IIC_TIMEOUT_HIGH or Disable timeout detection or enable for SCL stuck at a low level high level or both low and high level Timeout mode PDL_IIC_TIMEOUT_LONG or PDL_IIC_TIMEOUT_SHORT Select 16 bit long or 14 bit short mode SDA output delay count PDL_IIC_SDA_DELAY_0 or PDL_IIC_SDA_DELAY 1 or PDL IIC SDA DELAY 2 or PDL IIC SDA DELAY 3 or PDL IIC SDA DELAY 4 or PDL_IIC_SDA DELAY 5 or PDL IIC SDA DELAY 6 or PDL_IIC_SDA_DELAY 7 Select the number of cycles for the SDA output delay counter SDA output delay clock source PDL_IIC_SDA_DELAY_DIV_1 or PDL_IIC_SDA DELAY DIV_2 Select the clock source internal reference clock 1 or 2 for the SDA output delay counter R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS Page 4 238 RX210 Group 4 Library Reference Description 2 3 e Noise filter c
234. IMEOUT_1024 or PDL_IWDT_TIMEOUT_4096 or PDL_IWDT_TIMEOUT_8192 or PDL_IWDT_TIMEOUT_16384 The number of cycles of the selected clock before the reset occurs PDL_IWDT_CLOCK_OCO_1 or PDL_IWDT_CLOCK_OCO_16 or PDL_IWDT_CLOCK_OCO_32 or PDL_IWDT_CLOCK_OCO_64 or PDL_IWDT_CLOCK_OCO_128 or PDL_IWDT_ CLOCK OCO_ 256 Clock division ratio selection The IWDTCLK clock 1 16 32 64 128 or 256 Time out control PDL_IWDT_TIMEOUT_NMI or PDL_IWDT_TIMEOUT_RESET If the IWDT times out select if a Reset or an NMI Interrupt will be generated Window Start Position PDL_IWDT_WIN_START_25 or PDL_IWDT_WIN_START_50 or PDL_IWDT_WIN_START_75 or PDL_IWDT_WIN_START_100 The window start position specified as a percentage of the down counter 0 is when the down counter would underflow Selecting 100 is equivalent to no window start position Window End Position PDL_IWDT_WIN_END_0 or PDL_IWDT_WIN_END_25 or PDL_IWDT_WIN_END_50 or PDL_IWDT_WIN_END 75 The window end position specified as a percentage of the down counter 0 is when the down counter would underflow Hence specifying 0 is equivalent to no window end position Sleep Mode Count Stop PDL_IWDT_STOP_DISABLE or PDL_IWDT_STOP_ENABLE Enable or disable Count stop mode If the Count Stop mode is enabled the IWDT counter is stopped at a transition to sleep mode software standby mode deep software standby mode o
235. IN is selected when the CPU is restored from the sleep mode middle speed operating mode 1A will be automatically turned on e MCU Versions A and C do not support operating power modes PDL_LPC_MIDDLE_SPEED_MODE_2A or PDL_LPC_MIDDLE_SPEED_MODE_2B e If using MCU version B then flash power control is automatically controlled in software standby mode Therefore when setting the HOCO software standby control the flash part of the parameter setting is ignored So as an example these two settings become equivalent PDL_LPC_SOFTCUT_HOCO_POR or PDL_LPC_SOFTCUT_FLASH_HOCO_POR If the frequency of the ICLK will be set to gt 32MHz then PDL_LPC_HIGH_SPEED_MODE must be selected as the operating power control mode e If using MCU Version A do not select PDL_LPC_SLEEP_RETURN_SWITCH_MAIN RENESAS rae te RX210 Group Program example R20UT0708EE0211 Rev 2 11 Aug 01 2014 RPD RPDI L definitions include r pdl lpc h L device specific definitions include r pdl definitions h void func void A Allow a fa R_LPC Create PDL_NO_DA7 PDL TA PC CANCEL IRQO FALLING PDL NO DAT PDL PDL NO DAT PDL NO DAT PDL NO DAT TA PC MAIN 32 TA TA TA 2tENESAS 4 Library Reference lling edge on IRQO DS to cancel deep software standby Page 4 73 RX210 Group 4 Library Reference 2 R_LPC_Control Synop
236. ISABLE or PDL_LPC_CANCEL_IRQ2_FALLING or PDL_LPC_CANCEL_IRQ2 RISING Prevent or allow an edge on the IRQ2 DS pin to cancel deep software standby mode PDL_LPC_CANCEL_IRQ3_DISABLE or PDL_LPC_CANCEL_IRQ3_FALLING or PDL_LPC_CANCEL_IRQ3_RISING Prevent or allow an edge on the IRQ3 DS pin to cancel deep software standby mode PDL_LPC_CANCEL_IRQ4_DISABLE or PDL_LPC_CANCEL_IRQ4_FALLING or PDL_LPC_CANCEL_IRQ4 RISING Prevent or allow an edge on the IRQ4 DS pin to cancel deep software standby mode PDL_LPC_CANCEL_IRQ5_DISABLE or PDL_LPC_CANCEL_IRQ5_ FALLING or PDL_LPC_CANCEL_IRQ5 RISING Prevent or allow an edge on the IRQ5 DS pin to cancel deep software standby mode PDL_LPC_CANCEL_IRQ6_DISABLE or PDL_LPC_CANCEL_IRQ6_FALLING or PDL_LPC_CANCEL_IRQ6_RISING Prevent or allow an edge on the IRQ6 DS pin to cancel deep software standby mode PDL_LPC_CANCEL_IRQ7_DISABLE or PDL_LPC_CANCEL_IRQ7_FALLING or PDL_LPC_CANCEL_IRQ7_RISING Prevent or allow an edge on the IRQ7 DS pin to cancel deep software standby mode data3 Select the interrupt to cancel deep software standby mode The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Deep software standby cancel control PDL_LPC_CANCEL_LVD1_DISABLE or PDL_LPC_CANCEL_LVD1_ FALLING or PDL_LPC_CANCEL_LVD1_RISING Prevent or allow an edge on the LVD1 pin to cancel deep software standby mode PDL_LPC_CANCEL_LVD
237. LE if a transition to deep software standby is to be made Do not select PDL_CPA_NEGATION_AFTER_RESET if a transition to software standby or deep software standby is to be made Must call R_LINTC_CreateExtInterrupt PDL_INTC_LVDi_ENABLE to enable the NMI before set PDL_CPA_INTERRUPT_NONMASKABLE Note Comparator Non Interrupt Callback function is created by this call Set PDL_CPA_NEGATION_AFTER_RESET under the LOCO in operating The LVDi reset or LVDi non maskable interrupt should not be generated during flash memory programming erasure If a callback function is specified this function will enable the relevant interrupt Please see the notes on callback function use in 6 To enable the CPA event link output function enable the CPA first then enable the CPA event link function at the ELC To disable this function disable the CPA event link function at the ELC first then disable the CPA RPDL definitions include r pdl cpa h RPDL device specific definitions tinclude r pdl definitions h void CPAi handler void void func void Non Maskable Interrupt Comparator A channel 0 Digital Filter interrupt enable LOCO div 2 R_CPA Create 0 PDL CPA FILTER LOCO DIV 2 PDL _CPA_INTERRUPT_ RESET ENABLE PDL NO FUNC 0 7 Maskable Interrupt Comparator A channel 1 Digital Filter interrupt enable LOCO div_1 R_CPA Create 1 PDL CPA FILT
238. LKD_ P17 or PDL_TPU_PIN_CLKD_PB3 or Select the P17 PB3 or PC1 pin for TCLKD PDL_TPU_PIN_CLKD_PC1 True if all parameters are valid and exclusive otherwise false Timer Pulse Unit R_TPU_Create Remarks Program example e Device packages with 144 pins or more incorporate a TPU Before calling R_TPU_Create call this function to configure the relevant pins Not more than one peripheral function can be assigned to a single pin Make sure the configuration of TCLK pins is consistent for all the channels RPDL definitions include r pdl tpu h RPDL device specific definitions include r pdl definitions h void func void Configure TPU TIOCAO and TCLKA R_TPU_ Set 0 PDL TPU PIN AO P86 PDL TPU PIN CLKA P14 y R20UT0708EE0211 Rev 2 11 Page 4 304 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 2 R_TPU_Create Synopsis Prototype Description 1 5 Configure a Timer Pulse Unit channel bool R_TPU_Create uint8_t data1 uint32_t data2 uint32_t data3 uint32_t data4 uint32_t data5 uint16_t data6 uint16_t data7 uint16_t data8 uint16_t data9 uint16_t data10 Channel selection Configuration selection II Configuration selection Configuration selection II Configuration selection Register value Register value Reg
239. LK_HOCO L NO DATA L CGC_RTC_NOT_USF Figure 5 23 Example of initialization of not using RTC with available sub clock R20UT0708EE0211 Rev 2 11 Page 5 40 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 2 Initialize RTC without providing clock Figure 5 24 shows an example of initialization in case of RTC is not used and RTC count source is not defined PDL functions include r pdl cgc h include r pdl cmt h PDL device specific definitions include r pdl definitions h void main void Prepare the LOCO set R_CGC Set PDL_CGC_CLK_LOCO PDL_CGC_BCLK_DISABLI 125E3 125E3 PDL_NO_DATA 125E3 125E3 PDL_NO_DATA PDL NO DATA y Configure the HOCO settings p PDL CGC _HOCO 50000 p 5 2 PDI TA 2 2 P P Generate the 2s delay before enabling RTC by R CGC Control R_CMT CreateOneShot 0 PDL_NO_DATA 2 0 PDL_NO_FUNC 0 y Select the HOCO as the clock source R CGC Control PDL_CGC CLK HOCO PDL NO DATA PDL CGC RTC NOT USI Figure 5 24 Example of initialization of not using RTC without providing clock R20UT0708EE0211 Rev 2 11 Page 5 41 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 15 3 Use case of RTC over reset and power consumption 1 Wake up from sleep mode Figure 5 25 shows an example of using the Real time Clock wake up from sleep mode The sub cl
240. LVD Create PDL NO DATA PDL NO DATA PDL LVD INTERR _DETECT FALL PDL_LVD FILTER LOCO DIV 2 PDL LVD VOLTAGE LEVEL 280 PDL NO FUNC PDL NO DATA Callback_LVD 15 Low Voltage Callback function static void Callback LVD void uint8 t status Read status R_LVD GetStatus amp status User Handle Low Voltage Detection Figure 5 4 Example of Voltage Detection Circuit use R20UT0708EE0211 Rev 2 11 Page 5 8 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 4 2 Non maskable interrupts This shows an example of Voltage detection circuit usage An NMI is generated if the supply voltage drops below 3 1V Peripheral driver function prototypes include r pdl lvd h include r pdl intc h PDL device specific definitions include r pdl definitions h static void Callback NMI void void main void Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Configure the NMI to be triggered by the LVD1 signal only no NMI pin R_INTC_CreateExtInterrupt PDL INTC NMI PDL INTC LVD1_ENABLE Callback NMI PDL NO DATA Setup VDET1 to callback if VCC drops below 3 1V R LVD Create P WVD INTERRUPT NMI DETECT FALL PDL LVD FILTER DISABLE VD VOLTAGE LEVEL 310
241. L_2_COMPARE_MATCH_A2 or PDL ELC LINK EVENT TMR_CHANNEL_2_COMPARE_MATCH_B2 or PDL ELC LINK EVENT TMR_CHANNEL_2_OVERFLOW or PDL ELC LINK EVENT RTC_PERIODIC or PDL ELC LINK EVENT IWDT or PDL ELC LINK EVENT SCI5_ERROR or PDL ELC LINK EVENT SCI5_RECEIVE_DATA_FULL or PDL ELC LINK EVENT SCI5_TRANSMIT_DATA_EMPTY or PDL ELC LINK EVENT SCI5_TRANSMIT_END or PDL ELC LINK EVENT 1IC_ERROR_OR_EVENT or PDL ELC LINK EVENT 1IC_RECEIVE_DATA_FULL or PDL ELC LINK EVENT 1IC_TRANSMIT_DATA_EMPTY or PDL ELC LINK EVENT 1IC_TRANSMIT_END or PDL ELC LINK EVENT SPI_ERROR or PDL ELC LINK EVENT SPI_IDLE or PDL ELC LINK EVENT SPI_RECEIVE_DATA_FULL or PDL ELC LINK EVENT SPI_TRANSMIT_DATA_EMPTY or PDL ELC LINK EVENT SPI_TRANSMIT_END or PDL ELC LINK EVENT ADC12_CONVERSION_END or PDL ELC LINK EVENT COMPARATOR_BO_CHANGE or PDL ELC LINK EVENT COMPARATOR_B0_B1_COMMON_CHANGE or PDL ELC LINK EVENT LVD1_VOLTAGE_DETECTION or PDL ELC LINK EVENT LVD2_VOLTAGE_DETECTION or PDL ELC LINK EVENT DMAC_CHANNEL_0_TRANSFER_END or PDL ELC LINK EVENT DMAC_CHANNEL_1_TRANSFER_END or PDL ELC LINK
242. L_IO_PORT_XOR data3 The value to be used for the modification Between 0x00 and OxFF for a port 0 or 1 for a pin True if the parameters are valid otherwise false I O port None e lf an invalid port or pin is specified the operation of the function cannot be guaranteed RPDL definitions include r pdl io port h RPDL device specific definitions tinclude r pdl definitions h void func void Invert port pin P05 R_IO PORT Modify PDL IO PORT 0 5 PDL IO PORT XOR 1 7 And the value port 6 with 0x55 R IO PORT Modify PDL IO PORT 6 PDL IO PORT AND 0x55 i R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS Ea RX210 Group 4 Library Reference 8 R_IO_PORT_Wait Synopsis Prototype Description Return value Category References Remarks Program example Wait for a match on an I O port bool R_IO_PORT_Wait uint16_t data1 Output port or port pin selection uint8_t data2 II Comparison value Loop until an I O port or I O port pin matches the comparison value data1 Use either one of the following definition values from 4 2 3 One port definition or One port pin definition data2 The value to be compared with Between 0x00 and OxFF for a port O or 1 for a pin True if the parameters are valid otherwise false 1
243. L_TMR_TMR1_TMCI1_P12 or PDL_TMR_TMR1_TMCI1_P54 or PDL_TMR_TMR1_TMCI1_PC4 PDL_TMR_TMR1_TMRI1_P24 or PDL_TMR_TMR1_TMRI1_PB5 Select the pins for TMO1 Select the pins for TMCI1 Select the pins for TMRI1 e Valid when n 2 PDL_TMR_TMR2_TMO2_P16 or PDL_TMR_TMR2_ TMO2 PC7 PDL_TMR_TMR2_TMCI2_ P15 or PDL_TMR_TMR2_TMCI2_P31 or Select the pins for TMCI2 PDL_TMR_TMR2_TMCI2_PC6 PDL_TMR_TMR2_TMRI2_P14 or PDL_TMR_TMR2_TMRI2_PC5 Select the pins for TMO2 Select the pins for TMRI2 e Valid when n 3 PDL_TMR_TMR3_TMO3_P13 or PDL_TMR_TMR3_TMO3_P32 or Select the pins for TMO3 PDL_TMR_TMR3_TMO3_P55 PDL_TMR_TMR3_TMCI3_P27 or PDL_TMR_TMR3_TMCI3_P34 or Select the pins for TMCI3 PDL_TMR_TMR3_TMCI3_PA6 PDL_TMR_TMR3_TMRI3_P30 or PDL_TMR_TMR3_TMRI3_P33 Select the pins for TMRI3 Return value True if all parameters are valid and exclusive otherwise false Category Timer TMR R20UT0708EE0211 Rev 2 11 Page 4 155 Aug 01 2014 RENESAS RX210 Group 4 Library Reference Reference Remarks Program example R_TMR_CreateChannel R_TMR_CreateUnit Before calling any R_TMR_Create function call this function to configure the relevant pins e Call this function multiple times if more than one channel is to be configured Pins which are not used
244. ME_4 or 4 1 4 PDL_SPI_FRAME_5 or 5 1 5 PDL_SPI_FRAME_6 or 6 1 6 PDL_SPI_FRAME_7 or 7 1 7 PDL_SPI_FRAME_8 8 1 8 Parity bit control PDL_SPI_PARITY_NONE or PDL_SPI_PARITY_EVEN or Disable or enable the addition of the parity bit PDL_SPI_PARITY_ODD data4 Extended timing control optional All items apply only to Master mode If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA if not required Extended clock delay PDL_SPI_CLOCK_DELAY_1 or PDL_SPI_CLOCK_DELAY_2 or PDL_SPI_CLOCK_DELAY_3 or PDL_SPI_CLOCK_DELAY 4 or PDL_SPI_CLOCK_DELAY_5 or PDL_SPI_CLOCK_DELAY 6 or PDL_SPI_CLOCK_DELAY_7 or PDL_SPI_CLOCK_DELAY 8 The number of bit clock periods between the assertion of the SSL pin and the start of RSPCK oscillation Ignored in Slave mode Extended SSL negation delay PDL_SPI_SSL_DELAY_1 or PDL_SPI_SSL_DELAY_2 or PDL_SPI_SSL_DELAY_3 or PDL_SPI_SSL_DELAY 4 or PDL_SPI_SSL_DELAY_5 or PDL_SPI_SSL_DELAY_6 or PDL_SPI_SSL_DELAY_7 or PDL_SPI_SSL_DELAY 8 The number of bit clock periods between the end of RSPCK oscillation and the negation of the active SSL pin Ignored in Slave mode Extended next access delay PDL_SPI_NEXT_DELAY_1 or PDL_SPI_NEXT_DELAY_2 or PDL_SPI_NEXT_DELAY_3 or PDL_SPI_NEXT_DELAY_4 or PDL_SPI_NEXT_DELAY_5 or PDL_SPI_NEXT_DELAY_6 or PDL_SPI_NEXT_
245. MR_CreateChanneli 0 PDL TMR C K PCLK DIV 1 PDL TMR CLEAR CM A PDL NO DATA 0 199 99 PDL_NO_FUNC PDL_NO_FUNC PDL_NO_FUNC 0 MRO PCLKB clear after a compare match A R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS Page 4 159 RX210 Group 4 Library Reference 3 R_TMR_CreateUnit Synopsis Prototype Description 1 2 R20UT0708EE0211 Rev 2 11 Aug 01 2014 Configure a timer TMR unit bool R_TMR_CreateUnit uint8_t data1 Unit selection uint32_t data2 uint8_t data3 uint16_t data4 uint16_t data5 uint16_t data6 Output control Register value Register value II Register value void func1 II Callback function void func2 Callback function void func3 Callback function uint8_t data7 1 Configuration selection Interrupt priority level Set up a timer TMR unit in 16 bit count mode data1 The unit number n where n 0 or 1 data2 Configure the unit If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Counter clock source selection PDL_TMR_CLK_OFF or The clock input is disabled PDL_TMR_CLK_EXT_RISING or PDL_TMR_CLK_EXT_FALLING or PDL_TMR_CLK_EXT_BOTH or The external clock signal TMCIx x 1 or 3 for n O or 1 is used with rising fallin
246. MTU2_OUT_P_PHASE_1_DISABLE MTOGSE PDL MTU2 OUT N PHASE 1 ENABLE or PDL MTU2 OUT N_PHASE_1_DISABLE MTIOC3D PDL MTU2 OUT P_PHASE_2_ENABLE or PDL MTU2 OUT P_PHASE 2 DISABLE MTIOCAA PDL_MTU2 OUT N_PHASE_2_ ENABLE or PDL_MTU2_OUT_N_PHASE_2 DISABLE MUOCAC PDL MTU2 OUT P_PHASE_3 ENABLE or TERA PDL_MTU2 OUT P_PHASE 3 DISABLE l PDL MTU2 OUT N_PHASE_3 ENABLE or SEA PDL_MTU2_OUT_N PHASE 3 DISABLE Or all six phase outputs can be controlled together b selecting one of each PDL_MTU2_OUT_P_PHASE_ALL_ENABLE or PDL_MTU2_ OUT_P_PHASE_ALL_DISABLE All P phase outputs PDL_MTU2_OUT_N_PHASE_ALL_ENABLE or PDL_MTU2_OUT_N PHASE ALL DISABLE All N phase outputs Output inversion control applies only to reset synchronised or complementary PWM modes Each phase output can be configured for a initial high level active low level or b initial low level active high level If dead time is not generated the options for negative phases will be ignored as their outputs are always the inverse of the positive phases All six phase outputs can be controlled together by selecting one of each PDL_MTU2_OUT_P_PHASE_ALL_HIGH_LOW or PDL_MTU2_ OUT_P_PHASE_ALL_LOW_HIGH Positive phase outputs PDL_MTU2_OUT_N_PHASE_ALL_HIGH_ LOW or PDL_MTU2_OUT_N PHASE _ALL_LOW_HIGH Negative phase outputs Or independently by selecting one option for each re quired output PDL_MTU2_OUT
247. NEL_1 or TMR_CHANNEL_0 or TMR_CHANNEL_2 or ADC12 or DAC_CHANNEL_0 or INTERRUPT_ 1 or INTERRUPT_2 or OUTPUT_PORT_B_GROUP or OUTPUT_PORT_E_ GROUP or INPUT_PORT_B_GROUP or INPUT_PORT_E_GROUP or SINGLE_PORT_0 or SINGLE_PORT_1 or SINGLE _PORT_2 or SINGLE_PORT_3 or CLOCK_SOURCE or POE2 Select the module to remove the link from Operation data1 PDL_ELC_TIMER_OPERATION data2 Timer selection PDL_ELC_TIMER_MTU2_CHANNEL_1 or PDL_ELC_TIMER_MTU2_CHANNEL_2 or PDL_ELC_TIMER_MTU2_CHANNEL_3 or PDL_ELC_TIMER_MTU2_CHANNEL_4 or Select the timer to configure PDL ELC_TIMER CMT_CHANNEL_1 or PDL ELC_TIMER TMR_CHANNEL_0 or PDL_ ELC_TIMER _ TMR_CHANNEL_2 gas Timer operation PDL_ELC_TIMER_COUNT_START or PDL_ELC_TIMER_COUNT_RESTART or PDL_ELC_TIMER_EVENT_COUNTER or PDL_ELC_TIMER_INPUT_CAPTURE or PDL_ELC TIMER EVENT DISABLE Select the timer operation when triggered Operation data1 PDL_ELC_PORT_GROUP data2 Select the port PDL_ELC_PORT_Bor PDL_ELC PORT E Select a port whose bits will make up a port group data3 Select the bits which define the port group b31 b7 b0 Not used Bit mask where a high bit selects the bit as part of the port group R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS Page 4 118 RX210 Group Description 5 6
248. NT PDL NO PTR amp time amp date i enter sleep mode after alarm in 10sec while bEnterSleepMode false Enter sleep mode An internal reset will occur if false R LPC Control PDL LPC_ MODE SLEEP while 1 It is correct to be here if have just woken from sleep mode while 1 Read time R_RTC_Read PDL_RTC_ READ CURRENT amp flags amp time amp date If no carry error output the time flags amp BIT 6 Has time changed R20UT0708EE0211 Rev 2 11 Page 5 44 Aug 01 2014 ztENESAS RX210 Group 5 Usage Examples if time OxFFFFFF time previous OXFFFFFF time previous time sprintf char buffer Time 5d d r n j j 0xF00000 gt gt 0x0F0000 gt gt 0x00F000 gt gt 0x000F00 gt gt time 0x0000F0 gt gt time 0x00000F gt gt R_SCI Send RSK_SCI CHANN PDL_NO_DATA buffer 0 PDL_NO FUNC static void SetClocks void Prepare the LOCO settings R_CGC_Set PDL CGC CLK LOCO PDL CGC_BCLK DISABLE PDL CGC SUB CLOCK CL STANDARD 125E3 125E3 125E3 125E3 125E3 PDL NO DAT PDL NO DAT de Configure the HOCO settings p PDL_CGC_BCLK_DISABL TA TA TA W g a a Dood i Sub clock R_CGC Set PDL_CGC_CLK_SUB_CLOCK PDL _CGC_BCLK_ DISABLE 32768 Frequency of selected clock source 32768
249. None In Addition Mode the flag is set if the result of the addition exceeds FFFFh In Subtraction the flag is set if the result of the subtraction is less than zero In Comparison Mode the flag is set when the comparison criteria Match Mismatch is met If the flag is set it is automatically cleared by this function If using interrupts the flag is automatically cleared when the interrupt is handled RPDL definitions tinclude r pdl_doc h RPDL device specific definitions tinclude r pdl_definitions h VO id func void uint8 t status uintl6 t result Read result R_DOC_Read amp status amp result y Page 4 301 RENESAS RX210 Group 4 Library Reference 5 R DOC Write Synopsis Prototype Return value Category References Remarks Program example Write data to the Data Operation Circuit bool R_DOC_Write uint16_t data1 Pointer to buffer holding data to write uint16_t data2 Number of 16 bit words to write data1 The start address of the data to be written data2 The number of 16 bit words to write True DOC None e This function will not return until all the supplied data has been written to the DOC The DMAC DTC can be used to write data to the DOC independently of this function RPDL definitions tinclude r pdl _doc h RPDL devic
250. None RPDL definitions include r pdl cpb h RPDL device specific definitions tinclude r pdl definitions h void func void Shutdown channel 0 R_CPB Destroy 0 R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 294 RENESAS RX210 Group 4 Library Reference 3 R_CPB_GetStatus Synopsis Read the Comparator B channel status Prototype bool R_CPB_GetStatus uint8_t data 11 A pointer to the data storage location Description Read and store the status flag data The comparator B status flag shall be stored in the following format b7 b6 b4 b3 b2 b0 0 CMPB1 lt CVREFB1 0 0 CMPBO lt CVREFBO 0 1 CMPB1 gt CVREFB1 1 CMPBO gt CVREFBO Return value True Category Comparator B Reference None Remarks None Program example RPDL definitions include r pdl cpb h RPDL device specific definitions tinclude r pdl definitions h uint8 t Flags void func void Read the comparator B values R_CPB GetStatus amp Flags i R20UT0708EE0211 Rev 2 11 Page 4 295 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 4 2 30 Data Operation Circuit 1 R_DOC_Create Synopsis Prototype Description Return value Category References Remarks Configure the Data Operation Cir
251. O dtc_cmt0 transfer data void Ox0000zAA0O void 0x0000BBO00 100 0 RENESAS PDL DTC SIZE 8 full address mode for the CMT0 triggered transfer Page 4 105 RX210 Group 4 Library Reference 3 R_DTC_Destroy Synopsis Prototype Description Return value Category Reference Disable the Data Transfer Controller bool R_DTC_Destroy void 1 No parameter is required Shutdown the Data Transfer Controller True Data Transfer Controller R_DTC_Control Remarks Program example This function will also shut down the DMAC Before calling this function i If another peripheral is being used to trigger a DTC transfer stop the triggers from that peripheral using Control or Destroy for that peripheral ii Use R_DTC_Control to stop the DTC iii Stop the DMAC RPDL definitions tinclude r pdl_dtc h RPDL device specific definitions tinclude r pdl_definitions h void func void Shutdown the DTC amp DMAC R_DTC_ Destroy y R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 106 RENESAS RX210 Group 4 R_DTC_Control Synopsis Prototype Description Return value Category Reference R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference Control the Data Transfer Controller bool R
252. O DATA buffer 0 PDL NO FUNC R_RTC_CreateWarm Alarm handler Alarm handler LS Alarm priority PDL_NO FUNC Periodic Handler PDL _NO DATA Periodic priority de R_RTC_Read PDL RTC READ CURRENT PDL _NO PTR amp time amp date Configure the clock R_RTC Control p DATA UPDATE ALARM TIME DATA DATA 0x10 Alarm in another 10 seconds DATA DATA Error Adjust DATA Capture DATA Capture DAT Capture DAT Periodic gggygyyvyvtyyygyyl HWH g g w t g y E o o t If Cold start is detected the RTC clock should be re started R_SCI Send RSK_ SCI CHANNEL PDL NO DATA r nRTC Start in Cold start mode Initailize RTC r n 0 PDL NO FUNC if R RTC Create RTC ALARM TIME ENABLE PDL RTC ALARM DAT ENABLE L NO DATA FF114250 Automatic day of week 11 42 50 20131118 18 Nov 2013 L_NO_DATA Capture 0 L_NO DATA Capture 1 L NO DATA Capture 2 L NO DATA Periodic FF114300 Alarm in 10 seconds R P P 0 0 P p P p 0 D D x x D D D D x R20UT0708EE0211 Rev 2 11 Page 5 48 Aug 01 2014 ztENESAS RX210 Group 5 Usage Examples 0x20131118 18 Nov 2013 Alarm _handler 15 PDL_NO_FUNC PDL_NO_DATA false R_SCI_Send RSK_SCI_CHANNEL PDL NO DATA r nRTC Create error in Cold start m
253. O708EE0211Rev211 C lt lt lt 3R Rage 2 14 Aug 01 2014 RENESAS RX210 Group 2 Driver 2 15 Event Link Controller The driver functions support the control of the Event Link Controller providing the following operations 1 Enabling the module 2 Disabling the module 3 Linking events with modules 4 Configuring Timer output 5 Setting and controlling port groups R20UT0708EE0211 Rev 2 11 Page 2 15 Aug 01 2014 RENESAS RX210 Group 2 Driver 2 16 Multi Function Timer Pulse Unit Driver The driver functions support the use of the six 16 bit timers providing the following operations 1 Selection of the MTU pins for use 2 Configuration for use including e Access to all control bits e Automatic interrupt control e Automatic I O pin configuration 3 Disabling channels that are no longer required and enabling low power mode 4 Control of a timer channel 5 Control of a timer unit 6 Reading the status flags and registers of a timer channel 7 Reading the status flags and registers of a timer unit Note The Clock Generation Circuit must be configured before configuring any timer channel R20UT0708EE0211 Rev 2 11 Page 2 16 Aug 01 2014 RENESAS RX210 Group 2 Driver 2 17 Port Output Enable Driver The driver functions support the use of the Port Output module providing the following operations 1 Configuring the pins for use 2 Configuring the interrupts and callback fu
254. OFS LVD 0 280 D D D DL DI DI DI void main void R20UT0708EE0211 Rev 2 11 Aug 01 2014 L MCU OFS CGC HOCO DISABLE te that the macro is used outside of xecutabl cod 2tENESAS Page 4 55 RX210 Group 4 Library Reference 4 2 6 Voltage Detection Circuit 1 R_LVD_Create Synopsis Prototype Description 1 2 Configure the voltage detection circuit bool R_LVD_Create uint16_t data1 II Monitor 1 Configuration selection uint16_t data2 Monitor 1 Voltage selection uint16_t data3 II Monitor 2 Configuration selection uint16_tdata4 Monitor 2 Voltage selection void func1 II Monitor 1 Callback function uint8_t data5 1 Monitor 1 Interrupt priority level void func2 II Monitor 2 Callback function uint8_t data6 1 Monitor 2 Interrupt priority level Set the voltage detection configuration data1 Monitor 1 voltage detection configuration If the monitor is not required specify PDL_NO_DATA otherwise use to separate each selection e Operation PDL_LVD_MONITOR_ONLY or PDL_LVD_RESET_NEGATION_VCC_MORE_THAN_VDET or PDL_LVD_RESET_NEGATION_AFTER_DELAY or Select no action a reset PDL_LVD_INTERRUPT_NMI_DETECT_RISE or on low voltage detection PDL_LVD_INTERRUPT_NMI_DETECT_FALL or or an interrupt when a PDL_LVD_INTERRUPT_NMI_DETECT_RISE_AND_FALL or specified voltage event is PDL_LVD_INTERRUPT_MI_D
255. OM ADDRESS PDL NO PTR 0 PDL NO FUNC 0 i while bus_busy true void iic_tx_dmac_end_handler void uint32 t status flags 0 Wait for the transmission to complete do R_IIC_GetStatus 0 amp status_flags PDL NO PTR PDL NO PTR i while status flags amp 0x00000080u1 0x0u Issue a Stop condition on channel 1 R_IIC Control 0 PDL IIC STOP bus_busy false R20UT0708EE0211 Rev 2 11 Page 5 81 Aug 01 2014 ztENESAS RX210 Group 5 Usage Examples void iic rx dmac end handler void uint32 t DestAddr Read the next destination address for the current transfer R_DMAC GetStatus 2 PDL_NO PTR PDL_NO PTR amp DestAddr PDL_NO PTR PDL_NO PTR i Read one more byte with NACK condition on channel 1 and stop R_IIC MasterReceiveLast 0 uint8 t DestAddr de bus_busy false Figure 5 46 An example of write data to and reading data from an EEPROM using two DMAC channels R20UT0708EE0211 Rev 2 11 Page 5 82 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 18 3 Master mode with DTC In the following example data is written to an EEPROM in two bursts The DTC is used to handle the data transfer The same EEPROM address locations are then read out in two bursts The DTC is used to handle the data transfer Peripheral driver function prototypes include include include ry pal
256. P40 for ANOOO PDL_ADC 12 PIN_ANOO01_P41 Select P41 for ANO01 PDL_ADC_12 PIN_ANO02 P42 Select P42 for ANOO2 PDL_ADC 12 PIN_ANOO3 _P43 Select P43 for ANOO3 PDL_ADC_12 PIN_ANO04 P44 Select P44 for ANO04 PDL_ADC 12 PIN_ANOO5 P45 Select P45 for ANOO5 PDL_ ADC 12 PIN _ANO06_ P46 Select P46 for ANOO6 PDL_ADC_12 PIN _ANO0O7_P47 Select P47 for ANOO7 PDL_ADC 12 PIN ANO08 PEO Select PEO for ANOO8 PDL_ADC 12 PIN ANOO9 PE1 Select PE1 for ANOO9 PDL_ ADC 12 PIN_ANO10_PE2 Select PE2 for ANO10 PDL_ADC 12 PIN_ANO11_PE3 Select PE3 for ANO11 PDL_ADC_12 PIN_ANO12 PE4 Select PE4 for ANO12 PDL_ADC 12 PIN_ANO13 PES Select PE5 for ANO13 Select PE6 for ANO14 Select PE7 for ANO15 PDL_ADC_12 PIN_ANO14_PEG PDL_ADC_12 PIN_ANO15_PE7 PDL_ADC_12_PIN_ADTRGO_PO7 or PDL_ADC_12 PIN_ADTRGO_P16 or PDL_ADC_12 PIN_ADTRGO P25 Select P07 P16 or P25 for ADTRGO Return value True if all parameters are valid and exclusive otherwise false Category 12 bit ADC Reference R_ADC_12 CreateUnit Remarks If there are I O pins to be used call this function before calling R_ADC_12_CreateUnit Device packages with 80 or fewer pins do not have all of the pin options Program example RPDL definitions include r pdl adc 12 h
257. PDL definitions include r pdl_iic h RPDL device specific definitions tinclude r pdl_definitions h uint8 t data_array 5 0x23 0x48 0x59 0x60 OxFE void func void Assign 5 bytes to be read by a master on channel 0 R_IIC_SlaveSend 0 data_array 5 y R20UT0708EE0211 Rev 2 11 Page 4 251 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 9 R_IIC_Control Synopsis Prototype Description Return value 12C channel control bool R_IIC_Control uint8_t data1 uint8_t data2 Channel selection Control options Modify the operation of the selected 1 C channel data1 Select channel IICn where n 0 data2 Control the channel If multiple selections are required use to separate each selection Stop generation PDL_IIC_STOP Issue a Stop condition NACK generation PDL_IIC_NACK Set the Acknowledge bit to the NACK state Pin control PDL_IIC_SDA_LOW or PDL_IIC SDA HI Z PDL_IIC_SCL_LOW or PDL_IIC_SCL_HI_Z Set the SDA pin to low level or high impedance Set the SCL pin to low level or high impedance e Extra clock cycle generation Generate an extra clock cycle on the SCL pin This can be used in Master mode to try and unlock a slave device that is holding the SDA signal low PDL_IIC_CYCLE_SCL Reset control PDL_I
258. PDL_CGC_SUB_ 1024 or PDL_CGC_SUB_ 2048 or PDL_CGC_SUB_4096 or PDL_CGC_SUB_16384 or PDL_CGC_SUB_32768 or PDL_CGC_SUB_65536 or PDL_CGC_SUB_131072 or PDL_CGC_SUB_262144 or PDL_CGC_SUB_524288 Select the oscillation settling time of the sub clock oscillator RENESAS id RX210 Group Return value Category References Remarks R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference True if all parameters are valid and exclusive otherwise false For RX210 the following rules shall be checked e MAIN_CLOCK_OSCILLATOR lt 20 MHz and 2 4 MHz if the PLL will be used fet 50 to 100 MHz ficik lt 50 MHz frciko lt 50 MHz frcike 32 MHz fectkS 32 MHz fecik lt 25 MHz fecLk_PIN lt 12 5 MHz fick 2 fecLk The frequency of the PLL is achievable main clock x 8 10 12 16 20 24 or 25 The frequencies of the internal clocks ICLK PCLKD PCLKB FCLK and BCLK are achievable selected clock source 1 2 4 8 16 32 or 64 Clock generation circuit R_CGC_Control R_LPC_Create R_MCU_GetStatus R_BSC_Control Call this function once to set the clock frequency for whether it is used as system clock or RTC count source If the current clock source is selected in parameter data1 the frequencies of the internal clocks will be changed by this function Because this can not be done if ROM Flash Program Erase mode is set or if a operating power mod
259. PDL_SCI_IIC_MODE IIC Mode selected Use the functions R_SCI_IIC_Read and R_SCI_lIC_ Write not R_SCI_Send or R_SCI_Receive Options which are available in Clock Synchronous and SPI mode Data clock source selection PDL_SCI_CLK_INT_OUT or Select the On chip baud rate generator The SCKn pin outputs the bit clock In SPI Mode this is Master mode PDL_SCI_CLK_EXT Input the clock to the SCKn pin In SPI Mode this is Slave mode SPI Clock Polarity Inversion PDL_SCI_CLOCK _POLARITY INVERTED The SCK clock is inverted SPI Clock Phase Delay PDL_SCI_CLOCK PHASE DELAYED The SCK clock is delayed Options which are available in Clock Synchronous mode Not SPI or IIC Hardware Flow Control PDL_SCI_HW_FLOW_CTS or PDL_SCI_HW_FLOW_RTS PDL_SCI_HW_FLOW_NONE or Select the Hardware Flow Control Option Notes e CTS can only be selected if using an internal clock source for SCLK e RTS can only be selected if using external clock source for SCLK Options which are available in SPI mode e SPI SS Pin PDL_SCI_SPI_SS_DISABLE or The SS pin is not used Single master environment PDL_SCI_SPI_SS_ENABLE The SS pin is used Note This option is not available if using SPI Master mode if selected the function will return false Data inversion PDL_SCI INVERSION_ON PDL_SCI_INVERSION_OFF or Control data inver
260. PRD PDL_INTC_ REG _IR_SCI1_TXI PDL INTC REG IR S12AD0 S12ADI PDL_INTC REG IR SCI1 TEI PDL INTC REG IR S12AD0 GBADI PDL INTC REG IR SCI2 ERI PDL_INTC REG IR ELC ELSR 18l PDL_INTC_REG_IR_SCI2_RXI PDL_INTC_ REG IR ELC ELSR19l PDL_INTC_REG_IR_SCI2_TXI PDL_INTC_REG_IR_MTUO_TGIA PDL_INTC_REG_IR_SCI2_TEI PDL INTC REG IR MTUO TGIB PDL INTC REG IR SCI3 ERI PDL INTC REG IR MTUO TGIC PDL INTC REG IR SCI3 RXI PDL_INTC_ REG _IR_MTUO TGID PDL_INTC_REG_IR_SCI3_TXI PDL_INTC_REG_IR_MTUO_TCIV PDL_INTC_REG_IR_SCI3_TEI PDL_INTC_REG_IR_MTUO_TGIE PDL_INTC_REG_IR_SCI4_ERI PDL INTC REG IR MTUO TGIF PDL_INTC REG IR SCl4 RXI PDL INTC REG IR MTU1 TGIA PDL INTC REG IR _SCI4 TXI PDL_INTC_ REG _IR_MTU1_TGIB PDL_INTC REG IR_SCl4 TEI PDL_INTC_ REG _IR_MTU1_TCIV PDL_INTC_ REG _IR_SCI5 ERI PDL_INTC_ REG _IR_MTU1_TCIU PDL_INTC_ REG _IR_SCI5 RXI PDL_INTC REG IR MTU2 TGIA PDL_INTC REG IR SCI5 TXI PDL_INTC REG IR MTU2 TGIB PDL INTC REG IR SCI5 TEI PDL_INTC_REG_IR_MTU2_TCIV PDL_INTC_REG_IR_SCI6_ERI PDL_INTC_REG_IR_MTU2_TCIU PDL_INTC_REG_IR_SCI6_RXI PDL_INTC_REG_IR_MTU3_TGIA PDL_INTC_REG_IR_SCI6_TXI PDL INTC REG IR MTU3 TGIB PDL INTC REG IR SCI6 TEI PDL INTC REG IR MTU3 TGIC PDL INTC REG IR SCI7 ERI PDL_INTC_ REG _IR_MTU3_ TGID PDL_INTC_ REG _IR_SCI7_RXI PDL_INTC_REG_IR_MTU3_TCIV PDL_INTC_REG_IR_SCI7_TXI R20UTO708EE0211 Rev 2 11 Page 4 26 Aug 01 2014 RENESAS RX210 Group 4 Library Reference
261. PSRSTF 1 bDeepStdbyExit true SYSTEM RSTSRO BIT DPSRS1 Create async for debug output R_SCI_ Set RSK_SCI CHANNEL PDL SCI PIN SCIO RXDO P21 PDL SCI PIN SCIO TXDO P20 i R SCI Create RSK_SCI CHANNEL PDL SCI ASYNC 9600 10 r PDL SCI _8N1 Check warm cold start flag CWSF 1 call R_RTC_CreateWarm to start up the RTC if warm cold start flag is detected power ON from warm start Get Reset Status Flag R_MCU_GetStatus PDL NO PTR amp status PDL_NO PTR PDL NO PTR R20UT0708EE0211 Rev 2 11 Page 5 47 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples RSTSR1 CWSF Warm start RTC is running if status amp BIT 8 uint16 t BIT 8 amp amp RTC RCR2 BIT START 0 Tf warm start is detected and RTC is running then warm start R_SCI_Send RSK_SCI_CHANNEL PDL NO DATA r nRTC Start in Warm start mode Control to change time r n 0 PDL NO FUNC Warm wake up Read time R_RTC_Read PDL_ RTC READ CURRENT amp flags amp time amp date sprintf char buffer RTC Time before changing d d d d d d r n int time amp OxF00000 gt gt 20 int time Ox0F0000 gt gt 16 int time amp 0Ox00F000 gt gt 12 int time amp 0x000F00 gt gt 8 int int time 0x0000F0 gt gt 4 time 0x00000F gt gt 0 R SCI Send RSK_SCI CHANNEL PDL N
262. PU3_TGID PDL_INTC_REG_IR_SCI12_RXI PDL_INTC_REG_IR_TPU3_TCIV PDL_INTC_REG_IR_SCI12_TXI PDL_INTC_REG_IR_TPU4_TGIA PDL_INTC_REG_IR_SCI12_TEl PDL_INTC_REG_IR_TPU4_TGIB PDL_INTC_REG_IR_SCI12_SCIX0O PDL_INTC_REG_IR_TPU4_TCIV PDL_INTC_REG_IR_SCI12_SCIX1 PDL_INTC_REG_IR_TPU4_TCIU PDL_INTC_REG_IR_SCI12_SCIX2 PDL_INTC_REG_IR_TPU5_TGIA PDL_INTC_REG_IR_SCI12_SCIX3 PDL_INTC_REG_IR_TPU5_TGIB PDL_INTC_REG_IR_IICO_TXI PDL_INTC_REG_IR_TPU5_TCIV PDL_INTC_REG_IR_IICO_TEI PDL_INTC_REG_IR_TPU5_TCIU IER register definitions PDL_INTC_REG_IERO2 PDL_INTC_REG_IER10 PDL_INTC_REG_IERO3 PDL_INTC_REG_IER12 PDL_INTC_REG_IER04 PDL_INTC_REG_IER13 PDL_INTC_REG_IERO5 PDL_INTC_REG_IER14 PDL_INTC_REG_IERO6 PDL_INTC_REG_IER15 PDL_INTC_REG_IERO7 PDL_INTC_REG_IER16 PDL_INTC_REG_IER08 PDL_INTC_REG_IER17 PDL_INTC_REG_IERO9 PDL_INTC_REG_IER18 PDL_INTC_REG_IEROA PDL_INTC_REG_IER19 PDL_INTC_REG_IEROB PDL_INTC_REG_IER1A PDL_INTC_REG_IEROC PDL_INTC_REG_IER1B PDL_INTC_REG_IEROD PDL_INTC_REG_IER1C PDL_INTC_REG_IEROE PDL_INTC_REG_IER1D PDL_INTC_REG_IEROF PDL_INTC_REG_IER1E PDL_INTC_REG_IER1F PDL_ INTC REG IPR BSC BUSERR PDL_INTC REG IPR MTU1 TGIA PDL INTC REG IPR FCU FIFERR PDL INTC
263. PU_Destroy Disable the TPU R_TPU_ControlChannel Control a timer channel R_TPU ControlUnit Control a timer unit O O1 BY CO P f OT BY CO PO GO PO CO PO PO OO PM gt OD 1 BR O PO BRO M NJ ol RB OG Mh a R_TPU_Read Read from TPU registers R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS Page 4 3 RX210 Group 4 Library Reference 4 2 Description of Each API This section describes each API and explains how to use them showing a program example for each The description of each API is divided into the following items Synopsis Summarises processing by the API function Prototype The function format and a brief explanation of the arguments Description Explains how to use the API function and shows assignable parameters separating each argument with argument Return value Describes the returned value of the API function Category Indicates the category of the API function Reference Indicates the API functions to be referred Remark Describes notes to use the API function Program example Represents how to use the API function by a program example Two examples of return value checking are shown below RPDL definitions include r pdl_mpc h include r pdl sci h RPDL device specific definitions include r pdl definitions h void func void
264. READ CURRENT PDL NO PTR amp time amp date Figure 5 20 Example of configuration CGC and RTC counting by sub clock Only RTC count source R20UT0708EE0211 Rev 2 11 Page 5 34 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 2 Configuration CGC and RTC counting by sub clock both RTC count source and System clock Figure 5 21 shows an example of sub clock used as both RTC count source and system clock PDL functions include r pdl cgc h include r pdl cmt h include r pdl rtc h PDL device specific definitions include r pdl definitions h void main void volatile uint32 t date Prepare the LOCO set R_CGC Set PDL_CGC_CLK_LOCO PDL_CGC_BCLK_DISABL 125E3 125E3 PDL_NO_DATA 125E3 125E3 PDL_NO_DATA PDL NO i Prepare the Sub clock settings PDL CGC CLK SUB CLOCK L CGC BCLK DISABLE PDL CGC SUB CLOCK CL STANDARD TA PCLKB clock sub clock when sub clock is source clock rA L_CGC_SUB_32768 i Wait for the Subclock stabilisation time 2 seconds minimum NOTE As curently running from the Sub clock the R_CMT CreateOneShot max time limit is gt 2 Secs R_CMT CreateOneShot 0 PDL NO DATA 20 PDL_NO_FUNC 0 i Select the sub clock as the clock source R_CGC_Control PDL CGC CLK SUB CLOCK PDL NO DATA PDL CGC RTC TO BE USED y
265. RPDL device specific definitions tinclude r pdl definitions h void func void Set up port P13 as an input port with the pull up on R_IO PORT Set PDL IO PORT 1 3 PDL IO PORT INPUT PDL IO PORT PULL UP_ON 7 R20UT0708EE0211 Rev 2 11 Page 4 35 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 2 R_IO_PORT_ReadControl Synopsis Prototype Description Return value Category References Remarks Read an I O port s control register bool R_IO_PORT_ReadControl uint16_t data1 Port or port pin selection uint8_t data2 Control register selection uint16_t data3 Data storage location Read an I O port pin control setting data1 Use either one of the following definition values from 4 2 3 One port definition or One port pin definition data2 Select the register to be read PDL_IO_PORT_DIRECTION or Data direction PDL_IO_PORT_MODE or General or Peripheral I O mode control Open drain control PDE IO PORT INFE or See hardware manual for ports that this is available on PDL_IO_PORT_PULL_UP or Pull up control Drive capacity control POL IG OIR See hardware manual for ports that this is available on data3 The address where the register value shall be stored using one of the formats below Pin not PE1 open drain control
266. R_ELC_Control y tinclude r pdl elc h RPDL device specific definitions tinclude r pdl definitions h void func void uint8 t value R_ELC_ Read PDL ELC_PORT_B amp value y RENESAS Page 4 113 RX210 Group 4 R_ELC Write Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference Write to the ELC port buffer bool R_ELC_Write uint8_t data1 II Port uint8_t data2 Value Write to the ELC port buffer of the specified port data1 Port selection PDL_ELC_PORT_B or PDL_ELC_PORT_E Select the port whose buffer should be written to data2 Value to write True if all parameters are valid and exclusive otherwise false Event Link Controller R_ELC_Create R_ELC_Control e Ifan event occurs while updating a port with bit rotation enabled abnormal operation may occur include r pdl_elc h RPDL device specific definitions tinclude r pdl_definitions h void func void R_ELC_Write PDL_ELC_PORT_B OxAA y 2tENESAS Page 4 114 RX210 Group 5 R_ELC_ Control Synopsis Prototype Description 1 6 R20UT0708EE0211 Rev 2 11 Aug 01 2014 Control the ELC bool R_ELC_Control
267. R_INTC_CreateExtInterrupt PDL_INTC_NMI PDL INTC FALLING PDL INTC LVD2_ ENABLE NMI handler cpa 7 i Non Maskable Interrupt Digital Filter interrupt enable LOCO div 2 R_CPA Create 1 PDL CPA FILTER LOCO DIV 2 PDL CPA INTERRUPT RESET ENABLE PDL NO FUNC 0 5 FlagsNonMASKABLE true do 1 if FlagsNonMASKABLE break while 1 R20UT0708EE0211 Rev 2 11 Page 5 101 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples disable comparator A channel 1 if R_CPA Control 1 PDL CPA LVD CIRCUIT DISABLE false while 1 Maskable Interrupt Digital Filter interrupt enable LOCO div 2 R_CPA_Create 1 PDL CPA FILTER LOCO DIV 2 PDL CPA INTERRUPT RESET ENABLE PDL CPA MASKABLE INTERRUPT CPA1 handler 6 get status LVDiDET LVDiMON R_CPA_GetStatus amp FlagsStatus while 1 Comparator A channel 0 void CPAO handler void uint8 t FlagsStatus get status LVDiDET LVDiMON R_CPA_GetStatus amp FlagsStatus Toggle the LED state R_IO PORT Modify PDL IO POR L IO PORT XOR 1 R_IO PORT Modify PDL IO PORI L IO PORT XOR 1 Comparator A channel 1 void CPA1 handler void uint8 t FlagsStatus get status LVDiDET LVDiMON R_CPA_GetStatus amp FlagsStatus Toggle the LED state R_IO PORT Modify PDL IO PORI L IO PORT XOR 1 R_IO PORT Modify PDL
268. SABLE 32768 32768 32768 32768 32768 PDL_NO_DATA PDL CGC SUB 32768 Configure the HOCO settings PDL CGC _CLK_ HOCO CGC _HOCO 50000 PDL CGC BCLK DISABLE TA TA TA W a u e a a OY t the hoco as the system clock source R CGC Control PDL CGC_CLK_HOCO PDL_NO_DATA L CGC RTC TO B i Set the current time and enable the alarm R20UT0708EE0211 Rev 2 11 Page 5 37 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples R_RTC_Create PDL_RTC_24 HOUR MODE L RTC PIN RTCIC1 P31 FF114250 Automatic day of week 11 42 50 20140324 24 Mar 2014 L_NO_DATA Capture 0 RTC_CAPTURE EDGE FALLING RTC_CAPTURE FILTER ON DIV 1 Capture 1 DATA Capture 2 DATA Periodic Setup DATA Alarm time DATA Alarm date FUNC Alarm callback DATA Alarm priority FUNC Periodic callback DATA Periodic priority E E E ZZZZZZZ _ _ Dott a y a a a o DOOM Y UUUUUYUUUUUXx x OT sci lak teal chose ek E Z dF while 1 Read Capture status until see that an edge has been detected R_RTC_Read PDL_ RTC READ CAPTURE 1 amp flags amp time amp date if 1 flags amp BIT 0 bDetected true NOTE Variables time and date now hold the time when the edge was detected Figure 5 22 Example of
269. SCI_PIN_SCI5_CTS5_PCO PDL_SCI_PIN_SCI5_RTS5_PAG6 or PDL_SCI PIN_SCI5_RTS5_PCO PDL_SCI_PIN_SCI5_SS5_PA6 or PDL_SCI PIN_SCI5_SS5 PCO SCI5 SMISO5 SMOSI5 Valid when n 6 PDL_SCI_PIN_SCI6_RXD6_P01 or PDL_SCI_PIN_SCI6_RXD6_P33 or PDL_SCI_PIN_SCI6_RXD6_PBO PDL_SCI_PIN_SCI6_SMISO6_P01 or PDL_SCI_PIN_SCI6_SMISO6_P33 or PDL_SCI_PIN_SCI6_SMISO6 _PBO PDL_SCI_PIN_SCI6_SSCL6_P01 or PDL_SCI_PIN_SCI6_SSCL6_P33 or PDL_SCI_PIN_SCI6_SSCL6_PBO PDL_SCI_PIN_SCI6_TXD6_P00 or PDL_SCI_PIN_SCI6_TXD6_P32 or PDL_SCI_PIN_SCI6_TXD6_PB1 PDL_SCI_PIN_SCI6_SMOSI6_P00 or PDL_SCI_PIN_SCI6_SMOSI6_ P32 or PDL_SCI_PIN_SCI6_SMOSI6_PB1 PDL_SCI_PIN_SCI6_SSDA6_P00 or PDL_SCI_PIN_SCI6_SSDA6_P32 or PDL_SCI_PIN_SCI6_SSDA6_PB1 PDL_SCI_PIN_SCI6_SCK6_P02 or PDL_SCI_PIN_SCI6_SCK6_P34 or PDL_SCI PIN_SCI6_SCK6_PB3 PDL_SCI_PIN_SCI6_CTS6_PB2 or PDL_SCI_PIN_SCI6_CTS6_PJ3 PDL_SCI_PIN_SCI6_RTS6_PB2 or PDL_SCI_PIN_SCI6_RTS6_PJ3 PDL SCI PIN SCI6 SS6 PB2or PDL_SCI_PIN SCI6 SS6_PJ3 SCI6 SMISO6 SMOSI6 RENESAS Page 4 210 RX210 Group Description 5 6 Valid when n 7 4 Library Reference R20UT0708EE0211 Rev 2 11 Aug 01 2014
270. SCIn where n 0 to 12 data2 Not IIC Mode Control the channel If multiple selections are required use to separate each selection Select the process to be stopped Stop the transmission process PDL_SCI_STOP_TX If a reception process is active the transmit output will not become idle until the reception process has stopped Stop the reception process If a transmission process is active the receive error flags may be set erroneously These can be ignored and will be cleared when a new reception process is started PDL_SCI_STOP_RX The option PDL_SCI_STOP_TX_AND_RX can be used to select both processes If both processes are selected transmission and reception will stop immediately Generate a Space or Mark signal when idle Only applicable in Async and Async Multi Processor Modes ignored in other modes Set the idle output to Space logic 0 AO PAGE This can be used to generate a Break condition PDL_SCI_OUTPUT_MARK Set the idle output to Mark logic 1 e Error flag control PDL_SCI_CLEAR_RECEIVE_ERROR_FLAGS Try to clear the receive error flags e Manual SCK control PDL_SCI_GSM_SCK_STOP or Disable or enable the clock output can be used while PDL_SCI_GSM_SCK_START GSM mode is enabled data2 IIC Mode only Control the channel e Stop condition generation PDL_SCI_IIC_STOP A stop will be output on the bus e Clock Sync
271. SC_RCV_SWRS_ENABLE Read Same PDL_BSC_RCV_SWRD_ENABLE Write Different PDL_BSC_RCV_SWWS_ENABLE Write Same PDL_BSC_RCV_SWWD_ENABLE Different PDL_BSC_RCV_MRRS_ENABLE Read Same PDL_BSC_RCV_MRRD_ENABLE Read Different PDL_BSC_RCV_MRWS_ENABLE Write Same PDL_BSC_RCV_MRWD_ENABLE Multiplexed Different PDL_BSC_RCV_MWRS_ENABLE Read Same PDL_BSC_RCV_MWRD_ENABLE Write Different PDL_BSC_RCV_MWWS_ENABLE Write Same PDL_BSC_RCV_MWWD_ENABLE Different data4 e Error monitoring PDL_BSC_ERROR_ILLEGAL_ADDRESS_DISABLE or Disable or enable illegal PDL_BSC_ERROR_ILLEGAL_ADDRESS_ENABLE address access detection PDL_BSC_ERROR_TIME_OUT_DISABLE or Disable or enable bus time out PDL_BSC_ERROR_TIME_OUT_ENABLE detection func The function to be called when a bus error occurs Specify PDL_NO_FUNC if not required data5 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func Return value True if all parameters are valid and exclusive otherwise false Category Bus Controller Reference R_BSC_Set R_BSC_CreateArea R_BSC_Control Remarks e If required call R_BSC_Set before using this function e Call this function after all calls of function R_BSC_CreateArea e After calling this function use R_BSC_Control to start the external bus operation e Multifunction Pin Control registers are modified by this function Acallback function is executed b
272. SDA e SCL pin selection PDL_IIC_PIN_SCL or PDL_IIC_PIN SCL_DS Select the normal or DS pin for SCL True if all parameters are valid exclusive and achievable otherwise false Program example Category C Reference R_IIC_Create Remarks e Before calling R_IIC_Create call this function to configure the relevant pins RPDL definitions include r pdl iic h RPDL device specific definitions tinclude r pdl definitions h void func void Configure the applicable IIC pins R TIC Set PDL IIC PIN SDA PDL IIC PIN SCL y R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 237 RENESAS RX210 Group 4 Library Reference 2 R_IIC_Create Synopsis 12C channel setup Prototype bool R_IIC_Create uint8_t data1 Channel selection uint32_t data2 Channel configuration uint32_t data3 Detection configuration uint16_t data4 Slave address uint16_t data5 Slave address uint16_t data6 Slave address uint32_t data7 Transfer rate control uint32_t data8 Rise and fall time correction Description 1 3 data1 Select channel IICn where n 0 data2 Set up the selected C channel Configure the channel If multiple selections are required use to separate each selection The default settings are shown in bold Bus mode selection PDL_lIC_MODE_IIC or PDL_
273. SSDA9 PB7 7 Setup the SCI IIC channel R_SCI_Create CHANNEL SCI_IIC PDL SCI SYNC PDL SCI_IIC MODE PDL SCI_IIC DELAY SDA 20 21 9600 1 i Configure the DTC controller R_DTC Set PDL DTC ADDRESS FULL dtc_vector table y Set current EEPROM address IIC Buffer 0 EEPROM ADDRESS Use blocking function for this DTC will be used for the data part R_SCI_IIC Write R20UT0708EE0211 Rev 2 11 Page 5 71 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples HANNEL SCI_IIC DL SCI _IIC NOSTOP LAVE ADDRESS LA IC Buffer DL NO FUNC de Set flag data_received false Read data from current EEPROM address using DTC Start with an IIC Re start DIC om Rx R_DTC_Create PDL DTC NORMAL PDL DTC DESTINATION ADDRESS PLUS PDL DTC SOURCE ADDRESS FIXED PDL DTC SIZE 8 PDL DTC IRQ COMPLETE PDL_DTC_TRIGGER_RXI9 dtc_iicl_ rx transfer data uint8 t amp SCI9 RDR Source IIC Buffer Destination Data length is one less than we want to read as use R_SCI_IIC ReadlLastByte 4 PDL_NO_DATA i DTC on Tx To write the dummy data out Data length is 2 less than we want to read as first dummy byte is written out by R_SCI_IIC Read function and last one when we use R_SCI_IIC_ ReadLastByte R_DTC_Create PDL DTC NORMAL PDL DTC SOURCE ADDRESS FIXED PDL DTC DES
274. Source void DOC DODIR Destination a Transfer Count DATA COUNT Data length PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA Callback Done Callback done function 7 Interrupt priority i Enable and start the DMAC AC Control MAC CHANNEL DMAC_ENABL PDL DMAC START L NO PTR L NO PTR L NO DATA L NO DATA L NO DATA L NO DATA L NO DATA D P P P P p UUUOUU UU UU R20UT0708EE0211 Rev 2 11 Page 5 105 Aug 01 2014 RENESAS RX210 Group Wait for the DMAC to complete while false g bCallbackDone Read the result including checking for overflow R_DOC Read status result i static void Callback Done void g_bCallbackDone true Figure 5 56 Example of DOC R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS 5 Usage Examples RX210 Group 5 Usage Examples 5 27 Timer Pulse Unit This shows an example of using the Timer Pulse Unit Peripheral driver function prototypes include Yr pdl tpu h include r pdl cgc h RPDL device specific definitions include r pdl definitions h void main void uint8 t Flags uintl6 t General A uintl6 t General D Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Configure TPU pins R_TPU_Set
275. T 4 Port P4 PDL IO PORTE PortPE PDL_IO_ PORT 5 Port P5 PDL_IO PORT F PortPF PDL_IO PORT 6 Port P6 PDL_IO PORT H PortPH PDL_IO_ PORT 7 Port P7 PDL_IO PORT J Port PJ PDL_IO_PORT 8 Port P8 PDLIO PORT K Port PK PDL_IO_ PORT 9 Port P9 PDLIO PORTL PortPL I O port pin definitions Note Refer to the hardware manual for the ports which are available on the device that you have selected PDL_IO PORT 0 0 Port pin POo PDL_IO PORT_0 1 Port pin PO PDL_IO PORT 0 2 Port pin PO PDL_IO_PORT_0_3 Port pin PO PDL_IO PORT 0 5 Port pin POs PDL_IO_PORT_0_7 Port pin P07 PDL_IO PORT 12 Port pin P12 PDL_IO_PORT_1_3 Port pin P1 PDL_ IO PORT_1 4 Port pin P14 PDL_IO PORT 1_5 Port pin P15 PDL_IO_PORT_1_6 Port pin P16 PDL_IO_PORT_1_7 Port pin P17 PDL_IO PORT 2 0 Port pin P20 PDL_IO PORT 2 1 Port pin P2 PDL_IO PORT 2 2 Port pin P22 PDL_IO PORT 2 3 Port pin P2 PDL_IO PORT 2 4 Port pin P24 PDL_1O PORT 2 5 Port pin P25 PDL_IO PORT 2 6 Port pin P26 PDL_IO_PORT
276. TC The function to be called at the interval specified in R_DTC_Create func3 The function to be called if a receive error occurs Specify PDL_NO_FUNC to ignore errors In Polling Mode True if all parameters are valid and the operation completed OK false if a parameter was out of range or an error was detected In Non Polling mode True if all parameters are valid false if a parameter was out of range SCI R_SCI_Control R_SCI_GetStatus The maximum number of characters to be received or transmitted is 65535 e Wait until a transmission on the same channel is complete before calling this function e If no error callback function func3 is specified the error flags are cleared automatically to allow the reception process to complete Callback functions are executed by the interrupt processing function This means that no other interrupt can be processed until a callback function has completed In SPI master mode the slave s SS pin must be asserted before calling this function A general I O pin can be used for this see the I O Port API If using the DMAC or DTC this module does not know when the transfer has ended Therefore when the transfer has completed the user must call the R_SCI_Control function with options PDL_SCI_STOP_TX PDL_SCI_STOP_RxX to manually disable the transmission reception as appropriate e If a callback function is specified and the interrupt priority level is zero this function will return false
277. TCOUT pin Clock control PDL_RTC_CLOCK_STOP or PDL_RTC_CLOCK_START Stop or re start the clock 30 second adjustment control PDL_RTC_ADJUST_START Start the 30 second adjustment process Reset control PDL_RTC_RESET_START Start the reset process RENESAS Page 4 191 RX210 Group Description 2 4 R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference data2 Select the values to be changed To set multiple options at the same time use to separate each value If no change is required specify PDL_NO_DATA Select the time counters to be updated using values supplied in parameter data3 PDL_RTC_UPDATE_CURRENT_HOUR PDL_RTC_UPDATE_CURRENT_MINUTE PDL_RTC_UPDATE_CURRENT_SECOND All three can be selected using PDL_RTC_UPDATE_CURRENT_TIME Select the date counters to be updated using values supplied in parameters data3 and data4 PDL_RTC_UPDATE_CURRENT_YEAR All four can be selected using PDL_RTC_UPDATE_CURRENT_MONTH PDL_RTC_UPDATE_CURRENT_DATE PDL_RTC_UPDATE_CURRENT_DAY Parameter data3 is used for the day of the PDL_RTC_UPDATE_CURRENT_DOW week Select the alarm time counters to be updated using values supplied in parameter data5 PDL_RTC_UPDATE_ALARM_HOUR PDL_RTC_UPDATE_ALARM_MINUTE PDL_RTC_UPDATE_ALARM_SECOND All three can be selected using PDL_RTC_UPDATE_ALARM_TIME
278. TC_REG_DTCER_SCI12_RXI PDL_INTC_REG_DTCER_ ICO_RXI PDL_INTC_REG_DTCER_SCI12_TXI PDL_INTC_REG_DTCER_IICO_TXI PDL_INTC_REG_DTCER_TPU0O_TGIA PDL_INTC_REG_DTCER_TPU3_TGIA PDL_INTC_REG_DTCER_TPUO_TGIB PDL_INTC_REG_DTCER_TPU3_TGIB PDL_INTC_REG_DTCER_TPUO_TGIC PDL_INTC_REG_DTCER_TPU3_TGIC PDL_INTC_REG_DTCER_TPUO_TGID PDL_INTC_REG_DTCER_TPU3_TGID PDL_INTC_REG_DTCER_TPU1_TGIA PDL_INTC_REG_DTCER_TPU4_ TGIA PDL_INTC_REG_DTCER_TPU1_TGIB PDL_INTC_REG_DTCER_TPU4 TGIB PDL_INTC_REG_DTCER_TPU2_TGIA PDL_INTC_REG_DTCER_TPUS_TGIA PDL_INTC_REG_DTCER_TPU2_TGIB PDL_INTC_REG_DTCER_TPUS_TGIB R20UT0708EE0211 Rev 2 11 Page 4 29 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 8 R_INTC Read Synopsis Prototype Description Return value Category Reference Remarks Program example Read an interrupt register bool R_INTC_Read uint16_t data1 Register selection uint8_t data2 Data storage location Read an interrupt register and store the value data1 e The register to be read PDL_INTC_REG_IPL or Select the current CPU interrupt priority level or PDL_INTC_REG_IR_ register or Interrupt Request register or PDL_INTC_REG_IER register or Interrupt Request Enable register or PDL_INTC_REG_IPR_ register or Interrupt Priority register or PDL_INTC_REG_DTCER register DTC Activation Enable register data2 The location where the reg
279. TINATION ADDRESS FIXED PDL DTC_SIZE 8 PDL DTC IRQ COMPLETE PDL DTC TRIGGER TXI9 dtc_iicl tx transfer data SIIC Dummy value Source uint8_t amp SCI9 TDR Destination 3 Data length PDL_NO_DATA de Enable the DIC R_DTC Control PDL DTC START PDL NO PTR PDL NO PTR PDL NO PTR PDL NO DATA PDL NO DATA y Start the IIC Read R_SCI_IIC Read CHANNEL SCI_IIC PDL SCI IIC RESTART PDL SCI_IIC_DTC_TRIGGER_ENABL SLAVE ADDRESS PDL_NO DATA No data length as using DTC PDL NO DATA No buffer as using DTC CallbackRx de Wait for rx while data_received false Because using DMAC need to manually get the last byte This will also generate the stop condition R_SCI_ TIC ReadLastByte R20UT0708EE0211 Rev 2 11 Page 5 72 Aug 01 2014 stENESAS RX210 Group 5 Usage Examples CHANNEL SCI IIC SIIC Buffer 4 de Callback function for Rx static void CallbackRx void data_received true Figure 5 38 Example of SCI in IIC mode using DTC R20UT0708EE0211 Rev 2 11 Page 5 73 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 18 12C Bus Interface In the following examples the bus activity will be illustrated using the following format AA AA AAA From the master A Acknowledge SDA held low A Not Acknowledge SDA released high Fr
280. TOP_CH_1 or PDL_TPU_START_CH_1 PDL_TPU_STOP_CH_2 or PDL_TPU_START_CH_2 PDL_TPU_STOP_CH_3 or PDL_TPU_START_CH_3 PDL_TPU_STOP_CH_4 or PDL_TPU_START_CH_4 PDL_TPU_STOP_CH_5 or PDL_TPU_START_CH_5 Stop or start the count operation for the selected channels 0 Stop or start the count operation for the selected channels 1 Stop or start the count operation for the selected channels 2 Stop or start the count operation for the selected channels 3 Stop or start the count operation for the selected channels 4 Stop or start the count operation for the selected channels 5 True if all parameters are valid and exclusive otherwise false Timer Pulse Unit R_TPU_Set R_TPU_Create R_TPU_ControlChannel RPDL definitions include r pdl tpu h RPDL device specific definitions include r _pdl definitions h void func void Enable the counter on TPU channel 0 4 Disable the counter on TPU channel 1 5 R_TPU_ControlUnit 0 PDL TPU START CH O PDL TPU START CH 4 PDL TPU STOP CH 1 PDL TPU STOP CH 5 R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 314 RENESAS RX210 Group 6 R_TPU_Read Synopsis Prototype Description Return value Category Reference Remarks Read from timer channel registers bool R_TPU_Read uint8_t data1 uint8_t
281. TRIGGER_ENABLE or DMAC or DTC for data transmission PDL_SPI_DTC_TRIGGER_ENABLE and reception data3 The start address of the data to be transmitted The data must be stored as 32 bit values Specify PDL_NO_PTR if no data is to be transmitted or if the data content is not important or if the DMAC or DTC shall be used to handle the data transfer data4 The start address of the data to be received The data will be stored as 32 bit values Specify PDL_NO_PTR if no data is to be received or if the DMAC or DTC shall be used to handle the data transfer data5 The number of times that the command sequence will be executed The value should not be zero if the DMAC and DTC trigger are disabled func Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Return value Category Reference R20UT0708EE0211 Rev 2 11 Aug 01 2014 Transfer method Parameter Pollin PDL_NO_FUNC This function will handle the data transfer until g completion or an error occurs The function to be called when the transfer has completed or an error has Interrupts occurred DMAC or DTC The function to be called if an error has occurred or when the DMAC or DTC passes on the transfer interrupt data6 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for para
282. TROUGH_6 or PDL_MTU2_INT_SKIP_TROUGH_7 PDL_MTU2_INT_SKIP_CREST_DISABLE or PDL_MTU2_INT_SKIP_CREST_1 or PDL_MTU2_INT_SKIP_CREST_2 or PDL_MTU2_INT_SKIP_CREST_3 or PDL_MTU2_INT_SKIP_CREST_4 or PDL_MTU2_INT_SKIP_CREST_5 or PDL_MTU2_INT_SKIP_CREST_6 or PDL_MTU2_INT_SKIP_CREST_7 Disable TCNT underflow TCIV interrupt skipping or set the skip count between 1 and 7 Disable TGRA compare match TGIA interrupt skipping or set the skip count between 1 and 7 Dead time generation control applies only to complementary PWM modes PDL_MTU2_DEAD_TIME_DISABLE or PDL_MTU2_DEAD_TIME_ENABLE Disable or enable dead time generation e Waveform retention control applies only to complementary PWM modes PDL_MTU2_WAVEFORM_RETAIN_DISABLE or Disable or enable waveform output PDL_MTU2_WAVEFORM_RETAIN_ENABLE retention e Compare match clearing control applies only to complementary PWM mode 1 PDL_MTU2_CNT_CLEAR_CM_A_DISABLE or Disable or enable counter clearing on PDL_MTU2_CNT_CLEAR_CM_A_ENABLE TGRA compare match e Reset synchronised or complementary PWM control PDL_MTU2_PWM_RS_COMP_ENABLE Enable reset synchronised or complementary PWM mode e Register protection PDL_MTU2_ACCESS DISABLE Control access to the registers and PDL_MTU2_ACCESS ENABLE counters in channels 3 and 4 register_selection The
283. URE FILTER_ON_DIV_1 or PDL_RTC_CAPTURE FILTER_ON DIV_32 Configure the capture noise filter If enabling select the sampling period relative to the count source RENESAS Page 4 193 RX210 Group 4 Library Reference Description 4 4 data10 Configure the Capture 2 RTCIC2 pin options To set multiple options at the same time use to separate each value e Edge PDL_RTC_CAPTURE_EDGE_NONE or PDL_RTC_CAPTURE_EDGE_RISING or Select the edge that will trigger a capture PDL_RTC_CAPTURE_EDGE_FALLING or event PDL_RTC_CAPTURE_EDGE_BOTH Time Capture Noise Filter Control PDL_RTC_CAPTURE_FILTER_OFF or Configure the capture noise filter If PDL_RTC_CAPTURE_FILTER_ON_DIV_1 or enabling select the sampling period PDL_RTC_CAPTURE_FILTER_ON_DIV_32 relative to the count source data11 Configure the clock periodic interrupt e Periodic interrupt selection PDL_RTC_PERIODIC_DISABLE or PDL_RTC_PERIODIC_256_HZ or PDL_RTC_PERIODIC_128_HZ or PDL_RTC_PERIODIC_64_HZ or PDL_RTC_PERIODIC_32_HZ or PDL_RTC_PERIODIC_16_HZ or PDL_RTC_PERIODIC_8_HZ or PDL_RTC_PERIODIC_4_HZ or PDL_RTC_PERIODIC_2_HZ or PDL_RTC_PERIODIC_1_HZ or PDL_RTC_PERIODIC_2S The frequency or interval for periodic interrupt requests Return value True if all parameters are valid and exclusive otherwise false Category Real time clock Reference R_RTC_Create R_RTC_Read Re
284. UT0708EE0211 Rev 2 11 Page 4 266 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 4 2 24 CRC calculator 1 R_CRC_Create Synopsis Prototype Description Return value Category References Remarks Program example Configure the CRC calculator bool R_CRC_Create uint8_t data II Configuration Enable the CRC and set the operating conditions data Calculation options To set multiple options at the same time use to separate each value e Polynomial selection PDL_CRC_ POLY CRC 8or X X 4X41 PDL_CRC_POLY_CRC_16or X xX x 4 1 PDL_CRC POLY CRC CCITT x x x 1 Bit order PDL_CRC_LSB_FIRST or PDL_CRC_MSB FIRST Select LSB or MSB first operation True if all parameters are valid and exclusive otherwise false CRC None None RPDL definitions tinclude r pdl_crc h RPDL device specific definitions tinclude r pdl_definitions h void func void Set up the CRC in 8 bit mode with LSB first R_CRC_Create PDL CRC _POLY CRC_8 PDL_CRC_LSB FIRST R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 267 RENESAS RX210 Group 4 Library Reference 2 R_CRC_Destroy Synopsis Shut down the CRC calculator Prototype bool R_CRC_Destroy void No parameter is required
285. V_value Register value uinti6 _t TGRE_TGRW_value Register value uint16_t TGRF_value Register value uint16_t TADCOBRA_value Register value uint16_t TADCOBRB_value Register value Modify a timer channel s registers data1 The channel number n where n 0 to 5 control_setting The channel settings to be modified If multiple selections are required use to separate each selection Specify PDL_NO_DATA if no change is required e Counter stop start Valid for n 0 to 4 PDL_MTU2_STOP Stop the count operation PDL_MTU2_START Start the count operation e Counter stop Start Valid for n 5 PDL_MTU2_STOP_U PDL_MTU2_STOP_V PDL_MTU2_STOP_W PDL_MTU2_START_U PDL_MTU2_START_V PDL_MTU2_START_W Stop the count operation Start the count operation register_selection The channel registers to be modified If multiple selections are required use to separate each selection Specify PDL_NO_DATA if no register change is required The registers to be modified Forn 0to 4 PDL_MTU2_REGISTER_COUNTER Timer counter register TCNT PDL_MTU2_REGISTER_TGRA General register A PDL_MTU2_REGISTER_TGRB General register B PDL_MTU2_REGISTER_TGRC General register C Valid for n 0 3 or 4 PDL_MTU2_REGISTER_TGRD General register D Valid for n 0 3 or 4 PDL_MTU2_REGISTER_TGRE
286. W_CM_INV or PDL_TPU_A_OC_HIGH_CM_LOW or PDL_TPU_A_OC_HIGH or PDL_TPU_A_OC_HIGH_CM_INV or TIOCAn output disabled TIOCAn output low TIOCAn initial output low goes high at compare match TIOCAn initial output low toggles at compare match TIOCAn initial output high goes low at compare match TIOCAn output high TIOCAn initial output high toggles at compare match PDL_TPU_A_IC_RISING_EDGE or PDL_TPU_A_IC_FALLING_ EDGE or PDL_TPU_A_IC_BOTH EDGES or Input capture at TIOCAn rising edge Input capture at TIOCAn falling edge Input capture at TIOCAn both edges PDL_TPU_A_IC_TPU_COUNT_CLK or Input capture at TPU n 1 count clock count up or count down Invalid if TPU n 1 uses PCLK 1 Valid for n 0 and 3 PDL_TPU_A_IC_TPU_CM_IC Input capture at TPU n 1 TGRA compare match or input compare Valid for n 1 and 4 Input capture output compare control for register TGRB PDL_TPU_B_OC_DISABLED or PDL_TPU_B_OC_LOW or PDL_TPU_B_OC_LOW_CM_HIGH or PDL_TPU_B_OC_LOW_CM_INV or PDL_TPU_B_OC_HIGH_CM_LOW or PDL_TPU_B_OC_HIGH or PDL_TPU_B_OC_HIGH_CM_INV or TIOCBn output disabled TIOCBn output low TIOCBn initial output low goes high at compare match TIOCBn initial output low toggles at compare match TIOCBn initial output high goes low at compare match TIOCBn output high TIOCBn initial output high toggles at compare match PDL_TPU_B_IC_RISING_ED
287. W_IC PWM_LOW BOTH or Input capture at trough crest or both for low pulse width measurement PDL_MTU2_W_IC_PWM_HIGH_TROUGH or PDL_MTU2_W_IC_PWM_HIGH_CREST or PDL_MTU2_W_IC_PWM_HIGH_BOTH Input capture at trough crest or both for high pulse width measurement R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS Page 4 131 RX210 Group Description 8 9 R20UT0708EE0211 Rev 2 11 Aug 01 2014 noise_filter_operation Noise filter control for register NFCRn n 0 to 5 The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Noise filter control for register NFCRn 4 Library Reference PDL_MTU2_NF_A_U_DISABLEor PDL_MTU2_NF_A U ENABLE Enable or disable noise filter for MTIOCnA n 0 to 4 or TIOC5U n 5 PDL_MTU2_NF_B_V_DISABLEor PDL_MTU2_NF_B_V ENABLE Enable or disable noise filter for MTIOCnB n 0 to 4 or TIOCHV n 5 PDL_MTU2 NF C W DISABLE or PDL_MTU2_NF_C_W_ENABLE Enable or disable noise filter for MTIOCNC n 0 3 or 4 or TIOCSW n 5 Not valid for n 1 or 2 PDL_MTU2_NF_D_DISABLE or PDL_MTU2_NF_D ENABLE Enable or disable noise filter for MTIOCND n 0 3 or 4 Not valid forn 1 2 or 5 Noise filter clock select for register NFCRn PDL_MTU2_NF_PCLK_DIV_1 or PDL_MTU2_NF_PCLK_DIV_8 or PDL_MTU2_NF_PCLK_DIV_32 or PDL_MTU2_NF_PCLK_DIV_SRC Set the clock of the nois
288. XI PDL INTC REG IPR _SCI11 TXI PDL INTC REG IPR _SCI4 TEI PDL INTC REG IPR SCI11 TEI PDL_INTC_REG_IPR_SCI5_ERI PDL_INTC_REG_IPR_SCI12_ERI PDL_INTC_REG_IPR_SCI5_RXI PDL_INTC_REG_IPR_SCI12_RXI PDL_INTC_REG_IPR_SCI5 TXI PDL_INTC_REG_IPR_SCI12_TXI PDL INTC REG IPR _SCI5 TEI PDL INTC REG IPR SCI12 TEI PDL INTC REG IPR _SCI6 ERI PDL INTC REG IPR SCI12 SCIXO PDL_INTC_REG_IPR_SCI6_RXI PDL_INTC REG _IPR_SCI12_SCIX1 PDL_INTC_REG_IPR_SCI6_TXI PDL_INTC_REG_IPR_SCI6_TEI PDL INTC REG IPR TPUO TGIA PDL INTC REG IPR TPU3 TGIA PDL_INTC_REG_IPR_TPUO_TGIB PDL_INTC_REG_IPR_TPU3_TGIB PDL_INTC_ REG IPR _TPUO TGIC PDL_INTC_ REG IPR _TPU3_ TGIC PDL_INTC_ REG _IPR_TPUO TGID PDL_INTC_ REG IPR _TPU3 TGID PDL_INTC REG IPR TPUO TCIV PDL INTC REG IPR TPU3 TCIV PDL_INTC_ REG _IPR_TPU1_TGIA PDL_INTC_ REG IPR _TPU4 TGIA PDL_INTC_ REG _IPR_TPU1 TGIB PDL_INTC REG IPR _TPU4 TGIB R20UTO708EE0211 Rev 2 11 Page 4 28 Aug 01 2014 RENESAS RX210 Group 4 Library Reference
289. _16 or PDL_MTU2 CLK PCLK DIV 64 or The internal clock signal PCLKB 1 4 16 or 64 PDL_MTU2_CLK_PCLK_DIV_256 or PCLKB 256 Valid for n 1 3 and 4 PDL_MTU2_CLK_PCLK DIV_1024 or PCLKB 1024 Valid for n 2 3 and 4 PDL_MTU2_CLK_MTCLKA or MTCLKA pin input Valid for n 0 to 4 PDL_MTU2_CLK_MTCLKB or MTCLKB pin input Valid for n 0 to 4 PDL_MTU2_ CLK_MTCLKC or MTCLKC pin input Valid for n 0 or 2 PDL_MTU2_CLK_MTCLKD or MTCLKD pin input Valid for n 0 PDL_MTU2_CLK_CASCADE The overflow underflow signal from channel n 1 Valid forn 1 TCNT counter clock edge selection Valid for n 0 to 4 Not effective for n 1 and 2 in Phase Counting Mode PDL_MTU2_CLK_RISING or PDL_MTU2_CLK_FALLING or PDL_MTU2 CLK BOTH The TCNT counter clock signal shall be counted on rising falling or both edges TCNT counter clearing Valid for n 0 to 4 unless stated otherwise PDL_MTU2_CLEAR_DISABLE or Clearing is disabled PDL_MTU2_CLEAR_TGRA or Cleared by TGRA compare match or input capture PDL_MTU2_CLEAR_TGRB or Cleared by TGRB compare match or input capture PDL_MTU2_CLEAR_SYNC or Cleared by counter clearing on another channel configured for synchronous operation PDL_MTU2_CLEAR_TGRC or Cleared by TGRC compare match or input capture Valid for n 0 3 and 4 PDL_MTU2_CLEAR_TGR
290. _2 7 Port pin P27 PDL_IO PORT 3 0 Port pin P3o PDL_IO PORT 3 1 Port pin P3 PDL_IO PORT 3 2 Port pin P32 PDL_IO PORT 3 3 Port pin P3 PDL_IO PORT 3 4 Port pin P34 PDL_IO PORT 35 Port pin P35 PDL_IO PORT 3 6 Port pin P36 PDL_IO_PORT_3_7 Port pin P37 PDL_IO PORT 40 Port pin P4o PDL_IO_PORT_4 1 Port pin P4 PDL_IO PORT 4 2 Port pin P42 PDL_1O PORT 4 3 Port pin P43 PDL_IO PORT 44 Port pin P44 PDL_IO PORT 4 5 Port pin P4s PDL_IO PORT 4 6 Port pin P46 PDL_IO PORT 4 7 Port pin P47 PDL_IO PORT 50 Port pin P5o PDL_IO PORT_5 1 Port pin P5 PDL_IO PORT 5 2 Port pin P52 PDL_1O PORT 5 3 Port pin P53 PDL_IO PORT 5 4 Port pin P54 PDL_IO _PORT_5 5 Port pin P5s PDL_IO PORT 56 Port pin P56 PDL_IO PORT 60 Port pin P6o PDL_IO PORT 61 Port pin P6 PDL_IO PORT 6 2 Port pin P62 PDL_1O PORT 6 3 Port pin P6 PDL_IO PORT 64 Port pin P64 PDL_IO PORT 6_5 Port pin P65 PDL_IO PORT 66 Port pin P6s PDL_IO PORT 6_ 7 Port pin P67 PDL_IO PORT 7 0 Port pin P7o PDL_IO PORT_7_1 Port pin P7 PDL_IO PORT 7 2 PortpinP7 gt PDL_1O PORT 7 3 Port pin P73 PDL_IO PORT 7 4 Port pin P74 PDL_IO PORT 7 5 Port pin P75 PDL_IO PORT 7 6 Port pin P76 PDL_IO PORT 7 7 Port pin P77 PDL_IO PORT 8 0 Port pin P8o PDL_IO PORT 8 1 Port pin P8 PDL_IO PORT 8 2 Port pin P82 PDL_IO PORT 8 3 Port pin P83 PDL_IO PORT 8 6 Port pin P86 PDL_IO PORT 8 7 Port pin P87 PDL_IO PORT 9 0 Port pin P9o PDL_IO PORT_9 1 Port pin P9 PDL
291. _Buffer 10 Initialise the system clocks NOTE The code to initialise the system clock using R CGC Set is omitted here Set Channel 9 pin options R_SCI_Set 9 PDL SCI PIN SCI9 SSCL9 PB6 PDL SCI PIN SCI9 SSDA9 PB7 i Configure the SCI IIC Channel R_SCI_Create CHANNEL SCI_IIC PDL SCI SYNC PDL SCI IIC MODE PDL SCI IIC DELAY SDA 20 21 9600 1 7 Set up data buffer for the write Address in EEPROM IIC Buffer 0 EEPROM ADDRESS Data to write IIC Buffer 1 EEPROM VALUE TIC write R_SCI_IIC Write CHANNEL SCI_IIC PDL_NO DATA SLAVE ADDRESS 2 IIC Buffer PDL_NO_ FUNC i Wait for 5ms while the EEPROM updates R_CMT_CreateOneShot 0 0 5E 3 PDL NO FUNC R20UT0708EE0211 Rev 2 11 Page 5 67 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 7 Confirm this write worked by reading back the data from the EEPROM 1 Set current EEPROM address IIC Buffer 0 EEPROM ADDRESS R_SCI_IIC Write CHANNEL SCI_IIC PDL NO DATA SLAVE ADDRESS 1 IIC Buffer PDL_NO_FUNC i 2 Read data from current address R_SCI_ TIC Read CHANNEL SCI_IIC PDL_NO_DATA SLAVE ADDRESS 1 IIC Buffer PDL_NO_FUNC de Confirm the value written is the same as the value read if IIC Buffer 0 l EEPROM VALUE User Handle Erro
292. _DISABLE or PDL_INTC_LVD1_ENABLE Disable or enable the NMI signal when a low voltage detection 1 interrupt occurs PDL_INTC_LVD2_DISABLE or PDL_INTC_LVD2_ENABLE Disable or enable the NMI signal when a low voltage detection 2 interrupt occurs RENESAS Page 4 15 RX210 Group Description 2 2 Return value Category Reference Remarks Program example R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference func The function to be called when a valid condition is detected Specify PDL_NO_FUNC if no IRQn interrupt is required A function must be specified for the NMI data3 The IRQn interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func This value does not apply to the NMI and is ignored True if all parameters are valid and exclusive otherwise false Interrupt control R_INTC_SetExtInterrupt Ifan IRQn pin will be used function R_INTC_SetExtInterrupt must be called before any use of this function e The selected interrupt is enabled automatically e Please see the notes on callback function use in 86 e The NMI callback function should not return It should stop operation or reset the system e If the NMI interrupt fails to initialise this function will return false RPDL definitions include r p
293. _DTC_Control uint32_t data1 Control options uint32_t data2 Transfer data start address void data3 Source start address void data4 Destination start address uint16_t data5 Transfer count uint8_t data6 1 Block size Modify the operation of the Data Transfer Controller data1 Control the operation Stop Start control PDL_DTC_STOP or PDL_DTC_START Enable re enable or suspend DTC transfers The transfer registers to be modified using the selected parameters PDL_DTC_UPDATE_SOURCE po ae Address register using parameter PDL_DTC_UPDATE_DESTINATION etek Address register using parameter PDL_DTC_UPDATE_COUNT The Transfer Count register using parameter data5 PDL_DTC_UPDATE_BLOCK_SIZE _ The Block Size register using parameter data6 e Transfer trigger control When the transfer count specified in R_DTC_Create is completed the DTC will ignore further interrupts from that trigger source If you require the interrupt to trigger another transfer specify the trigger used in the relevant call of R_DTC_Create data2 If transfer registers are to be modified specify the start address of the transfer data area the same as that declared in R_DTC_Create lfno registers are to be modified specify PDL_NO_PTR data3 The new source start address The valid range depends on the address mode short or full Specify PDL_NO_PTR if not required data4 The new d
294. _HIGH_CM_INV or MTIOCnB output disabled MTIOCnB output low MTIOCnB initial output low goes high at compare match MTIOCnB initial output low toggles at compare match MTIOCnB initial output high goes low at compare match MTIOCnB output high MTIOCnB initial output high toggles at compare match PDL_MTU2_B_IC_RISING_EDGE or PDL_MTU2_B_IC_FALLING EDGE or PDL_MTU2_B IC_ BOTH EDGES or Input capture at MTIOCnB rising edge Input capture at MTIOCnB falling edge Input capture at MTIOCnB both edges PDL_MTU2_B_IC_COUNT or Input capture at channel n 1 up count or down count Valid only for n 0 PDL_MTU2_B_IC_CM_IC Input capture at channel n 1 TGRC compare match or input capture Valid only for n 1 Cascade input capture control Valid in cascade mode for n 1 Channel n forms the higher 16 bits and channel n 1 forms the lower 16 bits PDL_MTU2_CASCADE AL_IC_INC_H PDL_MTU2_CASCADE_AL_IC_EXC_H or Exclude or include pin MTIOCnA in the TGRA input capture conditions for channel n 1 PDL_MTU2_CASCADE BL_IC_INC_H PDL_MTU2_CASCADE_BL_IC_EXC_Hor Exclude or include pin MTIOCnB in the TGRB input capture conditions for channel n 1 PDL_MTU2_ CASCADE_AH_IC_INC_L PDL_MTU2_CASCADE_AH_IC_EXC_L or Exclude or include pin MTIOC n 1 A in the TGRA input capture conditions for channel n PDL_MTU2_CASCADE_BH_IC_INC_L PDL_MTU2_CASCADE_BH_IC_EXC_L
295. _IO PORT 9 2 Port pin P92 PDL_IO PORT 9 3 Port pin P93 R20UT0708EE0211 Rev 2 11 Aug 01 2014 2tENESAS Page 4 33 RX210 Group PDL_IO PORT A0 Port pin PAo PDL_IO_PORT_A 1 Port pin PA PDL_IO PORT A 2 Port pin PA2 PDL_IO PORT A 3 Port pin PA PDL_IO PORTA 4 Port pin PA PDL_IO PORT A 5 Port pin PAs PDL_IO PORT A 6 Port pin PAs PDL_IO PORT_A 7 Port pin PA PDL_IO PORT_B_0 Port pin PBo PDL_IO_PORT_B_1 Port pin PB PDL_IO PORT B 2 Port pin PB2 PDL_IO_PORT_B_3 Port pin PBs PDL_IO PORT B 4 Port pin PBa PDL_IO PORT B 5 Port pin PBs PDL_IO PORT B6 Port pin PBe PDL IO _PORT_B 7 Port pin PB7 PDL_IO PORT C 0 Port pin PCo PDL_IO_PORT_C_1 Port pin PC PDL_IO PORT C 2 Port pin PC2 PDL_IO_PORT_C_3 Port pin PCs PDL_IO PORT C 4 Port pin PCy PDL_1O PORT C 5 Port pin PCs PDL_IO PORT C 6 Port pin PCs PDL_IO_PORT_C 7 Port pin PC PDL_IO PORT D0 Port pin PDo PDL_IO_PORT_D_1 Port pin PD PDL_IO PORT D 2 Port pin PD PDL_IO_PORT_D_3 Port pin PDs PDL_IO PORT D 4 Port pin PDs PDL_1O PORT D 5 Port pin PDs PDL_IO PORT D 6 Port pin PDs PDL_IO
296. _P_PHASE_1_HIGH_LOW or PDL_MTU2_OUT P_PHASE_1_LOW_HIGH MHOC PDL_MTU2_OUT_N_PHASE_1_HIGH LOWor yrioc3p PDL_MTU2_OUT_N PHASE 1 LOW_HIGH PDL_MTU2_OUT_P_PHASE_2 HIGH LOWor mriocan PDL_MTU2_OUT_P_PHASE 2 LOW_HIGH PDL_MTU2_OUT_N_PHASE_2 HIGH LOWor urocac PDL_MTU2_OUT_N PHASE 2 LOW HIGH PDL_MTU2_OUT_P_PHASE_3 HIGH LOWor rocas PDL_MTU2 OUT P PHASE 3 LOW_HIGH PDL_MTU2_OUT_N_PHASE_3 HIGH LOWor MTIOCAD PDL_MTU2_OUT_N PHASE 3 LOW_HIGH Write access control applies only to reset synchronised or complementary PWM modes PDL_MTU2_OUT_LOCK_ENABLE Prevent further changes to the phase output control Toggle output control applies only to reset synchron ised or complementary PWM modes PDL_MTU2_OUT_TOGGLE_ENABLE or Enable or disable toggle output PDL_MTU2_OUT_TOGGLE DISABLE synchronised with the PWM cycle RENESAS Page 4 140 RX210 Group Description 3 4 R20UT0708EE0211 Rev 2 11 Aug 01 2014 buffer_control The buffer control settings to be modified All settings are optional If multiple selections are required use to separate each selection 4 Library Reference Output level buffer control applies only to reset synchronised or complementary PWM modes Set the output control to be transferred to the output PDL_MTU2_OUT_BUFFER_P_PHASE_1_LOW or
297. _TOLERANCE or PDL_CAC_LIMIT_REGISTER Parameters data4 and data5 will contain either the tolerance or the limit register values R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS Page 4 61 RX210 Group Description 2 2 Return value Category References R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference data2 Choose the CACREF input settings Use to separate each selection If the CACREF input is not required specify PDL_NO_DATA e External input configuration PDL_CAC_CACREF_PORT_A 0 or Select the pin to be used for signal CACREF PDL_CAC_CACREF_PORT_C_7 or Parameter data3 contains the frequency of PDL_CAC_CACREF_PORT_H_0 the signal applied to this pin PDL_CAC_CACREF_FILTER_DISABLE or PDL_CAC_CACREF_FILTER_DIV_1 or PDL_CAC_CACREF_FILTER_DIV_4 or PDL_CAC_CACREF FILTER DIV_16 If used the CACREF signal can be unfiltered or sampled using the clock to be measured divided by 1 4 or 16 data3 If the CACREF input will be used specify the input clock frequency in Hz Use PDL_NO_DATA if not required data4 Specify either a the maximum positive deviation for the measured clock as a percentage or b the upper count limit for the measured clock where the maximum value is 65535 data5 Specify either a the maximum negative deviation for the measured clock as a percentage or b the lower
298. a now in the Rx Buffer store it in the data_storage array static void StoreData uint16_t count uintl6 t index 0 R20UT0708EE0211 Rev 2 11 Aug 01 2014 ztENESAS Page 5 89 RX210 Group 5 Usage Examples Update data_storage_index data_storage index Rx Buffer index count index Store any data while count 0 data_storage data_storage index Rx Buffer index count index data _ storage index if data storage index STORAGE SIZE 1 Wrap around data storage index 0 Figure 5 48 Configure the I C channel and write 3 data bytes to the first locations R20UT0708EE0211 Rev 2 11 Page 5 90 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 19 Serial Peripheral Interface 5 19 1 Master operation with multiple slaves This is an example of Serial Peripheral Interface usage where one SPI master communicates with four SPI slaves Each slave requires different data bit lengths RSPCKB A SPI channel 0 MOSIB A MISOB A Master SSLBO A SSLB1 A SSLB2 A SSLB3 A Slave 0 8 bit data words Slave 1 9 bit data words Slave 2 15 bit data words 7 Slave 3 24 bit data words Figure 5 49 shows how data of appropriate bit lengths is transferred to each SPI slave Commands 0 to 3 are executed in sequence with each command asserting the appropriate SSL pin Peripheral driver function prototypes include r pdl_cgc h include r pal s
299. ae PDL_SCI_PARITY_ODD Select even or odd parity bit Block transfer mode selection PDL_SCI_BLOCK_MODE_OFF or c Block i d PDL SCI BLOCK MODE ON ontrol Block transfer mode GSM mode selection PDL_SCI_GSM_MODE_OFF or PDL SCI GSM MODE ON Control GSM mode SCKn pin output control Note how the default option changes depending upon the mode In Normal Mode the default is an I O Pin In GSM Mode the default is Fixed Low Normal mode GSM mode PDL_SCI_SCK_OUTPUT_OFF or I O pin Not applicable PDL_SCI_SCK_OUTPUT_LOW or Not applicable Fixed low PDL_SCI_SCK_OUTPUT_ON or Outputs the bit clock PDL_SCI_SCK_OUTPUT_HIGH Not applicable Fixed high R20UT0708EE0211 Rev 2 11 Page 4 215 Aug 01 2014 RENESAS RX210 Group Description 4 4 Return value 4 Library Reference data3 Select the SCI transfer rate See the Remarks section for the maximum rate that the device can support The format may be either The transfer bit rate in bits per second bps The clock division values will be calculated using this value This format is valid only when the on chip baud rate generator is selected as the data clock source in parameter data2 Or the following using to separate each selection e b31 b30 b24 b23 b0 4 0 A value between 256 0x100 and 16 776 960 OxFFFFOO that is nearest to the expected transfer bit rate
300. age 1 15 Aug 01 2014 RENESAS RX210 Group 1 Introduction 1 3 5 Recommended initialisation code The RX tool chain has a designated function for MCU initialisation HardwareSetup During the MCU initialisation phase it is recommended that the following functions are placed in this function Note that the file resetprg c supplied when a new project is created requires editing to remove the comment identifiers for the two lines below extern void HardwareSetup void HardwareSetup 1 Initialisation of pins that are not available For pins that are not available on the selected MCU package type set the control registers to the recommended values using R_IO_PORT_NotAvailable This function can be called even if the largest device has been selected This will allow for the user s code to be ported to another project that does use a smaller MCU package 2 Initialisation of the sub clock oscillator if not used If the sub clock oscillator will not be used it should be put into a stable state Please refer the program in Section 5 15 2 R20UT0708EE0211 Rev 2 11 Page 1 16 Aug 01 2014 RENESAS RX210 Group 1 4 Document structure The drivers are summarised in section 2 and explained in detail in section 4 Section 5 provides usage examples Section 6 provides details which are specific to the RX CPU R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS 1 Introduction Page 1 17 RX210 Group
301. alse IC R_CGC_Set R_IIC_Set R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 240 RENESAS RX210 Group 4 Library Reference Remarks Function R_CGC_Set must be called with the current clock source selected before using this function Function R_IIC_Set must be called before any use of this function This function configures each I C pin that is required for operation It also disables the alternative modes on those pins The 7 or 10 bit slave addresses should use the format b15 b8 b7 b1 bO 7 bit address b15 b11 b10 b1 bO 10 bit address The timing limits depend on the frequency of the internal reference clock IRC Transfer _ rate 1 t rise t ant ICBRH Di gc ICBRL Di rc The maximum transfer rate is given when ICBRH ICBRL 0 the minimum when ICBRH ICBRL 31 The absolute limits with zero rise and fall times are frcike MHz fire 12 5 12 32 8 f 1 195 kbps to 187 5 kbps to 500 kbps to 16 0 125 kbps to TERS 6 25 Mbps 6 0 Mbps Mbps 4 00 Mbps f 2 97 7 kbps to 93 75 kbps to 250 kbps to 8 00 62 5 kbps to PERKE 3 13 Mbps 3 0 Mbps Mbps 2 00 Mbps f 4 48 8 kbps to 46 875 kbps 125 kbps to 4 00 31 3 kbps to S 1 56 Mbps to 1 5 Mbps Mbps 1 00 Mbps f 8 24 4 kbps to 23 4 kbps to 62 5 kbps to 15 6 kbps to id 781 kbps 750 kbps 2 00 Mbps 500 kbps f 16 12 2 kbps to 11 71 kbps to 31 3 kbps to 7 81
302. ange the day to the 23rd R_RTC_Control L NO DATA L RTC UPDATE CURRENT_DOW PDL RTC UPDATE CURRENT DAY FF000000 00000023 L NO DATA L NO DATA L NO DATA L NO DATA L NO DATA L NO DATA L NO DATA W g y a a g A a O g g D D x x D D D D D D D R20UT0708EE0211 Rev 2 11 Page 4 195 Aug 01 2014 RENESAS RX210 Group 4 R_RTC Read Synopsis Prototype Description Return value R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference Read the Real time clock status flags and counters bool R_RTC_Read uint8_t data1 uint8_t data2 uint32_t data3 uint32_t data4 II Specify what to read A pointer to the flags storage location 11 A pointer to the data storage location A pointer to the data storage location Read the Clock counters registers and status flags data1 Specify what to read PDL_RTC_READ_CURRENT or PDL_RTC_READ_ALARM or PDL_RTC_READ_CAPTURE_0 or PDL_RTC_READ_CAPTURE_1 or PDL_RTC_READ_CAPTURE_2 Specify which time to read data2 The format of data2 is dependent upon data1 Format if datal PDL_RTC_READ CURRENT The clock status shall be stored in the following format Specify PDL_NO_PTR if the flags are not to be read b7 b6 b5 b4 Mode Interrupt requests 0 12 hour Carry e Alarm dll 1 Occurred b3 b2 b1 bO S
303. annel dedicated sample and hold circuits do not operate PDL_ADC_12_CH_SAMPLE_AND_HOLD_ENABLE should not be specified for any channel The double trigger can not be selected if any of the following are true a Continuous scan mode is selected b Internal reference voltage is selected c Synchronous trigger is not enabled d Diagnostic mode is enabled Make sure sampling time calculated or specified for channel O and self diagnosis are the same RPDL definitions include r pdl adc 12 h RPDL device specific definitions include r pdl definitions h void func void Configure ANOOO R_ADC_ 12 CreateChannel r DL ADC 12 CH GROUP A PDL ADC 12 CH ADSSTR CALCULATE E 6 aol R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 278 RENESAS RX210 Group 4 Library Reference 4 R_ADC 12 Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example Shut down the ADC unit bool R_ADC_12_Destroy uint8_t data ADC unit selection Put the ADC into the Power down state with minimal power consumption data Select the ADC unit to be shut down This must always be 0 True if a valid unit is selected otherwise false 12 bit ADC e This function includes a 1ms delay to allow the ADC to stop any current scan cycle RPDL
304. annels that are no longer required 2 Disabling a channel 3 Reading the status flag R20UT0708EE0211 Rev 2 11 Page 2 31 Aug 01 2014 RENESAS RX210 Group 2 Driver 2 32 Data Operation Circuit Driver The driver functions support the use of the DOC module providing the following operations 1 Configuring and enabling the DOC 2 Disabling the DOC 3 Controlling operation including switching between comparison addition and subtraction modes 4 Writing data to the DOC 5 Reading result from DOC R20UTO708EE0211 Rev 2 11 A Page 2 32 Aug 01 2014 RENESAS RX210 Group 2 Driver 2 33 Timer Pulse Unit Driver The driver functions support the use of the twelve 16 bit timers providing the following operations 1 I O pin configuration 2 Configuration for use including e Access to all control bits e Automatic interrupt control 3 Disabling channels that are no longer required and enabling low power mode 4 Control of a timer 5 Control of a unit 6 Reading the status and registers of a timer R20UT0708EE0211 Rev 2 11 Page 2 33 Aug 01 2014 RENESAS RX210 Group 3 Types and definitions 3 Types and definitions 3 1 Data types This section describes the data types used in this library For details about the setting values refer to the section 4 2 Description of Each API The header files stdint h and stdbool h are included with the Renesas RX compiler Table 1 Data types
305. arameters are valid and exclusive otherwise false Category Timer Pulse Unit Reference Remarks The Stop operation is executed at the start of thisfunction The Start operation is executed at the end Therefore both options can be selected together with other changes in one function call R20UT0708EE0211 Rev 2 11 Page 4 312 Aug 01 2014 RENESAS RX210 Group 4 Library Reference Program example RPDL definitions include r_pdl _tpu h RPDL device specific definitions include r pdl definitions h void func void Load the counter on channel TPU channel 0 R_TPU_ControlChannel 0 PDL TPU COUNTER OxFFDD R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS Page 4 313 RX210 Group 4 Library Reference 5 R_TPU_ControlUnit Synopsis Prototype Description Return value Category Reference Remarks Program example Control a timer unit bool R_TPU_ControlUnit uint8_t data1 Unit selection uint16_tdata2 Simultaneous control Simultaneous start stop specified channels data1 The unit number n where n 0 data2 Simultaneous stop start control All selections are optional If multiple selections are required use to separate each selection e Counter stop start control for unit 0 PDL_TPU_STOP_CH_0 or PDL_TPU_START_CH_0 PDL_TPU_S
306. arameters for CMTO triggered transfers R_DTC_Control PDL DTC UPDATE DESTINATION PDL DTC UPDATE COUNT dtc_cmt0 transfer data PDL_NO_PTR void 0x0000BBO00 100 PDL NO DATA Page 4 108 2tENESAS RX210 Group 4 Library Reference 5 R_DTC_GetStatus Synopsis Prototype Description Return value Category Reference Remarks R20UT0708EE0211 Rev 2 11 Aug 01 2014 Check the status of the Data Transfer Controller bool R_DTC_GetStatus uint32_t data1 Transfer data start address uint16_t data2 Status flags pointer uint32_t data3 Current source address pointer uint32_t data4 Current destination address pointer uint16_t data5 Current transfer count pointer uint8_t data6 Current block size count pointer Return status flags and current channel registers data1 The start address of the transfer data area If all parameters data3 data4 data5 and data6 are not required specify PDL_NO_PTR data2 The status flags shall be stored in the following format Specify PDL_NO_PTR if the status flags are not required b15 b14 b8 b7 bO O Idle 1 A transfer is in progress 0 The trigger vector valid only when bit b15 1 data3 Where the current source address shall be stored Ignored if data1 is set to PDL_NO_PTR If this value is not required specify PDL_NO_PTR data4 Where
307. ard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or systems manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass des
308. asure clock settings Use to separate each selection e Reference signal selection PDL_CAC_REFERENCE_MAIN or PDL_CAC_REFERENCE_SUB_CLOCK or PDL_CAC_REFERENCE_HOCO or PDL_CAC_REFERENCE_LOCO or PDL_CAC_REFERENCE_IWDTLOCO or PDL_CAC_ REFERENCE _CACREF Select the main clock oscillator sub clock oscillator high speed on chip oscillator low speed on chip oscillator or IWDT low speed on chip oscillator or input to pin CACREF as the reference signal PDL_CAC_REFERENCE_RISING or PDL_CAC_REFERENCE_FALLING or PDL_CAC_REFERENCE_BOTH Select rising edges falling edges or both rising and falling edges to be valid PDL_CAC_REFERENCE_DIV_32 or PDL_CAC_REFERENCE_DIV_128 or PDL_CAC_REFERENCE_DIV_1024 or PDL_CAC_REFERENCE_DIV_8192 Divide the reference signal by 32 128 1024 or 8192 Not required when the CACREF input is selected as the reference signal Measured clock selection and division PDL_CAC_MEASURE_MAIN or PDL_CAC_MEASURE_SUB_CLOCK or PDL_CAC_MEASURE_HOCO or PDL_CAC_MEASURE_LOCO or PDL_CAC_MEASURE_IWDTLOCO Select the main clock oscillator sub clock oscillator high speed on chip oscillator low speed on chip oscillator or IWDT low speed on chip oscillator for measurement PDL_CAC_MEASURE_DIV_1 or PDL_CAC_MEASURE_DIV_4 or PDL_CAC_MEASURE_DIV_8 or PDL_CAC_MEASURE DIV_32 Divide the clock to be measured by 1 4 8 or 32 e Limit value calculation PDL_CAC_LIMIT
309. ay 5 0x23 0x48 0x59 0x60 OxFE id func void Send 5 bytes to device 0x0A0 on channel 0 using polling R_IIC_MasterSend 0 PDL NO DATA 0x0A0 data_array 5 PDL NO FUNC 0 R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 245 2tENESAS RX210 Group 4 Library Reference 5 R_IIC_MasterReceive Synopsis Prototype Description Read data from a slave device bool R_IIC_MasterReceive uint8_t data1 Channel selection uint16_t data2 Channel configuration uint16_t data3 Slave address uint8_t data4 Data start address uint16_t data5 Receive threshold void func Callback function uint8_t data6 Interrupt priority level Read data over an 1 C channel and store it data1 Select channel IICn where n 0 data2 Configure the channel The default setting is shown in bold Specify PDL_NO_DATA to use the defaults e Slave address size override Specify this option if 10 bit address mode is to be PDL_IIC_10_BIT_SLAVE_ADDRESS used instead of 7 bit mode when the slave address is lt FFh DMAC DTC trigger control PDL_IIC_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_IIC_DMAC_TRIGGER_ENABLE or DMAC or DTC when a data byte is PDL_IIC_DTC_TRIGGER_ENABLE received data3 The address of the slave device data4 The start address of the storage area for the expected data
310. b clock oscillator PDL_CGC_CLK_PLL Phase locked loop PLL circuit data2 Clock control selection All selections are optional If no change is required specify PDL_NO_DATA If multiple selections are required use to separate each selection BCLK pin output control ignored if the device package does not support the external bus PDL_CGC_BCLK_ENABLE or PDL CGC BCLK DISABLE Enable or disable the BCLK pin output e Low speed on chip oscillator control PDL_CGC_LOCO_ENABLE or PDL_CGC_LOCO_DISABLE Enable or disable the LOCO e High speed on chip oscillator control PDL_CGC_HOCO_ENABLE or PDL_CGC_HOCO_DISABLE Enable or disable the HOCO e High speed on chip oscillator power control PDL_CGC_HOCO_POWER_ON or PDL_CGC_HOCO_POWER_OFF Control the HOCO power supply e Main clock oscillator control PDL_CGC_MAIN_ENABLE or PDL_CGC_MAIN_DISABLE Enable or disable the main clock oscillator e Main clock Oscillation Stop Detection control PDL_CGC_OSC_STOP_ENABLE or Enable without or with interrupt request output PDL_CGC_OSC_STOP_INTERRUPT or or disable the oscillation stop detection function PDL_CGC_OSC_STOP_DISABLE for the main clock oscillator e Main clock Oscillation Stop Detection flag control PDL_CGC_OSC_STOP_CLEAR FLAG ae to clear the oscillation stop detection data3 Clock control selection All selections are optional If no chan
311. be ignored if a value change is not requested Data use Parameter type The timer period in seconds or double The timer frequency in Hz or double The value to be put in the selected register uint16_t True if all parameters are valid and exclusive otherwise false Compare Match Timer R_CMT_Create e R_CMT_Create must be used first to configure the channel R20UT0708EE0211 Rev 2 11 Aug 01 2014 The Stop operation is executed at the start of this function The Start operation is executed at the end Therefore both options can be selected together with a value change in one function call To avoid register access conflicts or invalid calls to the callback function use this method when changing any value Ifthe CMCNT register value is changed to the same value as the CMCOR register the CMCNT register will be set to 0 Page 4 183 RENESAS RX210 Group Program example RPD L definitions include r pdl_cmt h RPD L device specific definitions include r pdl definitions h void func void Change channel 2 to Ims period R_CMT Control R20UT0708EE0211 Rev 2 11 Aug 01 2014 2 1E 3 RENESAS 4 Library Reference E PDL CMT STOP PDL CMT PERIOD PDL CMT START Page 4 184 RX210 Group 4 Library Reference 5 R_CMT_Read Synopsis Prototype Description Return value Categ
312. brary Reference II Configuration selection PDL_WDT_TIMEOUT_1024 or PDL_WDT_TIMEOUT_4096 or PDL_WDT_TIMEOUT_8192 or PDL_WDT_TIMEOUT_16384 Time out period specified in cycles of the divided clock as specified in the Clock Selection below Clock selection PDL_WDT_PCLK_DIV_4 or PDL_WDT_PCLK_DIV_64 or PDL_WDT_PCLK_DIV_128 or PDL_WDT_PCLK_DIV_512 or PDL_WDT_PCLK_DIV_2048 or PDL_WDT_PCLK_DIV_8192 The division ratio for the internal clock signal PCLKB MCU reset control PDL_WDT_TIMEOUT_RESET or PDL_WDT_TIMEOUT_NMI When the WDT times out select if either a Reset or an NMI interrupt will be generated Window Start Position PDL_WDT_WIN_START_25 or PDL_WDT_WIN_START_50 or PDL_WDT_WIN_START_75 or PDL_WDT_WIN_START_100 The window start position specified as a percentage of the down counter 0 is when the down counter would underflow Selecting 100 is equivalent to no window start position Window End Position PDL_WDT_WIN_END_0 or PDL_WDT_WIN_END_ 25 or PDL_WDT_WIN_END_50 or PDL_WDT_WIN END 75 The window end position specified as a percentage of the down counter 0 is when the down counter would underflow Hence specifying 0 is equivalent to no window end position True if all parameters are valid and exclusive otherwise false Watchdog Timer R_MCU_OFS R_INTC_CreateExtInterrupt RENESAS Page 4 199 RX210 Group 4
313. c naar n nc c naar nn cn naar nn cn nana nnccnns 5 95 5 22 5 23 5 24 5 25 5 26 5 27 5 28 5 29 5 30 6 6 1 6 2 10 bit Digital to Analog Converter oocoonoccccconocccccononcncnononcncnnnoncnccnno nn nr cano nn A EATA 5 97 Temperature Sensor seis it pct ictus iaa 5 98 Comparator Ass cries ee eerie eee aes A rade ee ta eee ae des 5 100 Comparatom Ba dd ts atta duh Nes reed 5 103 Data Operation Circuit meringis e ad eens nda denen 5 105 Timer Pose LN ii ai hace ited tas A os ete dt ne Ge eee eed 5 107 Multi Function Timer Pulse Unit oocooonnnccccnnnoccccnnnoncccnononc cono nono canon ocn rra cn naar rca rra 5 109 Register Writer Protection esner italia lada diri 5 111 MCU Operation san aa ii td eh Se ee A A eee ee 5 112 RA Specific NOES iconos o cient llosa whee Micvhld e cd a A 6 1 Interrupts and processor MOE cccecceceeeececeeceeeeeeeeeeeaeaeceeeeeeeeeaaaneeceeeeecasaeaeeeseeeeesessnnieeeeeeeeeenes 6 1 Interrupts and DSP instructions 0 cccccceeeeececee cece eeeeeeceeeae cece ee eeeeceaeaeeeeeeesescaeaeeeeeeeseeeesieeeeeeeetenes 6 1 Revision HISTORY A Raa saa ace dagen Ge ag AE eee te 1 RX210 Group 1 Introduction 1 Introduction The Renesas Peripheral Driver Library RPDL is a unified API for controlling the peripheral modules on the microcontrollers made by Renesas Electronics Target MCU Figure 1 1 System configuration with all peripherals supported by RPDL
314. cable SPI pins R_SPI_Set PDL_SPI_RSPCKA_PA5 PDL SPI SSLA0 PA4 PDL SPI SSLA2 PAL y PDL SPI MOSIA PA6 PDL SPI SSLA1 PAO PDL SPI SSLA3 PA2 PDL SPI MISOA PA7 R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS Page 4 255 RX210 Group 4 Library Reference 2 R_SPI_Create Synopsis Configure an SPI channel Prototype bool R_SPI_Create uint8_t data1 Channel selection uint32_t data2 Channel configuration uint32_t data3 Data format uint32_t data4 Extended timing control uint32_t data5 Bit rate or register value Description 1 3 Set up the selected SPI channel data1 Select channel SPIn where n 0 only data2 Configure the channel mode and connection settings If multiple selections are required use to separate each selection The default settings are shown in bold Connection mode PDL_SPI_MODE_SPI_MASTER or PDL_SPI_MODE_SPI_MULTI_MASTER or The required SPI four wire or Clock PDL_SPI_MODE_SPI_SLAVE or synchronous three wire operation PDL_SPI_MODE_SYNC_MASTER or connection type PDL_SPI_MODE_SYNC_SLAVE e Reception control PDL_SPI_FULL_DUPLEX or PDL_SPI_TRANSMIT_ONLY Enable or disable reception operations e Pin control If output signal SSLx where x 0 1 2 or 3 is used call function R_SPI_Set to select the respective output pin
315. calculation PDL_TMR_PERIOD or The parameters data3 and data4 will contain either PDL_TMR_FREQUENCY period and pulse width or frequency and duty cycle e Output pin control PDL_TMR_OUTPUT_ENABLE or Enable or disable the periodic output on pin TMOn PDL_TMR_OUTPUT_DISABLE For 16 bit operation the pin shall be TMO2 when n 1 e Counter stop start PDL_TMR_STOP or PDL_TMR_START Disable or re enable the counter clock source data3 The new period or frequency This will be ignored if a timing change is not requested data4 The new pulse width or duty cycle This will be ignored if a timing change is not requested True if all parameters are valid and exclusive otherwise false Timer TMR R_TMR_CreatePeriodic e See the remarks for R_TMR_CreatePeriodic Page 4 173 RENESAS RX210 Group Program example RPD RPD L definitions include r_pdl_tmr h L device specific definitions include r pdl definitions h void func void Change timer TMR1 to 600ns period R_TMR ControlPeriodic y R20UT0708EE0211 Rev 2 11 Aug 01 2014 PDL 1 PDL 1 MR TMR1 MR PERIOD 600E 9 100E 9 RENESAS 4 Library Reference 100ns pulse width Page 4 174 RX210 Group 4 Library Reference 10 R_TMR_ReadChamnel Synopsis Prototype Description Return value Ca
316. can be used In this example Timer channel 0 is configured to provide pulses on pin TMOO with a pulse width of 200 ticks of PCLKB and a duty cycle of 50 Note that the output transitions and counter clearing occur after the compare match has occurred So the values for compare match A and compare match B should be 1 less than the required count Peripheral driver function prototypes include r pdl_tmr h include r pdl definitions h void main void Configure TMRO input and output pins R_TMR Set 0 PDL TMR TMRO TMOO PB3 Configure TMRO to clear on a compare match A output 1 at a compare match A and output 0 at a compare match B R_TMR CreateChannel 0 PDL TMR CLK PCLK DIV 1 PDL TMR CLEAR CM A PDL TMR OUTPUT HIGH CM A PDL TMR OUTPUT LOW CM B 0 200 1 200 2 1 PDL_NO_FUNC PDL_NO_FUNC PDL_NO_FUNC Figure 5 17 Example of Pulse Output code Counter value Figure 5 18 Example of pulse output operation R20UT0708EE0211 Rev 2 11 Page 5 30 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 14 Compare Match Timer Figure 5 19 shows an example of Compare Match Timer usage One channel is used to generate interrupts at regular intervals Peripheral driver function prototypes include r pdl cmt h include r pdl cgc h include r pdl io port h include r pdl intc h RPDL device speci
317. ce Remarks Program example Read from MTU registers bool R_MTU2_ReadUnit uint8_tdata1 Unit selection uint16_t data2 A pointer to the data storage location uint8_t data3 11 A pointer to the data storage location Read any of the timer unit s counter registers data1 The unit number n where n 0 data2 A pointer to where the Timer subcounter register TCNTS value shall be stored Specify PDL_NO_PTR if it is not required data3 Where the Timer Interrupt Skipping Counter register TITCNT value shall be stored Specify PDL_NO_PTR if it is not required True if all parameters are valid and exclusive otherwise false Multi function Timer Pulse Unit None None RPDL definitions include r pdl_mtu2 h RPDL device specific definitions include r pdl definitions h uint16 t Sub count uint8 t Skip count void func void Read the counter registers for unit 0 R_MTU2_ ReadUnit 0 amp Sub count amp Skip count y R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 147 RENESAS RX210 Group 4 Library Reference 4 2 15 Port Output Enable 1 R_POE Set Synopsis Prototype Description 1 2 Configure the Port Output Enable module bool R_POE_Set uint32_t data1 Input configuration selection uint16_t data2 Input POEn pin selection uint16_t data3 Output configurat
318. channel 3 and 4 pins in the high impedance state PDL POE SHORT _MTIOC4BD_A Select the MTU channel I O pin pairs that shall be PDL_POE _SHORT_MTIOC4AC_A controlled by the short detection response software PDL_POE_SHORT_MTIOC3BD_A control or the oscillation stop detection flag True if all parameters are valid and exclusive otherwise false Port Output Enable R_POE_Control R_POE_GetStatus R_MTU2_Set i i Do not select MTU pins that are not used Use R_POE_GetStatus to get the oscillation stop detection flag If event is received from the ELC the target pin is placed to the high impedance state Not all pins are available on all device package sizes RPDL definitions nclude r pdi poe h RPDL device specific definitions nclude r pdl definitions h void func void Configure POE pins 0 and 3 R POE Set PDL POE 0 MODE EDGE PDL POE 3 MODE LOW 128 PDL POE 0 PORT D 7 PDL POE 3 PORT D 4 PDL NO DATA Page 4 149 RENESAS RX210 Group 2 R_POE Create Synopsis Prototype Description Return value Category Reference Remarks R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference Configure the Port Output Enable event handling bool R_POE_Create uint8_t data1 Input configuration selection void f
319. cified for parameter func1 func2 The function to be called at the periodic interval Specify PDL_NO_FUNC if not required data2 The periodic interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func2 True if all parameters are valid and exclusive otherwise false Real time clock R_CGC_Set R_CGC_Control R_MCU_OFS Remarks Program example R20UT0708EE0211 Rev 2 11 Aug 01 2014 The function is called only at warm start up This module is not available on the 48 pin package RPDL definitions tinclude r pdl _rtc h RPDL device specific definitions tinclude r pdl definitions h void alarm function void void func void start RIC R_RTC_CreateWarm alarm function 15 PDL NO FUNC PDL NO DATA Page 4 198 RENESAS RX210 Group 4 2 19 1 R_WDT Set Synopsis Prototype Description Return value Category Reference R20UT0708EE0211 Rev 2 11 Aug 01 2014 Watchdog Timer Configure the Watchdog timer bool R_WDT_Set uint32_t data Set up and start the Watchdog timer data Configure the timer To set multiple options at the same time use to separate each value The default settings are shown in bold Time out selection 4 Li
320. ck function is specified then interrupts will be automatically enabled After calling a callback function the DOC flag is automatically cleared R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS Page 4 296 RX210 Group 4 Library Reference Program example RPDL definitions include r pdl doc h RPDL device specific definitions include r pdl definitions h void Callback void void func void Setup DOC in addition mode R_DOC_Create PDL DOC_MODE ADD 0 Callback 15 R20UT0708EE0211 Rev 2 11 Page 4 297 Aug 01 2014 RENESAS RX210 Group 2 R_DOC_Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example Disable the Data Operation Circuit bool R_DOC_Destroy void Disable and enable the DOC module stop state True DOC include r pdl doc h RPDL device specific definitions include r pdl definitions h void func void R_DOC Destroy R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS 4 Library Reference Page 4 298 RX210 Group 4 Library Reference 3 R_DOC_Control Synopsis Prototype Description Return value Category References Remarks Control the Data Operation Circuit bool R_DOC_Control uint8_t data1 Con
321. condition for the independent watchdog timer to stop counting applied at the time of a transition to all module clock stop mode using a reset from the independent watchdog timer to release the chip from all module clock stop mode is impossible because the independent watchdog timer is stopped The peripheral Create functions bring modules out of the clock stop state as required The peripheral Destroy functions put modules into the clock stop state as required When All Module Clock Stop mode is cancelled the peripherals that were active when that mode was entered will be re activated MCU Versions A and C do not support operating power modes PDL_LPC_MIDDLE_SPEED_MODE_2A or PDL_LPC_MIDDLE_SPEED_MODE_2B If using MCU version B and not using the PLL then to reduce power consumption the PLL power can be disabled using function R_CGC_Control with option PDL_CGC_PLL_DISABLE If the frequency of ICLK is gt 32MHz then High speed operating mode must be used so do not change to a different operating mode If entering Software Standby Mode and using SCI in Smart Card Mode then the SCK pin must be kept at the idle level by controlling it as a general IO pin Do not try to change operating mode if ROM Program Erase mode is set or a mode transition is already in progress This function will return false if this is detected RPDL definitions include r pdl lpc h RPDL device specific definitions tinclude r pdl_de
322. control PDL_CAC CLEAR FREQUENCY _ERROR PDL_CAC CLEAR _MEASUREMENT Clear any selected flag PDL_CAC CLEAR _OVERFLOW e Operation control PDL_CAC DISABLE Stop the measurement operation PDL_CAC_ENABLE Re start the measurement operation data2 Operation control options All selections are optional If multiple selections are required use to separate each selection If no selections are required specify PDL_NO_DATA Reference signal selection PDL_CAC_REFERENCE_MAIN or PDL_CAC_REFERENCE_SUB_CLOCK or PDL_CAC_REFERENCE_HOCO or PDL_CAC_REFERENCE_LOCO or PDL_CAC_REFERENCE_IWDTLOCO or PDL_CAC_REFERENCE_CACREF Select the main clock oscillator sub clock oscillator high speed on chip oscillator low speed on chip oscillator or IWDT low speed on chip oscillator or input to pin CACREF as the reference signal e Reference signal edge selection PDL_CAC_REFERENCE_RISING or PDL_CAC_REFERENCE_FALLING or PDL_CAC_REFERENCE_BOTH Select rising edges falling edges or both rising and falling edges to be valid e Reference signal division selection PDL_CAC_REFERENCE_DIV_32 or PDL_CAC_REFERENCE_DIV_128 or PDL_CAC_REFERENCE_DIV_1024 or PDL_CAC_REFERENCE_DIV_8192 If an internal clock is used as the reference signal divide it by 32 128 1024 or 8192 Ignored if the CACREF input is selected Measured clock selection
323. ction double data3 Period frequency or register data void func Callback function uint8_t data4 Interrupt priority level Set up a Compare Match Timer channel data1 The channel number n where n 0 1 2 or 3 data2 Configure the timer To set multiple options at the same time use to separate each value The default settings are shown in bold e Clock calculation The parameter data3 will specify the timer period PDL_CMT_PERIOD or The counter clock source and compare match value will be calculated by this function The parameter data3 will specify the timer frequency PDL_CMT_FREQUENCY or The counter clock source and compare match value will be calculated by this function Select the internal clock signal PCLKB 8 32 128 or 512 as the counter clock source The parameter data3 will be the register CMCOR value PDL_CMT_PCLK_DIV_8 or PDL_CMT_PCLK_DIV_32 or PDL_CMT_PCLK_DIV_128 or PDL_CMT_PCLK_DIV_512 Counter start control PDL_CMT_START or PDL_CMT STOP Enable or disable the starting of the timer count operation e DMAC DTC trigger control PDL_CMT_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_CMT_DMAC_TRIGGER_ENABLE or DMAC or DTC when a compare match PDL_CMT_DTC_TRIGGER_ENABLE occurs data3 The data to be used for the register value calculations Data use Parameter type The timer period in seconds or double T
324. cuit bool R_DOC_Create uint8_t data1 Configuration uint16_tdata2 Output value void func Callback function uint8_t data3 Interrupt priority level Enable the DOC module and set the operating conditions data1 Operation Mode PDL_DOC_COMPARISON_MATCH or PDL_DOC_COMPARISON_MISMATCH or PDL_DOC_MODE_ADD or PDL_DOC_MODE SUBTRACT Specify the mode of operation data2 This meaning of this parameter depends upon the Operation Mode Operation Mode Description Comparison The comparison value Addition The initial output value before any additions are made Subtraction The initial output value before any subtractions are made func The function to be called when a DOC interrupt is generated Specify PDL_NO_FUNC if no callback function is required data3 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for func True if all parameters are valid and exclusive otherwise false DOC None In Addition Mode an interrupt is generated if the result of the addition exceeds FFFFh e In Subtraction Mode an interrupt is generated if the result of the subtraction is less than zero In Comparison Mode an interrupt is generated when the comparison criteria Match or Mismatch is met This function brings the DOC module out of the power down state e Ifa callba
325. d 0x0000AA00 void 0x0000BBOO 10 PDL NO DATA PDL NO DATA PDL NO DATA PDL NO DATA PDL NO FUNC R20UT0708EE0211 Rev 2 11 Page 4 94 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 2 R_DMAC_ Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example Disable the DMA controller bool R_DMAC_Destroy uint8_t data Channel number Shutdown the DMAC module data The channel number n where n 0 to 3 True if the shutdown succeeded otherwise false DMA controller R_DMAC_ Create e If all channels have been suspended the DMAC module will be shut down Disabling the DMAC module will also shut down the DTC If another peripheral is being used to trigger a DMA transfer stop the triggers from that peripheral using Control or Destroy for that peripheral before calling this function RPDL definitions tinclude r pdl_dmac h RPDL device specific definitions tinclude r pdl_definitions h void func void Shutdown channel 2 R_DMAC Destroy 2 i R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS dia RX210 Group 4 Library Reference 3 R_DMAC_ Control Synopsis Prototype Description 1 2 R20UT0708EE0211 Rev 2 11 Aug 01 2014 Control the DMA controller
326. d channel 9 as the slave The master transmits data to the slave The slave receive function call uses interrupts to call a callback function on completion Peripheral driver function prototypes include r pdl sci h include r pdl cgc h include r pdl inton RPDL device specific definitions include r pal definitions h SCI channel selection define MASTER CHANNEL 6 define SLAVE CHANNEL 9 Rx complete flag volatile uint8 t data received Callback function prototype static void SCI9RxFunc void volatile uint8 t rx _buffer 5 void main void Initialise the system clocks NOTE The code to initialise the system clock using R CGC Set is omitted here Set Master Channel 6 pins R SCI Set 6 PDL SCI PIN SCI6 RXD6 PBO PDL SCI PIN SCI6 TXD6 PB1 PDL SCI PIN SCI6 SCK6 PB3 y Set Slave Channel 9 pins R SCI Set 9 PDL SCI PIN SCI9 RXD9 PB6 PDL SCI PIN SCI9 TXD9 PB7 PDL SCI PIN SCI9 SCK9 PB5 Create Master Channel R SCI Create MASTER CHANNEL PDL SCI_ SYNC PDL SCI RX DISCONNECTED PDL SCI CLK INT_OUT 19200 1 Create Channel slave NOTE Even though using an external clock the driver needs to know the expected baud rate Bit 31 is set to signify not generating baud R SCI_Create SLAVE CHANNEL PDL SCI_SYNC PDL SCI TX DISCONNECTED PDL SCI _CLK_EXT 0x80000000 1
327. d here Set Channel 6 pin options R SCI Set 6 PDL SCI PIN SCI6 SMISO6 PBO PDL SCI PIN SCI6 SMOSI6 PB1 PDL SCI PIN SCI6 SCK6 PB3 PDL SCI PIN SCI6 SS6 PB2 i Create SPI master R_SCI_Create 6 PDL SCI_SYNC PDL SCI SPI MODE PDL SCI RX DISCONNECT PDL SCI CLK INT_OUT 19200 1 y Start sending data R_SCI_SPI Transfer 6 PDL NO DATA 5 12345 SCLEX PDL NO DATA PDL NO FUNC PDL NO FUNC 7 Wait for data to be sent while data_sent false Close this channel R_SCI Destroy 6 static void SCItx void data_sent true Figure 5 35 Example of SCI in SPI mode R20UT0708EE0211 Rev 2 11 Page 5 66 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 17 9 SCI in IIC Mode This shows the setting of SCI channel 9 in IIC mode and then a write and read to an IIC EEPROM PDL functions include r pdl _sci h include r pal cgc h include r pdl cmt h PDL device specific definitions include r pdl definitions h SCI IIC Channel define CHANNEL SCI_IIC 9 IIC Slave address of EEPROM define S AVE ADDRESS OxA0 Address in EEPROM where we will write a byte define EEPROM ADDRESS 0x01 Value to be written to the EEPROM define EEPROM VALUE OxAA void main void Data Buffer volatile uint8 t IIC
328. d port or pin is specified the operation of the function cannot be guaranteed The input buffer for the specified port or pin must be switched on see R_IO_PORT_Set RPDL definitions include r pdl io port h RPDL device specific definitions tinclude r _pdl definitions h void IoHandlerl void void IoHandler2 void void func void Call function IoHandlerl if port pin P05 is high R_IO_ PORT Compare PDL IO PORT 0 5 1 IoHandler1 Call function IoHandler2 if port 6 reads as 0x55 R_IO_ PORT Compare PDL IO PORT 6 0557 IoHandler2 RENESAS es RX210 Group 4 Library Reference 7 R_IO_PORT_Modify Synopsis Prototype Description Return value Category References Remarks Program example Modify the pin states on an I O port bool R_IO_PORT_Modify uint16_t data1 Output port or port pin selection uint16_t data2 Logical operation uint8_t data3 1 Modification value Read the output state of an I O port or I O port pin modify the result and write it back to the port data1 Use either one of the following definition values from 4 2 3 One port definition or One port pin definition data2 The logical operation to be applied to the port or port pin PDL_IO_PORT_AND or PDL_IO_PORT_OR or Select between AND amp OR or Exclusive OR PD
329. das 4 178 1 EAO DD EEE I E E E E A E T EA A E EE 4 178 2 R CMT CreateOne Shot rones ee a a cide a aeea aa aaa eaan aeara 4 180 3 CROM DESTOY iraniar Ea E dada 4 182 Ayy R CMT A aee eb aa aa e a a aa aae eea ea aaa eaa aariaa 4 183 So S O D E E ET o O A E E E 4 185 4218 Realtime ClO CK 32 t fabs ea aa r aaa a a aaa aa Aaa aaa aeaa aaa a aa riae 4 186 1 URSRT GC Create idas ti ai aaa 4 186 2 RIRTCADOSMOY ita tdo 4 190 3 CRERTO CONO ita id A A AAA AA ti di 4 191 49 ORORTC Read id it lc Ii A id A a ia 4 196 5 R RTC Create VW sii li E AA title 4 198 4 2 19 Watchdog TINEri ahaaa acest dde 4 199 dy R WDT Sete sie t id A saat ac dean A ib taeda 4 199 2 REWDTUCONtTOL ct did ad etl 4 201 3 Re WDT Read id id decadent A A AAA AAA tie 4 202 4 2 20 Independent Watchdog TiMeTF ooooocccnnnoncccnnnoccccnononcnncnnonnncnnno cnn c canon nn rro rca r nan nr ran rar 4 203 1 ARAWIDT Seti acallar lit It tit A db tit ta 4 203 2 CREW DT 2G ONUU OM gence a O O See Read tee as ta 4 205 3 AA DT RAG a 245 TS Li A hens ats ON eee ges tees edo 4 206 4 2 21 Serial Communication Interface cceccececceceeeeeeeeeceaeceeeeeeeseneaeaeceeeeeseseaaeeeeeeeeeseeseneeeeees 4 207 OD REO CIES Cte ees acento ag te EE eine hee eae ee ts A Aa ee ade lee tea gay 4 207 2 RSC s Create cis sine RR 4 213 3 RESCI Destroy ota 4 218 Ay IR SCI SONG EEE tne eee ag a aches ny 4 219 5 Re OCIS RECCIVG 32 45 fire teat a tela 4 222 6 RSC SPSS
330. defaults DMAC DTC trigger control PDL_SCI_IIC_DMAC_DTC_TRIGGER_DISABLE or PDL_SCI_IIC_DMAC_TRIGGER_ENABLE or PDL_SCI_IIC_DTC_TRIGGER_ENABLE Disable or enable activation of the DMAC or DTC for the data stage e Slave Address Size PDL_SCI_IIC_7_BIT_SLAVE_ADDRESS or PDL_SCI_IIC_10 BIT_SLAVE_ADDRESS Specify the slave address width e Repeated Start PDL_SCI_IIC_RESTART The transfer will start with a re start rather than the default behaviour of a start condition e Stop Condition selection PDL_SCI_IIC_NOSTOP By default the transfer will end with a stop condition Select this option to prevent the stop condition being generated data3 Slave address either 7 or 10 bits use the format as specified here b15 b8 b7 b1 bO 7 bit address b15 b11 b10 b1 bO 10 bit address data4 The number of data bytes that must be transferred before the function completes or the callback function is called If the DMAC or DTC shall be used to handle the received data specify PDL_NO_DATA data5 The start address of the buffer that contains the data to be written Specify PDL_NO_PTR if not transmitting data or if no data shall be processed by this function e g if the DMAC or DTC shall be used to send the data Page 4 228 RENESAS RX210 Group Description 2 2 4 Library Reference func Specify PDL_NO_FUNC
331. definitions include r pdl adc 12 h RPDL device specific definitions include r pdl definitions h void func void Shut down the ADC unit R_ADC_ 12 Destroy 0 R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 279 RENESAS RX210 Group 4 Library Reference 5 R_ADC_12 Control Synopsis Prototype Description Return value Category Reference Remarks Program example Start or stop an ADC unit bool R_ADC_12_Control uint8_t data Conversion unit control Controls start stop operation of the specified ADC data To select multiple options at the same time use to separate each value e On off control PDL_ADC 12 0 ON or Start a software triggered conversion or re enable the trigger PDL_ADC 12 0_OFF Stop the conversion and disable all triggers e Control the CPU during the ADC conversion Stop the CPU when the scan conversion process starts PBL ADE 12 CPUOFF The CPU will re start when any valid interrupt occurs True if all parameters are valid and exclusive otherwise false 12 bit ADC For single scan mode the ADC will stop automatically when the conversion is complete Do not select CPU Off unless there is any interrupt to wake up the CPU RPDL definitions include r pdl adc 12 h RPDL device specific definitions
332. definitions tinclude r pdl_cmt h RPDL device specific definitions tinclude r pdl_definitions h void func void Configure C R_CMT Create 0 PDL CMT_ PERIOD 10E 6 PDL_NO_FUNC 0 y T channel 0 for 10us operation Configure CMT channel 1 for 1kHz operation R_CMT Create T D D Saoka g nl Configure CMT channel 2 using register values R_CMT Create L_CMT_FREQUE 3 L NO FUNC NCY ay PDL CMT PCLK DIV 32 Ox55AA PDL NO FUNC 0 R20UTO708EE0211 Rev 2 11 Page 4 179 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 2 R_CMT_CreateOneShot Synopsis Prototype Description Return value Category Reference R20UT0708EE0211 Rev 2 11 Aug 01 2014 Configure a CMT channel as a one shot event bool R_CMT_CreateOneShot uint8_t data1 Timer channel selection uint16_t data2 Configuration selection double data3 Period void func II Callback function uint8_t data4 Interrupt priority level Set up a Compare Match Timer channel and start the timer data1 The channel number n where n 0 1 2 or 3 data2 Configure the timer The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Control the CPU during the one shot operation PDL_CMT_CPU_ON or Allow the CPU to
333. device specific definitions include r pdl definitions h void NMI handler lpc void void main void const uint8 t data_to_save Hello World 1234567890 abcdefghi uint8 t data_to_restore R_ PDL LPC BACKUP AREA SIZE uint32 t status flags Check if recover from deep software standby amp what caused the exit R_LPC_GetStatus amp status flags i Restore data if recovering from deep software standby if status flags amp 0x00800000 0 Read data from the backup registers R_LPC_ReadBackup data_to restore R PDL LPC BACKUP AR i Configure the NMI pin P35 R_INTC_CreateExtInterrupt PDL_INTC_NMI PDL_INTC_FALLING NMI handler lpc 7 y Allow a falling edge on NMI to cancel deep software standby R_LPC Create DL LPC EXT BUS HI Z PDL LPC IO DELAY L NO DATA LPC CANCEL NMI FALLING L NO DATA L NO DATA L NO DATA L NO DATA y Write data into the backup registers R_LPC WriteBackup data_to save R PDL LPC BACKUP AR i Enter deep software standby mode R_LPC_Control PDL LPC MODE DEEP SOFTWARE STANDBY An internal reset will occur when exiting from deep software standby The program counter will not return to here while 1 R20UT0708EE0211 Rev 2 11 Page 5 13 Aug 01 2014 RENESAS RX210 Grou
334. dl_intc h RPDL device specific definitions tinclude r pdl_definitions h Callback function void CallBackFunc void void func void Configure the IR L interrupt R_INTC_CreateExtInterrupt PDL INTC IRQ1 PDL _ INTC FALLING CallBackFunc 7 y Configure the NMI pin R_INTC_CreateExtInterrupt PDL_INTC_NMI PDL_INTC_FALLING CallBackFunc 15 Configure the NMI triggered by the WDT only no NMI pin R_INTC_CreateExtInterrupt PDL INTC NMI PDL INTC WDT ENABLE CallBackFunc PDL NO DATA RENES Page 4 16 RX210 Group 4 Library Reference 3 R_INTC_CreateSoftwarelnterrupt Synopsis Enable use of the software interrupt Prototype bool R_INTC_CreateSoftwarelnterrupt uint8_t data1 Configuration void func II Callback function uint8_t data2 Interrupt priority level Description Configure and enable the software interrupt data1 Choose the pin settings The default setting is shown in bold e DTC trigger control PDL_INTC_DTC_SW_TRIGGER_DISABLE or Disable or enable activation of the DTC PDL_INTC_DTC_SW_TRIGGER_ENABLE when a software interrupt is generated func The function to be called when a valid condition is detected Specify PDL_NO_FUNC if no interrupt is required data2 The interrupt priority level Select between 1 lowest priority and
335. dress offset using parameter data7 PDL DMAC UPDATE REPEAT SOURCE Source address extended repeat area using a parameter data8 Destination address extended repeat PDL_DMAC_UPDATE_REPEAT_DESTINATION i z area using parameter data9 data3 The new source address Specify PDL_NO_PTR if not required data4 The new destination address Specify PDL_NO_PTR if not required data5 The transfer count value Specify PDL_NO_DATA if not required data6 The repeat or block size for each transfer Valid between 0 and 1023 0 1024 units Ignored in normal mode Specify PDL_NO_DATA if not required RENESAS ae RX210 Group Description 2 2 Return value Category Reference Remarks R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference data7 The address offset value The range is from 16 777 215 to 16 777 216 This value is ignored if the offset function is not selected Specify PDL_NO_DATA if not required data8 The source address extended repeat value The value can be any power of 2 from 2027 Specify PDL_NO_DATA if not required data9 The destination address extended repeat value The value can be any power of 2 from 2 to 27 Specify PDL_NO_DATA if not required True if all parameters are valid and exclusive otherwise false DMA controller R_DMAC_ Create e The Software trigger control is va
336. e to separate each selection Each selection is optional If a selection is not made the control setting will be left unchanged Direction control PDL_IO_PORT_INPUT or PDL_IO_PORT_OUTPUT Input or output e Output type control See hardware manual for ports that this is available on PDL_IO_PORT_TYPE_CMOS or Select CMOS push pull output PDL_IO_PORT_TYPE_NMOS or NMOS open drain PMOS Available PDL_IO_PORT_TYPE_PMOS or PMOS open drain or on pin PE1 only PDL_IO_PORT_TYPE_HI_Z high impedance e Input pull up resistor control PDL_IO_PORT_PULL_UP_ON or PDL_IO_PORT_PULL_UP_OFF On or off e Drive capacity control PDL_IO_PORT_DRIVE_NORMAL or Normal or high current drive PDL_IO_PORT_DRIVE_HIGH Valid for ports 1 to 3 5 Ato E Hand J Return value True if all parameters are valid and exclusive otherwise false Category I O port References R_IO_PORT_NotAvailable Remarks Ensure that the specified functions are valid for the selected port pin The data direction and mode registers may be modified by other driver functions Take care to not overwrite existing settings e Pin P35 is fixed as an input and cannot be modified All pins that are not available on the selected package can be set to the required state using the R_IO_PORT_NotAvailable function Program example RPDL definitions include r pdl_io port h
337. e Detection Circuit Driver rariora EA rE E R A E EAT rre 2 8 2 9 Clock Frequency Accuracy Measurement Circuit DriVeF ooooonnncccnnnoncccnnnancccnononcccnnnanccnnnnonc nc nnnnncncnnns 2 9 2 10 Low Power Consumption Driver ccccceceeeeeececceeeeeeeeeeeceaeceeeeeeeseceaaeeeeeseeesecaaeceeeeeeesessicaneeeees 2 10 2 11 Register Write Protection Driver aieri rrearen nono ccnnnrrc cnn narrar rca rr 2 11 2 12 Bus Controller Driver cotorra di and nd nie at dela nde 2 12 2 13 DMA Controller DVA di td 2 13 2 14 Data Transfer Controller Driver c ccccceceeeeeeeecceeeeeeesececeaeeeeeeeeesecaaeceeesesesesenaeeeeeeeeesessucaseeeees 2 14 2 15 Event Link Comtrolle tia ss occ ct coa aaa ti ten seid antic icc tia tine de cece laastcl cadbaecnd tad a a a aaa eaaeo 2 15 2 16 Multi Function Timer Pulse Unit Driver cece ceccecccceeeeeeeeceeceeeeeeeeeceecaeceeeeeeeseceaeseeeeseesecsacaeeeeees 2 16 2 17 Port Output Enable Driver cccccceccececeeeeeeeeneeeeeeeeeseceaaaeaeeeeeeesecaaaeaeeeeesesesceeaeeeeeeeeesensiceeeeees 2 17 218 BD Timer DIVER ci A A ah r dea stan A eget aed cee 2 18 2 19 Compare Match Timer Driver ccccccccceeeeeeeeeec cece ee eeeececaaeaeeeseeesecaaaaeaeeeeeeesececaaeceeeeeeesecsuceeeeees 2 19 2 20 Real time Clock Driver cisco sede te eect ba ds cea heat deed steadiness teal aed ee 2 20 2 21 Watchdog Timer Driver c cccceeecececeeneeceeeeneececeaneesee
338. e after using option PDL_CGC_RTC_TO_BE_USED b Call R_CGC_Set once to set sub clock frequency before call R_CGC_Control with option PDL_CGC_RTC_TO_BE_USE c Make sure PCLKB clock frequency 2 RTC count source clock frequency R_IO_PORT_Compare Revise program example R_MCU_Control Remove On chip RAM control R_LVD_Create Revise program example R_DTC_GetStatus Revise program example R_RTC_Create Revise remarks gt Revise remarks This function is called to use RTC after setting option PDL_CGC_RTC_TO_BE_USED in R_CGC_Control at cold start R_RTC_Control Add description of the Clock output control RTC counting will be stopped temporarily during the writing of RTCOE bit R_RTC_Control Revise remarks gt Delete remark IfR_RTC_Create has been used and then a warm reset is performed it is not necessary to call R_RTC_Create again before using this function However it is necessary to call R_CGC_Control or R_CGC_Set to enable the sub clock even if it is already enabled before calling this function gt Add remarks This function is called after R_RTC_Create or R_RTC_CreateWarm R_RTC_CreateWarm Remove in Prototype of data1 data2 R_SCI_IIC_Write Revise program example R_SCI_IIC_Read Revise program example R_SCI_IIC_ReadLastByte Revise program example R_IIC_MasterSend Revise program example R_IIC_MasterReceiveLast Revise program example R_IIC_SlaveSend Revise program example R_TPU_Create R
339. e bus until an address match occurs and store any data received Register the storage area and transfer method for data received on the selected I C channel data1 Select channel IICn where n 0 data2 Select the operation options The default setting is shown in bold Specify PDL_NO_DATA to use the default DMAC DTC trigger control PDL_IIC_RX_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_IIC_RX_DMAC_TRIGGER_ENABLE or DMAC or DTC when a byte is PDL_IIC_RX_DTC_TRIGGER_ENABLE received PDL_IIC_TX_DMAC_DTC_TRIGGER_DISABLE or PDL_IIC_TX_DMAC_TRIGGER_ENABLE or PDL_IIC_TX_DTC_TRIGGER_ENABLE Disable or enable activation of the DMAC or DTC for data transmission data3 The start address of the storage area for any received data If the DMAC or DTC shall be used to handle the received data specify PDL_NO_PTR data4 The number of bytes in the storage area If the DMAC or DTC shall be used to handle the received data specify PDL_NO_DATA func Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Return value Category Reference Transfer method Parameter Pollin PDL_NO_FUNC This function will continue until a Stop condition is 9 detected or the master tries to read data from this slave The function to be called when a Stop condition is detected or the master Interrupts tries t
340. e data to the selected DAC channel s data1 Select the DAC channel output to be modified PDL_DAC_10_CHANNEL_0 Select channel 0 PDL_DAC_10 CHANNEL_1 Select channel 1 data2 The value to be written to the channel O output register Ignored if the channel is not selected data3 The value to be written to the channel 1 output register Ignored if the channel is not selected True if all parameters are valid otherwise false DAC R_DAC_10_Create e Refer to the data alignment that was selected when R_DAC_10_Create was called RPDL definitions include r pdl dac 10 h RPDL device specific definitions include r_pdl definitions h void func void Write new data to DAC channel 0 R_DAC_10 Write PDL DAC 10 CHANNEL 0 100 0 R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 284 RENESAS RX210 Group 4 Library Reference 4 2 27 Temperature Sensor 1 R_TS_Create Synopsis Prototype Description Return value Category References Remarks Configure the Temperature Sensor bool R_TS_Create uint8_t data II Configuration Set the operating condition and enable the Temperature Sensor data Operating condition e PGA gain PDL_TS_PGA_GAIN_0 or Set PGA gain according to 1 8V lt AVCCO lt 2 7V PDL_TS_PGA_GAIN_1 or or 2 7V lt AVCCO lt 3 6V PDL_TS_PGA_GAIN_2 or or
341. e filter as PCLKB 1 8 32 or the count source TCNT_TCNTU_value For n 0 to 4 The timer counter TCNT value For n 5 The timer counter TCNTU value TGRA_TCNTV_value For n 0 to 4 The register TGRA value For n 5 The timer counter TCNTV value TGRB_TCNTW_value For n 0 to 4 The register TGRB value For n 5 The timer counter TCNTW value TGRC_TGRU_value For n 0 3 or 4 The register TGRC value For n 5 The register TGRU value Ignored for n 1 or 2 TGRD_TGRV_value For n 0 3 or 4 The register TGRD value For n 5 The register TGRV value Ignored for n 1 or 2 TGRE_TGRW_value For n 0 The register TGRE value For n 5 The register TGRW value Ignored forn 1 2 3 or 4 TGRF_TADCORA_value For n 0 The register TGRF value For n 4 The register TADCORA value Ignored forn 1 2 3 or 5 TADCORB_value The register TADCORB value ignored for n 4 TADCOBRA_value The register TADCOBRA value ignored for n 4 TADCOBRB_value The register TADCOBRB value ignored for n 4 RENESAS Page 4 132 RX210 Group Description 9 9 Return value Category Reference 4 Library Reference func1 For n 0 to 4 The function to be called when a TGRA event occurs For n 5 The function to be called when a TGRU event occurs Specify PDL_NO_FUNC if not required func2 For n 0 to 4 The function to be ca
342. e specific definitions tinclude r pdl definitions h void func void uinti t data 10 1 2 3 4 5 6 7 8 9 10 Write 10 numbers to the DOC R DOC Write data 10 y R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 302 RENESAS RX210 Group 4 2 31 1 R_TPU_Set Synopsis Prototype Description 1 2 R20UT0708EE0211 Rev 2 11 Aug 01 2014 Configure the Timer Pulse Unit pins 16 bit Timer Pulse Unit bool R_TPU_Set uint8_t data1 uint32_t data2 Select the TPU pins data1 The channel number n where n 0 to 5 data2 Configure the TPU input and output pins for the channel Use to separate each selection Valid when n 0 4 Library Reference Channel selection Pin configuration PDL_TPU_PIN_AO_P86 or PDL_TPU_PIN AO PAO Select the P86 or PAO pin for TIOCAO PDL_TPU_PIN_BO P17 or PDL_TPU_PIN BO PA Select the P17 or PA1 pin for TIOCBO PDL_TPU_PIN_CO P32 Select the P32 pin for TIOCCO PDL_TPU_PIN_DO P33 or PDL_TPU_PIN_DO PA3 Select the P33 or PA3 pin for TIOCDO Valid when n 1 PDL_TPU_PIN_A1_P56 or PDL_TPU_PIN_A1_PA4 Select the P56 or PA4 pin for TIOCA1 PDL_TPU_PIN_B1_P16 or PDL_TPU PIN B1 PA5 Select the P16 or PAS pin for TIOCB1 Valid when n 2 PDL_TPU_PIN_A2 P87 or PDL_TPU_PIN_A2 PAG Select the P87 or PAG pin for TIOCA2
343. e transition is in progress this function will return false if this is detected After a power on reset the MCU selects the LOCO as the clock source This function must be called before configuring clock dependent modules This function will enable the selected clock but will not select it as the current clock source After the required settling time use R_CGC_Control to select the desired clock source If the sub clock oscillator is not fitted use R_CGC_Control to disable the oscillation circuit The registers MOSCWTCR main clock SOSCWTCR sub clock PLLWTCR PLL and HOCOWTCR2 HOCO provide stabilisation delays for the respective oscillator and must be written to while that clock is stopped If any of these registers needs to be modified stop the clock using R_CGC_Control and call R_LPC_Create to set the new value If the PLL will be used first use this function to configure the main clock oscillator settings If the PLL will be used the frequencies of the internal clocks ICLK PCLKD PCLKB FCLK and BCLK must be no more than the PLL output clock frequency 2 If the PLL output frequency is to be changed while the PLL is enabled before calling this function use R_CGC_Control to select another clock source and stop the PLL If the IWDTLOCO is selected specify PDL_NO_DATA for parameters data2 and data4 to data8 The BCLK pin is available only on packaes with at least 100 pins The output will not be active until the external bus is
344. eceived PDL_INTC_VECTOR_TXI4 4 Start of next data transfer PDL_INTC_VECTOR_TEI4 End of data transfer PDL_INTC_VECTOR_ERI5 Error in data received PDL_INTC_VECTOR_RXI5 SCI channel Data received PDL_INTC_VECTOR_TXI5 5 Start of next data transfer PDL_INTC_VECTOR_TEI5 End of data transfer PDL_INTC_VECTOR_ERI6 Error in data received PDL_INTC_VECTOR_RXI6 SCI channel Data received PDL_INTC_VECTOR_TXI6 6 Start of next data transfer PDL_INTC_VECTOR_TEI6 End of data transfer PDL_INTC_VECTOR_ERI7 Error in data received PDL_INTC_VECTOR_RXI7 SCI channel Data received PDL_INTC_VECTOR_TXI7 7 Start of next data transfer PDL_INTC_VECTOR_TEI7 End of data transfer PDL_INTC_VECTOR_ERI8 Error in data received PDL_INTC_ VECTOR _RXI8 SCI channel Data received PDL_INTC_VECTOR_TXI8 8 Start of next data transfer PDL_INTC_VECTOR_TEI8 End of data transfer PDL_INTC_VECTOR_ERI9 Error in data received PDL_INTC_VECTOR_RXI9 SCI channel Data received PDL_INTC_VECTOR_TXI9 9 Start of next data transfer PDL_INTC_VECTOR_TEI9 End of data transfer PDL_INTC_VECTOR_ERI10 Error in data received PDL_INTC_VECTOR_RXI10 SCI channel Data received PDL_INTC_VECTOR_TXI10 10 Start of next data transfer PDL_INTC_VECTOR_TEI10 End of data transfer PDL_INTC_VECTOR_ERI11 Error in data received PDL_INTC_VECTOR_RXI11 SCI channel Data received PDL_INTC_VECTOR_TXI11 11 Start of next data transfer PDL_INTC_VECTOR_TEI11 End of data transfer PDL_INTC_VECTOR_ERI12 Error in data received P
345. ect the auto start settings to be stored in registers OFSO and OFS1 data1 Select the post reset IWDT configuration settings If multiple selections are required use to separate each selection Auto start control PDL_MCU_OFS_IWDT_HALTED or PDL_MCU_OFS_IWDT AUTOSTART Disable or enable the IWDT auto start mode If auto start mode is enabled select one setting from each of the following Timeout period PDL_MCU_OFS PDL_MCU_OFS PDL_MCU_OFS PDL_MCU_OFS IWDT IWDT IWDT IWDT TIMEOUT_1024 or TIMEOUT_4096 or TIMEOUT_8192 or TIMEOUT_16384 Timeout period specified in cycles of the divided clock as specified in the Clock division selection below Clock division PDL_MCU_OFS_IWDT_CLOCK_LOCO_1 or PDL_MCU_OFS IWDT CLOCK_LOCO_16 or PDL_MCU_OFS IWDT CLOCK_LOCO_32 or PDL_MCU_OFS IWDT CLOCK_LOCO_64 or PDL_MCU_OFS IWDT CLOCK_LOCO_128 or PDL_MCU_OFS IWDT_CLOCK_LOCO_ 256 The selected clock The LOCO 1 16 32 64 128 or 256 Window end position PDL_MCU_OFS_IWDT_WIN_END_75 or T PDL_MCU_OFS_IWDT_WIN_END_50 or he window end position specified as a PDL_MCU_OFS_IWDT_WIN_END_25 or PDL_MCU_OFS_IWDT_WIN_END_0 percentage of the down counter 0 is when the down counter would underflow Selecting 0 is equivalent to no window end position Window start
346. ect the low speed on chip oscillator LOCO PDL_CGC_CLK_HOCO or high speed on chip oscillator HOCO PDL_CGC_CLK_MAIN or main clock oscillator PDL_CGC_CLK SUB _CLOCK or sub clock oscillator PDL_CGC_CLK_PLL or Phase locked loop PLL circuit or IWDT dedicated PDL_CGC_CLK_IWDTLOCO low speed clock on chip oscillator IWDTLOCO data2 Configuration settings If multiple selections are required use to separate each selection BCLK pin output control ignored if the device package does not support the external bus PDL_CGC_BCLK_DIV_1 or Output the external bus clock BCLK PDL_CGC_BCLK_DIV_2 or BCLK 2 or PDL_CGC_BCLK_DISABLE disable the BCLK signal Options which are applicable only when the HOCO is selected in parameter data1 e High speed on chip oscillator frequency selection PDL_CGC_HOCO_32000 or PDL_CGC_HOCO_ 36864 or Select the HOCO frequency 32 0 36 864 PDL_CGC_HOCO_40000 or 40 0 or 50 0 MHz PDL_CGC_HOCO_50000 Options which are applicable only when the Main clock oscillator is selected in parameter data1 e Main clock oscillator type PDL_CGC_MAIN_RESONATOR or PDL_CGC_MAIN_EXTERNAL Select the oscillator type e Main clock oscillator drive type PDL_CGC_MAIN_CERAMIC_LEAD_16_20 Adjust the drive level when a 16 to 20 MHz lead type ceramic resonator is used e Sub clock oscillator drive ability select only once when power on
347. ection These driver functions are used for controlling and checking the register write protection 10 Bus Controller These driver functions are used for configuring the external address bus data bus and chip select pins and handling any bus errors 11 DMA Controller These driver functions are used for configuring and controlling the transfer of data within the address space 12 Data Transfer Controller These driver functions are used for configuring and controlling the transfer of data triggered by peripheral interrupts 13 Event Link Controller These driver functions are used for configuring and controlling the event links 14 Multi Function Timer Pulse Unit These driver functions are used for configuring and controlling the multi function timers 15 Port Output Enable These driver functions are used for additional configuring and controlling of the timer outputs 16 8 bit Timer These driver functions are used for configuring and controlling the timers 17 Compare Match Timer These driver functions are used for configuring and controlling the timers R20UT0708EE0211 Rev 2 11 Page 2 1 Aug 01 2014 ztENESAS RX210 Group 2 Driver 18 Real time Clock These driver functions are used for configuring and controlling the real time clock timer 19 Watchdog Timer These driver functions are used for configuring and controlling the timer 20 Independent Watchdog Timer These driver functions are used for
348. ection flag data2 Monitor 2 control All selections are optional If multiple selections are required use to separate each selection If no selections are required specify PDL_NO_DATA e Monitor control PDL_LVD_DISABLE Disable monitor 2 operation e Flag control PDL_LVD_CLEAR_DETECTION Clear the monitor 2 change detection flag True Voltage detection circuit R_LVD_Create Other operation changes require the shutdown of both voltage monitors If such changes are required call R_LVD_Create with the new settings RPDL definitions tinclude r pdl lvd h RPDL device specific definitions tinclude r pdl definitions h void func void Disable monitor 1 clear the monitor 2 flag R_LVD_ Control PDL LVD DISABLE PDL LVD CLEAR DETECTION y RENESAS Page 4 59 RX210 Group 4 Library Reference 3 R_LVD_GetStatus Synopsis Prototype Description Check the status of the voltage detection module bool R_LVD_GetStatus uint8_t data Status flags pointer Return the status flags Program example data The Monitor 1 and Monitor 2 status flag shall be stored in the following format b7 b6 b5 b4 b3 b2 b1 bO Monitor 2 Monitor 1 Status Change Status Change 0 i 0 0 VCC lt Vdet1 eee
349. ed see R_LPC_Create disable the HOCO Do not change the HOCO power state if in high speed operating mode middle speed operating mode 2A middle speed operating mode 2B or low speed operating mode 1 or 2 e If this function is used to enable a clock oscillator wait for the required settling time before selecting the clock source Do not enable the PLL if in low speed operating mode 1 or 2 e If using MCU version B the PLL power will also be controlled when the PLL is enabled disabled Note This may automatically perform a temporary change to Middle Speed Operating Mode 1A while this is performed Hence if not using the PLL then use PDL_CGC_PLL_DISABLE to reduce power consumption e This function can not be used if ROM Flash Program Erase mode is set or if a operating power mode transition is in progress This function will return false if this is detected Calling R_RTC_Create after using option PDL_CGC_RTC_TO_BE_USED e Call R_CGC_Set once to set sub clock frequency before call R_CGC_Control with option PDL_CGC_RTC_TO_BE_USE Make sure PCLKB clock frequency gt RTC count source clock frequency Sub clock oscillator is not available for 48 pin package R20UT0708EE0211 Rev 2 11 Page 4 10 Aug 01 2014 RENESAS RX210 Group 4 Library Reference Program example RPDL definitions include r pdl_cgc h RPDL device specific definitions include r pdl definitions h vo
350. ed until the callback function has completed If reception is enabled and receive errors occur transmission will be blocked until the errors are cleared In Multi processor mode R_SCI_Send is to be called in pair the first one is to send ID ID cycle the second one is to send data Data cycle For ID transmission it will be sent by internal polling operation For Data transmission it will be the same as normal Asynchronous mode For a usage example of Multi processor mode please refer to section 5 17 7 For ID cycle the DMAC DTC trigger control and the callback function will be ignored Do not use this function in SPI mode use R_SCI_SPI_Transfer Do not use this function in IIC mode use R_SCI_IIC_Write When using interrupts to manage the transfer if the channel is operating in synchronous mode transmit only and with an external clock the TXD pin may need to be held active for longer up to half a bit period to avoid violating the data hold time for the receiving device If a delay is required the user should refer to the comments in the Transmit End interrupt processing routines in the file Interrupt_SCl c in the i_src folder and implement the delay in a way that is suitable for their application If using the DMAC or DTC this module does not know when the transmission has ended Therefore when it has completed the user must call the R_SCI_Control function with option PDL_SCI_STOP_TX to manually disable the transmission If a callback
351. eeeceseeaenneseeaeeeseeaaneeedecueceseedunneceeeenseeedteneees 2 21 2 22 Independent Watchdog Timer Diver oooonnccccnnnncccononoccccnnnoncccnonon cnn non c cnn arrancar 2 22 2 23 Serial Communication Interface Driver ccccccccceceeeeeeeeeeeceeeeeeesececaeeeeeeeeesececaaeeeeeereeseesicaeeeeees 2 23 2 24 PC Bus Interface Driver ccccccceeeeecccececeeeeeeeeeaeee a a a aa Ea aa a aa aee aa aae A RE 2 24 2 25 Serial Peripheral Interface Driver ccccccccceeeecceceeeeeeeeeeeeeeeeeeeeseceaaeceeeeeseseceeaeeeeeeeeesensisaneeeees 2 25 2 203 ERC Calculator Driver eairt atlas sii lali data to lia 2 26 2 27 12 bit Analog to Digital Converter Driver ooooocononococccnnncccoconononccnnnnnnnnnnonnnncnnnnnnnnnnn nn nn cnnnnnnnnnnn rra 2 27 2 28 10 bit Digital to Analog Converter Driver oooooonnncccnnnnccccnnnonccnnnnoncccnn noc cnn nn cn anna 2 28 2 29 Temperature Sensor Driver ceccccccccceceeeeeeeee aces ce eeeecegeaeaeaeeeeeeeseceaaaeceeeeeeesesnaeceeeeeeeseeeinaeeeees 2 29 2 30 Comparator A Dive hice ia ico 2 30 2 31 Comparator B DriVeR noviciado eo aed ee de ene ed eet 2 31 2 32 Data Operation Circuit Driver sissien aaa i aada aiaa aeaaaee iaaiiai 2 32 2 33 Timer Pulse Unit Driver e a a a a ae a a A a r Aaaa rE a Eaa a TEE 2 33 Types and COPIMMIONS cenieni ea EE EA E E AE 3 1 3 1 Datta TYPOS E E ci 3 1 3 2 CASERA 3 1 3 2 1 PDEGNOMEUNG a aaa 3 1 3 2 2 PDE NOP TR oa aero laa rro nro aora 3 1
352. el the retention of I O port pin states Return value True if all parameters are valid and exclusive otherwise false Category LPC References R_LPC_Create R20UT0708EE0211 Rev 2 11 Page 4 74 Aug 01 2014 RENESAS RX210 Group Remarks Program example R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference Sleep mode is utilised by some peripheral drivers to turn off the CPU when required When entering software standby or deep software standby mode the oscillation stop detection function is disabled The detection is re enabled if software standby mode is interrupted On exit from deep software standby mode the MCU is reset If Sleep mode return clock source switching has been enabled the only possible clock sources are the LOCO or sub clock oscillator When PDL_LPC_SLEEP_RETURN_SWITCH_HOCO is selected the frequencies of the internal clocks ICLK PCLKD PCLKB FCLK and BCLK must be no more than the selected clock source frequency 2 before a transition is made to sleep mode The sleep mode return clock source switching function and clock source switching function by the ELC cannot be used at the same time Do not set up the DMAC and DTC to rewrite any registers related to WDT while the chip is in sleep mode If IWDT is stopped do not set up the DMAC and DTC to rewrite any registers related to IWDT while the chip is in sleep mode If a
353. elIRO4 i void IRQlHandler void Process the IRQl event here the flag is cleared automatically switch _swl pressed true void IRQ4Handler void Disable the level triggered interrupt R_INTC_ControlExtInterrupt PDL_INTC_IRQ4 PDL_INTC_DISABLE irg4 low true static void ReEnableIRQ4 void Re enable the interrupt and try to clear it R_INTC_ControlExtInterrupt PDL_INTC_IRQ4 PDL _ INTC ENABLE PDL INTC CLEAR IR FLAG Figure 5 2 Example of External Interrupt R20UT0708EE0211 Rev 2 11 Page 5 5 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 3 I O Port Figure 5 3 shows examples of I O port configuration reading and writing Peripheral driver function prototypes include r pdl_io port h RPDL device specific definitions include r padl definitions h void main void uint8 t result uintl6 t direction Set all reserved I O port pins to the recommended state R_IO_ PORT NotAvailable Configure port 4 as an input R_IO PORT Set PDL IO PORT 4 PDL IO PORT INPUT 7 Configure port pin P21 as an open drain output R_IO PORT Set PDL IO PORT 2 1 PDL IO PORT OUTPUT PDL IO PORT TYPE NMOS 7 Read the value of all the pins on port 4 R_IO_PORT Read PDL IO PORT 4 amp result i Set pin P21 to output high R_IO PORT Write PDL IO PORT
354. election uint8_t data2 Buffer to receive byte If R_SCI_IIC_Read has been used to start an IIC read where the DMAC or DTC will read all the data except for the last byte this function can be used to read the last byte ANACK will then be generated followed by a stop condition unless the original transfer request asked for the stop condition to be omitted Program example R20UT0708EE0211 Rev 2 11 Aug 01 2014 data1 Select channel SCIn where n 0 to 12 data2 The address of the buffer that will receive the byte Return value True Category SCl Reference R_SCI_IIC_Read Remarks PDL functions include r pdl_sci h RPDL device specific definitions tinclude r pdl_definitions h define CHANNEL SCI IIC 9 Buffer for IIC data uint8 t IIC Buffer 10 void func void Read the last byte of the IIC read operation R_SCI_TIC_ReadLastByte CHANNEL SCI_IIC amp IIC_ Buffer 9 Page 4 232 2tENESAS RX210 Group 10 R_SCI_Control Synopsis Prototype Description Return value Category Reference Remarks R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference Control the SCI channel bool R_SCI_Control uint8_t data1 Channel selection uint16_t data2 Channel control Control the SCI channel data1 Select channel
355. emark that PCLKB gt sub clock R_RTC_Read added remark that day of week is not captured R_RTC_Control add PDL_RTC_PERIODIC_8_HZ R_WDT_Control Update comment for data R_IWDT_Set Added remark about IWDT clock in relation to PCLKB R_SCI_Set Changed to have a channel parameter Must be called for all pins required R_SCI_Create Changed description of PDL_SCI_SPI_SS_DISABLE R_SCI_Create Added comment about format of baud rate to be used depending if using an external or internal clock R_SCI_Receive Added PDL_SCI_RX_CONTINUOUS_ENABLE R_SPI_Create Add comment for SSLx pin control R_SPI_Create Correct reference for SPI Frame configuration selection R_SPI_Command Changed remark about using PDL_SPI_DIV_1 R_SPI_Transfer update description for data5 R_ADC_12_CreateUnit Updated description for data3 data4 R_ADC_12_CreateUnit Added remarks about restrictions R_ADC_12 CreateUnit Added TPU triggers R_ADC_12 CreateChannel Added remark about diagnostic mode R_ADC_12_CreateUnit Added remark regarding sampling time R_ADC_12_CreateChannel Added remark regarding sampling time R_ADC_12_Read Add remark for Self diagnostic format R_TS_Create Add a remark R_CPA_GetStatus add remark R_DOC_Control Made it clear that a mode need only be specified if changing mode R_DOC_Read Allowed PDL_NO_PTR to be used in parameters R_DOC_Read and R_DOC_Write Return value is always true Added TPU module for devices with gt 144
356. enable the Voltage monitor 0 auto start PDL_MCU_OFS LVD O ENABLE mode If auto start mode is enabled select one setting from the following e Voltage threshold selection PDL_MCU_OFS LVD 0 380 or PDL_MCU_OFS LVD 0 280 or Select 3 80V 2 80V 1 90V or 1 72V as the voltage PDL_MCU_OFS LVD 0 190 or monitor O detection level PDL_MCU_OFS LVD_ 0 172 data4 Select the post reset CGC configuration settings Auto start control PDL_MCU_OFS_CGC_HOCO DISABLE or PDL_MCU_OFS_CGC_HOCO_ENABLE Disable or enable the HOCO after a reset MCU registers RENESAS Pen RX210 Group References Remarks Program example R_IWDT_Set R_WDT_Set R_CGC_Set 4 Library Reference e This is a macro not a function call There is no error checking or return value RPDL definitions include r pdl mcu ofs h Enable the IWDT auto start mode Leave the WDT disabled Enable reset at 2 80V Leave the HOCO disabled R_MCU_OFS p tw Wy ig hwy y No Li MCU_OFS IWDT AUTOSTART Li MCU_OFS IWDT CLOCK av aA P PDL MCU_OFS IWDT TIMEOUT 4096 MCU_OFS IWDT WIN STAR LOCO 16 PDL MCU OFS IWDT WIN END 50 PA l 75 PDL MCU OFS IWDT NMI MCU_OFS IWDT STOP DISABLE Li MCU OFS L MCU OFS LVD 0 ENAB WDT_HALTED E PDL MCU_
357. ency measurement use R20UT0708EE0211 Rev 2 11 Page 5 11 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 6 Low Power Consumption 5 6 1 Software Standby Mode Figure 5 7 shows an example of entering Software Standby mode through Low Power Consumption control Peripheral driver function prototypes include r pdl lpc h tinclude r pdl_intc h RPDL device specific definitions tinclude r pdl definitions h void SW2_handler void void main void Enable the switch SW2 interrupt R_INTC_CreateExtInterrupt PDL_INTC_IRQ3 PDL INTC FALLING SW2_handler gt Set Switch SW2 interrupt R_INTC_SetExtInterrupt PDL INTC IRQ3 PORT 3 3 Select the default options R_LPC Create PDL NO_ DATA PDL NO DATA PDL NO DATA PDL NO DATA PDL NO DATA PDL NO_ DATA PDL NO DATA y Enter software standby mode R_LPC Control PDL_LPC_MODE SOFTWARE STANDBY i Normal execution will resume after switch SW2 is pressed void SW2 handler void nop Figure 5 7 Example of Software Standby Mode R20UT0708EE0211 Rev 2 11 Page 5 12 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 6 2 Deep Software Standby Mode Figure 5 8 shows an example of entering Deep Software Standby mode through Low Power Consumption control PDL functions include r pdl lpc h include r pdi intc h PDL
358. endent Watchdog Timer use R20UT0708EE0211 Rev 2 11 Page 5 52 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 17 Serial Communication Interface 5 17 1 SCI Asynchronous Using Polling This shows the setting of SCI channel 0 and the transmission and reception of data using polling Peripheral driver function prototypes include r pal sci h include r pdl cgc h RPDL device specific definitions include r pal definitions h void main void volatile uint8 t rx buffer 5 1 Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Set pin options R_SCI Set 0 PDL SCI PIN SCIO RXDO P21 PDL SCI PIN SCIO TXDO P20 i Set up SCI channel 0 Async 8N1 38400 baud R_SCI_Create 0 PDL SCI _ASYNC PDL_SCI_8N1 38400 L de Wait while send message R_SCI_Send 0 PDL NO DATA r nHello Type 5 characters and I will echo them back r n 0 PDL_NO_FUNC de Wait for 5 characters to be read R_SCI_Receive 0 PDL NO DATA rx_buffer 5 PDL NO FUNC PDL_NO_FUNC y Echo the 5 characters back R_SCI Send 0 PDL NO_ DATA rx_buffer L NO FUNC Figure 5 28 Example of SCI asynchronous operation using polling R20UT0708EE0211 Rev 2 11 Page 5 53 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 17 2 SCI Asynchronous Using Interru
359. equired transfer method Transfer method Parameter PDL_NO_FUNC This function will continue until the required number of Polling bytes has been sent Interrupts The function to be called when the last byte has been sent Either the function to be called when each byte is sent or PDL_NO_FUNC DNAG if the callback function specified in R_DMAC_Create will be used DTC The function to be called at the interval specified in R_DTC_ Create data5 The start address of the storage area for the expected data Specify PDL_NO_PTR if not receiving data or if no data shall be processed by this function e g if the DMAC or DTC shall be used to process the received data Page 4 225 RENESAS RX210 Group 4 Library Reference Description 2 2 func2 Receive callback Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Transfer Parameter method Polling PDL_NO_FUNC This function will continue until the required number of bytes has been received The function to be called when the number of received bytes reaches the Return value Category Reference Remarks R20UT0708EE0211 Rev 2 11 Aug 01 2014 sl sh threshold number Either the function to be called when each byte is received or DMAC PDL_NO_FUNC if the callback function specified in RLDMAC_Create will be used D
360. eration bool R_IWDT_Control uint8_t data Control selection Modify the operation of the Independent Watchdog timer data Control the timer e Counter start refresh PDL_IWDT_REFRESH Start or refresh the counter by re loading the timeout value True if the parameter is valid otherwise false Independent Watchdog Timer R_IWDT_Set R_IWDT_Set must be used first to configure the timer unless using Initial Setting Memory Program example using R_MCU_OFS to enable the IWDT from reset RPDL definitions tinclude r pdl iwdt h RPDL device specific definitions tinclude r pdl definitions h void func void Refresh the IWDT R_IWDT Control PDL _IWDT REFRESH y R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 205 2tENESAS RX210 Group 4 Library Reference 3 R_IWDT_Read Synopsis Prototype Description Return value Category Reference Remarks Program example Read the watchdog timer status and counter bool R_IWDT_Read uint16_t data A pointer to the data storage location Read and store the status flags and current counter value data The timer status shall be stored in the following format b15 b14 b13 bO Refresh Error Underflow 0 No refresh error 0 No underflow Down Counter Value 1 Refresh error 1 Und
361. eration is executed at the end Therefore both options can be selected together with other changes in one function call If the noise filter is enabled before starting the timer make sure at least 2 cycles of the selected noise filter clock has elapsed after the timer configuration use R_MTU2_Create When generating PWM waveforms in complementary PWM mode 1 to complementary PWM mode 3 set the timer cycle data registers TCDR and timer dead time data registers TDDR to values that satisfy the following condition Timer cycle data register value gt Timer dead time data register value x 2 2 RPDL definitions nclude r pdl mtu2 h RPDL device specific definitions nclude r pdl definitions h id func void Allocate a copy of the structure for the selected channel R_MTU2 ControlUnit_ structure unit0 parameters unit0 parameters simultaneous control PDL MTU2 START CHO L MTU2 START CH 1 unit0 parameters output control L MTU2 OUT P PHASE ALL HIGH LOW unitO parameters general control PDL MTU2 DEAD TIME ENABLE unitO parameters register selection PDL MTU2 REGISTER DEAD TIME L_MTU2_REGISTER_CYCLE_DATA unit0O parameters TDDR value OxFFDD unitO parameters TCDR_ value 0x0100 Modify the operation of unit 0 R_MTU2 ControlUnit 0 amp unitO parameters Page 4 143 RENESAS RX210 Group 4 Library Re
362. erflow True Independent Watchdog Timer None e Ifthe Underflow flag is set to 1 it shall be automatically cleared to O by this function e Ifthe Refresh flag is set to 1 it shall be automatically cleared to O by this function RPDL definitions include r_pdl_iwdt h RPDL device specific definitions include r pdl_definitions h uintl6 t Status void func void Read the timer status R_IWDT_ Read amp Status R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 206 RENESAS RX210 Group 4 2 21 1 R_SCI Set Synopsis Prototype Description 1 6 R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference Serial Communication Interface Configure the SCI pin selection bool R_SCI_Set uint8_t data1 uint16_t data2 Channel selection Pin Configuration Configure I O pins All pins used must be specified there are no defaults data1 The channel number n where n 0 to 12 data Configure the global options Use to separate each selection e Valid when n 0 PDL_SCI_PIN_SCIO_RXDO_P21 or RENESAS PDL_SCI_PIN_SCIO_RXDO_P33 RADO PDL SCI_PIN_SCI0_SMISO0_P21 or PDL_SCI PIN SCIO_SMISOO P33 SMISO0 PDL_SCI_PIN_SCIO_SSCLO_P21 or mE PDL_SCI_PIN_SCI0_SSCL0_P33 PDL_SCI_PIN_SCIO_TX
363. eriod relative to the count source R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS Page 4 187 RX210 Group 4 Library Reference Description 3 4 data7 Configure the Capture 2 RTCIC2 pin options To set multiple options at the same time use to separate each value The default settings are shown in bold e Edge PDL_RTC_CAPTURE_EDGE_NONE or PDL_RTC_CAPTURE_EDGE_RISING or PDL_RTC_CAPTURE_EDGE_FALLING or PDL_RTC_CAPTURE EDGE BOTH Select the edge that will trigger a capture event e Time Capture Noise Filter Control PDL_RTC_CAPTURE_FILTER_OFF or PDL_RTC_CAPTURE FILTER_ON_DIV_1 or PDL_RTC_CAPTURE FILTER_ON DIV_32 Configure the capture noise filter If enabling select the sampling period relative to the count source data8 Configure the clock periodic interrupt The default setting is shown in bold e Periodic interrupt selection PDL_RTC_PERIODIC_DISABLE or PDL_RTC_PERIODIC_256_HZ or PDL_RTC_PERIODIC_128_HZ or PDL_RTC_PERIODIC_64_HZ or PDL_RTC_PERIODIC_32_HZ or PDL_RTC_PERIODIC_16_HZ or PDL_RTC_PERIODIC_8 HZ or PDL_RTC_PERIODIC_4_HZor PDL_RTC_PERIODIC_2 HZ or PDL_RTC_PERIODIC_1_HZ or PDL_RTC PERIODIC 2S requests The frequency or interval for periodic interrupt data9 The alarm day of the week and time in hours minutes and seconds BCD format is used If not required specify PDL_NO_DATA The fo
364. errupt data1 Choose the interrupt to be checked PDL_INTC_IRQn n 0 to 7 or IRQn n 0 to 7 interrupt pin or PDL_INTC_NMI NMI interrupt data2 The status flags shall be stored in the following format For an IRQ pin b7 b4 b3 b2 b1 bO Detection condition Current level Request status 00 Low level 0 01 Falling edge 0 Low 0 Not detected 10 Rising edge 1 High 1 Detected 11 Both edges For the NMI interrupt b7 b6 b5 b4 b3 b2 b1 bO Other interrupt request NMI pin Underflow Oscillation Current Detection LVD2 LVD1 WDT WDT stop level condition Request status 0 Not detected 0 Low 0 Falling 0 Not detected 1 Detected 1 High 1 Rising 1 Detected True if all parameters are valid and exclusive otherwise false Interrupt control R_INTC_ControlExtInterrupt e The MPC registers are used to determine which pin is used for IRQn e If this function is called from within a callback function the IRQn request status flag will be 0 e If any NMI interrupt detection flags have been set to 1 use R_INTC_ControlExtInterrupt to clear them to 0 RPDL definitions include r pdl_intc h RPDL device specific definitions include r pdl definitions h void func void uint8 t irq status Read the IR flag and pin state for IRO5 R_INTC_GetExtInterruptStatus PDL_INTC_IRO5 amp irq stat
365. ess to reserved addresses is prohibited The reserved addresses are provided for the possible future expansion of functions Do not access these addresses the correct operation of LSI is not guaranteed if they are accessed 4 Clock Signals After applying a reset only release the reset line after the operating clock signal has become stable When switching the clock signal during program execution wait until the target clock signal has stabilized When the clock signal is generated with an external resonator or from an external oscillator during a reset ensure that the reset line is only released after full stabilization of the clock signal Moreover when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress wait until the target clock signal is stable 5 Differences between Products Before changing from one product to another i e to a product with a different part number confirm that the change will not lead to problems The characteristics of an MPU or MCU in the same group but having a different part number may differ in terms of the internal memory capacity layout pattern and other factors which can affect the ranges of electrical characteristics such as characteristic values operating margins immunity to noise and amount of radiated noise When changing to a product with a different part number implement a system evaluation test for
366. est flag is set to 1 the flag will be cleared to O by this function RENESAS dei RX210 Group 4 Library Reference Program example RPDL definitions include r pdl dmac h RPDL device specific definitions include r pdl definitions h void func void uint8 t StatusValue uint32 t SourceAddr Read the status and current source address for channel 2 R_DMAC GetStatus 2 amp StatusValue amp SourceAddr PDL _NO PTR PDL _NO PTR PDL_NO PTR R20UT0708EE0211 Rev 2 11 Page 4 100 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 4 2 12 Data Transfer Controller 1 R_DTC Set Synopsis Prototype Description Return value Category Reference Set the Data Transfer Controller options bool R_DTC_Set uint8_t data1 Configuration options uint32_t data2 Vector table base address Set the global options for the Data Transfer Controller data1 Configuration selections If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Read skip control PDL_DTC_READ_SKIP_DISABLE or Disable or enable skipping of transfer data read PDL_DTC_READ_SKIP_ENABLE when the vector numbers match Address size control PDL_DTC_ADDRESS_ FULL or PDL_DTC_ADDRESS_SHORT Select 32 bit
367. estination start address The valid range depends on the address mode short or full Specify PDL_NO_PTR if not required data5 The new number of transfers to take place For normal or block mode valid between 0 and 65535 0 65536 transfers For repeat mode valid between 0 and 255 0 256 transfers Specify PDL_NO_DATA if not required data6 The new size of each block transfer Valid between 0 and 255 0 256 units Ignored in normal or repeat mode Specify PDL_NO_DATA if not required True if all parameters are valid and exclusive otherwise false Data Transfer Controller R_DTC_Create Page 4 107 2tENESAS RX210 Group Remarks Program example R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference This function must be called in order to start the DTC R_DTC_Create must be called at least once before starting the DTC Start the DTC before generating a transfer trigger RPDL definitions include r pdl dtc h RPDL device specific definitions include r pdl definitions h Reserve 16 bytes full address mode for the CMT0O triggered transfer data area Use a 32 bit type to make the address a multiple of 4 uint32 t dtc_cmt0O transfer data 4 void func void Start the controller R DTO Control PDL_DTC_START PDL_NO_PTR PDL_NO_PTR PDL NO PTR PDL NO_ DATA PDL NO DATA i Update the p
368. eter was out of range or the RX pin has not been selected by using the R_SCI_Set and or R_SCI_Create functions SCI R_SCI_Receive R_SCI_Set R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 235 2tENESAS RX210 Group Remarks Program example R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference The error flags are not modified by this function They are cleared when a new reception process is started For channels SCI1 SCI5 and SCI6 if the RxD pin to be used has not been specified using R_SCI_Set before calling this then the RxD pin level will always be read as low RPDL definitions include r pdl _sci h RPDL device specific definitions include r pdl definitions h uint8 t StatusValue uintl t TxChars uint t RxChars L6 void func void Read the status of SCI channel 0 R_SCI_GetStatus 0 amp StatusValue PDL_NO_PTR TxChars RxChars Page 4 236 RENESAS RX210 Group 4 Library Reference 4 2 22 IC Bus Interface 1 R_IIC_Set Synopsis Configure the I C pin selection Prototype bool R_IIC_Set uint8_t data Pin selection Description Set up the selected C channel Return value data Configure the 1 C pins Use to separate each selection SDA pin selection PDL_IIC_PIN_SDA or PDL_IIC_PIN_SDA DS Select the normal or DS pin for
369. eturn value data6 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid exclusive and achievable and a normal transfer completed otherwise false Category C Reference R_IIC_Create R_IIC_GetStatus Remarks e Ifa callback function is specified transmission interrupts are used Program example i i ui VO Please see the notes on callback function usage in 6 If the Start condition is enabled and the previous transfer did not issue a Stop condition a Repeated Start condition shall be generated If the Start condition is disabled the slave address will not be transmitted If no callback function is specified for transmission completion this function will monitor the status flags to manage the data transmission If the I C channel s registers are modified directly by the user this function may lock up If false is returned use R_IIC_GetStatus to check if an unexpected event on 1 C bus was the cause of the failure If the transfer has ended prematurely use R_IIC_Control to issue a Stop condition False will be returned if the DMAC channel has not been allocated using R_DMAC_ Create RPDL definitions nclude r pal iic h RPDL device specific definitions nclude r pdl definitions h nt8 t data_arr
370. ev 2 11 Aug 01 2014 2tENESAS Page 4 2 RX210 Group 4 Library Reference Serial Peripheral Interface 1 R_IIC_Set Configure the 1 C pin selection 2 R_IIC_Create 12C channel setup 3 R_IIC_Destroy Disable an C channel 4 R_IIC_MasterSend Write data to a slave device I2C bus interface 5 R_IIC_MasterReceive Read data from a slave device 6 R_IIC_MasterReceiveLast Complete a DMAC or DTC based read process 7 R_IIC_SlaveMonitor Monitor the bus and receive data from a master 8 R_IIC_SlaveSend Write data to a master device 9 R_IIC_Control 12C channel control 10 R_IIC_GetStatus Read the status for an C channel R_SPI_Set Configure the SPI pin selection R_SPI_Create Configure an SPI channel R_SPI_Destroy Shutdown an SPI channel R_SPI_Command Configure an SPI command R_SPI_Transfer Transfer data over an SPI channel R_SPI_Control Control an SPI channel R_SPI_GetStatus Check the status of an SPI channel CRC calculator R_CRC_Create Configure the CRC calculator R_CRC_Destroy Shut down the CRC calculator 12 bit Analog to Digital converter R_CRC_Write Write data into the CRC calculation register R_CRC_Read Read the CRC calculation result R_ADC_12_ Set Select the I O pins for 12 bit ADC R_ADC_12_CreateUnit Configure the 12 bit ADC unit R_ ADC
371. evant interrupt Please see the notes on callback function use in 6 Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed The timing limits depend on the peripheral module clock PCLKB fecike MHz Equation 32 12 5 12 8 8 Tmin 250ns 640ns 666 67ns 1us Frcik 9 Tmax 1 05s 2 68s 2 79s 4 19s Secix If the requested period is not a multiple of the minimum period the actual time period will be more than the requested time period Program example RPDL definitions include r pdl cmt h RPDL device specific definitions include r pdl_ definitions h void func void Use CMT channel 0 for a lms pause R_CMT CreateOneShot f DL NO DATA E 3 DL NO FUNC OovrRwol R20UT0708EE0211 Rev 2 11 Page 4 181 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 3 R_CMT_Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example Disable a CMT unit bool R_CMT_Destroy uint8_t data Unit selection Shut down a CMT unit data The timer unit n where n 0 or 1 Unit O comprises channels CMTO and CMT1 Unit 1 comprises channels CMT2 and CMT3 True if the un
372. evice ODO Figure 5 42 The bus activity showing 4 bytes being transmitted by the EEPROM Read data from the EEPROM using polling if R_IIC MasterReceive 0 PDL NO_ DATA EPROM ADDRESS ata_storage a PDL NO FUNC false Read the channel and transfer status R_TIC GetStatus 0 amp status_flags PDL NO PTR amp RxChars Review the flags and transmit count to decide on the next action Figure 5 43 An example of reading data from the EEPROM R20UT0708EE0211 Rev 2 11 Page 5 77 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 3 Repeated Start C channel 1 will be configured for Master operation The memory address pointer of an EEPROM will be modified and then a Repeat Start condition used to change to read the byte at that memory location in the EEPROM Slave address Memory address Slave address B MIDE Figure 5 44 The bus activity showing the Repeated Start condition when switching to the Read process Send 1 byte to the EEPROM to update the lower address bits and do not stop R_IIC_MasterSend 0 PDL IIC_STOP_DISABLE EPROM ADDRESS eeprom data array 1 1 Pp 0 PDL NO FUNC 7 Read data from the EEPROM A repeated start will occur R_IIC MasterReceive PDL NO DATA EPROM ADDRESS ata_storage PDL NO FUNC Figure 5 45 Set the lower address to 37h and
373. evise program example CGC Revise usage example RTC Revise usage example IIC Revise usage example of Master mode IIC Revise usage example of Slave mode MCU Add usage example R_ELC_Control Revised remark Old Event PDL_ELC_LINK_EVENT_SPI_ERROR cannot be used if multi master configuration SPI operation and master mode are selected for the RSPI This function will return false if this condition is detected New Event PDL_ELC_LINK_EVENT_SPI_ERROR cannot be used if multi master RENES Revision History 5 RX210 Group Revision History Description Page configuration SPI operation and master mode are selected for the RSPI 4 122 123 R_MTU2_Set Add missing pins PDL_MTU2_PIN_3C_P56 PDL_MTU2_PIN_3D_P81 PDL_MTU2_PIN_4A_P82 PDL_MTU2_PIN_4C_P83 R20UT0708EE0211 Rev 2 11 Revision History 6 Aug 01 2014 RENESAS Renesas Peripheral Driver Library User s Manual RX210 Group Publication Date Rev 2 11 Aug 01 2014 Published by Renesas Electronics Corporation ENESAS SALES OFFICES Renesas Electronics Corporation http Awww renesas com Refer to http www renesas com for the latest and detailed information Renesas Electronics America Inc 2801 Scott Boulevard Santa Clara CA 95050 2549 U S A Tel 1 408 588 6000 Fax 1 408 588 6130 Renesas Electronics Canada Limited 1101 Nicholson Road Newmarket Ontario L3Y 9C3 Canada Tel 1 905 898 5441 Fax 1 905 898 3220
374. f Temperature Sensor usage Peripheral driver function prototypes include r pdl adc 12 h include r pdl_cgc h include r pdl_cmt h include r pdl_ts h RPDL device specific definitions include r pdl definitions h void ADC_12 callback void uintl6 t ts result bool ADC_end void main void Configure main clock operation using an external 20 0 MHz clock ICLK 5 MHz PCLKD 5 MHz PCLKB 5 MHz FCLK 5 MHz BCLK not used BCLK pin not used R_CGC_Set PDL CGC CLK MAIN PDL CGC BCLK DISABLE PDL CGC _ MAIN RESONATOR PDL CGC NOT SUB 20E6 20E6 4 20E6 4 20E6 4 20E6 4 PDL_NO DAI PDL _NO DAI y Allow 100us for the main clock to stabilise R_CMT CreateOneShot 0 PDL NO_ DATA 100E 6 PDL_NO_FUNC 0 i Select the PLL as the clock source R_CGC_Control PDL_CGC_CLK_MAIN PDL NO DATA PDL NO DATA Configure ADC for TS R_ADC_12 CreateUnit L ADC_12 INPUT_TS PDL ADC 12 ADSSTR_CALCULATE L ADC 12 SCAN SINGLE L NO DATA L NO DATA E 6 L NO DATA r DC 12 callback r DL_NO_FUNC O mw m Ot e im a R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS Page 5 98 RX210 Group 5 Usage Examples Configure TS R TS Create PDL TS PGA GAIN 2 i ts_result 0 ADC_end false Start TS R_TS Control PDL_TS_PGA_START y
375. ference 6 R_MTU2_ReadChannel Synopsis Prototype Description 1 2 Read from MTU channel registers bool R_MTU2_ReadChannel uint8_tdata1 uint8_t data2 uint16_t data3 uint16_t data4 uint16_t data5 uint16_t data6 uint16_t data7 uint16_t data8 uint16_t data9 Read any of the timer s counter compare or status flag registers data1 1 Channel selection 11 A pointer to the data storage location 11 A pointer to the data storage location 11 A pointer to the data storage location 11 A pointer to the data storage location 11 A pointer to the data storage location 11 A pointer to the data storage location 11 A pointer to the data storage location 11 A pointer to the data storage location The channel number n where n 0 to 5 data2 The status flags shall be stored in the format below The input capture compare match flags will be set to1 if the condition has been detected Specify PDL_NO_PTR if the flags are not to be read Forn 0 b7 b6 b5 b4 b3 b2 b1 bO Detection Count Overflow Input capture compare match direction 0 down V F E D C B A 1 up Forn 1or2 b7 b6 b5 b3 b2 b1 bO Detection Count Underflow Overflow Input capture compare match direction U v 0 B A 9 do
376. fic definitions include r pdl definitions h Callback function prototype void CMTO_handler void void CMT1 handler void void main void 1 uint8 t Flags uint1l6 t Counter Configure main clock operation using an external 20 0 MHz clock ICLK 20 MHz PCLKD 20 MHz PCLKB 20 MHz FCLK 20 MHz BCLK not used BCLK pin not used R_CGC_Set PDL _CGC_CLK MAIN PDL _CGC_BCLK DISABLE PDL CGC MAIN EXTERNAL PDL_CGC_NOT SUB 20E6 20E6 20E6 20E6 20E6 PDL NO DAT PDL NO DAT de Configure PLL operation The PLL will be set to 100 MHz ICLK 50 MHz PCLKD 50 MHz PCLKB 25 MHz FCLK 25 MHz BCLK 25 MHz BCLK pin 12 5 MHz R CGC Set PDL_CGC_CLK PLL PDL CGC BCLK DIV 2 100E6 50E6 50E6 25E6 25E6 25E6 PDL_NO_DATA Allow 100us for the main clock to stabilise R_CMT CreateOneShot 0 PDL_NO DATA 100E 6 PDL NO FUNC 0 Select the PLL as the clock source R_CGC Control PDL CGC CLK PLL PDL NO DATA PDL NO DATA Set the CPU s Interrupt Priority Level to 0 R_INTC Write PDL INTC_REG IPL 0 Configure a port pin for output R_IO PORT Set PDL IO PORT 1 4 PDL IO PORT OUTPUT R_IO PORT Set PDL IO PORT 1 5 PDL IO PORT OUTPU R_IO PORT Write PDL IO PORT 1 4 1 Off LEDO R20UT0708EE0211 Rev 2 11 Page 5 31 Aug 01 2014 ENESAS
377. figuration uint16 tdata2 Data Control the DOC Module data1 Control operation To set multiple options at the same time use to separate each value If no selection is made specify PDL_NO_DATA the control setting will be left unchanged Operation Mode PDL_DOC_COMPARISON_MATCH or PDL_DOC_COMPARISON_MISMATCH or PDL_DOC_MODE_ADD or PDL_DOC_ MODE SUBTRACT If required specify a new mode of operation to change to e DOC Flag PDL_DOC_FLAG_CLEAR Clear the DOC flag If this flag is set when interrupts are enabled an interrupt will be generated Note The DOC flag is automatically cleared when the callback function is called e Interrupt control PDL_DOC_INTERRUPT_ENABLE or PDL_DOC_INTERRUPT_DISABLE Enable or disable the DOC interrupt e Update the DOC data value PDL_DOC_DATA_UPDATE Update the DOC with the value specified in data2 See data2 description for meaning data2 This meaning of this parameter depends upon the Operation Mode Operation Mode Description Comparison The comparison value Addition The initial output value before additions are made Subtraction The initial output value before subtractions are made True if all parameters are valid and exclusive otherwise false DOC R_DOC_Create Interrupts can only be enabled if a callback was registered using R_DOC_Create R20UT0708EE0211 Rev 2 11 Aug 01 201
378. filter the LOCO clock must be enabled Use R_CGC_Set with the LOCO selected Following a reset function R_LPC_GetStatus can be used to see what caused the reset If using a delay on Reset negation then the LOCO clock must be enabled See R_CGC_Set or R_CGC_Control If the CMPAZ2 pin input is selected the detection voltage is fixed at 1 33V The same voltage level must not be specified for more than one voltage monitor This includes voltage monitor 0 see R_MCU_OFS If this condition is detected this function will return false To enable the LVD event link output function enable the LVD first then enable the LVD event link function at the ELC To disable this function disable the LVD event link function at the ELC first then disable the LVD It is possible to configure the LVD to trigger the ELC but not generate an interrupt itself To do this setup the LVD as required using one of the following operations PDL_LVD_INTERRUPT_MI_DETECT_RISE or PDL_LVD_INTERRUPT_MI_DETECT_FALL or PDL_LVD_INTERRUPT_MI_DETECT_RISE_AND_FALL Set the callback function as PDL_NO_FUNC and set the interrupt priority to 0 Disable the digital filter circuit when using voltage monitoring 1 and 2 circuit in software standby mode or deep software standby mode Do not use the voltage detection 1 and 2 circuit in deep software standby mode with option PDL_LPC_DEEPCUT_ENABLE in function R_LPC_Create User wants to use both LVD1 and LVD2 user must configure both LVD1 a
379. finitions h void func void Enter deep software standby mode R_LPC Control PDL LPC MODE DEEP SOFTWARE STANDBY y Clear the I O port state retention R_LPC Control PDL LPC IO RELEASE y RENESAS eee RX210 Group 4 Library Reference 3 R_LPC_WriteBackup Synopsis Prototype Description Return value Category References Remarks Program example R20UT0708EE0211 Rev 2 11 Aug 01 2014 Write to the Backup registers bool R_LPC_WriteBackup uint8_t data1 Data pointer uint8_t data2 1 Data count Write data into the backup registers data1 The data to be written to the backup area data2 The number of bytes to be written to the backup area Valid from 1 to 32 True if all parameters are valid otherwise false LPC None The definition R_PDL_LPC_BACKUP_AREA_SIZE specifies the number of bytes that are available RPDL definitions include r pdl lpc h RPDL device specific definitions tinclude r pdl definitions h void func void uint8 t data to save R PDL LPC BACKUP AREA SIZE Write data into the backup registers R_LPC WriteBackup data_to_save R PDL LPC BACKUP AREA SIZE RENESAS ae RX210 Group 4 Library Reference 4 R_LPC_ReadBackup Synopsi
380. finitions h void func void Set all reserved 1 0 port pins to the recommended state R IO PORT NotAvailable R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS Page 4 45 RX210 Group 4 Library Reference 4 2 4 Multifunction Pin Controller The peripheral functions can be assigned to different pins controlled by the Multifunction Pin Controller The definitions available to the MPC functions are listed below MPC register definitions PDL_MPC_REG P03PFS PDL_MPC_REG PBOPFS PDL_MPC_REG_ POSPFS PDL_MPC_REG_ PB1PFS PDL_MPC_REG _PO7PFS PDL_MPC_REG _PB2PFS PDL_MPC_REG P12PFS PDL_MPC_REG PB3PFS PDL_MPC_ REG P13PFS PDL_MPC_ REG PB4PFS PDL_MPC_ REG P14PFS PDL_MPC_REG_PB5PFS PDL_MPC_REG P15PFS PDL_MPC_REG_PB6PFS PDL_MPC_REG P16PFS PDL_MPC_REG _PB7PFS PDL_MPC_REG_P17PFS PDL_MPC_REG _PCOPFS PDL_MPC_REG P20PFS PDL_MPC_REG PC1PFS PDL_MPC_ REG P21PFS PDL_MPC_REG PC2PFS PDL_MPC_REG P22PFS PDL_MPC_REG PC3PFS PDL_MPC_REG P23PFS PDL_MPC_REG _PC4PFS PDL_MPC_REG P24PFS PDL_MPC_REG PC5PFS PDL_MPC_ REG P25PFS PDL_MPC_REG PC6PFS PDL_MPC_REG P26PFS PDL_MPC_REG _PC7PFS PDL_MPC_REG P27PFS PDL_MPC_REG PDOPFS PDL_MPC_REG P30PFS PDL_MPC_REG PD1PFS
381. frequency Pulse width or duty cycle Callback function Callback function Interrupt priority level Set up a TMR timer channel or unit for periodic operation and start the timer data1 PDL_TMR_TMRO or PDL_TMR_TMR1 or PDL_TMR_TMR2 or PDL_TMR_TMR3 or PDL_TMR_UNITO or PDL_TMR_UNIT1 The channel n n 0 1 2 or 3 or unit n 0 or 1 to be configured data2 Configure the timer If multiple selections are required use to separate each selection The default settings are shown in bold e Period or frequency calculation PDL_TMR_PERIOD or The parameters data3 and data4 will contain either period PDL_TMR_FREQUENCY and pulse width or frequency and duty cycle e Output pin control PDL_TMR_OUTPUT_HIGH or Start with a high level or PDL_TMR_OUTPUT_LOW or low level output or PDL_TMR_OUTPUT_OFF no output on pin TMOn For 16 bit operation the pin shall be TMO2 when n 1 e Pulse DTC trigger co ntrol PDL_TMR_PULSE_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_TMR_PULSE_DTC_TRIGGER_ENABLE DTC at the pulse width interval e Period DTC trigger control PDL_TMR_PERIOD PDL_TMR_PERIOD_DTC_TRIGGER_DISABLE or Disable or enable activation of the DTC_TRIGGER_ENABLE DTC at the periodic interval data3 The period in seconds data4 or frequency in Hz The pulse width in seconds or duty cycle
382. g 3 destination string 3 1 uint8 t strlen source string 3 Start the controller R_DTC Control PDL_DTC_START PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA PDL_NO_DATA Generate a software interrupt request R_INTC Write PDL_INTC_REG_SWINTR 1 y Figure 5 12 Example of DTC chain transfer 5 10 Port Output Enable Figure 5 13 shows a usage example of Port Output Enable function PDL functions include r pdl poe h PDL device specific definitions tinclude r pdl definitions h R20UT0708EE0211 Rev 2 11 Page 5 24 Aug 01 2014 l ENESAS RX210 Group 5 Usage Examples void POEO 3 handler void void POE8 handler void void main void Configure POE pins R_POE Set POE 0 MODE EDGE POE 2 MODE LOW 16 POE 8 MODE LOW 8 POE 0 PORT C 4 PD POE 2 PORT A 6 PD POE 8 PORT E 3 POE HI Z REQ 8 ENABL I EQ OSTSTI POE HI Z REQ MTIOCOA Q MTIOCOB POE HI Z REQ MTIOCOC Q MTIOCOD P P P P OO Ooo Ooo q dA P P P P P E Create PDL POE IRQ HI Z E PDL POE IRQ SHORT 3 4 POEO 3 handler POE8 handler 15 while 1 void POEO 3 handler
383. g or both edges detected PDL_TMR_CLK_PCLK_DIV_1 or PDL_TMR_CLK_PCLK_DIV_2 or PDL_TMR_CLK_PCLK_DIV_8 or PDL_TMR_CLK_PCLK_DIV_32 or PDL_TMR_CLK_PCLK_DIV_64 or PDL_TMR_CLK_PCLK_DIV_1024 or PDL_TMR_CLK_PCLK_DIV_8192 The internal clock signal PCLKB 1 2 8 32 64 1024 or 8192 e Counter clearing PDL_TMR_CLEAR_DISABLE or Clearing is disabled PDL_TMR_CLEAR_CM_Aor Cleared after a compare match A occurs PDL_TMR_CLEAR CM Bor Cleared after a compare match B occurs PDL_TMR_CLEAR_RESET_RISING or Cleared by a rising edge on the external reset pin TMRIn PDL_TMR_CLEAR_RESET_HIGH Cleared when the external reset pin TMRIx x 0 or 2 for n 0 or 1 is high e Compare Match A DTC trigger control PDL_TMR_CM_A_DTC_TRIGGER_DISABLE or PDL_TMR_CM_A DTC TRIGGER ENABLE Disable or enable activation of the DTC when a Compare Match A occurs e Compare Match B DTC trigger control PDL_TMR_CM_B_DTC_TRIGGER_DISABLE or PDL_TMR_CM_B_DTC_TRIGGER ENABLE Disable or enable activation of the DTC when a Compare Match B occurs RENESAS Page 4 160 RX210 Group Description 2 2 Return value data3 Configure the output control If multiple selections are required use to separate each selection The default settings are shown in bold 4 Library Reference Output control for pin TMOy y 0 or 2 forn
384. ge is required specify PDL_NO_DATA If multiple selections are required use to separate each selection RENESAS TRARA RX210 Group 4 Library Reference Description 2 2 e Sub clock oscillator control PDL_CGC_SUB_CLOCK_ENABLE or PDL_CGC_SUB_CLOCK_DISABLE Enable or disable the sub clock oscillator PLL control PDL_CGC_PLL_ENABLE or PDL_CGC_PLL_DISABLE Enable or disable the PLL circuit WDT dedicated low speed on chip oscillator control PDL_CGC_IWDTLOCO_ENABLE or PDL CGC_IWDTLOCO_DISABLE Enable or disable the IWDTLOCO RTC initialization control PDL_CGC_RTC_TO_BE_USED or PDL_CGC_RTC_NOT_USE Select whether RTC will be used Return value True if all parameters are valid and exclusive and a selected clock source has been configured otherwise false Category Clock generation circuit References R_CGC_Set R_LPC_GetStatus R_LPC_Create Remarks e Use R_CGC_Set to configure a clock source before calling this function Ifthe oscillation stop detection flag is cleared the interrupt output is also disabled Use this function to re enable the interrupt output e Do not stop a clock that is in use Note that the PLL requires the main clock oscillator to be operating e Do not change the clock source if an Operating Power Control Mode transition is taking place see R_LPC_GetStatus If low speed operating mode 2 is select
385. ghest priority This parameter will be ignored if PDL_NO_FUNC is specified for all parameters func1 func2 and func3 True if all parameters are valid and exclusive otherwise false R20UT0708EE0211 Rev 2 11 Aug 01 2014 Category Timer TMR Reference R_TMR_Set Remarks e Please use R_TMR_Set to select the input TMCIn TMRIn and output TMOn pins as required This function will return false if a pin is enabled but is not set properly A closed clock loop will be created if The overflow signal from TMR1 is selected for TMRO and the compare match A signal from TMRO is selected for TMR1 or The overflow signal from TMR3 is selected for TMR2 and the compare match A signal from TMR2 is selected for TMR3 Either case should be avoided The output will be high impedance when PDL_TMR_OUTPUT_IGNORE_CM_A and PDL_TMR_OUTPUT_IGNORE_CM_B are selected e Ifa callback function is specified this function will enable the relevant interrupt Please see the notes on callback function usage in 6 Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed Page 4 158 2tENESAS RX210 Group 4 Library Reference Program example RPDL definitions include r pdl_tmr h RPDL device specific definitions include r pdl definitions h void func void Configure 1 R_T
386. gister RPDL definitions include r pdl_mpc h RPDL device specific definitions tinclude r pdl_definitions h void func void Set bit 7 in PFBCRO to 1 R_MPC_ Modify PDL MPC REG PFBCRO PDL _MPC_OR 0x80 i R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS oe RX210 Group 4 Library Reference 4 2 5 MCU operation 1 R_MCU_Control Synopsis Prototype Description Return value Category References Remarks Program example Control the operation of the MCU bool R_MCU_Control uint8_t data Control options Modify the MCU control registers data Select the operation states All selections are optional If multiple selections are required use to separate each selection e On chip ROM control PDL_MCU_ROM_ENABLE or PDL_MCU_ROM_DISABLE Enable or disable the on chip ROM Software reset control PDL_MCU_RESET_START Start a software reset of the MCU e Start type flag control PDL_MCU_WARM_START Set the Start type status flag to Warm True if a valid register is specified otherwise false MCU registers R_CGC Set R_RTC_Create e The PDL_MCU_WARM_START is used after the initialization of cold start caused by a power on reset has completed This is to indicate the next reset processing is warm start Caused by a reset si
387. gnal during operation RPDL definitions tinclude r pdl mcu h RPDL device specific definitions tinclude r pdl definitions h void func void Modify the MCU operation R_MCU Control PDL MCU ROM DISABLE R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS seen RX210 Group 4 Library Reference R_MCU_GetStatus Synopsis Prototype Description Return value Category References Remarks R20UT0708EE0211 Rev 2 11 Aug 01 2014 Read the MCU status bool R_MCU_GetStatus uint16_t data1 The location where the mode status flags shall be stored uint16_t data2 The location where the reset status flags shall be stored uint32_t data3 The storage location for the Option Function Select Register 0 uint32_t data4 The storage location for the Option Function Select Register 1 Read the status registers for the MCU data1 The mode status flags shall be stored in the format below Specify PDL_NO_PTR if they are not required b15 b14 b13 b12 b9 b8 Start up states User boot mode 0 0 Other 0 1 1 Selected b7 b5 b4 b1 bO Endian mode MD pin level 000b Big 0 0 Low 111b Little 1 High data2 The reset status flags shall be stored in the format below Specify PDL_NO_PTR if they are not required
388. gory References Remarks Program example R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference Read an MPC register bool R_MPC_Read uint8_t data1 MPC register selection uint8_t data2 Pointer to the variable where the MPC register s value shall be stored Get the value of an MPC register data1 One of the definition values from 84 2 4 data2 The value read from the register True if a valid MPC register is specified otherwise false MPC registers None None RPDL definitions include r pdl mpc h RPDL device specific definitions tinclude r pdl_definitions h void func void uint8 t data Get the value of register PFCSE R_MPC_Read PDL _MPC_REG PFCSE amp data RENESAS ia RX210 Group 4 Library Reference 2 R_MPC Write Synopsis Prototype Description Return value Category References Remarks Program example Write to a MPC register bool R_MPC_Write uint8_t data1 MPC register selection uint8_t data2 Data to be written to the MPC register Write the value to an MPC register data1 One of the definition values from 84 2 4 data2 The value to be written to the register True if a valid MPC register is specified otherwise false MPC registers None
389. guration uint16_tdata2 Output value uint16_tdata3 Output value Enable the DAC module and set the operating conditions data1 Configuration options To set multiple options at the same time use to separate each value The default settings are shown in bold Channel enable PDL_DAC 10 CHANNEL _0 Enable channel 0 PDL DAC 10 CHANNEL 1 Enable channel 1 Data alignment selection The alignment of the 10 bit output data within the 16 bit PDL_DAC_10_ALIGN_LEFT or parameters data2 and data3 PDL_DAC_10_ALIGN_RIGHT Left padded at the MSB end Right padded at the LSB end data2 The value to be written to the channel O output register Ignored if the channel is not enabled data3 The value to be written to the channel 1 output register Ignored if the channel is not enabled True if all parameters are valid and exclusive otherwise false DAC None e This function configures the relevant pin of selected channel for DAC operation This function brings the converter module out of the power down state This module is not available on the 48 pin package RPDL definitions include r pdl dac_10 h RPDL device specific definitions tinclude r pdl_definitions h void func void Set up DAC channel 0 with default operation mid voltage R_DAC_10_Create PDL DAC 10 CHANNEL 0 1024 2 0 R20UT0708EE0211 Rev 2 11 Aug 01 2014
390. he DTC read eeprom data static void write eeprom data void Set state variable so callback function will no how to behave g_IIC Tx State IIC_TX STATE WAIT DTC Send data to the EEPROM using the DTC R_IIC_MasterSend IIC CHANNEL PDL_IIC_DTC_ TRIGGER ENABLE EEPROM_ADDRESS PDL_NO_PTR 0 lic tx end handler 7 while g_ IIC Tx State IIC TX STATE FINISHED uint32 t iic flags uintl6 t flags uint32 t src uint32 t dest uintl6 t counter R_DTC _GetStatus dtc_iicl tx transfer data flags amp src amp dest amp counter PDL NO PTR i R_IIC GetStatus R20UT0708EE0211 Rev 2 11 Page 5 85 Aug 01 2014 ztENESAS RX210 Group 5 Usage Examples IIC CHANNEL amp iic flags PDL_NO PTR PDL_NO PTR Wait for 5ms while the EEPROM updates R_CMT CreateOneShot 0 0 5E 3 PDL_NO_FUNC 0 static void read eeprom data void g_IIC Rx busy true Read data from the EEPROM using the DTC R_IIC MasterReceive IIC CHANNEL PDL_IIC_DTC_TRIGGER ENABLE EEPROM_ADDRESS PDL_NO_PTR 0 lic rx end handler 7 while g_IIC_Rx_busy true This callback is registerd with R_IIC MasterSend We have configured the DTC to pass on the interrupt when it has transfered all data to the IIC so this will be called then This will also get called when the last byte has been transmi
391. he parameters supplied to R_ADC_12_CreateUnit and R_ADC_12_CreateChannel for configuration The data alignment is controlled using the R_ADC_12_CreateUnitfunction e If the temperature sensor or internal reference voltage is selected as the input source valid pointer should be supplied to data3 while data2 will be ignored lf analog channels are selected as the input source valid array pointer should be supplied to data2 If double trigger or self diagnostic is enabled the respective result will be stored to data3 if a valid pointer is supplied If no callback function is used this function waits for the IR flags to indicate that conversion is complete before reading the results If the ADC unit s control registers are directly modified by the user this function may lock up RPDL definitions include r pdl adc 12 h RPDL device specific definitions include r pdl definitions h void func void uintl6 t ADCresult 16 uintl6 t DIAGresult Read the ADC R_ADC_ 12 Read 0 ADCresult amp DIAGresult Page 4 281 RENESAS RX210 Group 4 Library Reference 4 2 26 10 bit Digital to Analog Converter 1 R_DAC_10 Create Synopsis Prototype Description Return value Category References Remarks Program example Configure the 10 bit DAC module bool R_DAC_10_Create uint8_t data1 Confi
392. he timer frequency in Hz or double The value to be put in register CMCOR uint16_t func The function to be called at the periodic interval Specify PDL_NO_FUNC if not required data4 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid and exclusive otherwise false Compare Match Timer R_CGC Set R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 178 RENESAS RX210 Group 4 Library Reference Remarks Program example e Function R_CGC_Set must be called with the current clock source selected before using this function Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed Ensure that the timer channel is stopped before calling this function The timing limits depend on the frequency of the peripheral module clock PCLKB frcike MHz Equation 32 12 5 12 8 8 Periodmin gt 250ns 640ns 667ns 1 0us de 92 Periodmax 1 05s 2 68s 2 79S 4 19s S recurs fmax Eras 4 0 MHz 1 56 MHz 1 5 MHz 1 0 MHz fmin est 0 95 Hz 0 37 Hz 0 357 Hz 0 24 Hz If the requested period is not a multiple of the minimum period the actual time period will be more than the requested time period RPDL
393. here the TGRD register value shall be stored For n 5 A pointer to where the TGRV register value shall be stored Specify PDL_NO_PTR if it is not required data8 For n 0 A pointer to where the TGRE register value shall be stored For n 5 Apointer to where the TGRW register value shall be stored Specify PDL_NO_PTR if it is not required data9 For n 0 A pointer to where the TGRF register value shall be stored Specify PDL_NO_PTR if it is not required True if all parameters are valid and exclusive otherwise false Multi function Timer Pulse Unit None e Ifthe flags are read any detection flag that has been set to 1 shall be automatically cleared to 0 by this function Page 4 145 RENESAS RX210 Group 4 Library Reference Program example RPDL definitions include r pdl_mtu2 h RPDL device specific definitions include r pdl definitions h uint8 t Flags uintl General_A uintl General_D I6 t L6 t void func void Read the status flags and registers of channel 3 R_MTU2_ReadChannel 3 amp Flags PDL _NO PTR amp General A PDL NO PTR PDL NO PTR amp General D PDL NO PTR PDL NO PTR R20UT0708EE0211 Rev 2 11 Page 4 146 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 7 R_MTU2_ReadUnit Synopsis Prototype Description Return value Category Referen
394. hless DC motor control 0 control unit para general control PDL MTU2 PWM RS COMP ENABLE control unit para register selection 0 R20UT0708EE0211 Rev 2 11 Page 5 109 Aug 01 2014 stENESAS RX210 Group 5 Usage Examples control unit para output control PDL MTU2 OUT P PHASE 3 ENAB U2 OUT N PHASE 3 ENAB PDL MTU2 OUT P PHASE 1 ENAB U2 OUT N PHASE 1 ENABI PDL MTU2 OUT _P PHASE 2 ENAB U2 OUT N PHASE 2 ENABI PDL MTU2 OUT _P PHASE ALL LOW HIGH R_MTU2 ControlUnit 0 control unit para i control parameter control setting PDL MTU2_ START control parameter register selection PDL_NO_ DATA Start count operation R_MTU2 ControlChannel 3 amp control parameter i while 1 Figure 5 59 Example of MTU operation R20UT0708EE0211 Rev 2 11 Page 5 110 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 29 Register Writer Protection This show an example of using the Register Write Protection Peripheral driver function prototypes include r pdl_ rwp h RPDL device specific definitions include r pdl definitions h void main void uint8 t PRCR_value uint8 t PWPR_ value Read the protection registers R_RWP_GetStatus amp PRCR_value amp PWPR_value de Enable access to the LVD registers R_RWP_ Control PDL RWP ENABLE LVD WRITE di Figure 5 60 Example
395. hould not be 0 or more than 15 Data use Parameter type The timer period in seconds or double The value to be put in register ADDISCR uint8_t func1 Page 4 274 RENESAS RX210 Group Description 4 4 Return value Category References Remarks R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference The function to be called when the ADC conversion scan cycle is complete in single scan mode and continuous scan mode or when the ADC conversion scan cycle is complete for Group A in group scan mode Specify PDL_NO_FUNC if no callback function is required data8 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func func2 The function to be called when the ADC conversion scan cycle is complete for Group B in group scan mode Specify PDL_NO_FUNC if no callback function is required data9 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func2 True if all parameters are valid and exclusive otherwise false 12 bit ADC R_CGC_Set e Interrupts are enabled automatically if a callback function is specified Please see the notes on callback function usage in 6 e If an external trigger is used the low level pulse width must be
396. hronisation Disable or enable the IIC clock PDL_SCI_IIC_CLOCK_SYNC_DISABLE or synchronisation PDL_SCI_IIC_CLOCK_SYNC_ENABLE Note Clock synchronisation is enabled by default as required for normal operation True if all parameters are valid otherwise false SCI Page 4 233 RENESAS RX210 Group Program example R20UT0708EE0211 Rev 2 11 Aug 01 2014 RPDL definitions include r pdl_sci h RPDL device specific definitions include r pdl definitions h void func void Terminate SCI reception on channel 0 R_SCI_Control 0 PDL SCI_STOP_RX RENESAS 4 Library Reference Page 4 234 RX210 Group 4 Library Reference 11 R_SCI_GetStatus Synopsis Prototype Description Return value Category Reference Check the status of an SCI channel bool R_SCI_GetStatus uint8_t data1 uint8_t data2 II Status flags uint8_t data3 Last byte received uint16_t data4 Bytes transmitted uint16_t data5 Bytes received Channel selection Acquires the channel status and the byte counts data1 Select channel SCln where n 0 to 12 data2 The status flags shall be stored in one of the following formats depending on the current mode Note Some bits are Not Applicable NA in all modes see descriptions Asynchronous or Synchronous modes Not II
397. id func void Stop the sub clock oscillator R CGC Control PDL NO DATA PDL NO DATA PDL CGC SUB CLOCK DISABLE Select the PLL R_CGC Control PDL_CGC_CLK_PLL PDL_NO_DATA PDL_NO_DATA R20UT0708EE0211 Rev 2 11 Page 4 11 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 3 R_CGC_GetStatus Synopsis Prototype Description Configure the clock generation circuit bool R_CGC_GetStatus uint16_t data Pointer to the variable where the status value shall be stored Read the clock status register Return value Category References Remarks Program example data The status flags shall be stored in the format below b15 b14 b13 b12 b11 b10 b9 b8 HOCO power Clock control 0 P HOCO IWDTLOCO LOCO Sub clock Main clock PLL 0 Power on 0 Operating 1 Power off 1 Stopped b7 b6 b4 b3 b2 b1 bO Selected clock source Main clock oscillation stop detection 000b LOCO 0 001b HOCO 0 0 Disabled 0 Normal operation pd 1 Enabled 1 Stop detected 011b Sub clock i i 100b PLL True Clock generation circuit R_CGC_Control Use R_CGC_Control to try to clear the oscillation stop detection flag Call this function to confirm that the clearing has occurred If not call R_CGC_Control again and repeat until
398. ied in your project are listed below The options other than cpu dbl_size are the default setting of the compiler cpu rx200 round nearest denormalize off dbl_size 8 unsigned_char unsigned_bitfield bit_order right unpack noexception rtti off fint_register 0 branch 24 2 The options which must NOT be specified in your project are listed below As the default setting of the compiler the following options are not specified int_to_short auto_enum base patch pic pid nouse_pid_register Save_acc 13 Using the library within your project The driver library can be used in two ways 1 3 1 Via the PDG graphical utility PDG can be downloaded from www renesas com pda The directions for use of the PDG utility are given in the PDG manual 1 3 2 Using RPDL stand alone To add the driver library to your project s build environment you need to a Unzip the RPDL distribution b Copy the required source header and library files into your project folder using the copy utility batch file c Include the required source files d Add the driver library file to the linked files list The instructions to follow for stand alone use start are given below 1 Unzip the RPDL files Double click on the file RPDL_RX210 exe to unpack the files The default location is C Renesas RPDL_RX210 R20UT0708EE0211 Rev 2 11 Page 1 2 Aug 01 2014 RENESAS RX210 Group 1 Introduct
399. ify PDL_NO_FUNC if not required ignored for n O and 3 data12 The interrupt priority level for overflow or underflow events Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for both parameters func5 and func6 True if all parameters are valid and exclusive otherwise false Timer Pulse Unit e Device packages with 144 pins or more incorporate a TPU e Ifa callback function is specified this function will enable the relevant CPU interrupt Please see the notes on callback function usage in 6 Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed e Ifthe channel is configured for phase counting mode the counter clock source setting is ignored For more detail of the phase counting mode please refer to the RX210 hardware manual If buffer operation is selected for registers TGRA and TGRC input capture output compare is not valid for register TGRC If buffer operation is selected for registers TGRB and TGRD input capture output compare is not valid for register TGRD e If synchronous mode is required at least two channels must be enabled for synchronous operation e Calling this function TPU will start automatically Page 4 309 RENESAS RX210 Group 4 Library Reference Program example RPDL definitions inc
400. iguration selection void func Callback function uint8_t data3 Interrupt priority level 4 2 29 Comparator B 1 R_CPB_Create Synopsis Prototype Description Return value Category Reference Remarks Set up a comparator B channel data1 The channel number n where n 0 or 1 data2 Configure the comparator B channel To set multiple options at the same time use to separate each value The default settings are shown in bold e Comparator B Interrupt control PDL_CPB_IRQ_DISABLE or PDL_CPB_IRQ_ENABLE Disable or enable interrupt Comparator B Interrupt ELC edge selection PDL_CPB_IRQ_ELC_FALLING_EDGE or PDL_CPB_IRQ_ELC_RISING_EDGE or PDL_CPB_IRQ_ELC_BOTH_ EDGE Select interrupt or ELC trigger at falling edge rising edge or both edges e Comparator B filter select register PDL_CPB_FILTER_DISABLE or Disable the comparator B filter PDL_CPB_PCLK_DIV_1 or PDL_CPB_PCLK_DIV_8 or PDL_CPB_PCLK_DIV_32 or PDL_CPB_PCLK_DIV_64 Enable the comparator B filter Select the sampling frequency at PCLKB 1 8 32 or 64 e DMAC DTC trigger control PDL_CPB_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_CPB_DMAC_TRIGGER_ENABLE or DMAC or DTC when comparator value PDL_CPB_DTC_TRIGGER_ENABLE matches with the reference value func The function to be called when comparator value matches with the
401. in PDL_SPI_SSL_DELAY_6 or Ignored in Slave mode PDL_SPI_SSL_DELAY_7 or PDL_SPI_SSL_DELAY_8 Extended next access delay PDL_SPI_NEXT_DELAY_1 or PDL_SPI_NEXT_DELAY_2 or PDL_SPI_NEXT_DELAY_3 or PDL_SPI_NEXT_DELAY_4 or PDL_SPI_NEXT_DELAY_5 or PDL_SPI_NEXT_DELAY_6 or PDL_SPI_NEXT_DELAY_7 or PDL_SPI_NEXT_DELAY_8 The number of bit clock periods plus two cycles of the peripheral clock between the end of one frame and the start of the next frame Ignored in Slave mode True if all parameters are valid otherwise false SPI R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 264 RENESAS RX210 Group 4 Library Reference Reference R_SPI_Create Remarks e Ifa channel is disabled using PDL_SPI_DISABLE call R_SPI_Create to resume channel Program example operations RPDL definitions include r pdl spi h RPDL device specific definitions include r pdl definitions h void func void Enable direct loopback mode R SPI Control 0 PDL SPI LOOPBACK DIRECT PDL NO DATA Change the extended timings R_SPI Control 0 PDL NO DATA PDL SPI CLOCK DELAY 8 PDL SPI SSL DELAY 5 de R20UT0708EE0211 Rev 2 11 Page 4 265 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 7 R_SPI_GetStatus Synopsis Check the status of an SPI cha
402. in for MTIOCOA PDL_MTU2_PIN_0B_P13 or PDL_MTU2_PIN_0B_P15 or PDL_MTU2 PIN OB PA Select the P13 P15 or PA1 pin for MTIOCOB PDL_MTU2_PIN_0C_P32 or PDL_MTU2 PIN OC _PB1 Select the P32 or PB1 pin for MTIOCOC PDL_MTU2_PIN_0D_P33 or PDL_MTU2_PIN_OD_PA3 Select the P33 or PA3 pin for MTIOCOD Valid when n 1 PDL_MTU2_PIN_1A_P20 or PDL_MTU2 PIN 1A PE4 Select the P20 or PE4 pin for MTIOC1A PDL MTU2 PIN 1B P21 or PDL_MTU2 PIN 1B_PB5 Select the P21 or PB5 pin for MTIOC1B Valid when n 2 PDL_MTU2_PIN_2A P26 or PDL_MTU2 PIN 2A PB5 Select the P26 or PB5 pin for MTIOC2A PDL_MTU2_PIN 2B P27 or PDL_MTU2 PIN 2B PE5 Select the P27 or PES pin for MTIOC2B Valid when n 3 PDL_MTU2_PIN_3A P14 or PDL_MTU2_PIN_3A P17 or PDL_MTU2_PIN_3A_PC1 or PDL_MTU2_PIN_3A_PC7 or PDL_MTU2 PIN 3A PJ1 Select the P14 P17 PC1 PC7 or PJ1 pin for MTIOC3A PDL_MTU2_PIN 3B P17 or PDL_MTU2_PIN_3B_P22 or PDL_MTU2_PIN_3B_P80 or PDL_MTU2_PIN_3B_PB7 or PDL_MTU2 PIN 3B _PC5 Select the P17 P22 P80 PB7 or PC5 pin for MTIOC3B PDL_MTU2_PIN 3C_ P16 or PDL_MTU2_PIN_3C_P56 or PDL_MTU2_PIN_3C_PCO or PDL_MTU2_PIN_3C_PC6 or PDL_MTU2 PIN 3C PJ3 Select the P16 P56 PCO PC6 or PJ3 pin for MTIOC3C PDL_MTU2_PIN_3D_P16 or PDL_MTU2_PIN_3D_P23 or PDL_MTU2_PIN_3D_P81 or PDL_MTU2_PIN_3D_PB6 or PDL_MTU2 PIN 3D_PC4 Select the P16 P23 P81 PB6 or PC4 pin f
403. include r pdl_definitions h void func void Configure SPI channel 0 commands 0 and 1 R_SPI_ Command 0 0 PDL SPI CLOCK MOD PDL SPI LENGTH 8 PDL NO DATA i R_SPI_ Command 0 1 PDL SPI CLOCK MOD PDL SPI LENGTH 8 PDL NO DATA R20UT0708EE0211 Rev 2 11 Aug 01 2014 E 0 E E 1 E PDL SPI ASSERT PDL SPI MSB FIRST PDL SPI ASSERT PDL SPI LSB FIRST RENESAS _SSLO OSSLI Page 4 261 RX210 Group 5 R_SPI_Transfer Synopsis Prototype Description 4 Library Reference Transfer data over an SPI channel bool R_SPI_Transfer uint8_t data1 Channel selection uint8_t data2 II DMAC DTC control uint32_t data3 Transmit data start address uint32_t data4 Receive data start address uint16_t data5 II Sequence loop count void func II Callback function uint8_t data6 Interrupt priority level In Master mode transfer the data to and or from the Slave device In Slave mode transfer the data under control of the Master device data1 Select channel SPIn where n 0 only data2 Select the automatic data transfer options The default setting is shown in bold Specify PDL_NO_DATA to use the default e DMAC DTC trigger control PDL_SPI_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_SPI_DMAC_
404. initions h U2 ControlUnit structure control unit para U2 Create structure create parameters U2 ControlChannel structure control parameter void main void Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Set channel 3 output pins MTIOC3B MTIOC3D R_MTU2_Set 3 PDL MTU2 PIN 3B PB7 PDL MTU2_ PIN 3D PB6 i Set channel 4 output pins MTIOC4A MTIOC4C MTIOC4B MTIOC4D R_MTU2 Set 4 PDL MTU2 PIN 4B PC2 PDL MTU2 PIN 4D PC3 PDL MTU2 PIN 4A PE2 PDL MTU2 PIN 4C PE1l di Load the defaults R_MTU2 Create load defaults amp create parameters Set the non default options create parameters channel mode PDL MTU2 MODE NORMAL create parameters TGRA TCNTV_ value 3000 create parameters TGRB TCNTW value 2000 R_MTU2 Create 4 amp create parameters i Load the defaults R_MTU2 Create load defaults amp create parameters Set the non default options create parameters channel mode PDL MTU2 MODE PWM RS create parameters counter operation PDL MTU2 CLK PCLK DIV 256 PDL MTU2_CLEAR_TGRA create parameters TGRA TCNTV value 4800 TGRA create parameters TGRB TCNTW value 3500 TGRB R_MTU2 Create 3 amp create parameters i control unit para simultaneous control 0 control unit para buffer control 0 control unit para brus
405. int8_t data16 II CSWOFF cycles IIWDOFF cycles II AWAIT cycles 1 RDON cycles 1 WRON cycles 1 WDON cycles II CSON cycles Set up an external bus area data1 The address area n where n 0 to 3 data2 Configure the operation of area CSn If multiple selections are required use to separate each selection The default settings are shown in bold External bus width PDL_BSC_WIDTH_8 or PDL_BSC_WIDTH_16 Select 8 or 16 bit data bus width Endian mode PDL_BSC_ENDIAN_SAME or PDL_BSC_ENDIAN_OPPOSITE Set the bus endian mode to be the same or opposite to that of the CPU e Multiplexed mode PDL_BSC_SEPARATE or PDL_BSC_MULTIPLEXED Select separate or multiplexed address and data pins e Write access mode PDL_BSC_WRITE_BYTE or PDL_BSC_WRITE_SINGLE Select byte or single write strobe mode External wait control PDL_BSC_WAIT_DISABLE or PDL_BSC_WAIT ENABLE Disable or enable external wait control using the WAIT signal e Page access control PDL_BSC_PAGE_READ_DISABLE or PDL_BSC_PAGE_READ_ NORMAL or PDL_BSC_PAGE_READ CONTINUOUS Disable or enable page read accesses using normal access compatible mode or continuous assertion mode PDL_BSC_PAGE_WRITE_DISABLE or PDL_BSC_PAGE_WRITE_ENABLE Disable or enable page write accesses data3 The number of read recovery cycles RR
406. ion Perform an IIC master read data1 Select channel SCln where n 0 to 12 data2 Control options The default options are shown in bold Specify PDL_NO_DATA to use the defaults e DMAC DTC trigger control PDL_SCI_IIC_DMAC_DTC_TRIGGER_DISABLE or PDL_SCI_IIC_DMAC_TRIGGER_ENABLE or PDL_SCI_IIC_DTC_TRIGGER_ENABLE Disable or enable activation of the DMAC or DTC for the data stage e Slave Address Size PDL_SCI_IIC_7_BIT_SLAVE_ADDRESS or PDL_SCI_IIC_10 BIT_SLAVE_ADDRESS Specify the slave address width e Repeated Start PDL_SCI_IIC_RESTART The transfer will start with a re start rather than the default behaviour of a start condition Stop Condition selection By default the transfer will end with a stop condition PDL_SCI_IIC_NOSTOP Select this option to prevent the stop condition being generated data3 Slave address either 7 or 10 bits use the format as specified here b15 b8 b7 b1 bO 7 bit address b15 b11 b10 b1 bO 10 bit address data4 The number of data bytes that must be transferred before the function completes or the callback function is called If the DMAC or DTC shall be used to handle the received data specify PDL_NO_DATA data5 The start address of the buffer that will receive the data Specify PDL_NO_PTR if no data shall be processed by this function e g if the DMAC or DTC sha
407. ion 2 Copy the files into your project area Navigate to where the RPDL files were unpacked A RPDL_RX210 File Edit View Favorites Tools ae Address C RenesasiRPDL_Rx210 Y EJ co Common Device specific E Copy _RPOL_RX210 bat 3 objec 8 05 KB 4 My Computer Double click on the file Copy_RPDL_RX210 bat to start the copy process The batch file requires some information about the target device so that it can configure RPDL correctly cx C WINDOWS system32 cmd exe Renesas RPDL for R8210 copy utility Please enter a number to select the endian option 1 little endian 2 big endian Select the endian option by pressing a number and then press Enter cx C WINDOWS system32 cmd exe Renesas RPDL for R8210 copy utility Please enter a number to select the endian option 1 little endian 2 big endian i Please enter the path where you wish RPDL for R8210 to be installed Type the full path to the folder where you wish RPDL to be copied to and then press Enter Note Put the path in double quotes if the path includes spaces The utility will create a folder in the location that you specified and copy the files into the new folder R20UT0708EE0211 Rev 2 11 Page 1 3 Aug 01 2014 RENESAS RX210 Group 1 Introduction lox Renesas RPDL for RX210 copy utility Please enter a number to select the endian option 1 little endian 2 big endian 1 Please enter the path
408. ion Applies only to reset synchronised or complementary PWM modes Brushless DC motor waveform control PDL_MTU2_BDCM_ENABLE or PDL_MTU2_BDCM_DISABLE Enable or disable brushless DC motor control PDL_MTU2_BDCM_P_PHASE_ENABLE or Enable or disable PWM outputs on the PDL_MTU2_BDCM_P_PHASE_DISABLE positive phase output pins PDL_MTU2_BDCM_N_PHASE_ENABLE or Enable or disable PWM outputs on the PDL_MTU2_BDCM_N_PHASE_DISABLE negative phase output pins PDL_MTU2_BDCM_OPS_FB or Use input capture signals for output switch control or PDL_MTU2_BDCM_OPS_000 or PDL_MTU2_BDCM_OPS_001 or PDL_MTU2_BDCM_OPS_010 or PDL_MTU2_BDCM_OPS_011 or Set the outputs according to table 21 39 in PDL_MTU2_BDCM_OPS_100 or the hardware manual PDL_MTU2_BDCM_OPS_101 or PDL_MTU2_BDCM_OPS_110 or PDL_MTU2 BDCM_OPS 111 RENESAS Page 4 141 RX210 Group Description 4 4 Return value Category R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference general_control General control settings All settings are optional If multiple selections are required use to separate each selection e Interrupt skipping control PDL_MTU2_INT_SKIP_TROUGH_DISABLE or PDL_MTU2_INT_SKIP_TROUGH_1 or PDL_MTU2_INT_SKIP_TROUGH_2 or PDL_MTU2_INT_SKIP_TROUGH_3 or PDL_MTU2_INT_SKIP_TROUGH_4 or PDL_MTU2_INT_SKIP_TROUGH_5 or PDL_MTU2_INT_SKIP_
409. ion or subtraction selection PDL_RTC_ERROR_ADJUST_PLUS or PDL_RTC_ERROR_ADJUST_MINUS Select if the adjustment value will be added or subtracted from the count Update the Error Adjustment value PDL_RTC_ERROR_UPDATE_ERROR_ADJUST_VALUE Select to specify a new error adjustment value Error Adjustment Value Valid Range 0 to 3Fh New automatic error adjustment value ignored if not selected above data8 Configure the Capture 0 RTCICO pin options To set multiple options at the same time use to separate each value Edge PDL_RTC_CAPTURE_EDGE_NONE or PDL_RTC_CAPTURE_EDGE_RISING or PDL_RTC_CAPTURE_EDGE_FALLING or PDL_RTC_CAPTURE EDGE BOTH event Select the edge that will trigger a capture Time Capture Noise Filter Control PDL_RTC_CAPTURE_FILTER_OFF or PDL_RTC_CAPTURE FILTER_ON_DIV_1 or PDL_RTC_CAPTURE FILTER_ON DIV_32 Configure the capture noise filter If enabling select the sampling period relative to the count source data9 Configure the Capture 1 RTCIC1 pin options To set multiple options at the same time use to separate each value Edge PDL_RTC_CAPTURE_EDGE_NONE or PDL_RTC_CAPTURE_EDGE_RISING or PDL_RTC_CAPTURE_EDGE_FALLING or PDL_RTC_CAPTURE EDGE BOTH event Select the edge that will trigger a capture Time Capture Noise Filter Control PDL_RTC_CAPTURE_FILTER_OFF or PDL_RTC_CAPT
410. ion selection Initialise the POE pins data1 Configure the input pin detection for pins POEO to POE3 and POE8 If multiple selections are required use to separate each selection All settings are optional Specify PDL_NO_DATA if none are required PDL_POE_0_MODE_EDGE or PDL_POE_0 MODE LOW _8 or PDL_POE_0 MODE _LOW_16 or PDL_POE 0 MODE LOW_128 PDL_ POE 1 MODE EDGE or PDL POE 1 MODE LOW 8 or PDL POE 1 MODE LOW 16 or PDL_POE 1 MODE LOW 128 PDL POE 2 MODE EDGE or PDL POE 2 MODE LOW 8or PDL_POE 2 MODE LOW_16 or PDL POE 2 MODE LOW 128 PDL_POE_3_MODE EDGE or PDL_POE_3 MODE LOW _8or PDL_POE_3 MODE_LOW_16 or PDL_POE_3 MODE LOW_128 PDL_POE_8 MODE_EDGE or PDL_POE_8 MODE_LOW_8or PDL_POE_8 MODE_LOW_16 or PDL_POE_8 MODE LOW_128 For each pin POEO to POE3 and POE8 select falling edge or low level for 16 samples at PCLKB 8 16 or 128 data2 Allocate the pins for signals POEO to POE3 and POE8 If multiple selections are required use to separate each selection All settings are optional Specify PDL_NO_DATA if none are required PDL_POE_0 PORT C 4or PDL_POE_0 PORT D 7 Pin POEO input selection PDL POE 1 PORT B 5or PDL POE 1 PORT D 6 Pin POE1 input selection PDL_POE_2_PORT_3_4 or PDL POE 2 PORT D 5 PDL_POE_2 PORT_A 6or Pin POE2 input selection PDL_POE_3_PORT_3_3 or PDL_POE
411. iption Return value Category Reference Write to timer unit registers bool R_TMR_ControlUnit uint8_t data1 Unit selection uint32_t data2 Configuration selection uint16_t data3 Register value uint16_t data4 Register value uint16_t data5 Register value Modify a timer unit s counter and compare registers data1 The unit number n where n 0 or 1 data2 The channel settings to be modified If multiple selections are required use to separate each selection e Counter stop re start PDL_TMR_STOP or PDL_TMR_START Disable or re enable the counter clock source e The counter or compare registers to be modified PDL_TMR_COUNTER Update the timer counter register TCNT PDL_TMR_TIME_CONSTANT_A Update the timer compare match A register TCORA PDL_TMR_TIME_CONSTANT_B Update the timer compare match B register TCORB data3 The 16 bit counter value This will be ignored if the register is not selected data4 The 16 bit compare match A value This will be ignored if the register is not selected data5 The 16 bit compare match B value This will be ignored if the register is not selected True if all parameters are valid and exclusive otherwise false Timer TMR R_TMR_CreateUnit Remarks R20UT0708EE0211 Rev 2 11 Aug 01 2014 For unit 0 the upper byte is the value for TMRO and the lower byte i
412. ircuits This function supports 1 Setting voltage thresholds and detection types 2 Controlling the operation 3 Reading the detection status R20UT0708EE0211 Rev 2 11 Page 2 8 Aug 01 2014 RENESAS RX210 Group 2 Driver 2 9 Clock Frequency Accuracy Measurement Circuit Driver The driver functions support access to the registers which control the Clock Frequency Accuracy Measurement Circuit These functions support 1 Configuring the operation 2 Stopping the operation 3 Modifying the operation 4 Reading the status R20UT0708EE0211 Rev 2 11 Page 2 9 Aug 01 2014 RENESAS RX210 Group 2 Driver 2 10 Low Power Consumption Driver The driver functions support access to the registers which select the lower power modes of operation for the microcontroller These functions support 1 Configuring the state while in standby mode and the activity that can be used to resume operation 2 Selecting one of the low power modes 3 Writing data to the backup memory area 4 Reading data from the backup memory area 5 Determining the cause of the exit from the lowest power mode R20UT0708EE0211 Rev 2 11 Page 2 10 Aug 01 2014 RENESAS RX210 Group 2 Driver 2 11 Register Write Protection Driver The driver functions support the control of the Register Write Protection providing the following operations 1 Enabling or disabling writing to the registers 2 Reading the status of the write protecti
413. is not used coocccconocccccononcnccononcncnononcncnanoncnn nano nn cc canon cc cnn nn nccc naar nccnnns 5 39 1 Initialize RTC with providing sub clock use case sub clock is available oooooononnnnnnnn n c 5 39 2 Initialize RTC without providing ClOCK sesira noaa a O nr crac E 5 41 5 15 3 Use case of RTC over reset and power consumption ooococononococincncconnnononccnncnnnnnnnononncnnnnnnnnnns 5 42 1 Wake up from sleep mode cccccceeeetecccceceeeeeeeeeeneeeeeeeeeeceneaeaeceeeeeseseneaeaeeeeeeesetensieeeeeeeeteees 5 42 2 Wake up from deep standby mode ooocccccinoccccnnnoccccnnnoncccnononccnnn nono cc nn non cn rra rr cn nn rn 5 47 5 16 Independent Watchdog Timer inrcis ieri a ae AA TARR A EAA AAEE SER TEELE ERR 5 52 5 17 Serial Communication Interface ooncconnnncccnnnocccccnnoncccnononcncnnnon cnc naar nnnc canon cnc naar nn nr naar nn cr naar a ncr nana nnccnnns 5 53 5 17 1 SCI Asynchronous Using Polling ssns innnan i eaa a eaaa 5 53 5 17 2 SCI Asynchronous Using Interrupts oooooccccnnnccccnnnocccccononcccnononcncnononcncnnnnncccnn nn ncc naar nnccnnnnnnccnnns 5 54 5 17 3 SCI Asynchronous Using DMAC oriei eieaa enie eii Teaia nncr naar nnncinns 5 56 5 17 4 Synchronous Transmission and Reception oocccconoccccnnnocccccnnoncncnononcncnnnncncnnnnnnnc nana nccnnnnncccnns 5 58 5 17 5 Synchronous Full Duplex Operation oooooooccccnncccocononocococcoccnnnnononnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnanns 5 60
414. ises channels TMR2 and TMR3 True Timer TMR None The timer unit is put into the stop state to reduce power consumption RPDL definitions tinclude r pdl_tmr h RPDL device specific definitions tinclude r pdl_definitions h void func void Shutdown channels 0 and 1 R_TMR_Destroy 0 y R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS Page 4 168 RX210 Group 4 Library Reference 7 R_TMR_ControlChannel Synopsis Prototype Description Return value Category Reference Remarks R20UT0708EE0211 Rev 2 11 Aug 01 2014 Write to timer channel registers bool R_TMR_ControlChannel uint8_t data1 Channel selection uint32_t data2 Configuration selection uint8_t data3 Register value uint8_t data4 Register value uint8_t data5 Register value Modify a timer channel s operation counter and compare registers data1 The channel number n where n 0 1 2 or 3 data2 The channel settings to be modified If multiple selections are required use to separate each selection Counter stop re start PDL_TMR_STOP or PDL_TMR START Disable or re enable the counter clock source The counter or compare registers to be modified PDL_TMR_COUNTER Update the timer counter register TCNT PDL_TMR_TIME_CONSTANT_A Update the timer compa
415. ister s value shall be stored True if all parameters are valid and exclusive otherwise false Interrupt control None For register select one of the registers listed in the tables starting on page 4 26 RPDL definitions include r pdl_intc h RPDL device specific definitions tinclude r pdl_definitions h void func void uint8 t ipl Read the IPL bits R_INTC_Read PDL INTC REG IPL amp ipl y R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS fee RX210 Group 4 Library Reference 9 R_INTC Write Synopsis Prototype Description Return value Category Reference Remarks Program example Update an interrupt register bool R_INTC_Write uint16_t data1 Register selection uint8_t data2 Register value Write the new value to an interrupt register data1 e The register to be updated PDL_INTC_REG_IPL or Select the current CPU interrupt priority level or PDL_INTC_REG_IR_ register or Interrupt Request register or PDL_INTC_REG_IER_ register or Interrupt Request Enable register or PDL_INTC_REG_IPR_ register or Interrupt Priority register or PDL_INTC_REG_DTCER register or DTC Activation Enable register or PDL_INTC_REG_SWINTR Software interrupt activation register data2 The value to be written to the register True if the pa
416. ister value Register value Register value void func1 void func2 void func3 void func4 uint8_t data11 void func5 void func6 uint8_t data12 Set up a 16 bit TPU channel data1 The channel number n where n 0 to 5 data2 Configure the channel mode If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Operation mode Callback function Callback function Callback function Callback function Interrupt priority level Callback function Callback function Interrupt priority level PDL_TPU_MODE_NORMAL or Normal operation PDL_TPU_MODE_PWM1 or PDL_TPU_MODE PWNM2 or Pulse Width Modulation PWM mode 1 or 2 PDL_TPU_MODE_PHASE1 or PDL_TPU_MODE_PHASE2 or PDL_TPU_MODE_PHASE3 or PDL_TPU_MODE_PHASE4 Phase counting mode 1 2 3 or 4 Valid for n 1 2 4 and 5 Timer start stop PDL_TPU_START or PDL_TPU_STOP Start or stop the count operation Synchronous mode PDL_TPU_SYNC_DISABLE or PDL_TPU_SYNC_ ENABLE Disable or enable synchronous operation Noise Filter for TIOCA PDL_TPU_TIOCA_NF_DISABLE or PDL_TPU_TIOCA_NF_ENABLE Disable or enable noise filter for TIOCA Noise Filter for TIOCB PDL_TPU_TIOCB_NF_DISABLE or PDL_TPU_TIOCB_NF_ENABLE Disable or enable noise filter for TIOCB Noise Filter f
417. it selection is valid otherwise false Compare Match Timer R_CMT_Create The timer unit is put into the stop state to reduce power consumption RPDL definitions include r pdl_cmt h RPDL device specific definitions tinclude r pdl_definitions h void func void Shutdown channels 0 and 1 R_CMT Destroy 0 R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 182 RENESAS RX210 Group 4 R_CMT_Control Synopsis Prototype Description Return value Category Reference Remarks 4 Library Reference Control CMT operation bool R_CMT_Control uint8_t data1 Channel selection uint16_t data2 Configuration selection double data3 II Period frequency or register data Modify the operation of a CMT channel data1 The channel number n where n 0 1 2 or 3 data2 Configure the timer channel To set multiple options at the same time use to separate each value Counter stop re start PDL_CMT_STOP Disable the counter clock source PDL_CMT_START Enable the counter clock source Value change request PDL_CMT_PERIOD or The parameter data3 will contain the new period PDL_CMT_FREQUENCY or frequency PDL_CMT_CONSTANT or constant register CMCOR or PDL_CMT_COUNTER counter register CMCNT value data3 The new period frequency or register value This will
418. ize PDL_DMAC_SIZE 8 or PDL_DMAC_SIZE 32 PDL_DMAC_SIZE_16 or Select 8 16 or 32 bits for the data to be transferred Interrupt generation optional PDL_DMAC_IRQ_END Transfer completion PDL_DMAC_IRQ_ ESCAPE _END Escape end PDL_DMAC_IRQ_REPEAT_SIZE_END 1 repeat size or 1 block data transfer completion PDL_DMAC_IRQ_EXT_SOURCE Extended repeat area overflow on the source Extended repeat area overflow on the PDL_DMAC_IRQ_EXT_DESTINATION destination R20UT0708EE0211 Rev 2 11 Page 4 91 Aug 01 2014 RENESAS RX210 Group 4 Library Reference Description 2 3 e Start trigger forwarding PDL_DMAC_TRIGGER_CLEAR or When the DMAC transfer is complete clear the PDL_DMAC_TRIGGER_FORWARD_ DMAC activation trigger or pass it on to the CPU e DTC trigger control PDL_DMAC_DTC_TRIGGER_DISABLE or PDL_DMAC_DTC_TRIGGER_ENABLE Disable or enable activation of the DTC when an event specified in the Interrupt generation options occurs data3 Select one activation source for channel DMAn e Trigger selection Trigger cause PDL_DMAC_TRIGGER_SW or By software PDL_DMAC_TRIGGER_CMTO or PDL_DMAC_TRIGGER_CMT1 or Compare match on channel CMTn PDL_DMAC_TRIGGER_CMT2 or n 0 to 3 PDL_DMAC_TRIGGER_CMT3 or PDL_DMAC_TRIGGER_SPIO_RX or Receive buffer full on RSPI channel 0 PDL_DMAC_TRIGGER_SPIO_TX or Transmit buffer empt
419. k source The calls to R_CGC_Set configure the LOCO dividers and enable the main clock oscillator and the PLL circuit After an appropriate time to allow for the crystal based main clock oscillator and the PLL circuit to stabilise a call to R_CGC_Control is used to select the PLL circuit as the clock source Peripheral driver function prototypes include r pdl cgc h include r pdl cmt h RPDL device specific definitions include r pdl definitions h void main void Set the LOCO clock settings the clock source used after a power on reset ICLK 125 kHz PCLKD not used PCLKB 125 kHz FOLK 125 kHz BCLK not used R_CGC PDL CGC CLK LOCO L_CGC_BCLK DISABLE PDL CGC SUB CLOCK CL STANDARD E3 E3 L NO DATA E3 E3 L NO DATA L NO DATA vurr mr P it Prepare the sub clock settings ICLK 32 768 KHz PCLKD 20 MHz PCLKB 20 MHz FCLK 20 MHz BCLK not used BCLK pin not used R_CGC Set PDL CGC CLK SUB CLOCK PDL CGC _BCLK_ DISABLE 32768 32768 32768 32768 32768 PDL_NO_DATA PDL CGC_SUB 32768 7 Prepare the main clock settings ICLK 20 MHz PCLKD 20 MHz PCLKB 20 MHz FCLK 20 MHz BCLK 20 MHz BCLK pin 10 MHz R CGC Set PDL CGC CLK MAIN PDL CGC_BCLK DIV 2 PDL CGC MAIN E ERNAL 20E6 20E6 20E6 20E6 20E6 20E6 PDL NO DATA
420. kbps to PEEKE 391 kbps 375 kbps 1 00 Mbps 250 kbps f 32 6 10 kbps to 5 86 kbps to 15 6 kbps to 500 3 91 kbps to PERS 195 kbps 187 5 kbps kbps 125 kbps f 64 3 05 kbps to 2 93 kbps to 7 81 kbps to 250 1 95 kbps to PEIS 97 7 kbps 93 75 kbps kbps 62 5 kbps f 128 1 53 kbps to 1 46 kbps to 3 91 kbps to 125 977 bps to POLKB 48 8 kbps 46 875 kbps kbps 31 3 kbps The actual rise and fall times will not be zero Using the limits from the 1 C specification Rise time rate lt 100 kbps 1000 ns 100 kbps lt rate lt 400 kbps 300 ns 400 kbps lt rate lt 1 Mbps 120 ns Fall time rate lt 400 kbps 300 ns 400 kbps lt rate lt 1 Mbps 120 ns Maximum rate 1 Mbps The achievable transfer rates are frcike _ Hz IRC 12 5 12 32 8 PCLKB 1 175kbpsto1 168 5kbpsto 446 kbps to 1 116 kbps to 1 Mbps 1 Mbps Mbps Mbps PCLKB 2 86 7 kbps to 1 83 6 kbpsto 217kbps o1 5 8 kbps to 1 Mbps 1 Mbps Mbps Mbps PCLKB 4 45 9 kbps to1 44 2 kbps to 116 kbps to 1 30 0 kbps to Mbps 1 Mbps Mbps 806 kbps PCLKB 8 23 7 kbps to 22 7 kbps to 57 8 kbps to 1 15 3 kbps to 658 kbps 635 6 kbps Mbps 446 kbps PCLKB 16 12 0 kbps to 11 5 kbps to 30 0 kbps to 7 73 kbps to 316 kbps 306 1 kbps 806 kbps 217 kbps PCLKB 32 6 06 kbps to 5 8 kbps to 15 3 kbps to 3 89 kbps to 175 kbps 168 5 kbps 446 kbps 116 kbps PCLKB 64 3 04 kbps to 2 9 kbps to 7 73 kbps to 1 95 kbps to 8
421. l True if all parameters are valid and exclusive otherwise false Bus Controller None e If itis necessary to call this function call it once only Ensure that both the DTC and DMAC are stopped RPDL definitions tinclude r pdl bsc h RPDL device specific definitions tinclude r pdl definitions h void func void Give internal main bus 1 priority access to the internal peripheral bus 1 R_BSC_ Set PDL_BSC_PRIORITY PB1 MBL i R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS ds RX210 Group 2 R_BSC_Create Synopsis Prototype Description 1 2 R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference Configure the external bus operation bool R_BSC_Create uint16_t data1 uint32_t data2 uint16_t data3 Bus control pin selection Bus address pin selection 1 Recovery cycle insertion uint8_t data4 void func uint8_t data5 Error control Callback function Interrupt priority level Configure the I O pins cycle insertion error detection and register the callback function d ata1 Configure the bus control signals Use to separate each selection Ignored for packages with less than 100 pins specify PDL_NO_DATA Chip select pin selection only required for each external memory area that will be enabled PDL_BSC_CS0_P24 or PDL_BSC_CSO PC7 Select the p
422. l output low toggles at compare match TIOCCH initial output high goes low at compare match TIOCCn output high TIOCCn initial output high toggles at compare match PDL_TPU_C_IC_RISING_EDGE or PDL_TPU_C_IC_FALLING_EDGE or PDL_TPU_C_IC_BOTH EDGES or Input capture at TIOCCn rising edge Input capture at TIOCCH falling edge Input capture at TIOCCn both edges PDL_TPU_C_IC_TPU_COUNT_CLK Input capture at TPU n 1 count clock count up or count down Invalid if TPU n 1 uses PCLK 1 Input capture output compare control for register TGRD PDL_TPU_D_OC_DISABLED or PDL_TPU_D_OC_LOW or PDL_TPU_D_OC_LOW_CM_HIGH or PDL_TPU_D_OC_LOW_CM_INV or PDL_TPU_D_OC_HIGH_CM_LOW or PDL_TPU_D_OC_HIGH or PDL_TPU_D_OC_HIGH_CM_INV or TIOCDn output disabled TIOCDn output low TIOCDn initial output low goes high at compare match TIOCDn initial output low toggles at compare match TIOCDn initial output high goes low at compare match TIOCDn output high TIOCDn initial output high toggles at compare match PDL_TPU_D_IC_RISING_EDGE or PDL_TPU_D_IC_FALLING_EDGE or PDL_TPU_D_IC_BOTH_EDGES or Input capture at TIOCDn or TIOCCn rising edge Input capture at TIOCDn or TIOCCHn falling edge Input capture at TIOCDn or TIOCCn both edges See below for TIOCDn or TIOCCn pin selection PDL_TPU_D_IC_TPU_COUNT_CLK Input capture at TPU n 1 count clock count up or count down Invalid if TPU n 1
423. lChannel Add R_TPU_ControlUnit R_CGC_Set Add new parameter and options for RTC count source selection and sub clock stabilization times R_CGC_Set Add new remarks relating to sub clock usage R_CGC_Set Add an example code of using sub clock into Program examples R_CGC_Control Remove invalid option of HOCO frequency control Main clock oscillator drive type control both type 1 and 2 and sub clock oscillator drive control R_CGC_Control Add new RTC initialization control and new remarks relating to sub clock usage Remove invalid description in Sub clock oscillator control and invalid remarks R_CGC_GetStatus Add Sub clock oscillator is not available for 48 pin package R_MCU_Control Replace the remark by The PDL_MCU_WARM_START is used after the initialization of cold start caused by a power on reset has completed This is to indicate the next reset processing is warm start caused by a reset signal during operation R_LVD_Create Add remark User wants to use both LVD1 and LVD2 user must configure both LVD1 and LVD2 simultaneously R_ELC_Control Add remark Event PDL_ELC_LINK_EVENT_SPI_ERROR cannot be used if multi master configuration SPI operation and master mode are selected for the RSPI This function will return false if this condition is detected R_MTU2_Set Add missing pin for channel 3 R_MTU2_ControlUnit Add remark for complementary PWM mode R_TMR_Set Add missing pins R_RTC_Create Remove RTC use cont
424. latile uint8 t receive data NUM_DATA void main void uint8 t i bool id received Initialise the system clocks NOTE The code to initialise the system clock using R CGC Set is omitted here Initialise the receive buffer for i 0 i lt NUM_DATA i receive data i 0 Set pins R SCI Set 9 PDL SCI PIN SCI9 RXD9 PB6 PDL SCI PIN SCI9 TXD9 PB7 Configure the RS232 port specify Async MP mode R_SCI_Create 9 PDL SCI_8N1 PDL_SCI_ASYNC MP 9600 Async MP mode data Reception by CPU ISR data received false error happen false Wait by CPU ISR until receive matching Station ID 0x0A R_SCI Receive 9 0x0A00 PDL SCI MP ID CYCLI PDL NO PTR 0 SCIrx SCIEr y while data received false R20UT0708EE0211 Rev 2 11 Page 5 62 Aug 01 2014 ztENESAS RX210 Group 5 Usage Examples data received false Receive data ID 0x0A by CPU ISR R_SCI Receive 9 PDL_NO_DATA receive data 10 SCIrx SCIEr while data received false PEE 5255445525252 Se35e52524e5e8 Async MP mode data Reception by polling Seo gt gt gt o o id_received false Wait by polling until receive matching Station ID 0x01 id received R SCI Receive 9 0x0100 PDL SCI MP ID CYCLE PDL NO PTR 0 PDL NO FUNC SCIEr y
425. lect the P14 P24 PA4 or PC6 pin for MTCLKA Select the P15 P25 PA6 or PC7 pin for MTCLKB e Valid when n 0 or 2 PDL_MTU2_PIN CLKC_ P22 or PDL_MTU2_PIN_CLKC_PA1 or Select the P22 PA1 or PC4 pin for MTCLKC PDL_MTU2 PIN CLKC PC4 PDL_MTU2_PIN CLKD_ P23 or PDL_MTU2_PIN_CLKD_PA3 or PDL_MTU2_PIN_CLKD_PC5 Select the P23 PA3 or PC5 pin for MTCLKD When n 2 required in Phase Counting Mode only True if all parameters are valid and exclusive otherwise false Multi function Timer Pulse Unit R_MTU2_Create Before calling R_MTU2_Create call this function to configure the relevant pins Make sure no more than one peripheral function is assigned to a single pin Make sure the configuration of MTCLK pins is consistent for all the channels e Device packages with 80 or fewer pins do not have all of the pin options R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 123 RENESAS RX210 Group 4 Library Reference Program example include r pdl_mtu2 h void func void Configure the MTU pins R_MTU2_Set 0 PDL MTU2 PIN 0A P34 R20UTO708EE0211 Rev 2 11 L2 Z Page 124 Aug 01 2014 RENESAS RX210 Group 2 R_MTU2 Create Synopsis Prototype Description 1 9 R20UT0708EE0211 Rev 2 11 Aug 01 2014 Configure an MTU channel bool R_MTU2_Create uint8_t data1
426. lid only if the Software trigger option has been selected e This function must be called in order to start the DMAC The Suspend Enable and Start control is executed at the end of the function If a channel has completed a transfer parameters may be changed and the channel re enabled in one function call RENESAS ee RX210 Group 4 Library Reference Program example RPDL definitions include r pdl_ dmac h RPDL device specific definitions include r pdl definitions h include lt string h gt const char source string 1 Renesas RX210 volatile char destination string 1 ooooooooooomoooo void func void Re enable transfers on channel 2 R_DMAC Control L_DMAC ENABLE L NO PTR L NO PTR L NO DATA L NO DATA L NO DATA L NO DATA L NO DATA W U W YUU TN eS y Reload and trigger channel 1 R_DMAC Control 1 PDL DMAC ENABLE PDL DMAC START PDL DMAC UPDATE SOURCE PDL DMAC UPDATE DESTINATION PDL DMAC UPDATE COUNT PDL _DMAC UPDATE SIZE source string 1 destination string 1 1 uint16_t strlen source_string 1 PDL NO DATA PDL NO DATA PDL NO DATA R20UT0708EE0211 Rev 2 11 Page 4 98 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 4 R_DMAC_GetStatus Synopsis Prototype Description Return value Catego
427. ll be used to process the received data Page 4 230 RENESAS RX210 Group Description 2 2 4 Library Reference func Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Return value Category Reference Transfer method Parameter PDL_NO_FUNC This function will continue until the required number of Polling Sy bytes has been transferred or an error occurs The function to be called when the transfer has completed or an error Interrupts detected Either the function to be called when each byte is transferred or DMAC PDL_NO_FUNC if the callback function specified in R_DMAC_Create will be used DTC The function to be called at the interval specified in R_DTC_Create In Polling Mode True if all parameters are valid and the operation completed OK false if a parameter was out of range or an error was detected In Non Polling mode True if all parameters are valid false if a parameter was out of range SCI R_SCI_GetStatus R_SCI_IIC_ReadLastByte R_SCI_Control Remarks Program example R20UT0708EE0211 Rev 2 11 Aug 01 2014 The maximum number of characters to be received is 65535 e Wait until a transmission on the same channel is complete before calling this function e Callback functions are executed by the interrupt processing function This means that no other interrupt
428. lled when a TGRB event occurs For n 5 The function to be called when a TGRV event occurs Specify PDL_NO_FUNC if not required func3 For n 0 3 or 4 The function to be called when a TGRC event occurs For n 5 The function to be called when a TGRW event occurs Specify PDL_NO_FUNC if not required func4 For n 0 3 or 4 The function to be called when a TGRD event occurs Specify PDL_NO_FUNC if not required interrupt_priority_1 The interrupt priority level for TGR A to D or U to W events Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for all parameters func 1 to 4 func5 For n 0 The function to be called when a TGRE event occurs Specify PDL_NO_FUNC if not required func6 For n 0 The function to be called when a TGRF event occurs Specify PDL_NO_FUNC if not required func7 For n 0 to 3 The function to be called when an overflow occurs For n 4 The function to be called when an overflow or underflow occurs Specify PDL_NO_FUNC if not required func8 Forn 1 or2 The function to be called when an underflow occurs Specify PDL_NO_FUNC if not required interrupt_priority_2 The interrupt priority level for TGRE TGRF overflow or underflow events Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for all parameters func 5 to 8 True if all
429. lude r pdl_tpu h RPDL device specific definitions include r pdl definitions h void TPUO_1V callback void void func void Configure TPUO PCLK clear after a compare match A R_TPU_Create 0 PDL TPU MODE NORMAL PDL TPU CLK PCLK DIV 1 PDL TPU CLEAR CM A PDL NO_ DATA PDL NO DATA 199 99 553 66 88 PDL_NO_FUNC PDL NO FUNC PDL NO FUNC PDL NO FUNC 0 TPUO_1V_callback PDL_NO FUNC 0 R20UT0708EE0211 Rev 2 11 Page 4 310 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 3 R_TPU_Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example Disable a timer unit bool R_TPU_Destroy uint8_t data Unit selection Shut down a timer pulse unit data The timer pulse unit For this device this must always be 0 True if the unit selection is valid otherwise false Timer Pulse Unit The timer pulse unit is put into the stop state to reduce power consumption include r pdl tpu h void func void Shutdown TPU R TPU Destroy 0 y R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 311 2tENESAS RX210 Group 4 Library Reference 4 R_TPU_ControlChannel Synopsis Control a timer channel Prototype bool R_TPU_ControlChannel uint8_t data1 Channel selec
430. marks Refer to R_RTC_Create for the time and date formats If the current time or date values are updated the clock is stopped during the update If the day of week is updated using automatic calculation the most recent year month and date will be used The range checking for either day value uses the most recent year and month values e If entering software standby or deep software standby mode soon after modifying the RTC values use R_RTC_Read first to confirm that the values are correct If the output of the RTCOUT pin is enabled or disabled the clock is stopped during the update e If capture is enabled for a capture pin that has not been selected in R_RTC_Create this function will return false This function is called after R_RTC_Create or R_RTC_CreateWarm This module is not available on the 48 pin package R20UT0708EE0211 Rev 2 11 Page 4 194 Aug 01 2014 RENESAS RX210 Group 4 Library Reference Program example RPDL definitions include r pdl_rtc h RPDL device specific definitions include r pdl definitions h void func void Disable the alarm calendar and update the alarm time R_RTC_Control PDL RTC ALARM DATE DISABLE PDL RTC UPDATE ALARM TIME PDL NO DATA PDL NO DATA 0x00105300 Alarm at 10 53 PDL NO DATA PDL NO DATA PDL NO DATA PDL NO DATA PDL NO DATA PDL NO DATA y Ch
431. matchA PDL_INTC_VECTOR_CMIB1 TMR Compare match B PDL_INTC_VECTOR_OVI1 channel 1 Overflow PDL_INTC_VECTOR_CMIA2 8 bit timer Compare matchA PDL_INTC_VECTOR_CMIB2 TMR Compare match B PDL_INTC_VECTOR_OVI2 channel 2 Overflow PDL_INTC_VECTOR_CMIA3 8 bit timer Compare match A PDL_INTC_VECTOR_CMIB3 TMR Compare match B PDL_INTC_VECTOR_OVI3 channel 3 Overflow PDL_INTC_VECTOR_DMACOI Direct PDL_INTC_VECTOR_DMAC1I memory Transfer complete or Transfer PDL_INTC_VECTOR_DMAC2I access escape end PDL_INTC_VECTOR_DMAC3I controller PDL_INTC_VECTOR_ERIO Error in data received PDL_INTC_VECTOR_RXIO SCI channel Data received PDL_INTC_VECTOR_TXI0O 0 Start of next data transfer PDL_INTC_VECTOR_TEIO End of data transfer PDL_INTC_ VECTOR _ERI1 SCI channel Error in data received PDL_INTC_VECTOR_RXI1 1 Data received R20UT0708EE0211 Rev 2 11 Page 4 19 Aug 01 2014 RENESAS RX210 Group Description 3 4 PDL_INTC_VECTOR_TXI1 Start of next data transfer PDL_INTC_VECTOR_TEI1 End of data transfer PDL_INTC_VECTOR_ERI2 Error in data received PDL_INTC_VECTOR_RXI2 SCI channel Data received PDL_INTC_VECTOR_TXI2 2 Start of next data transfer PDL_INTC_VECTOR_TEI2 End of data transfer PDL_INTC_VECTOR_ERI3 Error in data received PDL_INTC_VECTOR_RXI3 SCI channel Data received PDL_INTC_VECTOR_TXI3 3 Start of next data transfer PDL_INTC_VECTOR_TEI3 End of data transfer PDL_INTC_VECTOR_ERI4 Error in data received PDL_INTC_VECTOR_RXI4 SCI channel Data r
432. ment Bus Serial Peripheral Interface Watchdog Timer R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS 1 Introduction Page 1 18 RX210 Group 2 Driver 2 Driver 2 1 Overview This library provides a set of peripheral function control programs peripheral drivers for Renesas microcontrollers and allows the peripheral driver to be built into a user program 2 2 Control Functions summary This library has the following control functions available as peripheral drivers 1 Clock Generation Circuit These driver functions are used to configure the multiple internal clock signals 2 Interrupt These driver functions are used for configuring the external interrupt pins handling fixed interrupts and controlling the interrupt priority 3 WV OPort These driver functions are used to configure the I O pins and provide data read write compare and modify operations 4 Multifunction Pin Control These driver functions are used for configuring the I O pin optional functions 5 MCU Operation These driver functions are used for configuring the MCU operation 6 Voltage Detection Circuit These driver functions are used for configuring the low voltage detection response 7 Clock Frequency Accuracy Measurement Circuit These driver functions are used for configuring the clock comparisoncircuit 8 Low Power Consumption These driver functions are used for selecting lower power consumption 9 Register Write Prot
433. meter func True if all parameters are valid otherwise false SPI R_SPI_Create Page 4 262 RENESAS RX210 Group Remarks Program example 4 Library Reference The amount of data for must match the total number of transfer frames refer to parameter data3 in R_SPI_Create If a callback function is specified and DMAC DTC control is not used interrupts are used to handle the data transfer Please see the notes on callback function usage in 86 When using transmit only in slave mode return of the function by using polling or trigger of interrupt by using interrupt or DTC DMAC does not ensure the end of transmission After using this function use R_SPI_GetStatus to check for and clear any error flags RPDL definitions include r pdl spi h RPDL device specific definitions tinclude r pdl_definitions h void func void uint32 t transmit _data 8 uint32 t receive data 8 Transmit and receive all enabled frames once R_SPI Transfer 0 PDL NO DATA transmit data receive data 1 PDL_NO_FUNC 0 R20UT0708EE0211 Rev 2 11 Page 4 263 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 6 R_SPI_Control Synopsis Prototype Description Return value Category Control an SPI channel bool R_SPI_Control uint8_t data1 uint8_t data2 uint32_t da
434. meters are valid otherwise false I O port None e lf an invalid port or pin is specified the operation of the function cannot be guaranteed RPDL definitions include r pdl io port h RPDL device specific definitions tinclude r pdl definitions h void func void Set the output of port pin P05 R_IO PORT Write PDL IO PORT 0 5 0 y Set the output of port 6 R_IO PORT Write PDL_IO PORT 6 0x55 i R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS dei RX210 Group 4 Library Reference 6 R_IO_PORT_Compare Synopsis Prototype Description Return value Category References Remarks Program example R20UT0708EE0211 Rev 2 11 Aug 01 2014 Check the pin states on an I O port bool R_IO_PORT_Compare uint16_t data1 Input port or port pin selection uint8_t data2 Comparison value void func II Function pointer Read the input state of an I O port or I O port pin and call a function if a match occurs data1 Use either one of the following definition values from 4 2 3 One port definition or One port pin definition data2 The value to be compared with Between 0x00 and OxFF for a port 0 or 1 for a pin func The function to be called if a match occurs True if the parameters are valid otherwise false I O port R_IO_PORT_Set e lf an invali
435. mp Flags while 1 R20UT0708EE0211 Rev 2 11 Page 5 103 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples Select the PLL as the clock source void CPB _handlerl void Toggle the LED state R_IO PORT Modify PDL IO PORT 1 4 PDL IO PORT XOR 1 Figure 5 55 Example of Comparator B R20UT0708EE0211 Rev 2 11 Page 5 104 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 26 Data Operation Circuit This shows the configuration of the DOC and the DMAC to sum an array of numbers PDL functions include r pal dogn include r pdl dmac h PDL device specific definitions include r pdl definitions h define DMAC CHANNEL 0 define DATA COUNT 10 static void Callback Done void Data to calculate sum of static uint16 t data DATA COUNT 1 2 3 4 5 6 7 8 9 10 Callback Flag static volatile bool g bCallbackDone false void main void uint8 t status uintl6 t result Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Setup the DOC in addition mode initial value 0 R_DOC_Create PDL DOC MODE ADD 0 PDL NO FUNC 0 Setup DMAC to write data to the 16bit DOC Input register R_DMAC Create DMAC_CHANNEL PDL DMAC BLOCK PDL DMAC SOURCE ADDRESS PLUS PDL DMAC DESTINATION ADDRESS FIXED PDL DMAC SIZE 16 PDL_DMAC_IRQ_ PDL_DMAC_TRIGGER_SW data
436. nctions 3 Run time control of outputs interrupts and flags 4 Checking the module status R20UT0708EE0211 Rev 2 11 Page 2 17 Aug 01 2014 RENESAS RX210 Group 2 Driver 2 18 8 bit Timer Driver The driver functions support the use of the four 8 bit timers providing the following operations 1 2 8 9 Selection of the TMR pins for use Configuring a channel for use using register values which have been determined elsewhere Configuring two channels as a 16 bit pair using register values which have been determined elsewhere Configuration for as a periodic timer including e Automatic clock setting using frequency or period as an input e Automatic pulse width setting using pulse width or duty cycle as an input e Automatic interrupt control Configuration for as a one shot timer including e Automatic clock setting using pulse width as an input e Automatic interrupt control e CPU sleep option e Automatic support for using two channels as a single 16 bit timer Disabling channels that are no longer required and enabling low power mode Control of a single timer channel Control of two timer channels when configured as one 16 bit channel Control of channels in periodic mode enabling pulse width modulation PWM output 10 Reading the registers of a single timer channel 11 Reading the registers of a 16 bit timer channel pair Note The Clock Generation Circuit must be configured befo
437. nd LVD2 simultaneously RPDL definitions tinclude r pdl_lvd h RPDL device specific definitions tinclude r pdl_definitions h void Callback LowVoltage void void func void Use Monitor 2 to generate an NMI when VCC drops below 4V R_LVD Create PDL NO_ DATA PDL NO DATA PDL LVD INTERRUPT NMI DETECT FALL PDL LVD FILTER DISABLE PDL LVD VDET2 PIN VCC PDL LVD VOLTAGE LEVEL 400 4 00V PDL NO FUNC PDL NO DATA Callback _LowVoltage 15 R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS ae RX210 Group 2 R_LVD_Control Synopsis Prototype Description Return value Category References Remarks Program example R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference Control the voltage detection circuit bool R_LVD_Control uint8_t data1 Monitor 1 control uint8_t data2 1 Monitor 2 control Control the voltage detection configuration data1 Monitor 1 control All selections are optional If multiple selections are required use to separate each selection If no selections are required specify PDL_NO_DATA e Monitor control PDL_LVD_DISABLE Disable monitor 1 operation e Flag control PDL_LVD_CLEAR DETECTION Clear the monitor 1 change det
438. nd day BCD format is used If not required specify PDL_NO_DATA b31 b16 b15 b8 b7 b0 Year Month Day Valid from O to 9999 Valid from 1 to 12 Valid from 1 to the number of days in the month data5 Configure the Capture 0 RTCICO pin options To set multiple options at the same time use to separate each value The default settings are shown in bold Edge PDL_RTC_CAPTURE_EDGE_NONE or PDL_RTC_CAPTURE_EDGE_RISING or PDL_RTC_CAPTURE_EDGE_FALLING or PDL_RTC_CAPTURE EDGE BOTH Select the edge that will trigger a capture event Time Capture Noise Filter Control PDL_RTC_CAPTURE_FILTER_OFF or PDL_RTC_CAPTURE FILTER_ON_DIV_1 or PDL_RTC_CAPTURE FILTER ON DIV_32 Configure the capture noise filter If enabling select the sampling period relative to the count source data6 Configure the Capture 1 RTCIC1 pin options To set multiple options at the same time use to separate each value The default settings are shown in bold Edge PDL_RTC_CAPTURE_EDGE_NONE or PDL_RTC_CAPTURE_EDGE_RISING or PDL_RTC_CAPTURE_EDGE_FALLING or PDL_RTC_CAPTURE EDGE BOTH Select the edge that will trigger a capture event Time Capture Noise Filter Control PDL_RTC_CAPTURE_FILTER_OFF or PDL_RTC_CAPTURE FILTER_ON_DIV_1 or PDL_RTC_CAPTURE FILTER_ON DIV_32 Configure the capture noise filter If enabling select the sampling p
439. ng R CGC Set is omitted here Set up a DMAC channel for IIC transmission R_DMAC Create 3 PDL _DMAC NORMAL PDL DMAC SOURCE_ADDRESS PLUS PDL DMAC DESTINATION ADDRESS FIXED PDL DMAC SIZE 8 PDL DMAC IRQ PDL _DMAC_TRIGGER_IICO_TX eeprom data array 1 uint8 t RIICO ICDRT 6 PDL NO DATA PDL NO DATA PDL NO DATA PDL NO DATA iic tx dmac end handler 7 Set up a DMAC channel for IIC reception R_DMAC Create 2 PDL DMAC NORMAL PDL _DMAC SOURCE ADDRESS FIXED PDL DMAC DESTINATION ADDRESS PLUS PDL DMAC SIZE 8 PDL DMAC IRQ PDL DMAC TRIGGER_IICO RX uint8 t RIICO ICDRR data storage A PDL NO DATA PDL NO DATA PDL NO DATA PDL NO_ DATA lic rx dmac end handler R20UT0708EE0211 Rev 2 11 Page 5 79 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples de Select the IIC I O pins R_TIC Set PDL_IIC_PIN SDA PDL IIC PIN SCL i Select IIC mode at 100kHz 300ns rise time 200ns fall time R_IIC_Create 0 PDL ITIC MODE IIC PDL IIC_INT PCLK DIV 8 0 0 0 0 100E3 300 lt lt 16 200 y Write the data into the EEPROM write eeprom data Prepare the next data for the EEPROM R_DMAC Control 3 PDL DMAC SUSPEND PDL DMAC UPDATE SOURCE PDL DMAC UPDATE COUNT eprom data array 2 L_NO PTR F L NO D
440. ng RTC is used and wake up from deep standby mode R20UT0708EE0211 Rev 2 11 Page 5 51 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 16 Independent Watchdog Timer This shows an example of Independent Watchdog timer usage The watchdog timer is configured with a 25 to 75 window and to generate an NMI Interrupt if it does time out Because the watchdog timer is not refreshed it does time out and the NMI_handler function is called Peripheral driver function prototypes include r pdl iwdt h include r pdl cgc h include r pdl intc h PDL device specific definitions include r pdl definitions h extern void NMI_handler void void main void Initialise the system clocks NOTE The code to initialise the system clock using R CGC Set is omitted here Enable the IWDTCLK clock R_CGC_Set PDL CGC CLK IWDTLOCO DATA DATA DATA DATA DATA DATA DATA DATA IULUVUYOUVUOI P P P P P P P P Enable the NMI interrupt for IWDT R_INTC_CreateExtInterrupt PDL INTC NMI PDL_INTC_IWDT_ENABLE NMI_handler 7 Configure WDT with a 75 to 25 window generate NMI on time out R_IWDT_Set PDL_IWDT_TIMEOUT_8192 PDL IWDT CLOCK OCO 16 PDL IWDT WIN START 75 PDL IWDT WIN END 25 PDL_IWDT TIMEOUT NMI Wait for time out while 1 Figure 5 27 Example of Indep
441. nitions h volatile uint8 t switch swl pressed volatile uint8 t irg4 low Callback function prototypes void IROlHandler void void IRQ4Handler void static void ReEnableIRQ4 void void main void uint8 t irq status Set the CPU s Interrupt Priority Level to 0 R_INTC Write PDL INTC REG IPL 0 i Configure the IRQ interrupt on pin PD_1 R_INTC SetExtInterrupt PDL INTC_IRO1 PORT D R_INTC_CreateExtInterrupt PDL_INTC_IRQI PDL INTC FALLING IROlHandler 7 Configure the IRQ3 interrupt on pin P3_3 R_INTC_SetExtInterrupt PDL INTC_IRQ3 PORT 3 R_INTC_CreateExtInterrupt PDL_INTC_IRQ3 PDL INTC FALLING PDL_NO FUNC 0 y Configure the IRQ4 interrupt on pin P3_4 R_INTC_SetExtInterrupt PDL _INTC_IRO4 PORT 3 R_INTC_CreateExtInterrupt PDL_INTC_IRQ4 PDL INTC LOW TROQ4Handler 15 i irg4 low false while 1 Poll the IRQ1 flag R_INTC GetExtInterruptStatus R20UT0708EE0211 Rev 2 11 Page 5 4 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples PDL_INTC_IRO1 amp irg status de if irq_status amp 0x01 0 Disable IRQ1 R_INTC_ControlExtInterrupt PDL _INTC_IRQ1 PDL INTC DISABLE Has IRQ4 triggered if irq4 low true 1 Re enable the interrupt if the signal has returned to the high level R_1O_ PORT Compare PDL IO PORT 3 2 1 ReEnabl
442. nly in complementary PWM mode Buffer operation PDL_MTU2_BUFFER_AC_DISABLE or PDL_MTU2_BUFFER_ AC ENABLE Disable or enable buffer operation for registers TGRA and TGRC Valid for n 0 3 and 4 PDL_MTU2_BUFFER_BD_DISABLE or PDL_MTU2 BUFFER BD ENABLE Disable or enable buffer operation for registers TGRB and TGRD Valid for n 0 3 and 4 PDL_MTU2_BUFFER_EF_DISABLE or PDL_MTU2 BUFFER EF ENABLE Disable or enable buffer operation for registers TGRE and TGRF Valid for n 0 Buffer data transfer PDL_MTU2_BUFFER_AC_CM_A or PDL_MTU2_BUFFER_AC_TCNT_CLR Transfer the data from TGRC to TGRA when a compare match A occurs or when TCNT is cleared in each channel Valid for n 0 3 and 4 PDL_MTU2_BUFFER_BD_CM_B or PDL_MTU2_BUFFER_BD_TCNT_CLR Transfer the data from TGRD to TGRB when a compare match B occurs or when TCNT is cleared in each channel Valid for n 0 3 and 4 PDL_MTU2_BUFFER_EF_CM_E or PDL_MTU2_BUFFER_EF_TCNT_CLR Transfer the data from TGRF to TGRE when a compare match E occurs or when TCNT is cleared in either channel Valid for n 0 Transfer on TCNT clear is available only in PWM mode 1 or 2 R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS Page 4 128 RX210 Group Description 5 9 R20UT0708EE0211 Rev 2 11 Aug 01 2014 TGR_A_B_ operation Configure the operation for general registers 4 Library Reference TGRA and
443. nnancccnn nono cannnrrr cnn nr 4 61 Riz CAC lt Create entabla atinada iate silba 4 61 RICAC DestO Y simio ideas EA E foie diia cidade betes dida iii E TE 4 64 MARA A 4 65 RCAC GetStatus i e tit lili id aaa ida aeaaeae aaa aia ae at pt aaas 4 67 Low Power Consumption A 4 68 LAA A O O 4 68 A NO 4 74 AAA A O 4 76 R LEPC ReadBackup ii e aa a ideada bateat acti aaiae aaa aeaa e a i aeaaee aeS 4 77 RILPC Gets id dd Add datada 4 78 Register Write Protection e Assane RE TES ARAA e aA ea AO RIDA AARE 4 79 R RWP Control is title id e eaa a ae A A it 4 79 R RWP GetSt tU Sina a ae AA A aa A eaaa a ita 4 80 Bus Controller sirsa ee Li Id id eaaa de esa 4 81 R BSO Bra A A AAA AAA A At 4 81 REBSOC CEI it la A A AAA it 4 82 RUEBSOCTEA O TOA trail A AAA tata 4 85 RUBS DeStOys 20 da id A A AA id 4 88 RUBSO CONTO A AAA AAA ita 4 89 R BSC GetStatus id dd ld IS A dit A ad 4 90 DMA Controler Aa a o o ah 4 91 RB ITNO Create A EE E AE ET E La Anc 4 91 ADMA O De SO a a a a E E 4 95 RUDMAC Control ia dd O o a E 4 96 RR DMAC GerStatus ic a een ae aie a ete nes ha aie o aaa ig 4 99 PEN EC A 4 101 RODTE Si E io ea chee 4 101 RADE Cy Create 1 A A E AA 4 102 Re DCH DESO a ido 4 106 RD Cx Control EAE etre aaa 4 107 RID CS GetStatUs ad es a he 4 109 Event Mk Controlletcct 4 iia 4 111 AA O Aea Aaaa 4 111 Ro EEC DESTA ect ee ne eee ee coed 4 112 R JELG Read ari nt A E A A AD 4 113 R ELG Writes 00 A dads cde A ae ee eds 4 114 R ELC Cont
444. nnel Prototype bool R_SPI_GetStatus uint8_t data1 Channel selection uint16_t data2 Status flags uint16_t data3 Sequence count Description Acquires the SPI channel status data1 Select channel SPIn where n 0 only data2 The status flags shall be stored in the format below Specify PDL_NO_PTR if this information is not required b15 b14 b12 b11 b10 b8 0 Error command 0 Command pointer b7 b6 b5 b4 b3 b2 b1 bO Receive Transmit Parity error Mode fault Bus state Overrun buffer 0 buffer 0 error 0 Empty 0 Full 0 No error 0 No fault 0 Idle 0 No error 1 Full 1 Empty 1 Detected 1 Detected 1 Active 1 Detected data3 The storage location for the number of sequence loops that have been completed in the current transfer Specify PDL_NO_PTR if this information is not required Return value True if all parameters are valid otherwise false Category SPI Reference None Remarks Ifthe status flags are read and an error or fault flag is set to 1 the flag will be cleared to O by this function Program example RPDL definitions include r pdl spi h RPDL device specific definitions tinclude r pdl_definitions h void func void uintl6 t StatusValue Read the status of channel 0 R_SPI_GetStatus 0 amp StatusValue PDL NO PTR y R20
445. nsmit Done uint8_t data5 Data receive buffer void func2 Callback function Receive Done void func3 Callback function Error Perform an SPI transfer This may be sending receiving or both sending and receiving data data1 Select channel SCIn where n 0 to 12 data2 Control options The default options are shown in bold Specify PDL_NO_DATA to use the defaults e DMAC DTC trigger control PDL_SCI_SPI_TX_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of PDL_SCI_SPI_TX_DMAC_TRIGGER_ENABLE or the DMAC or DTC when a PDL_SCI_SPI_TX_DTC_TRIGGER_ENABLE data byte is transmitted e DMAC DTC trigger control PDL_SCI_SPI_RX_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of PDL_SCI_SPI_RX_DMAC_TRIGGER_ENABLE or the DMAC or DTC when a PDL_SCI_SPI_RX DTC TRIGGER ENABLE data byte is received data3 The number of bytes that must be transferred either transmitted received or both before the function completes or the callback function is called If the DMAC or DTC shall be used to handle the received data specify PDL_NO_DATA data4 The start address of the storage area for the expected data Specify PDL_NO_PTR if not transmitting data or if no data shall be processed by this function e g if the DMAC or DTC shall be used to process the received data func1 Transmit callback Specify PDL_NO_FUNC or a callback function name depending on the r
446. nt func The function to be called when a maskable interrupt request from comparator A except ELC is used Specify PDL_NO_FUNC if PDL_CPA_NONMASKABLE_INTERRUPT ELC Event Generation Condition Selection or monitor only operation are selected data3 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid and exclusive otherwise false Comparator A R20UTO708EE0211 Rev 2 11 Aug 01 2014 Page 4 288 2tENESAS RX210 Group 4 Library Reference Reference R_CGC_Set R_LVD_Create R_LVD_Control and R_CPA_GetStatus Remarks Do not use VDET1 and Comparator A channel 0 VDET2 and comparator A channel 1 at Program example R20UTO0708EE0211 Rev 2 11 Aug 01 2014 same time because they share same registers See R_LVD_Create and R_LVD_Control Function R_CGC_Set must be called with the current clock source selected before using this function If using the digital filter the LOCO clock must be enabled see R_CGC_Set Disable the digital filter circuit when using Comparator A interrupt to return from software standby mode or deep software standby mode Use R_CPA_GetStatus to determine the interrupt cause Do not use Comparator Ain deep software standby mode with PDL_LPC_DEEPCUT_ENABLE Do not select PDL_CPA_MODE_RESET_ENAB
447. nternal reference voltage Scan mode PDL_ADC_12_SCAN_SINGLE or PDL_ADC_12_SCAN CONTINUOUS or PDL_ADC_12 SCAN GROUP Select single scan continuous scan or group scan mode Trigger sources enable Not valid if PDL_ADC_12 INPUT_TS or PDL_ADC_12 SCAN GROUPis selected for data2 PDL_ADC_12_ASYNC_TRIGGER_ENABLE or PDL_ADC_12_SYNC_TRIGGER_ENABLE Enable the ADC to be started by asynchronous or synchronous trigger sources If neither option is selected only software will be used as the trigger source e Value addition control Not valid if PDL_ADC_12_INPUT_TS is selected for data2 PDL_ADC_12_VALUE_ADDITION_0 or PDL_ADC_12_VALUE_ADDITION_1 or PDL_ADC_12 VALUE ADDITION 2 or PDL_ADC 12 VALUE ADDITION 3 Set the conversion to be 1 time 2 time addition once 3 time addition twice or 4 time addition three times Data alignment PDL_ADC_12_DATA_ALIGNMENT_RIGHT or PDL_ADC_12_DATA_ALIGNMENT_LEFT The alignment of the 12 bit ADC conversion result within the 16 bit register Ignored for channels using value addition mode the 14 bit result is always left alignea R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS Page 4 272 RX210 Group 4 Library Reference Description 2 4 Self diagnostic control PDL_ADC_12_SELF_DIAGNOSTIC_DISABLE or PDL_ADC_12 SELF_DIAGNOSTIC_VREFHO_ZERO or PDL ADC 12 SELF DIAGNOSTIC
448. ntrol ADC triggers Valid for n 4 in complementary PWM mode unless stated otherwise PDL_MTU2_ADC_TRIG_A_DOWN_DISABLE or PDL_MTU2_ADC_TRIG_A_DOWN_ENABLE Disable or enable ADC trigger TRGnAN requests during down count operation PDL_MTU2_ADC_TRIG_B_DOWN_DISABLE or PDL_MTU2_ADC_TRIG_B_DOWN_ENABLE Disable or enable ADC trigger TRGnBN requests during down count operation PDL_MTU2_ADC_TRIG_A UP_DISABLE or PDL_MTU2_ADC_TRIG_A UP_ENABLE Disable or enable ADC trigger TRGnAN requests during up count operation This option can be selected in other modes PDL_MTU2_ADC_TRIG_B_UP_DISABLE or PDL_MTU2_ADC_TRIG_B_UP_ENABLE Disable or enable ADC trigger TRGnBN requests during up count operation This option can be selected in other modes 2tENESAS Page 4 127 RX210 Group 4 Library Reference Description 4 9 buffer_operation Configure the buffer operation If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Control the cycle set buffer transfer timing Valid for n 4 PDL_MTU2_CSB_DISABLE or Select no transfer PDL_MTU2_CSB_CREST or transfer on crest detection PDL_MTU2_CSB_TROUGH or transfer on trough detection or PDL_MTU2_CSB_ BOTH transfer on crest and trough detection PDL_MTU2_CSB_TROUGH and PDL_MTU2_CSB_BOTH are available o
449. o read data from this slave DMAC or DTC The function to be called when a Stop or error condition is detected data5 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid exclusive and achievable otherwise false C R_IIC_Create R_IIC_GetStatus R_IIC_SlaveSend R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 249 RENESAS RX210 Group 4 Library Reference Remarks e Ifa callback function is specified interrupts are used Use R_IIC_GetStatus in the callback function to identify the activity that has occurred Please see the notes on callback function usage in 6 e If no callback function is specified this function will read the status flags to monitor the bus activity Use R_IIC_GetStatus to identify the activity that has occurred If the 12C channel s control registers are directly modified by the user this function may lock up e If the master sends more data than is expected and the DMAC DTC trigger is disabled this function will issue a NACK to the master When a Stop condition is detected if the DMAC or DTC is used for transferring data use R_DMAC_Control or R_DTC_Control to re set the address and count before the next transfer begins e False will be returned if the DMAC channel has not been allocated using R_DMAC_Create Program example
450. ock is used as RTC count source and HOCO is set as system clock include lt stdio h gt include lt string h gt PDL functions include r pdl_cgc h include r pdl lpc h include r pdl cmt h include r pdl mcu h include r pdl _rtc h include r pal sci h PDL device specific definitions include r pdl definitions h define RSK_SCI CHANNEL 0 static void SetClocks void static void Alarm handler void volatile bool bEnterSleepMode false void main void uint8 t flags uint32 t time uint32 t time previous 0 uint32 t date uint8 t buffer 50 uintl6 t status 0 Sets system clock SetClocks Create async for debug output R_SCI Set RSK_SCI_CHANNEL PDL SCI PIN SCIO RXDO P21 PDL SCI PIN SCIO TXDO P20 7 R SCI Create RSK SCI CHANNEL PDL SCI _ASYNC 9600 10 PDL_SCI_8N1 Check warm cold start flag CWSF 1 call R_RTC_CreateWarm to start up the RTC if warm cold start flag is detected power ON from warm start Get Reset Status Flag R_MCU_GetStatus PDL_NO PTR amp status PDL_NO PTR PDL NO PTR RSTSR1 CWSF Warm start RTC is running status amp BIT 8 uintl6 t BIT 8 amp amp RTC RCR2 BIT START 0 R20UT0708EE0211 Rev 2 11 Page 5 42 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples If warm start is detected and RTC is running then warm start
451. ode r n 0 PDL NO FUNC while 1 after the complete initialization Set the warm start indicator R_MCU_Control PDL MCU WARM START y Find out what caused the exit from deep software standby NOTE THE El USES IRQO DS AND IRO1 DS PINS AND THEREFORE THESE BITS WILL BE SET IN status flags IF USING THE El R_LPC GetStatus status flags de if true bDeepStdbyExit this is us exiting from deep sleep An interrupt has caused an exit from deep software standby mode followed by an internal reset if 0 status flags BIT 23 Flag should have been set while 1 It is correct to be here if have just woken from deep software standby while 1 Read time R_RTC_Read PDL_RTC_ READ CURRENT amp flags amp time amp date sprintf char buffer Time Sd d d Sd d d r n int time amp OxF00000 gt gt 20 int time amp 0x0F0000 gt gt 16 int time amp 0Ox00F000 gt gt 12 int time amp 0x000F00 gt gt int time amp 0x0000F0 gt gt int time amp 0x00000F gt gt R_SCI Send RSK_SCI CHANNEL PDL NO DATA buffer 0 PDL NO FUNC This call should cancel the settings made in above call to R_LPC Create Allow RTC interval interrupt signal wake us up from deep software standby R_LPC Create PDL LPC_HIGH SPEED MODE PDL_LPC_IO DELAY PDL _LPC_EXT BUS HI Z
452. ogical operation selection uint16_t data3 Modification value Modifying the operation of an I O port or I O port pin data1 Use either one of the following definition values from 4 2 3 One port definition or One port pin definition data2 Select the register to be modified and the logical operation using to separate the selections The control register to be modified PDL_IO_PORT_DIRECTION or Data direction PDL_IO_PORT_MODE or General or Peripheral I O mode control Open drain control PPEIC PORT Vr Eo See hardware manual for ports that this is available on PDL_IO_PORT_PULL_UP or Pull up control Drive capacity control POE IC_PORT DRIVE See hardware manual for ports that this is available on The logical operation to be applied to the control register PDL_IO_PORT_AND or PDL_IO_PORT_OR or Select between AND amp OR or Exclusive OR PDL_IO_PORT_XOR data3 The value to be used for the modification using one of the formats below Pin not PE1 open drain control b15 b1 bO Do not care 0or1 Pin PE1 open drain control b15 b2 b1 b0 Do not care 0to3 Port not open drain control b15 b8 b7 b0 Do not care Register Port open drain control b15 b8 b7 b0 Register ODR1 Register ODRO True if all parameters are valid and exclusive otherwise false I O port None
453. om the slave S Start condition P Stop condition Sr Repeated Start condition R Read SDA released high W Write SDA held low Figure 5 39 IPC bus activity notation 5 18 1 Master mode In this example an EEPROM device has been connected to channel 0 The EEPROM responds to the 7 bit slave address 1010xxxb During a read process the bits xxx can be any value During a write process i The bits xxx represent the EEPROM memory address bits a10 a9 and a8 ii The first byte after the slave address is the EEPROM memory address bits a7 to a0 The EEPROM has a write cycle time of 5 ms The following examples illustrate the use of Master mode R20UT0708EE0211 Rev 2 11 Page 5 74 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 1 Configuration and transmission The MCU s I C channel 1 will be configured for Master operation and used to send three bytes to a slave AA AAA A A AE Figure 5 40 The bus activity showing 4 bytes being transmitted to the EEPROM Peripheral driver function prototypes include r pdl iic h include r pdl cgc h include r pdl intc h include r pdl cmt h RPDL device specific definitions include r pdl definitions h define EEPROM ADDRESS 0xA0 uint8 t data storage 10 void main void const uint8 t eeprom data array 1 5 0x00 0x01 0x02 0x03 0x04 uint32 t status flags 0 uintl6 t TxChars
454. on R20UT0708EE0211 Rev 2 11 Page 2 11 Aug 01 2014 RENESAS RX210 Group 2 Driver 2 12 Bus Controller Driver The driver functions support the control of the external bus providing the following operations 1 Setting the internal bus operation 2 Configuration of the controller 3 Configuration of the four external address space areas 4 Disabling an area that is not required 5 Controlling the bus controller 6 Reading the status of the controller R20UT0708EE0211 Rev 2 11 Page 2 12 Aug 01 2014 2tENESAS RX210 Group 2 Driver 2 13 DMA Controller Driver The driver functions support the control of the Direct Memory Access DMA controller providing the following operations 1 Configuration for use including e Access to all control bits e Automatic interrupt control 2 Disabling DMA channels that are no longer required and enabling low power mode 3 Control of a channel 4 Reading the status and operation registers of a channel R20UT0708EE0211 Rev 2 11 Page 2 13 Aug 01 2014 RENESAS RX210 Group 2 Driver 2 14 Data Transfer Controller Driver The driver functions support the control of the Data Transfer Controller providing the following operations 1 Setting the central options 2 Configuration for use including support for chain transfers 3 Disabling the controller 4 Starting or stopping the controller 5 Reading the status flags and data transfer registers R20UT
455. on section for details RENESAS Page 4 13 RX210 Group 4 Library Reference Program example RPDL definitions include r pdl intc h RPDL device specific definitions tinclude r pdl definitions h void func void Select P30 for IRQO P31 for IRQland PE7 for IRQ7 R_INTC_SetExtInterrupt PDL INTC IRQO PORT 3 0 PDL INTC IRQ1 PORT 3 1 PDL INTC IRQ7 PORT E 7 y R20UT0708EE0211 Rev 2 11 Page 4 14 Aug 01 2014 RENESAS RX210 Group 2 R_INTC_CreateExtInterrupt Synopsis Prototype Description 1 2 R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference Configure an external interrupt signal bool R_INTC_CreateExtinterrupt uint8_t data1 uint32_t data2 void func uint8_t data3 II Signal selection II Configuration Callback function Interrupt priority level Sets the specified interrupt detection and control data1 Choose the interrupt signal to be configured PDL_INTC_IRQn n 0 to 7 or PDL_INTC_NMI IRQn n 0 to 7 interrupt pin or NMI data2 Choose the settings If multiple selections are required use to separate each selection The default settings are shown in bold e Digital filter selection PDL_INTC_FILTER_DISABLE or PDL_INTC_FILTER_DIV_1 or PDL_INTC_FILTER_DIV_8 or PDL_INTC_FILTER_DIV_32 or PDL_INTC FILTER DIV_64
456. on usage in 6 If no callback function is specified this function waits for the CMIB flag to indicate that the one shot time delay is complete If the timer s control registers are directly modified by the user this function may lock up A callback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed The timer period limits depend on the peripheral module clock PCLKB fecixe MHz Equation 12 5 12 8 1 Tmn ES 80ns 83 3ns 125ns FS rcuxr 9 Tmax_CHANNEL 167 7ms 174 8ms 262ms Jerks 92 Tmax_uNIT 42 9s 44 78 67 18 Srcuxs tinclude r pdl_tmr h RPDL device specific definitions tinclude r pdl_definitions h void func void Output a pulse and wait for 40ms R_TMR_CreateOneShot PDL_TMR_TMRO PDL_TMR_OUTPUT_HIGH 40E 3 PDL_NO_FUNC 0 y R20UT0708EE0211 Rev 2 11 Page 4 167 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 6 R_TMR_Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example Disable a TMR timer unit bool R_TMR_Destroy uint8_t data Unit selection Shut down a TMR timer unit data The timer unit n where n 0 or 1 Unit O comprises channels TMRO and TMR1 Unit 1 compr
457. ondition and finish with a Stop condition However ifusing DMAC or DTC the Stop condition will not be generated automatically so use the R_SCI_Control function to manually generate a stop Ifa callback function is specified and the interrupt priority level is zero this function will return false e The SCI IIC module is always configured to use Reception and Transmission interrupts IICINTM bit 1 rather than ACK NACK interrupts This means that if using the DMAC or DTC to transmit then all data will be transmitted even if the slave device fails to ACK PDL functions tinclude r pdl_sci h RPDL device specific definitions tinclude r_pdl definitions h define CHANNEL SCI_IIC 9 define SLAVE ADDRESS OxA0 Buffer for IIC data uint8 t IIC Buffer 10 void func void Wait while send 10 bytes R_SCI_IIC Write CHANNEL SCI_IIC PDL_NO_DATA SLAVE_ADDRESS 10 IIC Buffer PDL_NO_FUNC Page 4 229 RENESAS RX210 Group 4 Library Reference 8 R_SCI_IIC_Read Synopsis Prototype Description 1 2 R20UT0708EE0211 Rev 2 11 Aug 01 2014 Perform an IIC master read on an SCI channel bool R_SCI_IIC_Read uint8_tdata1 Channel selection uint16_tdata2 Channel configuration uint16_t data3 Slave Address uint16_t data4 Number of bytes to transfer uint8_t data5 Buffer void func 1 Callback funct
458. onfiguration uint32_t data3 Bit rate or register value uint8_t data4 Interrupt priority level Set up the selected SCI channel data1 Select channel SCIn where n 0 to 12 data2 Configure the channel If multiple selections are required use to separate each selection The default settings are shown in bold Operation mode PDL_SCI_ASYNC or PDL_SCI_SYNC or PDL_SCI_SMART or PDL_SCI_ASYNC_MP Choose between Asynchronous Clock synchronous includes SPI and IIC Smart Card Interface or Multi Processor Asynchronous operation e Transmit Receive connections Not applicable in IIC Mode option will be ignored PDL_SCI_TX_CONNECTED or PDL_SCI_TX_DISCONNECTED The TXDn output is required not required PDL_SCI_RX_CONNECTED or PDL_SCI_RX_DISCONNECTED The RXDn input is required not required Data transfer format Not applicable in IIC Mode option will be ignored PDL_SCI_LSB_FIRST or PDL_SCI_MSB FIRST Select least or most significant bit first Options which are available in Asynchronous mode or Multi Processor Asynchronous mode e Noise Filter PDL_SCI_RX_FILTER_DISABLE or PDL_SCI_RX FILTER ENABLE Enable or disable the Digital Noise Filter on the RXDn pin Hardware Flow Control PDL_SCI_HW_FLOW_NONE or PDL_SCI_HW_FLOW_CTS or PDL_SCI_HW_FLOW_RTS Select the Hardware Flow Control Option Note CTS and RTS functi
459. ons cannot both be used as they share the same pin Data clock source selection PDL_SCI_CLK_INT_IO or Select the on chip SCKhn pin available as an I O pin PDL_SCI_CLK_INT_OUT or baud rate generator SCKn pin SCI bit clock output PDL_SCI_CLK_EXT or Input a clock of 8 or 16 times the desired bit rate to the SCKn pin See parameter data3 for the multiplier selection PDL_SCI_CLK_TMR For SCI5 select Timer output TMOO TMO1 For SCI6 select Timer output TMO2 TMOS For SCI12 select Timer output TMOO TMO1 The SCKn pin is set to high impedance e Data length PDL_SCI_8_BIT_LENGTH or PDL_SCI_7_BIT_LENGTH 8 or 7 bit data length RENESAS Page 4 213 RX210 Group Description 2 4 e Parity mode 4 Library Reference PDL_SCI_PARITY_NONE or PDL_SCI_PARITY_EVEN or PDL_SCI_PARITY_ODD No parity bit even parity bit or odd parity bit Note Do not set parity bit for Multi Processor Asynchronous mode e Stop bit length PDL_SCI_STOP_1 or PDL_SCI_STOP 2 One or two stop bits The option PDL_SCI_8N1 can be used to select 8 bit data length no parity and one stop bit Options which are available in all Clock Synchronous modes including IIC and SPI SPI mode selection PDL_SCI_SPI_MODE SPI Mode selected Use the R_SCI_SPI_Transfer function not R_SCI_Send or R_SCI_Receive IIC mode selection
460. ontrol PDL_IIC_NF_DISABLE or PDL_IIC_NF_1 or PDL_IIC_NF_2 or Select the number of stages in the noise filter PDL_IIC_NF_3 or PDL_IIC_NF_4 data3 Detection settings Specify PDL_NO_DATA to use the defaults NACK Transmission Arbitration Lost Detection control PDL_IIC_NTALD_DISABLE or Disable or enable arbitration to be lost when an ACK is PDL_IIC_NTALD_ENABLE detection during transmission of a NACK in receive mode e Slave Arbitration Lost Detection control PDL_IIC_SALD_DISABLE or Disable or enable arbitration to be lost when a mismatch PDL_IIC_SALD_ENABLE occurs during slave data transmission e Slave address detection control PDL_IIC_SLAVE_0_DISABLE or Disable or enable detection of slave address 0 in PDL_IIC_SLAVE_0 _ENABLE_7 or 7 bit or PDL_IIC_ SLAVE O ENABLE 10 10 bit format PDL_IIC_ SLAVE _1_DISABLE or Disable or enable detection of slave address 1 in PDL_IIC_SLAVE_1_ENABLE_7 or 7 bit or PDL_IIC_SLAVE 1 ENABLE 10 10 bit format PDL_IIC_SLAVE_2 DISABLE or Disable or enable detection of slave address 2 in PDL_IIC_SLAVE_2 ENABLE 7 or 7 bit or PDL_IIC_SLAVE_2 ENABLE 10 10 bit format PDL_IIC_SLAVE_GCA_DISABLE or Disable or enable detection of the General Call PDL_IIC_SLAVE_GCA_ENABLE address e Device ID detection control PDL_IIC_DEVICE_ID_DISABLE or Disable or enable detection of the Device ID PDL_IIC_DEVICE_ID_ ENABLE address 1111 100b
461. ools Test Window Help osaejejs ajo a JAR R om eos 22 ae a rain Pe eD rpdl_lib_test rpdl_lib_test H E C source file 4 dbsct c Interrupt_4DC_12 c Interrupt_BSC c Interrupt_CAC c Interrupt_CMT c Interrupt_CP4_LYD c Interrupt_CPB c Interrupt_DMAC c Interrupt_DOC c Interrupt_ELC c Interrupt_IIC c Interrupt_INTC c Interrupt MTU2 c Interrupt_not_RPDL c Interrupt_POE c Interrupt_RATC c Interrupt_SCl c Interrupt_SPl c Interrupt_TMR c IDU TPU c I pdl configuration resetprg c 2 rpdl_lib_test c ES ES Es ES in gE E JEE H E Download modules 5 Dependencies Ger Ten Ja Ready EE Ee EN E Defaults 7 Figure 1 3 intprg c and vecttbl c have been excluded R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS 1 Introduction Page 1 10 RX210 Group 1 Introduction 9 Set the build options Use the key sequence Alt B R to open the RX Standard Toolchain window In this section only options which you must change from the default settings are described If you add RPDL in existing project see also 1 2 Compiler options when you use this product a Set the optimisation To avoid linking unused RPDL functions adjust the Compiler and Linker settings i Compiler Select the C C tab Use the key sequence Alt Y O O to show the optimisation options Ensure that the Inter module optimization option is enabled RX Standard Toolchain Configuration C C
462. or PDL INTC IRQ5 PORT 1 5or PDL INTC IRQ5 PORT D_5or PDL INTC IRQ5 PORT E 5 PDL INTC IRQ6 PORT A 3or PDL INTC IRQ6 PORT 1 6or PDL INTC IRQ6 PORT D 6or PDL_ INTC _IRQ6_ PORT E 6 PDL_INTC_IRQ7 PORT E 2or PDL_INTC_IRQ7_PORT_1_7 or PDL_INTC_IRQ7_PORT_D_7 or PDL_INTC_IRQ7_PORT_E 7 Select the pins to be used for signals IRQO to IRQ7 Return value Category References Remarks R20UT0708EE0211 Rev 2 11 Aug 01 2014 Interrupt control R_INTC_CreateExtInterrupt True if all parameters are valid and exclusive otherwise false Before calling R_INTC_CreateExtInterrupt call this function to select the required pins The Multifunction Pin Control registers are modified to enable each selected IRQ pin and the 1 0 Port PMR and PDR registers are modified to set the pin as an input A pin can be used both as an interrupt input and a peripheral or general purpose input or output apart from an analog input If the dual operation is required call this function before configuring the peripheral or I O port operation Some pin options are not available on smaller device packages Some IRQ pins labelled in the hardware manual with the suffix DS can also be used to exit from Deep Software Standby mode Please refer to the Low Power Consumpti
463. or PDL_DTC_TRIGGER_TPU_TGI2B or Input capture compare match signals on TPU channel 2 PDL_DTC_TRIGGER_TPU_TGI3A or PDL_DTC_TRIGGER_TPU_TGI3B or PDL_DTC_TRIGGER_TPU_TGI8C or PDL_DTC TRIGGER TPU TGI3D or Input capture compare match signals on TPU channel 3 PDL_DTC_TRIGGER_TPU_TGI4A or PDL_DTC_TRIGGER_TPU_TGI4B or Input capture compare match signals on TPU channel 4 PDL_DTC TRIGGER TPU TGI5A or PDL_DTC TRIGGER TPU_TGI5B or Input capture compare match signals on TPU channel 5 PDL_DTC_TRIGGER_CMIAO or PDL_DTC_TRIGGER_CMIA1 or PDL_DTC_TRIGGER_CMIA2 or PDL_DTC TRIGGER _CMIA3 or Compare match Aon TMR channel n n 0 to 3 PDL_DTC TRIGGER _CMIBO or PDL_DTC_TRIGGER_CMIB1 or PDL_DTC_TRIGGER_CMIB2 or PDL_DTC_TRIGGER_CMIB3 or Compare match B on TMR channel n n 0 to 3 PDL_DTC_TRIGGER_DMACIO or PDL_DTC_TRIGGER_DMACI1 or PDL_DTC_TRIGGER_DMACI2 or PDL_DTC_TRIGGER_DMACI3 or Transfer complete on DMAC channel n n 0 to 3 2tENESAS Page 4 103 RX210 Group 4 Library Reference Description 3 3 PDL_DTC_TRIGGER_RXIO or Return value Category Reference Remarks R20UT0708EE0211 Rev 2 11 Aug 01 2014 PDL_DTC_TRIGGER_RXI1 or PDL_DTC_TRIGGER_RXI2 or PDL_DTC_TRIGGER_RXIS
464. or PDL_DTC_TRIGGER_RXI4 or PDL_DTC_TRIGGER_RXI5 or PDL_DTC_TRIGGER_RXI6 or PDL_DTC_TRIGGER_RXI7 or PDL_DTC_TRIGGER_RXI8 or PDL_DTC_TRIGGER_RXI9 or PDL_DTC_TRIGGER_RXI10 or PDL_DTC_TRIGGER_RXI12 or PDL_DTC_TRIGGER_RXI11 or PDL_DTC_TRIGGER_TXIO or PDL_DTC_TRIGGER_TXI 1 or PDL_DTC_TRIGGER_TXI 2 or PDL_DTC_TRIGGER_TXI3 or PDL_DTC_TRIGGER_TXI4 or PDL_DTC_TRIGGER_TXI5 or PDL_DTC_TRIGGER_TXI6 or PDL_DTC_TRIGGER_TXI7 or PDL_DTC_TRIGGER_TXI8 or PDL_DTC_TRIGGER_TXI9 or PDL_DTC TRIGGER _TXI10 or PDL_DTC TRIGGER TXI11 or PDL_DTC TRIGGER _TXI12 or PDL_DTC_TRIGGER_IICO_RX or Receive buffer full on C channel 0 PDL_DTC_TRIGGER_IICO_TX Transmit buffer empty on I C channel 0 Receive buffer full on SCI channel n n O to 12 Transmit buffer empty on SCI channel n n O to 12 data2 The start address of the transfer data area It must be a multiple of 4 For short address mode 12 bytes are required to store the transfer data For full address mode 16 bytes are required data3 The source start address The valid range depends on the address mode short or full data4 The destination start address The valid range depends on the address mode short or full data5 The number of transfers to take place For normal or block mode valid between 0 and 65535 0 65536 transfers
465. or MTIOC3D 2tENESAS Page 4 122 RX210 Group 4 Library Reference Description 2 2 Valid when n 4 Return value Category Reference Remarks PDL_MTU2_PIN_4A_P24 or PDL_MTU2_PIN_4A_P82 or PDL_MTU2_PIN_4A_PAO or Select the P24 P82 PAO PB3 or PE2 pin for MTIOC4A PDL_MTU2_PIN_4A_PB3 or PDL_MTU2 PIN 4A PE2 PDL_MTU2_PIN_4B_P30 or PDL_MTU2_PIN_4B_P54 or PDL_MTU2_PIN_4B_PC2 or Select the P30 P54 PC2 PD1 or PE3 pin for MTIOC4B PDL_MTU2_PIN 4B PD1 or PDL_MTU2 PIN 4B PE3 PDL_MTU2_PIN_4C_P25 or PDL_MTU2_PIN_4C_P83 or PDL_MTU2_PIN_4C_PB1 or Select the P25 P83 PB1 PE1 or PE5 pin for MTIOC4C PDL_MTU2_PIN_4C_PE1 or PDL_MTU2_ PIN 4C_PE5 PDL_MTU2_PIN 4D P31or PDL_MTU2_PIN_4D_P55 or PDL_MTU2_PIN_4D_PC3 or PDL_MTU2_PIN_4D_PD2 or PDL_MTU2 PIN 4D PE4 Select the P31 P55 PC3 PD2 or PE4 pin for MTIOC4D e Valid when n 5 PDL_MTU2_PIN_5U_PA4 or PDL MTU2 PIN 5U PD7 PDL_MTU2_PIN_5V_PA6 or PDL_MTU2_PIN_5V_PD6 PDL_MTU2_PIN_5W_PBO or PDL_MTU2 PIN 5W_PD5 Select the PA4 or PD7 pin for MTIOC5U Select the PA6 or PD6 pin for MTIOC5V Select the PBO or PD5 pin for MTIOC5W e Valid when n 0 1 2 3 0r4 PDL_MTU2_PIN_CLKA_P14 or PDL_MTU2_PIN CLKA P24 or PDL_MTU2_PIN_CLKA_PA4 or PDL_MTU2_PIN_CLKA_PC6 PDL_MTU2_ PIN CLKB P15 or PDL_MTU2_PIN CLKB P25 or PDL_MTU2_PIN CLKB_ PA6 or PDL MTU2 PIN CLKB PC7 Se
466. or TIOCC valid for n 0 and 3 PDL_TPU_TIOCC_NF_DISABLE or PDL_TPU_TIOCC_NF ENABLE Disable or enable noise filter for TIOCC R20UT0708EE0211 Rev 2 11 Aug 01 2014 2tENESAS Page 4 305 RX210 Group 4 Library Reference Description 2 5 Noise Filter for TIOCD valid for n 0 and 3 R20UT0708EE0211 Rev 2 11 Aug 01 2014 PDL_TPU_TIOCD_NF_DISABLE or PDL_TPU_TIOCD NF ENABLE Disable or enable noise filter for TIOCD Noise filter clock select PDL_TPU_NF_CLK_PCLK_DIV_1 or PDL_TPU_NF_CLK_PCLK_DIV_8 or PDL_TPU_NF_CLK_PCLK_DIV_32 or PDL_TPU_NF_CLK_COUNTING The noise filter clock signal PCLK 1 8 32 or the same as the TPU counting clock DMAC and or DTC trigger control for TGRA PDL_TPU_TGRA_DMAC_DTC_TRIGGER_DISABLE or PDL_TPU_TGRA_DMAC_TRIGGER_ENABLE or PDL_TPU_TGRA_DTC_TRIGGER_ENABLE Disable or enable activation of the DMAC or DTC when a TGRA compare match occurs DTC trigger control for TGRB PDL_TPU_TGRB_DTC_TRIGGER_DISABLE or PDL_TPU_TGRB_DTC_TRIGGER_ENABLE Enable activation of the DTC when a TGRB compare match occurs DTC trigger control for TGRC valid for n 0 and 3 PDL_TPU_TGRC_DTC_TRIGGER_DISABLE or PDL_TPU_TGRC_DTC_TRIGGER_ENABLE Enable activation of the DTC when a TGRC compare match occurs DTC trigger control for TGRD valid for n 0 and 3
467. or Trigger from the ELC TGRA compare match input capture PDL_ADC_12_GP_TRIGGER_TPU_TRGAN1 or from TPUO to TPU4 TGRA compare match input capture from TPUO PDL_ADC_12_GP_TRIGGER_MTU_TRGOBN or PDL_ADC_12_GP_TRIGGER_MTU_TRGAN or PDL_ADC_12_GP_TRIGGER_MTU_TRG4ABN or PDL_ADC_12_GP_TRIGGER_TPU_TRG4ABN1 DTC DMAC trigger control PDL_ADC_12_GP_DMAC_DTC_TRIGGER_DISABLE or PDL_ADC_12_GP_DMAC_TRIGGER_ENABLE or PDL_ADC_12_GP_DTC_TRIGGER_ENABLE Disable or enable activation of the DMAC or DTC data5 The data to be used for the sampling state register value calculations for self diagnosis temperature sensor or internal reference voltage depending on the input source parameter of data2 If PDL_ADC_12_ADSSTR_SPECIFY is selected for parameter data2 the value should not be less than 12 or more then 255 Data use Parameter type The timer period in seconds or double The value to be put in register ADSSTR uint8_t data6 The data to be used for the sample and hold circuit control register value calculations If PDL_ADC_12_ADSHCR_SPECIFY is selected for data2 the value should not be less than 4 or more then 255 Data use Parameter type The timer period in seconds or double The value to be put in register ADSHCR uint8_t data7 The data to be used for the disconnecting detection control register value calculations If PDL_ADC_12_ADDISCR_SPECIFY is selected for data2 the value s
468. ormat b7 b6 b5 b4 b3 b2 b1 bO TMR2 TMR3 0 Compare Compare 0 Compare Compare idad match B match A Overow match B match A data3 Where the counter value shall be stored Specify PDL_NO_PTR if it is not required data4 Where the compare match A value shall be stored Specify PDL_NO_PTR if it is not required data5 Where the compare match B value shall be stored Specify PDL_NO_PTR if it is not required True Timer TMR R_TMR_CreateUnit Ifthe status flags are read any flag that has been set to 1 shall be automatically cleared to 0 by this function Page 4 176 RENESAS RX210 Group 4 Library Reference Program example RPDL definitions include r pdl_tmr h RPDL device specific definitions include r pdl definitions h uint8 t Flags uint16 t Counter uint16 t CompareMatchA uint16 t CompareMatchB void func void Read the status flags and registers for TMR unit 0 R_TMR_ReadUnit 0 amp Flags amp Counter CompareMatchA amp CompareMatchB R20UT0708EE0211 Rev 2 11 Page 4 177 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 4 2 17 Compare Match Timer 1 R_CMT_Create Synopsis Prototype Description Return value Category Reference Configure a CMT channel bool R_CMT_Create uint8_t data1 Timer channel selection uint16_t data2 Configuration sele
469. ort pin to be used for signal CSO PDL_BSC_CS1_P25 or PDL_BSC_CS1 PC6 Select the port pin to be used for signal CS1 PDL_BSC_CS2 P26 or PDL_BSC_CS2 PC5 Select the port pin to be used for signal CS2 PDL_BSC_CS3_P27 or PDL_BSC_CS3_PC4 Select the port pin to be used for signal CS3 WAIT pin selection only re uired if the WAIT signal is to be used PDL_BSC_WAIT_P51or PDL_BSC_WAIT_P55 or PDL_BSC_WAIT_PC5 Select the port pin to be used for signal WAIT ALE signal control only required if the ALE signal is to be used PDL BSC ALE ENABLE Enable the ALE signal on pin P54 d ata2 Address output control The signals are enabled by default unless the pin is allocated to a bus control signal If multiple selections are required use to separate each selection Specify PDL_NO_DATA for no change Ignored for packages with less than 100 pins specify PDL_NO_DATA PDL_BSC _A7 AO DISABLE Disable the output of the A7 to AO signals PDL_BSC_A8 DISABLE Disable the output of the A8 signal PDL_BSC_A9 DISABLE Disable the output of the A9 signal PDL_BSC_A10_DISABLE Disable the output of the A10 signal PDL_BSC_A11_DISABLE Disable the output of the A11 signal PDL_BSC_A12_DISABLE Disable the output of the A12 signal PDL_BSC_A13_ DISABLE Disable the output of the A13 signal PDL_BSC A
470. ory Reference Read CMT channel status and registers bool R_CMT_Read uint8_t data1 Channel selection uint8_t data2 A pointer to the data storage location uint16_t data3 A pointer to the data storage location Read and store the counter value and status flag data1 The channel number n where n 0 1 2 or 3 data2 The compare match status flag shall be stored in the following format Specify PDL_NO_PTR if the flag is not to be read b7 b1 bO 0 0 Idle 1 Compare match condition detected data3 A pointer to where the counter value shall be stored Specify PDL_NO_PTR if it is not required True if all parameters are valid otherwise false Compare Match Timer R_CMT_Create Remarks Program example e lf the flag is read and is set to 1 it shall be automatically cleared to O by this function RPDL definitions tinclude r pdl_cmt h RPDL device specific definitions tinclude r pdl_definitions h uint8 t Flags uint16 t Counter void func void Read the channel 2 values R CMT Read amp Flags amp Counter R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 185 RENESAS RX210 Group 4 Library Reference 4 2 18 Real time Clock 1 R_RTC_Create Synopsis Prototype Description 1 4 Configure the Real time clock bool R_RTC_Create uint32_t data1 II
471. ous 8N1 38400 baud R_SCI_Create 0 PDL SCI _ASYNC PDL SCI_8N1 38400 1 y Configure SCI1 for asynchronous 8N1 register values supplied R_SCI_Create 1 PDL_SCI_ASYNC PDL SCI_8N1 BIT 31 PDL SCI PCLK DIV 1 PDL SCI CYCLE BIT 16 115200 amp OxOOFFFFOO 0x50 1 R20UT0708EE0211 Rev 2 11 Page 4 217 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 3 R_SCI_Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example Shut down a SCI channel bool R_SCI_Destroy uint8_t data Channel selection Stop data flow and shutdown the selected SCI channel data Select channel SCIn where n 0 to 12 True if all parameters are valid otherwise false SCI None e The SCI channel is put into the power down state RPDL definitions include r pdl_sci h RPDL device specific definitions tinclude r pdl_definitions h void func void Shutdown SCI channel 1 R_SCI Destroy 1 i R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 218 RENESAS RX210 Group 4 R_SCI_Send Synopsis Prototype Description 4 Library Reference Transmit data on a SCI channel bool R_SCI_Send uint8_t data1 uint16_t data2 uint8_t data3 uint16_t data4 void func
472. p 5 Usage Examples void NMI handler lpc void nop Figure 5 8 Example of Deep Software Standby Mode R20UT0708EE0211 Rev 2 11 Page 5 14 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 7 Bus Controller Figure 5 9 shows an example of external bus controller usage Peripheral driver function prototypes include r pdl bsc h include r pdl_cgc h include r pdl intc h RPDL device specific definitions include r pdl definitions h Callback function prototype void BSC error handler void void main void volatile uint8 t cs0 location 8 volatile uint8 t csl location 8 volatile uintl6 t cs2 location 16 volatile uintl6 t cs3 location 16 Point to respective external memory areas cs3 location 16 uint16 t 0x05000000ul cs2 location 16 uint16 t 0x06000000ul csl location 8 uint8 t 0x07000000ul cs0 location 8 uint8 t 0xFFO00000u1 Enable the BCLK output R_CGC_Set L CEC CLE LOCO L CGC BCLK DIV 2 D D 25E3 25E3 PDL NO DATA 25E3 25E3 DL NO DAJ Set the CPU s Interrupt Priority Level to 0 R_INTC Write PDL INTC REG IPL 0 i Configure area 0 R_BSC_CreateArea 0 PDL BSC WIDTH 8 15 15 7 7 R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS Page 5 15 RX210 Group 5 Usage Examples Configure area 1 R_BSC_CreateArea
473. p the CPU when the one shot timer starts POL PU RE The CPU will re start when any valid interrupt occurs data3 The one shot time period in seconds func The function to be called when the one shot period ends Specify PDL_NO_FUNC for this function to wait for the timer to complete before returning You should always specify a function if PDL_TMR_CPU_OFF is selected to ensure that an interrupt will re start the CPU data4 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid and exclusive otherwise false Timer TMR R_CGC_Set R_TMR_CreateChannel R_TMR_CreateUnit R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 166 RENESAS RX210 Group 4 Library Reference Remarks Program example Function R_CGC_Set must be called with the current clock source selected before using this function This function is an alternative to R_TMR_CreateChannel and R_TMR_CreateUnit Please use R_TMR_Set to select the output TMOn pin as required This function will return false if a pin is enabled but is not set properly This function stops the timer on completion so no other TMR function calls are required If a callback function is specified this function will enable the relevant interrupt Please see the notes on callback functi
474. pi h PDL device specific definitions include r pdl definitions h define MASTER CHANNEL 0 void main void const uint32 t master tx data 4 0x000000A4 8 bit data 0x00000132 9 bit data Ox00007F34 15 bit data 0x00345678 24 bit data fae uint32 t master rx data 4 R20UT0708EE0211 Rev 2 11 Page 5 91 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 0x00000000 0x00000000 0x00000000 0x00000000 y Configure the clocks Configure main clock operation using an external 20 0 MHz clock ICLK 20 MHz PCLKD 20 MHz PCLKB 20 MHz FCLK 20 MHz BCLK not used BCIK pin not used R CGC Set PDL_CGC_CLK_MAIN PDL CGC_BCLK DISABLE PDL CGC MAIN RESONATOR PDL CGC NOT SUB 20E6 20E6 20E6 20E6 20E6 PDL NO _ DAT PDL NO DAT i Configure PLL operation The PLL will be set to 50 MHz ICLK 25 MHz PCLKD 25 MHz PCLKB 25 MHz FCLK 25 MHz BCLK 25 MHz BCLK pin 12 5 MHz R CGC Set PDL CGC CLK PLL PDL CGC BCLK DIV 2 50E6 25E6 25E6 25E6 25E6 25E6 PDL NO DATA Allow 100us for the main clock to stabilise R_CMT_CreateOneShot 0 PDL NO DATA 100E 6 PDL_NO_FUNC 0 de Select the PLL as the clock source R_CGC_Control PDL_CGC_CLK_PLL PDL NO DATA PDL NO DATA de Configure the I O port master SPI channel
475. pin P32 is specified for both RTCOUT and RTCIC2at the same timethis function will return false Select PDL_NO_DATA if no pins are required To set multiple options at the same time use to separate each value e RTCOUT Pin PDL_RTC_PIN_RTCOUT_P16 or If using the RTCOUT pin then select the port to use for PDL_RTC_PIN_RTCOUT_P32 it e Capture Pins PDL_RTC_PIN_RTCICO_P30 PDL_RTC_PIN_RTCIC1_P31 Specify any capture pins which will be used PDL_RTC_PIN_RTCIC2_P32 R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 186 2tENESAS RX210 Group 4 Library Reference Description 2 4 data3 The current day of the week DOW and time in hours minutes and seconds BCD format is used The format is dependent upon if using 12 hour or 24 hour mode 24 Hour Mode b31 b24 b23 b16 b15 b8 b7 b0 Day of week Hours Minutes Seconds Valid from 0 to 6 0 Sunday Specify OxFF for Valid from O Valid from O Valid from automatic calculation using the values in data3 to 23 to 59 O to 59 12 Hour Mode b31 b24 b23 b22 b16 b15 b8 b7 bO Day of week Valid from 0 to 6 0 Sunday eM mours MUMMIES q cones 0 AM Valid from Valid from Valid from Specify OxFF for automatic a A 1 PM 1 to 12 0 to 59 0 to 59 calculation using the values in data3 data4 The current year month a
476. pins Updated the POE usage example Updated the TMR usage example Updated SCI samples now the R_SCI_Set function includes a channel parameter Updated the IIC usage example Repeated Start sample Invalid Buffer Address Updated the IIC usage example obsolete CGC setting IIC master with DTC Updated sample to show how user must handle callback Updated revision history for revision 2 00 changes RENES Revision History 2 RX210 Group Revision History Description 13 Sept 2013 19 Dec 2013 R20UT0708EE0211 Rev 2 11 Aug 01 2014 Add the 1 2 Compiler options when you use this product Change 1 3 2 content into Using RPDL stand alone Add content Copy folder RPDL into the folder project workspace created Example X rpdl_lib_test Add content To use library with debug information enter RPDL RX210_library_debug as the File path Add content In this section only options which you must change from the default settings are described If you add RPDL in existing project see also 1 2 Compiler options when you use this product Add section 11 Using library with debug information Add Event Link Controller overview Remove section 15 Programmable Pulse Generator Add section 31 Timer Pulse Unit Add pictures for the 69 pins Add 5 Control of a unit API list Add new R_RTC_CreateWarm Rename R_TPU_Control to R_TPU_Contro
477. port the control of the internal clock generator providing the following operations 1 Configuration of the multiple clock outputs for system peripheral and external bus operation 2 Controlling the clock generator operation 3 Reading the Clock generator status flags Note Configuring the Clock Generation Circuit also provides information on clock frequencies that will be used by the integrated drivers for other peripherals R20UT0708EE0211 Rev 2 11 Page 2 3 Aug 01 2014 RENESAS RX210 Group 2 Driver 2 4 Interrupt Control Driver The driver functions support the use of the interrupt controller providing the following operations Selecting the applicable interrupt pins 2 Configuration an external interrupt signal for use 3 Enabling use of the software interrupt 4 Assigning an interrupt to be processed using the Fast Interrupt route 5 Assigning handlers for the fixed exception interrupts 6 Controlling an external interrupt input 7 Reading the status of an external interrupt 8 Reading an interrupt register 9 Writing to an interrupt register 10 Modifying an interrupt register R20UT0708EE0211 Rev 2 11 Page 2 4 Aug 01 2014 RENESAS RX210 Group 2 Driver 2 5 l1 OPort Driver The driver functions support the use of the I O port pins providing the following operations 1 Configuration for use 2 Reading the pin or port configuration 3 Modifying the pin or port configuration
478. position PDL_MCU_OFS_IWDT_WIN_START_25 or PDL_MCU_OFS_IWDT_WIN_START_50 or PDL_MCU_OFS_IWDT_WIN_START_75 or PDL_MCU_OFS_IWDT_WIN_START_100 The window start position specified as a percentage of the down counter 0 is when the down counter would underflow Selecting 100 is equivalent to no window start position Underflow action PDL_MCU_OFS_IWDT_NMI or PDL_MCU_OFS IWDT_RESET Select an NMI or reset when the IWDT down counter underflows Count stop mode PDL_MCU_OFS_IWDT_STOP_DISABLE or PDL_MCU_OFS_IWDT_STOP_ENABLE Enable or disable Count stop mode If the Count Stop mode is enabled the IWDT counter is stopped at a transition to sleep mode software standby mode deep software standby mode or all module clock stop mode RENESAS Page 4 53 RX210 Group Description 2 2 Category R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference data2 Select the post reset WDT configuration settings If multiple selections are required use to separate each selection Auto start control PDL_MCU_OFS_WDT_HALTED or PDL_MCU_OFS_WDT_AUTOSTART Disable or enable the WDT auto start mode If auto start mode is enabled select one setting from each of the following Timeout period PDL_MCU_OFS_WDT_TIMEOUT_1024 or PDL_MCU_OFS_WDT_TIMEOUT_4096 or PDL_MCU_OFS_WDT_TIMEOUT_8192 or PDL_MCU_OFS_WDT_TIMEOUT_1
479. pts This shows the setting of SCI channel 0 and the transmission and reception of data using interrupts Peripheral driver function prototypes include r pdl_sci h include r pdl_cgc h RPDL device specific definitions tinclude r pdl definitions h volatile bool data received volatile bool data sent void SCIrx void void SCItx void void main void volatile uint t rx_buffer 5 Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Initialise flags data_sent false data_received false Set pin options R SCI Set 0 PDL SCI PIN SCIO RXDO P21 PDL SCI PIN SCIO TXDO P20 Set up SCI channel 0 Async 8N1 38400 baud R_ SCI _ Create 0 PDL SCI ASYNC PDL SCI 8N1 38400 EN de Send message register callback to say when sent R_SCI_Send 0 PDL NO DATA r nHello Type 5 characters and I will echo them back r n 0 SCItx Y Wait for message to be sent while false data sent Start a pending read of 5 characters R_SCI Receive 0 PDL NO_ DATA rx_buffer 5 SCIrx PDL_NO_FUNC y Wait for characters to be received while false data received R20UT0708EE0211 Rev 2 11 Page 5 54 Aug 01 2014 RENESAS RX210 Group Echo the 5 characters back R_SCI_Send 0 PDL NO DATA rx buffer 5 PDL NO FUNC
480. py the string Renesas RX210 into the destination area when a falling edge occurs on pin IRQ1 P31 Channel 1 will copy the string Hello World into the destination area as soon as it is enabled PDL functions and definitions include r pdl_dmac h include r pdl cgc h include r pal inte h include r pal io port h RPDL device specific definitions include r pdl definitions h Required for this example include lt string h gt Callback function prototype void DMACO transfer end handler void Data source and destination declarations const char source string 1 Renesas RX210 const char source string 2 Hello World volatile uint8 t destination string 1 volatile uint8 t destination string 2 void main void uint8 t StatusValue uint32_t SourceAddr uint32_t DestAddr uintl6 t TransferCount uintl6 t SizeCount Set the CPU s Interrupt Priority Level to 0 R_INTC Write PDL INTC REG IPL 0 y Enable control of LED1 R_IO_PORT_Set PDL IO PORT 1 5 PDL IO PORT OUTPUT Switch on LEDI R_IO_PORT Write PDL IO PORT 1 5 0 Configure channel 0 R_DMAC Create 0 PDL _DMAC BLOCK PDL DMAC SOURCE ADDRESS PLUS PDL DMAC DESTINATION ADDRESS PLUS PDL DMAC SIZE 8 PDL _DMAC IRQ END PDL DMAC TRIGGER_IRO1 source string 1 destination string 1 1 uint16 t strlen source string 1
481. pyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration modification copy or otherwise misappropriation of Renesas Electronics product Renesas Electronics products are classified according to the following two quality grades Standard and High Quality The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots etc High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems and safety equipment etc Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life o
482. r Figure 5 36 Example of SCI in IIC mode R20UT0708EE0211 Rev 2 11 Page 5 68 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 17 10 SCI in IIC Mode using DMAC This shows the setting of SCI channel 9 in IIC mode and then a write to an IIC EEPROM using the DMAC PDL functions include r pdl sci h include r pdl cgc h include r pdl dmac h PDL device specific definitions tinclude r pdl definitions h static void Callback void SCI IIC Channel define CHANNEL SCI IIC 9 TIC Slave address of EEPROM define S AVE ADDRESS OxA0 Address in EEPROM where we will write a byte define EEPROM ADDRESS 0x01 volatile bool data_sent false void main v id Data Buffer volatile uint8 t IIC Buffer 10 Initialise the system clocks NOTE The code to initialise the system clock using R CGC Set is omitted here Set Channel 9 pin options R SCI Set 9 PDL SCI PIN SCI9 SSCL9 PB6 PDL SCI PIN SCI9 SSDA9 PB7 y Configure the SCI IIC Channel R_SCI_Create CHANNEL SCI_IIC PDL SCI_SYNC PDL SCI _IIC_MODE PDL SCI IIC DELAY SDA 20 21 9600 1 i Setup date to write to EEPROM Address in EEPROM IIC Buffer 0 EEPROM ADDRESS Data to store in EEPROM IIC Buffer 1 1 IIC Buffer 2 TIC Buffer 3 IIC Buffer 4 I
483. r all module clock stop mode R_MCU_OFS R_CGC_Set R_CGC_Control R_INTC_CreateExtInterrupt Return value True if all parameters are valid and exclusive otherwise false Category Independent Watchdog Timer Reference Remarks If using the Initial Setting Memory using R_MCU_OFS to enable the IWDT from reset this function will have no affect and can be omitted The IWDTCLK must be enabled using R_CGC_Set or R_CGC_Control If configuring to use a NMI handler then R_INTC_CreateExtInterrupt must be used to enable the NMI for IWDT The IWDT counter frequency must not be greater than the PCLB 4 Set the IWDTCLK division ratio accordingly This function will return false if this condition is detected R20UT0708EE0211 Rev 2 11 Aug 01 2014 2tENESAS Page 4 203 RX210 Group 4 Library Reference Program example RPDL definitions include r pdl_ iwdt h RPDL device specific definitions include r pdl definitions h void func void Configure the IWDT R_IWDT_ Set PDL_IWDT TIMEOUT 16384 PDL IWDT CLOCK OCO 256 y R20UTO708EEO211Rev211 C lt lt i lt RP Page 4 204 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 2 R_IWDT_Control Synopsis Prototype Description Return value Category Reference Remarks Control the Independent Watchdog op
484. r bodily injury artificial life support devices or systems surgical implantations etc or may cause serious property damages nuclear reactor control systems military equipment etc You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application for which it is not intended Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to gu
485. r every transfer e Trigger selection Name Trigger cause PDL_DTC_TRIGGER_CHAIN or Chain transfer PDL_DTC TRIGGER SW or By software PDL_DTC_TRIGGER_CMTO or PDL_DTC_TRIGGER_CMT1 or PDL_DTC_TRIGGER_CMT2 or Compare match on channel CMTn n 0 to 3 PDL_DTC TRIGGER_CMT3 or PDL_DTC_ TRIGGER _SPIO_RX or Receive buffer full on SPI channel 0 PDL_DTC_TRIGGER_SPIO_TX or Transmit buffer empty on SPI channel 0 PDL_DTC_TRIGGER_CMPBO or Interrupt request from Comparator BO PDL_DTC_TRIGGER_CMPB1 or Interrupt request from Comparator B1 RENESAS Page 4 102 RX210 Group 4 Library Reference Description 2 3 PDL_DTC_TRIGGER_IRQO or R20UT0708EE0211 Rev 2 11 Aug 01 2014 PDL_DTC_TRIGGER_IRQ1 or PDL_DTC_TRIGGER_IRQ2 or PDL_DTC_TRIGGER_IRQ3 or PDL_DTC_TRIGGER_IRQ4 or PDL_DTC_TRIGGER_IRQ5 or PDL_DTC TRIGGER _IRQG6 or PDL_DTC_TRIGGER_IRQ7 or Valid edge detected on pin IRQn n 0 to 7 PDL_DTC_TRIGGER_ADC12 or Conversion completed on the 12 bit ADC unit PDL_DTC_TRIGGER_ADC12_GBADI or Conversion completed on group B of the 12 bit ADC unit PDL_DTC_TRIGGER_ELSR18l or Event link interrupt PDL_DTC_TRIGGER_ELSR19l or Event link interrupt PDL_DTC TRIGGER _TGIAO or PDL_DTC_TRIGG
486. r of bytes has been received The function to be called when the number of received bytes reaches the threshold nterrupts number DMAC Either the function to be called when each byte is received or PDL_NO_FUNC if the callback function specified in R_DMAC_Create will be used DTC The function to be called at the interval specified in R_DTC_Create func2 The function to be called if a receive error occurs Specify PDL_NO_FUNC to ignore errors True if all parameters are valid and the operation completed false if a parameter was out of range Page 4 222 2tENESAS RX210 Group 4 Library Reference Category Reference SCI R_SCI_Control R_SCl_GetStatus Remarks R20UT0708EE0211 Rev 2 11 Aug 01 2014 The maximum number of characters to be received is 65535 Wait until a transmission on the same channel is complete before calling this function If callback function func is specified reception interrupts are used Please see the notes on callback function usage in 6 If polling mode is used the RXI flag will be used to manage the data reception If the SCI channel s control registers are directly modified by the user this function may lock up If no error callback function func2 is specified the error flags are cleared automatically to allow the reception process to complete Callback functions are executed by the interrupt processing function This means that no other interr
487. ral register C value shall be stored Specify PDL_NO_PTR if it is not required data7 Where the general register D value shall be stored Specify PDL_NO_PTR if it is not required True if all parameters are valid and exclusive otherwise false Timer Pulse Unit Ifthe flags are read any detection flag that has been set to 1 shall be automatically cleared to O by this function R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS Page 4 315 RX210 Group 4 Library Reference Program example RPDL definitions include r pdl_tpu h RPDL device specific definitions include r pdl definitions h uint8 t Flags uintl6 t General A uintl6 t General D void func void Read the status flags and registers A and D for channel TPUO R_TPU_Read 0 amp Flags PDL NO PTR amp General A PDL NO PTR PDL NO PTR amp General D R20UT0708EE0211 Rev 2 11 Page 4 316 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 Usage Examples This chapter shows programming examples for drivers in this library R20UT0708EE0211 Rev 2 11 Page 5 1 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples 5 1 Clock Generation Circuit Figure 5 1 shows an example of configuring the clock generation circuit After a power on reset both the PLL and the main clock oscillator which drives the PLL circuit are switched off The MCU is using the LOCO as the cloc
488. rameter is within range otherwise false Interrupt control None i i This function uses an interrupt routine to modify the IPL bits If the user has disabled interrupts cleared the bit in the PSW register in their own code this function will lock up For register select one of the registers listed in the tables starting on page 4 26 Write 1 to the SWINTR register to generate a software interrupt request RPDL definitions nclude r pdl intc h RPDL device specific definitions nclude r pdl definitions h void func void Set the IPL to 6 R_INTC Write PDL INTC REG IPL 6 i Set the IR for IRQO to 0 R_INTC Write PDL INTC REG IR ICU IROO 0 R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS ee RX210 Group 4 Library Reference 10 R_INTC_Modify Synopsis Modify an interrupt register Prototype bool R_INTC_Modify uint16_t data1 Register selection uint8_t data2 Logical operation uint8_t data3 1 Modification value Description Update the value in an interrupt register data1 e The register to be updated PDL_INTC_REG_IR_ register or Select the Interrupt Request register or PDL_INTC_REG_IER_ register or Interrupt Request Enable register or PDL_INTC_REG_IPR register Interrupt Priority register data2 The logical operation to be applied to the register
489. rate each selection Enable or disable the interrupt pin for the IRQ pins PDL_INTC_ENABLE or PDL_INTC_DISABLE Enable or disable the IRQn interrupt pin e Digital filter selection PDL_INTC_FILTER_DISABLE or PDL_INTC_FILTER_DIV_1 or PDL_INTC_FILTER_DIV_8 or PDL_INTC_FILTER_DIV_32 or PDL_INTC_FILTER_DIV_64 Disable the filter or select PCLKB divided by 1 8 32 or 64 e Detection sense selection for the IRQ pins PDL_INTC_LOW or Select Low level PDL_INTC_FALLING or Falling edge PDL_INTC_RISING or Rising edge or PDL_INTC_BOTH Falling and rising edge detection e Interrupt request clearing Clear the IRQ or NMI interrupt request flag This is not required if e A callback function has been specified e The interrupt priority level is higher than 0 PDL_INTC_CLEAR_IR_FLAG e The processor interrupt priority level is lower than the interrupt priority level This operation should not be applied when low level detection is used the function will return false PDL_INTC_CLEAR_OSD_FLAG Clear the Oscillation Stop detection NMI flag PDL_INTC_CLEAR_WDT_FLAG Clear the WDT event detection NMI flag PDL_INTC_CLEAR_IWDT_FLAG Clear the IWDT event detection NMI flag PDL_INTC_CLEAR LVD1_FLAG Clear the LVD1event detection NMI flag PDL_INTC_CLEAR _LVD2 FLAG Clear the LVD2 event detection NMI flag Return value True if all parame
490. re configuring any timer channel R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS een RX210 Group 2 Driver 2 19 Compare Match Timer Driver The driver functions support the use of the two 16 bit timers providing the following operations 1 Configuration for use including e Automatic clock setting using frequency or period as an input e Manual clock setting using register values as inputs e Automatic interrupt control 2 Configuration for use as a one shot timer 3 Disabling channels that are no longer required and enabling low power mode 4 Control of a timer including constant register updates change of frequency 5 Reading the counter value and status flag Note The Clock Generation Circuit must be configured before configuring any timer channel R20UT0708EE0211 Rev 2 11 Page 2 19 Aug 01 2014 2tENESAS RX210 Group 2 Driver 2 20 Real time Clock Driver The driver functions support the use of the real time clock providing the following operations 1 Configuring the clock for use including Alarm configuration Optional day of week calculation Periodic interrupt control 12 or 24 hour mode selection Setup of capture pins 2 Disabling the clock 3 Control of the clock including e Changing the alarm settings e Changing the current date or time e Error adjustment 4 Reading the clock status flags current time and date alarm time and date and any captured times 5 Reconfigure
491. re configuring thel C module R20UT0708EE0211 Rev 2 11 Page 2 24 Aug 01 2014 2tENESAS RX210 Group 2 Driver 2 25 Serial Peripheral Interface Driver The driver functions support the use of the SPI channel providing the following operations 1 Selection of the SPI pins for use 2 Configuration for use including e Automatic clock setting using transfer rate as an input 3 Disabling channels that are no longer required and enabling low power mode 4 Configuration of command sequence settings 5 Managing the transfer of data on the interface including e Automatic interrupt control e Automatic DMAC DTC control 6 Control of special modes such as loopback 7 Reading the status of a module Note The Clock Generation Circuit must be configured before configuring any SPI channel R20UT0708EE0211 Rev 2 11 Page 2 25 Aug 01 2014 2tENESAS RX210 Group 2 Driver 2 26 CRC Calculator Driver The driver functions support the CRC calculator providing the following operations 1 Configuration for use including e Polynomial selection e Bit order selection e Preparation for a new calculation 2 Disabling the calculator and enabling low power mode 3 Writing data to be used for the calculation 4 Reading the calculation result R20UT0708EE0211 Rev 2 11 Page 2 26 Aug 01 2014 RENESAS RX210 Group 2 Driver 2 27 12 bit Analog to Digital Converter Driver The driver functions support the use of the
492. re match A register TCORA PDL_TMR_TIME_CONSTANT_B Update the timer compare match B register TCORB Counter stop in response to ELC PDL_TMR_ELC_COUNT_STOP Stop a counter that was started by the ELC data3 The counter value This will be ignored if the register is not selected data4 The compare match A value This will be ignored if the register is not selected data5 The compare match B value This will be ignored if the register is not selected True if all parameters are valid and exclusive otherwise false Timer TMR R_TMR_CreateChannel PDL_TMR_STOP is to disable the counter clock source but PDL_TMR_ELC_COUNT_STOP is to stop the counter triggered by the ELC If PDL_TMR_ELC_COUNT_STOP is selected the counter is stopped but the clock source is still running The system will wait for the next ELC event to trigger the counter again Page 4 169 RENESAS RX210 Group 4 Library Reference Program example R20UT0708EE0211 Rev 2 11 Aug 01 2014 RPDL definitions include r pdl_tmr h RPDL device specific definitions include r pdl definitions h void func void Load the counter on channel TMRO R_TMR ControlChannel 0 PDL_TMR_COUNTER OxFF PDL NO DATA PDL NO DATA RENESAS Page 4 170 RX210 Group 4 Library Reference 8 R_TMR_ControlUnit Synopsis Prototype Descr
493. received volatile uint8 t data_sent Callback function prototype static void SCI Rx Callback void static void SCI Tx Callback void void main void volatile uint8 t rx buffer DATA LENGTH Initialise the system clocks NOTE The code to initialise the system clock using R_CGC_Set is omitted here Set Master Channel 6 pin options R_SCI_Set 6 L SCI PIN SCI6 RXD6 PBO PDI PDL SCI PIN SCI6 TXD6 PB1 PDL SCI PIN SCI6 SCK6 PB3 y Set Slave Channel 9 pins options R_SCI_Set 9 PDL SCI PIN SCI9 RXD9 PB6 PDL SCI PIN SCI9 TXD9 PB7 PDL SCI PIN SCI9 SCK9 PB5 Create Clock master channel for Rx and Tx R_SCI Create MASTER CHANNEL PDL SCI SYNC PDL SCI CLIK INT_OUT PDL_SCI_TX CONNECTED PDL SCI RX CONN 19200 1 Create Slave Channel NOTE Even though using an external clock the driver needs to know the expected baud rate Bit 31 is set to signify not generating baud R SCI Create SLAVE CHANNEL PDL SCI_SYNC PDL SCI_CIK_EXT 0x80000000 19200 1 R20UT0708EE0211 Rev 2 11 Page 5 60 Aug 01 2014 ztENESAS RX210 Group 5 Usage Examples First setup the slave to send data_sent false R_SCI_Send SLAVE CHANNEL PDL NO DATA Slave DATA LENGTH SCI Tx Callback Setup master to receive Non polling
494. red b7 b6 b4 b3 b2 b1 bO The bus master that caused the error Timeout Illegal address access 0 000 CPU 0 0 None 011 DTC or DMAC 1 Occurred data2 The status flags shall be stored according to register BERSR2 format as below Specify PDL_NO_PTR if this information is not required b15 b3 b2 b0 The upper 13 bits of the address that was accessed when the bus error occurred 0 in units of 512 Kbytes Return value True Category Bus Controller Reference R_BSC_Control Remarks e Call R_BSC_Control to clear the status registers after reading the status Program example RPDL definitions include r pdl bsc h RPDL device specific definitions tinclude r pdl definitions h void func void uint8 t statusl uintl6 t status2 Read the flags R_BSC_GetStatus amp statusl amp status2 i R20UT0708EE0211 Rev 2 11 Page 4 90 Aug 01 2014 RENESAS RX210 Group 4 2 11 DMA Controller 1 R_DMAC_Create Synopsis Prototype Description 1 3 Configure the DMA controller bool R_DMAC_Create uint8_t data1 Channel selection uint32_t data2 Configuration selection uint8_t data3 1 Trigger selection void data4 Source start address void data5 Destination start address uint16_t data6 Transfer count uint16_t data7 Repeat or Block size int32_t data8 1 Address offset 4
495. red by this document refer to the relevant sections of the document as well as any technical updates that have been issued for the products 1 Handling of Unused Pins Handle unused pins in accordance with the directions given under Handling of Unused Pins in the manual The input pins of CMOS products are generally in the high impedance state In operation with an unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of LSI an associated shoot through current flows internally and malfunctions occur due to the false recognition of the pin state as an input signal become possible Unused pins should be handled as described under Handling of Unused Pins in the manual 2 Processing at Power on The state of the product is undefined at the moment when power is supplied The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied In a finished product where the reset signal is applied to the external reset pin the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified 3 Prohibition of Access to Reserved Addresses Acc
496. red in the format below b31 b25 b24 Operating Power Control Mode transition flag 0 0 Transition completed 1 During Transition b23 b22 b20 b19 b18 b17 b16 Event detection flags 0 not detected 1 detected An interrupt has caused an exit Poweron from deep software standby mode 0 LVD2 LVD1 LVDO reset followed by an internal reset b15 b14 b13 b12 b11 b10 b9 b8 Deep Software Standby cancel request detection 0 0 No activity 1 The exit from deep software standby was caused by one of the following signals lIC SCL IC SDA NMI RTC alarm RTC interval LVD2 LVD1 b7 b6 b5 b4 b3 b2 b1 bO Deep Software Standby cancel request detection 0 No activity 1 The exit from deep software standby was caused by one of the following signals IRQ7 DS IRQ6 DS IRQ5 DS IRQ4 DS IRQ3 DS IRQ2 DS IRQ1 DS IRQ0 DS True LPC R_LPC_Create R_LPC_Control e Ifa flag is set to 1 it shall be automatically cleared to O by this function apart from the Power on reset flag which can be cleared only by a hardware reset RPDL definitions include r pdl lpc h RPDL device specific definitions tinclude r pdl definitions h void func void uint32 t status flags Find out what caused the exit from deep software standby R_LPC_GetStatus amp status flags i R20UT0708EE0211 Rev 2 11 Aug 01
497. reference value Specify PDL_NO_FUNC if not required oat priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid and exclusive otherwise false Comparator B R_CGC_Set Function R_CGC_Set must be called with the current clock source selected before using this function If callback function needs to be used interrupt must be enabled R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 292 RENESAS RX210 Group 4 Library Reference Program Example RPDL definitions tinclude r pdl_cpb h RPDL device specific definitions tinclude r pdl_definitions h void func void Configure a comparator B channel R_CPB Create 0 PDL_CPB_ IRQ ENABLE PDL CPB_IRQ ELC FALLING EDGE PDL NO FUNC 0 R20UT0708EE0211 Rev 2 11 Page 4 293 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 2 R_CPB_Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example Disable a Comparator B channel bool R_CPB_Destroy uint8_t data Channel selection Shut down a CPB channel data The comparator B channel n where n 0 or 1 True if the channel selection is valid otherwise false Comparator B None
498. rence Remarks Program example Read the Watchdog timer status bool R_WDT_Read uint16_t data A pointer to the data storage location Read and store the status flags and current counter value data The timer status shall be stored in the following format b15 b14 b13 b0 Refresh Error Underflow Flag 0 No refresh error 0 No underflow Down Counter Value 1 Refresh error 1 Underflow True Watchdog Timer If the Underflow flag is set to 1 it shall be automatically cleared to 0 by this function e lf the Refresh flag is set to 1 it shall be automatically cleared to O by this function RPDL definitions tinclude r pdl_wdt h RPDL device specific definitions tinclude r pdl_definitions h uintl6 _t WDT Status void func void Read th R_WDT_ Read amp WDT_ Status timer values y R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 202 RENESAS RX210 Group 4 Library Reference 4 2 20 1 R_IWDT_Set Synopsis Prototype Description Independent Watchdog Timer Configure the Independent Watchdog operation bool R_IWDT_Set uint32_t data II Configuration selection Select the operation of the Independent Watchdog timer and start it data Configure the timer options Use to separate each value Counter selection PDL_IWDT_T
499. rmat is dependent upon if using 12 hour or 24 hour mode 24 Hour Mode b31 b24 b23 b16 b15 b8 b7 b0 Day of week Hours Minutes Seconds Valid from 0 to 6 0 Sunday Specify OxFF for Valid from O Valid from O Valid from automatic calculation using the values in data5 to 23 to 59 0 to 59 12 Hour Mode b31 b24 b23 b22 b16 b15 b8 b7 b0 Day of week ds PM Hours Minutes Seconds relegada ol 0 AM Valid from Valid from Valid from pecify 0 i 1 PM 1to12 0to59 Oto59 calculation using the values in data3 data10 The alarm year month and day BCD format is used If not required specify PDL_NO_DATA b31 b16 b15 b8 b7 b0 Year Month Day Valid from 1 to 12 Valid from 0 to 9999 Valid from 1 to the number of days in the month func1 The function to be called when an alarm occurs Specify PDL_NO_FUNC if not required data11 The alarm interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func1 R20UT0708EE0211 Rev 2 11 Aug 01 2014 ENESAS Page 4 188 RX210 Group 4 Library Reference Description 4 4 Return value Category Reference Remarks Program example func2 The function to be called at the periodic interval Specify
500. rol iii A eed ie eed 4 115 Multi Function Timer Pulse Unit ccccccccceceeeeeceecne cece eeeesecacaeceeeeeseseneaeaeeeeesesenennieeeeeeeeeeees 4 122 REMTUZ Seducir A ee dot 4 122 REMTUZ Create iii A eee ee eed 4 125 REMTUZ DESUOY ci ad 4 135 R MTU2_ ControlChamel isie ia did 4 136 Ro MTU2 ControlUnit ihri Ad A td adn 4 139 R MTU2Z ReadChannel tica a a a ia aig 4 144 T RAMTUZ ReadUnit cir rita ta ais 4 147 42 15 Port Output Enables ccc taco ria ae ni a arden ide 4 148 Te TREPOE Sy A it el ee ee ee 4 148 2 R POE Create wren ante ahh aia nee ee al 4 150 3 CR POE Controla eee it eae nde a es nee ieee 4 152 4 e R POE Ge tStatus ii A cH ede ie te aiii 4 154 42 16 26 bit TIME tenn ei eee ia ei RN 4 155 Dir GREZTMReS t ins th a a A cn eee ee te ere 4 155 2 R_TMR GreateChannel s inaina aaa i aa iaaea ai aida cda 4 157 3 R TMR CreateUnitii i a nee ate er iene arial 4 160 4 R TMR CreatePeriOdic ni ainra a e a nde a cid La 4 163 5 R TMR CreateQne Shot cninn aie dd eet eal 4 166 6 R TMR Destroy cuicos A 4 168 7 R TMR Co ntrolChannel noaie aa aa aa aaae a a diia 4 169 8 O RIMR Co trolUmit OU 4 171 9 ReTEMR2ControlPenodics iaaea aaa aaa aa aaa a a a e aaae aaa aaa ee it Sae ieat 4 173 10 S R IMR ReadGCHannel eien e aa ataie ci dla ds i aaa bras 4 175 11 R TMR Read Unites em r tio aa aa a a a ae a a aa a aet a a reaa a a adhe iaa ae ats aaa 4 176 4 2 1f Compare Match Timer s snien eae aeee a alia
501. rol option R_RTC_Create Correct the Remark and add cross reference for R_CGC_Set R_CGC_Control and R_MCU_OFS Add new R_RTC_CreateWarm API R_SCI_Set Add missing pins to SCI6 R_ADC_12_Control Do not select CPU Off unless there is any interrupt to wake up the CPU RENES Revision History 3 RX210 Group Revision History Description 14 Apr 2014 R20UT0708EE0211 Rev 2 11 Aug 01 2014 Add PDL_TPU_START PDL_TPU_STOP options Add remark Calling this function TPU will start automatically Rename R_TPU_Control to R_TPU_ControlChannel Add remark The Stop operation is executed at the start of thisfunction The Start operation is executed at the end Therefore both options can be selected together with other changes in one function call Add R_TPU_ControlUnit Revise CGC usage example Revise LVD usage example Revise CAC usage example Revise LPC usage example software standby mode example Revise TMR usage example Revise CMT usage example Set numbering to RTC s usage examples Add new usage example of using RTC with warm start mode Revise IWDT usage example Revise SCI usage example Revise SPI usage example Revise ADC12 usage example Revise TS usage example Revise CPA usage example Revise CPB usage example Rename R_TPU_Control to R_TPU_ControlChannel Add MTU2 usage example Add RWP usage example Replace old by If the sub clock oscillator will not be used it
502. ror interrupt requests Return value True if success False if invalid parameters are selected Category Bus Controller Reference R_BSC_Create Remarks Before enabling the BSC operation call R_BSC_Create This function can be called from the error handling function assigned in R_BSC_Create e This function will clear the Interrupt Status Flag indirectly The bus can not be enabled disabled if ROM Flash Program Erase mode is set or if a operating power mode transition is in progress This function will return false if this is detected Program example RPDL definitions tinclude r pdl_bsc h RPDL device specific definitions tinclude r pdl_definitions h void func void Clear the bus error signals R_BSC_Control PDL_BSC_ERROR_CLEAR R20UT0708EE0211 Rev 2 11 Page 4 89 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 6 R_BSC_GetStatus Synopsis Prototype Description Read the External Bus Controller status registers bool R_BSC_GetStatus uint8_t data1 The status register 1 storage location uint16_t data2 The status register 2 storage location Read the BSC status registers data1 The status flags shall be stored according to register BERSR1 format as below Specify PDL_NO_PTR if this information is not requi
503. roy iicroiicioca cdi dt dit 4 268 3 CRECRC Write cio ii A A ate ated ei nee a Li 4 269 4 V EA A teeta aa eaae aa eao eee blag vette Lines aa aeaee a a wet Melee 4 270 4 2 25 12 bit Analog to Digital Converter ooonncccnnnoccccnonoccccnanoncncnanoncnc Ra RE ENEAN nano rca rra nr nr aa aaka iii 4 271 A 2 E A A T E thd deka addside Co Padtels dade EE AE Gide ike sahil E 4 271 2 R ADG 12 Create Unitar orilla tadubactiacach aaa aaee a ae ia ea sasaaa 4 272 3 DA a NY 4 277 4 R ADG 12 DestrOVetccrotiicotes acid tl taguatt cedida a a eaa ae tasteetdadzien idas bas dina 4 279 5 ORL AAA O OL 4 280 A DI A A OL 4 281 4 2 26 10 bit Digital to Analog CONVerter oooooncccnnnociccconocccccononcncnanoncnc nano nc nn Erra nr ran narran ran Eea rca 4 282 D RADAG10 Createvisatoitetdca ici iii idilio ladilla cldgh i abba oe habias 4 282 2 R DACO DOSO V ae ici tilda lied a e aaa aa lat bathed 2 4 283 A O AS ORAA EA A E AA TATEA A EEE A 4 284 4 2 27 IA 4 285 1 R TSi Create Sarira AA a deters TARA AAA At da 4 285 2 R TS DeSWOY ti A tada 4 286 3 RTS ECONO A A A AA AA AA DAR td 4 287 4 2 28 COMpParator Acticin LR AA a di dada 4 288 Te ORECPA Create tio il A Ad A AA a ii Aa 4 288 2 RECPALCONTOL e ii A IA ita 4 290 Sir o R CGPA Getstatuss ss ti A AA AAA A id 4 291 42 29 ComparatoriB 00 ti id AA Ai AR a di bra 4 292 1 RECPB Create id A RRA ta Ab Ra 4 292 2 R CPR DOS viciado title 4 294 3 HRACPBriGetotatuses ti ti daa 4 29
504. run normally while the one shot operates Stop the CPU when the one shot timer starts PDRCMI CPU ORF The CPU will re start when any valid interrupt occurs e DMAC DTC trigger control PDL_CMT_DMAC_DTC_TRIGGER_DISABLE or Disable or enable activation of the PDL_CMT_DMAC_TRIGGER_ENABLE or DMAC or DTC when a compare match PDL_CMT_DTC_TRIGGER_ENABLE occurs data3 The one shot time period in seconds func The function to be called when the one shot period ends If you specify PDL_NO_FUNC this function will wait for the timer to complete before returning You should always specify a function if PDL_CMT_CPU_OFF is selected to ensure that an interrupt will re start the CPU data4 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid and exclusive otherwise false Compare Match Timer R_CGC Set R CGC_ Control Page 4 180 RENESAS RX210 Group 4 Library Reference Remarks e Function R_CGC_Set must be called with the current clock source selected before using this function Function R_CMT_Create is not required Ensure that the timer channel is stopped before calling this function Note that the timer is stopped automatically when the one shot period is reached e Ifa callback function is specified this function will enable the rel
505. ry Reference Remarks R20UT0708EE0211 Rev 2 11 Aug 01 2014 Check the status of a DMA channel bool R_DMAC_GetStatus uint8_t data1 Channel number uint8_t data2 Status flags pointer uint32_t data3 Current source address pointer uint32_t data4 Current destination address pointer uint16_t data5 Current transfer count pointer uint16_t data6 Current Repeat or Block size count pointer Return status flags and current channel registers data1 The channel number n where n 0 to 3 data2 The status flags shall be stored in the following format Specify PDL_NO_PTR if the flags are not to be read b7 b5 b4 b3 b2 b1 bO Interrupt Transfer Escape Transfer End Status a 0 request End interrupt ESIF interrupt DTIF ACT DTE IR 0 Idle 0 Idle 0 Idle 0 Disabled 1 Generated 1 Generated 1 Operating 1 Enabled data3 Where the current source address shall be stored Specify PDL_NO_PTR if it is not required data4 Where the current destination address shall be stored Specify PDL_NO_PTR if it is not required data5 Where the current transfer count shall be stored Specify PDL_NO_PTR if it is not required eds current repeat or block size count shall be stored Specify PDL_NO_PTR if it is not required True if all parameters are valid and exclusive otherwise false DMA controller R_DMAC_Create e Ifthe Interrupt requ
506. s Prototype Description Return value Category References Remarks Program example R20UT0708EE0211 Rev 2 11 Aug 01 2014 Read from the Backup registers bool R_LPC_ReadBackup uint8_t data1 Data pointer uint8_t data2 II Data count Read data from the backup registers data1 The storage area for the data read from the backup area data2 The number of bytes to be read from the backup area Valid from 1 to 32 True if all parameters are valid otherwise false LPC R_LPC_WriteBackup The definition R_PDL_LPC_BACKUP_AREA_SIZE specifies the number of bytes that are available RPDL definitions include r pdl lpc h RPDL device specific definitions tinclude r pdl definitions h void func void uint8 t data_to_restore R_ PDL LPC BACKUP AREA SIZE Read data from the backup registers R_LPC_ReadBackup data_to restore R PDL LPC BACKUP AREA SIZE RENESAS oe RX210 Group 4 Library Reference 5 R_LPC_GetStatus Synopsis Prototype Description Return value Category References Remarks Program example Read the status flags bool R_LPC_GetStatus uint32_t data Data pointer Read the Low power status flags data The status flags shall be sto
507. s are the only IRQ pins that can be used to exit from deep software standby mode When operating power control mode switching is in progress do not call this function When the ROM is in program or erase mode do not call this function During the period from the time of WAIT instruction issuance for a sleep mode transition to return from sleep mode to normal operation do not call this function Ifthe NMI pin is enabled for cancelling deep software standby mode it cannot be disabled e Use R_CGC_Control to stop and start the clocks as required e When switching from normal power consumption mode to low power consumption mode call R_CGC_Set to change the clock settings before calling this function When PDL_LPC_SLEEP_RETURN_SWITCH_HOCO is selected the frequencies of the internal clocks ICLK PCLKD PCLKB FCLK and BCLK must be no more than the selected clock source frequency 2 before a transition is made to sleep mode The sleep mode return clock source switching function and clock source switching function by the ELC cannot be used at the same time When the PLL is operating low speed operating mode 1 or 2 cannot be selected When HOCO is operating low speed operating mode 2 cannot be selected e When HOCO frequency is 32MHz 36 864MHz 40MHz minimum waiting time is 7168 cycles When the HOCO frequency is 50MHz minimum waiting time is 9216 cycles If PDL_LPC_SLEEP_RETURN_SWITCH_HOCO or PDL_LPC_SLEEP_RETURN_SWITCH_MA
508. s the value for TMR1 For unit 1 the upper byte is the value for TMR2 and the lower byte is the value for TMR3 Page 4 171 RENESAS RX210 Group 4 Library Reference Program example RPDL definitions include r pdl_tmr h RPDL device specific definitions include r pdl definitions h void func void Load the unit 1 counter and constants R_TMR_ ControlUnit 1 PDL _TMR COUNTER PDL TMR TIME CONSTANT A PDL _TMR TIME CONSTANT B OxAAFF 0x100 0x5600 R20UT0708EE0211 Rev 2 11 Page 4 172 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 9 R_TMR_ControlPeriodic Synopsis Prototype Description Return value Category Reference Remarks R20UT0708EE0211 Rev 2 11 Aug 01 2014 Control periodic operation bool R_TMR_ControlPeriodic uint8_t data1 8 bit channel or 16 bit unit selection uint32_t data2 Configuration selection double data3 The new period or frequency double data4 The new pulse width or duty cycle Modify a periodic timer operation data1 PDL_TMR_TMRO or PDL_TMR_TMR1 or PDL_TMR_TMR2 or The channel n n 0 1 2 or 3 or unit n 0 or 1 to be PDL_TMR_TMR3 or configured PDL_TMR_UNITO or PDL_TMR_UNIT 1 data2 Select the options to be modified Use to separate each selection e Period or frequency
509. selections If multiple selections are required use to separate each selection The default settings are shown in bold Transfer mode selection PDL_DTC_NORMAL or Normal or PDL_DTC_REPEAT or Repeat or PDL_DTC_BLOCK Block mode PDL_DTC_SOURCE or PDL_DTC_DESTINATION If Repeat or Block mode is selected select the source or destination side to be the Repeat or Block area Address direction selection PDL_DTC_SOURCE_ADDRESS_FIXED or PDL_DTC_SOURCE_ADDRESS PLUS or PDL_DTC_SOURCE ADDRESS MINUS After a data transfer leave the source address unchanged increment it or decrement it PDL_DTC_DESTINATION_ADDRESS_FIXED or PDL_DTC_DESTINATION_ADDRESS_PLUS or PDL_DTC_DESTINATION_ADDRESS_MINUS After a data transfer leave the destination address unchanged increment it or decrement it Transfer data size PDL_DTC_SIZE_8or PDL_DTC_SIZE_16 or PDL_DTC SIZE 32 Select 1 2 or 4 bytes to be transferred in one operation e Chain transfer control PDL_DTC_CHAIN_DISABLE or PDL_DTC_CHAIN_CONTINUOUS or PDL_DTC_CHAIN_0 Disable chain transfer operation Perform continuous chain transfers or Perform a chain transfer when the transfer counter is changed from 1 to 0 or 1 to transfer size block size Interrupt generation PDL_DTC_IRQ_COMPLETE or PDL_DTC_IRQ_TRANSFER Select interrupt request generation when the transfer sequence completes or fo
510. show the included file directories Click on the Add button In the Add include file directory window enter the details as shown Add include file directory Base path Project directory X r pdl_lib_test Sub Directory RPDL Click on OK to close the window Click on the Add button In the Add include file directory window enter the details as shown Add include file directory Base path Project directory y i rpdl_lib_test Sub Directory Cancel Click on OK to close the window R20UTO708EE0211 Rev 2 11 L _ Page Aug 01 2014 ENESAS RX210 Group 1 Introduction 4 Add the RPDL library file The library file is added to the list used by the linker application Select the Link Library tab From the Show entries for drop down menu select Library files Click on the Add button In the Add library file window select Project directory and enter RPDL RX210_library as the File path Add library file Base path Project directory v i rpdl_lib_test File path RPDL RX21 O_library Cancel To use library with debug information enter RPDL RX210_library_debug as the File path Modify library file Base path Project directory v i rpdl_lib_test File path APD L4AX210_library_debug Cancel Click on OK to close the window Click on
511. sing this function call R_CGC_Set for each clock that will be measured or used as a reference If both edges are selected the clock duty cycle is assumed to be 50 If a frequency error callback function is specified then it must clear the error flag using R_CAC_Control to prevent continuous interrupts callbacks If a measurement complete callback function is specified then it must clear the measurement flag using R_CAC_Control to prevent continuous interrupts callbacks If an overflow callback function is specified then it must clear the overflow flag using R_CAC_Control to prevent continuous interrupts callbacks If using MCU version A the main clock can not be selected as either the reference clock or the clock to be measured RPDL definitions tinclude r pdl_cac h RPDL device specific definitions tinclude r pdl definitions h Callback functions void CAC frequency error void void CAC measurement complete void void CAC_overflow void void func void Use the main clock to check the LOCO accuracy R_CAC Create PDL CAC REFERENCE MAIN PDL CAC REFERENCE RISING PDL CAC REFERENCE DIV_8192 PDL CAC MEASURE LOCO PDL CAC MEASURE DIV 1 PDL CAC LIMIT TOLERANCE PDL NO DATA PDL NO DATA 10 10 CAC frequency error 15 CAC measurement complete 6 CAC overflow 10
512. sion transmission and reception R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS Page 4 214 RX210 Group 4 Library Reference Description 3 4 Options which are available in IIC mode Noise Filter Clock Select PDL_SCI_IIC_FILTER_DISABLED or The noise filter is disabled PDL_SCI_IIC_FILTER CLOCK_DIV1 or PDL_SCI_IIC_FILTER_CLOCK_DIV2 or The clock signal 1 2 4 or 8 is used with the PDL_SCI_IIC_FILTER_CLOCK DIV4 or noise filter PDL_SCI_IIC_FILTER_CLOCK_DIV8 SSDA Delay Output Select Delay of output on the SDA Pin relative to the falling edge on the SCL pin PDL_SCI_IIC_DELAY_SDA_0_1 or 0 to 1 cycle delay PDL_SCI_IIC_DELAY_SDA_1_2or 1 to 2 cycle delay PDL_SCI_IIC_DELAY_SDA_2 3 or 2 to 3 cycle delay sequence continues oF PDL_SCI_IIC_DELAY_SDA_29_ 30 or 29 to 30 cycle delay PDL_SCI_IIC_DELAY_SDA_30_31 30 to 31 cycle delay Options which are available in Smart Card Interface mode Data inversion PDL_SCI_INVERSION_OFF or PDL _SCI INVERSION ON Control data inversion transmission and reception e Base clock pulse cycle count PDL_SCI_BCP_32 or PDL_SCI_BCP_64 or PDL_SCI_BCP_93 or PDL_SCI_BCP_128 or The number of base clock cycles in a 1 bit data PDL_SCI_BCP_186 or transfer period PDL_SCI_BCP_256 or PDL_SCI_BCP_372 or PDL_SCI_BCP_512 e Parity selection PDL_SCI_PARITY_EVEN or
513. sis Select a low power consumption mode Prototype bool R_LPC_Control uint32_t data Mode selection Description Transition to one of the low power modes data Control selection All selections are optional The default settings are shown in bold If multiple selections are required use to separate each selection e Mode selection PDL_LPC_MODE_SLEEP or PDL_LPC_MODE ALL MODULE _CLOCK_STOP or PDL_LPC_MODE_SOFTWARE_STANDBY or PDL_LPC_ MODE _DEEP_SOFTWARE_STANDBY Select the mode to be entered e Operating power control PDL_LPC_CHANGE_HIGH_SPEED or PDL_LPC_CHANGE_MIDDLE_SPEED_1A or PDL_LPC_CHANGE_MIDDLE_SPEED_1B or PDL_LPC_CHANGE_MIDDLE_SPEED_2A or PDL_LPC_CHANGE_MIDDLE_SPEED_2B or PDL_LPC_CHANGE_LOW_SPEED_1 or PDL_LPC CHANGE LOW SPEED 2 Select the operating power control mode MCU Version restriction see remarks Sleep mode return clock source switching PDL_LPC_SLEEP_RETURN_CHANGE_DISABLE or PDL_LPC_SLEEP_RETURN_CHANGE_HOCO or PDL_LPC SLEEP _RETURN_CHANGE_MAIN Control clock source switching at cancellation of sleep mode All module clock stop cancellation modification PDL_LPC_TMR_OFF or PDL_LPC_TMR_UNIT_0 or PDL_LPC_TMR_UNIT_1 or PDL_LPC_TMR_BOTH Select whether the TMR units can be used to exit from All module clock stop mode e 1 O port retention cancellation PDL_LPC_IO_RELEASE Canc
514. skable interrupt occurs Specify PDL_NO_FUNC if not required data5 The interrupt priority level for the Monitor 1 interrupt If specifying a callback function in func1 then select between 1 lowest priority and 15 highest priority Set to 0 if using LVD to trigger the ELC without generating an interrupt see Remarks for details func2 The function to be called when a Monitor 2 maskable interrupt occurs Specify PDL_NO_FUNC if not required data6 The interrupt priority level for the Monitor 2 interrupt If specifying a callback function in func2 then select between 1 lowest priority and 15 highest priority Set to 0 if using LVD to trigger the ELC without generating an interrupt see Remarks for details RENESAS dia RX210 Group 4 Library Reference Return value Category References True if the parameters are valid otherwise false Voltage detection circuit R INTC_CreateExtInterrupt R_CGC_Set R_CGC_Control R_LLPC_GetStatus R_MCU_OFS Remarks Program example If a non maskable interrupt will be generated call R_INTC_CreateExtInterrupt to set up the NMI handler and to accept LVD based interrupt signals The LVD shares its registers with Comparator A so both cannot be used at the same time If using the digital filter function R_CGC_Set must be called with the current clock source selected before using this function If using the digital
515. ta2 The value will be between 0x00 and OxFF for a port 0 or 1 for a pin If the I O port specification is incorrect false is returned otherwise true is returned 1 0 port R_IO_PORT_Set e lf an invalid port or pin is specified the operation of the function cannot be guaranteed The input buffer for the specified port or pin must be switched on see R_IO_PORT_Set RPDL definitions include r pdl io port h RPDL device specific definitions tinclude r _pdl definitions h void func void uint8 t data Get the value of port pin P12 R_IO_PORT_Read PDL IO PORT 1 2 amp data i Get the value of port 4 R_IO_PORT_Read PDL IO PORT 4 amp data i R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS ae RX210 Group 4 Library Reference 5 R_IO_PORT_Write Synopsis Prototype Description Return value Category References Remarks Program example Write data to an I O port bool R_IO_PORT_Write uint16_t data1 Port or port pin selection uint8_t data2 The data to be written to the I O port or port pin Write data to an I O port or I O port pin data1 Use either one of the following definition values from 4 2 3 One port definition or One port pin definition data2 The value must be between 0x00 and OxFF for a port O or 1 for a pin True if the para
516. ta3 Channel selection Control options II Extended timing control Modify the operation of the selected SPI channel data1 Select channel SPIn where n 0 only data2 Control the channel If multiple selections are required use to separate each selection All items are optional Specify PDL_NO_DATA if not required Channel control PDL_SPI_DISABLE Disable and partially initialise the SPI channel e Loopback control PDL_SPI_LOOPBACK_DISABLE or PDL_SPI_LOOPBACK_DIRECT or PDL_SPI_LOOPBACK_REVERSED Disable or enable loopback in direct or reversed mode data3 Extended timing control optional All items apply only to Master mode Specify PDL_NO_DATA if not required If multiple selections are required use to separate each selection e Extended clock delay PDL_SPI_CLOCK_DELAY_1 or PDL_SPI_CLOCK_DELAY_2 or PDL_SPI_CLOCK_DELAY_3 or PDL_SPI_CLOCK_DELAY_4 or PDL_SPI_CLOCK_DELAY_5 or PDL_SPI_CLOCK_DELAY_6 or PDL_SPI_CLOCK_DELAY_7 or PDL_SPI_CLOCK _DELAY_8 The number of bit clock periods between the assertion of the SSL pin and the start of RSPCK oscillation Ignored in Slave mode Extended SSL negation delay PDL_SPI_SSL_DELAY_1 or PDL_SPI_SSL_DELAY_2 or PDL_SPI_SSL_DELAY_3 or The number of bit clock periods between the end of PDL_SPI_SSL_DELAY_4 or RSPCK oscillation and the negation of the active SSL PDL_SPI_SSL_DELAY_5 or p
517. tatus 0 30 second adjustment Reset Clock 0 Normal operation 0 Normal operation 0 Stopped 1 Adjustment in progress 1 Reset in progress 1 Running Format if datal PDL_ RTC READ ALARM The enable bits for the alarm shall be stored in the following format 1 enabled meaning the unit is part of the alarm setting 0 disabled meaning the unit is ignored Specify PDL_NO_PTR if the flags are not to be read b7 b6 b5 b4 b3 b2 b1 bO 0 Year Month Day Day of week Hours Minutes Seconds Format if datal PDL_RTC READ CAPTURE x Specify PDL_NO_PTR if the flags are not to be read b7 b1 bO 0 1 Event detected 0 No event detected data3 The day of the week and time Specify PDL_NO_PTR if it is not required See R_RTC_Read for the format data4 The year month and day Specify PDL_NO_PTR if it is not required See R_RTC_Read for the format True if all parameters are valid otherwise false Page 4 196 RENESAS RX210 Group 4 Library Reference Category Real time clock Reference R_RTC_Create R_RTC_CreateWarm Remarks Ifan interrupt request flag is set to 1 it shall be automatically cleared to O by this function Refer to R_RTC_Create for the time and date formats Ifthe Carry flag is read as 1 the current time and date were updated during the read process and should be re read The year and day of week is not recorded when using the capture
518. ted RDON Valid between 0 and 7 data14 The number of cycles before the write strobe is asserted WRON Valid between 0 and 7 data15 The number of cycles before the write data is output WDON Valid between 0 and 7 data16 The number of cycles before the chip select is asserted CSON Valid between 0 and 7 True if all parameters are valid and exclusive otherwise false Bus Controller R_BSC_Create Use this function to set up each required area and then call R_BSC_Create This function is not applicable if using packages with less than 100 pins The endian mode of the CPU is selected by the MDE bits in the MDES or MDEB registers Multifunction Pin Control registers are modified by this function The cycle count parameters are not checked for validity Use the hardware manual to check these values Setting single write strobe mode is prohibited in the 8 bit bus space RENESAS PRAT RX210 Group 4 Library Reference Program example RPDL definitions include r pdl bsc h RPDL device specific definitions include r pdl definitions h void func void Configure CS2 8 bit width maximum cycle counts R_BSC CreateArea 2 PDL _BSC_ WIDTH 8 15 Loy R20UT0708EE0211 Rev 2 11 Page 4 87 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 4 R_BSC_Destroy Synopsis Prototype Description Return value
519. tegory Reference Remarks Program example R20UT0708EE0211 Rev 2 11 Aug 01 2014 Read from timer channel registers bool R_TMR_ReadChannel uint8_tdata1 II Channel selection uint8_t data2 A pointer to the data storage location uint8_t data3 A pointer to the data storage location uint8_t data4 A pointer to the data storage location uint8_t data5 A pointer to the data storage location Read any of the timer s counter compare or status flag registers data1 The channel number n where n 0 1 2 or 3 data2 The status flags shall be stored in the format below The flag will be set to 1 if the condition has been detected Specify PDL_NO_PTR if the flags are not to be read b7 b4 b3 b2 b1 bO 0 ELC count state Overflow Compare match B_ Compare match A data3 A pointer to where the counter value shall be stored Specify PDL_NO_PTR if it is not required data4 Where the compare match A value shall be stored Specify PDL_NO_PTR if it is not required data5 Where the compare match B value shall be stored Specify PDL_NO_PTR if it is not required True Timer TMR R_TMR_CreateChannel e Ifthe status flags are read any flag that has been set to 1 shall be automatically cleared to O by this function The ELC count flag is valid only when n 0 or 2 tinclude r pdl_tmr h RPDL device specific definitions tinclude
520. tegory data1 The comparator A channel number n where n 0 to 1 data2 Configure the Comparator A channel To set multiple options at the same time use to separate each value The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Operation PDL_CPA_MONITOR_ONLY or Select no action for monitor only PDL_CPA_INTERRUPT_RESET_ENABLE enable interrupt reset for comparator A Digital filter PDL_CPA_FILTER_DISABLE or PDL_CPA_FILTER_LOCO_DIV_1 or PDL_CPA_FILTER_LOCO_DIV_2 or PDL_CPA_FILTER_LOCO_DIV_4 or PDL CPA FILTER LOCO DIV 8 Configure the digital filter for comparator A Mode Select Not valid for monitor only operation selected PDL_CPA_MODE_SELECT_INTERRUPT or PDL_CPA_MODE_SELECT_RESET Select mode for comparator A e Reset negation Select Valid for reset mode selected PDL_CPA_NEGATION_AFTER_RESET or PDL_CPA_NEGATION_AFTER_DETECT Select reset negation for comparator A e Interrupt Event Generation Condition Select Valid for interrupt mode selected PDL_CPA_IRQ_BELOW_CVREFA or Select Interrupt Event Generation PDL_CPA_IRQ_ABOVE_N_EQUAL_CVREFA or Condition of above and equal below or PDL_CPA_IRQ_CROSS_CVREFA cross CVREFA for comparator A e Interrupt Type Valid for interrupt mode selected PDL_CPA_NONMASKABLE_INTERRUPT or Select non maskable interrupt PDL_CPA_MASKABLE_INTERRUPT Select maskable interrupt or ELC eve
521. ter is not selected TGRD_TGRV_value For n 0 3 or 4 The register TGRD value For n 5 The register TGRV value This will be ignored if the register is not selected TGRE_TGRW_value For n 0 The register TGRE value For n 5 The register TGRW value This will be ignored if the register is not selected TGRF_value For n 0 The general register TGRF value This will be ignored if the register is not selected TADCOBRA_value For n 4 ADC start request cycle set buffer A This will be ignored if the register is not selected TADCOBRB_value For n 4 ADC start request cycle set buffer B This will be ignored if the register is not selected True if the channel number is valid otherwise false Multi function Timer Pulse Unit R_MTU2_Create R_MTU2_ControlUnit Remarks R20UT0708EE0211 Rev 2 11 Aug 01 2014 e Before calling this function use R_MTU2_Create to configure the channel operation e Either this function or R_MTU2_ControlUnit must be used to start the timers The Stop operation is executed at the start of this function The Start operation is executed at the end Therefore both options can be selected together with other changes in one function call e If noise filter is enabled before starting the timer make sure at least 2 cycles of the selected noise filter clock has elapsed after the timer configuration use R_MTU2_Create Page 4 137 RENESAS RX210 Group
522. ters are valid and exclusive otherwise false Category Interrupt control Reference R_INTC_CreateExtInterrupt R_INTC_GetExtInterruptStatus Remarks The NMI pin was enabled during R_INTC_CreateExtInterrupt and cannot be disabled an MCU design feature When disabling an IRQn pin the Interrupt Request flag will be cleared automatically Acallback function may be called once more if a valid event occurs just before the interrupt pin is disabled R20UT0708EE0211 Rev 2 11 Page 4 23 Aug 01 2014 RENESAS RX210 Group 4 Library Reference Program example RPDL definitions include r pdl intc h RPDL device specific definitions include r pdl_ definitions h void func void Disable the IRQ1 interrupt pin and clear the flag R_INTC ControlExtInterrupt PDL_INTC_IRO1 PDL INTC DISABLE PDL INTC CLEAR IR FLAG R20UT0708EE0211 Rev 2 11 Page 4 24 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 7 R_INTC_GetExtInterruptStatus Synopsis Prototype Description Return value Category Reference Remarks Program example Read the external interrupt status bool R_INTC_GetExtinterruptStatus uint8_t data1 Pin selection uint8_t data2 A pointer to the buffer where the status data shall be stored Acquire the status for the specified external int
523. the given product Table of Contents Table ot Contents A ida 1 1 1 INTFOCUCION cnica add A Ai A 1 1 1 1 Tool chain requirement ccccceeceseenecceceeeeeeeesenaeeeeeeesesecaaeaeceeeeeseceaaaeeeeeeeedsenaeaeeeeeeeeeeeesanieeeeees 1 2 1 2 Compiler options when you use this Produc cccceceeeeeeeecceceeeeeeececaaeaeeeeeeesececaaeceeeeeeeseesesieeeeess 1 2 1 3 Using the library within your Project enina EE EEEREN 1 2 1 31 Mia the PDG gr phical utility s enea ae scceds ta cba 1 2 1 372 USING RPDL Stand alone serari giant E NEE E AEAEE E EEA EAE ceetaiaecttatiagieeeetabes 1 2 1 Urap the RPDE MES iorri aid ltd eii a 1 2 2 Copy the files into your project area ooococnnnccccnnonccccnnoncccnononcccnnnonnncnn non ncc canon nc cnn ARETA NEENA REAREA REDAT 1 3 A e the New O cag sacagetasad EEA thas ENEA EATE 1 6 4 Add the RPDE library tile stg ccoo its iii airada 1 7 5 Include the new source MeS astiaren aeieea een E AA EREA EEE A EREET 1 8 6 Peripherals that are not required cccccceceeeeceececeeeeeeeceecaeceeeeesecaaaeeeeeeeeeseceeaeeeeeeesesessesaeeeeees 1 8 7 Peripherals that are not supported by RPDL ccececeeccececeeeeeeeeneeeeeeeeeeseceeeaeeeeeeeeesessnaeeseees 1 8 8 Avoid conflicts with standard project files nnccconnncccnnnonnccnnnannncnnnarn nr nano rar rnnn nn 1 9 9 Setithe DUI OPt NS A sse eierne iaag A A AAA IIA AA e aa Eae bi 1 11 10
524. the write protection Other RPDL functions automatically enable and disable access to registers as required so this function is normally not required RPDL definitions include r pdl_ rwp h RPDL device specific definitions include r pdl definitions h void func void Enable access to the LVD registers R_RWP_ Control PDL RWP ENABLE LVD WRITE i R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS eee RX210 Group 4 Library Reference 2 R_RWP_GetStatus Synopsis Get the status of the register protection Prototype bool R_RWP_GetStatus uint8_t data1 Status flags pointer uint8_t data2 Status flags pointer Description Get the status of the register protection data1 The Protect Register PRCR If the value is not required specify PDL_NO_PTR b7 b4 b3 b2 b1 bO LVD VRCR Mode and Reset CGC 0 0 Write Disabled 0 Write Disabled 0 Write Disabled 0 Write Disabled 1 Write Enabled 1 Write Enabled 1 Write Enabled 1 Write Enabled data2 The MPC Write Protect Register PWPR If the value is not required specify PDL_NO_PTR b7 b6 b5 bO BOWI PFSWE 0 Writing to the PFSWE bit is enabled 0 Writing to the PFS register is disabled 0 1 Writing to the PFSWE bit is disabled 1 Writing to the PFS register is enabled Return value True Category RWP
525. this function e Clearing a level triggered event flag will fail if the trigger is still asserted e Interrupt disabling is processed at the start of the function and enabling is processed at the end This allows a flag to be cleared and the interrupt re enabled in one function call Page 4 152 ENESAS RX210 Group Program example RPDL definitions include r pdl poe h RPDL device specific definitions include r pdl definitions h void func void Select high impedance on the MTUO I O pins R_POE Control 4 Library Reference PDL POE MTUO HI Z ON PDL NO DATA PDL NO DATA R20UTO708EE0211 Rev 2 11 Page 4 153 Aug 01 2014 RENESAS RX210 Group 4 Library Reference 4 R_POE_GetStatus Synopsis Prototype Description Return value Category Reference Remarks Program example Check the status of the Port Output Enable module bool R_POE_GetStatus uint16_t data Status flags pointer Return the status flags data The status flags shall be stored in the following format b15 b14 b13 b10 b9 b8 Output short detection High impedance request detection more 0 MTU3 or MTU4 0 OSTSTF POE8 0 Not detected 0 No request 1 Detected 1 Requested b7 b6 b5 b4 b3 b2 b1 bO High impedance request detection on
526. tion uint8_t data2 Register selection uint16_t data3 Register value uint16_tdata4 Register value uint16_tdata5 Register value uint16_t data6 Register value uint16_tdata7 Register value Description Modify a timer channel s registers data1 The channel number n where n 0 to 5 data2 The channel settings to be modified If multiple selections are required use to separate each selection e Counter stop re start PDL_TPU_STOP Stop the count operation PDL_TPU_START Start the count operation e The registers to be modified PDL_TPU_COUNTER Update the timer counter register TCNT PDL_TPU_TGRA Update the general register A TGRA PDL_TPU_TGRB Update the general register A TGRB PDL_TPU_TGRC Update the general register A TGRC Only supported for n 0 or 3 PDL_TPU_TGRD Update the general register A TGRD Only supported for n 0 or 3 data3 The counter value This will be ignored if the register is not selected data4 The general register A value This will be ignored if the register is not selected data5 The general register B value This will be ignored if the register is not selected data6 The general register C value This will be ignored if the register is not selected data7 The general register D value This will be ignored if the register is not selected Return value True if all p
527. tion string 1 volatile char destination string 2 volatile char destination string 3 volatile uint8 t transfer complete void main void Enable software interrupts R_INTC_CreateSoftwareInterrupt PDL_INTC_DTC_SW_TRIGGER_ENABL PDL_NO_FUNC 0 y Configure the controller R_DTC_Set PDL DTC ADDRESS FULL R20UT0708EE0211 Rev 2 11 Page 5 23 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples dtc vector table i Configure the DTC for Software trigger R_DTC Create PDL DTC BLOCK PDL DTC SOURCE PDL DTC SOURCE ADDRESS PLUS PDL DTC DESTINATION ADDRESS PLUS PDL DTC SIZE 8 PDL DTC CHAIN 0 PDL DTC _TRIGGER_SW dtc_sw_transfer data source string 1 destination string 1 1 uint8 t strlen source string 1 Configure the DTC for chain transfer R_DTC Create PDL DTC BLOCK PDL DTC SOURCE PDL DTC SOURCE ADDRESS PLUS PDL DTC DESTINATION ADDRESS PLUS PDL DTC SIZE 8 PDL_DTC_CHAIN 0 PDL DTC TRIGGER CHAIN dtc_sw_transfer data 4 source string 2 destination string 2 1 uint8 t strlen source string 2 y Configure the DTC for chain transfer R_DTC Create PDL DTC BLOCK PDL DTC SOURCE PDL DTC SOURCE ADDRESS PLUS PDL DTC DESTINATION ADDRESS PLUS PDL DTC SIZE 8 PDL DTC TRIGGER CHAIN dtc_sw transfer data 8 source strin
528. truction When exporting the Renesas Electronics products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations It is the responsibility of the buyer or distributor of Renesas Electronics products who distributes disposes of or otherwise places the product with a third party to notify such third party in advance of the contents and conditions set forth in this document Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics products This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics 2012 4 General Precautions in the Handling of MPU MCU Products The following usage notes are applicable to all MPU MCU products from Renesas For detailed usage notes on the products cove
529. tted by the IIC When the last byte has been sent it is our job to issue a IIC stop void iic_tx_end_handler void Process according to state switch g_IIC Tx State case IIC TX STATE WAIT DTC DTC has finished transfer so now wait for last byte to be transmitted g_IIC Tx State IIC TX STATE WAIT LAST BYTE break Case IIC TX STATE WAIT LAST BYTE uint32 t status flags 0 Wait for the transmission to fully complete do R_TIC GetStatus IIC CHANNEL amp status flags PDL_NO PTR PDL NO PTR i while status flags amp 0x0080u Issue a Stop condition R_TIC Control IIC CHANNEL PDL IIC STOP R20UT0708EE0211 Rev 2 11 Page 5 86 Aug 01 2014 RENESAS RX210 Group 5 Usage Examples This master write has completed g_IIC Tx State IIC_TX STATE FINISHED break default Not expected This callback is registerd with R_IIC MasterReceive void iic rx end handler void uint32 t DestAddr 0 Read the next destination address for the current transfer R_DTC_GetStatus dtc_iicl rx transfer data PDL_NO PTR PDL_NO PTR amp DestAddr PDL_NO PTR PDL NO PTR y Read one more byte with NACK condition and stop R_IIC MasterReceiveLast IIC CHANNEL uint8 t DestAddr y g_IIC Rx busy false Figure 5 47 An example of write data to and reading data from
530. turn false if this condition is detected In Async and Async MP modes the Tx pin is initially set to the Mark state The R_SCI_Control function can subsequently be used to set the Space state SPI Multi Master mode is not supported Hence in SPI Master mode the SS pin cannot be enabled e If the option of using a delayed clock phase is selected in synchronous mode then a delay is required following the final receive interrupt before the operation can be completed This delay is implemented as a software loop in the SCI RXI interrupt routine See source file Interrupt_SCl c for details Smaller device packages do not support all SCI channels Page 4 216 RENESAS RX210 Group 4 Library Reference The range of achievable bit rates bps is listed below Data clock a frcikB Mode source Limit 32 MHz 12 5 MHz 12 MHz 8 MHz internal Minimum 62 24 23 16 Asynchronous Maximum 2 000 000 781 250 750 000 500 000 External 1 000 000 390 625 375 000 250 000 iNtemal Minimum 489 191 184 123 Synchronous Maximin 4 000 000 1 562 500 1 500 000 1 000 000 External 5 333 333 2 083 333 2 000 000 1 333 333 Smart card Internal Minimum 2 1 l 1 Maximum 500 000 195 312 187 500 125 000 Program example RPDL definitions include r_pdl_sci h RPDL device specific definitions tinclude r pdl definitions h void func void Configure SCIO for asynchron
531. uc Nene 1 VCC 2 Vdett 0 None SOME 1 Detected or the monitor is 1 Detected or the monitor is disabled disabled Return value True Category LVD Reference R_LVD_Control R_LVD_Create Remarks Use R_LVD_Control to clear the detection flags e Adetection flag is not valid if Monitor only operation was selected in R_LVD_Create RPDL definitions tinclude r pdl_lvd h RPDL device specific definitions tinclude r pdl_definitions h void func void uint8 t StatusFlags Read the LVD status R_LVD_GetStatus amp StatusFlags y R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS did RX210 Group 4 Library Reference 4 2 7 1 R_CAC_Create Synopsis Configure the clock accuracy circuit Prototype bool R_CAC_Create uint32_t data1 uint8_t data2 double data3 uint16_t data4 uint16_t data5 II Signal selection External input timing Upper limit value II Lower limit value void func II Callback function uint8_t data6 Interrupt priority level void func2 II Callback function uint8_t data7 Interrupt priority level void func3 II Callback function uint8_t data8 Description 1 2 data1 Interrupt priority level Clock Frequency Accuracy Measurement Circuit External input configuration Configure the operation of the Clock frequency accuracy measurement circuit Choose the reference and me
532. unc1 II Callback function void func2 Callback function uint8_t data2 Interrupt priority level Enable interrupts and register callback functions data1 Interrupt selection If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e High impedance request response PDL_POE_IRQ HI Z 0 3 DISABLE or Disable or enable an interrupt on detection of ea ii any high impedance request on pins POEO to PDL_POE_IRQ_HI_Z_ 0 3 ENABLE POES3 e Output short detection response PDL_POE_IRQ_SHORT_3_4_DISABLE or PDL_POE_IRQ_SHORT_3_4_ENABLE Disable or enable an interrupt on detection of a short on any MTU channel 3 or 4 two phase output pair func1 The function to be called when an enabled request on pins POEO to POE3 or an output short on MTU channels 3 or 4 occurs Specify PDL_NO_FUNC if not required func2 The function to be called when a request on pin POE8 occurs Specify PDL_NO_FUNC if not required data2 The interrupt priority level Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for all parameters func1 and func2 True if all parameters are valid and exclusive otherwise false Port Output Enable R_POE Set R POE GetStatus Use R_POE_GetStatus to determine the interrupt cause Acallback function is e
533. unit registers to be modified If multiple selections are required use to separate each selection e The registers to be modified These apply only to complementary PWM mode PDL_MTU2_REGISTER_DEAD_TIME Update the dead time data register TDDR PDL_MTU2_REGISTER_CYCLE_DATA Update the cycle data register TCDR PDL_MTU2_REGISTER_CYCLE BUFFER Update the cycle buffer register TCBR TDDR_value The dead time data register value This will be ignored if the register is not selected TCDR_value The cycle data register value This will be ignored if the register is not selected TCBR_value The cycle buffer register value This will be ignored if the register is not selected True if all parameters are valid and exclusive otherwise false Multi function Timer Pulse Unit Page 4 142 ENESAS RX210 Group Reference Remarks Program example R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference R_MTU2_ControlChannel i i VO PD PD PD Either this function or R_MTU2_ControlChannel must be used to start the timers The Stop operation is executed at the start of this function The Start operation is executed at the end Therefore both options can be selected together with other changes in one function call The register access enable operation is executed at the start of this function The register access disable op
534. upt can be processed until a callback function has completed In Multi processor mode R_SCI_Receive is to be called in a pair the first one is to receive ID ID cycle the second one is to receive data Data cycle For ID reception it could be done by reception interrupt by specifying func or by internal polling operation without specifying func1 For Data reception it will be the same as normal Asynchronous mode For a usage example of Multi processor mode please refer to section 5 17 6 For the ID cycle the DMAC DTC trigger control will be ignored In synchronous mode if both the Tx Data and the Rx Data pins have been enabled when R_SCI_Create was called then a reception must be performed in conjunction with a corresponding transmission This is achieved by calling R_SCI_Receive in non polling mode and then R_SCI_Send Please refer to the usage example in Section5 17 5 Do not use this function in SPI mode use R_SCI_SPI_Transfer Do not use this function in IIC mode use R_SCI_IIC_Read If using the DMAC or DTC this module does not know when the reception has ended Therefore when it has completed the user must call the R_SCI_Control function with option PDL_SCI_STOP_RX to manually disable the reception If a callback function is specified and the interrupt priority level is zero this function will return false If PDL_SCI_RX_CONTINUOUS_ENABLE is selected then the callback will be called after the data has been received
535. us R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS ei RX210 Group The INTC Read Write and Modify functions use one of the following register definitions IR register definitions 4 Library Reference PDL_INTC REG IR BSC BUSERR PDL_INTC REG IR MTU4 TGIA PDL_INTC_ REG IR FCU _FIFERR PDL_INTC_ REG IR _MTU4 TGIB PDL_INTC_ REG _IR_FCU _FRDYI PDL_INTC_ REG IR _MTU4 TGIC PDL_INTC REG _IR_ICU_ SWINT PDL_INTC_ REG _IR_MTU4 TGID PDL_INTC REG IR CMTO CMI PDL_INTC RE
536. us flags shall be stored in the format below b7 b4 b3 b2 4 Library Reference b1 Pointer to the variable where the status value shall be stored II Data storage location II Data storage location II Data storage location bO 0 Overflow Measurement Frequency error Operation 0 Not detected 1 Detected 0 No event 1 Completed 0 Not detected 1 Detected 0 Disabled 1 Enabled Return value Category References Remarks Program example R20UT0708EE0211 Rev 2 11 Aug 01 2014 data2 Where the upper limit value register CAULVR value shall be stored Specify PDL_NO_PTR if it is not required data3 Where the lower limit value register CALLVR value shall be stored Specify PDL_NO_PTR if it is not required data4 Where the counter buffer register CACNTBR value shall be stored Specify PDL_NO_PTR if it is not required True Clock frequency accuracy measurement circuit None None RPDL definitions tinclude r pdl_cac h RPDL device specific definitions tinclude r pdl_definitions h void func void uint8 t Status flags R_CAC_GetStatus amp Status_ flags PDL _NO PTR PDL NO PTR PDL NO PTR RENESAS Page 4 67 RX210 Group 4 Library Reference 4 2 8 Low Power Consumption 1 R_LPC_Create Synopsis Prototype
537. uses PCLK 1 TGRD input capture input selection PDL_TPU_D_IC_TIOCD or PDL_TPU_D IC TIOCC Input capture using pin TIOCDn or TIOCCn data6 The timer counter value data7 The register TGRA value data8 The register TGRB value data9 The register TGRC value ignored for n 0 and 3 data10 The register TGRD value ignored for n 0 and 3 func The function to be called when a TGRA event occurs Specify PDL_NO_FUNC if not required func2 The function to be called when a TGRB event occurs Specify PDL_NO_FUNC if not required RENESAS Page 4 308 RX210 Group Description 5 5 Return value Category Reference Remarks R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference func3 The function to be called when a TGRC event occurs Specify PDL_NO_FUNC if not required ignored for n 0 and 3 func4 The function to be called when a TGRD event occurs Specify PDL_NO_FUNC if not required ignored for n 0 and 3 data11 The interrupt priority level for TGRx events Select between 1 lowest priority and 15 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for all parameters func1 func2 func3 and func4 func5 The function to be called when an overflow occurs Specify PDL_NO_FUNC if not required func6 The function to be called when an underflow occurs Spec
538. ut TMOn pins as required This function will return false if a pin is enabled but is not set properly The output will be high impedance when PDL_TMR_OUTPUT_IGNORE_CM_A and PDL_TMR_OUTPUT_IGNORE_CM_B are selected If a callback function is specified this function will enable the relevant interrupt Please see the notes on callback function usage in 86 Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed RENESAS Page 4 161 RX210 Group 4 Library Reference Program example include r_pdl_tmr h RPDL device specific definitions tinclude r pdl_definitions h void func void Configure TMR unit 0 PCLKB clear after a compare match A R_TMR_ CreateUnit 0 PDL TMR CLK PCLK DIV 1 PDL TMR CLEAR CM A 0 0 199 99 PDL_NO_FUNC PDL_NO_FUNC PDL_NO_FUNC 0 R20UT0708EE0211 Rev 2 11 Page 4 162 Aug 01 2014 RENESAS RX210 Group 4 R_TMR_CreatePeriodic Synopsis Prototype Description Return value Category Select periodic operatio 4 Library Reference n bool R_TMR_CreatePeriodic uint8_t data1 uint32_t data2 double data3 double data4 void func void func2 uint8_t data5 II 8 bit channel or 16 bit unit selection 1 Configuration selection II Period or
539. vice specific definitions include r pdl definitions h void func void disable Comparator A channel 0 R_CPA_Control 0 PDL CPA LVD CIRCUIT DISABLE R20UT0708EE0211 Rev 2 11 Aug 01 2014 Page 4 290 RENESAS RX210 Group 4 Library Reference 3 R_CPA_GetStatus Synopsis Check the status of the Comparator A module Prototype bool R_CPA_GetStatus uint8_t data II Status flags pointer Description Return the status flags data The comparator A status flag shall be stored in the following format b7 b6 b5 b4 b3 b2 b1 bO Status Change Status Change 0 0 CMPA2 lt CVREFA 0 None 0 0 CMPA1 lt CVREFA 0 None 1 CMPA2 CVREFA 1 Detected 1 CMPA1 gt CVREFA 1 Detected Return value True Category Comparator A Reference None Remarks Ifthe flag is set it is automatically cleared by this function Program example RPDL definitions include r pdl cpa h RPDL device specific definitions tinclude r pdl_definitions h void func void uint8 t StatusFlags Read the CPA status R_CPA_GetStatus amp StatusFlags i R20UT0708EE0211 Rev 2 11 Page 4 291 Aug 01 2014 RENESAS RX210 Group 4 Library Reference Configure a Comparator B channel bool R_CPB_Create uint8_t data1 Channel selection uint16_t data2 Conf
540. when a privileged instruction is detected while in user mode Specify PDL_NO_FUNC if no callback function is required func2 The function to be called when an undefined instruction is detected Specify PDL_NO_FUNC if no callback function is required True Interrupt control e Please see the notes on callback function use in 86 Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed RPDL definitions include r pdl_intc h RPDL device specific definitions tinclude r pdl_definitions h Declaration of callback function void CallBackFunc void void func void Add a function to manage undefined instruction errors R_INTC_CreateExceptionHandlers PDL_NO_FUNC CallBackFunc R20UT0708EE0211 Rev 2 11 Page 4 22 Aug 01 2014 2tENESAS RX210 Group 4 Library Reference 6 R_INTC_ControlExtInterrupt Synopsis External interrupt control Prototype bool R_INTC_ControlExtinterrupt uint8_t data1 Pin selection uint32_t data2 Control Description Modifies the specified external interrupt data1 Choose the interrupt pin to be controlled PDL_INTC_IRQn n 0 to 7 or IRQn interrupt pin or PDL_INTC_NMI NMI interrupt pin data2 Select the controls If multiple selections are required use to sepa
541. where you wish RPDL for RX210 to be installed c my_project_folder Creating the destination directory c my_project_folder RPDL Copying the generic files Copying the files for little endian support 1 file s copied 1 file s copied Please enter a number to select the device pin package 48 Pins 64 69 Pins 80 Pins 100 Pins 144 145 Pins 4 Please enter a number to select the device MCU version Note there is only MCU version B in 69 Pins Please enter a number to select the device ROM size 1 64 to 512 KB 2 768 to 1000 KB 2 Finished Press any key to continue Depending upon the pin package option chosen you may also be asked for the MCU Version A B or C and the ROM Size Press any key to close the window Copy folder RPDL into the folder project workspace created Example X rpdl_lib_ test Note This copy utility generates a file based on your answers called r_pdl_configuration c This file will be included in your project so it is possible to manually edit the file if required to change the device specification However if changing the endian option then the copy utility must be used again to generate a new lib file R20UT0708EE0211 Rev 2 11 lt Page 1 5 ZNIES Aug 01 2014 RENES RX210 Group 1 Introduction 3 Include the new directory Use the key sequence Alt B R to open the RX Standard Toolchain window Select the C C tab Use the key sequence S to
542. wn 1 up Forn 3 b7 b6 b5 b4 b3 b2 b1 bO Detection Count Overflow Input capture compare match direction 0 V olplc B A 9 down 1 up Forn 4 b7 b6 b5 b4 b3 b2 b1 bO Detection Over or Fast nderfiow Input capture compare match irection 0 down 0 V 0 D C B A 1 up Forn 5 b7 b3 b2 b1 bO Detection Input capture compare match 0 W V U R20UT0708EE0211 Rev 2 11 Page 4 144 Aug 01 2014 RENESAS RX210 Group Description 2 2 Return value Category Reference Remarks R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference data3 For n 0 to 4 A pointer to where the TNCT register value shall be stored For n 5 A pointer to where the TNCTU register value shall be stored Specify PDL_NO_PTR if it is not required data4 For n 0 to 4 A pointer to where the TGRA register value shall be stored For n 5 A pointer to where the TNCTV register value shall be stored Specify PDL_NO_PTR if it is not required data5 For n 0 to 4 A pointer to where the TGRB register value shall be stored For n 5 A pointer to where the TNCTW register value shall be stored Specify PDL_NO_PTR if it is not required data6 For n 0 3 or 4 A pointer to where the TGRC register value shall be stored For n 5 A pointer to where the TGRU register value shall be stored Specify PDL_NO_PTR if it is not required data7 For n 0 3 or 4 A pointer to w
543. x_unit 42 9s 44 7s 67 1s J peux Widthmin Periodmin Widthmax_cHANNEL Periodimax_ CHANNEL Widthmax_unit Periodmax_ UNIT fmax Frcuxe 6 25 MHz 6 MHz 4 MHz 2 MIN_CHANNEL 5 96 Hz 5 7 Hz 3 81 Hz fin_uNit Sraya 0 0232 Hz 0 0224 Hz 0 0149 Hz If the requested period is not a multiple of the timer resolution the actual time period will be more than the requested time period The actual duty cycle will be less than the requested duty cycle if the resulting pulse width is not a multiple of the timer resolution A callback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS Page 4 164 RX210 Group Program example 4 Library Reference RPDL definitions include r pdl_tmr h RPDL device specific definitions include r pdl definitions h void func void Configure pin TMO1 for 500ns period 200ns pulse width R_TMR _CreatePeriodic PDL TMR TMR1 PDL TMR PERIOD PDL TMR OUTPUT HIGH 500E 9 200E 9 PDL_NO_FUNC PDL_NO_FUNC 0 5 Configure pin TMO1 for 5MHz frequency 60 duty cycle R_TMR _CreatePeriodic PDL_TMR_TMR1 PDL TMR FREQUENCY PDL TMR_OUTPUT_HIGH 5E6 60 PDL_NO_FUNC PDL_NO_FUNC 0 R20UT0708EE0211 Rev 2 11 Page 4 165 Aug 01 2014 RENESAS RX210 Group
544. xecuted by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed Page 4 150 RENESAS RX210 Group 4 Library Reference Program example RPDL definitions include r pdl poe h RPDL device specific definitions include r pdl definitions h void POEO handler void void func void Assign the callback function for pin POEO R_POE Create PDL POE IRQ HI Z 0 3 ENABLE POEO handler PDL_NO_FUNC 0x01 R20UT0708EE0211 Rev 2 11 Aug 01 2014 RENESAS Page 4 151 RX210 Group 4 Library Reference 3 R_POE Control Synopsis Prototype Description Return value Category Reference Control the Port Output Enable module bool R_POE_Control uint8_t data1 uint16_t data2 uint8_t data3 1 Control options Control options 1 Control options Change the state of output pins status flags and interrupt control data1 Manual high impedance control If multiple selections are required use to separate each selection All settings are optional Specify PDL_NO_DATA if no control is required e MTU channel high impedance control PDL_POE_MTU3_MTU4_HI_Z_ON or PDL_POE_MTU3_MTU4_HI_Z OFF PDL_POE_MTUO_HI_Z_ON or PDL_POE MTUO_HI_Z_ OFF Control the high impedance state of the MTU3 and MTU4 outputs Control
545. y PDL_NO_DATA PDL CGC SUB 32768 Configure main clock operation using a 20 0 MHz crystal ICLK 20 MHz PCLKD 20 MHz PCLKB 20 MHz FCLK 20 MHz BCLK not used BCLK pin not used R CGC Set PDL_CGC_CLK_MAIN PDL CGC_BCLK DISABLE PDL CGC MAIN RESONATOR 20E6 20E6 20E6 20E6 20E6 PDL_NO_DATA PDL_NO_DATA i Configure PLL operation The PLL will be set to 100 MHz ICLK 50 MHz PCLKD 50 MHz PCLKB 25 MHz FCLK 25 MHz BCLK 25 MHz BCLK pin 12 5 MHz R_CGC_Set PDL_CGC_CLK_PLL PDL CGC BCLK DIV 2 100E6 50E6 50E6 25E6 25E6 25E6 PDL_NO_DATA i R20UT0708EE0211 Rev 2 11 Page 4 8 Aug 01 2014 RENESAS RX210 Group 2 R_CGC_ Control Synopsis Prototype Description 1 2 R20UT0708EE0211 Rev 2 11 Aug 01 2014 4 Library Reference Modify the clock generation circuit operation bool R_CGC_Control uint8_t data1 Clock selection uint32_t data2 Clock control options uint8_t data3 1 Clock control options Modify the clock control registers data1 Clock source selection If no change is required specify PDL_NO_DATA e Clock source selection PDL_CGC_CLK_LOCO or Select the low speed on chip oscillator LOCO PDL_CGC_CLK_HOCO or high speed on chip oscillator HOCO PDL_CGC_CLK_MAIN or main clock oscillator PDL_CGC_CLK SUB _CLOCK or su
546. y on RSPI channel 0 PDL_DMAC_TRIGGER_CMPBO or Interrupt request from Comparator BO PDL_DMAC_TRIGGER_CMPB1 or Interrupt request from Comparator B1 PDL_DMAC_TRIGGER_IRQO or PDL_DMAC_TRIGGER_IRQ1 or PDL_DMAC_TRIGGER_IRQ2 or PDL_DMAC_TRIGGER_IRQ3 or PDL_DMAC_TRIGGER_ADC12 or Valid edge detected on pin IRQn n 0 to 3 Conversion completed on the 12 bit ADC unit PDL_DMAC_TRIGGER_ADC12 GBADI or Conversion completed on group B of the 12 bit ADC unit PDL_DMAC_TRIGGER_ELSR18l or Event link interrupt PDL_DMAC_TRIGGER_ELSR19I or Event link interrupt PDL_DMAC_TRIGGER_MTUO or PDL_DMAC_TRIGGER_MTU1 or PDL_DMAC_TRIGGER_MTU2 or PDL_DMAC_TRIGGER_MTU3 or PDL_DMAC_TRIGGER_MTU4 or PDL_DMAC_TRIGGER_TPUO or PDL_DMAC_TRIGGER_TPU1 or PDL_DMAC_TRIGGER_TPU2 or Input capture or compare match on TPU PDL_DMAC_TRIGGER_TPU3 or channel n n 0 to 5 PDL_DMAC_TRIGGER_TPU4 or PDL_DMAC_TRIGGER_TPU5 or PDL_DMAC_TRIGGER_SCIO_RX or PDL_DMAC_TRIGGER_SCI1_RX or PDL_DMAC_TRIGGER_SCI2_RX or PDL_DMAC_TRIGGER_SCI3_RX or PDL_DMAC_TRIGGER_SCI4_RX or PDL_DMAC_TRIGGER_SCI5_RX or PDL_DMAC_TRIGGER_SCI6_RX or PDL_DMAC_TRIGGER_SCI7_RX or PDL_DMAC_TRIGGER_SCI8_RX or PDL_DMAC_TRIGGER_SCI9_RX or PDL_DMAC_TRIGGER_SCI10_RX or PDL_DMAC_TRIGGER_SCI11_RX or PDL_DMAC_TRIGGER_SCI12_RX or PDL_DMAC_TRIGGER_SCIO_TX or PDL_DMAC_TRIGGER_SCI1_TX or Transmit buffer empty on SCI unit n PDL_DMAC_TRIGGER_SCI2_TX or n 0 to 12 PDL_DMAC_TRIGGER_SCI3_TX or PDL_DMAC_TRIGGER_SCI4_TX
547. y the interrupt processing function This means that no other interrupt can be processed until the callback function has completed R20UT0708EE0211 Rev 2 11 Page 4 83 Aug 01 2014 RENESAS RX210 Group 4 Library Reference Program example RPDL definitions include r pdl bsc h RPDL device specific definitions include r pdl definitions h Bus error handler void BusErrorFunc void void func void Select CS2 on pin P26 all address signals enable interrupts and register the callback function R_BSC_Create PDL BSC_CS2_P26 PDL NO DATA PDL NO DATA PDL BSC_ERROR_ILLEGAL ADDRESS ENABLE PDL BSC ERROR TIME OUT ENABLE BusErrorFunc 5 R20UT0708EE0211 Rev 2 11 Page 4 84 Aug 01 2014 RENESAS RX210 Group 3 R_BSC_CreateArea Synopsis Prototype Description 1 2 R20UT0708EE0211 Rev 2 11 Aug 01 2014 Configure an external bus area bool R_BSC_CreateArea uint8_t data1 Area selection uint16_t data2 uint8_t data3 RRCV cycles 4 Library Reference Configuration selection uint8_t data4 WRCV cycles uint8_t data5 CSPRWAIT cycles uint8_t data6 CSPWWAIT cycles uint8_t data7 CSRWAIT cycles uint8_t data8 CSWWAIT cycles uint8_t data9 CSROFF cycles uint8_t data10 uint8_t data11 uint8_t data12 uint8_t data13 uint8_t data14 uint8_t data15 u

RX210 Group Renesas Peripheral Driver Library User`s Manual

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