"user manual"
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1. Output SysAD 31 0 SysCmd 4 0 Input Kat too PValid PReq Output PMaster EValid EReq IntO to Int4 NMI Data Sheet U10116EJ6V0DS00 15 NEC uPD30200 30210 Clocking relationships Cycle 1 2 3 ii MasterClock Input SyncOut Output PClock Internal SClock Internal TClock Output SysAD Driven Output SysAD Received Input 16 Data Sheet U10116EJ6VODSO00 NEC 0200 30210 Power on reset timing MasterClock Input 64000 master clocks or more ColdReset tos Input tos 1 6 master clocks or more Reset toH Input tupsNote 2 DivMode 1 0 N Input SyncOut a Sha Output k ESSI Output Notes 1 In the uPD30200 xxx DivMode 2 0 in the uPD30210 xxx 2 In the uPD30200 100 and 30200 133 tps in the uPD30200 80 and 30210 xxx Data Sheet U10116EJ6VODS00 17 NEC PD30200 30210 Cold reset timing MasterClock Input ColdReset Input 64000 master clocks or more tos 16 master clocks or more Le Reset T Input SyncOut Undefined Output S TClock Undefined Output S ee ee eee i Software reset timing MasterClock Input ColdReset H tos Input 16 master clocks or more tos ms t gt Reset v Input SyncOut Output2. and external agent EValid External valid Signal indicating that external agent has transmitted valid address or data onto SysAD bus and valid command or data identifier onto SysCmd bus PValid Output Processor valid Signal indicating that processor has transmitted valid address or data onto SysAD bus and valid command or data identifier onto SysCmd bus EReq Input External request Signal used by external agent to request use of system interface PReq Output Processor request Signal used by processor to request use of system interface If the processor detects a protocol error this signal oscillates with the same frequency as SClock internal and the system interface hangs up PMaster Processor master Signal indicating processor controls system interface External OK Signal indicating that external agent can accept processor request Interrupt General purpose processor interrupt requests the input status of which can be confirmed by bits 14 through 10 of cause register Non maskable interrupt Interrupt request that cannot be masked ColdReset Cold reset Signal that initializes internal status of processor It can be made active inactive without synchronizing with the MasterClock Reset Input Reset Signal that generates reset exception without initializing internal status of processor MasterClock Input Master clock Clock input signal to pr
3. uPD30200GD 80 LBB uPD30200GD 100 MBB uPD30200GD 133 MBB uPD30210GD 133 MBB uPD30210GD 167 MBB ColdReset SysAD25 GND PMaster SysAD26 EReq SysCmd4 GND SysCmd0 DivMode1 Reset O SysCmd1 Voo GND SysAD22 SysAD21 GND SysAD20 VooP GNDP PLLCap0 PLLCap1 VopP GNDP Voo DivMode2 MasterClock GND TClock O O GNDO SyncOut O SysAD19 Q Voo 1 2 3 4 5 6 7 8 9 SysAD10 Into O SysAD9 GND O Voo O SysAD8 O SysAD7 JTMS O GND O O SysAD6 O SysAD5 Remark Pin in the uPD30210 xxx Data Sheet U10116EJ6V0DS00 NMI O GND JTCK O Inti O GND O Voo O 0200 30210 O GND O Int2 O SysAD27 O SysAD28 O O GND SysAD29 O EOK O SysAD30 O O GND O PValid O SysAD31 O O GND O PReq SysADO O O GND O SysADI O SysAD2 O O GND O SysAD3 JTDO SysAD4 JTDI O GND PIN NAMES ColdReset DivMode 1 0 Nete EOK ERea EValid Int 4 0 JTCK JTDI JTDO JTMS MasterClock NMI PLLCap 1 0 PMaster PRea PValid Reset Syncin SyncOut SysAD 31 0 SysCmd 4 0 TClock GND VppP GNDP NEC uPD30200 30210 Cold Reset Divide Mode External OK External Request External Valid Interrupt Reques
4. 11 20 MHz 60 MHz 20 MHz 1 3 1 DivMode 2 0 Vn4310 Example DivMode 2 0 MasterClock PClock TClock Ratio 000 26 7 MHz 133 MHz 26 7 MHz 1 51 001 22 2 MHz 133 MHz 22 2 MHz 1 6 1 010 66 7 MHz 167 MHz 66 7 MHz 2 5 2 011 33 3 MHz 100 MHz 33 3 MHz 1 31 100 33 3 MHz 133 MHz 33 3 MHz 1 41 101 Reserved 110 50 0 MHz 100 MHz 50 0 MHz 1 2 1 111 33 3 MHz 100 MHz 33 3 MHz 1 31 Note This setting is allowed with the 167 MHz model only With the 133 MHz model this setting is reserved After power application do not change the value of these pins otherwise the operation is not guaranteed PLLCap 1 0 PLL capacitor Connect capacitor to adjust internal PLL VooP PLL Voo Power supply for internal PLL GNDP PLL GND Ground for internal PLL Positive power supply pin Ground pin 8 Data Sheet U10116EJ6V0DS00 NEC 0200 30210 2 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Ta 25 C Parameter Conditions Ratings Supply voltage 0 5 to 4 0 Input voltageNete 0 5 to 0 3 Pulse of less than 10 ns 1 5 to 0 3 Operating case temperature 0 to 85 Storage temperature 65 to 150 Note The upper limit of the input voltage 0 3 is 4 0 V Cautions 1 Do not short circuit two or more outputs at the same time 2 Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parame
5. 3 0 to 3 5 V At 66 7 MHz Inputhete 3 At 33 3 MHz Input ete Parameter Conditions P P MIN MAX MIN MAX Data output delay timeNote 1 at 133 MHz operation at 167 MHz operation Data setup delay timeNote 1 tos Data hold delay timeNote 1 ton Clock rise timeNote 2 tcorise Clock fall timeNote 2 tcorall Clock high level widthNete 2 Clock low level widthNete 2 Notes 1 Applied to all interface pins 2 Applied to TClock pin 3 Master clock frequency example Load Coefficient Rating Parameter Symbol Conditions Unit Data Sheet U10116EJ6V0DS00 13 NEC PD30200 30210 Test Conditions SClock DE too All output pins 1 5V Test Load All output pins DUT C 50 pF Timing Charts Clock timing lMCkHigh 0 8 MasterClock 0 2 MCkLow tuorall tcoHigh 0 8 TClock 0 2 tcoLow tcorise tcorall 14 Data Sheet U10116EJ6V0DS00 NEC Clock jitter 0200 30210 MasterClock 0 5 Voo tucitter Les tMCitter TClockNote Note If SyncOut and Syncin are connected with the shortest path the point of TClock 50 is the point of MasterClock 50 Remark match the MasterClock edge make the load capacitance of the Syncln SyncOut path the same as that of TClock System interface edge timing too SysAD 31 0 SysCmd 4 0
6. TClock Output 18 Data Sheet U10116EJ6VODSO00 NEC 0200 30210 3 PACKAGE DRAWING 120 PIN PLASTIC QFP 28x28 detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0 15 mm of A 32 0 0 3 its true position T P at maximum material condition 28 0 0 2 28 0 0 2 32 0 0 3 2 4 2 4 0 08 0 37 307 0 15 0 8 T P 2 0 0 2 0 8 0 2 cje 0 08 0 1 70 07 M N 0 1 P 3 2 Q 0 1 0 1 R S 5 5 3 3 0 2 P120GD 80 LBB 2 Data Sheet U10116EJ6VODSO00 19 NEC uPD30200 30210 4 RECOMMENDED SOLDERING CONDITIONS The products should be soldered and mounted under the following recommended conditions For the details of the recommended soldering conditions refer to the document Semiconductor Device Mounting Technology Manual C10535E For soldering methods and conditions other than those recommended below contact your NEC representa tive Table 4 1 Surface Mounting Type Soldering Conditions uPD30200GD 80 LBB 120 plastic QFP 28 28 mm uPD30200GD 100 MBB 120 pin plastic 28 x 28 mm uPD30200GD 133 MBB 120 pin plastic 28 x 28 mm uPD30210GD xxx MBB 120 pin plastic 28 x 28 mm Recommended Soldering Method Soldering Conditi oldering Metho olderin
7. only Remark The operating supply current is almost proportional to the operating clock frequency Data Sheet U10116EJ6V0DS00 9 NEC uPD30200 30210 Capacitance Ta 25 C 0 V Input capacitance fc 1 MHz Output capacitance Unmeasured pins returned to 0 V AC Characteristics Tc 0 to 85 C 3 3 0 3 V 0200 80 30200 100 Tc 0 to 85 C 3 0 to 3 5 V uPD30200 133 30210 xxx Clock Parameters 1 uPD30200 xxx 0200 80 uPD30200 100 uPD30200 133 MIN MAX MIN MAX MIN MAX Parameter Conditions Master clock high level width Master clock low level width twcktow Master clock frequencyNote DivMode 1 1 DivMode 1 2 DivMode 2 3 DivMode 1 3 DivMode 1 4 Master clock cycle DivMode 1 1 DivMode 1 2 DivMode 2 3 DivMode 1 3 DivMode 1 4 Clock jitter tMCJitter Master clock rise time tMCRise Master clock fall time tmcrall JTAG clock cycle tuTaGcKP 4 x tmckP 4 x tmckP 4 x tmckP Note The operation of the internal PLL of the uPD30200 xxx is guaranteed The RP mode is supported only by uPD30200 80 and 30200 100 and guaranteed when the master clock frequency is 40 MHz or higher 10 Data Sheet U10116EJ6VODSO00 NEC 0200 30210 2 uPD30210 xxx uPD30210 133 30210 167 Pa
8. 0200 133 1 8 W TYP at 100 MHz operation 2 4 W TYP at 133 MHz operation e uPD30210 xxx 1 9 W TYP at 133 MHz operation 2 4 W TYP at 167 MHz operation Supply voltage 3 3 0 3 V uPD30200 80 30200 100 3 0 to 3 5 V uPD30200 133 30210 xxx Unless otherwise specified the Vr4300 uPD30200 is treated as the representative model throughout this document The information in this document is subject to change without notice Before using this document please confirm that this is the latest version Notall devices types available in every country Please check with local NEC representative for availability and additional information Document No U10116EJ6VODSO0 6th edition The mark x shows major revised points Date Published December 1999 CP K Corporation 1995 1998 Printed in Japan MIPS Technologies Inc 1994 NEC uPD30200 30210 APPLICATIONS Embedded controllers Page printer controllers Amusement game machines etc ORDERING INFORMATION Part Number Package Maximum Internal Operating Frequency MHz uPD30200GD 80 LBB 120 pin plastic QFP 28 x 28 mm 80 LP D30200GD 100 MBB 120 pin plastic QFP 28 x 28 mm 100 uPD30200GD 133 MBB 120 pin plastic QFP 28 x 28 mm 133 uPD30210GD 133 MBB 120 pin plastic QFP 28 x 28 mm 133 uPD30210GD 167 MBB 120 pin plastic QFP 28 x 28 mm 167 2 Data Sheet U10116EJ6V0DS00 NEC PIN CONFIGURATION Top View 120 pin plastic 28 x 28 mm
9. AUTION AGAINST ESD FOR SEMICONDUCTORS Note Strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it once when it has occurred Environmental control must be adequate When it is dry humidifier should be used It is recommended to avoid using insulators that easily build static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with semiconductor devices on it HANDLING OF UNUSED INPUT PINS FOR CMOS Note No connection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins itis possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to Vop or GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the u
10. DATA SHEET MOS INTEGRATED CIRCUIT uPD30200 30210 VR4300 M Vn4305 M VR4310 64 BIT MICROPROCESSOR NEC The uPD30200 100 30200 133 Vr4300 30200 80 Vr4305 and 30210 Vn4310 are high performance 64 bit RISC Reduced Instruction Set Computer type Vr Series microprocessors employing the RISC architecture developed by MIPS Technologies Inc The 4300 Vn4305 and 4310 are intended for the high performance embedded device field and have 32 bit system interface buses Detailed function descriptions are provided in the following user s manual Be sure to read this manual before designing e Vn4300 Vr4305 Vn4310 User s Manual U10504E FEATURES Employs 64 bit RISC MIPS architecture High speed operation processing 5 stage pipeline processing High speed execution of integer and floating point operations 48 SPECint92 36 SPECfp92 106 MIPS at 80 MHz operation uPD30200 80 60 SPECint92 45 SPECfp92 131 MIPS at 100 MHz operation uPD30200 100 80 SPECint92 60 SPECfp92 177 MIPS at 133 MHz operation uPD30200 133 uPD30210 133 100 SPECint92 75 SPECfp92 221 MIPS at 167 MHz operation uPD30210 167 e Instruction set compatible with Vr40007M Series conforms to MIPS I II III On chip cache memory Instruction 16 Kbytes Data 8 Kbytes 32 bit address data multiplexed bus facilitating system design Low power consumption uPD30200 80 1 5 W TYP at 80 MHz operation uPD30200 100 3
11. ax 02 2719 5951 NEC do Brasil S A Electron Devices Division Rodovia Presidente Dutra Km 214 07210 902 Guarulhos SP Brasil Tel 55 11 6465 6810 Fax 55 11 6465 6829 J99 1 23 NEC uPD30200 30210 Exporting this product or equipment that includes this product may require a governmental license from the U S A for some countries because this product utilizes technologies limited by the export control regulations of the U S A The information in this document is subject to change without notice Before using this document please confirm that this is the latest version No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation NEC Corporation assumes no responsibility for any errors which may appear in this document NEC Corporation does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device No license either express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Corporation or others Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these circuits software and infor
12. g Conditions Condition Symbol Infrared reflow Package peak temperature 235 C Time 30 seconds max at 210 C or higher IR35 367 2 Count Two times or less Exposure limit 7 days after that prebake at 125 C for 36 hours Package peak temperature 215 C Time 40 seconds max at 200 C or higher VP15 367 2 Count Two times or less Exposure limit 7 days after that prebake at 125 C for 36 hours Wave soldering Solder bath temperature 260 C max Time 10 seconds max WS60 367 1 Count Once Preheating temperature 120 C max package surface temperature Exposure limit 7 daysNete after that prebake at 125 C for 36 hours Partial heating Pin temperature 300 C max Time 3 seconds max per pin row Note After opening the dry pack store it at 25 C or less and 65 RH or less for the allowable storage period Caution Do not use different soldering methods together except for partial heating 20 Data Sheet U10116EJ6V0DS00 NEC 0200 30210 APPENDIX DIFFERENCES BETWEEN THE Vn4300 Vn4305 Vn4310 AND Vn41007M Parameter System bus Write data transfer Two buses D Dxx Four buses D Dx Dxx Dxxx Initial value setting pins at reset time DivMode 1 0 Can be set on power application only DivMode 2 0 Can be set on power application only BigEndian Div2 HizParity Block write access Sequential ordering Subblock ordering State afte
13. mation in the design of the customer s equipment shall be done under the full responsibility of the customer NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits software and information While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices the possibility of defects cannot be eliminated entirely To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device customers must incorporate sufficient safety measures in its design such as redundancy fire containment and anti failure features NEC devices are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application The recommended applications of a device depend on its quality grade as indicated below Customers must check the quality grade of each device before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster system
14. nused pins must be judged device by device and related specifications governing the devices STATUS BEFORE INITIALIZATION OF MOS DEVICES Note Power on does not necessarily define initial status of MOS device Production process of MOS does not define the initial operation status of the device Immediately after the power source is turned ON the devices with reset function have not yet been initialized Hence power on does not guarantee out pin levels I O settings or contents of registers Device is not initialized until the reset signal is received Reset operation must be executed immediately after power on for devices having reset function The related documents indicated in this publication may include preliminary versions However preliminary versions are not marked as such VR4000 4100 Vn4300 Vr4305 Vn4310 and Vn Series are trademarks of NEC Corporation MIPS is a trademark of MIPS Technologies Inc 22 Data Sheet U10116EJ6V0DS00 NEC 0200 30210 Regional Information Some information contained in this document may vary from country to country Before using any NEC product in your application please contact the NEC office in your country to obtain a list of authorized representatives and distributors They will verify Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications for example specificati
15. ocessor TClock Output Transmit receive signal clock This is the basic clock for the system interface and is synchronized with the MasterClock SyncOut Output Synchronization clock output Output of synchronization clock Syncin Input Synchronization clock input Input of synchronization clock JTDI Input JTAG data input Input of JTAG serial data Data Sheet U10116EJ6V0DS00 7 NEC uPD30200 30210 Pin Name Function JTDO Output JTAG data output Output of JTAG serial data JTMS Input JTAG command Indicates that input serial data is command data JTCK Input JTAG clock input Input of JTAG serial clock If the JTAG interface is not used set it to low level DivMode Input Mode setting Sets frequency ratio of MasterClock TClock and PClock DivMode 1 0 4300 Example DivMode 1 0 MasterClock PClock TClock Ratio 00 33 3 MHz 133 MHz 33 3 MHz 1 4 1 Note 1 01 66 7 MHz 100 0MHz 66 7 MHz 2 3 2 Note 2 10 50 0 MHz 100 0MHz 50 0 MHz 1 2 1 11 33 3 MHz 100 0MHz 33 3 MHz 1 3 1 Notes 1 This setting is allowed with the 133 MHz model only With the 100 MHz model this setting is reserved This setting is allowed with the 100 MHz model only With the 133 MHz model this setting is reserved DivMode 1 0 Vn4305 Example DivMode 1 0 MasterClock PClock TClock Ratio 00 66 7 MHz 66 7 MHz 66 7 MHz 1 1 1 01 Reserved 10 40 MHz 80 MHz 40 MHz 1 2 1
16. ons for third party tools and components host computers power plugs AC supply voltages and so forth Network requirements In addition trademarks registered trademarks export restrictions and other legal issues may also vary from country to country NEC Electronics Inc U S Santa Clara California Tel 408 588 6000 800 366 9782 Fax 408 588 6130 800 729 9288 NEC Electronics Germany GmbH Duesseldorf Germany Tel 0211 65 03 02 Fax 0211 65 03 490 NEC Electronics UK Ltd Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Italiana s r l Milano Italy Tel 02 66 75 41 Fax 02 66 75 42 99 NEC Electronics Germany GmbH Benelux Office Eindhoven The Netherlands Tel 040 2445845 Fax 040 2444580 NEC Electronics France S A Velizy Villacoublay France Tel 01 30 67 58 00 Fax 01 30 67 58 99 NEC Electronics France S A Spain Office Madrid Spain Tel 91 504 2787 Fax 91 504 2860 NEC Electronics Germany GmbH Scandinavia Office Taeby Sweden Tel 08 63 80 820 Fax 08 63 80 388 Data Sheet U10116EJ6V0DS00 NEC Electronics Hong Kong Ltd Hong Kong Tel 2886 9318 Fax 2886 9022 9044 NEC Electronics Hong Kong Ltd Seoul Branch Seoul Korea Tel 02 528 0303 Fax 02 528 4411 NEC Electronics Singapore Pte Ltd United Square Singapore 1130 Tel 65 253 8311 Fax 65 250 3583 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 2719 2377 F
17. r final data write Final data retained in transfer rate setting End of access Non cache high speed write Provided Provided Set with a register Corresponding instructions MIPS I II and III instruction sets MIPS 1 Il instruction sets plus sum of products arithmetic Cache memory Data protection Word parity instructions byte parity data JTAG interface Provided None SyncOut SynclIn path Provided None Clock interface Input vs internal multiplication rate 1 5Note t 2 3 ANote 2 2 2 5Note3 3 5 6 4 Internal vs bus frequency division rate 1 5Nete 1 2 3 ANote 2 2 2 5Note3 3 5 6 1 2 Power mode Low power mode Pipeline system bus operated at a quarter of the normal rateNote4 None None Wait mode None Three types PRId register Notes 1 this setting is reserved 2 The 4 times frequency setting is allowed with the 133 MHz model only With the 100 MHz model this setting is reserved 3 The 2 5 times frequency setting is allowed with the 167 MHz model only With the 133 MHz model this setting is reserved 4 Not supported by the 133 MHz model of the Vn 4300 Imp 0x0B Data Sheet U10116EJ6V0DS00 Imp 0x0C 1 5 times frequency setting is allowed with the 100 MHz model only With the 133 MHz model 21 NEC uPD30200 30210 NOTES FOR CMOS DEVICES PREC
18. rameter Conditions Master clock high level width Master clock low level width twcktow Master clock frequencyNote DivMode 2 0 DivMode 2 5 DivMode 3 0 DivMode 4 0 DivMode 5 0 DivMode 6 0 Master clock cycle DivMode 2 0 DivMode 2 5 DivMode 3 0 DivMode 4 0 DivMode 5 0 DivMode 6 0 Clock jitter tMCJitter Master clock rise time tMCRise Master clock fall time tmcrall JTAG clock cycle tuTaGcKP 4 x tvck 4 x luce Note The operation of the internal PLL of the uPD30210 xxx is guaranteed The RP mode is not supported by the uPD30210 xxx Data Sheet U10116EJ6VODS00 11 NEC PD30200 30210 System Interface Parameters 1 UPD30200 80 Tc 0 to 85 C Von 3 3 0 3 V At 66 7 MHz Input At 40 MHz Inputhot 5 At 33 3 MHz Input Parameter Conditions P P P MIN MAX MIN MAX MIN MAX Data output delay timeNote 1 Data setup delay timeNote 1 tos Data hold delay timeNote 1 ton Clock rise timeNote 2 tcorise Clock fall timeNote 2 tcorall Clock high level widthNote 2 Clock low level widthNete 2 tcotow Notes 1 Applied to all interface pins 2 Applied to TClock pin 3 Master clock frequency example 2 uPD30200 100 Tc 0 to 85 C 3 3 0 3 V At 66 7 MHz At 62 5 MHz Inpu
19. s anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems life support systems or medical equipment for life support etc The quality grade of NEC devices is Standard unless otherwise specified in NEC s Data Sheets or Data Books If customers intend to use NEC devices for applications other than those specified for Standard quality grade they should contact an NEC sales representative in advance M7 98 8
20. t JTAG Clock Input JTAG Data In JTAG Data Out JTAG Command Signal Master Clock Non maskable Interrupt Request Phase Locked Loop Capacitance Processor Master Processor Request Processor Valid Reset Synchronization Clock Input Synchronization Clock Output System Address Data Bus System Command Data ID Bus Transmit Clock Power Supply Ground for PLL GND for PLL Note n the uPD30200 xxx DivMode 2 0 in the uPD30210 xxx Data Sheet U10116EJ6V0DS00 NEC 0200 30210 INTERNAL BLOCK DIAGRAM Data address Control Master clock Clock System interface generator Instruction cache Data cache Execution unit Instruction address Pipeline control Data Sheet U10116EJ6VODSO00 5 NEC uPD30200 30210 TABLE OF CONTENTS 1 PIN FOUNO T O NS 2 7 2 ELECTRICAL SPECIFICATIONS 9 3 peccddbuuujcm M 19 4 RECOMMENDED SOLDERING CONDITIONS 20 APPENDIX DIFFERENCES BETWEEN THE Vn4300 Vr4305 4310 AND VR4100 21 6 Data Sheet U10116EJ6V0DS00 NEC 1 PIN FUNCTIONS Pin Name SysAD 31 0 0200 30210 Function System address data bus 32 bit bus for communication between processor and external agent SysCmd 4 0 System command data ID bus 5 bit bus for communication of commands and data identifiers between processor
21. tNe4 At 50 MHz Inputhot At 33 3 MHz Input Parameter Condition P P MIN MIN MAX Data output delay timeNote 1 Data setup delay timeNote 1 tos Data hold delay timeNote 1 ton Mode data setup timeNote 2 tups Clock rise timeNote 3 tcorise Clock fall timeNote 3 tcorall Clock high level widthNote 3 Clock low level widthNete 3 Notes 1 Applied to all interface pins except DivMode 1 0 pin 2 Applied to DivMode 1 0 pin 3 Applied to TClock pin 4 Master clock frequency example 12 Data Sheet U10116EJ6VODSO00 NEC 0200 30210 3 uPD30200 133 Tc 0 to 85 C Von 3 0 to 3 5 V At 66 7 MHz Input ele At 44 4 MHz Input ele At 33 3 MHz Inputhote Parameter Conditions i P MIN MAX MIN MAX MIN MAX Data output delay timeNote 1 Data setup delay timeNote1 tos Data hold delay timeNote 1 ton Mode data setup timeNote2 tuos Clock rise timeNote 3 tcorise Clock fall timeNote 3 tcorall Clock high level widthNete 3 Clock low level widthNote 3 Notes 1 Applied to all interface pins except DivMode 1 0 pin 2 Applied to DivMode 1 0 pin 3 Applied to TClock pin 4 Master clock frequency example 4 uPD30210 xxx Tc 0 to 85 C
22. ter That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded The specifications and conditions shown in the following DC Characteristics and AC Characteristics are the range within which the product can normally operate and the quality can be guaranteed DC Characteristics Tc 0 to 85 C Voo 3 3 0 3 V uPD30200 80 30200 100 Tc 0 to 85 C 3 0 to 3 5 V uPD30200 133 30210 xxx Parameter Conditions lt Output voltage high 400 uA Output voltage highNote 1 lou 400 uA Output voltage low lo 2 5 mA 0 4 Input voltage high 0 3 Input voltage low 0 8 Pulse of less than 10 ns 40 8 Input voltage highNote 2 Von 0 3 Input voltage lowNote 2 0 2Voo Pulse of less than 10 ns 0 2Vpp Supply current uPD30200 at 80 MHz operation 0 60 at 100 MHz operation 0 67 at 133 MHz operation 0 90 30210 at 133 MHz operation 0 69 Pr re gt Se lt lt lt lt lt lt lt lt lt at 167 MHz operation 0 85 Input leakage current high 10 Input leakage current low 10 Output leakage current high Output leakage current low Notes 1 Applied to the TClock pin 2 Applied to the MasterClock pin
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