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Elan(TM)SC520 Microcontroller Data Sheet

1. a 1 27 BSC 0 635 _ a ALL ROWS AND COLUMNS BSC BOTTOM VIEW 16 038 BGA388 2 ET118 10 26 98 Iv Elan SC520 Microcontroller Data Sheet ADVANCE Circuit Board Layout Considerations There are two basic ways to set up a BGA ball pad sol der mask defined and solder pad defined Solder mask defined is when the solder mask opening is smaller than the copper pad so the solder surface is defined by the solder mask rather than the copper pad Solder pad defined is when the copper pad is smaller than the solder mask so the solder surface is defined by the copper pad A problem can occur when you mix these two methods For example if the chip is solder pad defined and the 0 80 mm INFORMATION Copper Pad Exposed Copper Solder Mask Covered Copper Opening Top View of BGA Pad Solder Mask tA J 3600 popper Ea Printed Circuit Board board is pad defined then a problem can occur where there is more surface area on the board making contact than on the part itself When the part heats and cools a different amount of stress is placed on the chip than on the board because there is more surface area sol dered on the board and the chip can warp The pad definition on the board should match the chip The lanSC520 microcontroller is solder mask de fined so the circuit board design should be solder mask defined with a sold
2. P lcc Voc The board type is described in the standards document entitled Thermal Test Chip Guideline Wire Bond Type Chip at www jedec org On the home page click on the link Free Standards and Docs and then click on the document link JESD51 4 under JEDEC PUBLICATIONS Ty Tc P gt Ty Ta P where Oja Thermal r esistance from junction to ambient Thermal resistance from junction to case Thermal resistance from case to ambient Ty Junction te TA Ambient te mperature mperature Case temperature P Power in Watts Power supply current in mA Figure 24 Thermal Characteristics Equations Elan SC520 Microcontroller Data Sheet 57 ADVANCE INFORMATION SWITCHING CHARACTERISTICS AND WAVEFORMS The AC switching specifications provided in the AC characteristics tables that follow consist of output de lays input setup requirements and input hold require ments AC specifications measurement is defined by the fig ures that follow each timing table All timings are refer enced to 1 5 V unless otherwise specified Key to Switching Waveforms Output delays are specified with minimum and maxi mum limits measured as shown The minimum delay times are hold times provided to external circuitry Input setup and hold times are specified as minimums defining the smallest accept
3. Serial Ports DSR2 A 2 Elan SC520 Microcontroller Data Sheet ADVANCE INFORMATION Table 15 Multiplexed Signal Trade Offs Continued Signal You Want Signal You Give Up Ping Clocks CLKTEST CLKTIMER CLKTIMER Timers CLKTEST PITGATE2 TMRINO 1 TMROUTO TMROUT1 System Test CF_DRAM WBMSTR2 CF_ROM_GPCS WBMSTRO DATASTRB WBMSTR1 WBMSTRO CF_ROM_GPCS WBMSTR1 DATASTRB WBMSTR2 CF_DRAM Configuration Pins Pinstraps See Configuration on page 26 Programmable I O GPALE PIO1 GPBHE PIO2 GPRDY PIOS GPAEN 4 GPTC PIO5 GPDRQS 6 GPDRQ2 PIO7 GPDRQ1 PIO8 GPDRQ0 PIO9 GPDACK3 PIO10 GPDACK2 PIO11 GPDACK1 PIO12 GPDACKO 1 GPIRQ10 14 GPIRQ9 PIO15 GPIRQ8 PIO16 GPIRQ7 PIO17 GPIRQ6 PIO18 GPIRQ5 PIO19 GPIRQ4 PIO20 GPIRQ3 21 GPIRQ2 PIO22 GPIRQ1 PIO23 GPIRQO 1024 GPDBUFOE 25 GPIOCS16 PIO26 GPMEMCS16 PIO27 GPCS0 lanTMSC520 Microcontroller Data Sheet 3 AMD ADVANCE INFORMATION Table 16 PlOs Sorted by PIO Number PIO Default Multiplexed Pin Configuration Function Signal Following Sy
4. t gt 4 12 gt r 17 gt 13 gt SSI_CLK 14 14 5 SSI DI ig gt lie lig 551 DO p Notes Asserted on rising edge sampled on falling edge Figure 38 SSI Timing 72 Elan SC520 Microcontroller Data Sheet ADVANCE INFORMATION AMD JTAG Timing Advance Information Parameter Description Min JTAG TRST active pulse width period High time Low time TMS JTAG_TDI setup time JTAG_TMS JTAG_TDI hold time JTAG_TDO delay Input pin setup time Input pin hold time Output pin delay lt u JTAG TRST 1 4 12 gt lt gt lt 4 gt JTAG_TCK r 4 5 6 JTAG_TMS 4 15 6 tz JTAG_TDO gt Input Pin Output Pin Figure 39 JTAG Boundary Scan Timing Elan SC520 Microcontroller Data Sheet 73 ADVANCE APPENDIX A PIN TABLES This appendix contains pin tables for the ElanSC520 microcontroller Several different tables are included with the following characteristics m Multiplexed signal tradeoffs Table 15 on page 2 Programmable I O pins ordered PIO pin number and multiplexed signal name respectively including a column showing pin configurations following system reset Table 16 on page A 4 and Table 17 on page A 5 m Pin summary showing
5. 1 Pin List Summary Table Column Definitions A 6 Appendix B Physical Dimensions eee oN ace B 1 xu LE B 1 i M MM MT B 2 Circum Board Layout Considerations s ote oun loser B 3 Appendix Customer Support acta cane tac d eene dede C 1 denen elec deine undeletion C 2 Additional C 2 Customer Development Platform cia kue C 2 Third Party Development Support Products C 2 Gustomer Service C 3 Hotline and World Wide Web C 3 Corporate Applications Holline sss C 3 World Wide Web Home Page n De Son ee C 3 Documentation and a C 3 C 3 ED a aa PE Index 1 LIST OF FIGURES Figure 1 Elan SC520 Microcontroller Block Diagram 29 Figure 2 Elan SC520 Microcontroller Based Smart Residential Gateway Reference Design m 34 Figure 3 Elan SC520 Microcontroller Based
6. O O O O O r rrir r r 6 mA 30 pF AMDebug Interface BR TC CMDACK STOP TX TRIG TRACE System Test DRAM W24 PD Latched 6 mA 30 pF WBMSTR2 CFG2 Elan SC520 Microcontroller Data Sheet A 13 Signal Name Alternate Function Pinstrap CF_ROM_GPCS WBMSTRO ADVANCE INFORMATION Table 19 Pin List Summary Continued Termination Latched Max Load pF DATASTRB WBMSTR1 CFG1 Timers Latched PITGATE2 GPCS3 PITOUT2 CFG3 Latched TMRINO GPCS5 TMRIN1 GPCS4 TMROUTO GPCS7 TMROUT1 GPCS6 Power and Ground BBATSEN Latched GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Elan SC520 Microcontroller Data Sheet ADVANCE INFORMATION Table 19 Pin List Summary Continued Signal Name Alternate Function Termination Pinstrap Max Load pF Elan SC520 Microcontroller Data Sheet A 15 Signal Name Alternate Function Pinstrap
7. Elan SC520 Microcontroller Integrated 32 Bit Microcontroller with PC AT Compatible Peripherals PCI Host Bridge and Synchronous DRAM Controller DISTINCTIVE CHARACTERISTICS m Industry standard Am5 86 CPU with floating point unit FPU and 16 Kbyte write back cache 100 MHz and 133 MHz operating frequencies Low voltage operation core Voc 2 5 V 5 V tolerant I O 3 3 V output levels m E86 family of x86 embedded processors Part of a software compatible family of microprocessors and microcontrollers well supported by a wide variety of development tools Integrated PCI host bridge controller leverages standard peripherals and software 33 MHz 32 bit PCI bus Revision 2 2 compliant High throughput 132 Mbyte s peak transfer Supports up to five external PCI masters Integrated write posting and read buffering for high throughput applications m Synchronous DRAM SDRAM controller Supports 16 64 128 and 256 Mbit SDRAM Supports 4 banks for a total of 256 Mbytes Error Correction Code provides system reliability Buffers improve read and write performance m AMDebug technology offers a low cost solution for the advanced debugging capabilities required by embedded designers Allows instruction tracing during execution from the Am5 86 CPU s internal cache Uses an enhanced JTAG port for low cost debugging Parallel debug port for high speed data exchange du
8. ate 71 Figure ao ESSI TII A Aka Sa EA E 72 Figure 39 JTAG Boundary Scan Timing 73 Figure 40 BGA Ball Layout ctetu Lire nhi eb hunu kasqa B 3 LIST OF TABLES Table 1 Signal Descriptions Table 2 0 004004 4 16 Table 2 detur 17 Table 3 Glok Jitter Specifications e sett ere a Seta 40 Table 4 Clock Startup and Lock Times 40 Table 5 Analog VCC _ Specifications 40 Table 6 PLL1 Loop Filter Components ore oet tee 40 Table 7 Timing Error as It Translates to Clock 41 Table 8 32 768 kHz Crystal Specifications o cu rbi us 42 Table 9 33 MHz Crystal Specifications 2 2 eene St cha uae 42 Table 10 Voltage Monitor Component Specifications 46 Table 11 Device Power Dissipation aer IRE 56 Table 12 ANLG and Power Dissipation 56 Table 13 Thermal R
9. _ 9 d RST oe Figure 30 Internal System Reset Timing Elan SC520 Microcontroller Data Sheet ADVANCE INFORMATION AMD ROM Timing Advance Information Parameter Description Min GPA25 GPAA chip select setup before ROMBUFOE ROMRD GPAS3 GPAO active GPA25 GPAA chip select active pulse width read access Read data valid required from ROMRD and ROMBUFOE non page mode access Read data valid from GPA3 GPAO page mode access Read data hold from address chip select ROMRD and ROMBUFOE GPA25 GPAQ chip select hold time from ROMBUFOE read access ROMBUFOE ROMRD read recovery time GPAS GPAO valid first access GPA3 GPAO valid time non page mode access valid time page mode access GPA25 GPAQ chip select setup to ROMBUFOE FLASHWR active GPA25 GPAO valid chip select active pulse width write access Write data valid setup to ROMBUFOE FLASHWR GPA25 GPAQ chip select hold time from ROMBUFOE FLASHWR write access Write data hold time from ROMBUFOE FLASHWR write access ROMBUFOE FLASHWR write recovery time Notes 1 Chip Select includes BOOTCS ROMCS1 and ROMCS2 2 Pews represents the programmable first wait state timing parameter in the ROM controller register for the corresponding ROM chip select 3 The value of 30 corresponds to the 33 MHz crystal freque
10. Pin List Summary on page A 7 has a column named Max Load pF This column describes the specification load presented to the specific pin when testing was performed to generate the timing specification docu mented in the AC Characteristics section of this data sheet If the capacitive load on GPAO is 70 pF then a typical rise time is 6 5 ns From Figure 18 the same load gives a typical fall time of 7 ns Elan SC520 Microcontroller Data Sheet 51 ADVANCE INFORMATION Typical 0 20 40 60 80 100 120 pF Figure 15 Drive 6 mA Rise Time 35 30 Worst Case 25 20 E __ gt 15 10 5 0 0 20 40 60 80 100 120 pF Figure 16 WO Drive 6 mA Fall Time 52 Elan SC520 Microcontroller Data Sheet ns ns ADVANCE INFORMATION Worst Case Typical 20 40 60 80 100 pF Figure 17 Drive 12 mA Rise Time 120 Worst Case Typical 20 40 60 80 100 pF Figure 18 Drive 12 mA Fall Time Elan SC520 Microcontroller Data Sheet 120 53 54 ns ns ADVANCE INFORMATION Worst Case m 0 20 40 60 80 100 120 pF Figure 19 Drive 24 mA Rise Time Worst Case Typical T T T T T 0 20 40 60 80 100 120 pF Figure 20 Drive 24 mA Fall Time Elan SC520 Microcontroller Data Sheet ADVANC
11. 138 2 138 MHz DEVICE NUMBER DESCRIPTION ElanSC520 integrated 32 bit microcontroller with PC AT compatible peripherals PCI host bridge and synchronous DRAM controller Valid Combinations Valid Combinations Valid combinations list configurations planned to be ElanSC520 100 supported in volume for this device Consult the ElanSC520 133 local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations 2 Elan SC520 Microcontroller Data Sheet ADVANCE INFORMATION AMD TABLE OF CONTENTS Distinctive haracteristi6S ss nd tu de Ud HOS 1 E C ER 1 Ordering Information 2 Logic Diagram by Interface m 6 Logic Diagram by Default Pin Function avast enema 7 Connection hte tta o e oct tatu eet d Been bd 8 Pin Designations c eode c REO Re i t eet eh 10 Pin Designations Pin Number ota Quen ate d eee a dica 11 Pin Designations Pin Name 13 Signal DESEMPUOMS s ee estan eener Ere Ea 16 Architectural OVerVieW 28 Industry Sta
12. GPIRQ4 GPIRQS5 GPIRQ10 GPDACK2 GPTC CS16 FOE AE NC SIN1 27 23 020 PIO17 014 9 6 NC DCD2 GPCSO GPIRQO GPIRQ3 GPIRQ6 9 GPDACK3 GPDRQ2 GPAEN GPALE AF NC SOUT1 029 PIO28 1022 21 PIO16 PIO15 PIO8 PIO7 2 PIO1 NC 0582 CTS2 GPIRQ1 GPIRQ2 GPIRQ7 GPIRQS GPDRQO GPDRQ1 GPRDY GPBHE 1 2 3 4 5 6 7 8 9 10 11 12 13 Elan SC520 Microcontroller Data Sheet lt lt m gt Z XX x AA AB AC AD AE AF lt C m gt Z r XX AD AE AF ADVANCE CONNECTION DIAGRAM Continued 388 Pin Plastic BGA Package INFORMATION Top View 14 15 16 17 18 19 20 21 22 23 24 25 26 MD7 MD23 MD9 MD25 MD11 MD27 MD28 MD13 MD14 MD30 MD31 GND_ANLG VCC_RTC MD22 MD8 MD24 MD10 MD26 CLK MD12 MD29 GPA18 MD15 51 BBATSEN MEMOUT RSTLD3 GPCS1 GPA20 GPD13 GPIOWR GPD14 GPMEMWR GPA21 PWRGOOD GPA19 NC 52 GPA15 MECCO MECC4 RSTLD5 RSTLD6 RSTLD4 GPCS2 RSTLDO GPD12 VCC GPD15 CORE VCC CORE PRGRESETVCC l O NC GPA16 5 RSTLD1 NC GPA17 WEB SWEA RSTLD2
13. Table 3 Clock Jitter Specifications Clock Name Clock Frequency Min Nominal Max 1 1882 MHz 828 3 ns 840 9 ns 853 5 ns 18 432 MHz 53 44 ns 54 25 ns 55 07 ns 66 666 MHz 14 775 ns 15 0 ns 15 225 ns Table 4 Clock and Lock Times Clock Source 32 768 kHz Oscillator 33 MHz Oscillator PLL1 1 47456 MHz PLL2 36 864 MHz PLL3 66 MHz Table 5 Analog VCC VCC_ANLG Parameter Peak to Peak Noise on VCC_ANLG VCC_ANLG Voltage Level VCC_ANLG Current Table 6 PLL1 Loop Filter Parameter 0 009 uF m CTI 0 0009 0 001 uF 0 0011 4 465 4 7 kQ 4 935 40 Elan SC520 Microcontroller Data Sheet ADVANCE Selecting a Crystal The accuracy of the RTC depends on several factors relating to crystal selection and board design A clock timing budget determines the clock accuracy The de signer should determine the timing budget before se lecting a crystal There are four major contributors to a clock timing bud get m Frequency Tolerance This is the crystal calibration frequency It states how far off the actual crystal frequency is from the nominal frequency For a typical 32 768 kHz crystal watch crystal the frequency tolerance is 20 parts per million ppm Frequency tolerance is specified at room temperature m Frequency Stability This parameter is
14. AMD K6 E AMD K6 2E Notes Table 20 Related AMD Products E86 Family Devices Description 16 bit microcontroller Low voltage 16 bit microcontroller High performance 16 bit embedded microcontroller High performance 16 bit embedded microcontroller High performance 16 bit embedded microcontroller High performance 16 bit embedded microcontroller High performance 80 186 and 80C188 compatible 16 bit embedded microcontroller with 8 or 16 bit external data bus High performance 80C186 and 80C188 compatible low voltage 16 bit embedded microcontroller with 8 or 16 bit external data bus High performance low voltage 16 bit embedded microcontroller with 32 Kbyte of internal RAM High performance 16 bit embedded communications controller High performance 16 bit embedded HDLC microcontroller High performance 16 bit embedded USB microcontroller High performance highly integrated low voltage 32 bit embedded microcontroller High performance single chip 32 bit embedded PC AT compatible microcontroller High performance single chip low power PC AT compatible microcontroller High performance single chip PC AT compatible microcontroller High performance single chip 32 bit embedded microcontroller High performance 32 bit embedded microprocessor with 32 bit external data bus High performance 32 bit embedded microprocessor with 16 bit external data bus High performance 32 bit embedded microprocessor with 32 bit ex
15. measure of how much the crystal resonant frequency is influenced by operating temperature For watch crystals typical numbers are around 30 ppm over the temperature range m Aging This parameter is how much the crystal resonant frequency changes with time Typical Aging numbers are 3 ppm per year m Load Capacitance The crystal is calibrated with a specific load capacitance If the system load capacitance does not equal the crystal load capacitance a timing error is introduced The timing error is calculated by the following equation Error 1 C1 CLyai Co 2 1 1 CL Co 2 1 GANCL 4 4C0 System ta 10 pF INFORMATION If you multiply Error by 1 06 the error in ppm is given In the above equation C1 is the crystal motional capacitance and Co is the crystal static capacitance is the crystal load capacitance and CLsystem is the system load capacitance Once the complete timing error has been calculated by adding all of the errors together compare it to the initial timing budget Table 7 provides a convenient translation of ppm to seconds per month Table 7 Timing Error as It Translates to Clock Accuracy Timing Error Parts per million Seconds Month 32 768 kHz Crystal Selection The 32 768 kHz crystal oscillator is shown in Figure 8 The oscillator load capacitance is 5 pF Table 8 pro vides specifications for selecting a
16. 18 pin summary A 16 write cycles 65 Index 2 Elan SC520 Microcontroller Data Sheet ADVANCE O operating ranges 48 ordering information 2 P package PBGA physical dimensions B 1 PAR programmable address region registers 31 PBGA package physical dimensions B 1 thermal characteristics 56 PCI bus AC timing 58 capacitance 51 description 30 pin summary A 8 signal descriptions 18 switching test waveforms 58 timing 65 voltage 49 peripherals integrated description of 31 physical dimensions B 1 PIC programmable interrupt controller 31 pins See also signals clock pin loading 40 pin and signal tables 10 pin connection diagram 8 pin designations 10 pin designations by pin name 13 pin designations sorted by pin number 11 pin tables Appendix A A 1 Multiplexed Signal Trade Offs table A 2 Pin List Summary table A 7 Sorted by PIO Number table 4 Sorted by Signal Name table 5 PIO See programmable I O PIO power characteristics 56 pin summary A 14 power dissipation 56 signal descriptions 27 supply current 56 voltage levels 48 power on reset timing 59 programmable I O PIO multiplexed signal trade offs A 3 signal descriptions 25 sorted by pin number A 4 INFORMATION sorted by signal name 5 R real time clock RTC backup battery 46 circuit with backup battery 47 circuit without backup battery 47 not using backup battery 46 vol
17. 2 Data includes GPD15 GPDO0 or MD31 MDO Figure 33 Flash Write Cycle Timing PCI Bus Timing The characteristics of the PCI interface pins are speci fied in the Local Bus Specification Revision 2 2 section 4 2 1 1 DC Specifications Table 4 1 DC Spec ifications for 5V Signaling and section 4 2 2 1 DC Specifications Table 4 3 DC Specifications for 3 3V Signaling Elan S C520 Microcontroller Data Sheet 65 ADVANCE INFORMATION SDRAM Timing Advance Parameter Information Name Parameter Description Refresh active to active command period Active command to precharge command period Tras Active command to column command same bank Trop Precharge command to active command period Trp Write recovery or data in to precharge lead time CK High pulse width CK Low pulse width Tox CK period Command setup Command hold A Access time from CK Tac Data out hold time E CK to data out high impedance CK to data out low impedance Tz Transition time of CK rise and fall Data in setup time Tps Data in hold time Address setup time Tas Address hold time Tay N O N Notes 1 Corresponds to the 33 MHz crystal frequency and assumes 33 333 MHz with no guardband 2 This access time is based on th
18. 388 Pin PBGA Package aei 56 Switching Characteristics and Waveforms 58 Key to Switching 58 Elan SC520 Microcontroller Data Sheet ADVANCE INFORMATION AC Switching Test Waveforms 58 Non PCI Bus Interface Pins as Oe to ene 58 PCI Bus Interface Pins 58 Switching Characteristics over Commercial Operating Ranges 59 Power On Reset eie ertt eo 59 Reset Timing with Power Applied 61 ROM rc pH MN E 63 PCI Bus TIMIN cx cms 65 DENN cl 66 SP oTo a od eoo tepidis e un ayapa 67 CE Reco ee err En 68 GP Bus Read Cycle Timing 70 GP Bus DMA Write Cycle Timing cedro e ie br cere tee RE edere taber 71 SSI Timing i eie equ 72 JTAG TiIMINg T PE 73 Appendix A Pin Tables
19. 5 Setup GPIOCS16 GPMEMCS16 asserted to programmed command deassertion 45 Delay GPIOCS16 GPMEMCS16 hold from programmed command deassertion Command pulse width GPIOWR GPMEMWR GPIORD GPIOWR 8 16 bit cycles 303 5 GPA GPBHE hold from command deassertion 25 Setup GPRDY deasserted to programmed command deassertion 45 GPRDY pulse width 303 Command High deassertion time 85 Setup GPD to write command assertion OFFS 1 303 15 GPD from write command deassertion 25 Setup GPD stable to read command deassertion 10 Hold GPD from read command deassertion 0 Setup GPA GPBHE stable to GPALE falling edge OFFS PW 2 303 10 GPALE pulse width PW 1 303 5 Setup GPAEN High to GPIORD GPIOWR assertion echo mode OFFS 1 303 15 Setup GPA stable to GPCS OFFS 1 303 5 Hold stable from GPCS RCOV 1 303 5 Pulse width GPCS PW 1 303 5 Hold GPAEN to GPIORD GPIOWR deassertion echo mode 25 Setup GPDBUFOE assertion to command assertion OFFS 1 303 15 Notes Hold GPDBUFOE assertion from command assertion 25 1 If the GPCS7 GPCSO signals are internally qualified with the command the 57 50 and command pads switch simultaneously
20. AF7 GPIRQ6 PIO17 7 B7 MECC4 C26 NC AF15 PIO17 GPIRQ6 GPIRQ7 PIO16 AF7 A8 5 025 AF16 PIO18 GPIRQ5 07 GPIRQ8 PIO15 AF8 9 MECC6 Y26 NC AF18 PIO19 GPIRQ4 6 GPIRQ9 PIO14 AE8 A10 NC A3 NC AF20 PIO20 GPIRQ3 6 GPIRQ10 PIO13 AD8 MD4 B11 NC AA26 NC AF23 PIO21 GPIRQ2 AF6 GPMEMCS16 4 MD5 A12 NC AB3 NC AF25 PIO22 GPIRQ41 AF5 26 24 MD6 B13 NC NC B3 PIO23 GPIRQO 5 GPMEMWR C18 MD7 A14 NC NC B4 P1024 AD5 GPDBUFOE GPRDY PIO2 AF11 MD8 B15 NC AC12 NC B6 PIO25 AC4 GPIOCS16 GPRESET AC22 MD9 A16 AC16 NC C5 26 AD4 GPMEMCS16 GPTC PIO4 AD11 MD10 B17 AC17 NC C6 PIO27 GPCSO 4 INST D4 MD11 A18 NC AC25 NC C22 PlO28 CTS2 AF4 GPA24 INTA K3 MD12 20 AD1 D23 PIO29 DSR2 AF3 INTB J3 MD13 A21 NC AD2 NC E3 PIO30 DCD2 AE3 INTC H3 MD14 A22 AD12 NC E23 PIO31 RIN2 AD3 INTD H4 MD15 B23 NC AD13 NC PITGATE2 AC21 GPCS3 IRDY L2 MD16 B8 NC AD14 NC 124 PITOUT2 CFG3 24 JTAG TCK AD21 MD17 A9 NC AD15 PAR P1 PRGRESET D20 JTAG TDI AF21 MD18 B10 NC AD16 PERR N2 PWRGOOD C20 JTAG TDO AF22 MD19 11 AD17 PIOO GPALE AE12 REQO L3 JTAG_TMS AE21 MD20 B12 AD18 PIO1 GPBHE AF12 REQT N3 JTAG_TRST AE22 MD21 A13 NC AD25 PIO2 GPRDY AF11 REQ2 LF PLL1 AF24 MD22 B14 NC AD26 PIO3 GPAEN AE11 RE
21. An efficient communications protocol transmits key board and mouse commands upstream and trans mits video BIOS calls downstream The thin client renders and displays the graphics for the user The thin client is typically connected to an Ethernet LAN although a remote location can connect to a server via a WAN connection such as a modem A minimum speed of 24 kbaud is required for the com munication protocol unless the application is graph ics intensive in which case a faster connection is required Figure 4 on page 36 shows an lanSC520 micro controller based digital set top box DSTB which is a consumer client device that uses a television set as the display Common applications for the DSTB are internet access e mail and streaming audio and video content The minimal system includes a connection to the WAN via a modem ADSL or cable modem an out put to a TV and an InfraRed IR link to a remote control or wireless keyboard Expanded systems in clude DVD drives and MPEG2 decoders to deliver digital video content A hard drive may be employed to store video data for future replay Keyboard mouse printer or a video camera are options that can be included Figure 5 on page 37 shows an lanSC520 micro controller based telephone line concentrator lo cated in the neighborhood that converts multiple analog subscriber loops into a high speed digitally multiplexed line for connection to the central office switching ne
22. GP Bus DMA Acknowledge can each be mapped to one of the seven available DMA channels They are asserted active Low to acknowledge the corresponding DMA requests GPDBUFOE PIO24 O O O GP Bus Data Bus Buffer Output Enable is used to control the output enable on an external transceiver that may be on the GP data bus Using this transceiver is optional in the system design and is necessary only to alleviate loading or voltage issues This pin is asserted for all external GP bus accesses It is not asserted during accesses to the internal peripherals even if GP bus echo mode is enabled Note that if the ROM is configured to use the GP data bus then its bytes are not controlled by this buffer enable they are controlled by the ROMBUFOE signal GPDRQO GPDRQ1 GPDRQ2 GPDRQ3 PIO8 PIO7 6 PIO5 GP Bus DMA Request can each be mapped to one of the seven available DMA channels They are asserted active High to request DMA service GPIOCS16 PIO25 GP Bus I O Chip Select 16 is driven active early in the cycle by the targeted I O device on the GP bus to request a 16 bit I O transfer GPIORD GP Bus I O Read indicates that the current cycle is a read of the currently addressed I O device on the GP bus When this signal is asserted the selected I O device can drive data onto the data bus GPIOWR GP Bus I O Write indicates that the current cycle is a write of the currently addressed I
23. 1995 ISBN 0 201 87697 3 Customer Development Platform The lanSC520 microcontroller customer development platform CDP is provided as a test and development platform to illustrate the capabilities of the lanSC520 microcontroller using the PCI bus and an on board 10 100 Mbit s Ethernet connection In addition the CDP serves as a platform for embedded product develop ment using the lanSC520 microcontroller Am79C972 Ethernet controller and the PCI bus The lanSC520 microcontroller CDP enables develop ers to benchmark their embedded network ready ap plications understand the functionality of the microcontroller and to know how to wire an lanSC520 microcontroller system using off the shelf components The CDP board also demonstrates how the embedded PCI bus controller works well with other PCl ready pe ripherals Third Party Development Support Products The FusionE86 Program of Partnerships for Applica tion Solutions provides the customer with an array of products designed to meet critical time to market needs Products and solutions available from the AMD FusionE86 partners include protocol stacks emulators hardware and software debuggers board level prod ucts and software development tools among others In addition mature development tools and applications for the x86 platform are widely available in the general marketplace C 2 Elan SC520 Microcontroller Data Sheet ADVANCE Customer Service The
24. 3 SWEA SWEB SDRAM Memory Write Enables are used in combination with the SRASA SRASB and SCASA SCASB to encode the SDRAM command type SWEA and SWEB are the same signal provided on two different pins to reduce the total load connected to WE Suggested system connection SWEA for SDRAM banks 0 and 1 SWEB for SDRAM banks 2 and 3 Elan SC520 Microcontroller Data Sheet 17 AMD ADVANCE INFORMATION Table 2 Signal Descriptions Continued Multiplexed Tyre section ssssaaaa ROM Flash BOOTCS ROM Flash Boot Chip Select is an active Low output that provides the chip select for the startup ROM and or the ROM Flash array BIOS HAL O S etc The BOOTCS signal asserts for accesses made to the 64 Kbyte segment that contains the Am5 86 CPU boot vector addresses SFF0000h 3FFFFFFh In addition to this linear decode region BOOTCS asserts in response to accesses to user programmable address regions FLASHWR Flash Write indicates that the current cycle is a write of the selected Flash device When this signal is asserted the selected Flash device can latch data from the data bus GPA25 GPAO0 General Purpose Address Bus provides the address to the system s ROM Flash devices It is also the address bus for the GP bus devices Twenty six address lines provide a maximum addressable space of 64 Mbytes for each ROM chip select GPD15 GPDO General Purpose Data Bus inputs data during memor
25. 42 Running the Elan SC520 Microcontroller at 33 333 43 Bypassing Internal Oscillators 44 RTE Voltage Monitor E 45 Backup Battery Considerations n 46 Using an External RTC Backup 0 46 Not Using an External RTC Backup 2 46 Absolute Maximum Rallnigs so 48 Operating Ranges at Commercial Temperatures 2 48 Voltage Levels for Interface Pins 220 88 49 Voltage Levels for PCI Interface Pins r 49 DC Characteristics Over Commercial Operating Ranges 50 Capacitance t 51 Interface Pin Capacitance 51 PCI Interface Pin Capacitance heads vote tae eee Chena 51 Grystal n aN 51 Bs pz ugs ORV SS NS 51 Power Characteristics Saat 56 Thema Characteristics uu du Di D cq V dE 56
26. AD12 RIN1 PITGATE2 GPCSS PIO30 DCD2 PIO2 GPRDY AD11 GPRESET PIO27 GPCS0 PIO1 GPBHE REQ4 VCC_I O TMROUT1 GPCS6 PIO23 GPIRQO NC GNT4 TMRIN1 GPCS4 DATASTRB WBMSTRI ICFGI PIO20 GPIRQ3S NC SOUT2 ROMBUFOE NC PIO17 GPIRQ6 NC CMDACK NC 33MXTAL2 PIO14 GPIRQ9 NC BA1 AD2 NC PIO9 GPDACKS STOP TX MA11 AD3 NC PIO6 GPDRQ2 NC AD9 NC P1031 PIOS GPAEN SSI DO AD10 NC 26 GPMEMCS 16 PIOO GPALE NC CTS1 ROMRD PIO24 GPDBUFOE NC JTAG TDI DCD1 FLASHWR PIO19 GPIRQ4 NC JTAG TDO BOOTCS PIO18 GPIRQS NC NC SIN2 33MXTAL1 PIO13 GPIRQ10 NC PLL1 SCSO AD1 PIO10 GPDACK2 NC NC MA12 ADO NC AD8 NC PIO4 GPTC CBEO Notes PIO25 GPIOCS16 NC 1 See Table 16 on page A 4 for PIOs sorted by pin number 12 NC Elan SC520 Microcontroller Data Sheet 32KXTAL1 ADVANCE INFORMATION AMD Pin Designations Pin Name Signal Name Pin Signal Name Pin Name Signal Name Pin Signal Name 32KXTAL1 AF26 AMDEBUG_DIS D3 GN GND_ANLG A25 GPCS1 ROMCS1 GPA23 32KXT
27. AMD customer service network includes U S of fices international offices and a customer training cen ter Expert technical assistance is available from the AMD worldwide staff of field application engineers and factory support staff to answer E86 and Comm86 fam ily hardware and software development questions Hotline and World Wide Web Support For answers to technical questions AMD provides e mail support as well as a toll free number for direct access to our corporate applications hotline The AMD World Wide Web home page provides the latest product information including technical informa tion and data on upcoming product releases In addi tion EPD Codekit software on the Web site provides tested source code example applications Corporate Applications Hotline 800 222 9323 Toll free for U S and Canada 44 0 1276 803 299 U K and Europe hotline Additional contact information is listed on the back of this datasheet For technical support questions on all E86 and Comm86 products send e mail to epd sup port amd com INFORMATION World Wide Web Home Page To access the AMD home page go to www amd com Then follow the Embedded Processors link for infor mation about E86 family Comm86 products Questions requests and input concerning AMD s WW pages can be sent via e mail to webmas ter amd com Documentation and Literature Free information such as data books user s manuals data sheets
28. DO SSI DI 1 0 32KXTAL2 32KXTAL1 33MXTAL2 33MXTAL1 LF_PLL1 CLKTIMER CLKTEST PWRGOOD PRGRESET BBATSEN INFORMATION GPA25 GPA0 GPD15 GPD0 GPRESET GPIORD GPIOWR GPMEMRD GPMEMWR GPALE GPBHE GPRDY GPAEN GPTC GPDRQS GPDRQO GPDACK3 GPDACKO GPIRQ10 GPIRQO GPDBUFOE GPIOCS16 GPMEMCST6 GPCS7 GPCSO GPA25 GPAO0 GPD15 GPDO MD31 MDO BOOTCS ROMCS2 ROMCST ROMRD FLASHWR ROMBUFOE TMRIN1 TMRINO TMROUT1 TMROUTO PITGATE2 PITOUT2 JTAG TRST JTAG TCK JTAG TDI JTAG JTAG TMS CMDACK BR TC STOP TX TRIG TRACE WBMSTR2 WBMSTRO CF DRAM DATASTRB CF ROM GPCS DEBUG ENTER INST TRCE AMDEBUG DIS CFG3 CFGO RSTLD7 RSTLDO Elan SC520 Microcontroller Data Sheet GP Bus ROM Flash Timers JTAG AMDebug System Test Configuration ADVANCE INFORMATION LOGIC DIAGRAM BY DEFAULT PIN FUNCTION PCI Bus SDRAM Serial Ports UART 1 UART 2 SSI Clocks and Reset Notes lt p AD31 AD0 CBE3 CBE0 DEVSEL PT CLKPCIOUT CLKPCIIN RST INTA INTD REQ4 REQO 4 GNT4 GNTO MA12 MAO 4 1 lt p MD31 MDO 4 85 53 5 50 CLKMEMOUT CLKMEMIN 4 SRASA SRASB SCASA SCASB SWEA SWEB SDQM3 SDQMO MECC6 MECCO SOUT2 SOUT1 SIN2 SIN1 DTR2 DTR1 DCD1 RIN1 PIO28 CTS2 P1029 DSR2 PIO30
29. GPCSx may deassert prior to the deassertion of the command 2 OFFS represents the programmable offset timing parameter for the corresponding pin 3 The 30 corresponds to the 33 MHz crystal frequency and assumes 33 333 MHz 4 PW represents the programmable pulse width parameter for the corresponding pin 5 This can be increased based on the programmed chip select offset and pulse width along with its recovery time 6 This parameter must be met to ensure that a cycle is extended by GPRDY 7 This parameter assumes that the 57 50 signals not internally qualified with the command 8 RCOV represents the programmable recovery time for the chip selects 68 Elan SC520 Microcontroller Data Sheet GPA25 GPA0 GPCS7 GPCS0 GPALE GPIOWR GPMEMWR GPIORD GPMEMRD ADVANCE INFORMATION GPIOCS16 GPMEMCS16 GPRDY GPD15 GPDO Write GPD15 GPDO Read GPDBUFOE GPAEN 120 120 121 121 22 ap 22 PS 115 115 gt 116 m gt 116 Iz 1 t3 I t4 11 oem SR t2 l t2 9 15 gt be 6 114 113 m A LI 1 146 t45 t46 117 t27 t17 127 Figure 35 GP Non DMA Cycle Timing Elan SC520 Microcontroller Data Sheet 69 AMD ADV
30. O Control PCI Bus MA12 MAO GPD15 GPDO MD31 MDO GPA25 GPA0 Elan SC520 Microcontroller SDRAM SDRAM Bus GP Bus Flash Control Control 33 MHz Crystal 32 kHz Crystal Control 1 GPD15 GPD0 DVD or HDD EIDE Figure 4 Elan SC520 Microcontroller Based Digital Set Top Box Reference Design 36 lanTMSC520 Microcontroller Data Sheet Memory AMDA INFORMATION ADVANCE Soeur I340 LL ols LVCHELWY LycH6ZWY ols 6 OVISI eoepnelu 9 1 01 Lvcd6ZUv LVCHELWY ols 6 ols Lvecd6ZUv 2 OV ISI L NH 1 PCM Highway ISS GPD15 GPDO MD31 MDO 58 4 25 sng 39 Elan SC520 Microcontroller sng WVYds MA12 MAO INVHIS Control Control mms n e1s9 ZHA ZE T 15 10 zHIW Figure 5 Elan SC520 Microcontroller Based Telephone Line Concentrator Reference Design Elan SC520 Microcontroller Data Sheet 37 ADVANCE CLOCK GENERATION AND CONTROL The ElanSC520 microcontroller is
31. O device on the GP bus When this signal is asserted the selected I O device can latch data from the data bus 20 Elan SC520 Microcontroller Data Sheet ADVANCE INFORMATION AMD Table 2 Signal Descriptions Continued Multiplexed Signal GPIRQO PIO23 GP Bus Interrupt Request can each be mapped to one of the GPIRQ1 22 available interrupt channels or NMI They are asserted when IGPIRQ2 PIGA peripheral requires interrupt service GPIRQ3 PIO20 Configuration registers allow inversion of these interrupt requests to GPIRQ4 PIO19 recognize active low interrupt requests These interrupt requests can be routed to generate NMI Signal Description GPIRQ5 PIO18 GPIRQ6 PIO17 GPIRQ7 PIO16 GPIRQS PIO15 GPIRQS PIO14 GPIRQ10 PIO13 SPMEMCS16 PIO26 GP Bus Memory Chip Select 16 is driven active early in the cycle by the targeted memory device on the GP bus to request a 16 bit memory transfer GPMEMRD GP Bus Memory Read indicates that the current GP bus cycle is a read of the selected memory device When this signal is asserted the selected memory device can drive data onto the data bus GPMEMWR GP Bus Memory Write indicates that the current GP bus cycle is a write of the selected memory device When this signal is asserted the selected memory device can latch data from the data bus GPRDY GP Bus Ready can be driven by open drain devices When pulled Low during a GP bus access wait states
32. Signal Name La Signal Name AD30 CLKMEMOUT INFORMATION VCC_CORE VCC_CORE AD31 MD12 VCC_CORE 5 MD29 GPD11 SDQM3 CLKMEMIN GPA18 RSTLD3 GPD12 SDQM1 RST MD15 AD18 CLKPCIOUT ROMCS1 GPCS1 VCC_I O AD17 CLKTIMER CLKTEST BBATSEN GPD15 INTB MD1 VCC_ANLG VCC_CORE VCC_I O MD17 GPA6 VCC_CORE GPA3 GND 9 PRGRESET GPAO GND MD19 GPA25 DEBUG_ENTER SCS2 GND MD5 GPDO SCS3 GND MD21 NC NC CBE2 GND MD7 NC GPA16 RSTLD1 AD16 GND MD23 GPD2 5 GPA11 MD9 GPD3 MECC1 VCC_I O GPA12 MD25 GPD4 AD25 4 MD11 GPD7 AD24 MAS MD27 GPD8 NC PAR MD28 GPD9 VCC_CORE SERR MD13 GPD10 NC GNT2 MD14 GPA20 RSTLD5 GPA17 RSTLD2 REQ2 MD30 GPD13 SWEB GND MD31 GPIOWR SWEA VCC l O GND GND ANLG GPD14 AD23 GND GND VCC RTC GPMEMWR CBES GND GND AD29 GPA21 RSTLD6 GPA22 RSTLD7 GND GND AD28 PWRGOOD VCC_CORE GND GND NC GPA19 RSTLD4 GPA7 GND VCC_CORE NC NC GPMEMRD GND GPA13 ROMCS2 GPCS2 SCASA VCC_I O MA7 NC GPA15 RSTLDO SCA
33. an external oscillator is used 32KXTAL1 should be unconnected and the clock source driven on 32KXTAL2 33MXTAL2 33MXTAL1 Osc 33 MHz Crystal Interface is the main system clock for the chip This clock source is used to derive the SDRAM CPU and PCI clocks When an external oscillator is used 33MXTAL1 should be grounded and the clock source driven on 33MXTAL2 CLKTEST CLKTIMER O Test Clock Output is a shared pin that allows many of the internal clocks to be driven externally CLKTEST can drive the internal clocks of the UARTs PLL1 PLL2 the programmable interval timer PIT or the real time clock RTC for testing or for driving an external device CLKTIMER CLKTEST Timer Clock Input is a shared clock pin that can be used to input frequency to the programmable interval timer PIT LF PLL1 Loop Filter Interface is used for connecting external loop filter components Component values and circuit descriptions are contained in Clock Generation and Control on page 38 PRGRESET STI Programmable Reset can be programmed to reset the lanSC520 microcontroller but allow SDRAM refresh to continue during the reset This allows the system to be reset without losing the information stored in SDRAM On power up PRGRESET is disabled and must be programmed to be operational When disabled this pin has no effect on the ElanSC520 microcontroller PWRGOOD STI Power Good is
34. and at full execution speeds It also allows trac ing during execution from the Am5 86 CPU s internal cache AMDebug technology provides the product design team with two different communication paths on the lanSC520 microcontroller each of which is supported by powerful debug tools from third party vendors in AMD s FusionE86 program W Serial AMDebug technology uses a serial connec tion based on an enhanced JTAG protocol and an inexpensive 12 pin connector that can be placed on each board design This low cost solution satisfies the requirement of a large number of software de velopers W Parallel AMDebug technology uses a parallel debug port to exchange commands and data between the lanSC520 microcontroller and the host The higher pin count requires that the extra signal pins be provided on a special bond out package of the lanSC520 microcontroller which is only made available to tool developers such as in circuit emu INFORMATION lator manufacturers The parallel AMDebug port greatly simplifies the task of supporting high speed data exchange Industry Standard PCI Bus Interface The lanSC520 microcontroller provides a 33 MHz 32 bit PCI bus Revision 2 2 compliant host bridge inter face including integrated write posting and read buff ering capabilities suitable for high throughput applications The PCI host bridge leverages standard peripherals and software It also provides W High throughput 132 Mbytes s
35. inputs are 5 V tolerant OPERATING RANGES AT COMMERCIAL TEMPERATURES Parameter Description Minimum Typical Maximum TcASE Commercial case temperature operating in free air 0 485 VCC CORE Core voltage 42 25 42 5 42 75 V I O voltage 43 0 43 3 43 6 V VCC RTC Real time clock voltage 42 0 42 5 43 3 V VCC ANLG Analog voltage 2 25 2 5 2 75 V Notes 1 Operating ranges define the temperature and voltage limits between which the functionality of the device is guaranteed 2 Referenced from GND 3 All inputs are 5 V tolerant 48 Elan SC520 Microcontroller Data Sheet ADVANCE INFORMATION AMD VOLTAGE LEVELS FOR NON PCI INTERFACE PINS Advance Information Parameter Description Min Max Input Low voltage 0 3 0 8 Input High voltage 2 0 VCO O 1 7 Output High voltage 6 mA VCC_I O 0 45 Output Low voltage 6 mA 0 45 Output High voltage lop 12 mA VCC_I O 0 45 Output Low voltage 12 mA 0 45 Output High voltage lop 18 mA O 0 45 Output Low voltage lo 18 mA 0 45 Output High voltage lop 24 mA VCC_I O 0 45 lt lt lt lt lt lt lt lt Output Low voltage 24 mA Notes 1 The drive strengths of all the pins are listed in Table 19 Pin List Summary on page A 7 The pins with variable dri
36. kHz pe Figure 12 RTC Voltage Monitor Block Diagram RTC VOLTAGE MONITOR If an external backup battery is connected to the lanSC520 microcontrollers VCC_RTC pin the real time clock RTC remains operational even if all the other power supplies are turned off The lanSC520 microcontroller s RTC voltage monitor is designed to signal the RTC core when the backup battery is not in stalled or is low Additionally the voltage monitor circuit signals the RTC core when the rest of the system is being powered down Features of the voltage monitor include m Bandgap voltage generator for precision reference voltage m High gain amplifier for adjusting bandgap voltage to low battery trip voltage m The RTC can be connected to the main power plane if a backup battery is not needed in the system Figure 12 shows a block diagram of the RTC voltage monitor The voltage monitor circuit uses a delta Vbe voltage voltage from base to emitter source to generate a bandgap voltage of approximately 1 23 V This voltage is the input to an amplifier whose gain is such that the output voltage is a 2 V reference This reference signal is an input to a comparator along with the backup bat tery voltage BBATSEN If BBATSEN drops below the 2 V reference an RTC invalidate signal is generated to notify the user via the RTC_VRT bit RTC index ODh 7 that the RTC contents are no longer valid There are three conditions that trigge
37. otherwise to any intel lectual property rights is granted by this publication Except as set forth in AMD s Standard Terms and Conditions of Sale AMD assumes no liability whatsoever and disclaims any express or implied warranty relating to its products including but not limited to the implied warranty of merchantability fitness for a particular purpose or infringement of any intellectual property right AMD s products are not designed intended authorized or warranted for use as components in systems intended for surgical implant into the body or in other applications intended to support or sustain life or in any other application in which the failure of AMD s product could create a situation where personal injury death or severe property or environmental damage may occur AMD reserves the right to discontinue or make changes to its products at any time without notice 1999 Advanced Micro Devices Inc All rights reserved Elan SC520 Microcontroller Data Sheet
38. provide the ability to interface with off chip hardware A standard PC AT compatible programmable inter val timer PIT that consists of three 16 bit timers A software timer that eases the task of keeping sys tem time It provides 1 us resolution and can also be used for performance monitoring A watchdog timer to guard against runaway soft ware A real time clock RTC with battery backup capa bility The RTC also provides 114 bytes of battery backed RAM for storage of configuration parame ters Two integrated 16550 compatible UARTs that pro vide full handshaking capability with eight pins each Enhancements enable the UARTs to operate at baud rates up to 1 152 Mbits s The UARTs can be configured to use the integrated GP bus DMA controller to transfer data between the serial ports and SDRAM A synchronous serial interface SSI that is compat ible with SCP SPI and Microwire slave devices The SSI interface can be configured for either full duplex or half duplex operation using a 4 wire or 3 wire interface 32 programmable I O pins are provided These pins are multiplexed with other peripherals and interface functions The lanSC520 microcontroller also provides PC AT compatible functions for control of the a20 gate and the soft CPU reset Ports 0060h 0064h 0092h INFORMATION JTAG Boundary Scan Test Interface The lanSC520 microcontroller provides a JTAG test port that is compliant with IEEE 1149 1 f
39. provided in all op erating modes of the ElanSC520 microcontroller In addition to these three primary interfaces the ElanSC520 microcontroller also contains internal oscil lator circuitry and phase locked loop PLL circuitry re quiring only two simple crystals for virtually all system clock generation Diagrams showing how the ElanSC520 microcontroller can be used in various system designs are included in Applications on page 33 28 Elan SC520 Microcontroller Data Sheet Am5 86 CPU AMDebug Technology and JTAG Bus Interface Unit GP DMA Request and Grant CPU Bus Arbiter PCI Bus Arbiter PCI Requests and Grants ADVANCE CPU Address Bus CPU Data Bus CPU Control Status Bus Control Status CPU Bus Interface FIFOs and FIFO Control PCI Master PCI Bus lanTMSC520 Microcontroller Fi gure 1 lanTMSC520 Microcontroller Data Sheet Clock Generation INFORMATION CPU Bus Interface SDRAM Controller Address Decode Unit Read Write Buffers ROM Flash Controller GP DMA Controller GP Bus Controller External GP Bus Programmable Interrupt Controller Programmable Interval Timer Watchdog Timer Real Time Clock CMOS RAM General Purpose Timers Software Timer 16550 UART 16550 UART Synchronous Serial Interface Programmable I O Controls PC AT Compatibility Logic Elan SC520 Microcontroller Block Diagram 2
40. signal name and alternate function pin number type termination reset state output drive and maximum load Table 19 on page A 7 INFORMATION For tables showing pins sorted by pin number signal name respectively see Pin Designations Pin Number on page 11 and Pin Designations Pin Name on page 13 For signal descriptions see Table 2 Signal Descrip tions on page 17 In all tables the brackets indicate alternate multi plexed functions and braces indicate reset config uration pins pinstraps The line over a pin name indicates an active Low signal The word pin refers to the physical wire the word signal refers to the electrical signal that flows through it Elan SC520 Microcontroller Data Sheet 1 AMD ADVANCE INFORMATION Table 15 Multiplexed Signal Trade Offs Signal You Want Signal You Give Up Ping ROM Flash Control ROMCS1 ROMCS2 PIOO PIO1 P1027 ROMCS1 ROMCS2 PITGATE2 TMRIN1 GPCS5 TMRINO GPCS6 TMROUT1 GPCS7 TMROUTO GPDACKO 1012 GPDACK1 PIO11 GPDACK2 PIO10 GPDACK3 PIO9 GPDBUFOE PIO24 GPDRQ0 PIO8 GPDRQ1 PIO7 GPDRQ2 PIO6 GPDRQ3 PIO5 GPIOCS16 PIO25 GPIRQ0 PIO23 GPIRQ1 PIO22 GPIRQ2 PIO21 GPIRQ3 PIO20 GPIRQ4 PIO19 GPIRQ5 PIO18 GPIRQ6 PIO17 GPIRQ7 PIO16 GPIRQ8 PIO15 GPIRQ9 PIO14 GPIRQ10 PIO13 GPMEMCS16 PIO26 GPRDY PIO2 PIO4
41. this signal is asserted the selected ROM device can drive data onto the data bus Peripheral Component Interconnect PCI Bus AD31 ADO B PCI Address Data Bus is the PCI time multiplexed address data bus B Command or Byte Enable Bus functions 1 as a time multiplexed bus command that defines the type of transaction on the AD bus or 2 as byte enables CBEO for AD7 ADO CBE1 for AD15 AD8 CBE2 for AD23 AD16 for AD31 AD24 CLKPCIIN PCI Bus Clock Input is the 33 MHz PCI bus clock This pin can be connected to the CLKPCIOUT pin for systems where the ElanSC520 microcontroller is the source of the PCI bus clock 18 Elan SC520 Microcontroller Data Sheet ADVANCE INFORMATION AMD Table 2 Signal Descriptions Continued Multiplexed Signal CLKPCIOUT PCI Bus Clock Output is a 33 MHz clock output for the PCI bus devices This signal is derived from the 33MXTAL1 33MXTAL2 interface Signal Description DEVSEL Device Select is asserted by the target when it has decoded its address as the target of the current transaction FRAME Frame is driven by the transaction initiator to indicate the start and duration of the transaction GNT4 GNTO Bus Grants are asserted by the lanSC520 microcontroller to grant access to the bus INTA INTD Interrupt Requests are asserted to request an interrupt These four interrupts are the same type of interrupt as the GPIRQ10
42. uration pins pinstraps The line over a pin name indicates an active Low signal The word pin refers to the physical wire the word signal refers to the electrical signal that flows through it ADVANCE m Pin designations are listed in the Pin Designations Pin Number table on page 11 and the Pin Designations Pin Name table on page 13 m Table 2 Signal Descriptions on page 17 contains a description of the microcontroller signals organized alphabetically by functional group Table 1 on page 16 defines terms used in Table 2 The table includes columns listing the multiplexed functions and I O type INFORMATION Refer to Appendix A Pin Tables on page A 1 for an additional group of tables with the following informa tion m Multiplexed signal tradeoffs Table 15 on page 2 Programmable I O pins ordered by 1 PIO pin number and 2 multiplexed signal name respectively including pin numbers multiplexed functions and pin configuration following system reset Table 16 on page A 4 and Table 17 on page A 5 m Comprehensive pin and signal summary showing signal name and alternate function pin number I O type maximum load values power on reset default function reset state power on reset default opera tion hold state and voltage Table 19 on page A 7 10 Elan SC520 Microcontroller Data Sheet ADVANCE Pin Designations Pin Number La Signal Name Pins Signal Name Ls Signal Name La
43. 0 microcontroller offers user config urable CPU core clock speed operation at 100 or 133 MHz for different power performance points depending on the application Not all lanSC520 microcontroller devices support all CPU clock rates The maximum supported clock rate for a device is indicated by the part number printed on the package The clocking circuitry can be programmed to run the device at higher than the rated speeds However if an lanSC520 microcontroller is programmed to run at a higher clock speed than that for which it is rated then erroneous operation can result and physical damage to the device may occur The lanSC520 microcontroller includes on chip oscilla tors and PLLs as well as most of the required PLL loop filler components The lanSC520 microcontroller re quires two standard crystals one for 32 768 kHz and one for 33 MHz All the clocks required inside the lanSC520 microcontroller are generated from these crystals The lanSC520 microcontroller also supplies the clocks for the SDRAM and PCI bus however exter nal clock buffering may be required in some systems Note The lanSC520 microcontroller supports either a 33 000 MHz or 33 333 MHz crystal In this docu ment the generic term 33 MHz refers to the system clock derived from whichever 33 MHz crystal fre quency is being used in the system Integrated Peripherals The lanSC520 microcontroller is a highly integrated single chip CPU with a se
44. 12 15 14 15 16 17 18 19 20 21 22 23 24 26 ENCAPSULATION c v z x lt 17 0 14 0 FLAT AREA 4 00 X 45 1c AD ax 4X 4 20 1 1 TOP SIDE 050 DIE SIDE 0 70 51 30 TYP NL 70156 f 0 15 A 3 y 2 20 SIDE VIEW 2 46 SEATING PLANE 0 15 C DETAIL A SCALE NONE Elan SC520 Microcontroller Data Sheet B 1 Bottom View B 2 ADVANCE INFORMATION 31 75 BSC A1 CORNER DATUM A1 CORNER I D 2 30 C A B 10 26 25 24 23 22 21 2019 18 17 16 15 14 3 12 1110 9 8 7 6 5 4 3 2 1 000000000000l0000000000006 A 37 090 1 99990000000000000000000000 388X O0000000000000l0000000000000 oooo 0 635 _ 60600 BSC 31 75 BSC DATUM v 0000 v w a
45. 20 Microcontroller Data Sheet ADVANCE INFORMATION AMD Table 2 Signal Descriptions Continued Multiplexed Signal RSTLDO GPA15 Reset Latched Inputs are shared signals that are latched into a RSTLD1 GPA16 register when PWRGOOD is asserted They are used to input static information to software i e board revision These signals have built in pulldown resistors Signal Description RSTLD2 GPA17 RSTLD3 GPA18 RSTLD4 GPA19 RSTLD5 GPA20 RSTLD6 GPA21 RSTLD7 GPA22 Power BBATSEN Backup Battery Sense is a pin on which real time clock RTC backup battery voltage is sampled each time PWRGOOD is asserted If this pin samples below 2 0 V the Valid RAM and Time VRT bit in RTC index ODh is cleared until read After the read the VRT bit is set until BBATSEN is sensed via a subsequent PWRGOOD assertion BBATSEN also provides a power on reset signal for the RTC when an RTC backup battery is applied for the first time VCC_ANLG Analog Power Supply for the analog circuits PLLs VCC_CORE Power Supply for the ElanSC520 microcontroller core logic VCC_I O Power Supply to the I O pad ring VCC_RTC Power Supply for the real time clock and 32 kHz oscillator GND Digital Ground for the remaining ElanSC520 microcontroller core logic GND_ANLG Analog Ground for the analog circuits Elan SC520 Microcontroller Data Sheet 27 ARCHITECTURAL OVERVIEW The ElanSC520 microcontroller wa
46. 6 overview 31 pin loading 40 pin summary A 13 real time clock RTC voltage monitor 45 RTC voltage monitor block diagram 45 RTC voltage monitor specifications 46 SDRAM clock timing 67 signal descriptions 22 specifications 40 system clock block diagram 38 configuration multiplexed signal trade offs A 3 signal descriptions 26 CPU x86 instruction set 30 crystal 32 768 kHz crystal circuit 41 32 768 kHz crystal selection 41 33 333 MHz crystal speed 43 33 MHz crystal selection 42 3rd overtone crystal circuit implementation 42 capacitance 51 crystal speeds 38 selecting 41 customer support customer development platform C 2 documentation and literature C 3 hotline and web C 3 literature ordering C 3 ordering the microcontroller 2 related AMD products devices C 1 related documents information C 2 third party development support products C 2 web home page C 3 D DC characteristics 50 operating ranges 48 voltage for non PCI interface pins 49 51 Elan SC520 Microcontroller Data Sheet Index 1 ADVANCE INFORMATION debugging G See also AMDebug technology features and system test 32 GP bus JTAG boundary scan test interface 32 chip select signal descriptions 24 JTAG signal descriptions 23 description 31 derating curves 51 DMA read cycle 70 DMA DMA write cycle 71 multiplexed signal trade offs A 2 pin summary A 10 signal descriptions 19 GP bus DMA read cycle 70 GP bus DMA writ
47. 9 ADVANCE Industry Standard x86 Architecture The Am5 86 CPU in the ElanSC520 microcontroller utilizes the industry standard x86 microprocessor in struction set that enables compatibility across a variety of performance levels from the 16 bit Am186 proces sors to the high end AMD Athlon processor Soft ware written for the x86 architecture family is compatible with the ElanSC520 microcontroller Other benefits of the Am5 86 CPU include Improved time to market and easy software migra tion Existing availability of multiple operating systems that directly support the x86 architecture Whether the application requires a real time operating sys tem RTOS or one of the popular Microsoft oper ating systems the ElanSC520 microcontroller provides consistent compatibility with many off the shelf operating systems Multiple sources of field proven development tools m Integrated floating point unit FPU compliant with ANSI IEEE 754 standard W 16 KByte unified cache configurable for either write back or write through cache mode AMDebug Technology for Advanced Debugging The lanSC520 microcontroller provides support for low cost full featured in circuit emulation capability This in circuit emulation support was developed at AMD specifically to enable users to test and debug their software earlier in the design cycle Utilizing this capability the software can be more extensively exer cised
48. ADVANCE INFORMATION Table 19 Pin List Summary Continued Termination Max Load pF No Connects NC NC AA26 NC AB3 4 12 NC AC16 NC AC17 NC AC25 m AD1 NC AD12 m NC AD13 NC AD14 AD15 m NC AD16 AD17 m NC AD18 AD2 NC AD25 zm m AD26 m 1 m NC AE13 14 15 ES m 16 NC AE17 NC AE18 m 16 Elan SC520 Microcontroller Data Sheet ADVANCE INFORMATION Table 19 Pin List Summary Continued Signal Name Alternate Function Termination Pinstrap Max Load pF Notes 1 The NCs are true no connects and should be left disconnected Elan SC520 Microcontroller Data Sheet A 17 ADVANCE INFORMATION APPENDIX B PHYSICAL DIMENSIONS 388 Pin Plastic BGA PBGA Package Top View 35 00 BSC gt x A1 CORNER lt 28 00 BSC gt 3X 0 50 R 1 CORNER I D 11 2 3 4 5 6 7 8 9 1011
49. AL2 AE26 BAO T25 GND 112 GNTO M3 GPCS2 ROMCS2 C23 33MXTAL1 AB26 BA1 U25 GND L13 GNT1 N4 GPCSS PITGATE2 21 33MXTAL2 AC26 BBATSEN B25 GND L14 GNT2 P3 GPCS4 TMRIN1 AA24 ADO AC2 BOOTCS AB25 GND L15 GNT3 T3 GPCS5 TMRINO 20 AD1 1 BR TC AD24 GND L16 GNT4 U4 GPCS6JTMROUT1 23 AD2 AB1 W2 GND 11 GPAO J24 7 AD23 AD3 AB2 1 R1 GND M12 1 G4 GPDO C4 AD4 2 K1 GND M13 GPA2 K24 GPD1 B5 AD5 1 F2 GND 14 423 GPD2 C7 AD6 Y1 CF DRAM W24 GND M15 GPA4 124 GPD3 C8 WBMSTR2 CFG2 AD7 Y2 CF ROM GPCS AD20 GND M16 5 H24 GPD4 C9 WBMSTROJ CFGO AD8 W1 AD20 GND N11 GPA6 C1 GPD5 D9 CF ROM GPCS WBMSTRO AD9 V1 CFG1 DATASTRB AC24 GND N12 7 F23 GPD6 D10 WBMSTR1 AD10 V2 2 DRAM W24 GND N13 GPA8 M24 GPD7 C10 WBMSTR2 AD11 U2 CFG3 PITOUT2 Y24 GND N14 GPAQ C2 GPD8 C11 AD12 U1 CLKMEMIN A4 GND N15 10 M23 GPD9 12 AD13 T1 CLKMEMOUT B19 GND N16 GPA11 N23 GPD10 C13 AD14 T2 CLKPCIIN G3 GND P11 GPA12 N24 GPD11 D13 AD15 R2 CLKPCIOUT A6 GND 12 GPA13 P24 GPD12 D14 AD16 K2 CLKTEST A7 GND P13 GPA14 R24 GPD13 C15 CLKTIMER AD17 J2 CLKTIMER A7 GND 14 GPA15 RSTLDO C24 GPD14 C17 CLKTEST AD18 CMDACK U24 GND P15 GPA16 RSTLD1 024 GPD15 D17 AD19 H1 CTS1 V3 GND 16 GPA17 RSTLD2 E24 GPDACKOJPIO12 AC8 AD20 H2 CTS2 P1028 AF4 GND R11 GPA18 RSTLD3 B22 G
50. ANCE INFORMATION GP Bus DMA Read Cycle Timing Advance Information Parameter Description GP DMA clock cycle GPDRQ asserted to GPDACK assertion GPDACK asserted to GPAEN and GPDBUFOE assertion setup time for GPIOWR GPMEMWAR for non compressed and non extended write mode GPDACK asserted to GPIOWR GPMEMWR assertion GPIOWR GPMEMWR pulse width GPDACK asserted to GPTC assertion GPTC pulse width GPAEN and GPDBUFOE deasserted from command deasserted deasserted from GPDACK assertion GPDACK deasserted from command deasserted GPD hold from GPIOWR GPMEMWR setup time for GPIOWR GPMEMWR for compressed or extended write mode GPDRQ 1 gt 10 gt GPDACK GPDBUFOE I tn1 GPD15 GPDO 2 3 14 gt t5 gt GPIOWR GPMEMWR 16 gt 7 gt GPTC Figure 36 GP DMA Read Cycle Timing 70 Elan SC520 Microcontroller Data Sheet ADVANCE INFORMATION AMD GP Bus DMA Write Cycle Timing Advance Information Parameter Description GP DMA clock cycle GPDRQ to GPDACK assertion GPDACK asserted to GPAEN and GPDBUFOE assertion GPIORD GPMEMRD asserted to GPD valid GPDACK asserted to GPIORD GPMEMRD assertion GPIORD GPMEMRD pulse width GPDACK asserted to GPTC a
51. ATION Table 19 Pin List Summary Continued Signal Name Alternate Function Termination Pinstrap Max Load pF PSE GE SE SE SE SE s E SS E H Latched c Latched c Latched c Latched c Latched c Latched c A 10 Elan SC520 Microcontroller Data Sheet ADVANCE INFORMATION AMD Table 19 Pin List Summary Continued Signal Name Alternate Function Termination Pinstrap GPA21 RSTLD6 GPA22 RSTLD7 GPA23 AMDEBUG_DIS GPA24 INST_TRCE GPA25 DEBUG_ENTER GPDO GPD1 GPD2 GPD3 GPD4 GPD5 GPD6 GPD7 GPD8 GPD9 GPD10 GPD11 GPD12 GPD13 GPD14 GPD15 GPIORD GPIOWR GPMEMRD GPMEMWR GPRESET PIOO GPALE PIO1 GPBHE PIO2 GPRDY PIOS GPAEN 4 PIO5 GPDRQ3 PIO6 GPDRQ2 Max Load pF Latched Latched c Latched c Latched c Latched c O O O O J m umm Uu uuu uu w Ou Elan SC520 Microcontroller Data Sheet A 11 Signal Name Alternate Function Pi
52. Alternate Function Pinstrap SDRAM ADVANCE Table 19 Termination INFORMATION Pin List Summary Output Drive Load pF BAO 12 18 24 mA BA1 12 18 24 mA CLKMEMIN CLKMEMOUT Active 24 mA MAO H 12 18 24 mA MA1 12 18 24 mA MA2 12 18 24 mA 12 18 24 mA MA4 12 18 24 mA MAS 12 18 24 mA MA6 12 18 24 mA 12 18 24 mA MA8 12 18 24 mA 9 12 18 24 mA MA10 12 18 24 mA MA11 12 18 24 mA MA12 12 18 24 mA MDO E 0 ee 12 18 24 mA MD1 12 18 24 mA MD2 12 18 24 mA MD3 12 18 24 mA MD4 12 18 24 mA MD5 12 18 24 mA MD6 12 18 24 mA MD7 12 18 24 mA MD8 12 18 24 mA MD9 12 18 24 mA MD10 12 18 24 mA MD11 12 18 24 mA MD12 12 18 24 mA MD13 12 18 24 mA MD14 12 18 24 mA MD15 12 18 24 mA MD16 12 18 24 mA MD17 12 18 24 mA MD18 12 18 24 mA MD19 12 18 24 mA MD20 12 18 24 mA MD21 12 18 24 mA MD22 12 18 24 mA MD23 wio wio w o w o w o w o w o D O IO IO O O O O O I O O Elan SC520 Microcontroller Data Sheet 12 18 24 mA A 7 ADVANCE INFORMATION Table 19 Pin List Summa
53. Column 4 Termination The Termination column specifies the presence of pullups or pulldowns on the pins Column 5 Reset State Definitions of the abbreviations in the Reset State col umn are shown in Table 18 Column 6 Output Drive The Output Drive column shows the output amperage Column 7 Max Load pF The Max Load column designates the capacitive load at which the I O timing for that pin is guaranteed Column 8 Note The Note column shows footnote numbers INFORMATION Table 18 Pin List Summary Table Abbreviations Definition None or not applicable Brackets signify a programmable alternate state Reset configuration pin These are the configuration pins latched during reset Active Used in the Reset State column to indicate signals active during reset Analog Pin is an analog input Bidirectional Driven High a logical 1 Pin is an input Input or open drain output Driven Low a logical 0 Used in the Reset State column to indicate a signal latched on reset Not applicable Pin is an active output Open drain output Oscillator Built in pulldown resistor 100 150 Power pins Built in pullup resistor 100 150 Pin is a Schmitt trigger input Sustained three state PCI drive Three state output A 6 Elan SC520 Microcontroller Data Sheet Signal Name
54. DCD2 PIO31 RIN2 SSI_CLK SSI_DO SSI DI y 32KXTAL2 32KXTAL1 32MXTAL2 32MXTAL1 4 gt j LF PLL1 CLKTIMER CLKTEST p PWRGOOD p PRGRESET 5 BBATSEN GPA25 DEBUG ENTER GPA24 INST GPA23 AMDEBUG DIS GPA22 GPA15 RSTLD7 RSTLDO GPA13 GPAO GPD15 GPDO GPRESET GPIORD GPIOWR GPMEMRD GPMEMWR GPALE PIO1 GPBHE 2 GPRDY PIO3 GPAEN PIO4 GPTC PIO5 PIO8 GPDRQ3 GPDRQO PIO9 PIO12 GPDACK3 GPDACKO PIO13 PIO23 GPIRQ10 GPIRQO P1024 GPDBUFOE PIO25 GPIOCS16 1026 GPMEMCS16 P1027 GPCS0 GPA25 GPAO0 GPD15 GPDO MD31 MDO BOOTCS ROMCS2 ROMCS 1 GPCS2 GPCS1 ROMRD FLASHWR ROMBUFOE TMRIN1 TMRINO GPCS4 GPCS5 TMROUT1 TMROUTO GPCS6 GPCS7 PITGATE2 GPCS3 PITOUT2 CFG3 JTAG_TRST JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS CMDACK BR TC STOP TX TRIG TRACE CF_DRAM WBMSTR2 CFG2 DATASTRB WBMSTR1 CFG1 CF ROM GPCS WBMSTRO 0 GP Bus ROM Flash Timers JTAG AMDebug System Test 1 Pin names bold indicate the default pin function Brackets indicate alternate multiplexed functions Braces indicate pinstrap pins Pins noted with asterisks are duplicated in this diagram to clarify which signals are used for each interface Elan SC520 Microcontroller Data Sheet ADVANCE CONNECTION DIAGRAM 388 Pin Plastic BGA Package INF
55. E INFORMATION AMD 3 Typical 2 Best Case 1 0 T T T T 0 10 20 30 40 50 60 pF Figure 21 PCI Pads Rise Time with 1 ns Rise Fall 4 4 3 Worst Case 2 5 2 2 1 5 Best Case 1 0 5 0 0 10 20 30 40 50 60 pF Figure 22 PCI Pads Fall Time with 1 ns Rise Fall Elan SC520 Microcontroller Data Sheet 55 ADVANCE POWER CHARACTERISTICS Dynamic Icc measurements are dependent upon chip activity operating frequency output buffer logic and capacitive resistive loading of the outputs Actual power supply current is dependent on system design and may be greater or less than the typical loc number INFORMATION present here Maximum power is measured at maxi mum Vcc at maximum case temperature Typical power is measured at typical Vcc at 55 C For power dissipation values refer to Table 11 and Table 12 Table 11 Device Power Dissipation Maximum power 1 7 2 0 W Typical power 1 2 Notes 1 4 W 1 Device power dissipation calculation assumes that 50 of the I O power is consumed on chip Table 12 ANLG Power Dissipation Supply voltage level Typical VCC_ANLG current VCC_ANLG power voltage level VCC_RTC current VCC_RTC power THERMAL CHARACTERISTICS 388 Pin PBGA Package The lanSC520 microcontroller is specified for opera tion with case temperature ranges from 0 C t
56. ER Programmable Driver CLKTEST 4 gt lanSC520 Microcontroller Y Y n Note Dotted line ovals signify frequency groups PCI PCI Device Device Figure 6 System Clock Distribution Block Diagram 38 Elan SC520 Microcontroller Data Sheet ADVANCE Internal Clocks Figure 7 shows a block diagram of the ElanSC520 mi crocontroller s internal clocks The clocks are generated from two local oscillators The 32 768 kHz oscillator is used to drive PLL1 1 47456 MHz PLL which in turn drives PLL2 36 864 INFORMATION MHz PLL 36 864 2 clock is divided by 2 to produce the 18 432 MHz UART clock It is divided by 31 to produce the 1 1882 MHz PIT clock The 33 MHz oscillator produces the 33 MHz PCI and CPU clocks The 33 MHz oscillator is also used to drive PLL3 66 MHz PLL to produce the SDRAM clock 32 768 kHz RTC 32 768 kHz SDRAM Refresh 36 864 MHz DIV 31 1 1882 MHz PIT 18 432 MHz UART 32 768 kHz 32 768 kHz Crystal Oscillator 1 47456 MHz LF PLL1 33 MHz 33 MHz Crystal Oscillator Notes 33 MHz CPU 33 MHz 33 MHz GP Bus 33 MHz GP DMA 33 MHz ROM 33 MHz 551 1 33 MHz Timers 66 MHz SDRAM 1 Includes the programmable interval timer PIT general purpose timers watchdog timer and the software timer F
57. Estimate based on 3 3 V operation Current for the supply is constant independent of the CPU frequency 2 Value determined by simulation will be updated once characterization is complete 3 Current measured with power applied only to the supplies 4 I O 3 6 V 5 Table 19 Pin List Summary on page A 7 shows which pins have internal pullups or pulldowns 50 Elan SC520 Microcontroller Data Sheet ADVANCE CAPACITANCE Interface Pin Capacitance Parameter Description Cin Input capacitance INFORMATION Test Conditions i Max CaokxrAL 32KXTAL1 33KXTAL2 pin capacitance 1 33MXTAL2 pin capacitance Ca3MXTAL Cour Output capacitance Cio pin capacitance PCI Interface Pin Capacitance Pin capacitance values are specified in the PCI Local Bus Specification Revision 2 2 section 4 2 2 1 DC Specifications Table 4 3 DC Specifications for 3 3V Signaling Crystal Capacitance The crystal specifications can be found in Table 8 32 768 kHz Crystal Specifications on page 42 and Table 9 33 MHz Crystal Specifications on page 42 Advance Information Derating Curves All programmable I O pins can be driven to the maxi mum drive current at once The derating curves on the following pages can be used to determine potential specified timing variations based on system capacitive loading Table 19
58. GPA7 GPMEMRD SCASA SCASB CORE GPIORD SDQMO SDQM2 CORE GPA5 SDQMS3 SDQM1 GPA3 GPAO SCS2 SCS3 GPA2 SRASA SRASB GND GND GND GPA4 MAO MA1 GND GND GND 10 GPA8 MA3 MA2 GND GND GND GPA11 GPA12 MA4 MA5 GND GND GND VCC CORE GPA13 MA7 MA6 GND GND GND VCC CORE GPA14 MA8 MA9 GND GND GND NC NC BA0 MA10 SOUT2 CMDACK 1 MA11 SIN2 SCSO MA12 SCS1 MECC2 WBMSTR2 CFG2 PITOUT2 6 TMRIN1 54 ROMRD FLASHWR BOOTCS 33MXTAL1 CORE VCC_CORE ING NC TMRINO PITGATE2 IIMROUT1 DATASTRB INC 33MXTAL2 GPCS5 GPCS3 56 WBMSTR1 1 NC NC NC NC NC 55 CF_ROM_ JTAG_TCK RTS2 TMROUTO BR TC NC NC GPCS GPCS7 WBMSTRO NC NC NC NC NC SSI_DI NC JTAG_TMS JTAG_TRST DTR2 NC NC 32KXTAL2 NC NC NG STOP TX SSI NC JTAG TDI TDOINC LF PLL1 32KXTAL1 14 15 16 17 18 19 20 21 22 23 24 25 26 Elan SC520 Microcontroller Data Sheet A m gt Z r X DESIGNATIONS This section identifies the pins of the ElanSC520 micro controller and lists the signals associated with each pin In all tables the brackets indicate alternate multi plexed functions and braces indicate reset config
59. GPIRQO signals and they go to the same interrupt controller They are named INTx to match the common PCI interrupt naming convention Configuration registers allow inversion of these interrupt requests to recognize active low interrupt requests These interrupt requests can be routed to generate NMI Initiator Ready is asserted by the current bus master to indicate that data is ready on the bus write or that the master is ready to accept data read PCI Parity is driven by the initiator or target to indicate parity on the AD31 ADO and buses Parity Error is asserted to indicate a PCI bus data parity error in the previous clock cycle REQ4 REQO Bus Requests are asserted by the master to request access to the bus RST Reset is asserted to reset the PCI devices System Error is used for reporting address parity errors or any other System error where the result is catastrophic Stop is asserted by the target to request that the current bus transaction be stopped Target Ready is asserted by the currently addressed target to indicate its ability to complete the current data phase of a transaction General Purpose Bus GP Bus GPA14 GPA0 O General Purpose Address Bus outputs the physical memory or I O GPA15 RSTLDO port address Twenty six address lines provide maximum addressable space of 64 Mbytes This bus also provides the address GPA16 RSTLD1 O to the s
60. ORMATION Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 AD30 AD31 NC CLKMEMIN RST CLK CLKTIMER 1 MD17 MD3 MD19 MD5 MD21 PCIOUT CLKTEST AD29 AD28 NC NC GPD1 NC MD0 MD16 MD2 MD18 MD4 MD20 MD6 GPA6 GPA9 GPA25 GPD0 NG NC GPD2 GPD3 GPD4 GPD7 GPD8 GPD9 GPD10 DEBUG_ ENTER D AD26 AD27 GPA23 GPA24 VCC VCC VCC l O GPD5 GPD6 CORE VCC GPD11 AMDEBUG INST _TRCE E AD25 AD24 NG CORE AD23 CBE3 GPA22 CORE RSTLD7 G AD22 AD21 CLKPCIIN GPA1 AD19 AD20 INTC INTD 9 AD18 AD17 INTB K 2 AD16 INTA L IRDY REQO VCC_I O GND GND GND DEVSEL TRDY GNTO VCC_I O GND GND GND 5 PERR REQ1 GNT1 GND GND GND SERR GNT2 REQ2 GND GND GND R CBE1 AD15 REQ3 GND GND GND AD13 AD14 GNT3 GND GND GND U AD12 AD11 REQ4 GNT4 V AD9 AD10 CTS1 DCD1 W AD8 CBEO DTR1 RTS1 Y AD6 AD7 DSR1 AD5 AD4 RIN1 AB AD2 ADS NC NC AC 1 ADO NC 025 CORE CORE VCC CORE PIO12 PIO11 VCC_I O VCC_I O NC TRIG GPIOCS16 GPDACK1 TRACE AD NC NC PIO31 026 24 19 PIO18 PIO13 PIO10 PIO5 4 NC RIN2 GPDBU
61. PDACKT PIO11 9 AD21 G2 DATASTRB AC24 GND R12 GPA19 RSTLD4 C21 GPDACK2 PIO10 AD9 WBMSTR1 CFG1 AD22 G1 DCD1 V4 GND R13 GPA20 RSTLD5 C14 9 9 AD23 1 DCD2 PIO30 AES GND R14 GPA21 RSTLD6 C19 PDBUFOE AD5 24 24 2 DEBUG_ENTER C3 GND R15 GPA22 RSTLD7 GPDRQO PIO8 AF9 GPA25 AD25 E1 DEVSEL M1 GND R16 GPA23 D3 GPDRQ1 PIO7 AF10 AMDEBUG_DIS AD26 D1 DSR1 Y3 GND T11 GPA24 D4 GPDRQ2 PIO6 AE10 INST_TRCE AD27 D2 DSR2 P1029 GND T12 GPA25 C3 5 AD10 DEBUG_ENTER AD28 B2 DTR1 W3 GND T13 AE11 GPIOCS16 PIO25 4 AD29 B1 DTR2 AE23 GND 114 GPALE PIOO AE12 GPIORD G24 AD30 A1 FLASHWR AB24 GND T15 GPBHE PIO1 12 GPIOWR C16 AD31 A2 FRAME L1 GND T16 GPCSO PIO27 4 GPIRQO PIO23 5 Elan SC520 Microcontroller Data Sheet 13 AMD ADVANCE INFORMATION Pin Designations Pin Name Continued Signal Name E sona Name Pns Signal Name e Name Pin Signal Name Lr GPIRQ1 PIO22 MD31 24 PIO12 GPDACKO AC GPIRQ2 PIO21 AF6 MA9 R26 C25 NC AE25 PIO13 GPIRQ10 AD8 GPIRQ3 PIO20 AE6 T26 MECC1 D26 NC AF1 PIO14 GPIRQ9 AE8 GPIRQ4 PIO19 6 MA11 U26 MECC2 W26 NC AF13 PIO15 GPIRQ8 AF8 GPIRQ5 PIO18 AD7 12 v26 MECC3 Y25 AF14 PIO16 GPIRQ7
62. Q3 R3 MAO L25 MD23 A15 NC AE1 PIO4 GPTC AD11 REQ4 U3 MA1 126 MD24 B16 NC AE13 AD10 RINT AA3 MA2 M26 MD25 A17 NC 14 PIO6 GPDRQ2 AE10 RIN2 PIO31 AD3 MA3 M25 MD26 B18 AE15 PIO7 GPDRQ1 AF10 ROMBUFOE 25 MA4 N25 MD27 19 NC 16 PIOS GPDRQO AF9 ROMCS1 GPCS1 B24 MA5 N26 MD28 A20 NC 17 PIOS GPDACK3 9 ROMCS2 C23 GPCS2 MA6 P26 MD29 B21 NC 18 PIO10 GPDACK2 AD9 ROMRD AB23 MA7 25 MD30 A23 NC 20 PIO11 GPDACK1 AC9 RST 5 14 Elan SC520 Microcontroller Data Sheet ADVANCE INFORMATION AMD Pin Designations Pin Name Continued Sinai Name _ Name Ping Signet Name Pin Signal Name _ Pin RSTLDO GPA15 TMRINO GPCS5 20 VCC_CORE VCC_I O RSTLD1 GPA16 TMRIN1 GPCS4 24 VCC CORE VCC RSTLD2 GPA17 TMROUTO AD23 VCC_CORE VCC_I O GPCS7 RSTLD3 GPA18 SERR TMROUT1 AC23 CORE GPCS6 RSTLD4 GPA19 SIN1 TRDY M2 VCC_CORE VCC_I O J4 RSTLD5 GPA20 SIN2 TRIG TRACE VCC_CORE VCC_I O RSTLD6 GPA21 SOUT1 VCC_ANLG VCC_CORE VCC_I O K4 RSTLD7 GPA22 SOUT2 VCC_CORE VCC_I O VCC_I O L4 RTS1 SRASA VCC_CORE VCC_I O L23 SRASB VCC CORE VCC 551 VCC_I O VCC_I O V23 SSI DI VCC CORE VCC_I O VCC_I O W23 SSI_DO VCC CORE VCC_I O VCC_I O Y4 STOP VCC_CORE VCC_I O VCC_I O Y23 STOP TX VCC CO
63. RE VCC_I O VCC_RTC A26 SWEA VCC_CORE VCC_I O WBMSTROJCFGO 20 CF_ROM_GPCS SWEB VCC_CORE VCC_I O WBMSTR1 CFG1 24 DATASTRB WBMSTR2ICFG2 W24 CF DRAM Notes 1 See Table 16 on page A 4 for PIOs sorted by pin number Elan SC520 Microcontroller Data Sheet 15 SIGNAL DESCRIPTIONS Table 2 Signal Descriptions on page 17 contains a description of the ElanSC520 microcontroller signals The microcontroller contains 258 signal pins in addition to power and ground pins in a Plastic Ball Grid Array PBGA package Table 1 describes the terms used in the signal descrip tion table The signals are organized alphabetically within the following functional groups Synchronous DRAM page 17 ROM Flash page 18 PCI bus page 18 GP bus page 19 Serial ports page 21 Clocks and reset page 22 JTAG page 23 AMDebug Interface page 23 System test page 23 Chip selects page 24 Programmable I O PIO page 25 Timers page 25 Configuration page 26 Power page 27 ADVANCE IN FORMATION Table 1 Signal Descriptions Table Definitions Term Definition General Terms Indicates the pin alternate function a pin defaults to the signal named without the brackets B Indicates the reset configuration pin pinstrap pin Refers to the physical wire signal Refers to the electrical signal that flows across a pin SIGNAL A line over
64. SB GPA4 MA6 MECCO AD22 CBE1 AD21 AD15 AD26 CLKPCIIN AD27 GPA1 VCC CORE GPA23 AMDEBUG DIS VCC CORE GND GPA24 INST TRCE GPIORD GND SDQMO GND VCC SDQM2 GND VCC_I O AD19 GND VCC_I O AD20 GND GPD5 VCC CORE GPD6 Elan SC520 Microcontroller Data Sheet GPA14 11 ADVANCE INFORMATION Pin Designations Pin Number Continued La e Name La Signal Name La Signal Name Pins e Name Pin Signal Name DTR1 VCC_CORE JTAG_TMS 9 51 VCC_CORE NC JTAG_TRST AD13 VCC CORE NC DTR2 AD14 CF DRAM WBMSTR2ICFG2 PIO12 GPDACKO NC NC GNT3 SCS1 PIO11 GPDACK1 NC NC VCC CORE MECC2 VCC NC 32KXTAL2 GND AD6 VCC SSI CLK NC GND AD7 NC CF_ROM_GPCS WBMSTROJICFGO SOUT1 GND DSR1 TRIG TRACE JTAG TCK PIO29 DSR2 GND VCC_I O VCC_CORE RTS2 PIO28 CTS2 GND VCC_I O VCC_CORE TMROUTO GPCS7 PIO22 GPIRQ 1 GND PITOUT2 CFG3 NC BR TC PIO21 GPIRQ 2 NC MECC3 NC NC PIO16 GPIRQ7 NC MECC6 VCC_I O NC PIO15 GPIRQ8 BAO AD5 VCC_I O NC PIO8 GPDRQO MA10 AD4 TMRINO GPCS5 PIO7 GPDRQ1
65. Thin Client Reference Design 35 Figure 4 Elan SC520 Microcontroller Based Digital Set Top Box Reference Design 36 Figure 5 Elan SC520 Microcontroller Based Telephone Line Concentrator Reference ET c 37 Figure 6 System Clock Distribution Block Diagram 38 Figure 7 Clock Source Block Diagram ettet ee reticere eng 39 Figure 8 32 768 kHz Crystal Circuit ptr teer err e eoe Be eed cs 41 Figure 9 33 333 2 Third Overtone Crystal Implementation 43 Figure 10 Bypassing the 32 768 kHz Oscillator 2 44 Figure 11 Bypassing the 33 MHz Oscillator 0 44 0 44 Figure 12 RTC Voltage Monitor Block Diagram 2 45 Figure 13 Circuit with Backup Battery teen he nia rena 47 Figure 14 Circuit without Backup Battery toes 47 Figure 15 I O Drive 6 mA Rise Time 52 Figure 16 I O Drive 6 mA Fall Time Pre Dette puedas 52 4 Elan SC520 Microcontroller Data Sheet ADVANCE INFORMATION AMD Figure 17 I O Drive 12 mA Rise Time eet eed ene 53 Figure 19 I O Drive 12 mA Fall Time 53 Figure 19 Drive 24 mA Rise Time 54 Figur
66. a reset signal that indicates to the ElanSC520 microcontroller that the Vcc levels are within the normal operation range It is used to reset the entire chip and must be held Low for one second after all Vcc signals except VCC_RTC on the chip are High This signal must be returned Low before the Vcc signals degrade to put the RTC into the correct state for operation in RTC only mode 22 Elan SC520 Microcontroller Data Sheet ADVANCE INFORMATION AMD Table 2 Signal Descriptions Continued Multiplexed gm a lt JTAG JTAG_TCK Test Clock is the input clock for test access port JTAG_TDI Test Data Input is the serial input stream for input data This pin has a weak internal pullup resistor It is sampled on the rising edge of JTAG_TCK If not driven this input is sampled High internally JTAG_TDO Test Data Output is the serial output stream for result data It is in the high impedance state except when scanning is in progress JTAG_TMS Test Mode Select is an input for controlling the test access port This pin has a weak internal pullup resistor If it is not driven it is sampled High internally JTAG_TRST AMDebug Interface JTAG Reset is the test access port TAP reset This pin has a weak internal pulldown resistor If not driven this input is sampled Low internally and causes the TAP controller logic to remain in the reset state BR TC Break Request Trace Capture requ
67. a signal name indicates that the signal is active Low a signal name without a line is active High Signal Types Analog Analog voltage Bidirectional High Input Programmable to hold last state of pin Totem pole output Totem pole output three state output Open drain output Open drain output or totem pole output Oscillator Internal pulldown resistor 100 150 Power pins Internal pullup resistor 100 150 Schmitt trigger input Schmitt trigger input or open drain output Three state output 16 Elan SC520 Microcontroller Data Sheet ADVANCE INFORMATION AMD Table 2 Signal Descriptions Multiplexed 8 Synchronous DRAM BA1 BAO Bank Address is the SDRAM bank address bus CLKMEMIN SDRAM Clock Input is the SDRAM clock return signal used to minimize skew between the internal SDRAM clock and the CLKMEMOUT signal provided to the SDRAM devices This signal compensates for buffer and load delays introduced by the board design CLKMEMOUT SDRAM Clock Output is the 66 MHz clock that provides clock signaling for the synchronous DRAM devices This clock may require an external Low skew buffer for system implementations that result in heavy loading on the SDRAM clock signal 12 0 SDRAM Address is the SDRAM multiplexed address bus MD31 MDO SDRAM Data Bus inputs data during SDRAM read cycles an
68. able sampling window Within the sampling window a synchronous input sig nal must be stable for correct microcontroller operation WAVEFORMS INPUTS OUTPUTS Must be Steady May Change from H to L May Change from L to H Don t Care Any Change Permitted Does Not Apply AC SWITCHING TEST WAVEFORMS Bus Interface Pins Will be Steady Will be Changing from H to L Will be Changing from L to H Changing State Unknown Center Line is High Impedance Off State 2 Test Points l O 2 0 Input Output Note For AC testing inputs are driven at 3 V for a logic 1 0 V for a logic 0 Figure 25 AC Switching Test Waveforms PCI Bus Interface Pins For AC timing for PCI bus interface pins refer to the PCI Local Bus Specification Revision 2 2 4 2 3 3 Measurement and Test Conditions Figure 4 7 Output Timing Measurement Conditions and Figure 4 8 Input Timing Measurement Conditions 58 Elan SC520 Microcontroller Data Sheet ADVANCE INFORMATION AMD SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES In this section the following timings and timing wave m SDRAM clock page 67 forms are shown GP bus page 68 GP bus DMA read page 70 GP bus DMA write page 71 SSI page 72 JTAG page 73 Power on reset page 59 Reset page 61 ROM page 63 PCI bus page 65 SDRAM page 66 Power On Reset Timing Advance In
69. ace 32 System test and debug features 32 System test multiplexed signal trade offs A 3 System test pin summary A 13 System test signal descriptions 23 thermal characteristics 56 equations 57 timers description 32 multiplexed signal trade offs A 3 pin summary A 14 signal descriptions 25 timing See switching characteristics and waveforms U UARTs description 32 V voltage for interface pins 49 for PCI interface pins 49 maximum ratings 48 operating ranges 48 Index 4 lanTMSC520 Microcontroller Data Sheet ADVANCE INFORMATION Trademarks AMD the AMD logo and combinations thereof AMD Athlon Elan AMDebug PCnet E86 Am186 Am188 and Comm86 are trademarks Am5 86 Am386 Am486 and AMD K6 are registered trademarks and FusionE86 is a servicemark of Advanced Micro Devices Inc Microsoft and Windows are registered trademarks of Microsoft Corporation Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies Disclaimer The contents of this document are provided in connection with Advanced Micro Devices Inc AMD products AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifi cations and product descriptions at any time without notice No license whether express implied arising by estoppel or
70. acies cause the period of CLKPCIOUT to become marginally less than 30 ns It is up to the system designer to choose the accuracy of the crystal used with the lanSC520 microcontroller The 33 000 MHz frequency provides a better guard band than the 33 333 MHz crystal In practice most PCI devices can tolerate both frequencies but it is im portant to be aware of the impact of choosing the crys tal on this potential violation of the PCI bus specifications The PCI bus specification requires that the minimum clock period be 30 ns Elan SC520 Microcontroller Data Sheet AMD 43 ADVANCE INFORMATION Bypassing Internal Oscillators The 32 768 kHz and the 33 MHz ElanSC520 micro external clock to the crystal pins Refer to Figure 10 controller oscillators can be bypassed by connecting an and Figure 11 for the suggested circuitry External 2 5 V max 32 768 kHz 32KXTAL2 Oscillator 100 ko m 2 lanSC520 Microcontroller Figure 10 Bypassing the 32 768 kHz Oscillator External 2 5 max 33 MHz 33MXTAL2 Oscillator No Connect 33MXTAL1 ElanSC520 Microcontroller Figure 11 Bypassing 33 MHz Oscillator 44 Elan SC520 Microcontroller Data Sheet ADVANCE INFORMATION VBG 2 0 V Voltage Amplifier Generator One RTC Reset Shot ta L BBATSEN PWRGOOD Internal RTC Power Down ed Q gt gt Flip Flop 32
71. ammed as inputs or outputs When they are outputs they can be driven High or Low by programming bits in registers PITGATE2 PITOUT2 GPCS3 CFG3 Programmable Interval Timer 2 Gate provides control for the PIT Channel 2 Programmable Interval Timer 2 Output is output from the PIT Channel 2 This signal is typically used as the PC speaker signal TMRINO 1 GPCS5 GPCS4 Timer Inputs 0 and 1 can be programmed to be the control or clock for the general purpose GP timers 0 and 1 TMROUTO TMROUT1 GPCS7 GPCS6 O O Timer Outputs 0 and 1 are outputs from two of the GP timers These outputs can be used as pulse width modulation signals lanTMSC520 Microcontroller Data Sheet 25 AMD ADVANCE INFORMATION Table 2 Signal Descriptions Continued Multiplexed E __ section 000000 Configuration AMDEBUG_DIS GPA23 AMDebug Disable is an active High configuration signal latched at the assertion of Power Good PWRGOOD This pin has a built in pulldown resistor At Power Good assertion Low Normal operation mode can be enabled by software High AMDebug mode is disabled and cannot be enabled by software CFGO CF_ROM_GPCS Configuration Inputs 3 0 are latched into the chip when PWRGOOD WBMSTRO is asserted These signals are all shared with other features These signals have built in pulldown resistors 0 Choose 8 16
72. application notes the E86 Family Prod ucts and Development Tools CD order 21058 and other literature is available with a simple phone call In ternationally contact your local AMD sales office for product literature Additional contact information is listed on the back of this data sheet Literature Ordering 800 222 9323 512 602 5651 Direct dial worldwide 512 602 7639 Fax Toll free for U S and Canada Elan SC520 Microcontroller Data Sheet C 3 ADVANCE INDEX a20 gate 32 address mapping 31 AMDebug technology description 30 parallel 30 pin summary A 13 serial 30 signal descriptions 23 applications description 33 digital set top box 36 Smart Residential Gateway 34 thin client 35 architecture overview 28 x86 instruction set 30 B block diagram 29 bootstraps See configuration capacitance crystal 51 derating curves 51 non PCl interface 51 PCI interface 51 chip select GP bus signal description 24 circuit board layout B 3 clock 32 768 kHz crystal selection 41 33 333 MHz crystal speed 43 33 MHz crystal selection 42 backup battery 46 circuit diagrams 47 block diagram of clock source 39 bypassing internal oscillators 44 circuit with backup battery 47 circuit without backup battery 47 control 38 crystal selection 41 INFORMATION AMD crystal speeds 38 generation and control 38 internal 39 multiplexed signal trade offs A 3 not using backup battery 4
73. are inserted in the current cycle This pin has an internal weak pullup that should be supplemented by a stronger external pullup for faster rise time GPRESET GP Bus Reset when asserted re initializes to reset state all devices connected to the GP bus GPTC GP Bus Terminal Count is driven from the internal DMA controller to indicate that the transfer count for the currently active DMA channel has reached zero and that the current DMA cycle is the last transfer Serial Ports CTS2 CTS1 Clear To Send is driven back to the serial port to indicate that the external data carrier equipment DCE is ready to accept data DCD1 Data Carrier Detect is driven back to the serial port from a piece of DCD2 DCE when it has detected a carrier signal from a communications target DSR1 Data Set Ready is used to indicate that the external DCE is ready to DSR2 029 establish a communication link with the internal serial port controller DTR2 DTR1 O Data Terminal Ready indicates to the external DCE that the internal serial port controller is ready to communicate RIN1 Ring Indicate is used by an external modem to inform the serial port RIN2 PIO31 that a ring signal was detected RTS2 RTS1 O Request To Send indicates to the external DCE that the internal serial port controller is ready to send data SIN2 SIN1 Serial Data In is used to receive the seria
74. d outputs data during SDRAM write cycles MECC6 MECCO Memory Error Correction Code contains the ECC checksum syndrome bits used to validate and correct data errors SCASA SCASB Column Address Strobes are used in combination with the SRASA SRASB and SWEA SWEB to encode the SDRAM command type SCASA and SCASB are the same signal provided on two different pins to reduce the total load connected to CAS Suggested system connection SCASA for SDRAM banks 0 and 1 SCASB for SDRAM banks 2 and 3 5 53 5 50 SDRAM Chip Selects are the SDRAM chip select outputs These signals are asserted to select a bank of SDRAM devices The chip select signals enable the SDRAM devices to decode the commands asserted via SRASA SRASB SCASA SCASB SWEA SWEB SDQMS SDQMO Data Input Output Masks make SDRAM data output high impedance and blocks data input on SDRAM while active Each of the four SDQM3 SDQM0 signals is associated with one byte of four throughout the array Each SDQM x signal provides an input mask signal for write accesses and an output enable signal for read accesses SRASA SRASB Row Address Strobes are used in combination with the SCASA SCASB and SWEA SWEB to encode the SDRAM command type SRASA and SRASB are the same signal provided on two different pins to reduce the total load connected to RAS Suggested system connection SRASA for SDRAM banks 0 and 1 SRASB for SDRAM banks 2 and
75. de 3 These timings apply only when powering down the chip while leaving only the RTC powered 4 Guarantees at least one rising edge on the 32 kHz signal after reset before 2 V is reached Figure 27 PWRGOOD Timing for RTC Standalone Mode 60 Elan SC520 Microcontroller Data Sheet ADVANCE INFORMATION AMD Reset Timing with Power Applied Advance Information Parameter Description PWRGOOD inactive pulse width CFGx RSTLDx setup to PWRGOOD active CFGx RSTLDx hold from PWRGOOD active PWRGOOD inactive to GPRESET RST outputs active PWRGOOD active to GPRESET RST outputs inactive PRGRESET active pulse width PRGRESET active to GPRESET RST outputs active PRGRESET inactive to GPRESET RST outputs inactive Reset outputs GPRESET RST active pulse width for internally generated system reset Notes 1 Internal system reset sources include software system reset SYS bit AMDebug interface system reset and watchdog timer reset ti gt 12 PWRGOOD CFGx RSTLDx t5 4 GPRESET SENS ha t5 gt RST Sa Figure 28 External System Reset Timing with Power Applied Elan SC520 Microcontroller Data Sheet 61 62 AMD ADVANCE INFORMATION t6 gt PRGRESET Ier t8 gt GPRESET 17 gt 18 gt RST Figure 29 PRGRESET Timing 9 gt GPRESET
76. derations The behavior of the RTC when the primary power sup ply is turned off depends on whether or not an external backup battery is included in the system design Using an External RTC Backup Battery An implementation using a backup battery is shown in Figure 13 on page 47 The primary power source for is the main power plane VCC D1 should be chosen so that the forward voltage drop is small less than 0 25 V D1 also prevents the backup battery from powering up the VCC power plane when the main sup ply is turned off The backup battery voltage must not exceed 3 3 V af fects the BBATSEN and VCC_RTC pins higher volt ages may damage the ElanSC520 microcontroller The RC network composed of R1 and C2 provides a time delay for the internal circuit power up sequence Accuracy tolerances are 1096 of nominal values given in Table 10 C1 is for high frequency filtering purposes Not Using an External RTC Backup Battery For the system that is not using a backup battery Figure 14 on page 47 shows how the circuit should be designed It uses the same RC that is needed by the battery system but it is now connected to VCC_RTC For this configuration the RTC is invalidated after power up but is not invalidated by subsequent PWR GOOD assertions W The RTC is invalidated after a power up In this case power has been removed from the RTC so it should be invalidated m When reset switch tied to PWRGOOD is pr
77. designed to gener ate all of the internal and system clocks it requires The lanSC520 microcontroller includes on chip oscillators and PLLs as well as most of the required PLL loop filter components The ElanSC520 microcontroller requires two standard crystals one for 32 768 kHz and one for 33 MHz All the clocks required inside the lanSC520 microcontroller are generated from these crystals Output clock pins are provided for selected clocks pro viding up to 24 mA of sink or source current INFORMATION The lanSC520 microcontroller also supplies the clocks for SDRAM and PCI bus however external clock buffering may be required in some systems Figure 6 shows a system block diagram of the ElanSC520 microcontroller s external clocks Note The lanSC520 microcontroller supports either a 33 000 MHz or 33 333 MHz crystal In this docu ment the generic term 33 MHz refers to the system clock derived from whichever 33 MHz crystal fre quency is being used in the system VCC ANLG m 32KXTAL1 32 768 kHz 2 Crystal i cn 32KXTAL2 4 R1 q ___ 93MXTAL1 Optional 33 MHz LF_PLL1 Clock SDRAM Crystal Driver 2 pod ME Vd ___ 56 MHz gt CLKMEMIN a 5 CLKPCIIN lg T133MHz cLKPCIoUT 33 MHZ amp Optional 133 MHz Clock CLKTIM
78. e 20 I O Drive 24 mA Fall Time taedio 54 Figure 21 PCI Pads Rise Time with 1 ns 55 Figure 22 PCI Pads Fall Time with 1 ns 55 Figure 23 Thermal Resistance C Watt 2 56 Figure 24 Thermal Characteristics Equations 2 57 Figure 25 Switching Test Waveforms 58 Figure 26 Power Up Timing Sequence tope siete etie eu buda gu e bas pueda 60 Figure 27 PWRGOOD Timing for RTC Standalone Mode 60 Figure 28 External System Reset Timing with Power Applied 61 Figure 29 PHRORESET TIMING rnit eui taedet eio t neca tete lege 62 Figure 30 Internal System Reset Timing 2 nennen 62 Figure 31 Non Burst ROM Read Cycle Timing 2 2 4 44 64 Figure 32 Page Mode ROM Read Cycle Timing 2 64 Figure 33 Flash Write Cycle Timing eua bene e e e ta 65 Figure 34 SDRAM Clock Timing 67 Figure 35 GP Bus Non DMA Cycle Timing 69 Figure 36 GP DMA Read Cycle 70 Figure 37 GP DMA Write Cycle Timing
79. e clock period assuming minimal delay between the CLKMEMOUT output and the CLKMEMIN input It does not take into account external delays for clock buffering skew clock loading routing and data loading routing The delays that the system designer must take into consideration are identified by the equation below Tac TskEw Lp lt where Tac Access time of SDRAM device not impacted by board design Delay between CLKMEMOUT to CLKMEMIN Additional clock delay due to loading Data delay due to loading SDRAM memory clock 15 ns assumes 33 333 MHz crystal 66 Elan SC520 Microcontroller Data Sheet ADVANCE INFORMATION AMD SDRAM Clock Timing Advance Information Symbol Parameter Description Notes CLKMEMOUT period CLKMEMOUT High time CLKMEMOUT Low time CLKMEMIN delay rising from CLKMEMOUT rising Notes 1 This parameter is based on a PLL 2x multiplier of the frequency of the 33 MHz crystal The value is affected by the chosen frequency of the crystal 33 000 MHz or 33 333 MHz CLKMEMOUT CLKMEMIN E 3 Figure 34 SDRAM Clock Timing Elan SC520 Microcontroller Data Sheet 67 ADVANCE INFORMATION GP Bus Timing Parameter Description Setup GPA GPBHE stable to command assertion 8 16 bit and memory access Advance Information Min OFFS 1 30
80. e cycle 71 integrated controller 31 timing 68 documentation ground See customer support pin summary A 14 DRAM See SDRAM H hotline and world wide web support C 3 Elan SC520 microcontroller application examples 33 architectural overview 28 block diagram 29 51 programmable I O PIO signal descriptions 25 circuit board layout B 3 interrupts DC characteristics 50 programmable interrupt controller PIC 31 distinctive characteristics 1 documentation C 2 general description 1 J logic diagram by default pin function 7 JTAG logic diagram by interface 6 maximum ratings 48 boundary scan test interface 32 pin summary A 13 operating ranges 48 de ordering information 2 signal descriptions 23 PBGA package B 1 timing 73 peripherals overview 31 physical dimensions B 1 pin connection diagram 8 L pin designations 10 literature pin tables Appendix A A 1 See customer support power characteristics 56 programmable address region PAR registers 31 related AMD E86 family devices C 1 switching characteristics and waveforms 58 thermal characteristics 56 logic diagram by default pin function 7 by interface 6 voltage levels 48 49 M maximum ratings 48 F multiplexed functions Flash signal trade offs A 2 addressing mapping 31 controller description 30 N multiplexed signal trade offs A 2 pin summary A 8 no connect NC signal descriptions
81. ead cycles WBMSTR1 DATASTRB WBMSTR1 when a logical 1 indicates that the PCI master has CFG1 contributed to the write buffer rank write cycles or is reading from SDRAM read cycles WBMSTR2 CF_DRAM WBMSTR2 when a logical 1 it indicates that the CPU has contributed CFG2 to the write buffer rank write cycles or is reading from SDRAM read cycles Chip Selects GPCSO PIO27 O General Purpose Chip Select signals are for the GP bus They can GPCST ROMGS1 be used for either memory or I O accesses These chip selects SYED asserted for Am5 86 CPU accesses to the corresponding regions set GPCS2 ROMCS2 o up in the Programmable Address Region PAR registers GPCS3 PITGATE2 O GPCS4 TMRIN1 GPCS5 TMRINO GPCS6 TMROUT1 GPCS7 TMROUTO 24 Elan SC520 Microcontroller Data Sheet ADVANCE INFORMATION Table 2 Signal Descriptions Continued Multiplexed LANE asas wuW Programmable I O PIO Timers GPALE GPBHE GPRDY GPAEN GPTC GPDRQ3 GPDRQ2 GPDRQ1 GPDRQO GPDACK3 GPDACK2 GPDACK1 GPDACKO GPIRQ1 0 GPIRQS GPIRQ8 GPIRQ7 GPIRQ6 GPIRQ5 GPIRQ4 GPIRQ3 GPIRQ2 GPIRQ1 GPIRQO GPDBUFOE GPIOCS16 GPMEMCS16 GPCS0 CTS2 DCD2 RIN2 U UU U UU 0 m Programmable Input Output signals can be progr
82. er evaluation of AMD products as well as FusionE86 partner tools and technologies that support the E86 family Technical documen tation is included on the CD in PDF format To order literature contact the nearest AMD sales of fice or call the literature center at one of the numbers listed on the back cover of this manual In addition all these documents are available in PDF form on the AMD web site To access the AMD home page go to www amd com Then follow the Embedded Processor link for information about E86 microcontrollers Additional Information The following non AMD documents and sources pro vide additional information that may be of interest to ElanSC520 microcontroller users PCI Local Bus Specification December 18 1998 PCI Special Interest Group 800 433 5177 US 503 693 6232 International www pcisig com Std 1149 1 1990 Standard Test Access Port and Boundary Scan Architecture order SH16626 NYF Institute of Electrical and Elec tronic Engineers Inc 800 678 4333 www ieee org W PCI System Architecture Mindshare Inc Reading MA Addison Wesley 1995 ISBN 0 201 40993 3 ISA System Architecture Mindshare Inc Reading MA Addison Wesley 1995 ISBN 0 201 40996 8 INFORMATION W 80486 System Architecture Mindshare Inc Read ing MA Addison Wesley 1995 ISBN 0 201 40994 1 W 7he Indispensable PC Hardware Book Hans Peter Messmer Wokingham England Addison Wesley
83. er includes a simple gen eral purpose bus GP bus that provides programma ble bus timing and allows the connection of 8 16 bit peripheral devices and memory to the ElanSC520 mi crocontroller The GP bus operates at 33 MHz which offers good performance at a very low interface cost The lanSC520 microcontroller provides up to eight chip selects for external GP bus devices such as off the shelf I O peripherals custom ASICs and SRAM or NVRAM The GP bus interface supports programmable timing and dynamic bus width and cycle stretching to accommodate a wide variety of standard peripherals such as UARTs 10 Mbit LAN controller chips and se rial communications controllers Up to four external DMA channels provide fly by DMA transfers between peripheral devices on the GP bus and system SDRAM Internally the GP bus is used to provide a complement of integrated peripherals such as a DMA controller programmable interrupt controller timers and UARTs as described in Integrated Peripherals on page 31 These internal peripherals are designed to operate at the full clock rate of the GP bus The internal peripher als can also be configured to operate in PC AT compat ible configuration but are generally not restricted to this configuration The ElanSC520 microcontroller provides way to view accesses to the internal peripherals on the external GP bus for debugging purposes INFORMATION Clock Generation The ElanSC52
84. er mask opening of 0 60 mm over a 0 80 mm pad as shown in Figure 40 P Side View of BGA Pad Figure 40 BGA Ball Pad Layout Elan SC520 Microcontroller Data Sheet B 3 APPENDIX CUSTOMER SUPPORT Am386 8X D Microprocessors Am4868DX V Microprocessor AMD AMD K6 2 Microprocessor AMD K6 E lt Microprocessor Am5 86 7 Microprocessor ElanSC520 Microcontroller lan SC310 Microcontroller Microcontroller Am186 CU USB Microcontroller 80C186 and 80C188 Microcontrollers ElanSC400 _ Y Microcontroller ElanSC410 gt Microcontroller ElanSC300 186 Communications EE Controller m Am186CH HDLC Am186ER and 7 Microcontroller Microcontroller Am188ER Am186ES and Microcontrollers Am186EDLV Am188ES Microcontroller Am186EM and Microcontrollers Am188 EM Am186ESLV amp Microcontrollers Am188ESLV Am186EMLV amp Microcontrollers JAN Microprocessors Am188EMLV 80L186 and 80L188 Microcontrollers Microcontrollers 16 and 32 bit microcontrollers 16 bit microcontrollers E86 Family of Embedded Microprocessors and Microcontrollers Device 80C186 80C188 80L186 80L 188 Am186 EM Am188 EM Am186EMLV Am188EMLV Am186ES Am188ES Am186ESLV Am188ESLV Am186ED Am186EDLV Am186ER Am188ER Am186CC Am186CH Am186CU ElanSC300 ElanSC310 ElanSC400 ElanSC410 ElanSC520 Am386 DX Am386 SX Am486 DX Am 586
85. esistance C W and for BGA Package with 6 Layer Board 57 Table 14 Maximum TA for Plastic BGA Package with 6 Layer Board with Tease 85 C 57 Table 15 Multiplexed Signal Trade Offs A 2 Table 16 PlOsSoded by PIO Number A 4 Table 17 PIOs Sorted by Signal Name secre cess e oc oe estet pene EIE Pe A 5 Table 18 Pin List Summary Table Abbreviations 4044 40 A 6 Table 19 PIPE MISE SUMMARY alos cede c i npn etae gris a etes eee eco ia ela A 7 Table 20 Related AMD Products E86 Family Devices C 1 Elan SC520 Microcontroller Data Sheet ADVANCE LOGIC DIAGRAM BY INTERFACE PCI Bus SDRAM Serial Ports UART 1 UART 2 SSI Programmable Input Output Clocks and Reset Notes 1 Pins noted with asterisks are duplicated in this diagram to clarify which signals are used for each interface AD31 ADO SERR PERR FRAME TRDY TRDY STOP DEVSEL CLKPCIOUT CLKPCIIN RST INTA INTD REQ4 REQO GNT4 GNTO 12 BA1 BAO MD31 MDO 5 53 5 50 CLKMEMOUT CLKMEMIN SRASA SRASB SCASA SCASB SWEA SWEB SDQMS3 SDQMO MECC6 MECCO SOUT2 SOUT1 SIN2 SIN1 RTS2 RTS1 CTS2 CTS1 0582 0581 DTR2 DTR1 DCD2 DCD1 RIN2 RINT SSI_CLK SSI
86. essed Vcc remains High PWRGOOD reasserts with BBATSEN High so the RTC is not invalidated In this case power did not go away so the RTC con tents are still good VCC ANLG is selected as the power plane for VCC_RTC because it is a well filtered power plane that is well below the VCC_RTC maximum of 3 3 V Component values for the resistor and capacitor are shown in Table 10 46 Elan SC520 Microcontroller Data Sheet ADVANCE INFORMATION AMD D2 D1 gt LA VCC RTC I EM 100 BAIT 20 3 3 V max M VCC RTC c2 lanSC520 Microcontroller Figure 13 Circuit with Backup Battery VCC_ANLG C1 R1 VCC RTC BBATSEN 62 lanSC520 Microcontroller Figure 14 Circuit without Backup Battery Elan SC520 Microcontroller Data Sheet 47 ADVANCE INFORMATION ABSOLUTE MAXIMUM RATINGS Symbol Parameter Minimum Maximum Storage temperature VCC CORE Core voltage VCC_I O voltage 3 VCC_RTC Real time clock voltage2 VCC_ANLG Notes Analog voltage WARNING the Absolute Maximum Ratings are stress ratings only Stresses above those listed can cause permanent dam age Operation beyond the values specified in Operating Ranges at Commercial Temperatures is not recommended and ex tended exposure beyond these operating range values can affect device reliability 2 Referenced from GND 3 All
87. ests entry to AMDebug technology mode The AMDebug technology serial parallel interface can reconfigure this pin to turn instruction trace capture on or off CMDACK Command Acknowledge indicates command completion status It is asserted High when the in circuit emulator logic is ready to receive new commands from the host It is driven Low when the in circuit emulator core is executing a command from the host and remains Low until the command is completed STOP TX Stop Transmit is asserted High on entry to AMDebug mode During normal mode this is set High when there is data to be transmitted to the host during operating system application communication TRIG TRACE System Test Trigger Trace triggers events to a logic analyzer optional from Am5 86 CPU debug registers or indicates trace on or off status The AMDebug technology is used to enable and configure this pin CF_DRAM WBMSTR2 CFG2 Code Fetch SDRAM during SDRAM reads provides code fetch status When Low this indicates that the current SDRAM read is a CPU code fetch demanded by the CPU or a read prefetch initiated due to a demand code fetch by the CPU When High during reads this indicates that the SDRAM read is not a code fetch and it could have been initiated by the CPU PCI master or the GP bus GP DMA controller either demand or prefetch During SDRAM write cycles this pin provides an indication of the source of the data either GP DMA c
88. evices a simple interface via the GP bus see Easy to Use GP Bus In terface on page 31 for 8 and 16 bit devices and an interface to the SDRAM memory data bus for higher performance 8 16 and 32 bit devices 30 Elan SC520 Microcontroller Data Sheet ADVANCE The ROM Flash controller m Reduces system cost by gluelessly interfacing static memory with up to three ROM Flash chip selects Supports execute in place XIP operating systems for applications that require executing out of ROM or Flash memory instead of DRAM Supports high performance page mode devices Flexible Address Mapping Hardware In addition to the memory management unit MMU within the Am5 86 CPU core the ElanSC520 micro controller provides 16 Programmable Address Region PAR registers that enable flexible placement of mem ory SDRAM ROM Flash SRAM etc and peripher als into the two address spaces of the Am5 86 CPU memory address space and I O address space The PAR hardware allows designers to flexibly configure both address spaces and place memory and or exter nal peripherals as required by the application The in ternal memory mapped configuration registers space can also be remapped to accommodate system re quirements PAR registers also allow control of impor tant attributes such as cacheability write protection and code execution protection for memory resources Easy to Use GP Bus Interface The ElanSC520 microcontroll
89. formation Parameter Description valid hold before all other Vccs are valid PWRGOOD valid hold from all Vcc valid except RTC valid to BBATSEN active CFGx RSTLDx DEBUG ENTER INST TRCE AMDEBUG DIS setup to PWRGOOD active CFGx RSTLDx DEBUG ENTER INST TRCE AMDEBUG DIS hold from PWRGOOD active GPRESET active from PWRGOOD inactive RST active from PWRGOOD inactive PWRGOOD inactive to all Vccs invalid except RTC Notes 1 This parameter is dependent on the 32 kHz oscillator startup time which is dependent on the characteristics of the crystal leakage and capacitive coupling on the board and ambient temperature 2 This parameter ensures that the internal RTC valid status bit is cleared to indicate that the RTC time and CMOS contents are invalid 3 This parameter must be met to ensure that the RTC date and time are not invalidated Elan SC520 Microcontroller Data Sheet 59 ADVANCE INFORMATION VCC_RTC u All other Vccs t4 gt i5 lt PWRGOOD J CFGx RSTLDx DEBUG_ENTER CTT INST_TRCE AMDEBUG_DIS F 13 gt BBATSEN t6 gt GPRESET 7 RST Figure 26 Power Up Timing Sequence PWRGOOD 2 5V 2 0 V VGC Notes 2 Applies to all except for which is left on for this mo
90. igure 7 Clock Source Block Diagram Elan SC520 Microcontroller Data Sheet 39 ADVANCE INFORMATION Clock Specifications PLL period jitter specifications are summarized in Table 3 Jitter specifications are only guaranteed when analog supply noise restrictions are met Table 4 shows PLL lock times and oscillator start up times Loop filter components for the 1 47456 MHz PLL PLL1 must be supplied externally They are con nected between the analog Vcc the lanSC520 microcontroller pin LF_PLL1 Specifica tions for VCC_ANLG are shown in Table 5 Figure 6 on page 38 shows the loop filter circuit composed of C1 C2 and R1 Component values are given in Table 6 Clock Pin Loading The lanSC520 microcontroller s clock driver pins are designed to source or sink 24 mA As shown in Figure 6 on page 38 an external clock driver may be necessary when the system presents a large capaci tive load Clock pads are designed to either source or sink 24 mA The maximum amount of capacitive load that can be placed on a clock pad is determined by the required rise fall times Use the following equation to determine the maximum capacitive loading C I dV dt where current dV voltage change and dt time change As an example suppose that the system requires a rise fall time of 1 ns with a voltage swing of 2 5 V Then the maximum capacitive load is 24 mA 2 5 V 1 ns 9 6 pF
91. ion refer to Figure 9 on page 43 Components C4 and L1 are selected by the user C3 is a parasitic capacitor composed of board parasitics Typical values for C3 range from 5 pF to 15 pF C4 is required for DC isolation A nominal value for C4 is 0 1 L1 in conjunction with C3 and C2 form a resonant cir cuit The value of L3 is selected so that the resonant frequency is between the fundamental frequency and the third overtone frequency For a 33 333 MHz third overtone crystal the fundamental frequency is 11 111 MHz From this a desirable resonant frequency is be tween 11 111 MHz and 33 333 MHz A good target fre quency is 22 222 MHz L1 is selected from the basic equation L1 1 2 Pi frequency C2 C3 Assuming that the board parasitics are 15 pF then L1 1 2 Pi 22 222 MHz 7 pF 15 2 3 uH 42 Elan SC520 Microcontroller Data Sheet ADVANCE INFORMATION AMP C1 7 _C2 7pF Internal External 33MXTAL1 g 33MXTAL2 C3 C4 0 1 L1 Figure 9 33 333 MHz Third Overtone Crystal Implementation Running the Elan SC520 Microcontroller at 33 333 MHz The clock that is supplied to the PCI bus CLKPCIOUT is exactly the same as the frequency of the crystal The lanSC520 microcontroller simply buffers the 33 MHz crystal input and provides it to the CLKPCIOUT pin Since crystals have inaccuracies it is possible that these inaccur
92. l data from the external serial device or DCE into the internal serial port controller SOUT2 SOUT1 Serial Data Out is used to transmit the serial data from the internal serial port controller to the external serial device or DCE Elan SC520 Microcontroller Data Sheet 21 Signal ADVANCE INFORMATION Table 2 Signal Descriptions Continued Multiplexed Signal Description SSI_CLK SSI Clock is driven by the lanSC520 microcontroller SSI port during active SSI transmit or receive transactions The idle state of the clock and the assertion sample edge are configurable SSI_DI SSI Data Input receives incoming data from a peripheral device SSI port Data is shifted the opposite SSI_CLK signal edge in which SSI DO drives data 551 DO and 551 Dl can be tied together to interface to a three pin SSI peripheral Clocks and Reset SSI Data Output drives data to a peripheral device SSI port Data is driven on the opposite SSI_CLK signal edge in which SSI DI latches data The DO signal is normally at high impedance when no transmit transaction is active on the SSI port 32KXTAL2 32KXTAL1 Osc 32 768 kHz Crystal Interface is used for connecting an external crystal or oscillator to the lanSC520 microcontroller This clock Source is used to clock the real time clock RTC In addition internal PLLs generate clocks for the timers and UARTs based on this clock Source When
93. ldown GPDRQ2 Input with pulldown GPDRQ3 Input with pulldown GPIOCS16 Input with pullup GPIRQO Input with pullup GPIRQ1 Input with pullup GPIRQ10 Input with pullup GPIRQ2 Input with pullup GPIRQ3 Input with pullup GPIRQ4 Input with pullup GPIRQ5 Input with pullup GPIRQ6 Input with pullup GPIRQ7 Input with pullup GPIRQ8 Input with pullup GPIRQ9 Input with pullup GPMEMCS16 Input with pullup GPRDY Input with pullup GPTC Input with pullup RIN2 Input with pullup lanTMSC520 Microcontroller Data Sheet A 5 AMD ADVANCE Pin List Summary Table Column Definitions The following paragraphs describe the individual columns of information in Table 19 Pin List Summary on page A 7 The pins are grouped alphabetically by function Column 1 Signal Name Alternate Function Pinstrap This column denotes the primary and alternate func tions of the pins Brackets are used to indicate the alternate multi plexed function of a pin Braces are used to indicate the functionality of a pin only during a processor reset These signals are called pinstraps For pinstraps see Configuration on page 26 Column 2 Pin The pin number column identifies the pin number of the individual I O signal on the package Column 3 Type Definitions of the abbreviations in the Type column are shown in Table 18
94. ncy and assumes 33 333 MHz 4 Psws represents the programmable subsequent wait state timing parameter in the ROM controller register for the correspond ing ROM chip select Elan SC520 Microcontroller Data Sheet 63 25 4 Chip Select ROMBUFOE ROMRD DATA In Notes ADVANCE INFORMATION 1 Chip select includes BOOTCS ROMCS1 and ROMCS2 2 Data includes GPD15 GPDO or 31 GPA25 GPAA4 Chip Select GPA3 GPAO ROMBUFOE ROMRD DATA In Notes 1 Chip select includes BOOTCS ROMCS1 and ROMCS2 lt 2 t8 4 0 lt 7 lt 7 t3 3 15 i5 5 Figure 31 Non Burst ROM Read Cycle Timing lt t2 gt te 18 gt 110 P sm lt 7 17 Ew Le 15 gt 5 t5 Em 2 Data includes GPD15 GPD0 or MD31 MDO 64 Figure 32 Page Mode ROM Read Cycle Timing Elan SC520 Microcontroller Data Sheet ADVANCE INFORMATION lt t12 d 25 Us Chip Select t11 lt t16 gt ROMBUFOE t11 ns FLASHWR DATA 15 Out Notes 1 Chip select includes BOOTCS 51 ROMCS2
95. ndard x86 Architecture 30 AMDebug Technology for Advanced Debugging 30 Industry Standard PCI Bus Interface te Peace peto er x etre bim pua 30 High Performance SDRAM Controller 30 ROM Fl sh Controller AS 30 Flexible Address Mapping Hardware 31 Easy to Use GP Bus Interface e Ye 31 eise SEI cu zu l 31 Integrated Peripherals a iot et tpe este PO D MUI 31 JTAG Boundary Scan Test Interface Eden ita cid ierat 32 System Test and Debug Features essent nnne 92 ApBIICatI nS 33 Clock Generation and Control 38 Igiene d 39 Clock Specifications 40 Clock Pin Loadihg ET t 40 Su a arde chica Ae cei Co ian dar 41 32 769 kz Crystal Selectii N assoluto D 41 33 MHz Crystal 42 Third Overtone Crystal Component 2
96. nstrap PIO7 GPDRQ1 ADVANCE INFORMATION Table 19 Pin List Summary Continued Termination Max Load pF PIO9 GPDACK3 PIO10 GPDACK2 PIO11 GPDACK1 PIO12 GPDACKO PIO13 GPIRQ10 PIO14 9 PIO15 GPIRQS PIO16 GPIRQ7 PIO17 GPIRQS PIO18 GPIRQS 019 GPIRQ4 PIO20 GPIRQ3 PIO21 GPIRQ2 PIO22 GPIRQ1 PIO23 GPIRQ0 1024 GPDBUFOE PIO25 GPIOCS16 26 GPMEMCS16 PIO27 GPCSO Serial Ports CTS1 DCD1 DSR1 DTR1 Elan SC520 Microcontroller Data Sheet ADVANCE INFORMATION AMD Table 19 Pin List Summary Continued Signal Name Max Load pF PU 6mA 30 pF Alternate Function Termination Pinstrap P1028 AF4 B 52 029 B DSR2 B DCD2 1 AD3 B PU 6 mA 30 pF RIN2 RINT AA3 RTS1 WA RTS2 AD22 SIN1 AE2 SIN2 V24 SOUT1 AF2 SOUT2 U23 SSI_CLK AD19 SSI DI AE19 STI PU SSI DO AF19 OD Clocks and Reset 32KXTAL1 Active 32KXTAL2 Active 33MXTAL1 Active 33MXTAL2 Active CLKTIMER CLKTEST LF PLL1 PRGRESET PWRGOOD JTAG JTAG TCK JTAG TDI JTAG JTAG_TMS JTAG_TRST PU 6mA 30 pF PU 6mA 30 pF PU 6mA 30 pF 6mA 30 pF PU PU 6mA 30 pF 6mA 30 pF 6mA 30 pF
97. o 85 C for 25V 10 and VCC_I O 3 3 V 10 Case temperature is measured at the top center of the package as shown in Figure 23 The various temperatures and thermal resistances can be deter mined using the equations in Figure 24 with informa tion given in Table 14 Thermal electrical and mechanical characteristics of AMD qualified packages including the 388 PBGA can be found on AMD s website at www amd com Click on the link Products and then click on the document link Packages and Packing Methodologies JA Tc 20212712 Figure 23 Thermal Resistance C Watt 56 Elan SC520 Microcontroller Data Sheet ADVANCE INFORMATION Table 13 Thermal Resistance C W and for BGA Package with 6 Layer Board 1 Oja VS Airflow Board Type 0 200 400 600 800 Notes 1 The board type is described in the JEDEC standards document entitled Thermal Test Chip Guideline Wire Bond Type Chip at www jedec org On the home page click on the link Free Standards and Docs and then click on the document link JESD51 4 under JEDEC PUBLICATIONS Table 14 Maximum for Plastic BGA Package with 6 Layer Board with Tease 85 C Airflow Linear Feet Per Minute 200 400 600 CPU Clock Rate 133 MHz 70 C 71 C 72 C 100 MHz 72 C 74 C 74 C Notes
98. of computers and information appliances in the home The SRG pro vides firewall protection of the LAN from unautho rized access through the internet A common internet access medium is shared by all users on the LAN A variety of connections are possible for both the WAN and the LAN For example the WAN connec tion can be a V 90 modem cable modem ISDN ADSL or Ethernet The LAN connection can be HomePNA Home Phoneline Networking Alli ance an alliance with a widely endorsed home networking specification Bluetooth a computing and telecommunica tions industry specification that describes how computing devices can easily interconnect with each other and with home and business phones and computers using a short range wireless con nection Home RF a standard competing with Bluetooth for the interconnection of computing devices in a LAN using radio frequency Ethernet local area network technology power line a LAN using the AC power distribu tion network in a home or business to intercon nect devices Digital information is transmitted on a high frequency carrier signal on top of the AC power Figure 3 on page 35 shows an lanSC520 micro controller based thin client which is the modern replacement for the traditional terminal in a remote computing paradigm Application programs run re motely on a server and data is warehoused on cen trally managed disks at the server farm
99. ontroller PCI bus master or CPU When High this indicates that either a GP bus DMA initiator or an external PCI bus master contributed to the current SDRAM write cycle the CPU may also have contributed A Low indicates that the CPU is the only master that contributed to this write cycle CF_ROM_GPCS WBMSTRO Code Fetch ROM GPCS provides an indication that the CPU is performing a code fetch from ROM on either the GP bus or SDRAM data bus or from any GPCSx pin When Low during a read cycle as indicated by either GPMEMRD or ROMRD the CPU is performing a code fetch from ROM or a GP bus chip select At all other times including writes this signal is High DATASTRB WBMSTR1 CFG1 Data Strobe is a debug signal that is asserted to allow the external system to latch SDRAM data This can be used to trace data on the SDRAM interface with an in circuit emulator probe or logic analyzer Elan SC520 Microcontroller Data Sheet 23 AMD ADVANCE INFORMATION Table 2 Signal Descriptions Continued Multiplexed signal Signal Description WBMSTRO CF_ROM_GPCS Write Buffer Master indicates which block s wrote to a rank in the CFGO write buffer during SDRAM write cycles and which block is reading from SDRAM during SDRAM read cycles WBMSTRO when a logical 1 indicates that the internal GP bus DMA controller has contributed to the write buffer rank write cycles or is reading from SDRAM r
100. or 32 bit ROM Flash interface for BOOTCS CFG1 DATASTRB CFG1 Choose 8 16 or 32 bit ROM Flash interface for BOOTCS WBMSTR1 BOOTCS Data Width 8 bit 16 bit x don t care 32 bit CFG2 CF_DRAM CFG2 When Low when PWRGOOD is asserted the ElanSC520 WBMSTR2 microcontroller uses the GP data bus for BOOTCS When seen as High during PWRGOOD assertion the BOOTCS access is across the SDRAM data bus Default is Low by a built in pulldown resistor CFG3 PITOUT2 Internal AMD test mode enable For normal ElanSC520 microcontroller operation do not pull High during reset DEBUG_ENTER GPA25 Enter AMDebug Mode is an active High configuration signal latched at the assertion of Power Good PWRGOOD This pin enables the AMDebug mode which causes the processor to fetch and execute one instruction from the BOOTCS device and then enter AMDebug mode where the CPU waits for debug commands to be delivered by the JTAG port This pin has a built in pulldown resistor At PWRGOOD assertion High AMDebug mode enabled Low Normal operation INST GPA24 Instruction Trace is an active High configuration signal latched at the assertion of Power Good PWRGOOD Enables trace record generation from Power Good assertion This pin has a built in pulldown resistor At PWRGOOD assertion High Trace controller enabled to output trace records Low Normal operation 26 Elan SC5
101. or use during board testing System Test and Debug Features To facilitate debugging the lanSC520 microcontroller provides observability of many portions of its internal operation including m Athree pin interface that can be used in either sys tem test mode or write buffer test mode to aid in de termining internal bus initiators of SDRAM cycles and determining when SDRAM data is valid on the interface An additional mode provides observability of integrated peripheral accesses m nonconcurrent arbitration mode to reduce debug complexity when PCI bus masters and GP bus DMA initiators are also accessing SDRAM W CPU cache control and dynamic core clock speed control under program control W Ability to disable write posting and read prefetching in the SDRAM controller to simplify tracing of SDRAM cycles m Notification of memory write protection and non ex ecutable memory region violations Elan SC520 Microcontroller Data Sheet ADVANCE INFORMATION APPLICATIONS The figures on the following pages show the lanSC520 microcontroller as it might be used in sev eral reference design applications in the data commu nications information appliances and telecommunication markets Figure 2 on page 34 shows an ElanSC520 micro controller based Smart Resident Gateway SRG which is a router for a home network between the wide area network WAN the internet and a local area network LAN an intranet
102. peak transfer rate W Deep buffering and support for burst transactions from PCI bus masters to SDRAM W Flexible arbitration mechanism W Support for up to five external PCI masters High Performance SDRAM Controller The lanSC520 microcontroller provides an integrated SDRAM controller that supports popular industry stan dard synchronous DRAMs SDRAM m The SDRAM controller interfaces with SDRAM chips as well as with most standard DIMMs to en able use of standard off the shelf memory compo nents m The SDRAM controller supports programmable tim ing options and provides the required external clock m Up to four 32 bit banks of SDRAM are supported with a maximum capacity of 256 Mbytes m An important reliability enhancing Error Correction Code ECC feature is built into the SDRAM control ler The resultant increase in the memory content reliability enables the ElanSC520 microcontroller to be effectively utilized in applications that require more reliable operation such as communications environments m The SDRAM controller contains a write buffer and read ahead buffer subsystem that improves both write and read performance SDRAM refresh options allow the SDRAM contents to be maintained during reset ROM Flash Controller The ElanSC520 microcontroller provides an integrated ROM controller for glueless interfacing to ROM and Flash devices The ElanSC520 microcontroller sup ports two types of interfaces to such d
103. proper 32 768 kHz crystal The ECPSM29T is recommended 10 pF Internal External 32KXTAL2 32KXTAL1 rr E 32 768 kHz Crystal Figure8 32 768 kHz Crystal Circuit lanTMSC520 Microcontroller Data Sheet 41 ADVANCE INFORMATION Table 8 32 768 kHz Crystal Specifications Parameter Nominal Frequency Comment Effective Series Resistance ESR 60000 0 Drive Level Load Capacitance ElanSC520 microcontroller 5 5 pF Resonant Mode Parallel Crystal Cut BT Operating Mode Parameter or Characteristic Nominal Frequency 33 000 MHz Fundamental Comment 33 333 MHz ESR 40 Q Drive Level mW Load Capacitance ElanSC520 microcontroller Resonant Mode Parallel Crystal Cut AT or BT Operating Mode 33 MHz Crystal Selection The same information related to the 32 768 kHz crystal selection applies to the 33 MHz crystal selection The lanSC520 microcontroller supports either a 33 000 MHz or 33 333 MHz crystal Specifications for the 33 MHz crystal are shown in Table 9 AMD recommends using a fundamental mode 33 333 MHz crystal If a third overtone crystal is used the os cillator gain may not be large enough to produce a reli able clock Fundamental Third Overtone Crystal Component Selection For the third overtone crystal circuit implementat
104. r an RTC invalida tion They are the following m BBATSEN drops below 2 V sampled when PWR GOOD asserts During operation from the main power supply the backup battery voltage might drop below the trip voltage 2 V The RTC is not invali dated until a PWRGOOD assertion occurs m Power is applied to VCC_RTC the backup battery is plugged in When the backup battery is plugged in the RTC is immediately invalidated No battery during power up sampled after PWR GOOD asserts If the system does not contain a backup battery and the BBATSEN line potential is below 2 V the RTC is invalidated when PWRGOOD asserts In addition to the backup battery monitor function the voltage monitor also provides a power down signal to the RTC This signal is used to isolate the RTC core from the rest of the integrated peripherals A timing diagram for this sequence is shown in Figure 27 on page 60 Elan SC520 Microcontroller Data Sheet 45 ADVANCE INFORMATION Table 10 RTC Voltage Monitor Component Specifications Component Parameter Nominal D1 Forward Voltage Drop 0 25 V D2 Forward Voltage Drop Note D1 D2 Forward Current 100 C1 Capacitance 5pF 10 pF 20 pF C2 Capacitance 180 pF 200 pF 400 pF R1 Resistance 900 1 1 1 Notes 1 Diode should be selected so that the voltage into the RTC power pin does not exceed 3 3 V Backup Battery Consi
105. ring in circuit emulation W General Purpose GP bus with programmable timing for 8 and 16 bit devices provides good performance at low cost GENERAL DESCRIPTION The Elan SC520 microcontroller is a full featured mi crocontroller developed for the general embedded mar ket The ElanSC520 microcontroller combines a 32 bit low voltage Am5 86 CPU with a set of integrated pe ripherals suitable for both real time and PC AT compat ible embedded applications An integrated PCI host bridge SDRAM controller enhanced PC AT compatible peripherals and advanced debugging features provide the system designer with a wide range of on chip resources allowing support for legacy devices as well as new devices available in the current PC marketplace Copyright 1999 Advanced Micro Devices Inc All rights reserved ROM Flash controller for 8 16 and 32 bit devices Enhanced PC AT compatible peripherals provide improved performance Enhanced programmable interrupt controller PIC prioritizes 22 interrupt levels up to 15 external sources with flexible routing Enhanced DMA controller includes double buffer chaining extended address and transfer counts and flexible channel routing Two 16550 compatible UARTs operate at baud rates up to 1 15 Mbit s with optional DMA interface Standard PC AT compatible peripherals Programmable interval timer PIT Real time clock RTC with battery backup capability and 114 byte
106. ry Continued Signal Name Alternate Function Termination Pinstrap Max Load pF 12 18 24 mA 12 18 24 mA 12 18 24 mA 12 18 24 mA 12 18 24 mA 12 18 24 mA 12 18 24 mA 12 18 24 mA 12 18 24 mA 12 18 24 mA 12 18 24 mA 12 18 24 mA 12 18 24 mA 12 18 24 mA 12 18 24 mA 12 18 24 mA 12 18 24 mA 12 18 mA 12 18 mA 12 18 mA 12 18 mA 12 18 24 mA 12 18 24 mA 12 18 24 mA 12 18 24 mA 12 18 24 mA 12 18 24 mA 12 18 24 mA 12 18 24 mA B B B B B B B B B B B B B B B SE Se ESE Se T TL E E ROM Flash Control BOOTCS FLASHWR ROMBUFOE 51 GPCS1 ROMCS2 GPCS2 ROMRD PCI Bus ADO AD1 AD2 ADS A 8 Elan SC520 Microcontroller Data Sheet ADVANCE INFORMATION Table 19 Pin List Summary Continued Signal Name Alternate Function Termination Pinstrap Max Load pF L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L CLKPCIIN CLKPCIOUT Active DEVSEL TS FRAME TS GNTO TS GNT1 TS GNT2 TS GNT3 TS GNT4 TS INTA Elan SC520 Microcontroller Data Sheet A 9 ADVANCE INFORM
107. s designed to provide ADVANCE m A balanced mix of high performance and low cost interface mechanisms m A high performance industry standard 32 bit PCI bus Glueless interfacing to many 8 and 16 bit I O pe ripherals and an 8 and 16 bit bus with programma ble timing A cost effective system architecture that meets wide range of performance criteria while retaining the lower cost of a 32 bit system m A high degree of leverage from present day hard ware and software technologies Figure 1 on page 29 illustrates the integrated Am5 86 CPU bus structure and on chip peripherals of the ElanSC520 microcontroller Three primary interfaces are provided A high performance 66 MHz 32 bit synchronous DRAM SDRAM interface of up to 256 Mbytes is used for Am5 86 CPU code execution as well as buffer storage of external PCI bus masters and GP bus DMA initiators A high performance ROM Flash interface can also be connected to the SDRAM in terface INFORMATION W An industry standard 32 bit PCI bus is provided for high bandwidth I O peripherals such as local area network controllers synchronous communications controllers and disk storage controllers A simple 8 16 bit 33 MHz general purpose bus GP bus provides a glueless connection to lower bandwidth peripherals and NVRAM SRAM ROM or custom ASICs supports dynamic bus sizing and compatibility with many common ISA devices These three buses listed above are
108. s of RAM Additional integrated peripherals Three general purpose 16 bit timers provide flexible cascading for 32 bit operation Watchdog timer guards against runaway software Software timer Synchronous serial interface SSI offers full duplex or half duplex operation Flexible address decoding for programmable memory and I O mapping and system addressing configuration W 32 programmable input output PIO pins W Native support for pSOS QNX RTXC VxWorks and Windows CE operating systems Indusiry standard BIOS support W Plastic Ball Grid Array PBGA388 package Designed for medium to high performance applications in the telecommunications data communications and information appliance markets the lanSC520 micro controller is particularly well suited for applications re quiring high throughput combined with low latency The compact Plastic Ball Grid Array PBGA package pro vides a high degree of functionality in a very small form factor making it cost effective for many applications A 0 25 micron CMOS manufacturing process allows for low power consumption along with high performance Final Draft 22003 Rev A Amendment 0 Issue Date July 1999 AMD ADVANCE INFORMATION ORDERING INFORMATION lanSC520 133 TEMPERATURE RANGE C Commercial 0 to 85 C where case temperature PACKAGE TYPE A 388 Pin Plastic Ball Grid Array PBGA SPEED OPTION 100 100 MHz
109. ssertion GPTC pulse width GPAEN and GPDBUFOE deasserted from command deasserted GPDRQ deasserted from GPDACK assertion GPDACK deasserted from command deasserted GPIORD GPMEMRD deasserted to GPD invalid 9 GPDRQ t gt 2 18 0 GPAEN J GPDBUFOE E Vn 13 t11 GPD15 GPD0 4 5 gt GPIORD GPMEMRD 16 7 gt GPTC Figure 37 GP DMA Write Cycle Timing Elan SC520 Microcontroller Data Sheet 71 AMD ADVANCE INFORMATION SSI Timing Advance Information Parameter Description SSI CLK period SSI CLK High time SSI CLK Low time SSI DI setup time to sample edge SSI DI hold time from sample edge SSI DO hold time from assert edge SSI DO setup to sample edge SSI_DO high impedance from sample edge of last bit 05 5 Notes 1 The clock period for the 551 interface is programmable a divisor of 33 MHz crystal input Rates provided are binary multiples from divide by 4 110 ns to divide by 512 15526 ns The actual period is affected by the frequency of the crystal 33 000 MHz or 33 333 MHz 2 The sample assert clock edge for the SSI interface is programmable 3 refers to the programmed period for 551 pin
110. stem Reset GPALE Input with pullup GPBHE Input with pullup GPRDY Input with pullup GPAEN Input with pullup GPTC Input with pullup GPDRQ3 Input with pulldown GPDRQ2 Input with pulldown GPDRQ1 Input with pulldown GPDRQO Input with pulldown GPDACK3 Input with pullup GPDACK2 Input with pullup GPDACK1 Input with pullup GPDACKO Input with pullup GPIRQ10 Input with pullup GPIRQ9 Input with pullup GPIRQ8 Input with pullup GPIRQ7 Input with pullup GPIRQ6 Input with pullup GPIRQ5 Input with pullup GPIRQ4 Input with pullup GPIRQ3 Input with pullup GPIRQ2 Input with pullup GPIRQ1 Input with pullup GPIRQO Input with pullup GPDBUFOE Input with pullup GPIOCS16 Input with pullup GPMEMCS16 Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup A 4 Elan SC520 Microcontroller Data Sheet ADVANCE INFORMATION Table 17 PlOs Sorted by Signal Name Multiplexed PIO Default Pin Configuration Signal Function Following System Reset 52 Input with pullup DCD2 Input with pullup DSR2 Input with pullup GPAEN Input with pullup GPALE Input with pullup GPBHE Input with pullup GPCSO Input with pullup GPDACKO Input with pullup GPDACK1 Input with pullup GPDACK2 Input with pullup GPDACK3 Input with pullup GPDBUFOE Input with pullup GPDRQO Input with pulldown GPDRQ1 Input with pul
111. t of integrated peripherals that are a superset of common PC AT peripherals plus a set of memory mapped peripherals that enhance its usability in various applications W A programmable interrupt controller PIC that pro vides the capability to prioritize 22 interrupt levels up to 15 of these being external sources The PIC can be programmed to operate in PC AT compatible mode but also contains extended features includ ing support for more sources and flexible routing that allows any interrupt request to be steered to any PIC input Interrupt requests can be pro grammed to generate either non maskable interrupt NMI or maskable interrupt requests m Anintegrated DMA controller is included for trans ferring data between SDRAM and GP bus peripher als The GP DMA controller operates in single cycle fly by mode for more efficient transfers The GP DMA controller can be programmed for PC AT com patibility but also contains enhanced features Elan SC520 Microcontroller Data Sheet 31 32 ADVANCE A double buffer chaining mode provides a more efficient software interface Extended address and transfer counts Flexible routing of DMA channels Three general purpose 16 bit timers that provide flexible cascading for extension to 32 bit operation These timers provide the ability to configure down to the resolution of four clock periods where the clock period is the 33 MHz clock Timer input and output pins
112. tage monitor 45 voltage monitor block diagram 45 voltage monitor specifications 46 reset pin summary A 13 power on reset timing 59 signal descriptions 22 soft CPU reset 32 timing with power applied 61 ROM address mapping 31 controller description 30 multiplexed signal trade offs A 2 pin summary A 8 signal descriptions 18 timing 63 RTC See real time clock RTC 5 SDRAM address mapping 31 clock timing 67 controller description 30 error correction code ECC 30 pin summary A 7 signal descriptions 17 timing 66 serial ports multiplexed signal trade offs A 2 pin summary A 12 signal descriptions 21 signals See also pins multiplexed signal trade offs table A 2 signal description table 17 signal descriptions 16 software timer 32 551 See synchronous serial interface 551 Elan SC520 Microcontroller Data Sheet Index 3 AMD ADVANCE INFORMATION switching characteristics and waveforms GP bus 68 JTAG 73 watchdog timer 32 bus interface pins 58 WWW over commercial industrial operating ranges 59 home page C 3 PCI bus 65 support C 3 PCI bus interface pins 58 power on reset 59 reset with power applied 61 ROM 63 SDRAM 66 SSI 72 synchronous serial interface SSI description 32 timing 72 system test multiplexed signal trade offs A 3 pin summary A 13 signal descriptions 23 T technical support See customer support testing JTAG boundary scan test interf
113. ternal data bus High performance 32 bit embedded microprocessor with 32 bit external data bus High performance 32 bit embedded microprocessor with 64 bit external data bus High performance 32 bit embedded microprocessor with 64 bit external data bus and 3DNow technology 1 186 16 bit microcontroller and 80C186 compatible except where noted otherwise 188 16 bit microcontroller with 8 bit external data bus and 80C188 compatible except where noted otherwise LV low voltage Elan SC520 Microcontroller Data Sheet ADVANCE Related Documents The following documents contain additional information that will be useful in designing an embedded applica tion based on the ElanSC520 microcontroller Elan SC520 Microcontroller Register Set Manual order 22005 fully describes all the registers re quired to program the microcontroller Elan SC520 Microcontroller User s Manual order 22004 provides a functional description of the mi crocontroller for both hardware and software de signers m The Am486 Microprocessor Software Users Man ual order 18497 includes the complete instruction set for the integrated Am5 86 CPU Other information of interest Am5 86 Microprocessor Family Data Sheet order 19751 m Am486 DX DX2 Microprocessor Hardware Refer ence Manual order 17965 86 Family Products and Development Tools CD order 21058 provides a single source multimedia tool for custom
114. twork Elan SC520 Microcontroller Data Sheet 33 AMDA ADVANCE INFORMATION LAN Interface Am79C978 PCnet Home RJ 45 or RJ 45 or WAN Interface ADSL Cable Modem or V 90 AD31 ADO Control PCI Bus MA12 MAO GPA25 GPAO gt gt a 5 MD31 MDO z Elan SC520 Microcontroller 2 15 oc lt Control m 33 MHz Crystal 32 kHz Crystal Figure 2 Elan SC520 Microcontroller Based Smart Residential Gateway Reference Design 34 Elan SC520 Microcontroller Data Sheet ADVANCE INFORMATION AMD a 5 lt E 6 8 9 gt O gt _ ua g 0 o LO N Get 5 ABE S E x 42 lt 8 8 Control PCI Bus MA12 MAO GPD15 GPDO o a gt pa 031 00 lan SC520 Microcontroller 2 9 cc E ur 2 Control Control 9 D D D N N ak 9 9 Figure 3 Elan SC520 Microcontroller Based Thin Client Reference Design Elan SC520 Microcontroller Data Sheet 35 ADVANCE INFORMATION VGA NTSC PAL BIR O PS 2 Keyboard QO PS 2 Mouse Parallel RJ 11 WAN Interface ADSL Cable Modem or V 90 AD31 ADO Control Super I
115. ve strengths can take on the characteristics of 12 18 or 24 mA signals VOLTAGE LEVELS FOR PCI INTERFACE PINS The voltage characteristics of the PCI interface input pins are specified in the PCI Local Bus Specification Revision 2 2 section 4 2 1 5V Signaling Environment and section 4 2 2 3 3V Signaling Environment The voltage characteristics of the PCI interface output pins are specified in the PCI Local Bus Specification Revision 2 2 4 2 2 3 3V Signaling Environment Elan SC520 Microcontroller Data Sheet 49 ADVANCE INFORMATION DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES Advance Information Parameter Description Min Typ Max Unit CORE Current for supply 133 MHz 465 660 mA Icc CORE Current for supply 100 MHz 380 540 mA Current for I O supply 33 MHz 100 120 mA Current for RTC only mode i 5 uA Current for ANLG only mode 1 4 1 9 2 1 mA Input leakage current 0 1 20 uA All pins except those with internal pullup or pulldown resistors liio Input leakage current Vin VCC_I O 0 1 V i 60 uA All pins with internal pulldown resistors Input leakage current 0 1 V 60 uA All pins with internal pullup resistors lio Output leakage current t15 uA Notes 1
116. y and I O read cycles and outputs data during memory and I O write cycles A reset configuration pin CFG2 allows the GP bus to be used for the boot chip select ROM interface Configuration registers are used to select whether ROMCS2 and ROMCS 1 use the GP bus data bus or the MD data bus The GP data bus supports 16 bit or 8 bit ROM interfaces Two data buses are selectable to facilitate the use of ROM in a mixed voltage system MD31 MDO Memory Data Bus inputs data during SDRAM read cycles and outputs data during SDRAM write cycles Configuration registers are used to select whether ROMCS2 and ROMCS1 use the GP bus data bus or the MD data bus A reset configuration pin CFG2 allows the GP data bus to be used for BOOTCS The memory data bus supports an 8 16 or 32 bit ROM interface ROMBUFOE ROM Buffer Output Enable is an optional signal used to enable a buffer to the ROM Flash devices if they need to be isolated from the lanSC520 microcontroller other GP bus devices or SDRAM system for voltage or loading considerations This signal asserts for all accesses through the ROM controller The buffer direction is controlled by the ROMRD or FLASHWR signal ROMCS2 GPCS2 ROM Flash Chip Selects are signals that can be programmed to be 51 GPCS1 asserted for accesses to user programmable address regions ROMRD ROM Flash Read indicates that the current cycle is a read of the selected ROM Flash device When
117. ystem s ROM Flash devices 17 RSTLD2 18 RSTLD3 19 RSTLD4 20 RSTLD5 GPA21 RSTLD6 22 RSTLD7 GPA23 AMDEBUG_DIS 24 INST_TRCE 25 DEBUG_ENTER Elan SC520 Microcontroller Data Sheet 19 Signal Multiplexed Signal ADVANCE INFORMATION Table 2 Signal Descriptions Continued Type Description GPAEN O GP Bus Address Enable indicates that the current address on the GPA25 GPAO address bus is a memory address and that the current cycle is a DMA cycle All I O devices should use this signal in decoding their I O addresses and should not respond when this signal is asserted When GPAEN is asserted the GPDACKx signals are used to select the appropriate I O device for the DMA transfer GPAEN also asserts when a DMA cycle is occurring internally GPALE GP Bus Address Latch Enable is driven the beginning of a GP bus cycle with valid address This signal can be used by external devices to latch the GP address for the current cycle GPBHE PIO1 GP Bus Byte High Enable is driven active when data is to be transferred on the upper 8 bits of the GP data bus GPD15 GPDO General Purpose Data Bus inputs data during memory and I O read cycles and outputs data during memory and write cycles GPDACKO GPDACK1 GPDACK2 GPDACK3 PIO12 PIO11 PIO10 9

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