TLE9879 EvalKit User Manual
Contents
1. 1 ONIONO ONO ANS ceux la 9 19 19 5 a fa fn LE 3 001 A a 2 Sgen t a LP e va d 85 85 oon 464 83 13914 85 700 001 9 8 9 uld 49345 1849790 13534 ONS 6 ON ON OMS ONO 8 60 0005 AG Mn 001 ao 5 oD JT T al en o9euoju 65600360 CAE SEGGER 214 2 D Jai ZA yy gg gy 5 AA gaz 22 00000000 AAA DOA E A 6900000000 o Beso gt Zg p pe 000006000000 14 SIS KJK Te COGOR 7 3 0 6 GQ o gt 6 1 TS Ts 7 3 SSI 2 YG gan 152. gt a a L19 dl 0 6719 dl 5115 i Pom es DS 7 CHD dl DE A 2 0 LHD di 1 i cues lt 9 l 6 u 5 EE x 1 8 gl E eI 7 ES 2 gt d ene dQQA 72 5 8 NM Y D fo qj a 1 e SA D OSA Sie Qe LL d2 o Soo 3 5 ONO 2 N 7 _ _ ao 2 TE 5 y D an sed aT 5 es 5 5 Fd o gt CI E 6d db 2 nies oy 104 dur Ls es 2 ds 1 3 5 e m Pp E bd ar tz y A 0 Utd EE C 1 a E Dd C Z Dd e 0 d P E 0 02 2 13833 NOW o ONO mm 11 GPIO LED Jumper Power Supply EvalBoardTLES87x 2 02 2015 10 54 24 ND Motor Connector 12 sf 3L R 6 50 OSPONDGOdI prore sed 1 1G INF R2 54 CN e C mO Ld Ls ed 1 GO r St NO 6COdIl a 31 400 0 R26 E TOR 3
3. communication via UART The UART2 module of TLE9879 uses the pins P1 1 transmit and P1 2 receive Those are connected to the XMC4200 which emulates Rx and Tx on PC side with Segger firmware Though they cannot be disconnected physically bidirectional level shifters ensure that the XMC pins are hi Z in case the virtual COM port is not used By connecting the evaluation board to the PC a virtual COM port gets emulated by the Segger driver automatically The port used will show up in the Microsoft Windows device manager E e SCLK RESET Figure 5 UART and Debugging Note Only one of the interfaces USB or SWD can be used at one time While using the SWD interface the XMC is hold in reset As long as a debugger is connected with the SWD interface it eliminates therefore debugging or UART via USB 5 3 Debugging via USB or SWD Interface For serial wire debug the TLE9879 uses the pins TMS data and 20 0 clock Level shifters between XMC4200 and TLE9879 allow using 20 0 while it is not used for debugging The Segger J Link module on board allows serial wire debugging via USB Alternative debugging via SWD interface is possible to debug with another ISP than the onboard Segger e g U Link2 Therefore the signals are routed through the 10 pin header SWD interface between the XMC4200 and the TLE9879 The pin configuration makes sure that the XMC is hold in reset while another debugger is physically connected as DBPRE will be im
4. Capacity Snubber High side MOSFET Phase 3 C41 Gate Drain Capacity High side MOSFET Phase 3 R36 Resistance Snubber Low side MOSFET Phase 3 C46 Capacity Snubber Low side MOSFET Phase 3 C43 Gate Drain Capacity Low side MOSFET Phase 3 Table 8 Additional Placements 10 9 re E 0 6 0 8 631023 9l X S64 1L 003001 Goze i 00 93 ES 135340 48 ONO NITE c 1X3004 QNS 6 92 nt 1001 3 H E RI 3 A QNO 000 ONS 9 GND 10 T 7 Y 2 21 G10 d E a QNO 00 15 xe QNO 438 ONS 3 9 ONO 13 LHO L HS EHS B OZ TE TvwIX LHS 77 5 TLX zHS o B 8 GdO 0 dO HOA HOA 9 8847 NOW FC x Ez atte NIT QNO 1 59277 El 5527 QNO LINE Cl QE m 94 1 ld 954 1 O Hld3 1122 t DK 0 LO udi SNL 1350 ics and Layout 8 Schemat 8 CO X LED1 rang EvalBoardTLES987x 20 02 2015 10 54 24 dl ONS Bm ONS dl ONS use o dL g 00 cdO dl i 19 LAO dl ONS 0 dL 13 5 L19 52 3 L 619 dl
5. ab 5 Zz 9 R DO G 1 3 1 Y 1 J EPS G0 FOSFOND6 di S ai R2 Ld 10R rik XD e cr TT C 1 SL G0 FOS di ns 0 seb sed l YDH Phase 3 FW iDUF C4 S0 POSPONOGOdI ais dris 098 400 1 VDHA y LO TNF 1 IDK i 4 GH2 G G0 FOSFOND6 di dis 08 SA 4 EL 14 Phase 1 13 OND QNS l bd SAIL ONS QNO QNO 4 01 051 3 1 5 BIJ 1 uid QNO 2 9 8 E YODA O m 21 x 5 EAE JE 6 QNO ONS CAE CAE 1009501 55 0 QNO 1 3 ey 58 77 Iv La YODA 4994 QNO QNO 5 5 ZE la 55 3 0050817 10 5 5 QNO 56 7 E YOJA 6250A VO i EAE 6 it 1 1oqsb1ZOATzNS 59 0 QNO Zy 28 LA v VIDA CAE 57 57 PZ EZ 59 A 1 AS BrNJO 0070 Qqvd3 SSA 49 SWL AOL 1540d 2 V WIX OLY WIX 914 v nasus 00 22 29 FTOC OTV TE 4399354 peseme Myr 0 55 ONO ONO QNS O IO JO O S A SIE 31218
6. TLE9879 EvalKit V1 0 User s Manual 4 USD G Infineon y x 0 1 5 EEN gt 4 amp T n ticis 76 gt Infineon 3 TLE9879 3 gt 5 3 n VNLT cee d 55 1 8 we E G Infineon a XMC4200 um c54 5 T 828 bel imma 28 1 2360 bent term 080 24 Cie mei 7 7758 Etre gt 5 om ve 55 E 1 Infineon www segger com aunt M 4 Infineon EvalKit U1 0 TLESS87S Contents Abbreviations pp 8 os 2 111616015158665 aida 3 Test Points and LEDs 4 Jumper Settings pp 5 Communication Interfaces 5 1 LIN via Banana jack and ulO BSL 5 2 UART via USB 5 3 Debugging via USB or SWD Interface 5 Technical Data zu 7 Optional Additional Placements 8 Schematics and Layout Abbreviations Brushless Direct Current Bootstrap Loader Gate High side MOSFET for Phases 1 2 3 Gate Low side MOSFET for Phase 1 2 3 General Port Input Output In system Programmer Local Interconnect Network Monitor not connected not used Negative operational Amplifier Input Positive operational Amplifier Input Reset Source Low side MOSFET ARM Serial Wire Debug Te
7. ch gate has an intended test point to measure the respective signals at high side gates and low side gates GL1 GL2 GL3 GH1 GH2 GH3 Test points OP1 and OP2 are provided at both sides of the shunt which is 5mR Additionally there is an intended test point for VDDC and various ground points All test points marked in the following figure are not populated In order to use these pins they have to be soldered in the designated solder holes There are eleven LEDs for visual validations on the board LED 1 8 can be connected to GPIOs see Chapter 4 Jumper Settings LED 9 indicates VDDEXT activation LED 10 indicates power supply LED11 indicates debug activity 4 Jumper Settings and Potentiometer The following table summarizes the jumpers options More detailed information can be found in the text below JP1 Enable or disable MON button JP2 Enable or disable RESET button JP3 Select TLE9879 as LIN Master or LIN Slave JP4 Connect or disconnect VAREF with VDDEXT JP5 Replace by an ampere meter to measure input current JP6 Enable or disable POTI JP7 Enable or disable LED for respective GPIO Table 6 Jumpers functionalities 42 23 l 3 A El Figure 4 Jumpers JP1 Close this jumper to connect MON button to MON input Open it to disconnect MON button from MON input JP2 Close this jumper to connect RESET button to RESET input Open it to disconnect RESET button from RESET input JP3 Clos
8. e this jumper to connect an additional 1k pull up resistor This is intended for LIN master communication Open the jumper to use the TLE9879 as slave in a LIN network Software for LIN low level driver can be found at the homepage of IHR www ihr de JP4 Close this jumper in order to supply VAREF by VDDEXT In case VAREF is supplied externally the user has to take care by software that the internal VAREF is disabled Open the jumper to use the internal VAREF which has to be enabled by software JP5 This jumper is closed by default If this jumper is left open the device is not supplied It is intended to open the VS line in order to measure the current flowing into the TLE9879 JP6 Close this jumper to connect the potentiometer to P2 4 Open this jumper to disconnect the potentiometer JP7 Jumper 7 provides one individual jumper per LED in order to connect or disconnect the respective LED to the pin port Table 7 Combinations of GPIOs and LEDs 5 Communication Interfaces 5 1 LIN via Banana jack and 1110 BSL The device integrated LIN transceiver is connected to a banana jack and additionally to the ulO BSL interface To integrate the device in a LIN network it is sufficient to use the single wire banana interface The BSL interface is intended to program the device via LIN For further information about the ulO interface see www hitex com uio 5 2 UART via USB A virtual COM port provided by Segger driver enables a PC board
9. ns Following signals are connected to the pins X4 Table 2 Pin Configuration Top Line Pin Port X4 X5 eee 2 5 0 2 5 14 Table 3 Pin Configuration Bottom Line Pin Port X5 Terminal block for connecting the motor marked blue The three pins of the terminal block provide access to the three half bridges and are intended to connect a DC brushless motor USB for UART and Debugging marked green With this Micro USB PC and evaluation board can get connected ulO BSL for LIN marked orange This ulO bootstrap loader is an 8 pin header 2x4 with 2 54mm pitch It is intended to connect additional hardware for bootstrap loading For programming the TLE9879 via LIN this ulO interface can be used see www hitex com uio Table 4 Pin Configuration ulO BSL Pin Header for SWD marked purple There is a 10 pin header 2x5 with 1 27mm pitch on the evaluation board For debugging with another ISP than the onboard Segger this interface can be used DBPRE will be implicitly connected to GND by connecting the external ISP This keeps the XMC in reset state to prevent interference of the SWD communication 5 SWDIO TMS Table 5 Pin Configuration SWD Interface 3 Test Points and LEDs Figure 3 Test Points The 3 phase power half bridge is controlled by six gate driver pins driving the gates of high side MOSFET and side MOSFET for each phase Ea
10. plicitly connected to GND by connecting the external ISP see Table 5 Information regarding the software installation for editor compiler and debugger can be found in the documentation ePower Tool Chain Setup SDK on the provided USB flash drive 6 Technical Data Platine Size 110x66 mm Voltage Supply max 28V Motor Current max 20A Pin Ports 5V GPIOs of TLE9879 7 Optional Additional Placements A 389990909998 6 22 T Cal 1 f 1 1 3 5 2 t S 222 2 ico UA ee 7 ia Ger Es 5 lll 26 Figure 6 Additional Placements positions Values for these optional additional placements have to be determined depending on application Q1 External Oscillator C1 Oscillator Capacity 1 C2 Oscillator Capacity 2 R22 Resistance Snubber High side MOSFET Phase 1 C28 Capacity Snubber High side MOSFET Phase 1 C24 Gate Drain Capacity High side MOSFET Phase 1 R23 Resistance Snubber Low side MOSFET Phase 1 C29 Capacity Snubber Low side MOSFET Phase 1 C26 Gate Drain Capacity Low side MOSFET Phase 1 R28 Resistance Snubber High side MOSFET Phase 2 C36 Capacity Snubber High side MOSFET Phase 2 C32 Gate Drain Capacity High side MOSFET Phase 2 R29 Resistance Snubber Low side MOSFET Phase 2 C37 Capacity Snubber Low side MOSFET Phase 2 C34 Gate Drain Capacity Low side MOSFET Phase2 R35 Resistance Snubber High side MOSFET Phase 3 C45
11. several ground points on the evaluation board see Figure 3 For testing analog signals ADC inputs can be varied by the potentiometer on board Three phases of motor current can be picked off at a terminal block to connect a DC brushless motor The evaluation board can be operated by standard laboratory equipment as power supply and LIN communication are working via banana jacks Debugging and UART are provided via an USB interface combined with onboard Segger J Link XMC4200 Bidirectional level shifters ensure that the respective XMC pins are in tristate as long as UART or debugging is not used In case the user wants to use another ISP than the onboard Segger the SWD interface can be used To program the TLE9879 via LIN there is an additional ulO BSL interface see Table 4 There is a battery LED that indicates that the board is connected to supply the right way Otherwise reverse polarity protection secures the board from damage by cross connection 2 Interconnects onn CA Lt tx GO 8 2 Z 2 Y Y o zx 8 Y an pr m Pm im PA ph Figure 2 Interconnects Banana jacks marked yellow There are jacks in different colors for ground supply max 28V and LIN communication via banana jack GND black VBAT red LIN green Pin Ports X4 and X5 marked red Soldering pin headers with 2 54mm pitch for X4 1x10 and X5 1x16 yields test points for the TLE9879 pi
12. st Mode Select Universal Asynchronous Receiver Transmitter Reference Voltage Battery Voltage Supply Virtual COM Port Voltage Charge Pump Core Supply External Voltage Supply Output I O Port Supply Voltage Drain High side MOSFET Battery Supply Input Battery Supply Input for MOSFET Driver BLDC BSL GH1 2 3 GL1 2 3 GPIO ISP LIN MON n c n u 01 OP2 RST SL SWD TMS UART VAREF VBAT VCOM VCP VDDC VDDEXT VDDP VDH VS VSD Table 1 Abbreviations 1 Concept ulO BSL Interface SW Debug Interface gt Debug m m LEVEL UART LEVEL E Voltage Regulator Figure 1 Board Concept This board is intended to provide a simple easy to use tool for getting familiar with Infineon s embedded power IC TLE9879 It contains the TLE9879 and its typical application circuit including three MOSFET half bridges to instantly drive a BLDC motor The board is ready to connect with car supply or similar and has an implemented Segger for debugging on board All relevant chip pins are connected to pin headers at the edge of the board where signals can be probed or applied directly see Table 2 Table 3 By different jumper settings LEDs can be put in parallel to several ports and selected functions can be configured see Table 6 Push button switches allow easy hardware reset and triggering of the MON input There are intended test points for all six gate driver pins for measurements at the shunt VDDC and
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