Home

Variable-Length Encoding (VLE) extension

1. Table 1 Terminology conventions Architecture specification This manual Change bit Changed bit Extended mnemonics Simplified mnemonics Out of order memory accesses Speculative memory accesses Privileged mode or privileged state Supervisor level Problem mode or problem state User level Reference bit Referenced bit Relocation Translation Storage locations Memory Storage the act of Access Acronyms and abbreviations Table 2 contains acronyms and abbreviations that are used in this document Table 2 Acronyms and abbreviated terms Term Meaning CTR Count register DCR Data control register DTLB Data translation lookaside buffer EA Effective address ECC Error checking and correction FPR Floating point register GPR General purpose register IEEE Institute of Electrical and Electronics Engineers STA 9 50 Preface UM0438 Table 2 Acronyms and abbreviated terms continued Term ITLB Meaning Instruction translation lookaside buffer L2 Secondary cache LIFO Last in first out LR Link register LRU Least recently used LSB Least significant byte Isb Least significant bit MMU Memory management unit MSB Most significant byte msb Most significant bit MSR Machine state register NaN Not a number NIA Next instruction address No op No operation PTE
2. 49 50 UM0438 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS
3. Table 27 Word compare simplified mnemonics Operation Compare Word Immediate Simplified mnemonic e cmpwi crD rA SIMM Equivalent to e cmpi crD rA SIMM e cmpwi cr0 rA SIMM e cmp16i rA SIMM Compare Word cmpw crD rA rB cmp crD 0 rA rB Compare Logical Word Immediate e_cmplwi crD rA UIMM e_cmpli crD rA UIMM e cmplwi cr0 rA UIMM e_cmpl16i rA UIMM Compare Logical Word cmplw crD rA rB cmpl crD 0 rA rB 4 UMO438 Simplified mnemonics for VLE instructions As with branch mnemonics the crD field of a compare instruction can be omitted if CRO is used as shown in examples 1 nd 3 below Otherwise the target CR field must be specified as the first operand The following examples use word compare mnemonics 1 Compare rA with immediate value 100 as signed 32 bit integers and place result in CRO e_cmpwi rA 100 equivalent to e_cmp16i rA 100 2 Same as 1 but place results in CR4 e_cmpwi cr3 rA 100 equivalent to e_cmpi 3 rA 100 3 Compare rA and rB as unsigned 32 bit integers and place result in CRO cmplw rA rB equivalent to cmpl 0 0 rA rB A 7 Trap instructions simplified mnemonics The codes in Table 28 are for the most common combinations of trap conditions Table 28 Standard codes for trap instructions Code Description TO Encoding lt gt lt uM su It Less than 16 1 0 0 0 0 le Less than or equal 20 1 0 1 0 0
4. LJ UMO438 YZ User manual Variable Length Encoding VLE extension programming interface manual Introduction This user manual defines a programming model for use with the variable length encoding VLE instruction set extension Three types of programming interfaces are described herein m An application binary interface ABI defining low level coding conventions m An assembly language interface m A simplified mnemonic assembly language interface July 2007 Rev 1 1 50 www st com Contents UM0438 Contents luris canta A deen E alee ee eh an eee 7 About this DO sil raced dies he WER AME A Waseem da 7 AU CO 22s ESE CARER GELS RG E PEERS Eee owe REPRESS 7 OIganizdlOhs22ctneantetinsevessicniereneietetsaees O ER REPEHS 7 Suggested reading y 46x p xvssa tor Correas debates eb pd 7 Related documentation cues Erre ea PE a he 8 General information usus awe er i trade o RR Robe ERR ROC ERUR RR S RTL 8 CONVENTIONS 225 ced iae ECCE S OCURRE de tee pee idc dod 8 Terminology conventions oooooccoooooo ene 9 Acronyms and abbreviations emori deoa CER FR ERR reee eng ee 9 1 OVGIVIEW vrai Rh ERRARE ynin EGRE RR E ENG ES E ERE 11 1 1 Application Binary Interface ABI 0 0 00 eee ee eee 11 1 2 Assembly language interface oooooooornronomoonmm 11 13 Simplified mnemonics assembly language interface 11 2 Application Binary Interface ABI 0oo oooo eee e
5. e_bgt crS target Simplified mnemonic Mnemonic e bc 1 B132 target Instruction Branch if greater than e bc without LR updating se bgt target se bc 1 BI16 target Branch if greater than se bc e bgtl crS target e bcl 1 BI325 target Branch if greater than e bcl with LR updating e ble crS target e bc 0 BI325 target Branch if less than or equal e bc without LR updating se ble target se bc 0 BI16 target Branch if less than or equal se bc e blel crS target e bcl 0 BI325 target Branch if less than or equal e bcl with LR updating e bit crS target e bc 1 BI32 target Branch if less than e bc without LR updating se blt target se bc 1 BI16 target Branch if less than se bc e_bltl crS target e bcl 1 BI32 target Branch if less than e_bcl with LR updating e bne crS target e bc 0 BI32 target Branch if not equal e bc without LR updating se bne target se bc 0 B116 target Branch if not equal se bc e bnel crS target e bcl 0 BI132 target Branch if not equal e bcl with LR updating e bngcrS target e bc 0 BI325 target Branch if not greater than e bc without LR updating se bng target se bc 0 BI16 target Branch if not greater than se bc e bngl crS target e bnl crS target e bcl 0 BI325 target e bc 0 BI32 target Branch if not greater than e bcl with LR updating Bra
6. performance The intent of the VLE extension is not to define an entirely different ISA nor to supplant the existing PowerPC ISA Instead it can be viewed as a supplement that is applied conditionally to an application or to part of an application to improve code density The major objectives of the VLE extension are as follows e Maintain coexistence and consistency with the existing PowerPC Book E ISA and architecture e Maintain a common programming model and instruction operation model in the VLE extension e Reduce overall code size by 30 percent over existing PowerPC text segments e Limit the increase in execution path length to under 10 percent for most important applications e Limitthe increase in hardware complexity for implementations containing the VLE extension By meeting these objectives cost sensitive markets may significantly benefit from the use of the VLE extension The VLE extension uses the same semantics as traditional Book E Due to the limited instruction encoding formats VLE instructions typically support reduced immediate fields and displacements and not all Book E operations are encoded in the VLE extension The basic philosophy is to capture all useful operations with most frequent operations given priority Immediate fields and displacements are provided to cover most ranges encountered in embedded control code Instructions are encoded in either a 16 or 32 bit format and these formats can be freely in
7. There are no simplified mnemonics for unconditional branches branch to link register and branch to count register For these the basic mnemonics e b e bl se b se bl se bir se_birl se bctr and se bctrl are used Table 18 Branch simplified mnemonics LR Update Not Enabled LR Update Enabled Branch semantics e bc se bc e bcl Branch if condition true e bt se bt e btl Branch if condition false e bf se bf e bfl Decrement CTR branch if CTR 0 e_bdnz e bdnzl Decrement CTR branch if CTR 0 e_bdz e_bdzl 1 Simplified mnemonics for branch instructions that do not test CR bits should specify only a target Otherwise a programming error may occur Table 19 shows the syntax for basic simplified branch mnemonics Table 19 Branch instructions Simplified Instruction Standard mnemonic Syntax A Syntax mnemonic Branch e_b e_bl tardet addr N A syntax does not include BO32 or se_b se_bl ae BO16 Branch Conditional BO32 BI32 target add e bc e bcl r e bx e bxl BI32 target_addr se bc BO16 BI16 target add se bx BI16 target_addr r Branch to Link se bir se blrl o N A syntax does not include BO32 or Register a BO16 Branch to Count se_betr se bctrl m N A syntax does not include BO32 or Register gt gt BO16 1 xstands for one of the symbols in Table 14 where applicable 2 BI32 or BI16 can be a numeric value or an expression as shown in Table 17 A 5 1 The simplified mnemonics in Table 18 that
8. array index by the width of an element 23 50 Simplified mnemonics for VLE instructions UM0438 A 3 1 Table 12 Operations on words The simplified mnemonics in Table 12 do not support coding with a dot suffix In PowerPC instructions a dot suffix causes the Rc bit to be set in the underlying instruction However the following VLE instruction forms do not support this Word rotate and shift simplified mnemonics Operation Extract and left justify word immediate Simplified mnemonic e_extlwi rA rS n b n gt 0 Equivalent to e rlwinm rA rS b 0 n 1 Extract and right justify word immediate e extrwi rA rS n b n 0 e rlwinm rA rS b n 32 n 31 Insert from left word immediate e inslwi rA rS n b n gt 0 e rlwimi rA rS 32 b b b n 1 Insert from right word immediate e insrwi rA rS n b n gt 0 e rlwimi rA rS 32 b n b b n 1 Rotate left word immediate e rotlwi rA rS n e rlwinm rA rS n 0 31 Rotate right word immediate e rotrwi rA rS n e rlwinm rA rS 32 n 0 31 Shift left word immediate e slwi rA rS n n 32 e rlwinm rA rS n 0 31 n Shift right word immediate e srwi rA rS n n 32 e rlwinm rA rS 32 n n 31 Clear left word immediate e clriwi rA rS n n 32 e rlwinm rA rS 0 n 31 Clear right word immediate Clear left and shift left word immediate e cirrwi r
9. eq Equal 4 0 0 1 0 0 ge Greater than or equal 12 0 1 1 0 0 gt Greater than 8 0 1 0 0 0 nl Not less than 12 0 1 1 0 0 ne Not equal 24 1 1 0 0 0 ng Not greater than 20 1 0 1 0 0 Iit Logically less than 2 0 0 0 1 0 lle Logically less than or equal 6 0 0 1 1 0 lge Logically greater than or equal 5 0 0 1 0 1 Igt Logically greater than 1 0 0 0 0 1 Inl Logically not less than 5 0 0 1 0 1 Ing Logically not greater than 6 0 0 1 1 0 Unconditional 31 1 1 1 1 1 1 2 The symbol U indicates an unsigned less than evaluation is performed The symbol gt U indicates an unsigned greater than evaluation is performed The mnemonics in Table 29 are variations of trap instructions with the most useful TO values represented in the mnemonic rather than specified as a numeric operand 37 50 Simplified mnemonics for VLE instructions UMO438 38 50 Table 29 Trap simplified mnemonics Trap semantics tw Register Trap unconditionally trap Trap if less than twit Trap if less than or equal twle Trap if equal tweq Trap if greater than or equal twge Trap if greater than twgt Trap if not less than twnl Trap if not equal twne Trap if not greater than twng Trap if logically less than twilt Trap if logically less than or equal twlle Trap if logically greater than or equal twlge Trap if logically greater than twigt Trap if logically not less than twin Trap if logi
10. se bc 1 B116 target Simplified mnemonic se bit target Branch if less than or equal e bc e ble crS target se bc 0 BI16 target se ble target Branch if not less than Branch if greater than e bc 1 B1322 target e bnl crS target e bgt crS target se bc 1 BI16 target Branch if not greater than 2 e bn g 0 BI32 target ura se_bng target Branch if equal e_bc e_be q 1 B1320 target Paren se_bc 1 BI163 target se beq target jee if greater than or ns se_bge target equa e_be 0 B132 target Crs target se bc 0 B116 target se bnl target se bgt target Branchiif not egua e bc 0 BI32 target e bne se bc 0 B116 target se bne target crS target Branch if summary overflow e_bso se_bso target e be crS target i 4 BI324 t t se bc 1 Bl16 target Branch if unordered targe e_bun se_bun target crS target Branch if not summary e_bns se_bns target overflow crS target a e bc 0 BI32 target se bc 0 Bl16 target Branch if not unordered e bnu se bnu target crS target 1 The value in the BI32 or BI16 operand selects CRn 0 the LT bit 2 The value in the BI32 or BI16 operand selects CRn 1 the GT bit ky 35 50 Simplified mnemonics for VLE instructions UM0438 3 The value in the BI32 or BI16 operand selects CRn 2 the EQ bit 4 The value in the BI32 or BI16 operand selects CRn 3 the SO bit A 6 36 50 Table 2
11. 15 0 6 7 3 3 bdh24 E bdh24 ky 15 50 Application Binary Interface ABI UMO438 Table 5 VLE relocation fields continued 0 1 1 3 3 bdh15 5 6 0 1 bdh15 0 7 8 1 bdh8 5 bdh8 Table 6 describes the additional relocation fields required by VLE instructions Table 6 VLE relocation field descriptions Field Descriptions low21 21 bit field occupying the Isbs of a word bits 11 31 20 bit field with the 4 msbs occupying bits 17 20 the next 5 bits occupying bits 11 15 and the remaining 11 bits occupying bits 21 31 In addition bits 0 5 in the destination word are encoded with the binary split20 value 011100 bit 16 is encoded with the binary value O R This relocation field specifies the opcode for the VLE e_li instruction allowing the linker to force the encoding of the e_li instruction potentially changing the user s specified instruction This functionality supports small data area relocation types R_PPC_VLE_SDA21 and R_PPC_VLE_SDA21_LO 16 bit field with the 5 msbs occupying bits 11 15 the rA field and the remaining 11 bits occupying bits spliti6a 21 31 spliti6d 16 bit field with the 5 msbs occupying bits 6 10 the rD field and the remaining 11 bits occupying bits 21 31 bdh24 24 bit field occupying bits 7 30 used to resolve branch displacements to half word boundaries bdh15 15 bit field occupying bits 16 30 used to resol
12. 4 crO so un or 3 35 00 11 11 summary overflow or floating point unordered so un so fu 4 cr1 so un 7 39 01 for integer compare instructions this is a copy 4 cr2 so un 11 43 10 tef xer so at instruction completion 4 cr3 so un 15 47 11 __ for floating point compare instructions one or both of fra and frb is a nan Only the most useful simplified mnemonics are found in Section A 5 Simplified mnemonics that incorporate the BO32 and BO16 operands Unusual cases can still be coded using a standard branch conditional syntax The crS operand The crS symbols are shown in Table 17 Note that either the symbol or the operand value can be used in the syntax used with the simplified mnemonic Table 17 CR field identification symbols Symbol BI32 0 1 BI16 CR Bits crO default can be eliminated from syntax 00 Implied 32 35 cri 01 36 39 cr2 10 40 43 cr3 11 44 47 To identify a CR bit an expression in which a CR field symbol is multiplied by 4 and then added to a bit number within CR field symbol can be used for example crO 4 eq 30 50 Ti UMO438 Simplified mnemonics for VLE instructions A 5 Simplified mnemonics that incorporate the BO32 and BO16 operands The mnemonics in Table 18 allow common BO32 and BO16 operand encodings to be specified as part of the mnemonic along with the set link register bit LK
13. EMB sbssO the linker supplies a value of 0 otherwise the link fails The 16 Isbs of this 21 bit value are set to the address of the symbol plus the relocation entry r_addend value minus the appropriate base for the symbol section _SDA_BASE_ for a symbol in sdata or sbss _SDA2_BASE_ for a symbol in PPC EMB sdata2 or PPC EMB sbss2 O for a symbol in PPC EMB sdata0 or PPC EMB sbssO If the 5 msbs of the computed 21 bit value are non zero the linker uses the low21 relocation field where the 11 msbs remain unchanged and the computed 21 bit value occupies bits 11 31 Otherwise the 5 msbs of the computed 21 bit value are zero with the following results The linker uses the split20 relocation field where only bits occupying 6 10 remain unchanged The 5 msbs of the 21 bit value are ignored The next msb is copied to bit 11 and to bits 17 20 as a sign extension The next 4 msbs are copied to bits 12 15 The 11 remaining bits are copied to bits 21 31 In the destination word bits 0 5 are encoded with the binary value 011100 and bit 16 is encoded with the binary value O Use of the split20 relocation field forces the encoding of the VLE e li instruction which may change the user s specified instruction See Table 6 R PPC VLE SDA21 LO Like R PPC VLE SDA 1 except that the lo operator obtains the 16 Isbs of the 21 bit value The tlo operator is applied after the address of the symbol plus the relocation e
14. Page table entry RISC Reduced instruction set computing RTL Register transfer language SIMM SPR Signed immediate value Special purpose register TLB Translation lookaside buffer UIMM Unsigned immediate value UISA User instruction set architecture VA Virtual address VLE XER Variable length encoding Register used primarily for indicating conditions such as carries and overflows for integer operations 10 50 4 UM0438 Overview 1 1 Note 1 2 1 3 Overview This document defines a programming model for use with the variable length encoding VLE instruction set extension Three types of programming interfaces are described herein e Anapplication binary interface ABI defining low level coding conventions e Anassembly language interface e Asimplified mnemonic assembly language interface Application Binary Interface ABI The VLE programming model extends the existing PowerPC ABIs This extension is independent of the endian mode with regard to data however VLE instructions are supported only in big endian mode The ABI reviews instruction and data representations for memory management and distinguishes between PowerPC Book E and VLE instructions The ABI also discusses VLE section identification and relocation types used by the executable and linking format ELF Use this chapter in conjunction with the PowerPC e500 Applic
15. UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2007 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Swede
16. and se bc without LR updating equivalent to e_bc 0 15 target Simplified mnemonics for e_bc and se_bc without LR update Branch semantics Branch if condition true Simplified mnemonic e_bc Simplified se_bc mnemonic e bc 1 BI32 target e_bt PET target se_bc1 Bl16 target se bt Bl16 target Branch if condition false e bc 0 BI32 target e bf BI32 target se bc 0 B116 target se bf Bl16 target CTRz0 CTR 20 Decrement CTR branch if Decrement CTR branch if e bc 2 0 target e bdnz target e_bc 3 0 target e_bdz target 1 Instructions for which B032 is either 1 branch if condition true or O branch if condition false do not depend on the CTR value and can be alternately coded by incorporating the condition specified by the BI32 field as described in Section A 5 2 Simplified mnemonics that incorporate CR conditions eliminates BO32 and BO16 and replaces BI32 with crS 2 Simplified mnemonics for branch instructions that do not test CR bits should specify only a target Otherwise a programming error may occur Table 21 Table 21 provides simplified mnemonics and syntax for e bcl Simplified mnemonics for e_bcl with LR update Simplified Branch semantics Branch if condition true e_bcl e_bcl 1 B132 target mnemonic e_btl BI32 target Branch if condition false e bcl 0 B132 target e bfl BI32 target 32 50 ky UMO438
17. examples 35 A 5 4 Branch simplified mnemonics that incorporate CR conditions listings 35 A 6 Compare word simplified MnemonicS o ocooococcconoo 36 A 7 Trap instructions simplified mnemonics llle 37 A 8 Simplified mnemonics for accessing SPRS 00 e eee ee 39 A 9 Recommended simplified mnemonics llle 40 A 9 1 No Op hOoD sisit sates hase e 244 ge a eb Gs 40 A 9 2 Load Address la 1 2 20 0000 eee 40 A 9 3 Move Register mr 0 0 000 ee eee 40 A 9 4 Complement Register not ooococccoccc leise 40 A 9 5 Move to Condition Register mtcr 00 0c eee eee 40 A 10 EIS Specific simplified mnemonics 0000 e eee ee 41 A 10 1 Integer Select isel 0 00 00 c cee 41 A 11 Comprehensive list of simplified mnemonics ursus 41 Appendix B Glossary ici ciccc deci ad a ed ad de CR EC ced 45 Mio A Ml Ahead nd hae ewe ed 45 c CDI 45 P ETT 45 P ari e dd a O A ae 45 EU eek ala A a paa bd es 45 A E E E 46 PITT 46 rcc 46 er rM MM 46 ETT 46 c EP 47 E E A A nts See eee ata Bee oa eee 47 ky 3 50 Contents UM0438 MERE 47 je cT 48 ls II t ALI IL EU M LAE E 48 P MT REA 48 4 REVISION history iacu A COR Rab C e ee eee hes 49 4 50 ky UM0438 List of tables List of tables Table 1 Table 2 Table 3 Table 4 Table 5 T
18. in memory where the address n of a word corresponds to the most significant byte In an addressed memory word the bytes are ordered left to right O 1 2 3 with O being the most significant byte See Little endian Cache High speed memory component containing recently accessed data and or instructions subset of main memory Denormalized number A nonzero floating point number whose exponent has a reserved value usually the format s minimum and whose explicit or implicit leading significant bit is zero Effective address EA The 32 or 64 bit address specified for a load store or an instruction fetch This address is then submitted to the MMU for translation to either a physical memory address or an I O address ki 45 50 Glossary UMO438 Exponent In the binary representation of a floating point number the exponent is the component that normally signifies the integer power to which the value two is raised in determining the value of the represented number See also Biased exponent G General purpose register GPR Any of the 32 registers in the general purpose register file These registers provide the source operands and destination results for all integer data manipulation instructions Integer load instructions move data from memory to GPRs and store instructions move data from GPRs to memory l IEEE 754 A standard written by the Institute of Electrical and Electronics Engineers that defines operations and repr
19. is needed If the test bit is in CR1 CR3 the BI32 operand can be replaced with a crS operand that is cr1 cr2 or cr3 The BI16 operand cannot be used for test bits that are not in CRO Eliminating the BO32 and BO16 operands The 2 bit BO32 field shown in Figure 1 encodes the following operations in 32 bit conditional branch instructions e Decrement count register CTR Andtestif result is equal to zero And test if result is not equal to zero e Testcondition register CR Test condition true Test condition false UMO438 Simplified mnemonics for VLE instructions The 1 bit BO16 field shown in Figure 1 encodes the following operations in 16 bit conditional branch instructions e Test condition register CR Test condition true Test condition false As shown in Table 14 the c in the standard mnemonic is replaced with the operations otherwise specified in the BO32 or BO16 field d for decrement z for zero nz for non zero t for true and f for false Table 14 BO32 and BO16 operand encodings BO32 BO16 Value Field Field Decimal Description Symbol 00 0 0 Branch if the condition is FALSE f 01 1 1 Branch if the condition is TRUE t 10 2 Decrement the CTR then branch if the decremented CTR 0 dnz 9 117 3 Decrement the CTR then branch if the decremented CTR 0 dz 1 Instructions for which BO32 or BO16 are O branch if condition tr
20. the XER mtxer rS equivalent to mtspr 1 rS 2 Copy the contents of the LR to rS mflr rD equivalent to mfspr rD 8 3 Copy the contents of rS to the CTR mtctr rS equivalent to mtspr 9 rS The examples above show simplified mnemonics for accessing SPRs defined by the AIM version of the PowerPC architecture however the same formula is used for Book E EIS and implementation specific SPRs as shown in the following examples 1 Copy the contents of rS to CSRRO mtcsrr0 rS equivalent to mtspr 58 rS 2 Copy the contents of IVORO to rS mfivor0 rD equivalent to mfspr rD 400 3 Copy the contents of rS to the MAS1 mtmasl1 rS equivalent to mtspr 625 rS There are additional simplified mnemonics for accessing SPRGs which are not all supported by all assemblers These mnemonics are shown in Table 31 along with the equivalent simplified mnemonic using the formula described in this section Additional simplified mnemonics for Accessing SPRGs SPR SPRGs Move to SPR Move from SPR Simplified mnemonic Equivalent to Simplified mnemonic Equivalent to mtsprg n rS mfsprg rD n mtspr 272 n rS mfspr rD 272 n mtsprgn rS mfsprgn rD 39 50 Simplified mnemonics for VLE instructions UMO438 A 9 A 9 1 A 9 2 A 9 3 A 9 4 A 9 5 40 50 Recommended simplified mnemonics This section describes commonly used operations such as no op load immediate load address move register and complemen
21. the meanings described in Table 15 Table 16 BI32 and BI16 operand settings for CR fields for branch comparisons CR bits bi32 bi16 crn ae bit bit expression AIM BI Description Book E 0 1 2 3 0 1 operand crn 0 4 crO It orit O 32 00 00 00 less than or floating point less than It fl 4 cr1 It 4 36 01 for integer compare instructions 4 cr2 It 8 40 10 ra simm or rb signed comparison or ra lt 4 cr34 It 12 44 11 uimm or rb unsigned comparison for floating point compare instructions fra frb ky 29 50 Simplified mnemonics for VLE instructions UMO438 Table 16 BI32 and BI16 operand settings for CR fields for branch comparisons continued CR bits bi32 bi16 Pa bit expression AIM BI ee Peres Description operand crn 1 4 crO gt or gt 1 33 00 01 01 greater than or floating point greater than gt 4 crl gt 5 37 01 fg 4 cr2 gt 9 41 10 for integer compare instructions 4 cr3 gt 13 45 11 jn simm or rb signed comparison or ra gt uimm or rb unsigned comparison for floating point compare instructions fra gt frb crn 2 4 crO eq or eq 2 34 00 10 10 equal or floating point equal eq fe 4 cr1 eq 6 38 01 __ for integer compare instructions ra simm 4 cr2 eq 10 42 10 uimm or rb 4 cr3 eq 14 46 11 for floating point compare instructions fra frb crn 3
22. where the linker placed the symbol whose index is in r_info Represents a 5 bit value for the base register for the section where the linker placed the symbol whose index is in r_info Acceptable values are the value 13 for symbols in sdata or Sbss the value 2 for symbols in PPC EMB sdata2 or PPC EMB sbss2 or the value O for symbols in PPC EMB sdata0 or PPC EMB sbss0 Relocation entries apply to half words or words In either case the r offset value designates the offset or virtual address of the first byte of the affected storage unit The relocation type specifies which bits to change and how to calculate their values Processors that implement the PowerPC architecture use only the EIf32 Rela relocation entries with explicit addends For relocation entries the r addend member serves as the relocation addend In all cases the offset addend and the computed result use the byte order specified in the ELF header The following general rules apply to the interpretation of the relocation types in Table 8 and denote 32 bit modulus addition and subtraction Il denotes concatenation of bits or bit fields gt gt denotes arithmetic right shifting shifting with sign copying of the value of the left operand by the number of bits given by the right operand For relocation types associated with branch displacements in which the name of the relocation type contains 8 the upper 24 bits of the computed value before
23. 6 Table 26 shows simplified branch mnemonics and syntax for e_bel updating Simplified mnemonics for e_bcl with comparison conditions and LR Branch semantics Branch if less than e_bcl e bcl 1 B132 target Simplified mnemonic e_bltl crS target Branch if less than or equal Branch if not greater than e_bel 0 BI322 target e_blel crS target e_bngl crS target Branch if equal e bcl 1 B132 target e_beql crS target Branch if greater than or equal Branch if not less than e bcl 0 B132 target e bgel crS target e bnll crS target Branch if greater than e bcl 1 BI32 target e bgtl crS target Branch if not equal e bcl 0 BI32 target e bnel crS target Branch if summary overflow Branch if unordered e bcl 1 B132 target e bsol crS target e bunl crS target Branch if not summary overflow Branch if not unordered e bcl 0 B132 target e bnsl crS target e bnul crS target qe 20 qct The value in the BI32 operand selects CRn 0 the LT bit The value in the BI32 operand selects CRn 1 the GT bit The value in the BI32 operand selects CRn 2 the EQ bit The value in the BI32 operand selects CRHn 3 the SO bit Compare word simplified mnemonics In compare word instructions the L operand indicates a word L 0 or double word L 1 Simplified mnemonics in Table 27 eliminate the L operand for word comparisons
24. A rS n n lt 32 e clrisiwi rA rS b n nx b lt 31 e rlwinm rA rS 0 0 31 n e rlwinm rA rS n b n31 n A 4 24 50 Examples using word mnemonics follow 1 Extract the sign bit bit 0 of rS and place the result right justified into rA e_extrwi rA rS 1 0 equivalent to e_rlwinm rA rS 1 31 31 2 Insert the bit extracted in 1 into the sign bit bit 0 of rB e insrwi rB rA 1 0 equivalent to 3 Shift the contents of rA left 8 bits e_slwi rA rA 8 e_rlwinm rA rA 8 0 23 4 Clear the high order 16 bits of rS and place the result into rA e_clrlwi rA rS 16 equivalent to e_rlwinm rA rS 0 16 31 e rlwimi rB rA 31 0 0 equivalent to Branch instruction simplified mnemonics Branch conditional instructions can be coded with the operations and with a condition to be tested as part of the instruction mnemonic rather than as numeric operands the BO32 BI32 and BO16 BI16 operands Table 13 shows the four general types of branch instructions Simplified mnemonics are defined only for branch conditional instructions that include either the BO32 BI32 or BO16 BI16 operands there is no need to simplify the other branch mnemonics UMO438 Simplified mnemonics for VLE instructions Table 13 Branch instructions Instruction name Mnemonic Syntax Branch e b e bl target_addr se_b se_bl target_addr Branch Conditional e_bc e_bcl BO32 B132 target_addr se bc BO16 Bl16 target addr Branch to Link R
25. An error condition that occurs during arithmetic operations when the result cannot be stored accurately in the destination register s For example if two 32 bit numbers are multiplied the result may not be representable in 32 bits Record bit Bit 31 or the Rc bit in the instruction encoding When it is set updates the condition register CR to reflect the result of the operation Its presence is denoted by a following the mnemonic Reserved field In a register a reserved field is one that is not assigned a function A reserved field may be a single bit The handling of reserved bits is implementation dependent Software is permitted to write any value to such a bit A subsequent reading of the bit returns O if the value last written to the bit was O and returns an undefined value 0 or 1 otherwise RISC reduced instruction set computing An architecture characterized by fixed length instructions with nonoverlapping functionality and by a separate set of load and store instructions that perform memory accesses Saturate A value V which lies outside the range of numbers representable by a destination type is replaced by the representable number closest to V Signaling NaN A type of NaN that generates an invalid operation program exception when it is specified as arithmetic operands See Quiet NaN Significand The component of a binary floating point number that consists of an explicit or implicit leading bit to th
26. E technology implementations are beyond the scope of this manual Each processor is unique in its implementation of the VLE extension The information in this book is subject to change without notice As with any technical documentation it is the reader s responsibility to ensure they are using the most recent version of the documentation For more information contact your sales representative Audience This manual is for system software and application programmers who want to develop products using the VLE extension An understanding of operating systems microprocessor system design the basic principles of RISC processing and the VLE instruction set is assumed Organization Following is a summary of the major sections of this manual e Section 1 Overview provides a general understanding of what the programming model defines in the VLE extension e Section 2 Application Binary Interface ABI describes the VLE extensions for the PowerPC e500 Application Binary Interface e500 ABI to support VLE technology e Section 3 Instruction set provides an overview of the VLE instruction set architecture For a detailed description of each instruction including assembly language syntax refer to the VLE section of the EREF e Appendix A Simplified mnemonics for VLE instructions describes simplified mnemonics which are provided for easier coding of assembly language programs using VLE technology Suggested reading This section lists
27. LE_REL24 218 bdh24 S A P gt gt 1 R_PPC_VLE_LO16A 219 splitl a lo S A 17 50 Application Binary Interface ABI UM0438 18 50 Table 8 VLE relocation types continued Name Value Field Calculation R_PPC_VLE_LO16D 220 split16d lo S A R_PPC_VLE_HI16A 221 spliti6a hi S A R_PPC_VLE_HI16D 222 split16d hi S A R_PPC_VLE_HA16A 223 spliti6a ha S A R_PPC_VLE_HA16D 224 split16d ha S A R_PPC_VLE_SDA21 225 low21 Y II X A See Table 9 split20 R_PPC_VLE_SDA21_LO 226 low21 Y lo X A See Table 9 split20 R_PPC_VLE_SDAREL_LO16A 227 spliti6a lo X A R PPC VLE SDAREL LO16D 228 split16d lo X A R_PPC_VLE_SDAREL_HI16A 229 spliti6a hi X A R_PPC_VLE_SDAREL_HI16D 230 split16d hi X A R_PPC_VLE_SDAREL_HA16A 231 spliti6a ha X A R_PPC_VLE_SDAREL_HA16D 232 split16d ha X A Relocation types with special semantics are described in Table 9 UM0438 Application Binary Interface ABI Table 9 Relocation types with special semantics Name R_PPC_VLE_SDA21 Description The linker computes a 21 bit value with the 5 msbs having the value 13 for GPR13 2 for GPR2 or O If the symbol whose index is in r_info is contained in sdata or sbss a linker supplies a value of 13 if the symbol is in PPC EMB sdata2 or PPC EMB sbss2 the linker supplies a value of 2 if the symbol is in PPC EMB sdata0 or PPC
28. Simplified mnemonics for VLE instructions Table 24 Simplified mnemonics for e bcl with LR update continued Branch semantics e_bcl Simplified mnemonic Decrement CTR branch if CTR 0 e_bcl 2 0 target e_bdnzl target 2 Decrement CTR branch if CTR 0 e_bcl 3 0 target e bdzl target 2 1 Instructions for which B032 is either 1 branch if condition true or O branch if condition false do not depend on the CTR value and can be alternately coded by incorporating the condition specified by the BI32 field See Section A 5 2 Simplified mnemonics that incorporate CR conditions eliminates BO32 and BO16 and replaces BI32 with crS 2 Simplified mnemonics for branch instructions that do not test CR bits should specify only a target Otherwise a programming error may occur A 5 2 Simplified mnemonics that incorporate CR conditions eliminates BO32 and BO16 and replaces BI32 with crS The mnemonics in Table 24 are variations of the branch if condition true BO32 1 or BO16 1 and branch if condition false BO32 0 or BO16 0 encodings Because these instructions do not depend on the CTR the true false conditions specified by either BO32 or BO16 can be combined with the CR test bit specified by the BI32 or BI16 operand to create a different set of simplified mnemonics that eliminates the BO32 and BO16 operands and the portion of the BI32 and BI16 operands BI32 2 3 and BI16 0 1 that specifies one of the four possibl
29. Subtract 2 operand immediate and recorded e sub2is rA value e add2is rA value Subtract 2 operand shifted immediate e subi rD rA value e addi rD rA value Subtract immediate e subic rD rA value e addic rD rA value Subtract immediate carrying e subic rD rA value e addic rD rA value Subtract immediate carrying trap tw 31 0 0 Trap unconditionally tweq rA rB tw 4 rA rB Trap if equal twge rA rB tw 12 rA rB Trap if greater than or equal twgt rA rB tw 8 rA rB Trap if greater than twle rA rB tw 20 rA rB Trap if less than or equal twlge rA rB tw 12 rA rB Trap if logically greater than or equal twigt rA rB tw 1 rA rB Trap if logically greater than twile rA rB tw 6 rA rB Trap if logically less than or equal twllt rA rB tw 2 rA rB Trap if logically less than twing rA rB tw 6 rA rB Trap if logically not greater than twinl rA rB tw 5 rA rB Trap if logically not less than twit rA rB tw 16 rA rB Trap if less than twne rA rB tw 24 rA rB Trap if not equal twng rA rB tw 20 rA rB Trap if not greater than twnl rA rB tw 12 rA rB Trap if not less than 1 Simplified mnemonics for branch instructions that do not test a CR bit should not specify one a programming error may occur The value in the BI32 or BI16 operand selects CRn 2 the EQ bit Instructions for which B032 or BO16 is either 1 branch if condition true or O branch if condition false do no
30. able 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Terminology conventions 0 ccc mn 9 Acronyms and abbreviated terms 2 2 0 0 ec es 9 Typical Elf note section forMat o ooooccocccco meh 13 VUE identifier 2s ci a ta Rp A eae ee e m redeo a le eee 13 VLE relocation fields iscr tiroarieiers aseessa dria and tee 15 VLE relocation field descriptions 1 0 2 0 00 cee eee 16 Notation conventions 00 eens 16 VLE relocation typeS 1 2 tte un 17 Relocation types with special semantics oooocococccooo ee 19 Subtract immediate simplified mnemonics 0000 cece eae 23 Subtract simplified mnemonics 0000 0c tetas 23 Word rotate and shift simplified mnemonics llli 24 Branch instructions 20 260 s 0 ee e ene don aed ee ee a Ra e ad nex 25 BO32 and BO16 operand encodings ooooccccccoc eee 27 CRO and CR1 fields as updated by integer and floating point instructions 29 BI32 and BI16 operand settings for CR fields for branch comparisons 29 CR field identification symbols 00 0c ects 30 Branch simplified MNemMonicS ooocccooccccoo nn 31 Branch instructions ora ui dee SE 3 G3 eee e
31. addition to CTR operations the BO32 operand provides branch decisions based on true or false conditions For example if a branch instruction depends on an equal condition in CRO the expression is e bc 1 2 target To specify a true condition the BO32 value becomes 1 the CRO equal field is indicated by a BI32 value of 2 Incorporating the branch if true condition a t is used to replace the c in the original mnemonic e bt The BI32 value of 2 is replaced by the eq symbol Using the simplified mnemonic and the eq operand the expression becomes e bt eq target This example tests CRO EQ however to test the equal condition in CR3 CR bit 14 the expression becomes e bc 1 14 target The BI32 operand of 14 indicates CR 14 CR3 2 or 77 25 50 Simplified mnemonics for VLE instructions UMO438 A 4 1 A 4 2 26 50 BI32 field 0b1110 This can be expressed as the simplified mnemonic e_bt 4 x cr3 eq target The notation 4 x cr3 eq may at first seem awkward but it eliminates computing the value of the CR bit It can be seen that 4 x 3 2 14 Note that although 32 bit registers in Book E processors are numbered 32 63 only values 0 15 are valid or possible for BI32 operands A Book E compliant processor automatically translates the BI32 bit values specifying a BI32 value of 14 selects bit 46 on a Book E processor or CR3 2 CR3 EQ To reduce code size VLE provides a 16 bit conditional branch instruction that u
32. additional relocation types which allow the linker to resolve immediate and branch displacement fields in the instruction encoding once a symbol or label address is known at link time The VLE encodings require additional relocation types to resolve fields not present in the PowerPC Book E encodings 2 2 1 VLE information section The e500 ABI defines an information section named PPC EMB apuinfo having type SHT_NOTE and attributes of O which matches the format of a typical ELF note section as shown in Table 3 The information section allows disassemblers and debuggers to interpret the instructions properly within the binary and can be used by operating systems to provide emulation or error checking of the VLE extension revisions Table 3 Typical Elf note section format length of name in bytes length of data in bytes type name null terminated padded to 4 byte alignment data For the PPC EMB apuinfo section the name is APUinfo the type is 2 as type 1 is already reserved and the data contains a series of words providing information about the APU or extension one per word The information contains two unsigned half words the upper half contains the unique identifier and the lower half contains the revision number The VLE identifier is shown in Table 4 Table 4 VLE identifier Identifier 16 Bits APU Extension 0x0104 VLE Example Object file a o 0 0x00000008 8 bytes i
33. ate and shift and certain other instructions defined by the VLE extension The simplified mnemonics for the VLE extension are similar to those defined for the PowerPC programming environment The result is a consistent programming view when working with VLE instructions on PowerPC architectures Section A 11 Comprehensive list of simplified mnemonics provides an alphabetical listing of VLE simplified mnemonics used by a variety of processors Some assemblers may define additional simplified mnemonics not included here The simplified mnemonics listed here should be supported by all compilers Overview Simplified or extended mnemonics allow an assembly language programmer to use more intuitive mnemonics and symbols than the instructions and syntax defined by the instruction set architecture For example to code the conditional call branch to target if CR3 specifies a greater than condition setting the LR without simplified mnemonics the programmer would write the branch conditional and link instruction e bcl 1 13 target The simplified mnemonic branch if greater than and link e bgtl cr3 target incorporates the conditions Not only is it easier to remember the symbols than the numbers when programming it is also easier to interpret simplified mnemonics when reading existing code Simplified mnemonics are not a formal part of the architecture but rather a recommendation for assemblers that support the instruction set Simplified mnemo
34. ation Binary Interface e500 ABI Except for the sections discussed in this chapter the VLE ABI follows the e500 ABI standard For information on register usage and availability function calling sequence parameter passing stack frames and other topics refer to the e500 ABI Assembly language interface The assembly language interface provides an overview of the VLE instructions The description of each instruction along with the instruction mnemonic and operands can be found in the VLE section of the EREF Simplified mnemonics assembly language interface Simplified mnemonics are provided for easier coding of assembly language programs They are defined for the most frequently used forms of branch conditional compare trap rotate and shift and certain other instructions defined by the VLE extension Some assemblers may define additional simplified mnemonics not listed in this document however all assemblers should support the VLE simplified mnemonics listed in Appendix A 11 50 Application Binary Interface ABI UMO438 2 Note Note 2 1 2 2 12 50 Application Binary Interface ABI The ABI extensions described herein for VLE applications are still under review by the PowerPC ABI industry working group and may be subject to change Any modifications will be highlighted in revisions of this document This chapter specifies VLE extensions to the PowerPC e500 Application Binary Interface e500 ABI that defin
35. background reading for this manual as well as general information on the VLE extension and PowerPC architecture ky 7 50 Preface UM0438 Related documentation STMicroelectronics processor documentation is organized in the following types of documents e RM0004 A Programmer s Reference Manual for Book E processor A higher level view of the programming model as it is defined by Book E e Users manuals Provide details on individual implementations and are for use with the Programming Environments Manual for 32 Bit Implementations of the PowerPC Architecture e Datasheet Specific data regarding bus timing signal behavior and AC DC and thermal characteristics as well as other design considerations e Application notes Address specific design issues useful to programmers and engineers working with STMicroelectronics processors Additional literature is released as new processors become available General information The following documentation published by Morgan Kaufmann Publishers 340 Pine Street Sixth Floor San Francisco CA provides useful information on the PowerPC architecture and computer architecture in general e The PowerPC Architecture A Specification for a New Family of RISC Processors Second Edition by International Business Machines Inc e For updates to the specification see http www austin ibm com tech ppc chg html e Computer Architecture A Quantitative Approach Third Editio
36. cally not greater than twing The following examples use the trap mnemonics shown in Table 29 1 Trap if rA is not equal to rB twne rA rB equivalent to tw 24 rA rB 2 Trap unconditionally trap equivalent to tw 31 0 0 Trap instructions evaluate a trap condition by comparing the contents of rA with the contents of rB The comparison results in five conditions that are ANDed with operand TO If the result is not O the trap exception handler is invoked See Table 30 for these conditions Table 30 TO operand Bit Encoding TO Bit ANDed with condition 0 Less than using signed comparison 1 Greater than using signed comparison 2 Equal 3 Less than using unsigned comparison 4 Greater than using unsigned comparison UM0438 Simplified mnemonics for VLE instructions A 8 Table 31 Simplified mnemonics for accessing SPRs The mtspr and mfspr instructions specify a special purpose register SPR as a numeric operand Simplified mnemonics are provided that represent the SPR in the mnemonic rather than requiring it to be coded as a numeric operand The pattern for mtspr and mfspr simplified mnemonics is straightforward replace the spr portion of the mnemonic with the abbreviation for the spr for example XER SRRO or LR eliminate the SPRN operand leaving the source or destination GPR operand rS or rD Following are examples using the SPR simplified mnemonics 1 Copy the contents of rS to
37. cs not listed here Table 32 Simplified mnemonics Simplified mnemonic e bdnz target Mnemonic e bc 2 0 target Instruction Decrement CTR branch if CTR 0 e bc without LR update e bdnzl target e bcl 2 0 target Decrement CTR branch if CTR z 0 e bcl with LR update e bdz target e bdzl target e bc 3 0 target e bcl 3 BI32 target Decrement CTR branch if CTR 0 e bc without LR update Decrement CTR branch if CTR 0 e_bel with LR update e_beq crS target e bc 1 BI1322 target Branch if equal e_be without LR updating se_beq target se bc 1 BI16 target Branch if equal se bc e begl crS target e bf BI32 target e bcl 1 BI32 target e bc 0 BI32 target Branch if equal e bcl with LR updating Branch if condition false 9 e bc without LR update se bf Bl16 target se bc O BI16 target Branch if condition false se bc e bfl BI32 target e bcl 0 B132 target Branch if condition false e bcl with LR update e bge crS target e bc 0 BI32 target Branch if greater than or equal e bc without LR updating se bge target e bgel crS target se bc 0 BI16 target e bcl 0 BI32 target Branch if greater than or equal se bc Branch if greater than or equal e bcl with LR updating ky 41 50 Simplified mnemonics for VLE instructions UM0438 Table 32 Simplified mnemonics continued
38. e ee ee 31 Simplified mnemonics for e bc and se bc without LR update 32 Simplified mnemonics for e bcl with LR update 0 00 eee 32 Standard coding for branch conditions llle 33 Branch instructions and simplified mnemonics that incorporate CR conditions 34 Simplified mnemonics with comparison CONdItiONS ooooococccorocooco ooo 34 Simplified mnemonics for e bc and se bc without comparison conditions or LR updating35 Simplified mnemonics for e_bel with comparison conditions and LR updating 36 Word compare simplified MNemonicS ooooccocccccooo eee 36 Standard codes for trap instructions liliis 37 Trap simplified MNemMonicS oooccococccoco e I I nh 38 TO operand Bit ENCOdINQ ooccoccocco res 38 Additional simplified mnemonics for Accessing SPRGS 0000 0c eee eee 39 Simplified mnemonics 000 00a 41 Document revision history o ooocooccococcc eee 49 5 50 List of figures UMO438 List of figures Figure 1 Branch conditional e bc se bc instruction formats ooooooccooooooo 25 Figure 2 Bl32andBI16 fieldS oooooocccoocccnror e I REE 28 6 50 UMO438 Preface Preface About this book The primary objective of this manual is to help programmers provide software that is compatible across the family of processors using variable length encoding VLE extension Individual VL
39. e left of its implied binary point and a fraction field to the right Sticky bit A bit that when set must be cleared explicitly 47 50 Glossary UMO438 Supervisor mode The privileged operation state of a processor In supervisor mode software typically the operating system can access all control registers and can access the supervisor memory space among other privileged operations T Tiny A floating point value that is too small to be represented for a particular precision format including denormalized numbers they do not include 0 U Underflow An error condition that occurs during arithmetic operations when the result cannot be represented accurately in the destination register For example underflow can happen if two floating point fractions are multiplied and the result requires a smaller exponent and or mantissa than the single precision format can provide In other words the result is too small to be represented accurately User mode The unprivileged operating state of a processor used typically by application software In user mode software can only access certain control registers and can access only user memory space No privileged operations can be performed Also referred to as problem state W Word A 32 bit data element 48 50 ky UM0438 Revision history 4 Revision history Table 33 Document revision history Date 1 July 2007 Revision 1 Initial release Changes
40. e test bits However for simplified mnemonics using the BO32 operand the simplified mnemonic cannot specify in which of the four CR fields CRO CR3 the test bit falls so the BI32 operand is replaced by a crS operand The standard codes shown in Table 22 are used for the most common combinations of branch conditions For ease of programming these codes include synonyms for example less than or equal le and not greater than ng achieve the same result Note A CR field symbol cr0 cr3 is used as the first operand after the simplified mnemonic If the default CRO is used no erS is necessary Table 22 Standard coding for branch conditions Code Description Equivalent Bit Tested It Less than LT le Less than or equal equivalent to ng ng GT eq Equal EQ ge Greater than or equal equivalent to nl ni LT gt Greater than GT nl Not less than equivalent to ge ge LT ne Not equal EQ ng Not greater than equivalent to le le GT so Summary overflow SO ns Not summary overflow SO un Unordered after floating point comparison SO nu Not unordered after floating point comparison SO 77 33 50 Simplified mnemonics for VLE instructions UM0438 Table 23 shows the syntax for simplified branch mnemonics that incorporate CR conditions Here crS replaces a BI32 operand to specify only a CR field because the specific CR bit within the field is now pa
41. e underlying instruction mr rA rS equivalent to or rA rS rS Complement Register not Several instructions can be coded to complement the contents of one register and place the result into another register A simplified mnemonic allows this operation to be coded easily The following instruction complements the contents of rS and places the result into rA This mnemonic can be coded with a dot suffix to cause the Rc bit to be set in the underlying instruction not rA rS equivalent to nor rA rS rS Move to Condition Register mtcr The mtcr mnemonic permits copying the contents of a GPR to the CR using the same syntax as the mfcr instruction mtcr rS equivalent to mtcrf OXFErS UM0438 Simplified mnemonics for VLE instructions A 10 EIS Specific simplified mnemonics This section describes simplified mnemonics used by auxiliary processing units APUs defined as part of the Book E implementation standards EIS A 10 1 Integer Select isel The following mnemonics simplify the most common variants of the isel instruction that access CRO Integer Select Less Than isellt rD rA rB Integer Select Greater Than iselgt rD rA rB Integer Select Equal iseleq rD rA rB equivalent to isel rD rA rB 0 equivalent to isel rD rA rB 1 equivalent to isel rD rA rB 2 A 11 Comprehensive list of simplified mnemonics Table 32 lists simplified mnemonics Note that compiler designers may implement additional simplified mnemoni
42. ee 12 2 1 Instruction and data representation 00 0000 ee eee ee eee 12 2 2 Executable and Linking Format ELF object files 12 2 2 1 VLE information section 0 0000 cece eee 13 2 2 2 VLE identification liliis 14 2 2 3 Relocation typeS 2 1 eee 15 3 INSIFUCTION SOE ici iii 20 Appendix A Simplified mnemonics for VLE instructions 22 A 1 A A a dicum ab A ae 22 A 2 Subtract simplified mnemonics 00000 else 22 A 2 1 Subtractimmediate oooooooococonc ens 22 A 2 2 SUDAC ad nera rerea d tata MSN ALLE P M Ea ers sth 23 A 3 Rotate and shift simplified mnemonics lille 23 A 3 1 Operations on WOFOS oooocccc es 24 A 4 Branch instruction simplified mnemonics oooooooooo o 24 2 50 y UMO438 Contents A 4 1 Key facts about simplified branch mnemonics 26 A 4 2 Eliminating the BO32 and BO16 OperandS o o oooooooo 26 A 4 3 The BI32 and BI16 operand CR Bit and field representations 27 A 4 4 BI32 and BI16 operand instruction encoding o oo o 28 A 5 Simplified mnemonics that incorporate the BO32 and BO16 operands 31 A 5 1 Examples that eliminate the BO32 and BO16 operands 31 A 5 2 Simplified mnemonics that incorporate CR conditions eliminates BO32 and BO16 and replaces BI32 with crS 33 A 5 3 Branch simplified mnemonics that incorporate CR conditions
43. egister se bir se biri Branch to Count Register se bctr se bctrl The BO32 BI32 and BO16 BI16 operands correspond to fields in the instruction opcode as Figure 1 shows for Branch Conditional e bc e bcl and se bc instructions Figure 1 Branch conditional e bc se bc instruction formats e bc e bcl 0 5 6 9 10 11 12 15 16 30 31 01111 0 1 0 0 0 BO32 BI32 BD15 LK se bc 0 4 5 6 7 8 15 1 1 1 1 0 BOt6 Bl16 BD8 Both the BO32 and BO16 operands allow testing whether a CR bit causes a branch to occur based on a true or false condition The BO32 operand provides additional capability that allows branch operations that involve decrementing the CTR and testing for a zero or non zero CTR value The BI32 and BI16 operands identify a CR bit to test whether a comparison is less than or greater than for example The simplified mnemonics avoid the need to memorize the numerical values for BO32 BI32 and BO16 BI16 operands For example e bc 2 0 target is a conditional branch that as a BO32 value of 2 0b10 indicates decrements the CTR then branches if the decremented CTR is not zero The operation specified by BO32 is abbreviated as d for decrement and nz for not zero which replace the c in the original mnemonic so the simplified mnemonic for e bc becomes e bdnz The branch does not depend on a condition in the CR so BI32 can be eliminated reducing the expression to e bdnz target In
44. egisters are not accessible to VLE instructions using the 16 bit formats and not all fields of the condition register CR are used by condition setting or conditional branch instructions when executing from a VLE instruction page In addition immediate fields and displacements differ in size and use due to the more restrictive encodings imposed by VLE instructions Other than the requirement of big endian byte ordering for instruction pages and the additional page attribute to identify whether the instruction page corresponds to a VLE section of code VLE uses the identical storage model interrupts and exceptions timer facilities debug facilities and special purpose registers SPRs defined throughout Book E Executable and Linking Format ELF object files Both VLE and Book E instructions can coexist in the same ELF binary separated into different ELF sections allowing easy identification for defining memory management page tables for run time environments Because implementations supporting VLE use an extension to the existing PowerPC Book E page attributes providing a single additional page attribute to select between VLE and Book E encodings memory pages of VLE and Book E instructions can be freely intermixed Binding of VLE and Book E memory pages to different memory bounds requires separation of VLE and Book E encodings into different ELF sections ky UMO438 Application Binary Interface ABI The VLE encodings also require
45. es both a big endian and a little endian ABI This VLE ABI extension is independent of the endian mode with regards to data however VLE instructions are supported only in big endian mode This chapter should be used in conjunction with the PowerPC e500 Application Binary Interface e500 ABI Except for the sections discussed in this chapter the VLE ABI follows the e500 ABI standard For information on topics not covered in this section including function calling sequence register usage and availability stack frame layout parameter passing and other topics please refer to the e500 ABI Instruction and data representation The VLE extension includes additional operations with an alternate instruction encoding to enable reduced code footprint This alternate encoding set is selected on an instruction page basis A single page attribute bit selects between standard PowerPC Book E instruction encodings and the VLE instructions for the particular page of memory This page attribute is an extension to the existing PowerPC Book E page attributes Pages can be freely intermixed allowing for a mixture of code with both types of encodings Instruction encodings in pages marked as using VLE are either 16 or 32 bits long and are aligned on 16 bit boundaries Therefore all instruction pages marked as VLE must use big endian byte ordering The programmer s model uses the same register set when executing either instruction encoding although certain r
46. esentations of binary floating point arithmetic inexact Loss of accuracy in an arithmetic operation when the rounded result differs from the infinitely precise value with unbounded range L Least significant bit Isb The bit of least value in an address register data element or instruction encoding Little endian A byte ordering method in memory where the address n of a word corresponds to the least significant byte In an addressed memory word the bytes are ordered left to right 3 2 1 0 with 3 being the most significant byte See Big endian M Mnemonic The abbreviated name of an instruction used for coding Modulo A value v which lies outside the range of numbers representable by an n bit wide destination type is replaced by the low order n bits of the two s complement representation of v Most significant bit msb The highest order bit in an address registers data element or instruction encoding N NaN An abbreviation for Not a Number a symbolic entity encoded in floating point format There are two types of NaNs signaling NaNs SNaNs and quiet NaNs QNaNs 46 50 ky UM0438 Glossary Normalization A process by which a floating point value is manipulated such that it can be represented in the format for the appropriate precision single or double precision For a floating point value to be representable in the single or double precision format the leading implied bit must be a 1 Overflow
47. ision 2 or greater to work and does not work on APU 1 revision 1 If a revision breaks backwards compatibility it must be given a new unique identifier A linker may optionally warn when different objects require different revisions because moving the revision up may make the executable no longer work on processors with the older revision In this example the linker could emit a warning like Warning bumping APU 1 revision number to 2 required by b o VLE identification The executable and linking format ELF allows processor specific section header and program header flag attributes to be defined The following section header and program header flag attribute definitions are used to mark ELF sections containing VLE instruction encodings ky UM0438 Application Binary Interface ABI define SHF_PPC_VLE 0x10000000 define PF PPC VLE 0x10000000 section header flag program header flag The SHF PPC VLE flag marks ELF sections containing VLE instructions Similarly the PF PPC VLE flag is used by ELF program headers to mark program sections containing VLE instructions If either the SHF_PPC_VLE flag or the PF PPC VLE flag is set then instructions in those marked sections are interpreted as VLE instructions Book E instructions reside in sections that do not have these flags set ELF sections setting the SHF_PPC_VLE flag that contain VLE instructions should also use the SHF_ALLOC and SHF_EXECINSTR bits a
48. m the third rB The simplified mnemonics in Table 11 use the more common order in which the third operand is subtracted from the second Table 11 Subtract simplified mnemonics Simplified mnemonic Standard mnemonic subc o rD rA rB subfc o rD rB rA 1 rD rB rA is not the standard order for the operands The order of rB and rA is reversed to show the equivalent behavior of the simplified mnemonic A 3 Rotate and shift simplified mnemonics Rotate and shift instructions provide powerful general ways to manipulate register contents but they can be difficult to understand Simplified mnemonics are provided for the following operations e Extract Select a field of n bits starting at bit position b in the source register left or right justify this field in the target register clear all other bits of the target register e Insert Select a left or right justified field of n bits in the source register insert this field starting at bit position b of the target register leave other bits of the target register unchanged e Rotate Rotate the contents of a register right or left n bits without masking e Shift Shift the contents of a register right or left n bits clearing vacated bits logical shift e Clear Clear the leftmost or rightmost n bits of a register e Clear left and shift left Clear the leftmost b bits of a register then shift the register left by n bits This operation can be used to scale a known non negative
49. monics continued Simplified mnemonic e_bun crS target Mnemonic e bc 1 B132 target Instruction Branch if unordered e bc without LR updating se bun target se bc 1 B116 target Branch if unordered se bc e bunl crS target e bcl 1 B132 target Branch if unordered e bcl with LR updating e clrisiwi rA rS b n nx b lt 31 e rlwinm rA rS n b n 31 n Clear left and shift left word immediate e clriwi rA rS n n 32 e rlwinm rA rS 0 n 31 Clear left word immediate e_clrrwi rA rS n n lt 32 e rlwinm rA rS 0 0 31 n Clear right word immediate cmplw crD rA rB cmpl crD 0 rA rB Compare logical word e cmplwi crD rA UIMM e cmpli crD rA UIMM Compare logical word immediate e cmplwi cr0 rA UIMM e_cmpl16i rA UIMM Compare logical word immediate cmpw crD rA rB cmp crD 0 rA rB Compare word e_cmpwi crD rA SIMM e_cmpi crD rA SIMM Compare word immediate e_cmpwi cr0 rA SIMM e_cmp16i rA SIMM Compare word immediate e_extlwi rA rS n b n gt 0 e rlwinm rA rS b 0 n 1 Extract and left justify word immediate e extrwi rA rS n b n 0 e rlwinm rA rS b n 32 n 31 Extract and right justify word immediate e inslwi rA rS n b n gt 0 e rlwimi rA rS 32 b b b n 1 Insert from left word immediate e insrwi rA rS n b n gt 0 e rlwimi rA rS 32 b n b b Insert fr
50. mposed of two parts As Figure 2 shows BI32 0 1 indicates the CR field and BI32 2 3 represents the condition to test The 2 bit BI16 operand only has one part Bl16 0 1 represents the condition within CRO to test Figure 2 BI32 and BI16 fields BI32 Opcode Field 0 1 2 3 TTT Bl16 Opcode Field 0 1 LA L 4 BI32 0 1 specifies CR field CRO CR3 BI32 2 3 and BI16 0 1 specifies one of the 4 bits in a CR field LT GT EQ SO Simplified mnemonics based on Specified by a Incorporated into the CR conditions but not CTR values separate reduced simplified mnemonic branch if true BO32 1 or BI32 operand crS BO16 1 branch if false BO32 0 or BO16 0 Standard branch mnemonics and The BI32 operand specifies the entire 4 bit field simplified mnemonics based on and the BI16 operand specifies a 2 bit field If CTR values CRO is used the bit can be identified by LT GT EQ or SO For BI32 if CR1 CR3 are used the form 4 crS LTIGTIEQISO can be used Integer record form instructions update CRO and floating point record form instructions update CR1 as described in Table 15 28 50 Ti UMO438 Simplified mnemonics for VLE instructions Specifying a CR Bit Note that the AIM version of the PowerPC architecture numbers CR bits 0 31 and Book E numbers them 32 63 However no adj
51. n APUinfo 0 4 0x0000000C 12 bytes 3 words of APU information 8 0x00000002 NOTE type 2 12 0x41505569 ASCII for APUi 16 0x6e666f00 ASCII for nfo o 20 0x00010001 APU 1 revision 1 24 0x01040001 VLE revision 1 28 0x00040001 APU 4 revision 1 13 50 Application Binary Interface ABI UMO438 2 2 2 14 50 Example Object file b o 0 0x00000008 8 bytes in APUinfo 0 4 0x00000008 8 bytes 2 words of APU information 8 0x00000002 NOTE type 2 12 0x41505569 ASCII for APUi 16 0x6e666f00 ASCII for nfo o 20 0x00010002 APU 1 revision 2 24 0x00040001 APU 4 revision 1 Linkers merge all PPC EMB apuinfo sections in individual object files into one with merging of per APU information For example after linking file a o and b o the merged PPC EMB apuinfo is as shown in example below Example PPC EMB apuinfo 0 0x00000008 8 bytes in APUinfo 0 4 0x0000000C 12 bytes 3 words of APU information 8 0x00000002 NOTE type 2 12 0x41505569 ASCII for APUi 16 0x6e666f00 ASCII for nfo 0o 20 0x00010002 APU 1 revision 2 24 0x01040001 VLE revision 1 28 0x00040001 APU 4 revision 1 Note that it is assumed that a later revision of any APU or extension is compatible with an earlier one but not vice versa Thus the resultant PPC EMB apuinfo section requires APU 1 rev
52. n Switzerland United Kingdom United States of America www st com q 50 50
53. n by John L Hennessy and David A Patterson e Computer Organization and Design The Hardware Software Interface Second Edition David A Patterson and John L Hennessy Conventions This document uses the following notational conventions cleared set When a bit takes the value zero it is said to be cleared when it takes a value of one it is said to be set mnemonics Instruction mnemonics are shown in lowercase bold italics Italics indicate variable command parameters for example bcctrx 8 50 Book titles in text are set in italics Internal signals are set in italics for example qual BG 0x0 Prefix to denote hexadecimal number ObO Prefix to denote binary number rA rB Instruction syntax used to identify a source GPR rD Instruction syntax used to identify a destination GPR REG FIELD Abbreviations for registers are shown in uppercase text Specific bits fields or ranges appear in brackets For example MSR LE refers to the little endian mode enable bit in the machine state register ky UMO438 Preface x In some contexts such as signal encodings an unitalicized x indicates a don t care Xx An italicized x indicates an alphanumeric variable n An italicized n indicates an numeric variable a NOT logical operator amp AND logical operator OR logical operator Terminology conventions Table 1 lists certain terms used in this manual that differ from the architecture terminology conventions
54. nch if not less than e bc without LR updating se bnl target se bc 0 BI16 target Branch if not less than se bc e bnll crS target e bcl 0 BI32 target Branch if not less than e bcl with LR updating e bns crS target e bc 0 BI329 target Branch if not summary overflow e bc without LR updating se bns target e bnsl crS target se bc 0 B116 target e bcl 0 B132 target Branch if not summary overflow se bc Branch if not summary overflow e bcl with LR updating e bnu crS target e bc 0 B132 target Branch if not unordered e bc without LR updating se bnu target se bc 0 B116 target Branch if not unordered se bc e bnul crS target e bcl 0 B132 target Branch if not unordered e bcl with LR updating e bso crS target e bc 1 B132 target Branch if summary overflow e bc without LR updating se bso target se bso 1 BI16 target Branch if summary overflow se bc e bsol crS target e bcl 1 B132 target Branch if summary overflow e bcl with LR updating e bt BI32 target e bc 1 BI32 target Branch if condition true e bc without LR update se bt Bl16 target e btl BI32 target 42 50 se bc 1 Bl16 target e bcl 1 BI32 target Branch if condition true se bc Branch if condition true e bcl with LR update ky UM0438 Simplified mnemonics for VLE instructions Table 32 Simplified mne
55. nics for VLE instructions provide a consistent assembly language interface with the PowerPC architecture Many simplified mnemonics were originally defined in the PowerPC architecture documentation Some assemblers created their own and others have been added to support extensions to the instruction set for example AltiVec instructions and Book E auxiliary processing units APUs Simplified mnemonics for new architecturally defined and new implementation specific special purpose registers SPRs are described here very generally Subtract simplified mnemonics This section describes simplified mnemonics for subtract instructions Subtract immediate The effect of a subtract immediate instruction can be achieved by negating the immediate operand of the add immediate instructions e add16i e add2i e add2is and e addi Simplified mnemonics include this negation making the intent of the computation clearer These are listed in Table 10 UMO438 Simplified mnemonics for VLE instructions Table 10 Subtract immediate simplified mnemonics Simplified mnemonic Standard mnemonic e_sub16i rD rA value e_add16i rD rA value e_sub2i rA value e_add2i rA value e sub2is rA value e add2is rA value e subi rD rA value e addi rD rA value e subic rD rA value e addic rD rA value e subic rD rA value e addic rD rA value A 2 2 Subtract Subtract from instructions subtract the second operand rA fro
56. ntry r addend value is calculated minus the appropriate base for the symbol s section SDA BASE for a symbol in sdata or sbss SDA2 BASE fora symbol in PPC EMB sdata2 or PPC EMB sbss2 or 0 for a symbol in PPC EMB sdata0 or PPC EMB sbss0 The R_PPC_VLE_SDA21 entry describes applying the calculated 21 bit value to the destination word that uses either the low21 relocation field or the split20 relocation field See Table 6 1 Note that if the opcode is changed 27 bits are changed instead of 21 Note The relocations in Table 9 are not for load and store instructions such as e Iwz and e_stw which should use the EABI relocation R_PPC_EMB_SDA21 These relocations as written here only start with an e add16i A linker might convert the instruction to an e li Although other relocations do not specify the instructions they apply to it may be useful to know that these relocations can apply only to one instruction 4 19 50 Instruction set UMO438 3 Note 20 50 Instruction set This section provides an overview of the VLE instruction set architecture For details on each instruction including assembly mnemonic and operands refer to the VLE section of the EREF The VLE extension allows PowerPC Book E implementations to support more efficient binary representations of applications for the embedded processor spaces where code density plays a major role in affecting overall system cost and to a somewhat lesser extent
57. om right word immediate n 1 iseleq rD rA rB isel rD rA rB 2 Integer Select Equal iselgt rD rA rB isel rD rA rB 1 Integer Select Greater Than isellt rD rA rB isel rD rA rB 0 Integer Select Less Than e_la rD d rA e_add16i rD rA d Load address e_nop e_ori 0 0 0 No op se_nop se_or 0 0 No op not rA rS nor rA rS rS NOT Complement register e_rotlwi rA rS n e_rlwinm rA rS n 0 31 Rotate left word immediate e_rotrwi rA rS n e_rlwinm rA rS 32 n 0 31 Rotate right word immediate e slwi rA rS n n lt 32 e rlwinm rA rS n 0 31 n Shift left word immediate e srwi rA rS n n 32 e rlwinm rA rS 32 n n 31 Shift right word immediate sub rD rA rB subf rD rB rA Subtract from sub rD rA rB subf rD rB rA Subtract from subo rD rA rB subf rD rB rA Subtract from subo rD rA rB subf rD rB rA Subtract from subc rD rA rB subfc rD rB rA Subtract from carrying subc rD rA rB Y subfc rD rB rA Subtract from carrying Simplified mnemonics for VLE instructions UM0438 Table 32 Simplified mnemonics continued Simplified mnemonic subco rD rA rB Mnemonic subfco rD rB rA Instruction Subtract from carrying subco rD rA rB subfco rD rB rA Subtract from carrying e_sub16i rD rA value e_add16i rD rA value Subtract immediate e sub2i rA value e add2i rA value
58. onal Book E The description of each instruction is contained in the VLE section of the EREF and includes the mnemonic and a formatted list of operands VLE instructions have either exact or similar semantics to Book E instructions Where the semantics side effects and binary encodings are identical the Book E mnemonics and formats are used Where the semantics are similar but the binary encodings differ the Book E mnemonic is generally preceded with an e To distinguish similar instructions available in both 16 and 32 bit formats under VLE and standard Book E instructions VLE instructions encoded with 16 bits have an se_ prefix VLE instructions encoded with 32 bits that have different binary encodings or semantics than the equivalent Book E instruction have an e_ prefix Some examples are the following stw RS D RA Standard Book E instruction e stw RS D RA 32 bit VLE instruction se stw RZ SD4 RX 16 bit VLE instruction For detailed functional descriptions of each VLE instruction along with the assembly mnemonic and operands refer to the VLE section of the EREF 21 50 Simplified mnemonics for VLE instructions UMO438 Appendix A Simplified mnemonics for VLE instructions A 1 A 2 A 2 1 22 50 This appendix describes simplified mnemonics for easier coding of assembly language programs Simplified mnemonics are defined for the most frequently used forms of branch conditional compare trap rot
59. red e bnu se bnu e bnul Instructions using the mnemonics in Table 24 indicate the condition bit but not the CR field If no field is specified CRO is used For 32 bit instruction forms denoted with the e prefix the CR field symbols defined in Table 17 cr0 cr3 are used as shown in examples of Section A 5 3 Branch simplified mnemonics that incorporate CR conditions examples below Note that the 16 bit instruction forms denoted with the se prefix must use CRO ky UMO438 Simplified mnemonics for VLE instructions A 5 3 Branch simplified mnemonics that incorporate CR conditions examples The following examples use the simplified mnemonics shown in Table 24 1 Branch if CRO reflects not equal condition e_bne target equivalent to e bc 0 2 target se_bne target equivalent to se_bc 0 2 target 2 Same as 1 but condition is in CR3 e bne cr3 arget equivalent to e bc 0 14 target 3 Branch if CR2 specifies greater than condition setting the LR This is a form of conditional call e_bgtl cr2 target equivalent to e_bcl 1 9 target A 5 4 Branch simplified mnemonics that incorporate CR conditions listings Table 25 shows simplified branch mnemonics and syntax for e bc and se bc without LR updating Table 25 Simplified mnemonics for e bc and se bc without comparison conditions or LR updating Branch semantics Branch if less than e bc e bc 1 B132 target Simplified mnemonic e blt crS target se bc
60. rt of the simplified mnemonic Note that the default is CRO if no crS is specified CRO is used Table 23 Branch instructions and simplified mnemonics that incorporate CR conditions Instruction Standard Syntax Simplified Syntax mnemonic mnemonic Branch e_b e_bl t t_add se_b se_bl TE Branch Conditional e bc e bcl BO32 BI32 target addr e bx e bxl ers target_addr se bc BO16 BI16 target addr se bx target addr Branch to Link Register se blr se_blrl Branch to Count Register se bctr se bctrl 1 xstands for one of the symbols in Table 22 where applicable 2 crS can be a numeric value or an expression as shown in Table 17 34 50 Table 24 shows the simplified branch mnemonics incorporating conditions Table24 Simplified mnemonics with comparison conditions LR Update Not Enabled LR Update Enabled Branch semantics e bc se bc e bcl Branch if less than e bit se bit e biti Branch if less than or equal e ble se ble e blel Branch if equal e beq se beq e begl Branch if greater than or equal e bge se bge e bgel Branch if greater than e bgt se bgt e bgtl Branch if not less than e bnl se bnl e bnll Branch if not equal e bne se bne e bnel Branch if not greater than e bng se bng e bngl Branch if summary overflow e bso se bso e bsol Branch if not summary overflow e bns se bns e bnsl Branch if unordered e bun se bun e bunl Branch if not unorde
61. s necessary Setting the SHF_PPC_VLE bit does not automatically imply a section that is marked as allocate SHF ALLOC or executable SHF EXECINSTR The linker keeps sections marked as VLE SHF PPC VLE in separate output sections that do not contain Book E instructions Similarly ELF program headers setting the PF PPC VLE flag should use the PF X PF W and PF R flags to indicate executable writable or readable attributes It is considered an error for a program header with PF_PPC_VLE set to contain sections that do not have SHF PPC VLE set A program loader or debugger can then scan the section headers or program headers to detect VLE sections in case anything special is required for section processing or downloading 2 2 3 Relocation types Relocation entries describe how to alter the instruction relocation fields once symbols or labels are defined at link time The VLE instruction set requires relocation types beyond those described in the PowerPC e500 Application Binary Interface e500 ABI Table 5 shows additional relocation fields used by the VLE instruction set Table 5 VLE relocation fields Relocation field name 0 1 1 3 low21 o 1 1 low21 0 5 6 1 1 1 1 1 2 2 3 split20 0 1 5 6 7 0 1 1 011100 mE Split204 s 0 Split209 5 Split209 19 0 1 1 1 1 2 2 3 spliti6a o 1 5 6 0 1 1 split16a9 4 spliti6as 5 0 5 6 14 2 2 3 split16d 0 1 0 1 1 split16do 4 gt split 6d5
62. ses the BO16 and BI16 operands For example the 32 bit conditional branch e bc 1 2 target can be expressed using a 16 bit instruction format se bc 1 2 target In simplified mnemonic form this becomes se bt eq target The BO16 operand only allows testing a true or false condition unlike the BO32 operand that also allows decrementing the CTR The BI16 operand allows testing of only CRO unlike the BI32 operand which allows testing CRO CR3 Key facts about simplified branch mnemonics The following key points are helpful in understanding how to use simplified branch mnemonics e All simplified branch mnemonics eliminate the BO32 and BO16 operands so if any operand is present in a branch simplified mnemonic it is the BI32 or BI16 operand or a reduced form of it e Ifthe CR is not involved in the branch the BI32 and BI16 operands can be deleted e If the CR is involved in the branch the BI32 and BI16 operands can be treated in the following ways tcan be specified as a numeric value just as it is in the architecturally defined instruction or it can be indicated with an easier to remember formula 4 crn test bit symbol where n indicates the CR field number For BI16 operands only CRO is allowed for BI32 CRO CR3 is allowed The condition of the test bit eq It gt and so can be incorporated into the mnemonic leaving the need for an operand that defines only the CR field If the test bit is in CRO no operand
63. shifting must all be the same either all zeros or all ones that is sign extended displacement For relocation types in which the name contains 15 the upper 17 bits of the computed value before shifting must all be the same For relocation types in which the name contains 24 the upper 7 bits of the computed value before shifting must all be the same For relocation types whose names contain 8 15 or 24 the low 1 bit of the computed value before shifting must be zero half word boundary hi value and lo value denote the 16 msbs and Isbs of the indicated value That is lo x x amp OXFFFF and hi x x gt gt 16 amp OxFFFF The high adjusted value ha value compensates for lo being treated as a signed number ha x x gt gt 16 x 4 0x8000 1 0 8 OxFFFF SDA BASE is a symbol defined by the link editor whose value in shared objects is the same as GLOBAL OFFSET TABLE and in executable programs is an address within the small data area Similarly SDA2 BASE is a symbol defined by the link editor whose value in executable programs is an address within the small data 2 area Note that the relocation types in Table 8 apply only to VLE sections Sections containing Book E instructions should use the PowerPC e500 Application Binary Interface Table 8 VLE relocation types Name Value Field Calculation R PPC VLE REL8 216 bdh8 S A P gt gt 1 R_PPC_VLE_REL15 217 bdh15 S A P gt gt 1 R_PPC_V
64. t depend on the CTR value and can be alternately coded by incorporating the condition specified by BI32 or BI16 as described in Section A 5 2 Simplified mnemonics that incorporate CR conditions eliminates BO32 and BO16 and replaces BI32 with crS The value in the BI32 or BI16 operand selects CRn 0 the LT bit The value in the BI32 or BI16 operand selects CRn 1 the GT bit The value in the BI32 or BI16 operand selects CRn 3 the SO bit 44 50 4 UMO438 Glossary Appendix B Glossary The glossary contains an alphabetical list of terms phrases and abbreviations used in this book Some of the terms and definitions included in the glossary are reprinted from IEEE Std 754 1985 IEEE Standard for Binary Floating Point Arithmetic copyright 1985 by the Institute of Electrical and Electronics Engineers Inc with the permission of the IEEE Note that some terms are defined in the context of how they are used in this book Architecture A detailed specification of requirements for a processor or computer system It does not specify details of how the processor or computer system must be implemented instead it provides a template for a family of compatible implementations Biased exponent An exponent whose range of values is shifted by a constant bias Typically a bias is provided to allow a range of positive values to express a range that includes both positive and negative values Big endian A byte ordering method
65. t register No Op nop Many instructions can be coded in such a way that effectively no operation is performed Additional mnemonics are provided for the preferred forms of no op If an implementation performs any type of run time optimization related to no ops the preferred forms are the following e_nop equivalent to e_ori 0 0 0 se_nop equivalent to se_or 0 0 Load Address la The la mnemonic permits computing the value of a base displacement operand using the e_add16i instruction that normally requires a separate register and immediate operands e la rD d rA equivalent to e add16i rD rA d The e la mnemonic is useful for obtaining the address of a variable specified by name allowing the assembler to supply the base register number and compute the displacement If the variable V is located at offset dV bytes from the address in rV and the assembler is directed to use rV as a base for references to the data structure containing V the following line causes the address of V to be loaded into rD e larD V equivalent to e add16i rD rV dV Move Register mr Several instructions can be coded to copy the contents of one register to another A simplified mnemonic is provided to signify that no computation is being performed but merely that data is being moved from one register to another The following instruction copies the contents of rS into rA This mnemonic can be coded with a dot suffix to cause the Rc bit to be set in th
66. termixed Book E floating point registers are not accessible to VLE instructions Book E GPRs and SPRs are used by VLE instructions with the following limitations e VLE instructions using the 16 bit formats are limited to addressing GPRO GPR7 and GPR24 GPR31 in most instructions Move instructions are provided to transfer register contents between these registers and GPR8 GPR23 e VLE instructions using the 16 bit formats are limited to addressing CRO e VLE instructions using the 32 bit formats are limited to addressing CRO CR3 VLE instruction encodings generally differ from Book E instructions except that most Book E instructions falling within Book E primary opcode 31 are encoded identically in 32 bit VLE instructions Also they have identical semantics unless they affect or access a resource not supported by the VLE extension Primary opcode 4 is available to support additional instructions using identical encodings for both Book E and VLE Therefore an implementation of VLE can include additional APUs such as the cache line locking APU vector or scalar single precision floating point APU and SPE extension and use the exact encodings ky UM0438 Instruction set The VLE extension does not currently fully encompass 64 bit operations although the addition of such operations in a future version is envisioned For future compatibility and to avoid confusion with Book E register bit numbering remains the same as in traditi
67. test a condition require a corresponding CR bit as the first operand as the examples in Section A 5 1 Examples that eliminate the BO32 and BO16 operands below illustrate The symbols in Table 17 can be used in place of a numeric value Examples that eliminate the BO32 and BO16 operands The simplified mnemonics in Table 18 are used in the following examples 31 50 Simplified mnemonics for VLE instructions UM0438 Table 20 1 Decrement CTR and branch if it is still nonzero closure of a loop controlled by a count loaded into CTR note that no CR bits are tested e_bdnz target equivalent to Because this instruction does not test a CR bit the simplified mnemonic should specify only a target operand Specifying a CR for example e bdnz 0 target or e bdnz crO target may be considered a programming error Subsequent examples test conditions 2 Branchif condition in CRO is equal e bt eq target Other equivalents include e bt 2 target or the unlikely e bt 4 cr0 eq farget 3 Same as 2 but equal condition is in CR3 e_bt 4 cr3 eq target equivalent to e_be 2 0 target equivalent to e_be 1 2 target e_be 1 14 target e bt 14 target would also work 4 Branch if bit 47 of CR is false bf 15 target bf 4 cr3 so target would also work 5 Same as 4 but set the link register This is a form of conditional call bfl 15 target equivalent to bel 4 15 target Table 20 lists simplified mnemonics and syntax for e bc
68. ue or 1 branch if condition false do not depend on the CTR value and alternately can be coded by incorporating the condition specified by the BI32 or BI16 fields See Section A 5 2 Simplified mnemonics that incorporate CH conditions eliminates BO32 and BO16 and replaces BI32 with crS 2 Simplified mnemonics for branch instructions that do not test CR bits BO32 2 or 3 should specify only a target Otherwise a programming error may occur 3 Notice that these instructions do not use the branch in condition true or false operations so simplified mnemonics for these should not specify a BI32 operand A 4 3 The BI32 and BI16 operand CR Bit and field representations With standard branch mnemonics the BI32 and BI16 operands are used to test a CR bit as shown in the example in Section A 4 Branch instruction simplified mnemonics With simplified mnemonics the BI32 and BI16 operands are handled differently depending on whether the simplified mnemonic incorporates a CR condition to test as follows e Some branch simplified mnemonics incorporate only the BO32 or BO16 operand These simplified mnemonics can use the architecturally defined BI32 or BI16 operand to specify the CR bit as follows The BI32 or BI16 operands can be presented exactly as it is with standard mnemonics as a decimal number 0 15 for the BI32 operand and 0 3 for the BI16 operand Symbols can be used to replace the decimal operand as shown in the e
69. ustment is necessary to the code in Book E devices 32 is automatically added to the BI32 and BI16 values as shown in Table 15 and Table 16 Table 15 CRO and CR1 fields as updated by integer and floating point instructions CR Bits BI32 Bl16 CRn Bit Description AIM Book E 0 1 2 3 0 1 CRO O 0 32 00 00 00 Negative LT Set when the result is negative CRO 1 1 33 00 014 01 Positive GT Set when the result is positive and not zero CRO 2 2 34 00 10 10 Zero EQ Set when the result is zero CRO 3 3 35 00 11 11 Summary overflow SO Copy of XER SO at the instruction s completion CR1 O 14 36 01 00 Copy of FPSCR FX at the instruction s completion CR1 1 15 37 01 101 Copy of FPSCR FEX at the instruction s completion CR1 2 6 38 01 10 Copy of FPSCR VX at the instruction s completion CR1 3 7 39 01 11 Copy of FPSCR OX at the instruction s completion Some simplified mnemonics incorporate only the BO32 or BO16 fields as described Section A 4 2 Eliminating the BO32 and BO16 operands If one of these simplified mnemonics is used and the CR must be accessed the BI32 or BI16 operand can be specified either as a numeric value or by using the symbols in Table 16 Compare word instructions described in Section A 6 Compare word simplified mnemonics floating point compare instructions move to CR instructions and others can also modify CR fields so CRO and CR1 may hold values that do not adhere to
70. ve branch displacements to half word boundaries bdh8 8 bit field occupying bits 8 15 of a half word This field is used by a 16 bit branch instruction Note Relocation entry types applied to VLE sections use half word alignment boundaries because the VLE instruction architecture mixes 16 and 32 bit encodings within a VLE section Book E instruction encodings in non VLE sections use e500 ABI alignment specifications Calculations in Table 8 assume the actions are transforming a relocatable file into either an executable or a shared object file Conceptually the link editor merges one or more relocatable files to form the output It determines how to combine and locate the input files updates the symbol values and then performs relocations Relocations applied to executable or shared object files are similar and accomplish the same result The notations used in Table 8 are described in Table 7 Table 7 Notation conventions Field Descriptions A Represents the addend used to compute the value of the relocatable field P Represents the place section offset or address of the storage unit being relocated computed using r_offset S Represents the value of the symbol whose index resides in the relocation entry 16 50 y UM0438 Application Binary Interface ABI Table 7 Notation conventions continued Field Descriptions Represents the offset from the appropriate base _SDA_BASE_ SDA2 BASE or 0 to
71. xample in Section A 4 Branch instruction simplified mnemonics where e bt 4 cr3 eq target could be used instead of e bt 14 target This is described in Section Specifying a CR Bit The simplified mnemonics in Section A 5 Simplified mnemonics that incorporate the BO32 and BO16 operands use one of these two methods to specify a CR bit e Additional simplified mnemonics incorporate CR conditions that would otherwise be specified by the BI32 or BI16 operand so the BI32 or BI16 operand is replaced by the crS operand to specify the CR field See Section A 4 4 BI32 and BI16 operand instruction encoding 27 50 Simplified mnemonics for VLE instructions UMO438 These mnemonics are described in Section A 5 2 Simplified mnemonics that incorporate CR conditions eliminates BO32 and BO16 and replaces BI32 with crS A 4 4 BI32 and BI16 operand instruction encoding The entire 4 bit BI32 and 2 bit BI16 fields shown in Figure 2 represent the bit number for the CR bit to be tested For standard branch mnemonics and for branch simplified mnemonics that do not incorporate a CR condition the BI32 operand provides all 4 bits and the BI16 operand provides all 2 bits For simplified branch mnemonics described in Section A 5 2 Simplified mnemonics that incorporate CR conditions eliminates BO32 and BO16 and replaces BI32 with crS the BI32 or BI16 operand is replaced by a crS operand To understand this it is useful to view the BI32 operand as co

Variable-Length Encoding (VLE) extension

Contents

Download Pdf Manuals

Related Search

Related Contents