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1. 7e Information 2 3 4 96 zb 961 x Figure 6 12 The EDID Decoder Output of the HDMI TX Demonstration 82 Terasic Cyclone V GX Starter Kit User Manual www terasic com www teresic com 6 4 Transceiver HSMC Loopback test The XCVR HSMC loopback demonstration is a project to test XCVR HSMC Loopback function The system generate data pattern and transport data through the xcvr channel Meanwhile the system receives the data through the loopback daughter card and checks it Altera IP data pattern generator and data pattern checker are responsible for generating and checking the data pattern The Nios II CPU checks the test result The test result is shown through LEDGO LEDG3 and also displayed in the nios2 treminal period If the loopback test function not working the program will terminal and the LEDs will all turn off B Design Tools e Quartus II 13 0 e Nios II Eclipse 13 0 B Demonstration Source Code e Quartus Project directory CSG_XCVR_LOOPBACK e Nios II Eclipse 5 XCVR LOOPBACKNSoftware Nios II Project Compilation Before you attempt to compile the reference design under Nios II Eclipse make sure the project is cleaned first by clicking Clean from the Project menu of Nios II Eclipse B Demonstration Batch File Demo Batch File Folder C5G HSMC XCVR LOOPBACK TESTWdemo batch The demo batch file in
2. L S TDMS_TXO 3 HDMI TX DE TDMS TX Cyclone y TDMs r2 GX TX INT O 2 SDA I2C_SCL Figure 3 20 Connections between the Cyclone V GX FPGA and HDMI Transmitter Chip Table 3 13 HDMI Pin Assignments Schematic Signal Names and Functions Signal Name Pin Number Video Data bus Video Data bus Video Data bus 89V PINW25 Video Data bus 89V PNW26 Video Data bus Video Data bus Video Data bus 89V PINUA Video Data bus Video Data bus Video Data bus Video Data bus 89V PINR23 Video Data bus 89V 25 Video Data bus 89V 22 Video Data bus 89V PNP2 42 asic Terasic Cyclone V GX Starter Kit User Manual www terasic com www HDMI TX D14 Video Data bus 3 3 V PIN_N25 HDMI_TX_D15 Video Data bus 3 3 V PIN_P26 HDMI_TX_D16 Video Data bus 3 3 V PIN_P21 HDMI_TX_D17 Video Data bus 3 3 V PIN_R24 HDMI_TX_D18 Video Data bus 3 3 V PIN_R26 HDMI_TX_D19 Video Data bus 3 3 V PIN_AB26 HDMI_TX_D20 Video Data bus 3 3 V PIN AA24 HDMI TX 21 Video Data bus 3 3 V PIN AB25 HDMI TX D22 Video Data bus 3 3 V PIN_AC25 HDMI_TX_D23 Video Data bus 3 3 V PIN_AD25 TX CLK Video Clock 3 3 V PIN_AJ28 HDMI TX DE Data Enable Signal for Digital Video 3 3 V PIN Y26 HDMI TX HS Vertical Synchronization 3 3 V PIN U26 HDMI TX VS Horizontal Synchronization 3 3 V PIN U25 HDMI TX INT Interrupt Signal 1 2 V PIN T12 I2C_SCL 12 Clock
3. 18 2 19 2 0 HSMG m 20 2 10 OVERALL STRUCTURE OF THE C5G CONTROL PANEL nennen nennen innen nnns 21 CHAPTER3 USING THE STARTER KIT tasa stats 23 3 1 CONFIGURATION STATUS AND SETUP u a a e CHER bee AER VERE EN EN ES 23 3 2 GENERAL USER INPUT OUTPUT 5 e certet reb anan 27 CLOCK CIR CUNT MER E 33 3 4 RS 232 SERIAL PORT TO USB INTERFACE scesccecssecesscecsseceseeecaeceeeecsaceeeneecsaecsneecsaceeeaeeceaeceaeecaceseaeecaeeeeneesas 35 3 5 SRAM STATIC RANDOM ACCESS MEMORY 36 3 6 LPDDR2 MEMORY A 37 3 7 MICROSD CARD ES 40 2 9 HDMETX INTERFACE 42 3 9 AUDIO INTERFACE 43 3 10 HSMC HIGH SPEED MEZZANINE CARD 4 entente nnne tenens 44 3 11 USING THE 2X20 GPIO EXPANSION HEADER n nsn 49 4 SYSTEM BUILDER 56 m LANTRODUCTION 56 ZU GENERAL DESIGN FLOW 56 4 3 USING CSG SYSTEM BUILDER 57 1 Terasic Cyclone V GX Starter Kit User M
4. B Demonstration Setup Connect a USB cable between your computer and the CSG board Power on your C5G board you find an unrecognized USB Serial Port as shown in Figure 6 4 you should install the UART to USB driver before you run the demonstration g niubility PC Computer Disk drives Display adapters W DVD CD ROM drives oS Human Interface Devices cg IDE ATA ATAPI controllers lt gt Keyboards n Mice and other pointing devices Monitors Network adapters l Other devices 7 Ports COM amp LPT YY Communications Port COMI YY Printer Port LPT1 Processors Sound video and game controllers JE System devices Universal Serial Bus controllers Figure 6 4 Unrecognized USB Serial Port on PC To install UART_TO_USB driver on your computer please select the USB Serial Port to update the driver software The driver file is in the XXX CDM v2 08 28 Certified directory e Open the Device Manager to ensure which common port is assigned to the uart to usb port as shown in Figure 6 5 The common number 9 is assigned on this computer www terasic com Open the putty software and setup the parameter as shown in Figure 6 5 and click open button to open the terminal PuTTY Configuration File Action View Help 510 2 RG 4 gy niubility PC gt 4M Computer gt Disk drives gt 188 Display adapters gt 4 3 DVD CD ROM drives gt qq IDE ATA ATAPI cont
5. Store Audio Data Nios Program LED KEY ISW 2C 50MHz j2euuooJaju Figure 6 15 Block diagram of the audio recorder and player Demonstration File Locations Hardware Project directory CSG_Audio Bit stream used C5G Audio sof Software Project directory CSG_Audio software Demonstration Setup and Instructions Connect an Audio Source to the LINE IN port of the C5G board Connect a Microphone to MIC IN port on the C5G board Connect a speaker or headset to LINE OUT port on the C5G board Load the bit stream into FPGA note 1 Load the Software Execution File into FPGA note 1 Configure audio with the Slide switches as shown in Table 6 3 and Table 6 4 Press KEY3 on the C5G board to start stop audio recording note 2 Press KEY2 on the C5G board to start stop audio playing note 3 Table 6 3 Slide switches usage for audio source Slide Switches 0 DOWN Position 1 UP Position SWO Audio is from MIC Audio is from LINE IN SW1 Disable MIC Boost Enable MIC Boost 86 Terasic Cyclone V GX Starter Kit User Manual www terasic com Table 6 4 Slide switch setting for sample rate switching for audio recorder and player SW4 SW3 SW2 0 DOWN 0 DOWN 0 DOWN Sample Rate 1 UP 1 UP 1 UP 0 0 0 96K 0 0 1 48K 0 1 0 44 1K 0 1 1 32K 1 0 0 8K Unlisted combination 96K 1 Execute C5G_Audio demo_batch C5G_Audio bat will download sof and
6. CLOCK 125 p PINUI2 0 CLOCK 125 n PIN Vi2 CLOCK 50 B5B PINRO x REFCLK pO 125 0 MHz 1 5 34 Terasic Cyclone V GX Starter Kit User Manual www terasic com Table3 7 Programmable oscillator control pin Signal Name I O standard Pin Assignments and Descriptions Programmable Schematic Cyclone V GX EY 4 4 Standard N Description Oscillator Signal Name Pin Number SCL 25V PNB i U20 515338 oe I2C SDA 2 5 V PIN G11 connected with 15338 3 4 RS 232 Serial Port to USB interface The RS 232 is designed to perform communication between board and PC allowing a transmission speed of up to 3Mbps This interface wouldn t support HW flow control signals The physical interface is done using UART USB on board bridge from a FT232R chip and connects to the host using a USB Type B connector For detailed information on how to use the transceiver please refer to the datasheet which is available on the manufacturer s website or under the Datasheets 232 folder on the Kit System CD Figure 3 14 shows the related schematics and Table 3 8 lists the RS 232 pin assignments signal names and functions Table 3 9 lists the RS 232 status LEDs US JNO 8 A YANI USBDP j Cyclone V 1 TXD USBDM UART TX USB B TYPE Figure 3 14 Connections between the Cyclone V GX FPGA and FT232R Chip Table 3 8 RS 232 Pin Assignme
7. 1 2 V HSUL PIN AF11 PIN AE18 PIN AE20 PIN AE24 PIN N10 P10 PIN 14 PIN AE13 PIN R11 PIN T11 PIN_AE11 Micro SD Card Socket Figure 3 18 Connection between the SD Card Socket and Cyclone V GX FPGA 40 Terasic Cyclone V GX Starter Kit User Manual www terasic com L Figure 3 19 Micro SD Card Table 3 12 SD Card Pin Assignments Schematic Signal Names and Functions Sch t Cyclone V GX A Description VO Standard Signal Pin Number SD_CLK Serial Clock PIN_AB6 SD_CMD Command Response SD_DAT1 Serial Data 1 SD_DAT2 Serial Data 2 SD_DAT3 Serial Data 3 SD_DAT0 Serial Data 0 41 Terasic Cyclone V GX Starter Kit User Manual www terasic com 3 8 HDMI TX Interface The development board provides High Performance HDMI Transmitter via the Analog Devices ADV7513 which incorporates HDMI v1 4 features including 3D video support and 165 MHz supports all video formats up to 1080p and UXGA The ADV7513 is controlled via a serial 12 bus interface which is connected to pins on the Cyclone V GX FPGA A schematic diagram of the audio circuitry is shown in Figure 3 20 Detailed information on using the ADV7513 HDMI TX is available on the manufacturer s website or under the Datasheets HDMI folder on the Kit System CD Table 3 13 lists the HDMI Interface pin assignments and signal names relative to the Cyclone V GX device TX D 23 0 HDMI TX CLK HDMI TX HS
8. Cyclone GX 5CGXFC5C6F27C7N Device e 77K Programmable Logic Elements e 4884 Kbits embedded memory e Six Fractional PLLs e Two Hard Memory Controllers e Six 3 125G Transceivers Configuration and Debug e Quad Serial Configuration device EPCQ256 on FPGA e On Board USB Blaster Normal type B USB connector Memory Device e LPDDR2 x32 bits data bus e SRAM x16 bits data bus Communication e UART to USB Connectors e HSMC x 1 including 4 lanes 3 125G transceiver e 2x20 GPIO Header e Arduino header including analog pins e SMA pads unpopulated Display e HDMI TX compatible with DVI v1 0 and HDCP v1 4 asic Terasic Cyclone V GX Starter Kit User Manual www terasic com www Audio e 24 bit CODEC Line in line out and microphone in Jacks Switches Buttons and LEDs e 18LEDs 10 Slide Switches e 4 Debounced Push Buttons e CPU reset Push Buttons Power e 12V DC input asic Terasic Cyclone V GX Starter Kit User Manual www terasic com 1 4 Block Diagram of the Cyclone V GX Starter Kit Board Figure 1 4 gives the block diagram of the board To provide maximum flexibility for the user all connections are made through the Cyclone V GX FPGA device Thus the user can configure the FPGA to implement any system design USB Type B USB Type B HDMI TX Audio Jack a a ed SMA Transceiver DNI gg 34 gt Micro SD Card A XCVR 4 EE JNO S RA
9. LVDS TX bit 0 or CMOS I O LVDS TX bit 1 or CMOS LVDS TX bit 2 or CMOS I O 48 LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V PIN_E15 PIN D13 PIN D15 PIN D16 PIN D17 PIN_E19 PIN_D20 PIN A24 PIN N12 PIN M11 PIN H18 PIN L12 PIN H15 PIN J12 PIN G16 PIN G12 PIN E18 PIN F16 PIN E13 PIN C14 PIN E16 PIN D18 PIN E20 PIN D21 PIN B24 PIN PIN B9 PIN C10 PIN 11 PIN A11 PIN B19 PIN C15 PIN A21 PIN C12 PIN A9 PIN A13 PIN C22 PIN B14 PIN A22 PIN B17 PIN C18 PIN B20 PIN E10 PIN C9 PIN D10 www terasic com PIN A12 PIN B10 PIN C20 PIN B15 PIN B22 PIN C13 A8 PIN B12 PIN C23 PIN A14 A23 PIN C17 PIN C19 PIN B21 3 11 Using the 2x20 GPIO Expansion Header The board provides one 40 pin expansion header GPIO and one Arduino Uno R2 expansion header These two kinds of expansio
10. as shown in Figure 6 19 Processing FAT32 sdcard mount success Root Directory Item Count 2 test txt dump Ok Press KEY3 to test again Figure 6 19 Running result of SD_ CARD demo on C5G board 6 7 SD Card music player demonstration Many commercial media audio players use a large external storage device such as an SD Card or CF card to store music or video files Such players may also include high quality DAC devices so that good audio quality can be produced The C5G board provides the hardware and software needed for Micro SD Card access and professional audio performance so that it is possible to design advanced multimedia products using the C5G board In this demonstration we show how to implement an SD Card Music Player on the C5G board in which the music files are stored in an SD Card and the board can play the music files via its CD quality audio DAC circuits We use the Nios II processor to read the music data stored in the SD Card and use the Analog Devices SSM2603 audio CODEC to play the music Figure 6 20 shows the hardware block diagram of this demonstration The system requires a 50 clock provided from the board PLL generates a 100MHz clock for Nios II processor and the other controllers except for the audio controller The audio chip is controlled by the Audio Controller which is a user defined SOPC component This audio controller needs an input clock of 18 432 MHz In this desi
11. or off individually or by clicking Light All or Unlight All Figure 2 3 Controlling LEDs Terasic Cyclone V GX Starter Kit User Manual www terasic com www Choosing the 7 SEG tab leads to the window shown in Figure 2 4 From the window directly use the left right arrows to control the 7 SEG patterns on the Cyclone V GX Starter board which are updated immediately Note that the dots of the 7 SEGs are not enabled on Cyclone V GX Starter Board 8 Em Em Figure 2 4 Controlling 7 SEG display The ability to set arbitrary values into simple display devices is not needed in typical design activities However it gives users a simple mechanism for verifying that these devices are functioning correctly in case a malfunction is suspected Thus it can be used for troubleshooting purposes asic Terasic Cyclone V GX Starter Kit User Manual www terasic com www 2 3 Switches and Push buttons Choosing the Switches tab leads to the window in Figure 2 5 The function is designed to monitor the status of slide switches and push buttons in real time and show the status in a graphical user interface It can be used to verify the functionality of the slide switches and push buttons W3 SW2 SW1 SW0 Figure 2 5 Monitoring switches and buttons The ability to check the status of push button and slide switch is not needed in typical design activities However it provides users a simple mechanism to verify if the but
12. Bit Stream Clock 2 5 V PIN E6 I2C_SCL 2 Clock 2 5 V PIN_B7 I2C_SDA 12 Data 2 5 V PIN G11 3 10 HSMC High Speed Mezzanine Card The FPGA development board contains one HSMC connector The HSMC connector provides a mechanism to extend the peripheral set of an FPGA host board by means of add on cards which can address today s high speed signaling requirement as well as low speed device interface support The HSMC interfaces support JTAG clock outputs and inputs high speed serial I O transceivers and single ended or differential signaling The HSMC interface connected to the Cyclone V GX device is a female HSMC connector having a total of 172pins including 121 signal pins 120 signal pins 1 PSNTn pin 39 power pins and 12 ground pins The HSMC connector is based on the SAMTEC 0 5 mm pitch surface mount QSH family of high speed board to board connectors The Cyclone V GX device provides 12 V DC and 3 3 V DC power to the mezzanine card through the HSMC connector Table 3 15 indicates the 44 asic Terasic Cyclone V GX Starter Kit User Manual www terasic com maximum power consumption for the HSMC connector Note that the 12V DC power rail goes through a jumper See Figure 3 22 The function of the jumper is to avoid cases when users no longer use the 12V power and the power goes directly to HSMC daughter boards and thus leads to burning the FPGA I Os This jumper can be found bottom right corner near the HSMC connector
13. Configuration Project Www terasre Cyclone V GX Starter Kit CoG iv CLOCK iv 7 Segment x 4 LED x18 Switch x 10 Button x 4 iv SD CARD HDMI TX M Audio SRAM b12KB LPDDR2 512MB UART to USB 515338 I2C SMA XCVR DNI GPIO Header Prefix Name Arduino Digital x Prefix Name None M Default Setting Load Setting Save Setting Generate Figure 4 6 Arduino Expansion HSMC Expansion Users can connect HSMC daughter cards onto the HSMC connector located on the development board As shown in Figure 4 7 select the daughter card you wish to add to your design under the appropriate HSMC connector to which the daughter card is connected The System Builder will automatically generate the associated pin assignment including pin name pin location pin direction and I O standard 61 11 V GX Starter Kit User Manual www terasic com www terasic com V GX Starter Kit V1 0 0 F S System Configuration INDERA Project Name Cyclone V GX Starter Kit ese i iv CLOCK 7 Segment x 4 LEDx18 Switch x 10 iv Button x 4 50 CARD HDMI TX F Audio SRAM 512KB LPDDR2 512MB UART to USB iv ADC 515338 I2C SMAXCVR DNI GPIO Header Prefix Name None 4 Default Setting Load Setting Save Setting Generate Figure 4 7 HSMC Expansion The Prefix Name is an op
14. DQS p1 DDR2LP DQS p2 DDR2LP DQS p3 DDR2LP DQS DDR2LP DQS DDR2LP DQS n2 DDR2LP DQS n3 Terasic Cyclone V GX Starter Kit User Manual www teresic com Command address bus Command address bus Command address bus Command address bus Command address bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data bus Data Strobe positive Data Strobe positive Data Strobe positive Data Strobe positive Data Strobe negative Data Strobe negative Data Strobe negative Data Strobe negative 39 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL Differential 1 2 V HSUL Differential 1 2 V HSUL Differential 1 2 V HSUL Differential 1 2 V HSUL Differential 1 2 V HSUL Differential 1 2 V HSUL Differential 1 2 V HSUL Differential 1 2 V HSUL PIN_U11 PIN AE9 PIN AF9 PIN AB12
15. GPIO 25 3 3V GND GPIO 26 GPIO 27 GPIO 28 GPIO 29 GPIO 30 GPIO 31 GPIO 32 GPIO 33 GPIO 34 GPIO 35 Figure 3 25 GPIO Pin Arrangement Table 3 18 Power Supply of the Expansion Header Supplied Voltage Max Current Limit 5V 1A 3 3V 1 5A www terasic com Each pin on the expansion headers is connected to two diodes and a resistor that provides protection against high and low voltages Figure 3 26 shows the protection circuitry for only one of the pin on the header but this circuitry is applied for all 36 data pins _ JP9 e e O e e NU RYAN 3 GPIO 35 0 ee Cycione V mn GX a a NN _ O ee e E Figure 3 26 Connections between the GPIO connector and Cyclone V GX FPGA Table 3 19 Pin Assignments for 40 pin Expansion Header connector and share bus signal Schematic Share Bus S Cyclone V GX Description VO Standard Signal Signal Name Pin Number GPIO0 GPIO DATA 0 Dedicated Clock Input 3 3 V PIN_T21 GPIO1 GPIO DATA 1 3 3 V PIN_D26 GPIO2 GPIO DATA 2 Dedicated Clock Input 3 3 V PIN_K25 GPIO3 Arduino IOO GPIO DATA 3 Arduino IOO 3 3 V PIN E26 GPIO4 101 GPIO DATA 4 Arduino 101 3 3 V PIN_K26 GPIO5 Arduino 102 GPIO 5 Arduino 102 3 3 V PIN_M26 GPIO6 GPIO DATA 6 Arduino 1
16. LEDR9 LEDRO LEDR1 LEDR2 LEDR3 LEDR6 LEDR7 LEDR8 LEDR9 Figure 3 10 Connections between the LEDs and Cyclone V GX FPGA Table 3 4 lists the signal names and their corresponding Cyclone V GX device pin numbers 30 Cyclone V GX Starter Kit User Manual www terasic com Table 3 4 User LEDs Pin Assignments Schematic Signal Names and Functions Board Schematic VO Cyclone V GX Description Reference Signal Standard Pin Number LEDR0 LEDR0 Driving a logic 1 on the port turns the LED 2 5 V PIN_F7 LEDR1 LEDR1 ON 2 5 V PIN_F6 LEDR2 LEDR2 Driving a logic 0 on the port turns the LED 2 5 PIN G6 LEDR3 LEDR3 OFF 2 5 V PIN_G7 LEDR4 LEDR4 2 5 V PIN_J8 LEDR5 LEDR5 2 5 V PIN_J7 LEDR6 LEDR6 2 5 V PIN_K10 LEDR7 LEDR7 2 5 V PIN_K8 LEDR8 LEDR8 2 5 V PIN_H7 LEDR9 LEDR9 2 5 V PIN_J10 LEDGO LEDGO 2 5 V PIN_L7 LEDG1 LEDG1 2 5 V PIN_K6 LEDG2 LEDG2 2 5 V PIN_D8 LEDG3 LEDG3 2 5 V PIN E9 LEDG4 LEDG4 2 5 V PIN_A5 LEDG5 LEDG5 2 5 V PIN_B6 LEDG6 LEDG6 2 5 V PIN_H8 LEDG7 LEDG7 2 5 V PIN_H9 B User Defined 7 Segment Displays The FPGA board has four 7 segment displays As indicated in the schematic in Figure 3 11 the seven segments common anode are connected to pins on Cyclone V GX FPGA Applying a low logic level to a segment will light it up and applying a high logic level turns it off Please note that two 7 segment displays HEX2 and HEX3 share bus with the GPIO When using HEX2 and
17. PIN AB11 PIN AA14 PIN Y14 PIN AD11 PIN AD12 PIN Y13 PIN W12 PIN AD10 PIN AF12 PIN AC15 PIN AB15 PIN AC14 PIN AF13 PIN AB16 PIN AA16 PIN AE14 PIN AF18 PIN AD16 PIN AD17 PIN AC18 PIN AF19 PIN AC17 PIN AB17 PIN AF21 21 15 16 20 AD21 16 17 AD23 AF23 V13 114 V15 W16 W13 PIN V14 PIN W15 PIN W17 www terasic com Data Write Mask byte enables 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL 1 2 V HSUL Differential 1 2 V HSUL DDR2LP_DM0 DDR2LP_DM1 Data Write Mask byte enables DDR2LP_DM2 Data Write Mask byte enables DDR2LP_DM3 Data Write Mask byte enables DDR2LP_CK_p Differential Output Clock positive DDR2LP CK n Differential Output Clock negative DDR2LP CKEO DDR2LP CKE1 DDR2LP CS DDR2LP CS ni Clock Enable 0 Clock Enable 1 Not use Chip Select 0 Chip Select 1 Not use DDR2LP OCT RZQ ZQ calibration External resistance 2400 1 3 7 Micro SD Card The development board supports Micro SD card interface using x4 data lines Figure 3 18 shows the related signals connections between the SD Card and Cyclone V GX FPGA and Figure 3 19 shows micro SD card plug in position Finally Table 3 12 lists all the associated pins Differential 1 2 V HSUL 1 2 V HSUL _1 2 HSUL _1 2 HSUL 1 2 V HSUL
18. TX n3 HSMC TX n4 HSMC TX n5 HSMC TX n6 HSMC TX n7 HSMC TX n8 HSMC TX n9 HSMC TX n10 HSMC TX nti HSMC TX n12 HSMC TX n13 HSMC TX n14 HSMC TX n15 HSMC TX n16 HSMC TX pO HSMC TX HSMC TX p2 Terasic Cyclone V GX Starter Kit User Manual www teresic com LVDS RX bit 9n or CMOS I O LVDS RX bit 10n or CMOS I O LVDS RX bit 11n or CMOS I O LVDS bit 12n or CMOS I O LVDS RX bit 13n or CMOS I O LVDS bit 14n or CMOS I O LVDS bit 15n or CMOS I O LVDS bit 16n or CMOS I O LVDS RX bit 0 or CMOS I O LVDS RX bit 1 or CMOS I O LVDS RX bit 2 or CMOS I O LVDS RX bit 3 or CMOS I O LVDS RX bit 4 or CMOS I O LVDS RX bit 5 or CMOS I O LVDS RX bit 6 or CMOS I O LVDS RX bit 7 or CMOS I O LVDS RX bit 8 or CMOS I O LVDS RX bit 9 or CMOS I O LVDS bit 10 or CMOS I O LVDS bit 11 or CMOS I O LVDS bit 12 or CMOS I O LVDS bit 13 or CMOS I O LVDS bit 14 or CMOS I O LVDS bit 15 or CMOS I O LVDS bit 16 or CMOS LVDS TX bit or CMOS I O LVDS TX bit 1n or CMOS I O LVDS TX bit 2n or CMOS I O LVDS TX bit or CMOS I O LVDS TX bit or CMOS I O LVDS TX bit 5n or CMOS I O LVDS TX bit or CMOS I O LVDS TX bit 7n or CMOS I O LVDS TX bit 8n or CMOS I O LVDS TX bit 9n or CMOS I O LVDS TX bit 10n or CMOS I O LVDS TX bit 11n or CMOS I O LVDS TX bit 12n or CMOS LVDS TX bit 13n or CMOS I O LVDS TX bit 14n or CMOS LVDS TX bit 15n or CMOS LVDS TX bit 16n or CMOS
19. bit SD MODE is used to access the SD Card This function can be used to verify the functionality of the SD Card Interface Follow the steps below to perform the SD Card exercise 1 Choosing the SD Card tab leads to the window in Figure 2 7 2 Insert an SD Card to the Cyclone V GX Starter board and then press the Read button to read the SD Card The SD Card s identification specification and file format information will be displayed in the control window Figure 2 7 Reading the SD Card Identification and Specification 2 6 ADC From the Control Panel users are able to view the eight channel 12 bit analog to digital converter reading The values shown are the ADC register outputs from all of the eight separate channels The Terasic Cyclone V GX Starter Kit User Manual www terasic com www voltage shown is the voltage reading from the separate pins on the extension header Figure 2 8 shows the ADC readings when the ADC tab is chosen Figure 2 8 Reading of eight channel ADC 2 7 UART USB Communication The Control Panel allows users to verify the operation of the UART to USB serial communication interface on the Cyclone V GX Starter Board The setup is established by connecting a USB cable from the PC to the USB port where the Control Panel communicates to the terminal emulator software on the or vice versa The Receive terminal window on the Control Panel monitors the serial communication status Follow the ste
20. bus PIN H20 SRAM_A4 Address bus PIND25 36 asic Terasic Cyclone V GX Starter Kit User Manual www terasic com SRAMA5 Address bus 3 3 V PIN C25 3 3 V 3 3 V 33 V PIN_D22 33V 23 _ 920 SRAM Ai 7 Addressbus 33V PINF2 SRAM 7 Addressbus 33 PINEZ SRAM 13 77 Addressbs 33V 3 3 V __SRAM_AIS 77 Addressbs 33V 3 3 V 3 3 V 3 3 V SRAMD 33V SRAMD2 Databus 33 SRAMD3 Databus 33V 3 3 V SRAMD5 33V PING24 3 3 V 3 3 V 3 3 V 3 3 V 3 3 V SRAMDi Daabs 33V SRAM Di2 33 SRAMDI3 7 Databus 33V PING22 3 3 V ___5 5 Databus 33V PINK2 3 3 V __ OEn Output Enable activeLow 3 3 V SRAM WEn Write Enable activeLow 33 SRAM LB n Lower Byte Control 00 07 active Low 3 3 V SRAM UB n Upper Byte Control D8 D15 active Low 3 3 V 3 6 LPDDR2 Memory The development board has one 4Gb Mobile Low Power DDR2 SDRAM LPDDR2 which is a high speed CMOS dynamic random access memory containing 4 294 967 296 bits shown Figure 3 16 For detailed information on how to use the LPDDR2 please refer to the datasheet which is 37 Terasic Cyclone V GX Starter User Manual www terasic com available on the manufacturer s website or under the Datasheets LPDDR2 folder on the Kit System CD Figure 3 17 shows the related schema
21. data inputs to a circuit Each switch is connected directly to a pin on the Cyclone V GX FPGA When the switch is in the DOWN position closest to the edge of the board it provides a low logic level to the FPGA and when the switch is in the UP position it provides a high logic level Table 3 3 lists the signal names and their corresponding Cyclone V GX device pin numbers ANO 8 RYA dd Logic 1 SW8 SW SW6 SW3 SW2 SW1 Logic 0 Figure 3 9 Connections between the slide switches and Cyclone V GX FPGA 29 Terasic Cyclone V GX Starter Kit User Manual www terasic com Table3 3 Slide Switch Pin Assignments Schematic Signal Names and Functions Board Schematic Reference Signal Name vom Cyclone GX Description Standard Pin Number Slide Switch 0 PIN 9 SW Sw Slide Switch 4 Sw Slide Switch 6 Slide Switch 7 SW8 SW8 Slide Switch 8 Swe Sw Slide Switch 9 B User Defined LEDs There are also eighteen user controllable LEDs connected to FPGA on the board Ten red LEDs are situated above the ten slide switches and eight green LEDs are found above the push button switches Each LED is driven directly by a pin on the Cyclone GX FPGA driving its associated pin to a high logic level turns the LED on and driving the pin low turns it off Figure 3 10 shows the connections between LEDs and Cyclone V GX FPGA LEDRO LEDR1 LEDR2 LEDR3 LEDR6 LEDR7 LEDR8
22. in Figure 6 9 79 asic Terasic Cyclone V GX Starter Kit User Manual www terasic com www 2 PAL tera Nios II EDS 130sp1 gcc o Subscription Agreement Altera MegaCore Function License Agreement or other applicable license agreement including without limitation that your use is for the sole purpose of programming logic devices manufactured by Altera and sold hy Altera or its authorized distributors Please refer to the applicable agreement for further details sing started Thu Jul 18 17 37 38 2613 uartus m jtag c 1 o p CSG_HDMI_UPG sof 1 ing programming cable USB Blaster USB 81 ng programming file C5G HDMI UPG sof with checksum x 71CC785 for device SCGKFCSC6F27 1 Started Programmer operation at Thu Jul 18 17 37 39 2013 Configuring device index 1 Device 1 contains JTAG ID code 8x82B820DD Configuration succeeded 1 device lt s gt configured Successfully performed operation lt s gt Ended Programmer operation at Thu Jul 18 17 37 47 2013 Quartus II 32 bit Programmer was successful errors warnings Info Peak virtual memory 197 megabytes Info Processing ended Thu Jul 18 17 37 47 2013 Info Elapsed time 00 00 09 Info Total CPU time all processors 90 00 01 Using cable USB Blaster USB 81 device 1 instance 8x88 Resetting and pausing target Initializing CPU cache Cif present gt Downloaded 130KB 2 25 59 KB s gt Uerified
23. lists the all the pin assignments of the Arduino Uno connector digital signal names relative to the Cyclone V GX device Table 3 20 Pin Assignments for Arduino Uno Expansion Header connector Signal Name Pin NINE Arduino 100 Arduino 101 ee om Arduino 102 ArdunolO2 33V 26 Arduino 03 Arduinol03 33V PNMM Arduino 104 Arduinol04 33 PIN P2 Arduino 105 Arduino 105 106 ArduinolO7 Arduinol07 33 PINUI9 Arduino 108 Arduinol08 33V PNU2 Arduino 109 Arduino 1010 Arduino 1011 Arduinolo11 33V PIR Arduino 1012 Arduinolo12 33V PINRIO Arduino 1013 Arduino 1013 33 V F2 Arduino Reset n Reset signal low active PIN AB24 Terasic Cyclone V GX Starter Kit User Manual 53 www terasic com Besides 14 pins for digitial GPIO there are also 8 analog inputs on the Arduino Uno Expansion Header Consequently we use ADC LTC2308 from Linear Technology the board for possible future analog to digital applications The LTC2308 is a low noise 500ksps 8 channel 12 bit ADC with an SPI MICROWIRE compatible serial interface This ADC includes an internal reference and a fully differential sample and hold circuit to reduce common mode noise The internal conversion clock allows the external serial output data clock SCK to operate at any frequency up to 40MHz The LTC2308 is controlled via a serial SPI bus interfa
24. loop chain on Cyclone V GX Starter Kit board See Figure 3 2 Thus only the on board FPGA device Cyclone V GX will be detected by the Quartus II programmer If users want to include another FPGA device or interface containing FPGA device in the chain via HSMC connector remove JP2 Jumper open pinl and pin2 on JP2 to enable the JTAG signal ports on the HSMC connector USB Embedded Blaster Connector TDI MISES EPM240 nace Controller TDI TDO TDI 1 so JP2 GX Figure 3 1 The JTAG chain on Cyclone V GX Starter Kit board v B JP2 Figure 3 2 The JTAG chain configuration header The sections below describe the steps to perform both JTAG and AS programming For both methods the Cyclone V GX Starter Kit board is connected to a host computer via a USB cable Using this connection the board will be identified by the host computer as an Altera USB Blaster device 24 asic Terasic Cyclone V GX Starter Kit User Manual www terasic com B Configuring the FPGA in JTAG Mode Figure 3 3 illustrates the JTAG configuration setup To download a configuration bit stream into the Cyclone V GX FPGA you need to perform the following steps e Ensure that power is applied to the Cyclone V GX Starter Kit board e Configure the JTAG programming circuit by setting the RUN PROG slide switch SW11 to the RUN position See Figure 3 4 e Connect the supplied USB cable to the USB Blaster port on the Cyclone
25. serial resistor 47 ohm to 15 pins 14pins GPIO and Ipin Reset of the Cyclone V GX FPGA 8 pins Analog input connects to ADC and also provides DC 3 3 V 3 3 V 3 3 V 3 3 V 3 3 V 3 3 V 3 3 V 3 3 V 3 3 V 3 3 V 3 3 V 3 3 V 3 3 V 3 3 V 3 3 V 3 3 V 3 3 V 3 3 V 3 3 V 3 3 V 3 3 V 3 3 V 3 3 V 3 3 V 3 3 V 12V VCC12 DC 5V 5 DC 3 3V VCC3P3 and three GND pins Please refer to Figure 3 27 for detailed pin out information The red font in Figure 3 28 represents the signal name shared bus connected to FPGA 52 Terasic Cyclone V GX Starter User Manual PIN U22 PIN P8 PIN R8 PIN R9 PIN R10 PIN F26 PIN Y9 PIN G26 PIN Y8 PIN AA7 PIN AA6 PIN AD7 PIN AD6 PIN U20 PIN V22 PIN V20 PIN W21 PIN W20 PIN Y24 PIN Y23 PIN AA23 PIN AA22 PIN AC24 PIN AC23 PIN AC22 www terasic com Analog_Vref NC GND Arduino_l013 GPIO16 VCC3P3 CPU_Reset_n Arduino_Reset_n 1012 GPIO15 VCC3P3 Arduino 1011 GPIO14 VCC5 Arduino 010 GPIO13 GND Arduino 109 GPIO12 GND Arduino 108 GPIO11 VCCI2 Arduino Arduino 107 GPIO10 106 GPIO9 ptem 105 GPIO8 g m 04 GPIO7 g ees Arduino IO3 SP Interface lt Analog_in5 Arduino_lO2 GPIOS Arduino 01 4 f Analog_In5 _100 GPIO3 lt Analog In6 Analog In7 Figure 3 27 Arduino Pin Arrangement and Connections Table 3 20
26. sure the project is cleaned first by clicking Clean from the Project menu of Nios II Eclipse B Demonstration Batch File Demo Batch File Folder C5G SD MUSICNdemo batch The demo batch file includes following files e Batch File for USB Blaster CSG SD MUSIC bat C5SG SD MUSIC sh e FPGA Configure File 56 SD MUSIC sof e Nios II Program 56 SD MUSIC e f B Demonstration Setup e Format your Micro SD Card into FAT16 FAT32 format Place the wave files to the root directory of the Micro SD Card The provided wave files must have a sample rate of either 96K 48K 44 1K 32K or 8K In addition the wave files must be stereo and 16 bits per channel e Connect a headset or speaker to the C5G board and you should be able to hear the music played from the Micro SD Card e Insert the Micro SD card into the sd socket on C5G borad e Make sure Quartus II and Nios II are installed on your PC Power on the C5G board e Connect USB Blaster to the C5G board and install USB Blaster driver if necessary e Execute the demo batch file C5SG SD MUSIC bat under the batch file folder C5G SD MUSIC Memo batch e Press KEY3 on the C5G board to play the next music file stored in the SD Card and press KEYO to play last song e Press KEY2 and KEY to increase and decrease the output music volume respectively e Use Switch to play music in repeat mode or sequence mode 94 asic Terasic Cyclone V GX Starter Kit User Manual www terasic
27. the board is listed where users can enable or disable a component according to their design by simply marking a check or removing the check in the field provided If the component is enabled the C5G System Builder will automatically generate the associated pin assignments including the pin name pin location pin direction and I O standard Terasic Cyclone V GX Starter Kit V1 0 0 x System Configuration Project Name CoG iv CLOCK 7 Segment x 4 LEDx18 Switch x 10 Button x 4 iv SD CARD HDMI TX iv Audio iv SRAM b12KB LPDDR2 512MB iv UART to USB iv ADC 515338 2C SMA XCVR DNI GPIO Header Name 1 None E HSMC Prefix Name Y None E Default Setting Load Setting Save Setting Generate Exit Figure 4 4 System Configuration Group B GPIO Expansion Users can connect GPIO daughter cards onto the GPIO connector located on the development board As shown in Figure 4 4 select the daughter card you wish to add to your design under the appropriate HSMC connector to which the daughter card is connected The System Builder will automatically generate the associated pin assignment including pin name pin location pin direction and I O standard Note the GPIO header share bus with 7 segments HEX3 and 2 So when GPIO header is used the 7 segments only HEXO and are available as shown in 7 Segment x2 in Figure 4 5 Also in physica
28. the drop down menu shown in Figure 2 10 where you can output the selected color individually Figure 2 10 Controlling VGA display 2 9 HSMC Select the HSMC tab to reach the window shown in Figure 2 11 This function 15 designed to verify the functionality of the signals located on the HSMC connector Before running the HSMC loopback verification test follow the instruction noted under the Loopback Installation section and click on Verify Please note to turn off the Cyclone V GX Starter board before the HSMC loopback adapter is installed to prevent any damage to the board The HSMC loopback adapter is not provided in the kit package but can be purchased through the website below http hsmc_loopback terasic com 20 asic Terasic Cyclone V GX Starter Kit User Manual www terasic com the HSMC loopback cted to the HSMC Figure 2 11 HSMC loopback verification test performed under Control Panel 2 10 Overall Structure of the C5G Control Panel The C5G Control Panel is based on a Nios II Qsys system instantiated in the Cyclone V GX FPGA with software running on the on chip memory The software part is implemented in C code the hardware part is implemented in Verilog HDL code with Qsys builder The source code is not available on the C5G System CD To run the Control Panel users should make the configuration according to Section 3 1 Figure 2 12 depicts the structure of the Control Panel Each input output device is controlled
29. two parts the hardware design and the software control program A set of pre built video patterns will be sent out through the HDMI interface and presented on the LCD monitor as the user launches the provided executable binaries The design incorporates certain activities the user could perform to interact with the on board HDMI TX encoder B System Block Diagram Figure 6 8 shows the system block diagram of this reference design The module Video Pattern Generator copes with generating video patterns to be presented on the LCD monitor The pattern is composed in the way of 24 bit RGB 4 4 4 RGB888 per color pixel without sub sampling color encoding which corresponds to the parallel encoding format defined in Table 5 of the ADV7513 Hardware User s Guide as shown below 75 Terasic Cyclone V GX Starter Kit User Manual www terasic com www teresic com Pixel Data 23 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 7 0 G 7 0 B 7 0 Figure 6 8 Build in Display Modes of the HDMI TX Demonstration A set of display modes are implemented for presenting the generated video patterns The module Video Source Selector controls the selection of current video timing among build in display modes listed in Table 6 1 The module Mode Control allows users to switch current display mode alternatively via the KEY1 push button Table 6 1 Bui
30. 03 3 3 V PIN_M21 GPIO7 Arduino_104 GPIO DATA 7 Arduino 104 3 3 V PIN_P20 GPIO8 Arduino_105 GPIO DATA 8 Arduino 105 3 3 V PIN T22 GPIO9 Arduino 6 GPIO DATA 9 Arduino 106 3 3 V PIN_T19 GPIO10 Arduino 107 GPIO DATA 10 Arduino 107 3 3 V PIN U19 51 asic Terasic Cyclone V GX Starter Kit User Manual www terasic com WWW GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 GPIO35 108 Arduino 109 1010 1011 1012 1013 HEX2 HEX2_D1 HEX2 D2 HEX2 D3 2 D4 HEX2 D5 HEX2 D6 HEX3 DO HEX3 D1 HEX3 D2 HEX3 D3 HEX3 HEX3 D5 HEX3 D6 GPIO DATA 11 Arduino 108 GPIO DATA 12 Arduino 109 GPIO DATA 13 Arduino 1010 GPIO DATA 14 Arduino 1011 GPIO DATA 15 Arduino 1012 GPIO DATA 16 Arduino 1013 PLL Clock output GPIO DATA 17 GPIO DATA 18 PLL Clock output GPIO DATA 19 GPIO DATA 20 GPIO DATA 21 GPIO DATA 22 GPIO DATA 23 GPIO DATA 24 GPIO DATA 25 GPIO DATA 26 GPIO DATA 27 GPIO DATA 28 GPIO DATA 29 GPIO DATA 30 GPIO DATA 31 GPIO DATA 32 GPIO DATA 33 GPIO DATA 34 GPIO DATA 35 B Arduino Uno Expansion Header The board provides Arduino Uno revision 2 compatibility expansion header which comes with four independent headers The headers connect
31. 2 5 V PIN_B7 I2C_SDA I2C Data 2 5 V PIN_G11 3 9 Audio Interface The board provides high quality 24 bit audio via the Analog Devices SSM2603 audio CODEC Encoder Decoder This chip supports microphone in line in and line out ports with a sample rate adjustable from 8 kHz to 96 kHz The SSM2603 is controlled via a serial I2C bus interface which is connected to pins on the Cyclone V GX FPGA A schematic diagram of the audio circuitry is shown in Figure 3 21 Detailed information on using the SSM2603 codec is available in its datasheet which can be found on the manufacturer s website or under the Datasheets Audio CODEC folder on the Kit System CD Table 3 14 lists the Audio Codec pin assignments and signal names relative to the Cyclone V GX device 43 Terasic Cyclone V GX Starter User Manual www terasic com AUD_XCK AUD_BCLK AUD_DACDAT AUD_DACLRCK MCLK XTI BCLK PBDAT PBLRC RECDAT RECLRC SCLK SDIN AUD_ADCDAT AUD_ADCLRCK I2C SCL 2 SDA Figure 3 21 Connections between FPGA and Audio CODEC Table 3 14 Audio CODEC Pin Assignments Schematic Signal Names and Functions Schematic aS Cyclone V GX Description Standard Signal Name Pin Number AUD_ADCLRCK Audio CODEC ADC LR Clock 2 5 V PIN_C7 AUD_ADCDAT Audio CODEC ADC Data 2 5 V PIN_D7 AUD_DACLRCK Audio CODEC DAC LR Clock 2 5 V PIN G10 AUD DACDAT Audio CODEC DAC Data 2 5 V PIN H10 AUD XCK Audio CODEC Chip Clock 2 5 V PIN D6 AUD BCLK Audio CODEC
32. A at any time and it is also possible to change the non volatile data that is stored in the serial configuration device Both types of programming methods are described below 1 programming In this method of programming named after the IEEE standards Joint Test Action Group the configuration bit stream is downloaded directly into the Cyclone GX FPGA The FPGA will retain this configuration as long as power is applied to the board the configuration information will be lost when the power is turned off 2 AS programming In this method called Active Serial programming the configuration bit stream is downloaded into the Altera EPCQ256 serial configuration device It provides non volatile storage of the bit stream so that the information is retained even when the power supply to the Cyclone V GX Starter Kit board is turned off When the board s power is turned on the configuration data in the EPCQ256 device is automatically loaded into the Cyclone V GX FPGA B JTAG Chain on Cyclone GX Starter Kit board To use JTAG interface for configuring FPGA device the JTAG chain on Cyclone V GX Starter Kit must form a closed loop that allows Quartus II programmer to detect FPGA device Figure 3 1 illustrates the JTAG chain on Cyclone GX Starter Kit board Shorting and pin2 on JP2 23 asic Terasic Cyclone V GX Starter Kit User Manual www terasic com disable the JTAG signals on HSMC connector that will form a closed JTAG
33. C G LPDDR2 RTL Test Ndemo batch The demo batch file includes following files Batch File CSG LPDDR2 RTL Test bat FPGA Configure File CSG LPDDR2 RTL Test sof Demonstration Setup Make sure Quartus II is installed on your PC Connect the USB cable to the USB Blaster connector J10 on the C5G board and host PC Power on the C5G board Execute the demo batch file C5G_LPDDR2_RTL_Test bat under the batch file folder C5G LPDDR2 RTL Test demo_batch Press KEYO on the C5G board to start the verification process When KEYO is pressed the LEDs LEDG 2 0 should turn on At the instant of releasing KEY0 LEDG1 LEDG2 should start blinking After approximately 25 seconds LEDG1 should stop blinking and stay on to indicate that the LPDDR2 has passed the test respectively Table 5 1 lists the LED indicators If LEDG2 is not blinking it means 50MHz clock source is not working If LEDGI do not start blinking after releasing KEYO it indicates local init done or local cal success of the corresponding LPDDR2 failed If LEDGI fail to remain on after 25 seconds the corresponding LPDDRZ test has failed 66 asic Terasic Cyclone V GX Starter Kit User Manual www terasic com e Press KEY0 again to regenerate the test control signals for a repeat test Table 5 1 LED Indicators Table 5 2NAME Description LEDG0 Reset LEDG1 If light LPDDR2 test pass LEDG2 Blinks 67 asic Terasic Cyclone V GX Starter Kit User Manual www tera
34. Cuclone V GX Starter Kit USER MANUAL j mate sg LP d T 4 y 4 ABIER AN www terasic com Copyright 2003 2013 Terasic Technologies Inc All Rights Reserved _ a EM Vous HC P i T 9 mus a P as IS Rt lt m E an un NE iac OR _ T m CONTENTS E CHAPTER 1 INTRODUCTION 3 11 PACKAGE CONTENTS Em 3 1 2 CYCLONE V GX STARTER KIT SYSTEM CD sccssscssssesnsccosseesssscnsnsesnacconsesssossosetssscensesnascoscsessnsensnsesasossnsess snes 4 13 LAYOUT AND COMPONENTS P ai 4 1 4 BLOCK DIAGRAM OF THE CYCLONE GX STARTER KIT 1 8 HELP 25550 8 CHAPTER 2 CONTROL PANEL m 9 Del CONTROL PANEL SETUP tases cus dents 9 2 2 CONTROLLING THE LEDS 7 SEGMENT 12 2 3 SWITCHES AND PUSH BUTTONS 14 2 4 SRAM LPDDR2 CONTROLLER AND PROGRAMMER nn nn 15 DS SID CARD teet 17 17 2 7 UART USB
35. Digit 3 5 Share GPIO34 3 3 AC23 HEX0_D6 Seven Segment Digit 3 6 Share GPIO35 3 3 AC22 3 3 Clock Circuit The development board includes one 50MHz and one programmable Clock Generator Figure 3 13 shows the default frequencies of on board external clocks going to the Cyclone V GX FPGA 33 Terasic Cyclone V GX Starter User Manual www terasic com Si501 50MHz 50ppm 3 3 50MHz 2 5V 50 2 2 5 Bank 7A 125MHz LVDS or Variable 25MHz gt 156 25MHz LVDS or Variable Transceiver Black 125MHz LVDS or Variable Bank 3A Bank 3B Bank 4A Figure 3 13 Clock circuit of the FPGA Board The programming Clock Generator is a highly flexible and configurable clock generator buffer The is to provide special and high quality clock signals for high speed transceivers The clock generator is controlled by the FPGA through the I2C serial interface The user can modify the frequency between 0 16 MHz to 200 MHz Table 3 6 lists the clock source signal names default frequency and their corresponding Cyclone V GX device pin numbers Table 3 7 lists the programmable Clock Generator control pins signal names I O standard and their corresponding Cyclone V GX device pin numbers Table 3 6 Clock Source Signal Name Default Frequency Pin Assignments and Functions Schematic Cyclone V GX eee Application Signal Name Pin Number CLOCK_50_B3B PIN TI3
36. HEX3 you need to switch the Dip Switch 51 52 which is located on the back of the board to the ON position before FPGA can control corresponding 7 segment displays Each segment in a display is identified by an index listed from 0 to 6 with the positions given in Figure 3 12 In addition the decimal has no function at all Table 3 5 shows the mapping of the FPGA pin assignments to the 7 segment displays 31 Terasic Cyclone V GX Starter User Manual www terasic com VCC2P5 VCC2P5 8 L9 9 o gt vec2p5 HEX17 Segment Display 7 Segment Display VCC2P5 7 Segment Display 8 Z 9 9 o lt 7 Segment Display Figure 3 11 Connection between 7 segment displays and Cyclone V GX FPGA HEXO 0 HEXO 1 m ADIERA 3 4 gt HEXO 5 X A HEXO 6 Figure 3 12 Connections between the 7 segment display and Cyclone V GX FPGA Table 3 5 User 7 segment display Pin Assignments Schematic Signal Names and Functions Schematic Board a lO Cyclone V GX Signal Description Reference Standard Pin Number Name HEX0 HEX0_D0 Seven Segment Digit 0 0 2 5 19 32 Terasic Cyclone V GX Starter Kit User Manual www terasic com www HEX0 HEX0_D1 Seven Segment Digit 0 1 2 5 18 HEXO HEXO D2 Seven Segment Digit 0 2 2 5 V17 HEXO HEXO D3 Seven Segment Digit 0 3 2 5 W18 HEX
37. LVDS bit 1n or CMOS I O LVDS bit 2n or CMOS I O LVDS RX bit 3n or CMOS I O LVDS RX bit 4n or CMOS I O LVDS RX bit 5n or CMOS I O LVDS RX bit 6n or CMOS I O LVDS bit 7n or CMOS I O LVDS RX bit 8n or CMOS I O 47 2 5 V or LVDS 2 5 V or LVDS 2 5 V 2 5 V or LVDS 2 5 V or LVDS 2 5 V or LVDS 2 5 V or LVDS 2 5 V 2 5 V 2 5 V 2 5 V 2 5 V 2 5 V 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML 1 5 V PCML LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V LVDS or 2 5 V PIN_G15 PIN_L8 PIN A7 PIN A18 PIN A16 PIN A19 PIN A17 D11 PIN H14 PIN D12 PIN H13 PIN B7 PIN G11 PIN AD2 PIN AB2 PIN Y2 PIN V2 PIN 4 PIN 4 PIN AA W4 PIN AD1 PIN AB1 PIN Y1 PIN V1 PIN AE3 PIN AC3 AA3 PIN W3 PIN M12 PIN L11 PIN H17 PIN K11 PIN J16 PIN J11 PIN G17 PIN F12 PIN F18 www terasic com HSMC_RX _n9 HSMC RX n10 HSMC RX nii HSMC n12 HSMC n13 HSMC _ 14 HSMC _ 15 HSMC _n16 HSMC HSMC pi HSMC RX p2 HSMC RX p3 HSMC p4 HSMC RX p5 HSMC RX p6 HSMC p7 HSMC RX p8 HSMC RX p9 HSMC RX 10 HSMC RX pii HSMC 12 HSMC p13 HSMC RX 14 HSMC_RX _p15 HSMC_RX _p16 HSMC_TX _n0 HSMC_TX_n1 HSMC TX n2 HSMC
38. N Nc CTS Cyclone V Cyclone V GX FPGA wees unn unn mmummummum T T User Interface LED Slide Switch and Tact Switch g 70 Y Figure 1 4 Board Block Diagram 1 5 Getting Help Here are the addresses where you can get help if you encounter any problem e Terasic Technologies Taiwan 9F No 176 Sec 2 Gongdao 5th Rd East Dist Hsinchu City Taiwan 300 70 Email support terasic com Tel 886 3 5750 880 Web http c5g terasic com Cyclone V GX Starter Kit User Manual www terasic com eresic Chapter 2 Control Panel The Cyclone V GX Start board comes with a Control Panel program that allows users to access various components on the board from a host computer The host computer communicates with the board through a USB connection The program can be used to verify the functionality of components on the board or be used as a debug tool while developing RTL code This chapter first presents some basic functions of the Control Panel then describes its structure in the block diagram form and finally describes its capabilities 2 1 Control Panel Setup The Control Panel Software Utility is located in the directory Tools ControlPanel on the Cyclone V GX Starter Kit System CD It s free of installation just copy the whole folder to your host computer and launch the control panel by executing the C5G ControlPanel exe Specific control circui
39. Name Cyclone V GX Starter Kit EE iv CLOCK 7 Segment x 4 LEDx18 M Switch x 10 1 iv Button x 4 SDCARD f HDMI TX Audio SRAM 512KB M LPDDR2 512MB M UART to USB ADC 515338 2 5 DNI GPIO Header Prefix Name None HSMC Prefix Name None Y Generate Exit Default Setting Load Setting Figure4 2 The SoCKit System Builder window B Input Project Name Input project name as show in Figure 4 3 Project Name Type in an appropriate name here it will automatically be assigned as the name of your top level design entity Terasic Cyclone V GX Starter Kit V1 0 0 System Configuration Cyclone V GX Starter Kit f iv CLOCK 7 Segmentx 4 LEDx18 Switch x 10 i Button x 4 SD CARD HDMI TX M Audio SRAM b12KB LPDDR2 512MB UART to USB iv ADC 515338 2 XCVR DNI 2 GPIO Header ere Prefix Name Y Nons HSMC Prefix Name Y Nons Default Setting Load Setting Save Setting Generate Exit Figure4 3 Board Type and Project Name 58 Terasic Cyclone V GX Starter User Manual www terasic com www terasic com B System Configuration Under the System Configuration users are given the flexibility of enabling their choice of included components on the board as shown in Figure 4 4 Each component of
40. O HEXO D4 Seven Segment Digit 0 4 2 5 20 HEX0 HEX0_D5 Seven Segment Digit 0 5 2 5 19 HEXO HEXO D6 Seven Segment Digit O 6 2 5 V 18 1 00 Seven Segment Digit 1 0 2 5 PIN AA18 HEX1 HEXO D1 Seven Segment Digit 1 1 2 5 V AD26 HEX1 HEXO D2 Seven Segment Digit 1 2 2 5 V 19 1 HEXO D3 Seven Segment Digit 1 3 2 5 V PIN AE26 HEX1 HEXO 04 Seven Segment Digit 1 4 2 5 V AE25 HEX1 D5 Seven Segment Digit 1 5 2 5 AC19 1 HEXO 06 Seven Segment Digit 1 6 2 5 AF24 HEX2 HEXO DO Seven Segment Digit 2 0 Share GPIO22 3 3 V AD7 HEX2 HEXO D1 Seven Segment Digit 2 1 Share GPIO23 3 3 V AD6 HEX2 HEXO D2 Seven Segment Digit 2 2 Share GPIO24 3 3 20 2 HEX0_D3 Seven Segment Digit 2 3 Share GPIO25 3 3 V V22 HEX2 HEXO 0 4 Seven Segment Digit 2 4 Share GPIO26 3 3 20 2 HEX0_D5 Seven Segment Digit 2 5 Share GPIO27 3 3 V 21 2 HEX0_D6 Seven Segment Digit 2 6 Share GPIO28 3 3 V W20 DO Seven Segment Digit 3 0 Share GPIO29 3 3 24 HEX0_D1 Seven Segment Digit 3 1 Share GPIO30 3 3 PIN Y23 HEX3 HEX0_D2 Seven Segment Digit 3 2 Share GPIO31 3 3 AA23 HEX0_D3 Seven Segment Digit 3 3 Share GPIO32 3 3 PIN AA22 HEX3 HEXO D4 Seven Segment Digit 3 4 Share GPIO33 3 3 V 24 HEXO 05 Seven Segment
41. Starting processor at address 0x000801E8 connected to hardware target using JTAG UART on cable USB Blaster USB 1 device 1 tance Use the IDE stop button or Ctrl o terminate gt 54 4 1 77 adu7513 hdmi encoder demo chip fiDU 7511 rev 8x13 success to setup HDMI_TX_INT interrupt handler operation hints please wait for monitor sync the pattern will be auto sent out to your monitor press onboard push button can switch current display mode type in the command line prompt to see available commands a breif summary of commands for quick start up perform register space dump of the ADU7513 encoder display EDID raw data of currently connected monitor display EDID raw data of currently connected monitor and decode it in the human readable format display current UIC and mode info not exactly accurate power off the HDMI encoder power up the HDMI encoder and initialize it in HDMI mode command lt h for help gt Figure 6 10 Launching the HDMI TX Demonstration using the demo batch Folder e Wait for a few seconds for the LCD monitor to power up itself And you should see a pre defined video pattern shown on the monitor as shown in Figure 6 10 B Demonstration Operation The demonstration involves certain activities the user could perform to interact with the on board HDMI encoder Auto Hot Plug Detection The demonstration implements an interrupt driven hot plug detectio
42. The factory default setting is OFF meaning the 12V power won t be available to the daughter boards When users need to connect the daughter boards they need to switch the jumper to ON position Please see Table 3 15 for setting details DD 2 amp JP13 Figure 3 22 HSMC 12V Power Jump and Cyclone V GX FPGA default OFF Table 3 15 HSMC 12V Power Jump Setting Indicators HSMC 12V OFF J13 2 TP1 HSMC 12V ON J13 1 413 2 www terasic com There are three banks in this connector Figure 3 23 shows the bank arrangement of signals with respect to the SAMTEC connector Table 3 16 lists the mapping of the FPGA pin assignments to the HSMC connectors Bank 1 Power 8 TX Channels CDR 8 RX Channels CDR JTAG SMBus CLKINO CLKOUTO Bank 2 Power D 39 0 or D 3 0 LVDS CLKIN1 CLKOUT1 Bank 3 Power D 79 40 or LVDS CLKIN2 CLKOUT2 Figure 3 23 HSMC Signal Bank Diagram Table 3 16 Power Supply of the HSMC Supplied Voltage Max Current Limit 12V 1A 3 3V 1 5A Table 3 17 Pin Assignments for HSMC connector Schematic Cyclone V GX Description VO Standard Signal Number HSMC_CLKIN0 Dedicated clock input PIN_N9 HSMC CLKIN n1 LVDS RX or CMOS I O or 2 5 V or LVDS PIN G14 differential clock input HSMC CLKIN n2 LVDS RX or CMOS or 2 5 V or LVDS PIN K9 46 Terasic Cyclone V GX Starter Kit User Manual www ter
43. Use the IDE stop button or Ctrl C to terminate ensure the hsmc loopback daughter card is installed EDGO LEDG3 on indicate the related xcur channel test pass he system report test result every 5 seconds the test will continue and press 3 to terminate test est test all channels in parallel 5 JHSMC_XCUR_ pass _ _1 pass HSMC_XCUR_2 pass HSMC_XCUR_3 pass 19 1 _ _ pass HSMC XCUR 1 pass HSMC XCUR 2 pass HSMC XCUR 3 pass 15 1HSMC XCUR 8 pass HSMC XCUR 1 pass HSMC XCUR 2 pass HSMC XCUR 3 pass 29 1 _ _ pass _ _1 pass HSMC_XCUR_2 pass 3 pass Figure 6 13 Running result of XCVR HSMC loopback test e Press key0 key4 to terminate testing 6 5 Audio Recording and Playing This demonstration shows how to implement an audio recorder and player using the C5G board with the built in Audio CODEC chip This demonstration 1 developed based on Qsys and Eclipse Figure 6 14 shows the man machine interface of this demonstration Two push buttons and five slide switches are used to configure this audio system SW0 is used to specify recording source to be Line in MIC In SW1 is used to enable disable MIC Boost when the recording source is MIC In SW2 SW3 and SW4 are used to specify recording sample rate as 96K 48K 44 1K 32K or 8K The 7 SEG is used to display Recording Playing duration with time unit in 1 100 second The LED is used to indicate the a
44. V GX Starter Kit board See Figure 1 2 e The FPGA can now be programmed by using the Quartus II Programmer to select a configuration bit stream file with the sof filename extension USB Blaster Circuit II UART UART S RYA EPM 240 Config Signals Config Signals ey GX Figure 3 3 The JTAG configuration scheme SW11 Quartus II QUARTUS II Figure 3 4 The RUN PROG switch SW11 is set JTAG mode 25 Terasic Cyclone V GX Starter User Manual www terasic com Configuring the EPCQ256 in AS Mode Figure 3 5 illustrates the AS configuration setup To download a configuration bit stream into the 256 serial configuration device you need to perform the following steps e Ensure that power is applied to the Cyclone V GX Starter Kit board e Connect the supplied USB cable to the USB Blaster port on the Cyclone V GX Starter Kit board e Configure the JTAG programming circuit by setting the RUN PROG slide switch SW 11 to the PROG position e The EPCQ256 chip can now be programmed by using the Quartus Programmer to select a configuration bit stream file with the pof filename extension e Once the programming operation is finished set the RUN PROG slide switch back to the RUN position and then reset the board by turning the power switch off and back on this action causes the new configuration data in the EPCQ256 device to be lo
45. aded into the FPGA chip USB Blaster Circuit RUN Quartus II AS Mode Auto Power on II Config Config S 240 Ot ARTUS II V PROG GX Figure 3 5 The AS configuration scheme B Status LED e The FPGA development board includes board specific status LEDs to indicate board status Please refer to Table 3 1 for the description of the LED indicator Please refer to Figure 3 6 for detailed LED location Table 3 1 Status LED Board Reference _ D5 12 when 12 V power is active LED Name Description 26 11 V GX Starter Kit User Manual www terasic com D6 3 3 V Power when 3 3 V power is active D24 HSMC_12 V Power Illuminates when HSMC 12 V power is active D23 HSMC PSNT n illuminates when HSMC Daughter Card is present D7 ULED Illuminates when the on board USB Blaster is working D6 D5 07 024 023 Figure 3 6 Status LED position 3 2 General User Input Output This section describes the user I O interface to the FPGA B User Defined Push buttons The board includes four user defined push buttons that allow users to interact with the Cyclone V GX device as shown in Figure 3 7 Each of these switches is debounced using a Schmitt Trigger circuit as indicated in Figure 3 8 The four outputs called KEY0 KEY1 KEY2 and KEY3 of the Schmitt Trigge
46. and performance levels you need for high volume applications including protocol bridging motor control drives broadcast video converter and capture cards and handheld devices The Cyclone V GX Starter Kit development board includes hardware such as Arduino Header on board USB Blaster audio and video capabilities and much more In addition an on board HSMC connector with high speed transceivers allows for an even greater array of hardware setups By leveraging all of these capabilities the Cyclone V GX Starter Kit is the perfect solution for showcasing evaluating and prototyping the true potential of the Altera Cyclone V GX FPGA The Cyclone V GX Starter Kit contains all components needed to use the board in conjunction with a computer that runs the Microsoft Windows XP or later 1 1 Package Contents Figure 1 1 shows a photograph of the Cyclone V GX Starter Kit package w e _ Cyclone V GX Starter Kit board UM Starter PAA Cyclone Starter Kit Quick Start Guide Type A to B USB Cable Power DC Adapter 12V Figure 1 1 The Cyclone V GX Starter Kit package contents www terasic com The Cyclone V GX Starter Kit package includes e TheCyclone V GX Starter Kit board e Cyclone V GX Starter Kit Quick Start Guide e 12V DC Power Supply Type A Male to Type B Male USB Cable e System CD 1 2 Cyclone V GX Starter Kit System CD The Cyclone V GX Start Kit System CD contains the documen
47. anual www terasic com 5 BASED EXAMPLE CODES 64 5 FACTORY CONFIGURATION uu u a Gaus Ce vule cv aa 64 52 LPDDR2 SDRAMRETDP 65 CHAPTER 6 NIOS II BASED EXAMPLE CODES 68 se u 68 6 2 UART TO USB CONTROL L u L L ae e aus eo oue geo coa arva e eene 71 HDMI IX eed erect ecu LII I Lc 75 6 4 TRANSCEIVER HSMC LOOPBACK TEST 83 6 5 AUDIO RECORDING AND PLAYING a nemen emen enne enne ener eese sese sese e e e e e E EPE 84 6 6 MICRO SD CARD FILE SYSTEM 87 6 7 SD CARD MUSIC PLAYER 91 2 Terasic Cyclone V GX Starter Kit User Manual www terasic com Chapter 1 Introduction The Cyclone V GX Starter Kit presents a robust hardware design platform built around the Altera Cyclone V GX FPGA which is optimized for the lowest cost and power requirement for transceiver applications with industry leading programmable logic for ultimate design flexibility With Cyclone V FPGAs you can get the power cost
48. apter 4 System Builder This chapter describes how users can create a custom design project on the board by using the Software Tool of Cyclone V GX Starter Kit C5G System Builder 4 1 Introduction The C5G System Builder is a Windows based software utility designed to assist users to create a Quartus II project for the board within minutes The generated Quartus II project files include e Quartus II Project File qpf e Quartus II Setting File qsf e Top Level Design File v e Synopsis Design Constraints file sdc e Pin Assignment Document htm By providing the above files the SoCKit System Builder prevents occurrence of situations that are prone to errors when users manually edit the top level design file or place pin assignments The common mistakes that users encounter are the following 1 Board damage due to wrong pin bank voltage assignments 2 Board malfunction caused by wrong device connections or missing pin counts for connected ends 3 Performance degeneration due to improper pin assignments 4 2 General Design Flow This section will introduce the general design flow to build a project for the development board via the SoCKit System Builder The general design flow is illustrated in Figure 4 1 Users should launch the C5G System Builder and create a new project according to their design requirements When users complete the settings the C5G System Builder will generate two major files a top leve
49. asic com HSMC CLKIN p1 HSMC CLKIN p2 HSMC CLKOUTO HSMC CLKOUT n1 HSMC CLKOUT n2 HSMC CLKOUT p1 HSMC CLKOUT p2 HSMC DO HSMC D1 HSMC D2 HSMC D3 2 SCL I2C SDA HSMC GXB RX HSMC GXB RX p1 HSMC GXB RX p2 HSMC GXB RX p3 HSMC GXB TX HSMC GXB TX p1 HSMC GXB TX p2 HSMC GXB TX p3 HSMC GXB HSMC GXB RX n1 HSMC GXB RX n2 HSMC GXB RX n3 HSMC GXB TX n0 HSMC GXB TX n1 HSMC GXB TX n2 HSMC GXB TX n3 HSMC n0 HSMC ni HSMC RX n2 HSMC RX n3 HSMC RX n4 HSMC RX n5 HSMC RX n6 HSMC RX n7 HSMC n8 Terasic Cyclone V GX Starter Kit User Manual www teresic com differential clock input LVDS RX or CMOS I O or differential clock input LVDS RX or CMOS I O or differential clock input Dedicated clock output LVDS TX or CMOS I O or differential clock input output LVDS TX or CMOS I O or differential clock input output LVDS TX or CMOS I O or differential clock input output LVDS TX or CMOS I O or differential clock input output LVDS TX or CMOS I O LVDS RX or CMOS I O LVDS TX or CMOS I O LVDS RX or CMOS I O 12 Clock I2C Data Transceiver RX bit 0 Transceiver RX bit 1 Transceiver RX bit 2 Transceiver RX bit 3 Transceiver TX bit 0 Transceiver TX bit 1 Transceiver TX bit 2 Transceiver TX bit 3 Transceiver RX bit 0 Transceiver RX bit 1 Transceiver RX bit 2 Transceiver RX bit 3 Transceiver TX bit 0 Transceiver TX bit 1 Transceiver TX bit 2 Transceiver TX bit 3 LVDS RX bit or CMOS I O
50. ates one full rate system clock 330MHz for the controller itself SuSE Memory UNIPHY AFI gt 9 Avalon 652 SDRAM 5 1 1 RZQ i KEYO CLOCK_125_p 4 p Logic i Process inso Figure 5 1 Block Diagram of the LPDDR2 SDRAM 512MB Demonstration RW test modules read and write the entire memory space of the LPDDR2 through the Avalon interface of the controller In this project the Avalon bus read write test module will first write the entire memory and then compare the read back data with the regenerated data the same sequence as the write data KEYO will trigger test control signals for the LPDDR2 and the LEDs will indicate the test results according to Table 5 1 65 Cyclone V GX Starter Kit User Manual www terasic com erasic CO Altera LPDDR2 SDRAM Controller with UniPHY To use the Altera LPDDR2 controller users need to perform three major steps 1 Create correct pin assignments for the LPDDR2 2 Setup correct parameters in LPDDR2 controller dialog 3 Perform Analysis and Synthesis by selecting from the Quartus menu Process Start Start Analysis amp Synthesis 4 Run the TCL files generated by LPDDR2 IP by selecting from the Quartus II menu Tools TCL Scripts Design Tools 64 Bit Quartus 13 0 Demonstration Source Code Project directory 56 LPDDR2 RTL Test Bit stream used 5 LPDDR2 RTL Test sof Demonstration Batch File Demo Batch File Folder
51. by the Nios II Processor instantiated in the FPGA chip The communication with the PC is done via the USB Blaster link The Nios II interprets the commands sent from the PC and performs the corresponding actions 21 Terasic Cyclone V GX Starter User Manual www terasic com www lt gt gU EU gt ADC JTAG Blaster Hardware lt gt 7 SEG Display LED Button Switch SDCard n lt 5 3 8 8 3z 3 Q n 45 Figure 2 12 block diagram of the 5 control panel 22 11 V GX Starter Kit User Manual www terasic com www terasic com Chapter 3 Using the Starter In this chapter we introduce the important components on the Cyclone V GX Starter Kit 3 1 Configuration Status and Setup The procedure of downloading a circuit from a host computer to the Cyclone V GX Starter Kit board is described in the tutorial Quartus II Introduction This tutorial can be found under the tutorials folder on the Cyclone V GX Starter Kit System CD You are encouraged to read the tutorial first and treat the information below as a short reference The Cyclone V GX Starter Kit board contains a serial configuration device that stores configuration data for the Cyclone V GX FPGA This configuration data is automatically loaded from the configuration device into the FPGA when powered on Using the Quartus II software it is possible to reconfigure the FPG
52. ce which is connected to pins on the Cyclone V GX FPGA A schematic diagram of the ADC circuitry is shown in Figure 3 28 Detailed information for using the LTC2308 is available in its datasheet which can be found on the manufacturer s website or under the Datasheets ADC folder on the Kit System CD Table 3 21 lists the ADC SPI Interface pin assignments signal names relative to the Cyclone V GX device Analog Vref NC GND VCC3P3 Arduino 1013 Arduino Reset n Arduino 1012 VCC3P3 101 1 vecs 1010 GND Arduino 109 GND Arduino 108 VCCI2 Arduino Arduino 107 Arduino_lO6 lt Analog InO Arduino_lO5 ADC_CONVST lt Analog In1 U pads Arduino 104 Analog In INTERN ADC SCK 9 Arduino_IO3 Analog In3 Arduino 102 rduino Cyclone V ADC SDO lt Analog In4 mE GX Analog In5 Arduino 101 lt Analog In ADC SDI 9 Arduino 100 lt Analog In6 Analog In7 Figure 3 28 Arduino Analog input ADC Pin Arrangement and Connections www terasic com Table 3 21 ADC SPI Interface Pin Assignments Schematic Signal Names and Functions Schematic Cyclone V GX Description Standard Signal Name Pin Number ADC_CONVST Conversion Start raro mg AB22 ADC_SCK Serial Data Clock ADC_SDI Serial Data Input FPGA to ADC 1 2 V PALA 0 ADC SDO Serial Data Out ADC to FPGA 1 2 V PIN W10 35 asic Terasic Cyclone V GX Starter Kit User Manual www terasic com Ch
53. cludes following files e Batch File for USB Blaster CSG HSMC XCVR LOOPBACK TEST bat C5G HSMC XCVR TEST sh e FPGA Configure File CSG HSMC XCVR LOOPBACK TEST sof e Nios II Program 56 HSMC XCVR TEST elf B Demonstration Setup e Make sure Quartus II and Nios II are installed on your PC e Connect Connect USB Blaster to the C5G board and install USB Blaster driver if necessary e Install the HSMC loopback daughter card on C5G board e Power on the C5G board 83 asic Terasic Cyclone V GX Starter Kit User Manual www terasic com e Execute the demo batch file C5G HSMC XCVR LOOPBACK _ TEST bat for USB Blaster II under the batch file folder CSG_HSMC_XCVR_LOOPBACK_TEST Memo batch e After Nios II program is downloaded and executed successfully a prompt message will be displayed in nios2 terminal and the program will test XCVR HSMC loopback function e LEDG 3 0 light on if XCVR HSMC loopback test pass and the nios2 terminal displays the test result every 5 seconds as shown in Figure 6 13 BE Altera Nios II EDS 13 0 gcc4 sing cable USB Blaster USB 6 device 1 instance 6x Resetting and pausing target processor OK Initializing CPU cache Cif present Downloaded 68KB in 1 35 52 3KB s gt Starting processor at address 0x000001B4 ios2 terminal connected to hardware target using JTAG UART on cable ios2 terminal USB Blaster USB 81 device 1 instance 8 ios2 terminal
54. com
55. ct directory CSG SD DEMO e Nios Eclipse 56 SD DEMONSoftware Nios Project Compilation e Before you attempt to compile the reference design under Nios II Eclipse make sure the project is cleaned first by clicking Clean from the Project menu of Nios II Eclipse Demonstration Batch File Demo Batch File Folder C5G SD DEMO demo_ batch The demo batch file includes following files e Batch File for USB Blaster C5G SD DEMO bat 89 Terasic Cyclone V GX Starter Kit User Manual www terasic com C5G_SD_DEMO sh e FPGA Configure C5SG_SD_DEMO sof e Nios Program C5G_SD_DEMO elf B Demonstration Setup e Make sure Quartus II and Nios II are installed on your e Power on the C5G board e Connect USB Blaster to the C5G board and install USB Blaster driver if necessary Execute the demo batch SD DEMO bat for USB Blaster II under the batch file folder 5 SD DEMONdemo batch e After Nios II program is downloaded and executed successfully a prompt message will be displayed in nios2 terminal e Copy test files to the root directory of the SD Card e Insert the Micro SD Card into the SD Card socket of C5G as shown in Figure 6 18 TT ER TIETETETETE Figure 6 18 Insert the Micro SD card into C5G 90 Terasic Cyclone V GX Starter Kit User Manual www terasic com e Press KEY3 of the C5G board to start reading SD Card e The program will display SD Card information
56. e are confirmed to be asserted the ISR will try to power up the encoder chip and program it to interpret the incoming video signals The HDMI encoder then will detect the video timing automatically and send out video data via the HDMI cable The monitor sense interrupt will continue to be asserted whenever the HDMI cable is connected So it is disabled in the ISR until the cable is un plugged As soon as the HDMI cable is un plugged the ISR will again be asserted by the HPD interrupt Then the monitor sense interrupt will be re enabled along with making all other necessary settings in preparation for the next time hot plug event 77 Terasic Cyclone V GX Starter Kit User Manual www terasic com B Design Tools e Quartus IT 13 0sp1 e Nios II Eclipse 13 0sp1 Demonstration Source Code e Quartus Project directory CSG_HDMI_VPG e Nios II Eclipse CSG_HDMI_VPG Software B Rebuild the Quartus II Project Launch the Quartus II 13 0sp1 program Open the project file through the drop down menu File gt Open The pre built Quartus II project file is named as C5G HDMI VPG qpf in the C5G HDMI folder Users could follow the listed approaches below to rebuild a local copy of the FPGA SRAM sof file e Launch the Qsys editor to inspect or modify the existing design When asking for the location of qsys file select the file name as CSG_QSYS qsys in the C5G_HDMI_VPG folder e If any changes were made to the design pre
57. e provided from Nios II system and the function prototype is defined in the header file io h The SD Card block implements 4 bit mode protocol for communication with SD Cards The FAT File System block implements reading function for FAT16 and FAT 32 file system Long filename is supported By calling the public FAT functions users can browse files under the root directory of the Micro SD Card Furthermore users can open a specified file and read the contents of the file The main block implements main control of this demonstration When the program is executed it detects whether an Micro SD Card is inserted If an Micro SD Card is found it will check whether the Micro SD Card is formatted as FAT file system If so it searches all files in the root directory of the FAT file system and displays their names in the nios2 terminal If a text file named test txt is found it will dump the file contents If it successfully recognizes the FAT file system it will turn on the green LED On the other hand it will turn on the red LED if it fails to parse the FAT file system or if there is no SD Card found in the SD Card socket of the C5G board If users press KEY3 of the C5G board the program will perform above process again 88 Terasic Cyclone V GX Starter Kit User Manual www terasic com Figure 6 17 Software of micro SD demonstration Design Tools e Quartus II 13 0 e Nios II Eclipse 13 0 B Demonstration Source Code e Quartus Proje
58. elf files 2 Recording process will stop if audio buffer is full 3 Playing process will stop if audio data is played completely 6 6 Micro SD Card file system read Many applications use a large external storage device such as an SD Card or CF card to store data The C5G board provides the hardware and software needed for Micro SD Card access In this demonstration we will show how to browse files stored in the root directory of an SD Card and how to read the file contents of a specific file The Micro SD Card is required to be formatted as FAT File System in advance Long file name is supported in this demonstration Figure 6 16 shows the hardware system block diagram of this demonstration The system requires a 50MHz clock provided by the board The PLL generates 100MHz clock for the Nios II processor and other controllers Four PIO pins are connected to the Micro SD Card socket SD 4 bit Mode is used to access the Micro SD Card hardware The SD 4 bit protocol and FAT File System function are all implemented by Nios II software The software is stored in the on chip memory 87 asic Terasic Cyclone V GX Starter Kit User Manual www terasic com FPGA 50 MHz 1 j9euuooJeju uigjes S 1 m Figure 6 16 Block diagram of the Micro SD demonstration Figure 6 17 shows the software stack of this demonstration The Nios PIO block provides basic IO functions to access hardware directly The functions ar
59. gn the clock is provided by the PLL block The audio controller requires the audio chip working in master mode so the serial bit BCK and the left right channel clock LRCK are provided by the audio chip Two PIO pins are connected to the I2C bus The I2C protocol is implemented by software Four PIO pins are connected to the SD Card socket SD 4 Bit Mode is used to access the SD Card and is implemented by software All of the other SOPC components in the block diagram are SOPC Builder built in components The PIO pins are also 91 Terasic Cyclone V GX Starter Kit User Manual www terasic com rasic com connected to the keys leds and switches FPGA 50 MHz Nios 11 System Intercoment Fabric PIO Micro SD Controller f OnChip k LED KEY Memory v Switch Figure 6 20 Block diagram of Micro SD music player Figure 6 21 shows the software stack of this demonstration SD 4 Bit Mode block implements the SD 4 Bit mode protocol for reading raw data from the SD Card The FAT block implements FAT16 FAT32 file system for reading wave files that is stored in the SD Card In this block only read function is implemented The WAVE Lib block implements WAVE file decoding function for extracting audio data from wave files The I2C block implements I2C protocol for configuring audio chip The Audio block implements audio FIFO checking function and audio signal sending receiving function The key and switch block acts as a contr
60. he HDMI DEMO project in the Project Explore Select Clean Project e Right click on the HDMI DEMO project in the Project Explore Select Build Project The newly built binary will be located in the HDMI VPGNSoftwareHDMI DEMO folder and named as HDMI DEMO elf You can copy it and overwrite the same binary in the demo batch Please refer to the Launching the Demonstration section for how to launch and execute the demo B Launching the Demonstration The pre built demonstration binaries are located at the C5G HDMI batch folder accompanied with a set of tools in the form of command line batch file To make a quick start users could follow the listed approaches below to configure the development board and execute the demonstration program e Connect the development board to your PC with the on board JTAG connector via the bundled USB cable e Connect the development board to the LCD monitor with the on board HDMI connector via an HDMI cable e Power on the development board e Use File Manager to locate the C5G_HDMI_VPG demo_batch folder Launch the configuration and program download process by double clicking test bat batch file This will configure the FPGA download the demo application to the board and start its execution A console terminal will be kept on the screen and the user can interact with the demo application through the console box After it s done the screen should look like the one shown
61. ided to interact with the on board HDMI encoder Following is a list of commands available for the user Note that the commands are all case sensitive Users could type h for the latest command updates that is not included in this manual Table 6 2 Command Description e Dump the first 256 bytes EDID raw data of the currently connected LCD 81 www terasic com monitor Dump the first 256 bytes EDID raw data of the currently connected LCD monitor In addition print the decoded result in a human readable format d Perform a full dump of the HDMI encoder register set Power off the HDMI encoder i Power on the HDMI encoder and initialize it in HDMI mode v Power on the HDMI encoder and initialize it DVI mode m Report currently detected VIC Video Indentification Code and mode description Note that non CEA 861 D input formats may not be reported in a fully correct way r addr Read the register value of the HDMI encoder at address addr where addr is a 2 digit hexadecimal number w addr data Write the register value given by data to the HDMI encoder at address addr where addr and data are both 2 digit hexadecimal numbers Note that addr value should be exactly given in 2 digits format such as 02 1b Oc f7 Given in less than 2 digits will cause false interpretation of the value in the following data field Following is a part of the output after issuing the e p command OO 35 1e 78 6 y
62. igure 2 2 The Control Circuit that performs the control functions is implemented in the FPGA board It communicates with the Control Panel window which is active on the host computer via the USB Blaster link The graphical interface is used to send commands to the control circuit It handles all the requests and performs data transfers between the computer and the Cyclone V Starter Kit board 7 SEG Display UART to USB HDMI HSMC USB Blaster Button Switch SD Card SRAM LPDDR2 Figure 2 2 The C5G Control Panel concept The C5G Control Panel can be used to light up LEDs change the values displayed on 7 segment monitor buttons switches status read write the SRAM and LPDDR2 Memory output HDMI TX color pattern to VGA monitor verify functionality of HSMC connector I Os communicate with PC via UART to USB interface read SD Card specification information The feature of reading writing a word or an entire file from to the Memory allows the user to develop multimedia applications Flash Audio Player Flash Picture Viewer without worrying about how to build a Memory Programmer 11 11 V GX Starter Kit User Manual www terasic com 2 2 Controlling the LEDs 7 segment Displays A simple function of the Control Panel is to allow setting the values displayed on LEDs 7 segment displays Choosing the LED tab leads to the window in Figure 2 3 Here you can directly turn the LEDs on
63. l design file v and a Quartus II setting file qsf The top level design file contains top level Verilog HDL wrapper for users to add their own 56 asic Terasic Cyclone V GX Starter Kit User Manual www terasic com design logic The Quartus II setting file contains information such as FPGA device type top level pin assignment and the I O standard for each user defined I O pin Finally the Quartus II programmer must be used to download SOF file to the development board using a JTAG interface Launch SOC Kit System Builder Create New SOC Kit System Builder Project Launch Quartus II and Open Project Add User Design Logic Generate Quartus Project and Document Compile to generate SOF Configure FPGA Figure 4 1 The general design flow of building a design 4 3 Using C5G System Builder This section provides the detailed procedures on how the C5G System Builder is used Install and launch the C5G System Builder The C5G System Builder is located in the directory Tools SystemBuilder on the Cyclone V GX Starter Kit System CD Users can copy the whole folder to a host computer without installing the utility Launch the C5G System Builder by executing the C5G SystemBuilder exe on the host computer and the GUI window will appear as shown in Figure 4 2 www terasic com r Terasic Cyclone V Starter Kit V1 0 0 System Configuration ATERA Project
64. ld in Display Modes of the HDMI TX Demonstration Pattern ID 0 Q O N Video Format 640x480 60P 720x480 60P 1024x768 60P 1280x1024 60P 1920x1080 60P 1600x1200 60P PCLK MHZ 25 27 65 108 148 5 162 In the VPG module the Altera IP PLL Reconfig is used to set up pixel frequency of corresponding mode to the Altera IP PLL The RECONFIG data for each clock frequency is originated from the PLL Controller The source of the VPG module is located at the C5G HDMI _VPGNpg_source folder 76 asic Terasic Cyclone V GX Starter Kit User Manual www terasic com Push Button FPGA PLL Reconfig Nios Softcore Reconfig PLL Reconfig Video Pattern Generator Video Video Source Selector PLL Controller HDMI_TX_INT HDMI OUT Figure 6 9 Block Diagram of the HDMI TX Demonstration A NIOS II softcore is used to execute user program and send control commands to the HDMI encoder via the I2C interface The interrupt events from the HDMI encoder are sent back to the NIOS II softcore via the HDMI TX INT signal In this demonstration the hot plug and monitor sense interrupts are enabled in the HDMI encoder ADV7513 When any of the these interrupt is asserted the corresponding ISR which is registered by the control program in the NIOS II system will check current HPD and monitor sense state reported in one of the encoder registers If both HPD and monitor sens
65. lly users need to setup S1 and S2 dip switch to off position as shown in Figure 4 5 The S1 and S2 are located in the back of the Cyclone V GX starter board www terasic com erasic Cyclone V GX Starter Kit V1 0 0 js System Configuration ANBISAZN Project Name C5G Cyclone V GX Starter Kit f iv CLOCK 7 Segment x 2 gt LEDx18 Switchx 10 i iv Button x 4 SDCARD HDMI TX I7 Audio iv SRAM b12KB LPDDR2 512MB UART to USB iv ADC 515338 I2C SMA XCVR DNI PIO Header Prefix Name D5M 5M Pixel Camera M HSMC Prefix Name Nons L Default Setting Load Setting Save Setting Generate Figure 4 5 GPIO Expansion The Name is an optional feature that denotes the pin name of the daughter card assigned in your design Users may leave this field empty B Arduino Expansion Users can connect Arduino daughter cards onto the Arduino connector located on the development board As shown in Figure 4 6 select the Arduino Digital and check the ADC item The System Builder will automatically generate the associated pin assignment including pin name pin location pin direction and I O standard Note the Arduino header does not share pin with 7 segments HEX3 and HE2 so users don t need to set S1 S2 to OFF position 60 11 V GX Starter Kit User Manual www terasic com www terasic com System
66. n headers share parts of the IO In addition GPIO share I O with 7 Segment Display Please refer to Figure 3 24 for detailed connections and block diagrams GPIO 35 0 GPIO 40 pin Expansion Header Arduino_D 13 0 Arduino Uno R2 Digital Two 8 pin Expansion Header a a HEX2_D 6 0 gem m a A D 6 0 H H Two 7 Segment Display GPIO 28 22 GPIO 35 29 Figure 3 24 Connections between FPGA GPIO Arduino and 7 Segment display share bus Now we introduce the 40 pin expansion header GPIO and Arduino Uno R2 expansion header B 40 pin Expansion Header 49 1 1 V GX Starter Kit User Manual www terasic com www The 40 pin header connects directly to 36 pins of the Cyclone V GX FPGA and also provides DC 5V VCO5 DC 3 3V VCC3P3 and two GND pins Figure 3 25 shows the I O distribution of the GPIO connector The maximum power consumption of the daughter card that connects to GPIO port is shown in Table 3 18 Table 3 19 shows all the pin assignments of the GPIO connector and Share pin GPIO JP9 GPIO 0 GPIO 1 GPIO 2 GPIO 3 GPIO 4 GPIO 5 GPIO 6 GPIO 7 GPIO 8 GPIO 9 GND GPIO 10 GPIO 11 GPIO 12 GPIO 13 GPIO 14 GPIO 15 GPIO 16 GPIO 17 GPIO 18 GPIO 19 GPIO 20 GPIO 21 GPIO 22 GPIO 23 GPIO 24
67. n mechanism which will automatically power on the encoder chip when the HDMI cable is plugged into the development board and the LCD monitor is connected and powered on at the other side of the cable If the HDMI cable is already plugged into the on board HDMI connector before powering up the development board the monitor sense signal will trigger an interrupt to power up the HDMI encoder 80 Terasic Cyclone V GX Starter Kit User Manual www terasic com www teresic com When the HDMI encoder is powered up a sample video pattern will be displayed on the LCD monitor If the cable is un plugged the HDMI encoder will power off automatically to save the power consumption If the LCD monitor didn t power up automatically when performing activities described above in this demonstration users can try to completely switch off the power of the LCD monitor and then switch on again Alternatively the user can try to unplug and then replug the HDMI cable and wait for a reasonable time before the LCD monitor complete its initialization process and start to sync with the HDMI encoder Video Pattern Switching Pressing the on board push button KEY1 can switch the current display mode alternatively between the build in formats listed in Table 6 2 The pattern displayed will be looking similar to the one shown in Figure 6 11 Figure 6 11 The Video pattern used in the HDMI TX Demonstration Command Line Interface A tiny command line interface is prov
68. nts Schematic Signal Names and Functions Schematic T Stratix V GX Pin Description VO Standard Signal Name Se rs Number _UART_TX_ __Transmit Asynchronous Data Output 2 5 V __PIN_LO UART RX Receiving Asynchronous Data Input PIN M9 35 Terasic Cyclone V GX Starter Kit User Manual www terasic com www Table 3 9 RS 232 Status LED Board Reference LED Name Description D8 TX LED when RS 232 transmit is active DD RX LED when RS 232 receiving is active 3 5 SRAM Static Random Access Memory The IS61LV25616AL SRAM Static Random Access Memory device is featured on the development board For detailed information on how to use the SRAM please refer to the datasheet which is available on the manufacturer s website or under the Datasheets SRAM folder on the Kit System CD Figure 3 15 shows the related schematics and Table 3 10 lists the SRAM pin assignments signal names relative to the Cyclone V GX device SRAM A 17 0 pO SRAM D 15 0 SRAM OE n V SRAM WE n GX SRAM LB n SRAM_UB_n Figure 3 15 Connections between the Cyclone V GX FPGA and SRAM Chip SRAM Table 3 10 SRAM Pin Assignments Schematic Signal Names and Functions Schematic mm Cyclone V GX Description Standard Signal Number SRAM_A0 Address bus PINB2 Address bus PIN B26 SRAMA2 Address bus PIN HI9 SRAM A3 Address
69. of giving the number of bytes 3 initiate the writing process click on the Write a File to Memory button 4 When the Control Panel responds with the standard Windows dialog box asking for the source file specify the desired file in the usual manner The Control Panel also supports loading files with a hex extension Files with a hex extension are ASCII text files that specify memory values using ASCII characters to represent hexadecimal values For example a file containing the line 0123456789 ABCDEF defines eight 8 bit values 01 23 45 67 89 AB CD EF These values will be loaded consecutively into the memory The Sequential Read function is used to read the contents of the LPDDR2 and fill them into a file as follows 1 Specify the starting address in the Address box 2 Specify the number of bytes to be copied into the file in the Length box If the entire contents of the LPDDR2 are to be copied which involves all 512 Mbytes then place a checkmark in the Entire Memory box 3 Press Load Memory Content to a File button 4 When the Control Panel responds with the standard Windows dialog box asking for the destination file specify the desired file in the usual manner Users can use the similar way to access the SRAM asic Terasic Cyclone V GX Starter Kit User Manual www terasic com www 2 5 SD Card The function 15 designed to read the identification and specification information of the SD Card The 4
70. ol interface of the music player system 92 Terasic Cyclone V GX Starter Kit User Manual www terasic com Figure 6 21 Software Stack of the Micro SD music player The audio chip should be configured before sending audio signal to the audio chip The main program uses I2C protocol to configure the audio chip working in master mode the audio output interface working in I2S 16 bits per channel and with sampling rate according to the wave file contents In audio playing loop the main program reads 512 byte audio data from the SD Card and then writes the data to DAC FIFO in the Audio Controller Before writing the data to the FIFO the program will verify if the FIFO is full The design also mixes the audio signal from the microphone in and line in for the Karaoke style effects by enabling the BYPASS and SITETONE functions in the audio chip AS the demonstration running users can get the status information through nios2 terminal You can enable repeat mode by turning on the switch0 you can adjust the volume by pressing keyl or key2 And also you can choice the song by pressing key0 or key3 B Design Tools e Quartus II 13 0 e Nios II Eclipse 13 0 93 Terasic Cyclone V GX Starter Kit User Manual www terasic com Demonstration Source Code e Quartus Project directory CSG SD MUSIC e Nios II Eclipse 5 SD MUSICNSoftware Nios II Project Compilation Before you attempt to compile the reference design under Nios II Eclipse make
71. on was received and sent through a UART IP Figure 6 3 shows the hardware block diagram of this demonstration The system requires a 50 MHz clock provided from the board The PLL generates a 100MHz clock for Nios II processor and the controller IP The LEDs ard controlled by the PIO IP The UART controller send and receive command data Command is sent through Putty terminal on computer 71 Terasic Cyclone V GX Starter Kit User Manual www terasic com www teresic com FPGA QSYS 50 MHz UART to USB lt gt USB Circuit Connector System Intercoment Fabric 1 On Chip Memory Figure 6 3 Block diagram of UART Control LED demonstration B Design Tools e Quartus II 13 0 e Nios II Eclipse 13 0 B Demonstration Source Code e Quartus Project directory CSG_UART e Nios II Eclipse CSG_UART Software Nios II Project Compilation Before you attempt to compile the reference design under Nios II Eclipse make sure the project is cleaned first by clicking Clean from the Project menu of Nios II Eclipse B Demonstration Batch File Demo Batch File Folder C5G UART USB LEDNdemo batch 72 11 V GX Starter Kit User Manual www terasic com www terasic com The demo batch file includes following files e Batch File for USB Blaster CSG_UART_USB_LED bat CSG_UART_USB_LED sh e FPGA Configure File CSG_UART_USB_LED sof e Nios Program C5G UART USB LED elf
72. ource code for this demonstration is provided in the C5G Default folder which also includes the necessary files for the corresponding Quartus II project The top level Verilog HDL file called C5G Default v can be used as a template for other projects because it defines ports that correspond to all of the user accessible pins on the Cyclone V FPGA 64 asic Terasic Cyclone V GX Starter Kit User Manual www terasic com B Restore Factory Configuration e Ensure that power is applied to the C5G board e Connect the supplied USB cable to the USB Blaster port on the C5G board e Configure the JTAG programming circuit by setting the RUN PROG slide switch SW 11 to the PROG position e Execute the demo batch file pof_C5G_Default bar for USB Blaster under the batch file folder C5G Default demo batch e Once the programming operation is finished set the RUN PROG slide switch back to the RUN position and then reset the board by turning the power switch off and back on this action causes the new configuration data in the EPCQ256 device to be loaded into the FPGA chip 5 2 LPDDR2 SDRAM RTL Test This demonstration presents a memory test function on the bank of LPDDR2 SDRAM on the C5G board The memory size of the LPDDR2 SDRAM bank is 512MB B Function Block Diagram Figure 5 1 shows the function block diagram of this demonstration The controller uses 125 MHz as a reference clock generates one 330 MHz clock as memory clock and gener
73. ps below to initiate the UART communication 1 Choosing the UART USB tab leads to the window in Figure 2 9 2 Plug in an USB cable from PC USB port to the USB to UART port on Cyclone GX Starter board 3 The settings are provided below in case a connection from the PC is used asic Terasic Cyclone V GX Starter Kit User Manual www terasic com www e Baud Rate 115200 e Parity Check Bit None e Data Bits 8 e Stop Bits 1 e Flow Control CTS RTS OFF 4 begin the communication enter specific letters followed by clicking Send During the communication process observe the status of the Receive terminal window to verify its operation ale Ls Lon la n DISCONNECT Figure 2 9 UART to USB Serial Communication 2 8 HDMI TX C5G Control Panel provides video pattern function that allows users to output color pattern to HDMI interfaced LCD monitor using the Cyclone V GX Starter board Follow the steps below to generate the video pattern function Note do not install HSMC loopback board while using HDMI TX function because the loopback board will inference the I2C bus of HDMI Choosing the Video tab leads to the window in Figure 2 10 asic Terasic Cyclone V GX Starter Kit User Manual www terasic com www Plug a HDMI cable to HDMI connector of the Cyclone V GX Starter board and LCD monitor The LCD monitor will display the same color pattern on the control panel window Click
74. r Manual www terasic com www Altera Nios EDS 13 0dp gcc4 ars OK Downloaded 83KB 1 05 83 0KB s Verified OK Starting processor at address 0x200201B4 nios2 terminal connected to hardware target using JTAG UART on cable nios2 terminal USB Blaster USB 0 device 1 instance 0 nios2 terminal Use the IDE stop button or Ctrl C to terminate SRAM Test CPU 100000000 HZ 9 1 times 1 10 times 2 100 times 3 1000 times 10 20 30 40 50 60 70 80 90 100 read verify 10 20 30 40 50 60 70 80 90 100 SRAM Test 1 Pass SRAM Test CPU Frequency 100000000 HZ 9 1 times 1 10 times 2 100 times 3 1000 times Figure 6 2 6 2 Uart to USB control LED Many applications need communication with computer through common port the traditional connector is RS232 which need to connect to RS232 cable But today many personal computers don t have the RS232 connector which makes it very inconvenient to develop some projects The CSG board was designed to support UART communication through USB cable The UART to USB circuit is responsible for convert the data format Developers can use a usb cable rather than a RS232 cable to make the FPGA communicate with computer In this demonstration we will show you how to control the leds by sending command on computer putty terminal The command is sent and received through usb cable to the FPGA But in FPGA the informati
75. r devices are connected directly to the Cyclone V GX FPGA Each push button switch provides a high logic level when it is not pressed and provides a low logic level when 27 Terasic Cyclone V GX Starter User Manual www terasic com depressed Since the push button switches are debounced they are appropriate for using as clocks or reset inputs in a circuit Table 3 2 lists the board references signal names and their corresponding Cyclone V GX device pin numbers KEY3 KEY1 TAAUC17 Figure 3 7 Connections between the push button and Cyclone V GX FPGA depressed released Before Schmitt Trigger Debounced lt Figure 3 8 Switch debouncing 28 Terasic Cyclone V GX Starter Kit User Manual www terasic com Table 3 2 Push button Pin Assignments Schematic Signal Names and Functions Board Schematic VO Cyclone V GX Pm Description Reference Signal Name Standard Pin Number _KEYO KEYO High Logic Level when the button is not 1 2 PIN P11 KEY1 KEY1 pressed The four push buttons KEYO 1 2 V PIN P12 KEY2 KEY2 KEY1 KEY2 and KEY3 go through the 1 2 V PIN Y15 debounce circuit 1 2 V PIN_Y16 KEY4 High Logic ji button is 3 3 V PIN AB24 B User Defined Slide Switch There are ten slide switches connected to FPGA on the board See Figure 3 9 These switches are not debounced and are assumed for use as level sensitive
76. rollers D A Mice and other pointing devices M Monitors b J amp Network adapters Ports COM amp LPT 2201 Communications Port COMI Printer Port LPT1 USB Serial Port COMS b Processors b a Sound video and game controllers p jl System devices D Universal Serial Bus controllers Figure 6 5 Check the assigned Com Port number On PC Basic options for your PuTTY session Specify the destination you want to connect to Connection type Speed 6 gt Raw Tenet Rogn C SSH Seria Figure 6 6 putty terminal setup Make sure Quartus I and Nios are installed on your 74 Terasic Cyclone V GX Starter User Manual www terasic com www terasic com e Connect USB Blaster to the C5G board and install USB Blaster driver necessary e Execute the demo batch file C5G_UART_USB_LED bat under the batch file folder C5G_USRT demo_batch nios II terminal and putty terminal running result as shown in Figure 6 6 T on cable Figure 6 7 Running result of uart_usb demo In the putty terminal type character to change the led state Type digital number to toggle the LEDR 9 0 state and type a A or n N to turn on off all LEDR 6 3 HDMI TX This section introduces a reference design for programming the on board ADV7513 HDMI encoder The entire reference is composed of
77. s completed the result is displayed in the JTAG Terminal Design Tools e Quartus II 13 0 e Nios II Eclipse 13 0 B Demonstration Source Code e Quartus Project directory CSG_SRAM e Nios II Eclipse CSG_SRAM Software B Nios II Project Compilation Before you attempt to compile the reference design under Nios II Eclipse make sure the project is cleaned first by clicking Clean from the Project menu of Nios II Eclipse 69 11 V GX Starter Kit User Manual www terasic com www terasic com B Demonstration Batch File Demo Batch File Folder C5G_SRAM demo batch The demo batch file includes following files e Batch File for USB Blaster C5G SRAM bat C5G SRAM sh e FPGA Configure File C G SRAM sof e Nios II Program C5G SRAM elf B Demonstration Setup e Make sure Quartus II and Nios II are installed on your PC e Power on the C5G board Use USB cable to connect PC and the C5G board J10 and install USB Blaster driver if necessary e Execute the demo batch file C5G SRAM bat for USB Blaster under the batch file folder C5G SRAM Memo batch e After Nios II program is downloaded and executed successfully a prompt message will be displayed in nios2 terminal e Enter a digital number to choose how many times you want to test for SRAM e The program will display progressing and result information as shown in Figure 6 2 70 asic Terasic Cyclone V GX Starter Kit Use
78. sic com Chapter 6 5 Based Example Codes This chapter provides a number of NIOS II bases example codes designed for the starter board These examples provide demonstrations of the major features which connected to FPGA interface on the board such as audio video uart to usb sdcard sram Ipddr2 adn HDMI of the associated files can be found in the Demonstrations folder on the System CD 6 1 SRAM This demonstration presents a memory test function of SRAM on the C5G board The memory size of the SRAM is 512KB System Block Diagram Figure 6 1 shows the system block diagram of this demonstration The system requires a 100 MHz clock provided from the board In the Qsys Nios II and the On Chip Memory are designed running with the 100 clock and the Nios II program is running in the on chip memory 68 asic Terasic Cyclone V GX Starter Kit User Manual www terasic com 50 MHz On Chip System Intercoment Fabric Figure 6 1 Block diagram of the SRAM Basic Demonstration The system flow is controlled by a Nios program First the Nios II program writes test patterns into the whole 512KB of SRAM Then it calls Nios II system function alt dache flush all to make sure all data has been written to SRAM Finally it reads data from SRAM for data verification The program will show progress in JTAG Terminal when writing reading data to from the SRAM When verification process i
79. ss Ctrl S to save the qsys file and then click the Generation tab to activate the Generation property page Hit the Generate button below the page to regenerate the SOPC file named as HDMI QSYS sopcinfo which would be used to update the Nios II BSP project mentioned in the next section e Switch back to the Quartus II program Select Processing gt Start Compilation from the drop down menu or hit Ctrl L to recompile the FPGA configuration file The newly built configuration file will be named as HDMI VPG sof in the C5G HDMI folder You can copy it and overwrite the same binary in the demo batch Please refer to the Launching the Demonstration section for how to launch and execute the demo B Rebuild the Nios II Project Launch the Nios II 13 0sp1 Software Build Tools for Eclipse program When the program asks for the place of workspace enter your local full path of the HDMI VPGNSoftware folder to the dialog s edit box Users could follow the approaches listed below to rebuild a local copy of the Nios II program 78 asic Terasic Cyclone V GX Starter Kit User Manual www terasic com e Right click on the HDMI_DEMO_bsp project in the Project Explore Select Nios II gt Generate BSP e Right click on the HDMI_DEMO_bsp project in the Project Explore Select Clean Project e Right click on the HDMI_DEMO_bsp project in the Project Explore Select Build Project e Right click on t
80. tation and supporting materials including the User Manual Control Panel System Builder reference designs and device datasheets User can download this System CD from the web http c5g terasic com 1 3 Layout and Components This chapter presents the features and design characteristics of the board A photograph of the board is shown in Figure 1 2 and Figure 1 3 It depicts the layout of the board and indicates the location of the connectors and key components This chapter presents the features and design characteristics of the board asic Terasic Cyclone V GX Starter Kit User Manual www terasic com www UART MIC Line Line USB Blaster to USB HDMI TX In In Out Micro SD Card DC Power Jack Power ON OFF Arduino Header 2 20 GPIO 7 Segment Display CPU Reset Switch x10 Button x4 Figure 1 2 Development Board top view 41 2 P qun Dip Switch x2 Figure 1 3 Development Board bottom view 5 Terasic Cyclone V Starter User Manual www teresic com RUN PROG SWITCH SMA_TX DNI SMA_RX DNI LPDDR2 EPCQ SRAM HSMC Connector Altera Cyclone V GX 5CGXFC5C6F27C7N LED x18 HSMC 12V Jumper www terasic com The board has many features that allow users to implement a wide range of designed circuits from simple circuits to various multimedia projects The following hardware 1 provided on the board FPGA Device
81. tics and Table 3 11 lists the LPDDR2 pin assignments signal names and functions DDR2LP CA 9 0 DDR2LP DQ 31 0 C DDR2LP 005 p 3 0 a HA DDR2LP DOS 3 0 e a DDR2LP_OCT_RZQ ANOTE RYA DDR2LP DM 3 0 LPDDR2 20 DDR2LP DMI 0 DDR2LP CK p CK Cyclone V DDR2LP CK n y DDR2LP CS n 0 Eoo DDR2LP dis i Figure 3 16 Connections between the Cyclone V GX FPGA and LPDDR2 Chip Figure 3 17 LPDDR2 and Cyclone V GX FPGA Table 3 11 LPDDR2 Memory Pin Assignments Schematic Signal Names and Functions Schematic Cyclone V GX j Description VO Standard 2 Signal Name Pin Number DDR2LP CAO Command address bus 1 2 V HSUL PIN 6 DDR2LP CA1 Command address bus 1 2 V HSUL PIN DDR2LP CA2 Command address bus 1 2 V HSUL PIN AF7 DDR2LP CA3 Command address bus 1 2 V HSUL PIN AF8 DDR2LP CA4 Command address bus 1 2 V HSUL 910 38 Terasic Cyclone V GX Starter Kit User Manual www terasic com DDR2LP_CA5 DDR2LP_CA6 DDR2LP_CA7 DDR2LP_CA8 DDR2LP_CA9 DDR2LP DQO DDR2LP DDR2LP DQ2 DDR2LP DQ3 DDR2LP DQ4 DDR2LP DQ5 DDR2LP DQ6 DDR2LP DQ7 DDR2LP DDR2LP DQ9 DDR2LP DQ10 DDR2LP_DQ11 DDR2LP DQ12 DDR2LP DQ13 DDR2LP DQ14 DDR2LP DQ15 DDR2LP DQ16 DDR2LP DQ17 DDR2LP DQ18 DDR2LP DQ19 DDR2LP DQ20 DDR2LP_DQ21 DDR2LP_DQ22 DDR2LP_DQ23 DDR2LP_DQ24 DDR2LP_DQ25 DDR2LP_DQ26 DDR2LP_DQ27 DDR2LP_DQ28 DDR2LP_DQ29 DDR2LP_DQ30 DDR2LP DQ31 DDR2LP DQS DDR2LP
82. tional feature that denotes the pin name of the daughter card assigned in your design Users may leave this field empty B Project Setting Management The C5G System Builder also provides functions to restore default setting loading a setting and saving users board configuration file shown in Figure 4 8 Users can save the current board configuration information into a cfg file and load it to the CSG System Builder 62 11 V GX Starter Kit User Manual www terasic com www terasic com Terasic Cyclone V GX Starter Kit 100 a System Configuration ATERA Project Name Cyclone V Starter Kit f iv CLOCK 7 Segment x 4 A gt V LEDx18 Switch x 10 Button x 4 50 CARD HDMI TX V Audio SI st SRAM b12KB LPDDR2 512MB iv UART to USB iv ADC 515338 12 SMA XCVR DNI GPIO Header NEN w None HSMC Prefix Name None x Default Setting Load Setting Save Setting Generate Figure 4 8 Project Settings B Project Generation When users press the Generate button the C5G System Builder will generate the corresponding Quartus II files and documents as listed in the Table 4 1 Table 4 1 The files generated by C5G System Builder No Filename Description 1 Project name gt v Top level Verilog HDL file for Quartus 2 Project name gt qpf Q
83. tons and switches are functioning correctly Thus it can be used for troubleshooting purposes 14 Terasic Cyclone V GX Starter Kit User Manual www terasic com 2 4 SRAM LPDDR2 Controller and Programmer The Control Panel can be used to write read data to from the SRAM and LPDDR2 chips on the Cyclone V GX Starter board As an example we will describe how the LPDDR2 may be accessed the same approach is used to access the SRAM Click on the Memory tab and select LPDDR2 to reach the window in Figure 2 6 06CA w asa Length EN Entire Memory DISCONNECT rDATA 0 Figure 2 6 Accessing the LPDDR2 A 16 bit word can be written into the LPDDR2 by entering the address of the desired location specifying the data to be written and pressing the Write button Contents of the location can be read by pressing the Read button Figure 2 6 depicts the result of writing the hexadecimal value 06CA into offset address 200 followed by reading the same location The Sequential Write function of the Control Panel is used to write the contents of a file into the LPDDR SDRAM as follows 1 Specify the starting address in the Address box Terasic Cyclone V GX Starter Kit User Manual www terasic com 2 Specify the number of bytes to be written in the Length box If the entire file is to be loaded then a checkmark may be placed in the File Length box instead
84. ts should be downloaded to your FPGA board before the control panel can request it to perform required tasks The program will call Quartus II tools to download the control circuit to the FPGA board through the USB Blaster USB 0 connection To activate the Control Panel perform the following steps 1 Make sure Quartus II 13 0 or a later version is installed successfully on your PC 2 Setthe RUN PROG switch to the RUN position 3 Connect the supplied USB cable to the USB Blaster port connect the 12V power supply and turn the power switch ON 4 Start the executable C5G ControlPanel exe on the host computer The Control Panel user interface shown in Figure 2 1 will appear 5 The C5G ControlPanel sof bit stream is loaded automatically as soon as the C5G ControlPanel exe is launched 6 Incase of a disconnetion click on CONNECT where the sof will be re loaded onto the board asic Terasic Cyclone V GX Starter Kit User Manual www terasic com Please note that the Control Panel will occupy the USB port until you close that port you cannot use Quartus II to download a configuration file into the FPGA until the USB port is closed 7 The Control Panel Is now ready for use expertence it by setting the ON OFF status for some LEDs and observing the result on the C5G board Figure 2 1 The C5G Control Panel 10 Terasic Cyclone V GX Starter Kit User Manual www terasic com The concept of the C5G Control Panel is illustrated F
85. uartus II Project File 3 Project name gt qsf Quartus II Setting File 4 Project name gt sdc Synopsis Design Constraints file for Quartus II 5 Project name gt htm Pin Assignment Document Users can use Quartus II software to add custom logic into the project and compile the project to generate the SRAM Object File sof 63 Terasic Cyclone V GX Starter Kit User Manual www terasic com Chapter 5 RTL Based Example Codes This chapter provides a number of RTL based example codes designed for the starter board All of the associated files can be found in the Demonstrations folder on the System CD 5 1 Factory Configuration The C5G board is shipped from the factory with a default configuration bit stream that demonstrates some of the basic features of the board The setup required for this demonstration and the locations of its files are shown below B Demonstration File Locations Project directory C5G Default e Bit stream used C5G Default sof B Demonstration Setup and Instructions Power on the C5G board e You should now be able to observe that LEDs and 7 SEGs are flashing e Press CPU RESET n to make LEDs and 7 SEGs all light on e Optionally connect a HDMI display to the HDMI connector When connected the HDMI display should show a color picture Optionally connect a powered speaker to the stereo audio out jack and press KEY I to hear a 1 kHz humming sound from the audio out port e The Verilog HDL s
86. udio signal strength Table 6 3 and Table 6 4 summarize the usage of Slide switches for configuring the audio recorder and player 84 Terasic Cyclone V GX Starter Kit User Manual www terasic com www teresic com gt m e Looe oe EL bel Record Play Signal Strength MIC Boost Record Play Duration Sample Rate Audio Source Figure 6 14 Man Machine Interface of Audio Recorder and Player Figure 6 15 shows the block diagram of the Audio Recorder and Player design There are hardware and software parts in the block diagram The software part stores the Nios II program in the on chip memory The software part is built by Eclipse in C programming language The hardware part is built by Qsys under Quartus II The hardware part includes all the other blocks The AUDIO Controller is a user defined Qsys component It is designed to send audio data to the audio chip or receive audio data from the audio chip The audio chip is programmed through I2C protocol which is implemented in C code The I2C pins from audio chip are connected to Qsys System Interconnect Fabric through PIO controllers In this example the audio chip is configured in Master Mode The audio interface is configured as I2S and 16 bit mode 18 432MHz clock generated by the PLL is connected to the MCLK XTI pin of the audio chip through the AUDIO Controller 85 11 V GX Starter Kit User Manual www terasic com Qsys

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