DNR-AO-364 Product Manual - United Electronic Industries
Contents
1. 1 2 5 10x I O Connector A 32 bit 66MHz bus 43x PGA 16 bit 1V EEPROM Buffer jOUT IN 16 5MHz max OFFSET main DAC 18 bit 10V 1MHz max offset DAC Isolated DC DC Copyright 2013 United Electronic Industries Inc Figure 1 1 Block Diagram of the AO 364 Layer The DNA DNR AO 364 Function Generator Board has four individual analog output channels seen in Figure 1 1 On the right connected to the DNA bus the main controller is field programmable and is optically isolated from each of the four channels that it manages Each channel has its own individual program mable logic controller PLC controlling the output circuitry main DAC offset DAC PGA and output buffer with two isolated power supplies per channel The main DAC 1V 16 bit steps 16 5MHz or 60 6ns update rate max is the input to a 1 2 5 10x PGA The PGA also uses for reference a 10V offset DAC 18 bit steps 1MHz update rate max The PGA output is buffered with gain of 1 2x for a 12 0 max voltage span while supplying up to 25mA load current and can be en disabled in software with impedence 10 or 150kO respectively On the DB 62 connector the buffer s output is wired to the channel s AOUT pin and the return line on the AGND pin designed to be connected by twisted pair wire For analog signals use only AOUT and AGND and not the channel s reference gr2. 2013 Tel 508 921 4600 www ueidaq com Vers 4 7 United Electronic Industries Inc Date September 2013 DNx AO 364 Chap1x fm 6 DNA DNR AO 364 Function Generator Board Chapter 1 Introduction 1 5 Specification The technical specification for the DNx AO 364 board are listed in Table 1 1 Table 1 1 DNx AO 364 Technical Specifications General Specifications Number of channels 4 independently configurable Output type Sine Square Pulse Triangle Trapezoid DC AWFG Output Harmonic Distortion 72 dB at 150 kHz 84 dB at less than 10 kHz Output range 0 to 8 48 Vrms 12 0 VDC Output drive 10 mA min Output resolution 16 bit Output slew rate 10 Volt microsecond Output DC offset 12 VDC note max output including Vout and offset is 12 VDC DC offset resolution 18 bit Output states impedance Enabled lt 1 Ohm Disabled gt 150 kOhm Frequency Specifications Output Range 1mHz to 150 kHz Output Freq Resolution 0 25 Hz approximately 19 bits Output Freq Accuracy 1 Hz or better Phase shift control Configuration Slaved relative to any channel May be slaved to channels on other DNx AO 364 boards Phase shift range resolution 0 360 lt 0 1 Duty cycle control Duty cycle range Oto 100 Duty cycle resolution 0 25 in DDS mode Sweep Control Sweep update rate 1 ms max from host PC Sweep Frequency Range Full scale 1mHz to 150 kHz any timing possible within 50 ns sam
3. any other channel on the board as well as relative to a master channel on another AO 364 series board This phase shift may be set in increments of lt 0 1 Square wave duty cycle is also programmable from 0 to 100 in 0 25 increments in DDS mode Outputs may be swept over frequency and or output voltage offset The sweep range takes advantage of the boards AWFG capability and so may be set in to output sweep function that can be created based on discrete 50 ns updates Single Ramp Freq A to Freq B and then hold at Freq B Cycle Ramp Freq A to Freq B to Freq A and hold at Freq A or Continuous Freq A to Freq B to Freq A to Freq B and so on The sweep control may be set from the host PC at update rates up to 1 kHz The board also performs as a powerful Arbitrary Waveform Generator with 60 6 ns updates The 8 Megasample AWFG memory allows the user to create almost any desired output wave shape The AWFG generator outputs swing from 12 to 12 VDC All connections are made through standard DB 62 connectors making it easy for OEMs to design custom cabling For end user applications or proof of concept OEM applications UEI also provides the easy to use DNA STP 62 screw terminal panel The DNA CBL 62 series cable connects the DNx AO 364 to the DNA STP 62 screw terminal board and is available in lengths of 1 3 5 10 and 20 feet The DNA DNR AO 364 is supported by the UEIDAQ Framework providing a simple and complete software interface
4. is also a writer object that writes data scaled to volts where the framework will perform the conversion to binary codes before sending the data to the D A converter The following sample code shows how to create a scaled writer object and write a sample create a writer and link it to the session s stream CueiAnalogScaledWriter writer session GetDataStream the buffer must be big enough to contain one value per channel double data 2 0 0 0 0 write one scan where the buffer will contain one value per channel writer WriteSingleScan data Similarly you can create a raw writer object by entering the following create a writer and link it to the session s stream CueiAnalogRawWriter writer session GetDataStream the buffer must be big enough to contain one value per channel uInti16 data 2 0x1234 0x5678 write one scan writer WriteSingleScan data 2 6 Cleaning up The session object will clean itself up when it goes out of scope or when it is the Session destroyed To reuse the object with a different set of channels or parameters you can manually clean up the session as follows clean up the session wfmSession CleanUp Copyright 2013 Tel 508 921 4600 www ueidaq com Vers 4 7 United Electronic Industries Inc Date September 2013 DNx AO 364 Chap2x fm DNA DNR AO 364 Function Generator Board Chapter 3 Programming with the Low level API Chapter 3 Programming with the
5. selected channels and enable disable outputs DqAdv364SetWF applies waveform parameters for the channel DqAdv364SetWFSweep switch waveform into sweep mode DqAdv364SetDIO set direction and source for DIO on the channel DqAdv364SetChannelP11 Calculates and sends setup values for use by on layer PLL DgAdv364SetBaseClocks overwrite automatically selected PLL frequencies for output waveforms and or retrieve true frequencies to check for tolerances Copyright 2013 United Electronic Industries Inc Vers 4 7 DNx AO 364 Chap3 fm Tel 508 921 4600 Date September 2013 www ueidaq com DNA DNR AO 364 Function Generator Board Appendix A 19 Appendix A A Accessories The following cables and STP boards are available for the AO 364 layer DNA CBL 62 This is a 62 conductor round shielded cable with 62 pin male D sub connectors on both ends It is made with round heavy shielded cable 2 5 ft 75 cm long weight of 9 49 ounces or 269 grams up to 10ft 305cm for the DNA CBL 62 10 and 20ft 610cm for the DNA CBL 62 20 DNA STP 62 The STP 62 is a Screw Terminal Panel with three 20 position terminal blocks JT1 JT2 and JT3 plus one 3 position terminal block J2 The dimensions of the STP 62 board are 4w x 3 8d x1 2h inch or 10 2 x 9 7 x 3 cm with standoffs The weight of the STP 62 board is 3 89 ounces or 110 grams DB 62 female JT3 20 position JT2 20 position JT1 20 position J2 5 position 62 pi
6. the PowerDNA I O Cube and DNx to refer to both Copyright 2013 Tel 508 921 4600 www ueidaq com Vers 4 7 United Electronic Industries Inc Date September 2013 DNx AO 364 Chap1x fm DNA DNR AO 364 Function Generator Board Chapter 1 5 Introduction 1 2 The AO 364 The DNA AO 364 and DNR AO 364 are 4 channel function generator Arbitrary Interface Waveform Generator AWFG boards designed for use in UEI s popular Cube Board and RACKtangle chassis respectively Standard sine square pulse triangle sawtooth and trapezoid waveforms at up to 150 kHz are provided or the user may create a custom waveform by taking advantage of the boards AWFG capabilities Each channel s output may be set independently of the others or may be slaved to any other channel taking advantage of the programmable phase shift functionality The DNx AO 364 provides high resolution in both its frequency output as well as voltage output settings Output Frequency may be set from 1mHz to 150 kHz with 0 25 Hz resolution and 1 0 Hz overall accuracy Output voltages may be set from 0 to 8 45 Vrms with 16 bit resolution Output DC offset may be set between 12 VDC also with 16 bit resolution Note that total output voltage selected including output voltage and offset may not exceed 12 VDC The outputs may be enabled or disabled under software control with output impedances of lt 1 Ohm or gt 150 kOhm respectively Phase is programmable 0 to 360 degrees relative to
7. to all popular Windows programming languages and DAQ applications including LabVIEW MATLAB and DasyLAB An extensive factory written software driver is also provided for all popular non Windows operating systems including Linux VXworks QNX RTX INtime and more Copyright 2013 Tel 508 921 4600 www ueidag com Vers 4 7 lined Electronic Industies oe Date September 2013 DNx AO 364 Chap1x fm DNA DNR AO 364 Function Generator Board Chapter 1 Introduction 1 3 Features The AO 364 layer has the following features e 4 independently configurable channels DC Sine Square Pulse Triangle Sawtooth Trapezoid or Arbitrary Waveform Function Generator AWFG output 0 1 to 150 kHz output frequency e 0 25 Hz output resolution Software selectable phase shift between channels Real time frequency slew sweep e 350 Vrms channel to channel isolation Weight of 136 g or 4 79 oz for DNA AO 364 817 g or 28 8 oz with Cube Tested to withstand 5g Vibration 50g Shock 40 to 85 C Temperature and Altitude up to 70000 ft or 21000 meters 1 4 Indicators A photo of the DNR AO 364 unit is illustrated below The front panel has two LED indicators e RDY indicates that the layer is receiving power and operational e STS can be set by the user using the low level framework DNR bus connector NN OO DB 62 female 62 pin I O connector The DNR AO 364 Analog Output Layer a a eee al Copyright
8. wave duty cycle is also programmable from 0 03 to 99 97 in incre ments of 1 4096 or 0 2596 in DDS mode Outputs may be swept over DDS fre quency DDS phase DAC digital out gain DAC offset value output voltage offset In Function Generator FG mode the sweep functions can operate in the following modes e Sweep F4 to Fo Single Sweep e Sweep F to Fo to Fy Single Sweep e Sweep F to Fo Continuous sweeps F4 to F gt immediate change to F4 sweep F4 to Fz and repeat e Sweep F to F5 to F4 Continuous sweeps F4 to F gt to F4 to F5 to F4 and repeat where F4 and F3 are initial and ending function parameters respectively In Arbitrary Waveform Function Generator AWFG mode the PLC reads the user generated samples from the PSRAM 4096S per channel up to 8MS in new revisions and produces an output waveform AWFG mode cannot use DDS or make use of frequency of phase sweeps for waveforms not equal to 4096 samples Sweep functions in AWFG mode can be created based on pre generated discrete samples The frequency may be set from the host PC at update rates up to 1 kHz In addition to controlling analog output lines the channel controller logic is wired to process and make use of the digital lines marked DIO0 1 CLK and TRIG Note that the digital ground reference line is GND not AGND or analog ground Each channel may be individually configured in software to have its trigger clock Source be i any another channel s CLK TRIG pi
9. 21 4600 www ueidaq com Vers 4 7 United Electronic Indusinesn Inc Date September 2013 DNx AO 364 Chap1x fm 3 DNA DNR AO 364 Function Generator Board Chapter 1 4 Introduction Manual Conventions To help you get the most out of this manual and our products please note that we use the following conventions Tips are designed to highlight quick ways to get the job done or to reveal good ideas you might not discover on your own NOTE Notes alert you to important information CAUTION Caution advises you of precautions to take to avoid injury data loss and damage to your boards or a system crash Text formatted in bold typeface generally represents text that should be entered verbatim For instance it can represent a command as in the following example You can instruct users how to run setup using a command such as setup exe Text formatted in ixed typeface generally represents source code or other text that should be entered verbadim into the source code initialization or other file Examples of Manual Conventions Before plugging any I O connector into the Cube or RACKtangle be sure to remove power from all field wiring Failure to do so may cause severe damage to the equipment Usage of Terms Throughout this manual the term Cube refers to either a PowerDNA Cube product or to a PowerDNR RACKtangle rack mounted system whichever is applicable The term DNR is a specific reference to the RACKtangle DNA to
10. G 3 18 NC 39 GND3 60 NC 19 GND3 40 GND3 61 AGND3 20 GND3 41 RSVD 62 AOUT3 21 NC 42 NC Notes CLK n can be used as a general purpose DIO 0 signal if not used as CLK TRIG n can be used as a general purpose DIO 1 signal if not used as TRIG RSVD pins are for internal use Please do not connect to these pins Figure 1 2 Pinout Diagram of the AO 364 Layer Copyright 2013 f Tel 508 921 4600 United Electronic Industries Inc Date September 2013 www ueidaq com Vers 4 7 DNx AO 364 Chap1x fm DNA DNR AO 364 Function Generator Board Chapter 2 11 Programming with the High Level API Chapter 2 Programming with the High Level API This section describes how to control the DNx AO 364 using the UeiDaq Frame work High Level API UeiDaq Framework is object oriented and its objects can be manipulated in the same manner from different development environments such as Visual C Visual Basic or LabVIEW The following section focuses on the C API but the concept is the same no matter what programming language you use Please refer to the UeiDaq Framework User Manual for more information on use of other programming languages 2 1 Creating a The Session object controls all operations on your PowerDNx device Therefore Session the first task is to create a session object create a session object for input CUeiSession wfmSession 2 2 Configuring UeiDaq Framework uses resource strings to select which device s
11. Low level API The PowerDNA cube and PowerDNR RACKtangle and HalfRACK can be pro grammed using the low level API The low level API offers direct access to Pow erDNA DAQBios protocol and also allows you to access device registers directly However we recommend that when possible you use the UeiDaq Framework High Level API see Chapter 2 because it is easier to use You need to use the low level API only if you are using an operating system other than Windows For additional information about low level programming of the AO 364 please refer to the PowerDNA API Reference Manual document under Start Programs UEI PowerDNA Documentation Refer to the PowerDNA API Reference Manual on how to use the following low level functions of AO 364 as well as others related to cube operation Function Description DgAdv364SetConfig sets configuration for AO 364 DqAdv364SetAWF creates a new list of buffers for use with AWF generation DgAdv364SetOffsWF sets configuration for offset DAC DqAdv364WriteAWF writes waveform to AO 364 waveform buffer DqAdv364WriteOffsWF writes waveform to AO 364 waveform buffer for offset DAC DqAdv364SelectAWF Switches to new buffer with loaded AWF applies new parameters DgAdv364Write single scan function that allows to write static values to AO 364 card DqAdv364WriteChannel stops any waveform on that channel and write DC value to it DgAdv364Enable enables or disables
12. ZN United Electronic wy Industries The High Performance Alternative DNx AO 364 User Manual 4 Channel Function Generator AWFG I nterface Board for the PowerDNA Cube and PowerDNR RACKtangle Release 4 7 September 2013 PN Man DNx AO 364 913 Copyright 1998 2013 United Electronic I ndustries I nc All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form by any means electronic mechanical by photocopying recording or otherwise without prior written permission Information furnished in this manual is believed to be accurate and reliable However no responsibility is assumed for its use or for any infringement of patents or other rights of third parties that may result from its use All product names listed are trademarks or trade names of their respective companies See the UEI website for complete terms and conditions of sale http www ueidaq com cms terms and conditions Contacting United Electronic Industries Mailing Address 27 Renmar Avenue Walpole MA 02081 U S A For a list of our distributors and partners in the US and around the world please see http www ueidaq com partners Support Telephone 508 921 4600 Fax 508 668 2350 Also see the FAQs and online Live Help feature on our web site Internet Support Support support ueidag com Web Site www ueidaq com FTP Site ftp ftp ueidaq com Produc
13. ceDIO1 use channel DIO1 line for trigger UeiAOWaveformTriggerSourceSW use software trigger simultane ous only within single layer Set main DAC trigger source to DIO1 pWf mChan SetMainDACTriggerSource UeiAOWaveformTriggerSourceDIO1 Offset DAC trigger source source used to trigger a new period out of the offset DAC UeiAOWaveformOffsetTriggerSourceNone no trigger layer out puts when clock is available use with NIS clocking UeiAOWaveformOffsetTriggerSourceSYNC3 use SYNC3 line as a trigger UeiAOWaveformOffsetTriggerSourceSYNCI1 use SYNC line as a trigger UeiAOWaveformOffsetTriggerSourceALTO use channel 0 CHO TIN line for trigger needs to be connected to a source UeiAOWaveformOffsetTriggerSourceDIO1 use channel DIO1 line for trigger UeiAOWaveformOffsetTriggerSourceSW use software trigger simultaneous only within single layer Set offset DAC trigger source to DIOL pWfmChan SetOffsetDACTriggerSource UeiAOWaveformOffsetTriggerSourceDIOl 2 3 2 DC level Use the function call CreateAOChannel as follows to configure one or more Output channel s in DC output mode Configure channel 0 of an AO 364 set as device 1 for DC output wfmSession CreateAOChannel pdna 192 168 100 2 Dev0 ao0 10 0 10 0 Note that the last two parameters are presently ignored 2 4 Configuring Configure the AO 364 to run in simple timing mode the Timing configure timing of input to simple wfmSession C
14. d to time the main DAC UeiAOWaveformClockSourceSYNC2 use SYNC2 line for clock UeiAOWaveformClockSourceSYNCO use SYNCO line for clock UeiAOWaveformClockSourceALTO use layer channel zero PLL routed to Channel 0 trigger out to clock all channels UeiAOWaveformClockSourceTMR clock from internal TMRO time base UeiAOWaveformClockSourceDIOO use channel DIOO line for clock UeiAOWaveformClockSourcePLL clock from PLL UeiAOWaveformClockSourceSW DAC is clocked by software DC offset only Offset DAC clock source The source of the clock used to time the off set DAC UeiAOWaveformOffsetClockSourceDIOO use channel DIOO line for clock UeiAOWaveformOffsetClockSourceDIOI1 use channel DIO1 line for clock UeiAOWaveformOffsetClockSourceDAC main DAC clock divided is the source of offset DAC UeiAOWaveformOffsetClockSourcePLL PLL is the source of the offset DAC independent of main DAC UeiAOWaveformOffsetClockSourceSW offset DAC is clocked by software DC offset only e Main DAC clock sync Specifies where a clock signal should be routed to synchronize with other channels and or layers Route your signal out to TrgOut to synchronize multiple channels on the same AO 364 Route your signal out to the Sync lines to synchronize multiple AO 364s Only valid for channel 0 on AO 364 UeiAOWaveformClockRouteNone No sync routing UeiAOWaveformClockRouteDIO1ToTrgOut Route the DIO1 trigger input pin to ChannelO trigger out channel 0 only UeiAOWa
15. eating a Session sema cece eee 11 2 2 Configuring the Resource String 2 0 0 eae 11 2 3 OutpU t coe ia ha eR oie ioe bee we eta bil bald dad iba tbe oes 11 2 3 1 Waveform Output llsilllellsseeelll es 11 2 3 2 DC level Output 2000 eee 13 24 Configuring the Timing ses eereda siaaa i a RR n 13 2 5 Write Dates PPM CEU 14 2 5 1 Waveform Output 0 00000 eee 14 2 5 2 Waveform parameter sweep 0 00 00 e eee eee ee tenes 15 2 5 3 DC Level Output 2 cce etage novel dau La rA RU tak eee 17 2 6 Cleaning up the Session 0 00 eee 17 Chapter 3 Programming with the Low level API 0 20 cece eee eee eens 18 FAS Copyright 2013 Tel 508 921 4600 www ueidaq com Vers 4 7 V United Electronic Industries Inc Date September 2013 DNx AO 364 ManualTOC fm List of Figures Chapter 1 Introduction EE 1 1 1 Block Diagram of the AO 364 Layer sssssesseeeene eene 8 1 2 Pinout Diagram of the AO 364 Layer sssssesseeeeeeeeneeeeenenerennnn 10 A 1 Pinout and photo of DNA STP 62 screw terminal panel ssssssssssss 19 Copyright 2013 United Electronic Industries Inc Tel 508 921 4600 Date September 2013 www ueidaq com Vers 4 7 DNx AO 364 ManualLOF fm DNA DNR AO 364 Function Generator Board Chapter 1 Introduction Chapter 1 Introduction This document outlines the feature set and
16. erPhase the lower phase value upperPhase the upper phase value Set both the lower and upper values to 0 0 to disable any of the four parameter sweep s The following sample code shows how to sweep frequency from 10Hz to 1000Hz in 10 seconds configure writer to sweep from 10 1000 Hz in 10 sec tUeiAOWaveformSweepParameters sweepParams control UeiAOWaveformSweepUpStart sweepParams sweepParams sweepParams SweepParams sweepParams SweepParams sweepParams SweepParams sweepParams SweepParams sweepParams mode sweepTime 10 0 lowerFrequency 10 0 upperFrequency 1000 0 lowerAmplitude 0 0 upperAmplitude 0 0 lowerOffset 0 0 upperOffset 0 0 lowerPhase upperPhase UeiTimingDurationSingleShot 0 0 0 0 write waveform configuration to the hardware writer WriteSweep 1 amp sweepParams NULL SEES IONS un n c XX e e mrs rcrcme eom wu ree mH c mc m J BH ee i Tel 508 921 4600 www ueidaq com Vers 4 7 Date September 2013 DNx AO 364 Chap2x fm Copyright 2013 United Electronic Industries Inc DNA DNR AO 364 Function Generator Board Chapter 2 17 Programming with the High Level API 2 5 8 DC Level Writing data is done using writer object s There is a writer object that writes Output raw data straight to the D A converter There
17. ing Operating Parameters 6 Specifications 7 Support ii Copyright 2013 Tel 508 921 4600 www ueidaq com Vers 4 7 United elec oro Manel Date September 2013 DNx AO 364 ManuallX fm
18. n connector terminal block terminal block terminal block terminal block 22 1 20 41 61 19 40 60 SHIELD GND 62 42 21 43 23 2 44 24 E 45 25 4 46 26 a 47 EISPIESI ar 6 48 28 GND ejejeleleleleleleleleleleleleleje e e e ejejelelelelelelelelelelelelelelje e e e S ejelelelelelelelelelelelelelele e e e e w 21i i i 1 SHIELD p 1 1 0 0e e o e o e o e o o e CO 0 o o a ee02e2eeeeh eee ee 0600 0 o 077 i q 9103910102919 0101010 0 10 0 9 020 R 2 M 62 1 i 43 toJ2 toJT1 toJT2 toJT3 Figure A 1 Pinout and photo of DNA STP 62 screw terminal panel NOTE Filler plates and a rear mount cooling fan such as the DNA FANGB for 3 layer Cube or DNA FANG for 5 layer Cube or FAN 925 for RACKtangle should be used with this layer Copyright 2013 1 Tel 508 921 4600 www ueidaq com Vers 4 7 United Electronic Industries Inc Date September 2013 DNx AO 364 AppxA fm Index B J Block Diagram 8 Jumper Settings 7 C L Cable s 19 Low level API 18 Configuring the Resource String 11 Connectors and Wiring 10 Conventions 4 O Organization 3 Creating a Session 11 S H Screw Terminal Panels 19 High Level API 11 Sett
19. ns on the same AO 364 or ii the master channel i e ChO of another board where that board s trigger clock may be propagated using the internal sync bus of that Cube or RACKtangle Copyright 2013 f Tel 508 921 4600 www ueidaq com Vers 4 7 United Electronic Industies In Date September 2013 DNx AO 364 Chap1x fm DNA DNR AO 364 Function Generator Board Chapter 1 10 Introduction 1 7 Layer The following connections can be found for each channel of the AO 364 Connectors e Analog Connection Pins and Wiring AOUT analog output extending from the channel s output buffer AGND analog ground return line corresponding to AOUT Digital Connection Pins CLK TRIG the trigger clocking inputs or DIOO DIO1 digital input lines referenced to GND GND the board s DC DC ground designed for use as digital ground Figure 1 2 below illustrates the pinout of the AO 364 21 1 UE eee02e0002020000000080800080 4 e e e e e e e 0 0 0 0 0 0 0 0 6 60 0 0 0 0717 99599999999990909 9 9 62 43 Pin Signal Pin Signal Pin Signal 1 NC 22 NC 43 GNDO 2 NC 23 GNDO 44 CLKO 3 NC 24 TRIG 0 45 GNDO 4 AGNDO 25 AOUTO 46 GNDO 5 GNDO 26 RSVD 47 NC 6 NC 27 NC 48 NC 7 CLKi 28 GND1 49 TRIG 1 8 NC 29 GND1 50 NC 9 AGND1 30 AOUT 1 51 GND1 10 GND1 31 RSVD 52 GND1 11 NC 32 NC 53 GND2 12 NC 33 GND2 54 CLK2 13 NC 34 TRIG 2 55 GND2 14 AGND2 35 AOUT2 56 GND2 15 GND2 36 RSVD 57 NC 16 NC 37 NC 58 NC 17 CLK3 38 GND3 59 TRI
20. ock is created using two groups of cascaded PLLs set to the closest calculated frequency that matches the user selected output fre quency Each resulting clock edge is used to read one sample out of the 4096 sample buffer If the frequency is slower than the number of samples in the buf fer and since the type of waveform is user programmed as a sine pulse or trap ezoid the logic will create additional samples sub or super sample to create a smooth output if the frequency is faster only every few samples will be read instead Programming PLL mode for operation consumes 500 800ms which effectively limits using PLL mode from performing frequency sweep operations The Function Generator in DDS mode allows you to select an exact frequency to within 0 001Hz but has slightly more harmonics and introduces jitter into any waveform with sharp edges that becomes more evident at higher frequencies Frequency Generation mode generates sine pulse e g square trapezoid e g triangle sawtooth waveforms up to 150kHz Each channel s output may be set independently of the others or it may be slaved to another channel on the board or relative to a master channel on another AO 364 series board in the Cube or RACKtangle Slaved channels may have their timing programmed to follow a master channel s signal Slave channels can be programmed to have a relative phase shift of 0 to 360 from its master set in increments of less than 0 1 Square
21. onfigureTimingForSimpleIO Copyright 2013 i Tel 508 921 4600 www ueidaq com Vers 4 7 United Electronic Industries Inc Date September 2013 DNx AO 364 Chap2x fm DNA DNR AO 364 Function Generator Board Chapter 2 14 Programming with the High Level API 2 5 Write Data The writer object is used to output a waveform or set up a DC level signal 2 5 1 Waveform Setting waveform parameters for the AO 364 outputs is done using a writer Output object Each output channel is independent and you need to create one writer object per output channel to be able to set the waveform out of each channel in the channel list Waveform parameters are represented by a data structure or cluster under LabVIEW that contains the following fields mode The type of clock used to generate the waveform DDS allows immediate change in the waveform frequency at the expense of a higher THD PLL gives the lowest possible THD but requires 500ms to switch frequency type The shape of the waveform Sine sinusoid waveform Pulse square shape waveform with programmable duty cycle rise and fall time It can also be set to generate a trapezoid waveform Triangle Triangular shape this is a particular case of the pulse waveform with duty cycle 0 0 rise time 0 5 and fall time 0 5 Sawtooth outputs a linear ramp going from min amplitude to max amplitude Custom custom waveform uploaded by user to a 4096 sample hardware buffer xForm S
22. ound line GND which is also used as the digital input output ground Output voltages can be programmed from 0 to 8 45 Vrms with 16 bit resolution Output DC offset may be set between 12 0 VDC also with 16 bit resolution Output Frequency may be set from smaller than 1millihertz up to 150 kHz The channel s controller can be thought of as capable of 2 modes of operation Function Generator mode and Advanced Waveform Function Generator mode In Function Generator mode the PLC s internal 4096 x 16 bit sample memory provides data for direct digital synthesis DDS or a phase locked loop PLL Information is available online and in various books on the operation and advan tages and disadvantages of choosing either DDS or PLL to generate a wave form thus the capabilities of the AO 364 to generate each is explained briefly Both DSS and PLL mode have programmable voltage offset span and phase Tel 508 921 4600 www ueidaq com Vers 4 7 Date September 2013 DNx AO 364 Chap1x fm DNA DNR AO 364 Function Generator Board Chapter 1 Introduction control but frequency sweep is programmable only in DSS and not for PLL The Function Generator in PLL mode offers less harmonics and jitter deviation from the true periodicity of the waveform than DDS and PLL mode is better for waveforms with sharp edges pulse trapezoid at higher frequencies 100kHz than DDS but at low frequencies DDS is within 0 001Hz versus PLL s 0 1Hz In PLL mode the DAC cl
23. pecifies a geometrical transformation to apply to waveform None No transformation Mirror Horizontally mirror each period Invert Invert each period MirrorAndInvert Combine mirror and invert transforms frequency Specifies waveform frequency span Specifies waveform peak to peak amplitude offset Specifies waveform DC offset phase Specifies waveform phase shift relative to other channels applyTime specifies a delay to apply the new waveform on the output channel dutyCycle Applies to pulse waveform only specifies the time while the output is set in the high state as a ratio of a period use a value between 0 0 and 1 0 riseTime Applies to pulse and sawtooth waveforms only Specifies the delay for the signal to rise from low state to high state use a value between 0 0 and 1 0 fallTime Applies to pulse waveform only Specifies the delay for the signal to fall from high state to low state use a value between 0 0 1 0 Copyright 2013 Tel 508 921 4600 www ueidag com Vers 4 7 United Electronic Industies In Date September 2013 DNx AO 364 Chap2x fm create writer configure writer for sine waveform new CUeiAOWaveformWriter wfmSession GetDataStream DNA DNR AO 364 Function Generator Board Chapter 2 Programming with the High Level API 15 The following sample code shows how to create a writer object tied to channel 2 and set the waveform output to a 10kHz sine wave a write
24. ple update rate Amplitude offset rang Full scale 12 VDC Sweep modes Single Ramp Cycle Ramp Continuous Ramp Output timing resolution 60 6 ns Output waveform size 8 Megasample per channel Isolation 350 V channel to channel and channel to chassis ESD protection 15 kV Power Consumption 10 5 W should not be placed in adjacent slots Operating Temperature Tested 40 to 70 C Operating Humidity 0 95 non condensing Vibration IEC 60068 2 6 5 g 10 500 Hz sinusoidal IEC 60068 2 64 5 g rms 10 500 Hz broad band random Shock EC60068 2 27 50 g 3 ms half sine 18 shocks 6 orientations 30g 11 ms half sine 18 shocks 6 orientations Note A rear mount fan such as the DNA FAN3 for 3 layer Cube DNA FAN5 af for 5 layer Cube or FAN 925 for RACKtangle and filler plates should be used to avoid high ambient temperatures Copyright 2013 Tel 508 921 4600 www ueidaq com Vers 4 7 United Electroni Industries Ine Date September 2013 DNx AO 364 Chap1x fm 7 1 6 Device Architecture DNA DNR AO 364 Function Generator Board Chapter 1 Introduction Figure 1 1 is a block diagram of the architecture of the AO 364 layer CLK or DIOO 8MS RAM 4kS l Channel PLL Main Control meq Control y Optical Isolation TRIG or DIO1 vyv GND AGND p AOUT
25. r and link it to the session s stream port 2 2 10kHz tUeiAOWaveformParameters wfmParams wfmParams mode UeiAOWaveformModeDDS wfmParams type UeiAOWaveformTypeSine fmParams frequency 10000 0 wfmParams span 8 0 wfmParams offset 0 0 wfmParams phase 0 0 wfmParams applyTime 0 0 write waveform configuration to the hardware writer gt WriteWaveform 1 configure writer for square wave wfmParams wfmParams fmParams frequency 10000 0 wfmParams wfmParams phase z0 0 wfmParams wfmParams wfmParams wfmParams wfmParams writer gt WriteWaveform 1 2 5 2 Waveform parameter sweep amp wfmParams NULL The following code sets the waveform to a square wave instead pulse waveform with 50 duty cycle UeiAOWaveformModeDDS UeiAOWaveformTypePulse mode type 10kHz span 8 0 Ofttseb 0507 5 sharp rising edge sharp falling edge 50 duty cycle riseTime fallTime dutyCycle applyTime Den amp wfmParams NULL The AO 364 is capable of varying any combination of waveform frequency span offset and phase The sweep operation is programmed and started using the same writer object used to set the waveform shape The duration of the sweep is programmable It can either be specified in sec onds or as a number of steps to be evenly spread across a number of periods Sweep parameters are represented by a data structure or cluster under Lab VIEW that contain
26. s the following fields control Controls the sweep operation with parameters UpStart Starts sweeping parameters from the lower value to the upper value DownStart Starts sweeping parameters from the upper value to the lower value UpDownStart Starts sweeping parameters from the lower value to the upper value and back to the lower value DownUpStart Starts sweeping parameters from the upper value to the lower value and back to the upper value Stop Stops any on going sweep Copyright 2013 United Electronic Industries Inc Vers 4 7 DNx AO 364 Chap2x fm Tel 508 921 4600 Date September 2013 www ueidaq com DNA DNR AO 364 Function Generator Board Chapter 2 16 Programming with the High Level API mode the mode of the sweep Continuous automatically re start sweep operation SingleShot run sweep only once sweepTime specifies the duration of the sweep in seconds When set to 0 0 secs the numberOfPeriods stepsUp and stepsDown fields are used to set the duration numberOf Periods is an alternate way to specify the sweep duration stepsUp number of steps used to sweep from lower to upper values stepsDown number of steps used to sweep from upper to lower values lowerFrequency the lower frequency value upperFrequency the upper frequency value lowerAmplitude the lower amplitude value upperAmplitude the upper amplitude value lowerOffset the lower offset value upperOffset the upper offset value low
27. t Disclaimer WARNING DO NOT USE PRODUCTS SOLD BY UNITED ELECTRONIC INDUSTRIES INC AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS Products sold by United Electronic Industries Inc are not authorized for use as critical components in life support devices or systems A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness Any attempt to purchase any United Electronic Industries Inc product for that purpose is null and void and United Electronic Industries Inc accepts no liability whatsoever in contract tort or otherwise whether or not resulting from our or our employees negligence or failure to detect an improper purchase Specifications in this document are subject to change without notice Check with UEI for current status Table of Contents Chapter 1 Introduction 000 c cee eee 3 1 1 Organization of Manual liiis ren 3 1 2 The AO 364 Interface Board liliis en 5 1 3 Feat res uus ug lema pen een WR sand APERTE dad p dos UP e paws 6 1 4 heil cp 6 1 5 SPECHICAUON a ssa go atu eats BP AGES gales acd Word Tm 7 1 6 Device Architecture 0 2066 esse e dde bd e b mm e en E nd 8 1 7 Layer Connectors and Wiring 2 0 0 cece eh 10 Chapter 2 Programming with the High Level API 0020 ce eeeeeeeeeee 11 2 1 Cr
28. ubsystem the Resource and channels to use within a session The resource string syntax is similar to a String web URL device class gt lt IP address gt lt Device Id Subsystem Channel list For PowerDNA and RACKtangle the device class is pdna The AO 364 is pro grammed using the subsystem ao For example the following resource string selects analog output channels 0 1 2 on device 1 at IP address 192 168 100 2 pdna 192 168 100 2 Dev1 Ao0 2 as a range or as a list pdna 192 168 100 2 Dev 1 A00 1 2 2 3 Output The AO 364 can be configured for waveform output or constant DC level output 2 3 1 Waveform The AO 364 can be configured for waveform output with the Creat eAOWave Output formChannel function call as follows Configure channel 0 of an AO 364 set as device 1 session CreateAOWaveformChannel pdna 192 168 100 2 Dev1 ao0 UeiAOWaveformClockSourcePLL UeiAOWaveformOffsetClockSourceSW UeiAOWaveformClockRouteNone CreateAOWaveformChannel configures the following parameters SEE OIL H NFN ee 9c c s A J UEM a o Ge ccc c a a i Copyright 2013 Tel 508 921 4600 www ueidaq com Vers 4 7 United Electronic Indusities Ine Date September 2013 DNx AO 364 Chap2x fm DNA DNR AO 364 Function Generator Board Chapter 2 Programming with the High Level API Main DAC clock source The source of the clock use
29. use of the DNR and DNA AO 364 layer The AO 364 is a 4 channel function generator analog output module for the PowerDNA I O Cube DNA AO 364 and the DNR 1G HalfRACK and RACKtangle chassis DNR AO 364 The DNR version is identical to the DNA version except that the DNR version is designed to plug into a RACKtangle backplane instead of a Cube chassis 1 1 Organization This AO 364 User Manual is organized as follows of Manual Introduction This chapter provides an overview of DNx AO 364 function generator analog output board features device architecture connectivity and logic Programming with the High Level API This chapter provides an overview of the how to create a session configure the session and generate output on the DNx AO 364 with the UEIDAQ High level Framework API Programming with the Low Level API This chapter is an overview of low level API commands for configuring and using the AO 364 series layer Appendix A Accessories This appendix provides a list of accessories available for use with the DNx AO 364 board Index This is an alphabetical listing of the topics covered in this manual NOTE A glossary of terms used with the PowerDNA Cube Rack and layers can be viewed and or downloaded from www ueidaq com que A He B S M c HX T c 0 1G n P JO a s 1 Copyright 2013 f Tel 508 9
30. veformClockRouteDIOOToTrgOut Route the DIOO clock input pin to ChannelO trigger out channel 0 only UeiAOWaveformClockRoutePLLToTrgOut Route PLL clock to Channel trigger out channel 0 only UeiAOWaveformClockRoutePLLToSYNC2 Route PLL clock to SYNC2 channel 0 only UeiAOWaveformClockRoutePLLToSYNCO Route PLL clock to SYNCO channel 0 only In addition you can set additional parameters using the following channel object methods or a property node under LabVIEW Main DAC trigger source source used to trigger a new period out of the main DAC UeiAOWaveformTriggerSourceNone no trigger layer outputs when clock is available UeiAOWaveformTriggerSourceCHO channel 0 will deliver clock trig gered on CHO TRIGIN line UeiAOWaveformTriggerSourceSYNC3 use SYNC3 line as a trigger UeiAOWaveformTriggerSourceSYNCI use SYNC1 line as a trigger quc B PM M 1 ckyuci nr U i f P cw S me Copyright 2013 f Tel 508 921 4600 www ueidaq com Vers 4 7 United Electronic Indusinesn Inc Date September 2013 DNx AO 364 Chap2x fm DNA DNR AO 364 Function Generator Board Chapter 2 13 Programming with the High Level API UeiAOWaveformTriggerSourceALTO use channel 0 CHO TIN line for trigger needs to be connected to a source UeiAOWaveformTriggerSour
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