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1. z o u w A a o a lt E A i A lt Li Go z Fi E S s G Hi ou El M o o lt EE s w D D D D d ge pa i o s o Ha Z S a 99 DCHEMATICS LATOUL AND FLDS 9 9 3 5 5 Layout O O 9c1n O O MovLd 01n22 9 Id 6een ad vya 4 B1v siv 9v9dvi4 viv zv 9v9svz 4 1vsstyz 4 onikii ornee lt Izsdavz A dsdii ornee lt YEIN Tein Dern Ibin gern SIZN ee 6yIN H gv av 9r94re 4 vidved sr9sve 4 aaaovad otnee uIAANA BIAZZ lt Sa a aia 20 S10 9h94 L 2 siin sin gain sein Min oo mi LSIN 3 10780 979474 lt vesi 193A11 966S Wee 001 30 4 aaowaw raze lt zuisiozu 810e d 1E0 p2Q 97947L4 E ssin ezin 9rIN SIN zen ecin sein gsin Leon 4 waisvi ornee lt uv319 gadz 4 val
2. s A 8 m 4 a zj o m lt 3 s g g g s e Seel e zaji a a a e x EH s Le E G s E m Ed w l lil yA m D Ss D e z 5 z T 7 5 gt 2 9 ODGHEMALIGD LATOUL AND FLDS 1 lt E 8 lt Ge z TRE M o JE M xx o z o D gt l LG un w w n o o
3. 2 5 2 How to Compile on the Host machine with the MD96 library 1 WOOO CO CO OO OO O0 I I I cn DD D rw W yA CON LEIN ID 2 6 Example of MD96 Applications 34 2 6 1 3x3 Convolution 4 22 a 34 2 6 2 Deriche Filter 2 2 aaa a 35 2 6 3 Binocular Stereo Correlation 35 3 MD96 HARDWARE SUPPORT 37 3 1 Introduction 37 3 2 Hardware Description 0 20 00 02 37 3 2 1 Data Transfers 2 aaa a 37 3 2 2 VMEbus Slave Interface 2 a 37 3 2 23 VMEbus Interruption 38 3 24 DSP Module 38 3 2 5 Internal mapping 39 3 2 6 VMEbus Mastering 39 3 2 7 Timing Philosophy 39 3 2 8 Ouck aaa 40 3 2 9 Bugs or things which can be better 40 3 2 10 Hardware Bugs 40 3 3 Software Description 40 3 3 1 Detail of the address decoder logic 40 3 3 2 DSP Mapping View 41 3 3 3 VMEbus Mapping View 41 3 4 Reserved memory space description 47 3 4 1 For the X Data memory field 47 3
4. 92 GHAPFLER 9 MDJ0 HA RDVWVARE SUFFURL 4 sadada AAA RAA JI 9 9 ODGHEMALIGD LAYUUL AND FLDS 3 5 3 DSP Module 1 2 v A s 9 L 8 Tas EA ef ov o ova oN kosa azis aay 77 ra om asa PEE EH a E 77 Fa Se rosa rea mas HES VINI PR ME Visa HE sa F baa sea ao Ri wa Esi sou Ge You E PETT DG ER sie HS poom E vee bog E ve adea gS sepa ds 3 d EB po ar 988 8 Waa 119 968 ose ES E ZE Zg ves aae pae res Ze sie Tid wa me Pari wa QE zeen wa we pi ma be S SA A EAG Sia Se pe arr due osa L mo EH Dreck se aasa TAL Ei Ver are win Ze zg iji JHW iVd IDA WAY Lem TTT Fo Ze mo TEEST je M lt 87 gt 1 EE H H lt 32 gt 0 s EE a ZE WEPT je Hee A EE eme EEST mapa an
5. oo jr evr LT rene SOOOOOOKO Preserved 0 0 0 0 0 0 0 How to address the MD96 board You have to sum the different offsets concerning the register or the memory you want access As Example To access the BCR from the VMEbus BASE ADDRESS 110000 To access the ICS register of DSP 3 from the VMEbus BASE ADDRESS 138000 80 To access the beginning of the Communication memory from the VMEbus BASE ADDRESS 0 To access the BCSR from one DSP 10005000 To access the SEM register of DSP 1 from one other DSP 10006000 24 To access the beginning of the Communication Memory from one DSP 800 BE CAREFUL you can not access except during Boot the beginning of the Communication memory because the address 0 concerns the internal memory of the DSP Note about Broadcast Capability It is sometimes necessary to load the same data to severals MD96 The VMEbus interface supports the Broadcast of data write cycles only for some or for all the boards in VMEbus One Broadcast address is associated to this type of transfer 2 9 DUL I WARE DEC LION do The board address has 11 bits For a group of boards which are interested by Broadcast transfers there are some conditions The boards must have the same Broadcast address so they must have the same address bits A31 to A24 That means that only 7 boards can be interested by the same Broadcast transfer For the last address bit A23 to A21
6. Return OK or ERROR int iovme_read VmeMode address_dsp data_type address_vme size int VmeMode address_dsp data_type address_vme size gt It is used to transfer data on the VME bus without open_vme Read size data with format data type from VME address address vme to DSP address address dsp Return OK or ERROR int iovme read short address gt It is used to transfer data on the VME bus Must be used after open vme in VmeMode SHO NON PRI ACC or SHO SUP VIS ACC Read data at VME address address Return the value void iovme transfer address dsp data type address vme size rw int address dsp int data type int address vme int size int rw gt It is used to transfer data on the VME bus Must be used after open vme If rw READ read size data with format data type from VME address address_vme to DSP address address dsp If rw WRITE write size data from DSP address address dsp to VME address address dsp with format data type int iovme write VmeMode address dsp data type address vme size int VmeMode address dsp data type address vme size gt It is used to transfer data on the VME bus without open vme Write size data from DSP address address dsp to VME address address dsp with format data type Return OK or ERROR void iovme write short address value 2 4 MD30 ON BVARD LIBRARY Zi gt It is used to transfer data on the VME bus Mu
7. c HEXFILE cmd ITOOLS form96k HEXFILE ab ITOOLS gsmap HEXFILE ab o ITOOLS symlist HEXFILE ab o MYMD96 mem HEXFILE clean bin rm f CFILES c 01 HEXFILE ai HEXFILE ab HEXFILE s 2 3 4 Some C optimizations Some C instructions are better optimized when you take into account of some simple rules 2 4 MD30 ON BVARD LIBRARY e For a FOR loop the DSP96002 has a Hardware Do Loop which is twice better than a standard FOR with a register incremented and compared to a fixed value The Compiler uses the best solution only then the code in the FOR loop is subroutineless e For some very critical functions you would better extract the parameters of all the function and force the Compiler to place this code or these parameters internally The DSP96002 has some on chip memory which is more efficient 4 The DSP96002 has a Floating point ALU thus can do floating point operations at the rate of integer operations 2 4 MD96 On Board Library All these functions allow a high level communication between the four DSP96002 in a MD96 board or between a DSP96002 and the VMEbus 2 4 1 VMEbus Access Using Core Access These functions are used by the DSP to access the VMEbus VMEbus Acces Control Release 1 0 Function with open close iovme open Open the VMEbus connection iovme write short Read a short iovme read short Write a short iovme transfer Read or write data iovme close Clo
8. PR 000 3ff ROM XR 400 7ff ROM YR 400 7ff ROM COMMANDES RESERVE Memory areas reserved for hardware and software reasons PROGRAM reserve pi 000 to 200 Boot Program reserve pa 000 to 800 Internal Memory reserve pa after 40000 Memory Max Size 256Kx32 reserve pb before 2003C000 Reserved for Data reserve pb after 20040000 Memory Max Size 256Kx32 DATA X ET Y reserve xi 00 to 10 For Boot Program reserve yi 00 to 10 For Boot Program reserve xa 000 to ffffffff No XA reserve ya 000 to 800 ROM sin and cos reserve ya after 40800 Memory Max Size 256Kx32 reserve xb 000 to ffffffff No XB reserve yb before 20000000 Beginning of YB reserve yb after 2007C000 V Memory Max size 512Kx32 reserve xr 0 to ffffffff reserve yr 0 to ffffffff reserve pr 0 to ffffffff COMMANDES MEMORY Program Start locate init PB b 2003C000 COMMANDES LOCATE INTERNAL PROGRAM PI Si Interruption locate Sirga P i 00000200 locate libcode P i after 00000200 INTERNAL DATA XI YI et LI Data initialisee long 64 bits locate ildata_L i after 00000010 Data non
9. the VMEbus line BBSY shows that the MD96 owns the VMEbus The DSP96002 has only to pool this bit in the BCSR register and if it is asserted to access the VMEbus To perform a standard VMEbus access AS DS0 and DS1 are driven 40 ns after the busses That the second job of the PLD VMETIMING and the Delay Line chip When writing the data and address busses are latched into the buffers then TA is asserted To avoid two consecutive DSP accesses TA remains high active low until the end of the transfer When reading the addresses are latched and TA is asserted when the VMEbus DTACK is asserted 3 2 7 Timing Philosophy VMEbus View The transfer is between the VMEbus and an object which can be the Communication Memory or a register or the Host interface of one DSP The philosophy is e The addresses or the data need about 10 ns to go though the input buffers where they are latched Then it takes 30 ns after having set all the control lines to write the data into the object or to be able to read a data from the object 30 ns is the slowest time and represents a security time to access to 25ns memories That means that for slower communication memory for instance 70ns we have to change the 100ns delay line chip by a slower one for instance 300ns When reading data need 10 ns to go from the object to the output buffers The PLD VMETIMING and the Delay Line chip are in charge of those timings AU GHAPFLER 9 MUJO HANUWANE SUFFURL DS
10. there is one address for the Broadcast address and seven for the different board addresses Note that you can have more than one Broadcast group Detail of the DSP control and status registers All the board registers are mapped in the VMEbus addressing space and in the DSP addressing space so that any external board or any internal PE could use the resources shared on the common board bus and the VMEbus There are two major registers on the MD96 1 the BCR Board Control register The BCR register should be accessed in read modify write access It means that this register must be read before it is modified The read access is necessary to keep the control bit actived by another DSP or by the VMEbus 2 the BCSR Board Control and Status register The BCSR register is normally accessible in read or write access and is containing only the status bits which are read only or write only BE CAREFUL When you read the BCSR register write only bits are undefined 44 CHAPLIER 9 The active low bits are noted with a star Board Control Register BCR The control bit location of the BCR is the following All these bits are Read Write Reset State bit index BCR definition 7 TVECTORT 17 General RESET FJ 1 OnCE RESET D DSPIRESETF 1 1 1 X X 0 3 DSPs RESET 4 DSP RESET gt DSPIRESETT VMEbus Reguest Arbiter Lock 2 ND wj RO kal kal 24 LO DE DE
11. 1 5 3 Note about Broadcast Capability 1 5 4 Software View 1 6 Some Figures about the MD96 1 6 1 Internal Access Time 2 LA A L 1 6 2 VMEbus Access Time 1 6 3 Electrical and Mechanical Specification 164 Leds 16 5 MD96 Layout 1 7 System Integration and Communication 1 8 Future 2 MD96 SOFTWARE SUPPORT 2 1 Itroduction 2 2 Software Installation 2 3 Building an application on the MD96 2 3 1 Host to MD96 code translation 2 3 2 MD96mapping 2 3 3 How to Compile MD96 Code 2 3 4 Some C optimizations 0 0 a 2 4 MD96 On Board Library aoaaa 24 1 VMEbus Access 2 4 2 Inter DSP Communication 2 4 3 Communication between MD96 and Host 2 4 4 Inter MD96 Communication 2 4 5 High Level Functions for MD96 2 5 MD96 Host Library 2 5 1 TheLibrary
12. 75 ns 2 Note The direct link between the DSP and its Local memory gives a very efficient channel of 80 Mbytes sec 1 4 2 Common Bus Description This Common Bus provides a link between the VMEbus the DSPs and the Common memory The differents ways to achieve data transfers can be enumerated as following GHAPLER 1 MD30 LEOGHNICAL MANUAL e The VMEbus can access the the shared memory in direct addressing e The VMEbus can access the DSP Host interface which is also directly mapped It provides a way to access the Local memory of the DSPs using the DMA mode e Any DSP can access another one by addressing its Host interface e The VMEbus or any of the DSP can access the Status and Control registers of the MD96 Common Bus Arbitration The rules of arbitration of the MD96 Common bus are set to give the bus to the first bus request with a priority to VMEbus transfers This VMEbus priority is required to ensure fast VMEbus acknowledge on any data transfer avoiding spurious VMEbus timeout But the Common bus is locked until the master releases it In case of simultaneous requests the priority given by the arbiter is first the VMEbus then DSP1 then DSP2 then DSP3 and last DSP4 A special board control bit allows a DSP to lock the Common bus Read Modify Write access should be used for this bit This possibility must be used with many precaution to avoid VMEbus transfer failures Another special control bit allows the VM
13. Ragl These two bits indicate the VMEbus request level VME Rat TVMERGO VME ITO VME_IT1 VME IT2 These three bits indicate the VMEbus interruption level VMEJT2 VMEJTI VME_ITO 1 Lowest Priority 2 3 5 VMEbus Reguest when a DSP want to master the VMEbus it has to set the bit VMEbus Request The board will ask the VMEbus for the DSP The DSP has only to pool the VMEbus acknowledge bit see BCSR Table which indicates that VMEbus is available At the end of the transfer the same DSP has to set the VMEbus Reguest bit to unlock the VMEbus BE CAREFUL If you don t do that The DSP will block the MD96 because it will begin a transfer without any chance of receiving a DATCK Arbiter Lock Any DSP can lock the private bus for himself it has only to reset the Arbiter Lock bit This bit is not implemented now BE CAREFUL The same DSP has to set this bit to unlock the private bus If not you have to reset the DSP GHAPFLER 9 MUJO HANUWANE SUFFURL Board Control Status Register BCSR The control and status bit location of the BCSR is the following bit BOSH definition access mode Comment 7 0 IROB DSP1 W DSP interruption line IRQB DSP2 DSP interruption line IRQB DSP3 DSP interruption line DSP interruption line DSP interruption line DSP interruption line internal bus locker for VMEbus Memory capacity pin for Shared memory Memory capacity pi
14. The MD96 can receive 64K x 32 bits 128K x 32 bits or 256K x 32 bits size with compatible pinout The static memory configuration is automatically detected by the MD96 but several memory maps can be available using specific jumpers This flexibility allows to have cheaper MD96 if a small memory area is sufficient Most part of these Memory modules are on each Local bus then the VMEbus can not access them directly The VMEbus can access them in indirect mode the MD96 s DMA capabilities make it available This transfer is also made in parallel with core execution From the hardware point of view this solution allows the removing of a 32 bits multiplexer interface per DSP and so saves place for other devices Memory and Wait state During the Boot of the DSPs the internal registers BCRA and BCRB have to be set They indicate the number of Wait states during external accesses The SRAM modules can be 64K x32 128K x32 or 256K x32 which are memories with zip64 standard JEDEC format package The MD96 allows one Wait State on Common port and zero Wait State on Local port The next table gives more explanations For Common memory module DSP CLK Memory Access Time Wait State 33 Mz 10 Miz For DSP s Local memory modules t DSP CLK Memory Access Time Wait State 33 MHz less than 25 ns 33 MHz between 30 and 45 ns 1 33 MHz between 50 and 75 ns 2 1 40 MHz less than 20 ns 40 MHz between 25 and 45 ns 40 MHz between 50 and
15. Tow bis JA port SA0000000 SBEFEFEFF 1 o 1 x VMEbus 824 DIG high bits A port 5C0000000 5FFFFFFFF 1 1 x x mene A pon For the part Registers OnCE HOST DMA the memory mapping is COR Address ATS A1 A AB Comment ZZ 1 oo 0 o o o EEE sooo o o 0 1 DSP DMA mode E 0 USR DMA mode soos o 1 i SPA DMA mode sooo 1 0 0 BOR Register acces 0005000 ERREECHEN roa 0 S OI Debugger Register accs JJ SS O OT JT JT Dekugser ses i o o o DSP HOST Interrupt mode swo TN 0 KWA DS P2 HOST Interrupt mode soo0Aa000 1 o 1 o DSP3 HOST Interrupt mode ama 0 LL JDSPEHOST Interrupt mode soma 1 1 ET DSPI HOST Pooling mode sooo TT 0 1 is P2 HOST Pooling mode _ mam 1 1 1 o DSP HOST Pooling mode _ sooroo TT LT LL DSP OST Pooling mode When you access the HOST of one DSP you access one of the sixteen registers inside the DSP Here is the mapping of these registers opt Address AS TAI A3 TA Comment oo o o 0 0 xx soomaa Ja fo xe soos fo o i ow soc o fo Li ri x sooo fo i o o fixes sooo o 1 o xp soos TT 0 from sooo JI JI presene sooo fo fo fo fics Lamp oo sem Lampe 1 o 1 IIe soo o 1 1 Let Lamm fo fo five soo 1 1 fo ft CE Imma 1 1 1 0 preserved soonest TT preserved J 3 3 3 VMEbus
16. address dap address in the memory field mem type from the buffer beginning at the address buffer It use the DMA channel must be used for Local Memory and should not be used for Common memory Return Ok or ERROR int iodsp write com dsp number value int dsp number int value 2 4 MD30 ON BVARD LIBRARY gt This routine is used for Communication between the DSPs on a MD96 It writes the semaphore value to the DSP dsp_number dsp number must be different from the DSP running the function Return Ok or ERROR 2 4 3 Communication between MD96 and Host These functions allow you to communicate with some semaphore regardless of hardware Host Communication Release 1 0 float md96 read param float parameter number int parameter number gt This function is used for Communication between the MD96 and the Host Read the parameter parameter number Should be write by the Host parameter number should be PARAMETER 0 PARAMETER 1 Return value int md96 read parameter parameter number int parameter number gt This function is used for Communication between the MD96 and the Host Read the parameter parameter number Should be write by the Host parameter number should be PARAMETER 0 PARAMETER 1 Return value void md96 write status value int value gt This function is used for Communication between the MD96 and the Host Write value in the Status address Should be read by th
17. be too greedy in terms of memory space Only 9 Megabytes are available This chapter consists of three parts e The first one gives information about Soft installation It should be read after the Hardware Installation found in previous chapter e The second part explains how to build an application on the MD96 e The third one gives the libraries used for the MD96 It consists of one library for On Board program and another one for driving the MD96 from a Host machine 2 2 Software Installation The libraries given in the following sections depend on the hardware configuration of the system The MD96 base addresses the VMEbus interrupt level and vector and the VMEbus request level are defined in a file hard h read when libraries are compiled Here is a example of this included file These defines depend NOT on hardware configuration This driver is able to drive up to 4 MD96 define NB_BOARD_96_MAX 4 The MD96 was designed with 4 DSP define NB DSP PER BOARD 4 19 GHAPFLER 2 When using a workstation with a VMEbus all the transfers go though dev vme32d32 define BOARD 96DEVICE dev vme32d32 The MD96 is 2 mega bytes width on VMEbus define BOARD 96SIZE 2 1024 1024 MD50 0UH 1 WARE OUPPORL These defines depend on hardware configuration Just define the board physical address for the
18. by PLD BUFDIR for the drives EN and SR 3 2 2 VMEbus Slave Interface Address Decoder Lines A31 to A24 are compared with STRA31 to STRA24 in the 74FCT512 The result is DEC In the PLD DECODER The last three Address A23 to A21 are compared first to STRA23 to STRA21 and after to 0 0 0 which is the low Broadcast address for each MD96 board The jumper MOD24 allows when accepting the Address Modifier to choose between standard and extended transfers LW and Al are here to be sure that only D32 transfers are taken place 37 OO GHAPFLER 9 MUJO HANUWANE SUFFURL INT_ASK provides a acknowledge to give the interrupt vector When all those conditions are on the PLD DECODER generates the signals BRV to the PLD AR BITER or inclusive the signal Broadcast for the DTACK generation The signal DTACK_D is a security to not release BRV before the end of the transfer Arbitration At each clock rise the PLD ARBITER gives the common bus to one of the VMEbus the DSP1 the DSP2 the DSP3 and the DSP4 As input we have the five BR Bus Request which are BRV for the VMEbus and BR1 BR2 BR3 BR4 for the four DSPs To have no access conflict the PLD ARBITER controls the line BB Bus Busy which is describe in the DSP96002 User s Manuel The VMEbus can lock the Common Bus with LOCK_ARB Any DSP can do the same with BCSR_BRV DTACK Generation The DTACK line is active when e The VMEbus writes on the board the DTACK can be validat
19. gt This routine is used to initialize all the dsps in all the MD96 Boot VME interruption void md96 init com board number int board number gt This routine is used for Communication between the Host and the MD96 Initialize the Communication area void md96 irg dsp number ihichIrg int dsp number int WhichIrg gt This routine is used to interrupt the dsp dsp_number with one of its three interrupt inputs which are IRQA IRQB IRQC WhichIrg int md96_load_hex dsp_number file_name int dsp_number char file namel gt This routine is used to load a file to a dsp The file must be in hex format Return OK or ERROR int md96 load pgm dsp number file name start address int dsp number char file namel int start address gt This routine is used to load a program file to a dsp The program must be in hex format ol CGHAPLER 2 MDUs50 5 UB TWARE SDUFFURL start address is the start address of the program and is read at the end of the program file It can be used with the function run_dsp Return OK or ERROR void md96 read all dsp board number address buffer size int board number int address int buffer int size gt Used to read size data from the four DSPs Local Memory of the board board number at address to the buffer The first quater from DSP1 the second from DSP2 and so on board number should be BOARD96 1 BOARD96 2 int md96 re
20. initialisee long 64 bits locate uldata_L i after 00000010 Data initialisee data 32 bits locate idata_Y i after 00000010 Stack Area interne si petite 400 doubles voir pmain 96k locate S__STACK_LI i after 00000010 DATA IN LOCAL MEMORY YB Data non initialisee data 32 bits locate udata_Y b after 20000000 locate sdata_Y b after 20000000 locate cdata_Y b after 20000000 GHAPFLER 2 MD30 50UP 1 WARE SUFFORI locate class usep b after 20000000 locate class isep b after 20000000 DATA IN COMMON MEMORY YA Use the C compiler pragma option for this area FIN e You must compile your MD96 code This is an example of a Makefile AUTHOR Herve MATHIEU DATE 16 novembre 1992 TOPIC MAKEFILE for MD96 code H HH Notice ITOOLS amp RTLIBS are Defines for Intertools C compiler package MD96LIB is define for the MD96 On Board Library See your System Manager for these PATHs H HH HHH CFILES examplei c example2 c example3 c HEXFILE proto CCFLAGS i LDFLAGS do LDLIBRARY RTLIBS libc96k rom MD96LIB iolib hmio lib Others Libraries can be add for special systems SUFFIXES c ol c ol ITOOLS c96002 x c CCFLAGS S RTLIBS all HEXFILE hex HEXFILE hex CFILES c 01 ITOOLS llink CFILES c 01 LDFLAGS L LDLIBRARY
21. signals on VMEbus which are Address Strobe AS and DaTa ACKnowledge DTACK Standard VME acces READ AS 150 ns 450 ns DTACK Ons 450 ns 120 ns WRITE AS Ons 310 ns DTACK 60 n 310 ns 40 ns DMA mode or Hardware Do Loop READ AS 150 ns 240 ns DTACK Ons 240 ns 120 ns WRITE AS Ons 190 ns DTACK Ons 190 ns 40 ns 1 0 SOME FIGURES ABUUL LAHE MD50 19 1 6 3 Electrical and Mechanical Specification e This board has been designed in 1991 and routed on SUN workstations with Teradyne CAD e It is made of 8 layers in Class 4 6 for signals and two for power e The board is constituted of standard CMOS TTL compatible components only e It is implemented on a extended double Euro Card 220 mm x 233 mm and is one slot width e Maximum MD96 consumption is about 9 6 Amperes with the maximum Memory Configuration CHIP CONSUMPTION mA Number on the MD96 pipo MEMORY MODULE 960 working Standard logic ee Z1 MEMORY MODULE 200 idle RE od 1 6 4 Leds There are seven leds on the MD96 The upper one is the Reset Led It indicates that at least one DSP is reseted The next one is the Slave Led and is on when the VMEbus is accessing the MD96 The third one is the Master Led and indicates that the MD96 is accessing the VMEbus The last four DSP Leds one for each DSP indicate that a DSP is reseted or that it masters the Common bus MD50 LEOHNIGAL MANUAL GHAPLER 1
22. the acknowledge transfer that means when AS and IACK_IN are released If the IACKIN IACKOUT daisy chain go in the MD96 and the MD96 has no interrupt pending the signal go though the MD96 3 2 4 DSP Module Port B The only possible transfers on this port are from the DSP to the memory so there are no conflicts and arbitration is not necessary BG grounded The local memory can be accessed by this port The 32 data and the 15 lowest addresses lines are directly connected The addresses A15 A16 A17 go though one five jumpers and though the PLD 20L8 DSP_CONTROL SO SI select P X or Y memory fields BCSR PD1 BCSR_PDO and BCSR PD11 inform the PLD DSP_CONTROL about the memory modules Each DSP can receive two memory modules of size 64K 128K or 256K All these signals are put together to select the good memory module by CS and ONE ONE is used to separate Y data field and X P field when we have only one memory module 9 4 HARDWARE DESORIF LION od An equation in the PLD DSP_CONTROL control the mapping of the memory It can be change for special applications The input R_W is the reverse of the output OE TS and BS are used for timing considerations Only TS is used if we have a 20L8 5ns PLD with 0 Wait State and TS BS is used if we have a 10ns PLD with one Wait State Port A The arbitration is made by the PLD ARBITER described before The data and address busses are connected to the common busses In the PLD MEMORY the highes
23. then you have mixed all the fields X Y P One 128Kx32 memory chip one jumper joins DSP_A15 to SRAM A15 of the Static Ram and the other one join an output of the DSP PLD to SRAM A16 thus to separate the Y field and the X P field That means the software must take care when addressing the P field and the X field Another solution is to join DSP_A16 to SRAM A16 and DSP_A15 to SRAM A15 of the Static Ram then you have mixed all the fields X Y P One 64Kx32 memory chip a jumper joins an output of the DSP PLD to SRAM A15 thus to separate the Y field and the X P field That means the software must take care when addressing the P field and the X field Another solution is to join DSP_A15 to SRAM_A15 of the Static Ram then you have mixed all the fields X Y P 12 GHAPLER 1 MPI0O LECHNICAL MANUAL The next figure shows the location of jumpers for the different configurations 3SN LON 1SVJUVOdA ycAON ley SCH cev zev Sev 92y Ley EE 62y D
24. x32 Module 00000800 0003FFFF 00000800 0003FFFF Port A First 256K x32 Module 20000000 2003F FFF 20040000 2007F FFF Port B Second 256Kx32 Module Po 20000000 2003FFFF Port B 2 3 3 How to Compile MD96 Code To compile a program you need two things a locator file and source files e You must have a locator file which indicates the mapping of your application An example of this Locator file AUTHOR Herve MATHIEU INRIA Sophia DATE fevrier 1993 TOPIC Locator File REFERENCE Intermetrics Intertools C compiler PI 0 to 400 PA 400 to 40000 max PB 20000000 to 2007FFFF XI amp YI 0 to 1FF XA amp YA 200 to 401FF without ROM XA amp YA 800 to 407FF with ROM XB amp YB 20000000 to 2007FFFF CONVENTIONS COMMANDE RESERVE I B R Zone P pi Pa pb spe pr Zone X xi xe xa xb xr Zone Y yi ye ya yb Cyr Zone X et Y li xi amp yi laa xa amp ya la le lbb xb amp yb lab xa yb lba xb amp ya 1b Default page 129 of intermetrics C cross compilator 96002 PI 000 3ff XI 000 tiff YI 000 1ff PA 000 ffffffff 2 9 BUILDING AN AFELILALIUN ON IHE MOIO XA 4200 ffffffff YA 200 ffffffff PB 000 ffffffff XB 200 ffffffff YB 200 ffffffff
25. 10 1 6 5 MD96 Layout O O 9c1n O O MovLd 01n22 9 Id 6een ad vya 4 B1v siv 9v9dvi4 viv zv 9v9svz 4 1vsstyz 4 onikii ornee lt Izsdavz A dsdii ornee lt YEIN Tein Dern Ibin gern SIZN ee 6yIN H gv av 9r94re 4 vidved sr9sve 4 aaaovad otnee uIAANA BIAZZ lt Sa a aia 20 S10 9h94 L 2 siin sin gain sein Min oo mi LSIN 3 10780 979474 lt vesi 193A11 966S Wee 001 30 4 aaowaw raze lt zuisiozu 810e d 1E0 p2Q 97947L4 E ssin ezin 9rIN SIN zen ecin sein gsin Leon 4 waisvi ornee lt uv319 gadz 4 valid miodna 8192 4 reet 4 NJB 966STVIL S gten sein esin een LEIN 22In skin al EENG IERCH K AYOWSW NOTLVYIINAWWOS ziyara L3SFY I6CSTWhL lt BET ovan srin Toi ezan Frin SE g ZHWEE OX 662S WoL i arm x K JONO 8A91 x J mmen agin MI LANUILNI DTA2Z e esin Gi HEWER erin wuu ornze WA a Ne S Lein uvdS UrAze lt a 2 ON 2209645 AAR osin UJLIBAV OIAZZ seen LILI EECHER DAI OTA22 ON 20096450 k se Ein 8 ciu19d50 818e d
26. 4 2 For the Y Data memory field 47 3 4 3 For the Common memory 48 3 5 Schematics Layout and PLDs 49 3 5 1 Hierarchical Design LI 49 3 5 2 VMEbus Interface 50 3 5 3 DSP Module 53 3 5 4 OnCE Interface 2 a 54 3 5 5 Layout 55 3 5 6 Programmed Logic Device 2 a 56 3 5 7 Integrated Circuit 56 Chapter 1 MD96 TECHNICAL MANUAL 1 1 Introduction MD96 is the name of the Multi DSP 96002 board developed in Robotvis department INRIA Sophia during ESPRIT P940 European project in 1989 The MD96 is a high integrated board using four Motorola 96002 Digital Signal Processors and interfaced with the VMEbus This document is a general overview of the MD96 its synoptic its performance and its installation guide with also an overview of the processor used Two other chapters are about the MD96 A Hardware Annexes explains in details how the MD96 works it includes the schematics and the PLDs equations A Software support gives the C functions syntax of the MD96 library These functions allows you to develop application on the MD96 it includes functions to connect the MD96 and the Host machine SUN VxWorks system and functions which are internal functions of the MD96 inter DSP
27. BCR to lock the Common bus 3 2 10 Hardware Bugs Because the DSP TA Transfer acknowledge was not synchronous latch with the DSP clock it did not work Two straps and two pins out of their support make it possible e The first one in between the pin 14 of the PLD ARBITER and the pin 1 of the PLD BUFCLK which must be out of his support e The second one in between the support pin 1 of the PLD BUFCLK and the pin 6 of the PLD BUFCLK which must be out of his support 3 3 Software Description 3 3 1 Detail of the address decoder logic From the VMEbus view the board is decoded using A21 to A31 for single board access For Broadcast accesses the addresses lines A24 to A21 are compared to the three Broadcast bits 0 0 0 Note that the addresses lines are shifted from VMEbus backplane and the DSP addresses to manage the 32 bits data transfers correctly VME A31 to VME A02 correspond to DSP_A29 to DSP_AO thus 32 bits data transfers are considered by the VMEbus world as 4 bytes increment 2 9 DUL I WARE DEC LION 41 3 3 2 DSP Mapping View The memory mapping viewed by the DSP is for high addresses Aires AST AB0 A29 AS DSP addresses Ines Port ooo sorre oo o 0 0 Shared memory Ar S10000000 S1FFFEFEF 0 o o 1 OncE HOST DMA A port S20000000 sarrrrrrr 0 f 1 Usel memory access Bon Sms 0 1 x x VMEbus AR D32 A port S80000000 S9FFFFFFF 1 0 0 x VMEbus A24 DIG
28. CLK Read the section Hardware Bugs The actual Type is mentioned in the table The PLDs have been written and compiled with ABEL 4 10 on Sun Workstation The relative documents can be send by mail or by email Refer to the address at the beginning of the document 3 5 7 Integrated Circuit The following table shows the Integrated Circuit used on the MD96 game Number Domat TIFOTSHap 74FCT827bp T4A LS996 Note Chips used in the Once interface do not appear in this table Bibliography 1 Eric Theron et Alexandre Schlayen Calcul parall le et traitement d image Multi DSP 96002 board Manuel utilisateur de programmation Matra MS2I Aout 91 2 Bernard Hotz Implementation et Evaluation d un algorithme de st r o corr lation sur dsp96002 Rapport interne CNES INRIA 1992 3 INTERMETRICS Microsystems Software Inc Intertools C Compiler Reference Manual 1992 4 INTERMETRICS Microsystems Software Inc ntertools C Compiler User s Manual 1992 5 MOTOROLA The VMEbus SPECIFICATION 1985 Revision C 1 6 MOTOROLA DSP development software 96002 media engine processor 1990 Manuel du simulateur DSP96000CLASA 7 MOTOROLA DSP96002 IEEE Floating Point Dual Port Processor User s Manual november 1990 57
29. CONTROL Most to DSP Control Parameter used by C functions 583010 SES DSPS CONTROL Host to DSP Control Parameter used by C functions 840 to 84F DSP4 CONTROL Host to DSP Control Parameter used by C functions J J ODGHEMALIGD LATOUL AND FLDS 3 5 Schematics Layout and PLDs 3 5 1 Hierarchical Design 1 D u w A a o m lt G s s ls li a g S zj 5 je j a Se ii F 5 lt z a El a lt la w ol iii o ooo go A4 EEE SEE Sep alex seen za D o GHAPLER 9 MDJ0 HA RDWVVARE SUFFURL 3 5 2 VMEbus Interface
30. DO 2 29 30 31 Bits signification e ITVECTORO MD530 HARVWARE SUFFURI Comment MEbus interrupt vector MEbus interrupt vector MEbus interrupt vector MEbus interrupt vector MEbus interrupt vector MEbus interrupt vector MEbus interrupt vector MEbus interrupt vector ddress Modifier ddress Modifier lobal board RESET Debug interface Reset Selective DSP RESET Selective DSP RESET Selective DSP RESET Selective DSP RESET Address Modifier Address Modifier Address Modifier Address Modifier Interrupt Register nterrupt Register nterrupt Register nterrupt Register evel of Reguest evel of Reguest evel of the VMEbus Interrupt evel of the VMEbus Interrupt Level of the VMEbus Interrupt AM Lock on the DSP DSP Reguest for V MEbus Common Bus Lock lt lt lt lt lt lt gt lt lt ITVECTOR7 The first 8 bits contain the VMEbus interrupt vector of the DSP board These bits must be written by the HOST processor at startup so that the interrupt control block of the board could pass this vector when a DSP interrupt is acknowledged on the VMEbus AM5 AMO and AM modifier The VMEbus modifier addresses are used when a DSP mastered the VMEbus To ensure proper coordination between the VMEbus reguests any DSP reguesting for the VMEbus MASTER access must poll the AM modifier bit before changing the address modifiers bits AM Modifier egual 1 me
31. Data program access buses ports A and B which allows for instance simultaneous access to an external data and to a program instruction The separation of data and program is really interesting in some cases when program could not be located in the internal program memory of the chip this memory is only 1K word This functionality can increase the execution speed in a 3 2 ratio The only limitation of this memory mapping is that the Common memory is a bottle neck for the four DSP Only applications with a low bandwidth on this bus can be implemented The internal program memory is left partially free for the user 512 words allowing to use it as a cache program memory for short critical routines No bootstrapping EPROM is present on the board and an Host bootstrap loading is required at startup it uses the first 512 words The external Local memory will be used for both X Y P addressing spaces The mapping of these three memory banks has some over lapping thus to optimize the flexibility of the memory That means that users have to build there software mapping during compilation Read MD96 Software Support for more explanation The DSP 96002 is able to map up to 8 memory segments by space X Y or P For each segment we choose the input output port A or B The following graph describes the segments implemented on the MD96 board Man segments Address Definition Pont X0 Y0 P0 00000800 1FFFFFFF Shared memory OnCE HOST DMA KLYL
32. EV IEY 1 5 3 Note about Broadcast Capability W W ni zl si o 3 a a LI a O O sch Leg a o x ZS pra KT x N dej a sa M K Li E Z z 2 LL o za us u u O a ESPRIT P940 INRIA MS21 MD96 4 revB 1991 za O a a gt e a a a so pa A c Es S o 319 a un D za S Ed D x gt Mi 5 Wu m Se a a 8 oO o e 2 2 2 el LN 3 2 LAI A A LAI LAI LAI ks ba a D 6 Li Li A zdj sch Kk alla EI o o a SAI s E ie le o S oO au E s Wi d z B B U210 x rd gt ol gi Ki pes LAJ gt Bi Si LN gt LN m 7 AI fs A s O gt cl Je a 2 EI a a Ob O gt 2 A 3 p CH o o ou D CH S a z a a in vo S Ce pe O Us o ra m 5 A A 9 O o 5 SEIN 0 gt AI gt a Ki N ba LAI gt a LA 2 LAI g a su CH AJ a a be m LAJ o 2 8 8 D 5 ol a a A A GC o SES S o o gt o je e e gt za amp S 8 o 20 D a a DU D i Sg ya LA D 5 5 gt 5 a 5 LANJ S aj ay 4 S 5 2 LA wo 5 2 D CO 3 E 8 8 OH U gt gt O o o H wa AI O Uj x CH Ch AN a A LN SI ts a H a O E E k R OU gt 5 Ri m za T n PL Jo D co 4 st M L ES 5 D gt LAI 5 STE 3 5 CU DU By gt w c A m Ri 4 S JI S TE x 8 D Ii mi a A Ka E U a a seen Sle oO A o Lo A a a Si bg D Fu x N a u o 5 AI b ne a 5 dis BR E E wu ut AI 5 E zl podil
33. Ebus to lock the Common bus Read Modify Write access should also be used with this bit 1 4 3 DSP Host interface The DSP can configure its external ports either as a standard addressing port master mode or as a Host interface slave mode This Aexibility allows DSP to DSP direct communication through standard or DMA mode In this case one DSP is in master mode and the other is in slave mode For VMEbus accesses the VMEbus interface is in master mode and the DSP in the slave mode The DSP Host interface configuration allows a master to access the 16 internal registers of the DSP Some compatible VMEbus registers such as interrupt vector register has been implemented by Motorola for VMEbus interface simplification 1 4 4 Slave VMEbus Interface the MD96 provides full MASTER SLAVE VMEbus interface The MD96 is mapped on the VMEbus as two Mega Bytes memory The Slave interface consists of two topics e An address decoder which decodes from A31 to A21 The MD96 accepts only A32 D32 and A24 D32 transfers e A DTACK generation which can be a standard DTACK or a Broadcast DTACK For all addresses and data we use Latch transceivers instead of State drivers this technique reduces ground bounce and buses reflectances and it is quicker A Broadcast capability writing the same data in several MD96 in one access is implemented on the MD96 A Broadcast address is fused in the PLD named DECODER and this address is Common for the MD96 includ
34. KD DMA Channels Status 500000003 500000004 50000000 to S000000 lie 500000008 500000009 50000000A 50000000 50000000C 50000000D 50000000E 50000000F 40 CHAPLIER 9 MUJO HANUWANE SUFFURL Detail of the ERROR address Bruse Name Jo Erra ai ror ised bythe kem o STAERR Stack Dror LI LI Tegal instruction EE LOL LE gt morn DSP templina Li oman O Dao 6 moser OST Error ror ise AVATA o aj tote WAA or BRROR DMA Timeout wher using the DMA Channel 29 ERROR DSP Timeout when reading the Host Interface of another DSP 0 ERRORAM Timeout when accessing the Addresses Modifier 31 ERROR VME Timeout when opening the VMEbus Connection 3 4 3 For the Common memory The following addresses are used only for some applications If not this memory field is free Address Names Comments ZZ 6502 DSP3ERROR Error Register written by the DSP and read by the host map DSPEERROR Error Register written by the DSP and read by the host Ca DSPLSTATUS Status Register written by the DSP and read by the host mar DSPZSTATUS Status Register written by the DSP and read by the host 3800 DSPESTATUS Status Register written by the DSP and read by the host 3807 DSPISTATUS Status Register written by the DSP and read by the host S810 to SELF DSPILCONTROL Host to DSP Control Parameter used by C functions S820 to SMI DSPE
35. Mapping View To obtain the correct address decoder you have to add the base address of the board which is defined with jumpers The memory mapping of the part Shared memory OnCE HOST DMA is 42 GHAPFLER 9 MUJO HANUWANE SUFFURL Offset Address VAT V AIG VAS VAN Comment somo k e Shared memory acces E sowo o o o 0 DSPT DNA mode Z LC zm o 0 0 1 DSP7DNA mode E 108000 10C000 1 10000 114000 118000 11C000 120000 CEE ns MA mode E T a T 1 1 TT DSP DNA mode o o BCR Register ace 1 JBCSR Register access o Wehagger Register as 1 Dobugeer access 0 DSP I HOST merapi mode IE DSP HOST Interrupt mode o DSP HOST Tatermupty mode 1 DSP 1 HOST interrupt mode o DSPT MOST Pooling mode IE DSP HOST Pooling mode f o S DS OST Pooling mode fs PEN OST Pooling mode When you access the HOST of one DSP you access one of the sixteen registers inside the DSP Here is the mapping of these registers ome Address VAT V AG VAS VAT Comment soo oo oo 0 0 ms Lamm o fo f o tyr mmm 0 0 1 0 fixxx w00 of UI wow TA 0000050 j a o O rer gm 1 LUesoet 0000070 o 1 1 _ _1_ freserved somo KAA 0 0 cs I 500000090 I 1 SEM o Rea reserved 128000 12C000 130000 1 134000 1 NE 0 0 KUI 0
36. N 153 Programme 4 Robotique Image et Vision MD96 A MULTI DSP96002 BOARD Herve MATHIEU mai 1993 MD96 A Multi DSP96002 BOARD Herve MATHIEU INRIA Projet Robotvis bp 93 06902 Sophia Antipolis Cedex Tel 93 65 78 36 Fax 93 65 78 45 email hervem Gsophia inria fr May 10 1993 Contents 1 MD96 TECHNICAL MANUAL 1 1 Introduction 1 2 MD96 Overview 1 3 DSP96002Implementation 1 3 1 DSP96002 Overview 1 3 2 DSP96002 Mapping 14 Description of the MD96 14 1 Memory 1 4 2 Common Bus 1 4 3 DSP Hostimmterface 1 44 Slave VMEbus Interface 1 4 5 Master VMEbus Interface 14 6 VMEbus Interrupt capability 14 7 DSP Interrupt facilities 1 48 RemoteRrReset 1 49 Use of the on chip emulator not yet implemented 1 5 Installation Guide of the MD96 1 5 1 Hardware necessitles 1 5 2 On Board Jumper Installation
37. OTs a TS Z real sd GERS E 5 7 a AA mamaaa arian WEDT H WERT zm mara 1 E masti TSI rea ano BEES SE ee SI SS Sr E TS lg Es Zo ja KHA Pa er DS Se zem Ei Ee E 2 HILDA SP ken H lt 32 gt 0 DER Ti FA wana tp Ea ee a RATE SLEJ TEOST BS IZI ZEEN wa E s e Ze Ze PCS as G EE Ze Ze Ze Kerg Ss E Ze ev TRT AET Bes sty DE EE H SLE gt V EA washa se oval sy way As ZS E SIA ny wap Ze Za TI szzrou ev EDN EDT PEET s ma H VZETI ivi DOE sn ano WAEDY ELE Us DE CNE PRG weal E ag ar weal ZS z D SE a el SEH WOODY TOHINOI 451 PEN ZE azae A ETTE Prev N wa a EN Ze a E Ze SS SI s ER RSD A SS BR Ze ZS 8 Wa OT PA 0531 use MT e AOD nza Ja JEE Roger AA TI LEBE IY ha ZAE D SE E H Idos u a MEV KAIDA hg AC ES Ge Ge wise ags y zi is A wasr aido 3 E Ea ure sj Ji a na was 82 za IRJE Ver pr EN 3 13 HINO da pris Ni 8 za ji SH tbs r zb Te rien ggg se n Han BEE ave pure Ke ag DR 282 Me me erun PZEZE ale Zoe sale eeoosese gege 10210m paje le E Ca mmm ahasa Gute Or visa Ze mz ees ou gie Lea asa vient auaste zuy SN O ee K v Saint SON Wows ayeisi00g vos EE TEE ANE VARNE 267 anma SROTSIASS 1 z v V E 9 L 8 GHAPLER 9 MDJ0 HARDVWVVARE SUFFURL 3 5 4 OnCE Interface
38. P96002 View The two major ideas are e The data are warranted at least 6 ns after TS is deasserted when the DSP 96002 is writing e There is no hold time after TS deasserted when the DSP 96002 is reading When reading there is no problem we can have always 0 wait state when writing The two PLDs interested by this are on the B port DSP_CONTROL and on the A port MEMORY and REGISTER If these PLDs are 20L8 5ns we can have 0 Wait State with the TS pulse when writing If these PLDs are 20V8 10ns we have to insert one wait state and to generate a pulse with TS and BS The TA of the DSP is asserted as soon as we know where the DSP want to go except for VMEbus read access where TA wait for the VMEbus DTACK 3 2 8 OnCE Not yet implemented 3 2 9 Bugs or things which can be better e VME A1 VME_A2 and VME A3 are used for data transfers and interrupt acknowledges These VMEbus lines should have only one load per board Each of these lines have two loads on the MD96 For the VMEbus specification rev C1 during a read transfer you must wait 25 ns after having received DTACK to latch the data The condition is not true e When the DSP 96002 reads the BCR register to modify it read modify write access this DSP should lock the common bus to be sure that no one else could change the register between the read and the write accesses The line BUSLOCK should be used for this but it is not The DSP can use the bit ARB_LOCK in the
39. PI 20000000 53FFFFFFF KIVIPI KIVIPI X1Y1PI P X6 Y6 P6 C0000000 5DFFFFFFF IP SEOOOOOOOSEFTETETE The second parameter of the addressing ports are the Wait States It depends on the memory access time and the logic between the DSP and the memory For the MD96 zero Wait State is achieve on Local port and one Wait State is necessary due to logic for Common memory accesses The number of A KOYOPo XLYLPI Ai XIV PE X4Y4P4 X55 PS X6Y6P6 KTM A 1 4 LDES5SORLEF LION OP LHE MID IO d Wait States is between 0x0 and 0xF For VMEbus accesses this parameter is not used because VMEbus is much slower than DSP and a special hardware acknowledge is used The number of Wait States is between 0x0 and 0xF 1 4 Description of the MD96 1 4 1 Memory Memory configuration Designers usually use static memory devices for real time applications These kinds of memories have the major advantage of having a very fast access time but the disadvantage of being expensive and only available with small capacities On the other hand dynamic memories have low prices ratio is 1 10 with the same memory size large capacities but are not fast enough for DSP applications The new DSP generation has been designed to accept both memories We have chosen large static memory JEDEC compatible memory modules in ZIP package offering a reasonable cost and a very compact solution It allowed to implement four PE
40. SP had asked for an interruption To disable the interruption the four bits must be set 1 4 7 DSP Interrupt facilities The VMEbus or one DSP can interrupt another DSP by three ways In fact each DSP has three input lines dedicated to these interruptions They are activated by clearing a bit in the Control register BCR Read MD96 Hardware Support 1 4 8 Remote Reset Four bits in the Control register BCR are dedicated to control the hardware input reset of each DSP When cleared the DSP concerned is reset Setting the bit allows the DSP to Boot 7 1 4 9 Use of the on chip emulator not yet implemented The DSP96002 s on chip emulation OnCE circuitry provides a means of interacting with the DSP96002 and its peripherals non intrusively so that the user may examine and change registers memory or on chip peripherals Breakpoints trace single and multiple steps functionalities are also provided The control of the four DSP units OnCE interface uses an 32 bits parallel shift register mapped in the VMEbus interface 1 5 Installation Guide of the MD96 1 5 1 Hardware necessities VMEbus rack The board is an extended VMEbus board 220x233 in millimeters which is A32 D32 or D16 Master or Slave that means that you need a VMEbus rack with a 233 millimeters width and a backplane using P1 and P2 5 DTACK daisy chain This paragraph can be skipped if Broadcast access are not used When Broadcast transfer is used a daisy chain is
41. TACKIN DTACKOUT daisy chain when OFF the board actives the DTACKIN DTACKOUT daisy chain as soon as it has finished the transfer If you don t use Broadcast transfers this jumper can be set or reset The second group concerns the DSP memory mapping There are several parameters concerning the memory mapping e Each Processor element can receive one or two modules of 64K x32 128Kx32 or 256Kx32 e The software has in charge to manage three memory fields the program field P the data field X and The data field Y e A development system like the 4 for DSP96002 can force to separate X and Y fields when computing floating point operations For each DSP96002 you have 4 hardware possibilities for the memory modules e Two memory chips one receives the X and P fields for the lower addresses and the Y field for the upper addresses The other one receives the Y field for lower addresses The jumpers join DSP A17 to SRAM_A17 DSP A16 to SRAM A16 and DSP_A15 to SRAM A15 of the Static Ram 1 9 LNSLALLA LION GUIDE OF LHE MUJO il One 256K x32 memory chip one jumper joins DSP A15 to SRAM_A15 and DSP A16 to SRAM_A16 of the Static Ram and the other one join an output of the DSPCTRL PLD to SRAM_AI17 to separate the Y field and the X P field That means the software must take care when addressing the P field and the X field Another solution is to join DSP A17 to SRAM A17 DSP_A16 to SRAM A16 and DSP_A15 to SRAM A15 of the Static Ram
42. UB TWARE SDUFFURL gt This routine is used for Communication between the DSPs on a MD96 Initialize the Communication area int iodsp read buffer dsp number dsp address mem type buffer size int dsp number int dsp address int mem type int buffer int size This routine is used to read data from one DSP to another DSP Read size data from the dsp dsp number at the dsp address dsp address in the memory field mem type to the buffer beginning at address buffer It use the DMA channel and should be used for Local Memory Return Ok or ERROR int iodsp read com dsp number int dsp number gt This routine is used for Communication between the DSPs on a MD96 Read the semaphore coming from the DSP dsp_number dsp number must be different from the DSP running the function Return value int iodsp run dsp dsp number start address with it vme int dsp number int start address int with it vme This routine is used to run a dsp Returns OK if the run has been done ERROR if not with it vme IT ON VME interrutpion at the end of the program with it vme lt IT OFF no VME interrution Return Ok or ERROR int iodsp write buffer dsp number dsp address mem type buffer size int dsp number int dsp address int mem type int buffer int size This routine is used to write data from one DSP to another DSP Write size data in the dsp dsp number memory at the dsp
43. ad buffer dsp number dsp address mem type buffer size int dsp number int dsp address int mem type int buffer int size This routine is used to read data from the MD96 to the Host Read size data from the dsp dsp number at the dsp address dsp address in the memory field mem type to the buffer beginning at address buffer It uses the DMA channel and should be used for Local Memory Return OK or ERROR void md96 read com board number com address buffer size int board number int com address int buffer l int size gt This routine is used to read size data from the address com_address in the Common memory to the buffer beginning at address buffer of the board board number It must be used only for Common memory int md96 read error dsp number int dsp number gt This routine is used for Communication between the Host and the MD96 Allow to read an error register in the Common memory Return Error value int md96 read status dsp number int dsp number gt This routine is used for Communication between the Host and the MD96 Allow to read a status register in the Common memory Return Status value 4 9 MIO HOSI LIBRARY void md96 reset all gt This routine is used to reset all the dsps for all the MD96 void md96 run board number int board number gt This routine is used to run all the dsp on a board via MD96 interrupts int md96 run dsp d
44. am hex file in a dsp Data Flow md96_write_buffer write a buffer via a DSP md96_read_buffer read a buffer via a DSP md96 write broadcast write a buffer to severals MD96 Common memory md96 read all dsp read a buffer from the four DSP of the same MD96 md96 write all dsp write a buffer in the four DSP of the same MD96 Communication md96 init com initialize the communication Host MD96 md96 write parameter write a parameter to the MD96 md96 read error read the MD96 error status md96 read status read the MD96 status Interruption md96 get it read the VME interruption status of the MD96 md96 irg active a MD96 interruption 4 9 MIO HOSI LIBRARY Common Notation gt board number select a MD96 You should use BOARD96 1 BOARD96 2 define in includemd96 h gt dap number select a DSP 96002 You should use DSP1 DSP2 DSP3 define in includemd96 h if dsp number is between DSP1 and DSP4 the dsp is in the first MD96 if dap number is between DSP5 and DSP8 the dsp is in the second MD96 And so on gt mem type means X Y or P field You should use MEM P MEM X and MEM Y define in includemd96 h void md96 get it board number WhichDSP int board number int sWhichDSP gt This routine is used to acknoledge a VME interruption WhichDSP must be a table of four integer WhichDSP i equal IT ON if DSPi had activate its interruption else IT OFF void md96 init all
45. ans that the five AM bits are busy 0 indicates that they are free The table following indicates the different Address Modifier Codes on VMEbus 2 9 DUL I WARE DEC LION 49 HEX AMS J ME AM AM AMI AM Acs UE or pt 1 1 1 1 EEE SAS ae TT Standard Supervisory program ap tt tT J Standard Supervisory data ae tT TJ Standard Nonprivileged block 1 1 Standard Nonprivileged progra Standard Nonprivileged program Standard Nonprivileged data S OT Shor Superior CIS nor Nonpriviegd Extended Supervisory block Extended Supervisory program Extended Supervisory data Extended Nonprivileged bok Extended Nonprivileged program Extended Nonprivileged dala All the other cases are Reserved or User Defined The codes accepted by the MD96 board as Slave depend of the hardware installation If MOD24 is insert only standard accesses are accepted If MOD24 is off only Extended accesses are accepted RESET Several Reset bits are available allowing to RESET any of the DSP unit RESET1 RE SET2 RESET3 RESET4 the debug interface only OnCE RESET and all the board GENERAL RESET The resets are active at level 0 IT DSPO IT_DSP3 When the DSP number 1 want to interrupt the VMEbus it resets the bit IT DSPi When the interrupter handler acknowledge the interrupt circle it read the four bits IT_DSP and knows which DSP has interrupted the VMEbus VME Rg0 VME
46. boards which are define BOARDO 96ADRESS 0x9F600000 define BOARDO_ITLEVEL 3 VMEbus interrupt level 1 define BOARDO_ITVECTOR OxEO VMEbus interrupt vector 8 define BOARDO_VMELEVEL 3 VMEbus request level O This MD96 does not exist for the VMEVME configuration but exist for another configuration ifndef VMEVME define BOARD1_96ADRESS 0x9 800000 endif define BOARD ITLEVEL 3 define BOARD1_ITVECTOR OxE1 define BOARD1_VMELEVEL 3 If this MD96 exist insert the base address here WA define BOARD2 ITLEVEL 6 define BOARD2_ITVECTOR 0x49 define BOARD2_VMELEVEL 2 If this MD96 exist insert the base address here WA define BOARD3 ITLEVEL 6 define BOARD3_ITVECTOR Ox4a define BOARD3_VMELEVEL 2 This is the Broadcast address of the MD96s Only one Broadcast address is support All the MD96 included in the Broadcast system must have the same beginning base address 0x9F define BROADCAST 0x9F000000 Refer to your System Manager for theses informations 2 3 Building an application on the MD96 2 3 1 Host to MD96 code translation 7 bits 3 present The debugging on MD96 is not very easy you must be confident with your code before proceeding to its implementation Here are some requests to take codes running on your Host machine and to run them on the MD96 The requirements for your software are 2 9 BUILDING AN APPLICATION ON LHE MD50 EI e No printf and mem
47. communication VMEbus accesses DMA transfer This chapter consists of four parts e The first one provides a general view of the board It explains the global architecture of the MD96 then a general view of the processor and some information about its implementation are given e The second one gives a full description of the board and explains the different element build around the data path on the MD96 The installation guide allows to insert the MD96 in a VMEbus system Some figures about electrical consumption mechanical and data transfer timing specifications are also given e The fourth part gives generalities about System Integration Communication and about future expansion for the MD96 The architecture of the MD96 allows a great reduction in terms of time computation in regard to a workstation if they fit these requirements e Firstly application must use the maximum of the DSP 96002 features That means to have a great amount of floating point operations to use trigonometry Look Up Table in the DSP 96002 or to accept perfectly DSP 96002 memory mapping X Y P fields e Secondly it must use the MD96 features That means to be parallelized in a small number of tasks between 4 and 16 to use the inter DSP communication not to be too greedy in terms of memory space Only 9 Megabytes are available 1 2 MD96 Overview The MD96 is VMEbus interfaced board achieving a peak processing power of 240 MFLOPS The mai
48. e In 1988 Gregory Randall INRIA Sophia did the MD56 a Multi DSP board with three Motorola DSP 56001 The experiment with the MD56 was very useful for the MD96 conception In 1990 another board with four DSP 96002 was born The architecture was modify but the experi ment was also very useful Today they are some other projects A video interface for the MD96 it could be connected on the Common bus and it could be design on a double Euro Card Another one is to do a new design with a video interface for the MD96 Wait and see lo GHAPLER 1 MD50 LEOHNIGAL MANUAL Chapter 2 MD96 SOFTWARE SUPPORT 2 1 Introduction MD96 is the name of the Multi DSP 96002 board developed in Robotvis INRIA Sophia department during ESPRIT P940 European project in 1989 The MD96 is a high integrated board using four Motorola 96002 Digital Signal Processors and interfaced with the VMEbus The architecture of the MD96 allows a great reduction in terms of time computation in regard to a workstation if they fit these requirements e Firstly application must use the maximum of the DSP 96002 features That means to have a great amount of floating point operations to use trigonometry Look Up Table in the DSP 96002 or to accept perfectly DSP 96002 memory mapping X Y P fields Secondly it must use the MD96 features That means to be parallelized in a small number of tasks between 4 and 16 to use the inter DSP communication not to
49. e Host 2 4 4 Inter MD96 Communication All these functions are running on one MD96 board and are used to access to DSP on other MD96 boards Inter MD96 Communication Release 1 0 int iomd96 dsp number its address my address size rw int dsp number int kits address my address Memory written by a DSP and read by another one to achieve synchronism between these DSPs CGHAPLER 2 MDUs50 5 UB TWARE SDUFFURL int size int rw gt This function provides some communication between two MD96 on the same VMEbus If rw READ read size data from the dsp dsp_number at address its address to the address my address If rw WRITE write size data from the address my_address to the dsp dsp_number at address its_address dap number should be DSP1 DSP2 and must be on another MD96 Return Ok or ERROR 2 4 5 High Level Functions for MD96 VMEbus interruption VMEbus Interruption Control Release 1 0 void ioit gt Use by one DSP to interrupt the VME bus 2 5 MD96 Host Library 2 5 1 The Library The name of all the functions running on the MD96 start with md96_ gt boot means to load the basic program in the dsp and to initialize it Driving Functions md96_reset_all reset all the DSPs md96_boot_all initialize all the DSPs md96_run_dsp run a dsp md96_run run the four DSPs of one board md96_load_hex load a hex file in a dsp md96_load_pgm load a progr
50. ed as soon as the address and the data are latched that means when A_CAB is asserted D_CAB is asserted at the same time e The VMEbus is reading we have to wait LAR30CLK to be asserted LAR30CLK shows that the internal transfer is finished and that the data are latched in the 74FCT646 buffers which drive those signals on the VMEbus LAR30CLK is the signal who latchs the data too When a Broadcast transfer takes place the DTACK is asserted only if the board is the last board concerned by the Broadcast transfer If the jumper STR_LAST is ON the board is the last one if not DTACKIN DTACKOUT daisy chain is activates on the first MD96 then on the second MD96 if its transfer is finished until the last MD96 jumper STR_LAST is OFF which activate the DATCK line The DTACK signal is released when all the transfer are finished that means when DS VMEbus data strobe and LAR30CLK are released 3 2 3 VMEbus Interruption A OR between the four IT_DSP of the BCR register PLD ITREGISTER generates an IT signal This signal is mixed which the three bits BCR_INT1 BCR_INT2 and BCR_INTS of the BCR which indicate the VMEbus interrupt level When the IACKIN IACKOUT daisy chain goes in the MD96 it does not propagate it but generates an INT_ASK to obtain the Common bus and to deliver the interrupt vector which is in a 74A LS996 part of the BCR register IT is released when all the IT_DSP are released like any OR INT_ASK is released at the end of
51. ed in the Broadcast system From the VMEbus point of view this is a memory window with the base address the Broadcast address and with a size of one Meg Bytes which is the maximum size of the Common memory Note that this Common address must be different than the Board base address Read Installation Guide Section for more explanation 1 4 5 Master VMEbus Interface The following two parts requires notions about VMEbus The Master interface provides 1 9 HNSLALLALION GUIDE VE LHE MD30 d e A bus reguester to issue a VMEbus reguest The MD96 board releases the bus at the end of its transfers WARNING You must be careful when using VMEbus access The VMEbus signal Bus Clear is not yet implemented that means than a VMEbus timeout will occur if the DSP does too many accesses On solution is to use packets with a maximum of 256 data e The bus request level used BRO BR3 is software configurable in the Control register BCR e The Addresses Modifier AMO AM5 are software configurable in the Control register BCR 1 4 6 VMEbus Interrupt capability Each DSP96002 can generate a VMEbus interruption The level and the vector are software configurable in the Control register BCR Each DSP has its own interrupt status bit When cleared this bit indicates that an interrupt is pending A VMEbus interruption is active as soon as one of these bits is cleared The interrupter handler Host machine read these four bits to identify which D
52. ei N N id LN gt sd lt m E a V205 EN bd a LJ wl D WW pti un bad Ps D Ke Li o ko gt g xv A La La x y CH g gt gt co m gt D 2 o U S 5 gt O D D AI AJ LAJ LAI LI LI pi I a A 2 A B ui a o o o 2 x gt o x o x o an E CS Iz x N N z 5 N z Z o o je yya a fa We S o ra x S W E m a e d o o e LE u u The Broadcast addresses must be different from the base address of the boards That means that the jumpers A24 to A21 have to be different from the fused Broadcast addresses in the logical decoder chip which are A23 0 A22 0 A21 0 1 5 4 Software View The MD96 is used as a powerful co processor and is mapped as memory on VMEbus U234 U232 U233 1 0 DOME FIGURES ADUVI LHE MUJO lo Severals data paths between the V MEbus and the MD96 are provided The VMEbus can access e the Common Memory by direct addressing e one of the fourth DSP Local memory via the DSP Host interface e the On Board registers to Boot and set your configuration A MD96 DSP can access e another DSP to transfer data without interfering with the VMEbus e the Common Memory This memory is a communication memory but it can be also a data field or a program field e the On Board registers to set interrupt or to lock the VMEbus e the VMEbus to access data or to control some process All the communication channels provide a very efficient way to program high level task to use some parallel
53. f 64K x32 128Kx32 or 256Kx32 PDO i PD1 i PD1Li provide a software control of the memory configuration The following table shows the different configurations 9 4 RESERVED MEMORY STALE DESORIEP LION K SOERENSEN o o 0 Sone mena Do A LE oaa E o TT kd III ILL no module o SC LE ES oa i CES AE Ce module If there is no module in port B we will have PDO i equal to 1 the same as a 64Kx32 module e Ready data Ready Cmd bits for the OnCE part Not available now e VMEbus Ack read VMEbus Request description What you can not do e Access to the DSP i from the DSP i e Access to the first Kword of the Communication Memory from one DSP These addresses are internal addresses 3 4 Reserved memory space description Severals memory space area are reserved for Boot operation or communication mechanism This is described for each memory field in the following sections 3 4 1 For the X Data memory field D Address Name Dommen saved register for subroutines saved register for subroutines 50000000 to 000000 _ not used saved register for subroutines saved register for subroutines saved register for subroutines saved register for subroutines saved register for subroutines 00000009 to 0000000F not used 3 4 2 For the Y Data memory field 00000000 PROG Start Address for C program 00000001 MONIT Communication Register between Boot and host 00000002 WOR
54. fer int size gt This routine is used to write data from the Host to the MD96 Write size data in the dsp dsp_number memory at the dsp address dap address in the memory field mem type from the buffer beginning at the address buffer It uses the DMA channel must be used for Local Memory and should not be used for Common memory Return OK or ERROR void md96 write com board number com address buffer size int board number int com address int buffer int size gt This routine is used to write size data from the buffer beginning at address buffer to the Common memory at address com address of the board board number It must be used only for Common memory void md96 write param float dsp number parameter number value int dsp number int parameter number float value gt This routine is used for Communication between the Host and the MD96 Allow to give parameters to the application program via the Communication memory void md96 write parameter dsp number parameter number value int dsp number int parameter number int value gt This routine is used for Communication between the Host and the MD96 Allow to give parameters to the application program via the Communication memory 2 5 2 How to Compile on the Host machine with the MD96 library Your have to insert two things in your Makefile the include path for includemd96 h and the library path for the MD96 Host l
55. ibrary MD96INCLUDE u MD96LIBPATH u MD96LIB libmd96 a or md96Lib o or For theses informations refer to your System Manager 2 6 Example of MD96 Applications 2 6 1 3x3 Convolution The 3x3 convolution has been implemented in 96K assembler 2 0 B AMELE OF MD50 APELICALIONI AUTHOR Herve MATHIEU DATE February 1993 SOFT 3x3 Convolution 96K Assembler SYSTEM MVME167 VxWorks INPUT Image of Intensity 512x256 Float OUTPUT Image after Convolution 512x256 Float MD96 one DSP used 40 Mhz main program in Internal memory input in Local memory outputs in Common memory EXECUTION TIME 2 1 10 second 2 6 2 Deriche Filter This filter has been implemented in C and compiled without optimization AUTHOR Herve MATHIEU DATE February 1993 SOFT Deriche Filter SYSTEM MVME167 VxWorks INPUT Image of Intensity 256x256 Float OUTPUT Image Gradient X and Y 256x256 Float MD96 one DSP used 40 Mhz main program in Local memory input in Local memory outputs in Common memory REFERENCE time on SS10 is 22 1 10 sec EXECUTION TIME 17 1 10 second 2 6 3 Binocular Stereo Correlation This program includes a image Rectification a floating point Correlation and a 3D Reconstruction The implementation has been described in 2 This table shows the time execution for the three algorithms implemented The image is 256 x 256 the disparity width is 20 and the correlation w
56. id miodna 8192 4 reet 4 NJB 966STVIL S gten sein esin een LEIN 22In skin al EENG IERCH K AYOWSW NOTLVYIINAWWOS ziyara L3SFY I6CSTWhL lt BET ovan srin Toi ezan Frin SE A as ZHWEE OX 662S7vrL Een MA LANUILNI DTA29 fre parn Sen Gi HEWER erin wuu ornze WA a Ne S Lein uvdS UrAze lt a 2 ON 2209645 AAR osin UJLIBAV OIAZZ seen LILI EECHER DAI OTA22 ON 20096450 k se Ein 8 ciu19d50 818e dr ESIN ve E zem een e ERSSECHECR 2g1n dSU 7 J INUOH Teen It TAA E SEIN gEIN PISTA sam d 2 INTON ee U208 anan Hi U183 Cecil fi V ON 23996450 ules c dSU 3 1INCON 7 IAaAao un teci a D 2 vies SEA Gcen c doll e 2 OD 77 TA UITE UITS Bech k v ON 20096450 m It 1 j 5 1 dn 7 1 237000 2741I451 8702 Sten 181n 1 dent 2 37N00 y dsa I 3 INON A EGE lt saaf U166 le TT loen CF enn cain atin MITA gain 601n ailm in dSd 3 1NCON 174194S1 8792 eg a TE vec O O por EEE O ZC E T R m m D m m m m 2 S E 5 6 8 8 v a 2 3 8 Z g m e 7 3 8 8 amp ei 5 a m n D gt 90 GHAPFLER 9 MUJO HANUWANE SUFFURL 3 5 6 Programmed Logic Device The following table shows the PLDs used on the MD96 ac fye Place Comme VMEbus Interface VMEbus Interface VMEbus Interface VMEbus Interface INTERRUPTER VMEbus Interface VMEbus Interface VMEbus Interface VMEbus Interface Some PLDs have a different Type in schematics The two Types are compatible except for BUF
57. indow is 7 x 7 Algorithm DSP used MD96 SPARC 2 DSP SUN Rectification 2 imags 2 ole tose 21 Correlation sub pixel 4 ose 368sec 10 Reconstruction SD 1 Lise 40sec 15 Total J oa Mie se 116 GHAPFLER 2 MD30 50UP 1 WARE SUFFORI Chapter 3 MD96 HARDWARE SUPPORT 3 1 Introduction Reading this part reguires knowledge about the VMEbus the Motorola DSP 96002 and Programmed Logic Devices PLD It is guite technigue part whereas only for people working with the MD96 without any hardware development can skip this chapter 3 2 Hardware Description To understand how the MD96 is working you have to take this technical manual A3 schematics the PLD s equations and the referenced books 3 2 1 Data Transfers Severals data paths between the VMEbus and the MD96 are provided The VMEbus can access e the Common Memory by direct addressing e one of the fourth DSP Local memory via the DSP Host interface e the On Board registers to Boot and set your configuration A MD96 DSP can access e another DSP to transfer data without interfering with the VMEbus e the Common Memory This memory is a communication memory but it can be also a data field or a program field e the On Board registers to set interrupt or to lock the VMEbus e the VMEbus to access data or to control some process The 74FTC646 buffers are controlled by the PLD BUFCLK for the latchs CPAB and so on and
58. ize the MD96 hardware architecture 1 2 MIO OVERVLE VV MULTI DSP96002 BOARD focar BUS ocaz BUS locar BUS focar BUS DSP DSP DSP DSP 96002 96002 96002 96002 l I l l COMMON BUS COMMON MEMORY VME On Board Interrupter Arbiter fig 1 summarize the board hardware architecture D GHAPLER 1 MD30 LEOGHNICAL MANUAL 1 3 DSP96002 Implementation 1 3 1 DSP96002 Overview The DSP96002 is the first member of dual port IEEE floating point programming CMOS processor family The device is available either in 33 MHz or in 40 MHz clock for 16 5 or 20 Million Instructions per second MIPS The processing core gives 49 5 or 60 MFLOPS power per device The main features of the DSP96002 are e A 32x32 bits floating point and integer multiplier unit e A 32 64 bits floating point and integer ALU e A full 32 bits Address Generation Unit e 2Kx32 bits internal memory in three banks Two A32 D32 channels DMA controller Full compatibility with IEEE 32 64 floating point and integer data format This means that format conversions are not required In fact the internal device architecture has been made for efficient C implementation e Graphics applications have already been studied by MOTOROLA including fast graphics instruc tions in the assembler language e The DSP is dual ported this means that input output capabilities are double if compared to standard DSP 1 3 2 DSP96002 Mapping The DSP96002 has 2 separate
59. n Bus Read MD96 Technical Support 20000000 to 2003FFFF used for special applications with a big amount of doubles or a very big C stack For most applications it is not used All other segments are reserved Y Data memory field 00000000 to 0000000F reserved for Boot s parameters 00000010 to 000001FF is used by the C stack for doubles and for very critical global values to optimize time computation 1 All the Addresses are calculated for the standard memory configuration of the MD96 which is nine 256Kx32 modules Refer to your System Manager for theses informations 24 CGHAPLER 2 MDUs50 5 UB TWARE SDUFFURL 00000200 to 000007FF reserved for the trigonometric function given in the C libraries 00000800 to 000407FF This is the Common memory including a Y and P space because there is no separation on the Common bus 20000000 to 2007FFFF is used to insert all the data which can not be insert internally 20000000 to 2007CFFF is the standard mapping All other segments are reserved Conclusion Using the standard given locator file should avoid all these memory mapping problems but if you need to change it you must take care of the memory overlapping problems For instance 20040000 to 2007F FFF for Y field is the same segment than 20000000 to 2003FFFF for X and P fields The following table gives the overlapping addresses Memory Module Hardware X and P Addresses Y Addresses Port Common 256K
60. n features of the MD96 are 4 GHAPLER 1 MD30 LEOGHNICAL MANUAL e Four Processing Elements PE working in parallel Each PE is composed of a 96002 Digital Signal Processor at 33 or 40 MHz and one or two JEDEC memory modules The memory modules are organized in 64Kx32 128Kx32 or 256Kx32 Thus each DSP can have 2 Mbytes of fast static memory e A On Board Shared bus between the four PE the VMEbus and a Common memory 64 Kwords to 256 Kwords This Common memory is one JEDEC module of 64Kx32 up to 256Kx32 This Common bus allows PE to create fast communication channels between them and to share data using a Common memory This memory could also be used by the VMEbus interface e Each PE can be master or slave on the VMEbus allowing the board to work without any master board except for boot operation The VMEbus interface module is fully compliant with the VME bus specification Revision C 1 The interface is a module which is A32 D32 MASTER SLAVE allowing 32 bit data transfers A24 D32 MASTER SLAVE and A24 D16 MASTER e The Arbiter Interrupter and Timer modules of the VMEbus specification are not provided on the DSP board e A Broadcast transfer can take place on the VMEbus to simultaneously access several MD96 It allows a simultaneous write into the Common memory Because Broadcast transfer is not support by VMEbus two external rows of the P2 connector are used to provide this feature e Remote Reset facility for each PE is pro
61. n for Shared memory Memory capacity pin for DSP1 Memory capacity pin for DSP4 Memory capacity pin for DSP3 w w 2 NEM 4 NEM 6 7 8 9 10 H WER 14 15 16 unused Na 18 19 20 21 22 23 24 p25 pd3 26 EM 28 29 2 3 4 5 7 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 0 2 4 5 6 7 8 9 0 2 3 4 5 6 7 8 9 0 nt 1 1 1 Memory capacity pin for DSP2 must be read sl Bits signification e IRQB1 IRQB4 IROC1 IROC4 IRQA1 IRQA4 Each DSP i has three hardware interrupt inputs which are IRQAi IROBi and IRQCi One of the other DSP or the VMEbus can activate the interruption by reseting the bit This interruption is only active during the BCSR access so you don t have to set the bit to disable the interruption In reset mode the IRQ bits are Read Write and they are used to determine the nature of the Boot for each DSP e DSP Bus lock The VMEbus can lock the private bus by reseting this bit At the end of the transfer the VMEbus has to set the bit If not the DSP could not access to the private bus e pd0 1 pd0 4 pdl1 pd1 4 pd11 1 pd11_4 Each DSP has on one port one or two memory modules o
62. on memory For most application only the Local memory is used The Common memory is used when common data are shared by severals DSP on the same MD96 The addresses are the same for X Y and P fields and for the four DSPs Here is the description of the memory areas Program memory field 00000000 to 000001FF Reserved It contains the Boot code and is used to initialize some internal registers and to run the C programs 00000200 to 000003FF Internal Memory is the best efficient field to insert code The Cross Compiler uses this field to insert the code created from some libraries Critical functions can be forced internally For this the locator file and the C file must be changed See Pragma option in 4 20000000 to 2003FFFF receives the extra code 2003C000 to 2003FFFF is the standard area and is enough for most applications All other segments are reserved X Data memory field This field is only used for the stack coming from C code for double data memory and for some parameters coming from the Boot code 00000000 to 0000000F reserved for Boot s parameters 00000010 to 000001FF used to insert the C stack and all the doubles This is a critical point because of the width of this memory field 00000200 to 000007FF reserved for the trigonometric function given in the C libraries 00000800 to 000407FF This is the Common memory area including a Y and P space because there is no separation on the Commo
63. ory alloc These functions exist but they can t work with the MD96 except if you need very few memory space e All big structure like tables must be defined as global at the beginning of the code Then the Host part of the code can read the table addresses and dump the data on the MD96 A MD96 application is made of two kinds of codes The first one is the code running on your Host machine It uses the MD96 Host library and can provide the Boot initialization the loading of code and data and the dumping of results The second one is the code running on the MD96 It can be the same for each DSP or can be totally different This code consists of two things one is user routines and the other one uses the MD96 On Board library to provides communication and synchronism between DSPs or VMEbus access or VMEbus interruption The following is about this second part of the code and gives you informations about the mapping of you application and about the way to compile it 2 3 2 MD96 mapping As written in the C compiler manual before compiling your code you need to know where your will load it The DSP 96002 has no MMU the user has in charge the mapping of his application that means that he has to choose where he will load his program and his data It is a hard job but it is very useful for optimization However the locator file given as example is convenient for most of applications There is two kinds of memories The Local memory and the Comm
64. provided to transmit the data transfer acknowledge DTACK to the supervisor processor Two pins of the external rows of the P2 connector are provided for this DTACK generation DTACKIN and DTACKOUT The figure following shows how to install the DTACKIN DTACKOUT daisy chain 1U GHAPLER 1 MPIJ0O LECHINICAL MANUAL DTACKIN DTACKOUT daisy chain in P2 connectors ROW MD96 MD96 MD96 MASTER No3 No 2 No 1 26 DD H D DH D DH DD D 7 000 0006 000 ood 28 DD H A D A D DD D 29 DD H D DH D DH DD D 30 DD H oad oad 0o00 CBA CBA CBA CBA VME Backplane Back View 1 5 2 On Board Jumper Installation Most of the board s parameters are available by software There is only two groups of jumpers to install the first one concerns the the VMEbus transfers e The base address of the MD96 has eleven address jumpers A31 to A21 They are compared to the VMEbus address to validate a transfer When ON a jumper equals to 0 Note that no jumper appears for Broadcast mode thus because extended address A31 to A24 are the same for Broadcast or no Broadcast transfer and Broadcast addresses A23 to A21 are fused in the PLD named DECODER These addresses are 0 0 0 e There is one jumper for Address Modifier Mode when ON only standard VMEbus transfers are recognized when OFF only extended VMEbus transfers are recognized e And one jumper when the VMEbus access the MD96 in Broadcast mode when ON the board is considered as the last board for the D
65. r ESIN ve E zem een Se ERSSECHECR 2g1n dSU 7 J INUOH Teen It TAA E SEIN gEIN PISTA sam d 2 INTON ee U208 anan Hi U183 Cecil fi V ON 23996450 ules c dSU 3 1INCON 7 IAaAao un teci a D 2 vies SEA Gcen c doll e 2 OD 77 TA UITE UITS Bech k v ON 20096450 m It 1 j 5 1 dn 7 1 237000 2741I451 8702 Sten 181n 1 dent 2 37N00 y dsa I 3 INON A EGE lt saaf U166 le TT loen CF enn cain atin MITA gain 601n ailm in dSd 3 1NCON SE 9 19 raad TIULIdS1 8 192 TPE KARGI O O por EEE O ZC E T R m m D m m m m 2 S E 5 6 8 8 v a 2 3 8 Z g m e 7 3 8 8 amp ei 5 a m n D gt 4 4 9 Y 9 EM LINLEGRA LION AND CUMMUNIGA LION Lf 1 7 System Integration and Communication The MULTI DSP 96002 board can be used in any VMEbus compatible system In general case the MD96 boards are managed by a supervisor CPU which uses them as fast slave task processors and are in charge of the following works e Task scheduling and monitoring e Data division and distribution e Results collecting and fusion e Time synchronism e DSP Host request interpretation Such tasks are currently well managed by standard CPU processors A workstation with a VMEbus repeater or standard Real Time operating systems like VRTX OS9 PSOS or VxWorks can be used These standard operating systems provide the advantage to propose additional facilities display mass storage network communication 1 8 Futur
66. se the VMEbus connection Function without open close iovme write Write data iovme read Read data gt When VmeMode is required in a function it selects the address modifier for VNE bus acces Convention EXT NON PRI DAT extended non privileged data access EKT NON PRI PGM extended non privileged program access EKT NON PRI BLK extended non privileged block access EKT SUP VIS DAT extended supervisory data access EKT SUP VIS PGM extended supervisory program access EKT SUP VIS BLK extended supervisory block access STA NOM PRI DAT standard non privileged data access STA NOM PRI PGM standard non privileged program access STA NOM PRI BLK standard non privileged block access STA SUP VIS DAT standard supervisory data access STA SUP VIS PGM standard supervisory program access STA SUP VIS BLK standard supervisory block access SHO NON PRI ACC short non privileged access SHO SUP VIS ACC short supervisory access default extended non privileged data access gt When type is reguired in a function it selects the data format for VME bus acces CGHAPLER 2 MDUs50 5 UB TWARE SDUFFURL Convention DATA 16 BIT 16 bits data DATA 32 BIT 32 bits data void iovme_close gt This routine is used to close the VME bus connection If forgotten at the end of VME transfers it lock the system int iovme_open VmeMode int VmeMode gt This routine is used to connect the MD96 to the VME bus
67. sp number start address with it vme int dsp number int start address int with it vme This routine is used to run a dsp The start address depends upon the program map Returns OK if the run has been done ERROR if the start address is undefined If go address is zero the program is run at the start address defined by the compiler with it vme IT ON VME interrutpion at the end of the program with it vme IT OFF no VME interrution Return OK or ERROR void md96 status board number int board number gt This function is used to know the MD96 s memory configuration This routine prints the results fprintf stderr void md96 write all dsp board number address buffer size int board number int address int buffer int size gt Used to load size data from the buffer to the four DSPs Local Memory of the board board number at address The first quater for DSP1 and so on board number should be BOARD96 1 BOARD96 2 void md96 write broadcast com address buffer size int com address int buffer l int size gt This routine is used to write size data from the buffer buffer to the Common memory at address com address with broacast accesses It must be used only for Common memory int md96 write buffer dsp number dsp address mem type buffer size int dsp number int dsp address int mem type CGHAPLER 2 MDUs50 5 UB TWARE SDUFFURL int buf
68. st be used after open vme in VmeMode SHO NON PRI ACC or SHO SUP VIS ACC Write value at VME address address Using DMA Access These functions are used by the DSP to access the VMEbus Using the DMA channel 7 provides high performance data transfers and allows you to work on DSP96002 in parallel mode DMA Control Release 1 0 int iodma adr sou type sou adr des type des size int adr sou type son adr des type des size gt This routine uses the DMA channel of the DSP It loads size data from the adr_sou address of type_sou memory field to adr des address of type des memory field type_sou and type des are VMEBUS MEN DP MEM X MEM Y Return Ok or ERROR 2 4 2 Inter DSP Communication These functions are used to communicate between DSP on the same MD96 Inter DSP Communication Release 1 0 Driving Functions iodsp run dsp run a DSP Data Flow iodsp write buffer write data iodsp read buffer read data Communication iodsp init com initialize inter DSP communication iodsp write com write a flag in another DSP iodsp read com read a flag from another DSP iodsp identity identification flag int iodsp identity gt Return DSP1 for the first DSP Return DSP2 for the second DSP Return DSP3 for the third DSP Return DSP4 for the fourth DSP Use by the code to know on which dsp it runs void iodsp init com CGHAPLER 2 MDUs50 5
69. t addresses A31 A30 A29 and A28 are used to select the commu nication memory CS the VMEbus OR_V_BR LW A1 the Host interface of another DSP OTHER or the MD96 registers OTHER 3 2 5 Internal mapping The three PLDs MEMORY DMA and REGISTER provide a multiplexer system with two inputs VME bus addresses or DSPs addresses and three outputs Communication Memory the Host interface of a DSP or one of the On Board registers BSR or BCSR On the VMEbus side we decode A18 which is A20 on the VMEbus to separate the Communication Memory CS and the other part For this part we decode A15 A14 A13 A12 to switch between a host interface HS1 HS2 HS3 HS4 HA1 HA2 HA3 HA4 or a register BCR BCSR ONCE On the DSP 96602 side we decode A31 A30 A28 to separate the Communication Memory the VMEbus as master and the rest and into the rest we decode A15 A14 A13 A12 to switch between a host interface HS1 HS2 HS3 HS4 HA1 HA2 HA3 HA4 or a register BCR BCSR ONCE NOTICE The OnCE interface is not yet implemented 3 2 6 VMEbus Mastering When one DSP96002 wants to master the VMEbus it has to assert the BCR V BR in the BCR register This line will do the VMEbus request The BCR_V_BR line is mixed with the two bits BCR BR0 and BCR BR1 VMEbus request level in the BCR register to request the VMEbus When the BGIN BGOUT daisy chain is driven the board keeps the line and take the VMEbus The bit VBA which is the same as
70. tasks and to insert the MD96 in a complex system with other boards like acquisition boards or axes control boards 1 6 Some Figures about the MD96 1 6 1 Internal Access Time Access Type Mbytes sec DSP to Local memory 80 II DSP to Common memory 533 DSP to DSP 1 6 2 VMEbus Access Time VMEbus Access The access time is a constant That means that the duration between AS and DTACK 5 is the same when the VMEbus accesses the Common Memory the Control BCR and Status BCSR registers or the DSP Host interface This duration equal 40 nanoseconds for a write access and 120 nanoseconds for a read access DSP VMEbus Access VMEbus timing should be as short as possible to reduce access time to heavy data banks These timing have been optimized but the transfer time depend of course on the board accessed Note In the following table STANDARD means for a C for with incremented counter DO LOOP means that the DSP 96002 was using its hardware DoLoop and DMA means that we used the DMA channel 7 WARNING All the results showed below was obtain with two MD96 to MD96 Mode Read or Write Time AS to AS Megaword see Mbytes see STANDARD Read ows o cc STANDARD Wie sows 25 0s DOLOOP Rad le 100 s KA oo DO 100P Wie sows Dm Roa os 25 100 oma wi sos ao o ld GHAPLER 1 MPIJ0O LECHNICAL MANUAL For more Details Here are the timing of the two major
71. vided Interrupt generation facilities The VMEbus interface is able to generate VMEbus interrupts with programming interrupt levels and vectors This function is used by the PE to provide synchronism with the supervisor and is very efficient for real time application e Each PE module can be interrupted by VMEbus In fact you can activate three different interrup tions by DSP e A DSP OnCE MOTOROLA Trademark debug interface will be implemented on the MD96 to debug the DSPs This interface is mapped into the VMEbus world register mapping able to access the serial OnCE DSP interface This interface will be used later for high level debugging e There is no need for a bootstrap memory EPROM on the board since each DSP will be start up from its Host interface This feature saves four EPROM devices but requires a Host intervention at RESET It allows a complete reconfiguration of the board both for the user program and the development tools e The MD96 is constituted of standard CMOS TTL components only and is implemented on a extended double Euro Card 220 mm x 233 mm The MD96 accepts up to 9 Mega Bytes of fast access memory which is useful to support C applications It efficiently uses the dual port DSP capability Each DSP can work in its Local memory port B with zero Wait State and no bus arbitration and the Common bus port A can be used by each DSP with one Wait State or by the VMEbus with a minimum of arbitration fig 1 summar

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