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Chapter 2 Altera DE2

1. USB Driver Figure 6 7 The setup for the USB paintbrush demonstration 6 6 USB Device Most USB applications and products operate as USB devices rather than USB hosts In this demonstration we show how the DE2 70 board can operate as a USB device that can be connected to a host computer As indicated in the block diagram in Figure 6 8 the Nios II processor is used to communicate with the host computer via the host port on the DE2 70 board s Philips ISP1362 device After connecting the DE2 70 board to a USB port on the host computer a software program has to be executed on the Nios II processor to initialize the Philips ISP1362 chip Once the software program is successfully executed the host computer will identify the new device in its USB device list and ask for the associated driver the device will be identified as a Philips PDIUSBDI2 SMART Evaluation Board After completion of the driver installation on the host computer the next step 15 to run a software program on the host computer called SP 362DcUsb exe this program communicates with the DE2 70 board In the JSP1362DcUsb program clicking on the Add button in the window panel of the software causes the host computer to send a particular USB packet to the DE2 70 board the packet will be received by the Nios II processor and will increment the value of a hardware counter The value of the counter is displayed on one of the board s 7 segment d
2. SW 74HC 245 swo sw1 sw2 sw3 sw4 SW5 swe SW7 GND GND GND GND GND GND GND GND VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 SWO Swi SW2 SW3 SW4 SW5 SW6 SW7 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND SLIDE SW SLIDE SW SLIDE SW SLIDE SW SLIDE SW SLIDE SW SLIDE SW SLIDE SW SW8 SW9 SW10 SW11 SW12 SW13 GND GND GND GND GND GND VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 SW8 SW9 SW10 SW11 SW12 R50 4 120 SW13 GND GND GND GND GND GND GND GND GND GND GND GND SLIDE Sw SLIDE SW SLIDE SW SLIDE Sw SLIDE SW SLIDE SW SW14 SW15 SW16 SW17 4 GND GND GND GND VCC33 VCC33 VCC33 VCC33 N35 120 KEYIO 3 a AA 1 sw EE GND GND GND GND E SW16 SW 0 17 GND GND GND GND A SW15 RA WEEE SLIDE SW SLIDE SW SLIDE SW SLIDE SW ET Figure 5 4 Schematic diagram of the pushbutton and toggle switches DE2 70 User Manual LEDR2 AA LEDR LEDR3 AA LEDR 5 EDR6 ZA LEDR LEDRZ ZA LEDR 7 LEDR9 7 LEDR LEDG8 AA LEDG 5 LEDR12 pn 7 LEDR LEDR13 7 LEDR LEDR16 LEDR LEDR17 AA Figure 5 5 Schematic diagram of the LEDs Table 5 1 Pin assignments for the toggle switches 34 KEY 0 KEY 1 KEY 2 KEY 3 DE2 70 User Manual Table 5 2 Pin assignments for the pushbutton switches LEDRI0 LEDR 1 LEDR 2 LEDR 3 LEDR 4 LEDR 5 LEDR 6 LEDR 7 LEDR 8 LEDR 9 LEDR 10 LEDR 11 LEDR 12 LEDR 13 LEDR 14 LEDR 15 LEDR 16 LEDR 17 LEDG O LEDG 1
3. D13 H CKE DRAM D14 DRAMI CKE DRAM_D30 CKE D14 gt CKE D14 DRAMO_LDQMO DRAM_D15 DRAMI LDQMO DRAM D31 2 ag LDQM EE L DRAMI UDQMt ag LDQM D15 UDQM 2 UDQM DRAMO_WE a DRAM1_WE a C ORS nWE LL CAS nWE DRAMO CAS n DRAMI CAS n D nCAS gt nCAS DRAMO RAS n 8 DRAMI RAS n 48 gt nRAS nRAS DRAMO CS n 4o DRAMI CS n D ncs ncs DRAMO BAO A DRAMI BAO L 2 DRAMO BAI BAO 2 DRAMI BA BAO u BA1 SDRAMO k cous ee SDRAM1 4 7K DRAMO WE n R7 4 7K DRAM1 WE n R2 4 7K DRAMO_CAS_n R8 4 7K DRAM1_CAS_n R3 4 7K DRAMO_RAS_n R9 47K DRAM1_RAS_n R4 4 7K DRAMO_CS_n R1 47K C8 n RS 4 7K DRAMO_CKE Ri 4 7K DRAM1_CKE Figure 5 22 SDRAM schematic 58 DE2 70 User Manual gt SRAM_DQJ0 31 gt SRAM_DPAIO 3 SRAM 0 18 me SRAM BE _n 0 3 ie s ip E U3 EEE 1388 3888 SRAM addro SRAM dataO SRAM_addr1 G SRAM data1 SRAM addr2 G SRAM data2 SRAM addr3 SRAM data3 SRAM_addr4 Q SRAM _data4 SRAM addr5 O SRAM data5 SRAM addr6 44 6 SRAM data6 SRAM addr7 4 G SRAM data SRAM addr8 AG SRAM dataparO SRAM addr9 SRAM addri0 eR SRAM data8 SRAM addr11 AQ SRAM data9 SRAM addr12 a SRAM data10 SRAM addr13 Q SRAM_data11 SRAM addrid A177 SRAM data12 SRAM_addri5 gg SRAM data13 SRAM_addr16 A15 Q SRAM data14 SRAM addri7 44 18 SRAM data15 SRAM addr18 4 n 30 SRAM_datapar1 NC A19 SRAM data16
4. Learning through Innovation MIFA 4 User Development and Education Board Manual fi Ing UNIVERSAL SERIAL BUS Version 1 08 Copyright 2009 Terasic Technologies Altera DE2 70 Board Chapter 1 227 0 PAC een 1 1 1 C OBFEBES N E E E A rr terre l 1 2 The DE2 70 Board AssemDly ee een 2 1 3 Ge E P een 3 Chapter 2 Altera DE2 70 Board scsscsseeciscsuavseneennavsazcscensssessaceususencadsvers useeuavsssicsasessuncescsareenveuvesaestinys 4 2 1 TAY 001 300 ORipOoble Il S ee E E E E wed E 4 22 Block Diagram or the ae a ca 5 2 3 Power up the DE2 9 Chapter 3 DE2 0 Control 1 3 1 Contool Pane SC BUD x E 1 32 Controlling the LEDs 7 Segment Displays and LCD Display ss 13 33 SWIICHeS and BUON ccc cet ete ON DN MR DU RN 15 3 4 SDRAM SSRAM Flash Controller and 16 3 5 USB MORTON I ae ae 18 30 H Meares 19 31 SEI AR 20 3 8 Audio Playing and Recording ann ee pn 21 3 9 Overall Structure of the DE2 70 Control 23 Chapter 4 DEZ2
5. VCC33 O 6 ENET n IOW a5 ENET IOR n Of 734 4 ENET NT S NT 34 ENELNT 75 L2 BEAD N VCC250 Ar A X y 7 GND 1 X En sms grep 2 5 pweoooa s 16b iR on von der 9 TX N VCC33O aP2 spo 28 a aS SS aes og ENET D10 N VCC330 L R73 R74 R75 R76 GP5 SD12 TI 1 ENET D13 RJ45INTLED j s CHSGND 49 9 49 9 49 9 49 9 icd to SU a CHSGND C18 C19 D U 0 1u 0 1u X80 i z254 R77 120 SPEED i R78 120 ACT ENET Dia ON VCC33 015 ENET DO ENET D1 ENET D2 ENET D3 ENET D4 ENET D5 ENET D6 ENET D7 Figure 5 17 Fast Ethernet schematic 51 DE2 70 User Manual ENET_CS_N PIN C28 DM9000A Chip Select ENET INT PIN C27 Interrupt ENET_IOR_N PIN_A28 DM9000A Read ENET_IOW_N PIN_B28 DM9000A Write ENET RESET N PIN B29 DM9000A Reset Table 5 15 Fast Ethernet pin assignments 5 12 TV Decoder The DE2 70 board is equipped with two Analog Devices ADV7180 TV decoder chips The ADV7180 is an integrated video decoder that automatically detects and converts a standard analog baseband television signal NTSC PAL and SECAM into 4 2 2 component video data compatible with the 8 bit ITU R BT 656 interface standard The ADV7180 15 compatible with a broad range of video devices including DVD players tape based sources broadcast sources and security surveillance cameras The regi
6. TiasiC TE t Memory Ww LeFBSTE DOM About SDRAM 2 Download Code Disconnect Exit Connected Figure 3 6 Monitoring switches and buttons The ability to check the status of button and switch is not needed in typical design activities However it provides users a simple mechanism for verifying if the buttons and switches are functioning correctly Thus it can be used for troubleshooting purposes 3 4 SDRAM SSRAM Flash Controller and Programmer The Control Panel can be used to write read data to from the SDRAM SSRAM and FLASH chips on the DE2 70 board We will describe how the SDRAM U1 may be accessed the same approach is used to access the SDRAM U2 SRAM and FLASH Click on the Memory tab and select SDRAM U1 to reach the window in Figure 3 7 Please note the target memory chosen for storing elf file is read only Also please erase the flash before writing data to it 16 DE2 70 User Manual LED 7 SEG LCD Button Memory USB PS2 SD CARD Audio SBRAM UT O00000h WORDS M Random Access Address 00000 WDATA DECA DATA DODD Write Read Seguential Write Address ogogo Length 1000000 File Length ve d Write a File to Memory Product Name DE 70 i Sequential Read Address joooooo Length 1000000 Entire Memary Load Memory Content ta a File hittp www altera com TiasiC Target Memory _ WWW DEAE IG DOM About SDRAM LI2 Do
7. LEDG 2 LEDG 3 LEDG A LEDG 5 LEDG 6 LEDG 7 LEDGI8 Table 5 3 Pin assignments for the LEDs 35 DE2 70 User Manual 53 Using the 7 segment Displays The DE2 70 Board has eight 7 segment displays These displays are arranged into two pairs and a group of four with the intent of displaying numbers of various sizes As indicated in the schematic in Figure 5 6 the seven segments are connected to pins on the Cyclone II FPGA Applying a low logic level to a segment causes it to light up and applying a high logic level turns it off Each segment in a display is identified by an index from 0 to 6 with the positions given in Figure 5 7 In addition the decimal point is identified as DP Table 5 4 shows the assignments of FPGA pins to the 7 segment displays HEXO DO HEXO D1 HEXO D2 HEXO DS3 HEXO D4 05 HEXO D6 p gt HEXO DP Figure 5 7 Position and index of each segment in a 7 segment display HEXO DIO PIN AE8 Seven Segment Digit O O D 1 PIN AF9 Seven Segment Digit O 1 HEXO D 2 PIN AH9 Seven Segment Digit O 2 36 DE2 70 User Manual HEXO_DP PIN_AF12 Seven Segment Decimal Point 0 37 DE2 70 User Manual HEX5 D 4 PIN K1 Seven Segment Digit 5 4 Table 5 4 Pin assignments for the 7 segment displays 5 4 Clock Circuitry The DE2 70 board includes two oscillators that produce 28 86 MHz and 50 MHz clock signals Both two clock signals are connected to the FPGA
8. The Sequential Read function 15 used to read the contents of the SDRAM UI and place them into a file as follows l Specify the starting address in the Address box 2 Specify the number of bytes to be copied into the file in the Length box If the entire contents of the SDRAM UI are to be copied which involves all 32 Mbytes then place a checkmark in the Entire Memory box 3 Press Load Memory Content to a File button 4 When the Control Panel responds with the standard Windows dialog box asking for the destination file specify the desired file in the usual manner Users can use the similar way to access the SSRAM and Flash Please note that users need to erase the flash before writing data to it 35 USB Monitoring The Control Panel provides users a USB monitoring tool which monitors the real time status of a USB mouse connected to the DE2 70 board The movement of the mouse and the status of the three buttons will be shown in the graphical and text interface The mouse movement is translated as a position x y with range from 0 0 1023 767 This function can be used to verify the functionality of the USB Host Follow the steps below to exercise the USB Mouse Monitoring tool 1 Choosing the USB tab leads to the window in Figure 3 8 2 Plug an USB mouse to the USB HOST port on the DE2 70 board 3 Press the Start button to start the USB mouse monitoring process and button caption 15 changed from Start to Stop In the monitori
9. 6 9 SD Card Music Player Many commercial media audio players use a large external storage device such as an SD card or CF card to store music or video files Such players may also include high quality DAC devices so that good audio quality can be produced The DE2 70 board provides the hardware and software needed for SD card access and professional audio performance so that it is possible to design advanced multimedia products using the DE2 70 board In this demonstration we show how to implement an SD Card Music Player on the DE2 70 board in which the music files are stored in an SD card and the board can play the music files via its CD quality audio DAC circuits We use the Nios II processor to read the music data stored in the SD Card and use the Wolfson WM8731 audio CODEC to play the music 81 DE2 70 User Manual Figure 6 14 shows the hardware block diagram of this demonstration The system requires a 50 MHZ clock provided from the board The PLL generates a 100 MHZ clock for NIOS II processor and the other controllers except for the audio controller The audio chip is controlled by the Audio Controller which is a user defined SOPC component This audio controller needs an input clock running at 18 432 MHZ In this design the clock is provided by the PLL block The audio controller requires the audio chip working in master mode so the serial bit BCK and the left right channel clock LRCK are provided by the audio chip The 7 segme
10. E TA CS n cs R120 330 0 VCC5 OTG OE m m WR a TER 24 u Voca OTG_INTA a TEST 60 A121 10K __ LEDB d OTe RESETE ao INTI TESTI 2 EAN D87 D88 p RESET TESTO v OU VCC33 x y OTG_DREQ1 25 lis Ser 25 DREQ2 CLKOUT 38 dia z gt DR QO 24 CREDI x1 43 OTG_FSPEED_R124 A A 1 SK i 1 JE een 5 OIG DACKO n 28 Duck gt 44 x gt lt OTG LSPEED Ri28 15K 2155 2 2 2 2 2 2 2 L11 BEAD O VCC5 1 e OGOGO a GND USB B TYPE 47p 47p je Pe EM C68 0 1u 12MHZ R126 WA 22 4 c54 47p Figure 5 20 USB ISP1362 host and device schematic 55 DE2 70 User Manual Table 5 17 USB ISP1362 pin assignments 56 DE2 70 User Manual 5 15 Using IrDA The DE2 70 board provides a simple wireless communication media using the Agilent HSDL 3201 low power infrared transceiver The datasheet for this device is provided in the DatasheetNrDA folder on the DE2 70 System CD ROM Note that the highest transmission rate supported is 115 2 Kbit s and both the TX and RX sides have to use the same transmission rate Figure 5 21 shows the schematic of the IrDA communication link Please refer to the following website for detailed information on how to send and receive data using the IrDA link http techtrain microchip com webseminars documents IrDA BW pdf The pin assignments of the associated interface are listed in Table 5 18 IRDA RXD R4
11. LtD LEX 18 Red LEDs 7 a Al 1 F E i m iL E E g 8 CLK 8 Green LEDs i PT Jon In il h om SMA Extemal Clock f 6 D M A E i 1 IT I Ll i d 4 18 Toggle Switches 32Mbyte SDRAMx2 28Mhz Oscillator 2Mbyte SSRAM 4 Push button Switches Figure 2 1 The DE2 70 board The DE2 70 board has many features that allow the user to implement a wide range of designed circuits from simple circuits to various multimedia projects The following hardware is provided on the DE2 70 board e Altera Cyclone II 2C70 FPGA device Altera Serial Configuration device EPCS16 USB Blaster on board for programming and user API control both JTAG and Active Serial 4 DE2 70 User Manual AS programming modes are supported e 2 Mbyte SSRAM e Two 32 Mbyte SDRAM e 8 Mbyte Flash memory e SD Card socket e 4 pushbutton switches 18 toggle switches 18 red user LEDs 9 green user LEDs e 50 MHz oscillator and 28 63 MHz oscillator for clock sources 24 bit CD quality audio CODEC with line in line out and microphone in jacks e VGA DAC 10 bit high speed triple DACs with VGA out connector e 2 TV Decoder NTSC PAL SECAM and TV in connector e 10 100 Ethernet Controller with a connector USB Host Slave Controller with USB type A and type B connectors e RS 232 transceiver and 9 pin connector e PS 2 mouse keyboard connector e IrDA transceiver e SMA connector Two 40 pin Expansion
12. NC A20 SSRAM 512Kx36 SRAM data17 SRAM MODE 3 SRAM data18 SRAM ZZ c4 MODE 1561 PS51236A 200TQLI SRAM_data19 SRAM_outen_n 26 ZZ 9 SRAM_data20 SRAM clock ag SRAM data21 SRAM globalw n gg CLK SRAM data22 SRAM writeen n g GW n SRAM data23 SRAM advance n g3 P WE n SRAM datapar2 SRAM_adsconttroler_ mes DV n SRAM adsprocessor ga APSC_N Q SRAM data24 SRAM chipent n gg ADSP_n Q SRAM data25 SRAM chipen2 97 CE1 n SRAM data26 SRAM chipen3 n o CE2 SRAM _data27 SRAM_byteen no 93 CE3_N SRAM_data28 byteen n1 oa BWA_n SRAM data29 SRAM byteen n2 BWB_n SRAM data30 SRAM byteen n3 og PC n Q SRAM data31 BWD n 0 SRAM datapar3 C C C C O SI O O O Figure 5 23 SSRAM schematic Ee FLASH DIO 14 Da FLASH A 0 21 F_VCC33 FLASH 0 z FLASH_A1 C roe FLASH A2 FLASH A3 4 FLASH DO FLASH A4 FLASH D1 FLASH 9 FLASH D2 FLASH A6 41 FLASH_D3 FLASH A7 g A4 FLASH D4 FLASH_A8 D ae FLASH D5 FLASH_A9 5 A8 FLASH D6 FLASH_A10 3 Q FLASH D7 FLASH A11 gt o FLASH D8 FLASH A12 a FLASH 59 FLASH A13 An FLASH D10 FLASH_A14 DQ10 7 5 FLASH D11 FLASH A15 DQ11 FLASH D12 FLASH A16 DQ12 7 FLASH D13 FLASH A17 a zie Ag FLASH D14 FLASH_A18 FLASH D15 A 1 FLASH A19 DQ15 A 1 e ou FLASH A20 FLASH 21 FLASH 8Mx8 FLASH WE n L 5 FLASH RESET n 27 FLASH WP n 28 L gt FLASH RY 30 lt FLASH CE n FLASH OE n L Z FLASH BYTE m ag F_VCC33 R32 4 7K FLASH
13. Video in 2 TD_clock as in1 27Mhz VGA TV decoder i Composite to data Main VGA multiplexer Main window VGA Main window Figure 6 4 Block diagram of the TV PIP demonstration 70 DE2 70 User Manual Demonstration Setup File Locations and Instructions e Project directory DE2_70_TV_PIP e Bit stream used DE2_70_TV_PIP sof or DE2 70 TV PIP pof Connect composite video output yellow plug of DVD player 1 and DVD player2 to the Video in 1 and Video in 2 RCA jack J8 and J9 of the DE2 70 board respectively Both DVD players must be configured to provide o 60 Hz refresh rate o 4 3 aspect ratio o Non progressive video Connect the VGA output of the DE2 70 board to a VGA monitor both LCD and CRT type of monitors should work Connect the one audio output of the DVD player to the line in port of the DE2 70 board and connect a speaker to the line out port If the audio output jacks from the DVD player are of RCA type then an adaptor will be needed to convert to the mini stereo plug supported on the DE2 70 board this 15 the same type of plug supported on most computers Load the bit stream into FPGA The detailed configuration for switching video source of main and sub window are listed in Table 6 1 Figure 6 5 illustrates the setup for this demonstration 71 DE2 70 User Manual La urs no VGA Out EN T F E E E E N
14. all LS ILS LS LS NL Figure 6 5 The setup for the TV box PIP demonstration 72 2 o DE2 70 User Manual ANU S AYA SW 17 OFF Signal display mode Video in 2 SW 16 OFF SW 17 OFF Signal display mode Video in 1 SW 16 ON SW 17 ON Main window Video in 2 PIP display mode SW 16 OFF Sub window Video in 1 SW 17 ON Main window Video in 1 PIP display mode SW 16 ON Sub window Video in 2 Table 6 1 The setup for the TV box PIP demonstration 6 55 USB Paintbrush USB 15 a popular communication method used in many multimedia products The DE2 70 board provides a complete USB solution for both host and device applications In this demonstration we implement a Paintbrush application by using a USB mouse as the input device This demonstration uses the device port of the Philips ISP1362 chip and the Nios II processor to implement a USB mouse movement detector We also implemented a video frame buffer with a VGA controller to perform the real time image storage and display Figure 6 6 shows the block diagram of the circuit which allows the user to draw lines on the VGA display screen using the USB mouse The VGA Controller block is integrated into the Altera Avalon bus so that it can be controlled by the Nios II processor Once the program running on the Nios II processor is started it will detect the existence of the USB mouse connected to DE2 70 board Once the mouse is moved the Nios II pr
15. 4 TV Box Picture in Picture PIP 70 6 5 USB Datis tup E Cla MANO PUN MM IM ELS SUUM 73 Oo USEDE cv 75 6 7 AK i OC Ma Mi een ee ee 71 6 8 Ethernet Packet Semi eier 79 6 9 en UU TT Sl 6 10 Music Synthesizer Demonstration essen 84 6 11 Audo dee a PIE HIR GRAM 88 CHAPter E 1 1 21173 91 7 1 0 ee 91 7 2 STAU TIL 91 DE2 70 User Manual Chapter 1 DE2 70 Package The DE2 70 package contains all components needed to use the DE2 70 board in conjunction with a computer that runs the Microsoft Windows software 1 1 Package Contents Figure 1 1 shows a photograph of the DE2 70 package AE RAY p Figure 1 1 The DE2 70 package contents 1 DE2 70 User Manual The DE2 70 package includes 1 2 The DE2 70 board USB Cable for FPGA programming and control DE2 70 System CD containing the DE2 70 documentation and supporting materials including the User Manual the Control Panel utility reference designs and demonstrations device datasheets tutorials and a set of laboratory exercises CD ROMs containing Altera s Quartus II Web Edition and the Nios II Embedded Design Suit Evaluation Edition software B
16. Config Blaster Dev Figure 2 2 Block diagram of the DE2 70 board Following is more detailed information about the blocks in Figure 2 2 Cyclone II 2C70 FPGA 68 416 LEs 250 M4K RAM blocks 1 152 000 total RAM bits 150 embedded multipliers 4 PLLs 622 user I O pins FineLine BGA 896 pin package Serial Configuration device and USB Blaster circuit Altera s EPCS16 Serial Configuration device On board USB Blaster for programming and user API control JTAG and AS programming modes are supported DE2 70 User Manual SSRAM e 2 Mbyte standard synchronous SRAM e Organized as 512K x 36 bits e Accessible as memory for the Nios II processor and by the DE2 70 Control Panel SDRAM e Two 32 Mbyte Single Data Rate Synchronous Dynamic RAM memory chips e Organized as 4M x 16 bits x 4 banks e Accessible as memory for the Nios II processor and by the DE2 70 Control Panel Flash memory e 8 Mbyte NOR Flash memory e Support both byte and word mode access e Accessible as memory for the Nios II processor and by the DE2 70 Control Panel SD card socket e Provides SPI and 1 bit SD mode for SD Card access e Accessible as memory for the Nios II processor with the DE2 70 SD Card Driver Pushbutton switches e 4 pushbutton switches e Debounced by a Schmitt trigger circuit e Normally high generates one active low pulse when the switch is pressed Toggle switches 18 toggle switches for user inputs A switch causes logic 0 when in the D
17. Manual Configuring the FPGA in JTAG Mode Figure 5 1 illustrates the JTAG configuration setup To download a configuration bit stream into the Cyclone II FPGA perform the following steps Quartus II Programmer Ensure that power 15 applied to the DE2 70 board Connect the supplied USB cable to the USB Blaster port on the DE2 70 board see Figure 2 1 Configure the JTAG programming circuit by setting the RUN PROG switch on the left s de of the board to the RUN position The FPGA can now be programmed by using the Quartus II Programmer module to select a configuration bit stream file with the sof filename extension USB Blaster Circuit PROG RUN JTAG Confi JTAG UART Auto Power on Config JTAG Config Port EPCS16 Serial Configuration Device Figure 5 1 The JTAG configuration scheme Configuring the EPCS16 in AS Mode Figure 5 2 illustrates the AS configuration set up To download a configuration bit stream into the EPCS 16 serial EEPROM device perform the following steps Ensure that power 15 applied to the DE2 70 board Connect the supplied USB cable to the USB Blaster port on the DE2 70 board see Figure 2 1 Configure the JTAG programming circuit by setting the RUN PROG switch on the left side of the board to the PROG position The EPCS16 chip can now be programmed by using the Quartus II Programmer module to select a configuration bit stream file with the pof filename extensi
18. RY R33 4 7K FLASH CE n Figure 5 24 Flash schematic 59 DE2 70 User Manual 60 DE2 70 User Manual DRAMO_CKE PIN AA8 SDRAM 1 Clock Enable 61 DE2 70 User Manual DRAM1 RAS N PIN N9 SDRAM 2 Row Address Strobe Table 5 19 SDRAM pin assignments DE2 70 User Manual SRAM DQ 9 PIN AJ17 SRAM Data 9 63 SRAM DPA3 SRAM GW N SRAM OE N SRAM WE N FLASH FLASH A 1 FLASH 2 FLASH A 3 FLASH A 4 FLASH A 5 FLASH A 6 FLASH A 7 FLASH A 8 FLASH A 9 FLASH A 10 FLASH A 11 FLASH A 12 FLASH A 13 FLASH A 14 FLASH A 15 FLASH A 16 FLASH A 17 FLASH A 18 FLASH A 19 FLASH A 20 FLASH 21 FLASH DQ O0 FLASH DQ 1 FLASH DQ 2 FLASH DQ 3 FLASH DQ 4 FLASH DQ 5 FLASH DQ 6 DE2 70 User Manual Table 5 20 SSRAM pin assignments DE2 70 User Manual FLASH DQ 7 PIN Y28 FLASH Data 7 Table 5 21 Flash pin assignments 65 DE2 70 User Manual Chapter 6 Examples of Advanced Demonstrations This chapter provides a number of examples of advanced circuits implemented on the DE2 70 board These circuits provide demonstrations of the major features on the board such as its audio and video capabilities and USB and Ethernet connectivity For each demonstration the Cyclone II FPGA or EPCS16 serial EEPROM configuration file is provided as well as the full source code in Verilog HDL code All of the associated files can be found
19. Rate 441 Open Wave Start Play Klasic a why DEFABIG COMI About SDRAM L2 Download Code Disconnect Connected ISD CARD read success Figure 3 11 Playing audio from a selected wave file To record sound using a microphone please follow the steps below Plug a microphone to the MIC port on the board 2 Select the Record MIC item in the com box and select desired sampling rate as shown in Figure 3 12 3 Click Start Record to start the record process The program will configure the audio chip for MIC recording retrieve audio signal from the MIC port and then save the audio signal into SDRAM UI 4 To stop recording click Stop Record Finally audio signal saved in SDRAM UI will be uploaded to the host computer and displayed on the waveform window Click Save Wave to save the waveform into a WAV file 22 DE2 70 User Manual TX LED 7 SEG LCD Button Memory USB PS2 SD CARD Audio Audia Mic Record http www altera com Sample Rate 44 1K Seve Wave Start Record Tiasic Target Memory Disconnect Www DE BSC com boy ISDRAM U2 Download Code Connected Auiod record successfully Figure 3 12 Audio Recording and Saving as a WAV file To record audio sound from LINE IN port please connect an audio source to the LINE IN port on the board The operation is as same as recording audio from MIC 30 Overall Structure of the DE2 70 Control P
20. SD card The provided wave files must have a sample rate of either 96K 48K 44 1K 32K or 8K Besides the wave files must be stereo and 16 bits per channel Also the file name must be short filename e Load the bitstream into the FPGA on the DE2 70 board e Run the Nios II IDE under the workspace DE2_70_SD_Card_Audio_Playe Software e Connect a headset or speaker to the DE2 70 board and you should be able to hear the music played from the SD Card 83 DE2 70 User Manual e Press KEY3 on the DE2 70 board can play the next music file stored in the SD card Press KEY2 and KEYI will increase and decrease the output music volume respectively Figure 6 16 illustrates the setup for this demonstration mm J LJ In with music fils wav Figure 6 16 The setup for the SD music player demonstration 6 10 Music Synthesizer Demonstration This demonstration shows how to implement a Multi tone Electronic Keyboard using DE2 70 board with a PS 2 Keyboard and a speaker PS 2 Keyboard is used as the piano keyboard for input The Cyclone II FPGA on the DE2 70 board serves as the Music Synthesizer SOC to generate music and tones The VGA connected to the DE2 70 board is used to show which key is pressed during the playing of the music 84 DE2 70 User Manual Figure 6 15 shows the block diagram of the design of the Music Synthesizer There are four major blocks in the circuit DEMO SOUND PS2 KEYBOARD STAF
21. Video IN 1 RCA jack 68 DE2 70 User Manual JS of the DE2 70 board The DVD player has to be configured to provide NTSC output o 60 Hz refresh rate o 4 3 aspect ratio Non progressive video e Connect the VGA output of the DE2 70 board to a VGA monitor both LCD and CRT type of monitors should work Connect the audio output of the DVD player to the line in port of the DE2 70 board and connect a speaker to the line out port If the audio output jacks from the DVD player are of RCA type then an adaptor will be needed to convert to the mini stereo plug supported on the DE2 70 board this is the same type of plug supported on most computers Load the bit stream into FPGA Press KEYO on the DE2 70 board to reset the circuit Figure 6 3 illustrates the setup for this demonstration Line Out Line In CVBS S Video YPbPr Output Video In Audio Output VGA Out Figure 6 3 The setup for the TV box demonstration 69 DE2 70 User Manual 6 4 TV Box Picture in Picture PIP Demonstration The DE2 70 board has two TV decoders and RCA jacks that allow users to process two video sources simultaneously using the 2C70 FPGA This demonstration will multiplex two different video source signals from the TV decoders and display both video signals on the LCD CRT monitor using picture in picture mode PIP mode One picture is displayed on the full screen and the other picture is displayed in a smal
22. Winkso Y ha Y fan T Zip NiosII 9 1 Examples Verilog im CutePDF NiosII 3 1 Examples YHDL I Lizard Tech O NiosII 9 1 Software Build Tools for Eclipse Figure 6 1 6 3 TV Box Demonstration This demonstration plays video and audio input from a DVD player using the VGA output audio CODEC and one TV decoder U11 on the DE2 70 board Figure 6 2 shows the block diagram of the design There are two major blocks in the circuit called 2C AV Config and TV to VGA The TV to VGA block consists of the JTU R 656 Decoder SDRAM Frame Buffer YUV422 to YUV444 YcrCb to RGB and VGA Controller The figure also shows the TV Decoder ADV7180 and the VGA DAC ADV7123 chips used As soon as the bit stream is downloaded into the FPGA the register values of the TV Decoder chip are used to configure the TV decoder via the 2C AV Config block which uses the I2C protocol to communicate with the TV Decoder chip Following the power on sequence the TV Decoder chip 67 YA DE2 70 User Manual will be unstable for a time period the Lock Detector 1s responsible for detecting this instability The TU R 656 Decoder block extracts YcrCb 4 2 2 YUV 4 2 2 video signals from the TU R 656 data stream sent from the TV Decoder It also generates a data valid control signal indicating the valid period of data output Because the video signal from the TV Decoder 15 interlaced we need to perform de interlacing on the data source We used the S
23. and Nios II are installed successfully on your PC 2 Connect the supplied USB cable to the USB Blaster port connect the 12V power supply and turn the power switch ON 3 Set the RUN PROG switch to the RUN position 4 Start the executable DE2 70 VIDEO exe on the host computer The Video Utility user interface shown in Figure 4 1 will appear 5 Click the Download Code button The Control Panel will occupy the USB port until you close that port you cannot use Quartus II to download a configuration file into the FPGA until you close the USB port 6 The Video Utility 15 now ready for use 25 DE2 70 User Manual Video Utility V1 0 0 Display Capture Image Position CENTER M Dimension 640 x 480 Pixels Load Display Download Code Disconnect Exit Connected Download code success Figure 4 1 The DE2 70 Video Utility window 4 2 VGA Display Choosing the Display tab in the DE2 70 Video Utility leads to the window shown in Figure 4 2 The function is designed to download an image from the host computer to the FPGA board and output the image through the VGA interface with resolution 640x480 Please follow the steps below to exercise the Video Utility 1 Connect a VGA monitor to the VGA port of the board 2 Click Load button and specify an image file for displaying It can be a bitmap or jpeg file The selected image file will be displayed on the display window of the Video Utility
24. display 66 DE2 70 User Manual e Optionally connect a VGA display to the VGA D SUB connector When connected the VGA display should show a pattern of colors e Optionally connect a powered speaker to the stereo audio out jack Place toggle switch SW17 in the UP position to hear a 1 kHz humming sound from the audio out port Alternatively if switch SW17 is DOWN the microphone in port can be connected to a microphone to hear voice sounds or the line in port can be used to play audio from an appropriate sound source The Verilog source code for this demonstration is provided in the DE2_70_Default folder which also includes the necessary files for the corresponding Quartus II project The top level Verilog file called DE2_70_Default v can be used as a template for other projects because it defines ports that correspond to all of the user accessible pins on the Cyclone II FPGA 6 2 Quartus II 9 1 amp Nios II EDS 9 1 Users Users that are using the latest Quartus and Nios version 9 1 to run the DE2 70 demonstrations with Nios II processor must ensure that Nios II 9 1 IDE is used instead of the Nios II Software Build Tools for Eclipse as it is not supported Figure 6 1 shows the directory of the correct Nios II software to run on the DE2 70 demonstrations Nios IT EDS 9 1 t Legacy Nios II Tools E Nios II 9 1 IDE Nios II 9 1 Command Shell Nios Il 9 1 Documentation avast Antivirus AM
25. 1 IRDA TXD H42 Figure 5 21 IrDA schematic IRDA TXD PIN W21 IRDA Transmitter IRDA RXD PIN W22 IRDA Receiver Table 5 18 IrDA pin assignments 57 DE2 70 User Manual 5 16 Using SDRAM SRAM Flash The DE2 70 board provides a 2 Mbyte SSRAM 8 Mbyte Flash memory and two 32 Mbyte SDRAM chips Figures 5 22 5 23 and 5 24 show the schematics of the memory chips The pin assignments for each device are listed in Tables 5 19 5 20 and 5 21 The datasheets for the memory chips are provided in the Datasheet Memory folder on the DE2 70 System CD ROM DRAM_Dj0 31 DRAMO_AJ0 12 DRAMI_A 0 12 DR_VCC33 DR_VCC33 O DRAMO_AO DRAM_DO DRAM1_AO DRAM_D16 DRAMO A1 4 0 DO 7 DRAM D1 DRAMI 4 AO DO 7 DRAM D17 DRAMO A2 A1 D1 DRAM_D2 DRAM1_A2 Al D1 DRAM D18 DRAMO A3 n D2 DRAM D3 DRAMI A3 n A2 D2 DRAM D19 DRAMO A4 AS D3 r DRAM 54 DRAMI A4 AS D3 7 DRAM D20 DRAMO A5 A je 2 5 DRAM_D5 DRAMI 4 Da Tr DRAM_D21 DRAMO A6 5 5 DRAM D6 DRAMI A6 AS DS DRAM D22 7 D6 DRAM_D7 DRAM1_A7 A6 D6 DRAM_D23 DRAMO A8 A7 D7 DRAM D8 DRAMI A8 A7 D7 DRAM D24 DRAMO A9 4 8 D8 DRAM D9 DRAMI A9 4 A8 D8 7 DRAM D25 DRAMO A10 A9 DI DRAM D10 DRAMI A10 A9 59 DRAM D26 DRAMO A11 A10 D10 7 DRAM D11 DRAMI A11 EOM ns j DRAM D27 DRAMO A12 3 ie SDRAM 16Mx1 a AR DRAM D12 DRAMI A12 M SDRAM 16Mx18 1 48 DRAM_D28 DRAMO CLK DRAM D13 DRAMI CLK x DRAM 529 CLK D13 X
26. 3 Select the desired Image Positioning method to fit the image to the VGA 640x480 display dimension Click Display button to start downloading the image to the DE2 70 board 5 After finish downloading you will see the desired image shown on the screen of the VGA monitor 26 DE2 70 User Manual Image Position STRETCH Dimension 640 x 480 Pixels Load Display Download Code Disconnect Exit Connected display success 6 4 sec Figure 4 2 Displaying selected image file on VGA Monitor 4 3 Video Capture Choosing the Capture tab leads to the window in Figure 4 3 The function is designed to capture an image from the video sources and sent the image from the FPGA board to the host computer The input video source can be PAL or NTSC signals Please follow the steps below to capture an image from a video source l Connect a video source such as a VCD DVD player or NTSC PAL camera to VIDEO IN 1 or VIDEO IN 2 port on the board Specify Video Source as VIDEO IN 1 or VIDEO IN 2 3 Click Capture button to start capturing process Then you will see the captured image shown in the display window of the Video Utility The image dimension of the captured image is also displayed 4 Users can click Save button to save the captured image as a bitmap or jpeg file 27 DE2 70 User Manual Video Utility V1 0 0 Display Capture Video Source VIDEO IN 1 Dimension 720x576 Save Capture Download Cade Di
27. 70 User Manual AN RYA data to the audio chip or receive audio data from the audio chip The audio chip is programmed through I2C protocol which is implemented in C code The PC pin from audio chip is connected to SOPC System Interconnect Fabric through PIO controllers In this example the audio chip 15 configured in Master Mode The audio interface is configured as I2S and 16 bit mode A 18 432MHz clock generated by the PLL is connected to the XTI MCLK pin of the audio chip through the AUDIO Controller 50M Hz Store DIEN Audio RESE N SDRAM Data SRAM SRAM Nios II JTAG Controller Pro gram UART PIO 3 LED KEY SW I2C LCD un e un gt 3 p 5 5 5 e 55 T lar mi e NV LCD ML 5 Controller SDRAM SEG7 SRAM NV SEG7 Controller AUDIO AUDIO Controller Figure 6 19 Block diagram of the audio recorder and player Demonstration Setup File Locations and Instructions e Hardware Project directory DE2 70 AUDIO e Bit stream used DE2P_TOP sof e Software Project directory DE2 70 AUDIONsoftwareNproject audio e Software Execution File DE2 70 AUDIONsoftwareNproject auidoNaudioMebug audio elf Connect an Audio Source to the LINE IN port of the DE2 70 board e Connect a Microphone to MIC IN port on the DE2 70 board e Connect a speaker or headset to LINE OUT port on the DE2 70 board e Load the bit stream into FPGA note 1 e Load the Software Execution File in
28. 70 VIGGO U Ulf y u 25 4 1 vid o UO ee 25 E E ae 26 4 3 iuis ee ee ee ee 27 4 4 Overall Structure of the DE2 70 Video Utility esses 28 Chapter 5 Using the DE2 70 Board vs 30 5 1 1 30 02 Wess the LEDs STE Sy CCS 32 53 Usine the SCC DD PIE enter 36 34 ON Tel m 38 5 5 Ms tie LED Module CT 40 20 Using the Expansion Header nun ea 41 5 7 USE VOR 9n H 45 5 8 Usine ine 247b t AUDIO CODEC consist quU eurer 48 5 0 11202928 Persi P 6 RR E DO EO TT DIT 49 S0 uocum ipm sd OIM 49 5 11 Fast Ethernet Network Controller eeeeeeeeessssessseeeeeeeeeeeeeen nennen eene 50 Altera DE2 70 Board 12 IV DEI ee a ee 52 2419 54 SM MES uris BP EU UU UTE 55 S USE EP E 57 516 UsneSDRAM SRAM ElASh 2 0 0 neun 58 Chapter 6 Examples of Advanced Demonstrations 222 999 9 eere eee eee 999 9 66 996 66 6 1 DE2 70 Factory UT All OM en een 66 6 2 Quartus II 9 1 amp Nios TE EDS near aachen 67 6 3 IV 67 6
29. DE2 70 User Manual TD1_CLK27 PIN_G15 TV Decoder 1 Clock Input Table 5 16 TV Decoder pin assignments 5 13 Implementing a TV Encoder Although the DE2 70 board does not include a TV encoder chip the ADV7123 10 bit high speed triple ADCs can be used to implement a professional quality TV encoder with the digital processing part implemented in the Cyclone II FPGA Figure 5 19 shows a block diagram of a TV encoder implemented in this manner TV Encoder Block Cyclone II 2C70 O Composite Y U cos V sin or Y S Video or RCA Y C U cos V sin DSP Block Clock Sync Calculate Timing Gen Composite Y S SIN COS V x Tables or RCA Pb Figure 5 19 A TV Encoder that uses the Cyclone II FPGA and the ADV7123 54 DE2 70 User Manual 5 14 Using USB Host and Device The DE2 70 board provides both USB host and device interfaces using the Philips ISP1362 single chip USB controller The host and device controllers are compliant with the Universal Serial Bus Specification Rev 2 0 supporting data transfer at full speed 12 Mbit s and low speed 1 5 Mbit s Figure 5 20 shows the schematic diagram of the USB circuitry the pin assignments for the associated interface are listed in Table 5 17 Detailed information for using the ISP1362 device 15 available in its datasheet and programming guide both documents can be found on the manufacturer s web site or in the Datasheet USB folder
30. DRAM Frame Buffer and a field selection multiplexer MUX which is udio lled by the VGA controller to perform the de interlacing operation Internally the VGA Controller generates data request and odd even selected signals to the SDRAM Frame Buffer and filed selection multiplexer MUX The YUV422 to YUV444 block converts the selected YcrCb 4 2 2 YUV 4 2 2 video data to the YcrCb 4 4 4 YUV 4 4 4 video data format Finally the YcrCb to RGB block converts the YcrCb data into RGB output The VGA Controller block generates standard VGA sync signals VGA_HS and VGA_VS to enable the display on a VGA monitor SDRAM TD_DATA Frame ecoder Data Valid Buffer Request Initiation an Delay Bun Timer DLY2 VGA VGA gt Controller VGA_HS DAC jn Decoder VGA_VS 7123 7180 TD_HS ER To Control the ea e TD VS Initiation ce Detector Sequence m gt DC SCLK YUV 4 2 2 YCbCr 3 DC AV To Ez it gt Config YUV 4 4 4 RGB Figure 6 2 Block diagram of the TV box demonstration Demonstration Setup File Locations and Instructions e Project directory DE2 70 TV Bitstream used DE2 70 TV sof or DE2 70 TV pof Connect a DVD player s composite video output yellow plug to the
31. F and TONE GENERATOR The DEMO SOUND block stores a demo sound for user to play 52 KEYBOARD handles the users input from PS 2 keyboard The STAFF block draws the corresponding keyboard diagram on VGA monitor when key s are pressed The TONE GENERATOR is the core of music synthesizer SOC User can switch the music source either from PS2 KEYBOAD or the DEMO SOUND block using SW9 To repeat the demo sound users can press KEYI The TONE GENERATOR has two tones 1 String 2 Brass which can be controlled by SWO The audio codec used on the DE2 70 board has two channels which can be turned ON OFF using and SW2 Figure 6 17 illustrates the setup for this demonstration CYCLONE Il 2070 a HS vs DEMO1 CODE Zr SOUND Demo2 CODE m R DAC GAG VGAB SOUND1 CODE MUX STAFF SOUND2 CODE SOUND KEY1 CODE SOUND2 mm KEY2 CODE SOUND1 orr GENERATOR CODEC SOUND2 OFF SW 9 SW 0 SW 2 1 Figure 6 17 Block diagram of the Music Synthesizer design 85 DE2 70 User Manual Demonstration Setup File Locations and Instructions e Project directory DE2 70 Synthesizer e Bit stream used DE2 70 Synthesizer sof or DE2 70 Synthesizer pof e Connect a PS 2 Keyboard to the DE2 70 board Connect the VGA output of the DE2 70 board to a VGA monitor both LCD and CRT type of monitors should work e Connect the Lineout of the DE2 70 board to a speaker e Load the bit stream into FPGA e Make sure all the switches S
32. Figure 6 15 Software Stack of the SD music player demonstration The audio chip should be configured before sending audio signal to the audio chip The main program uses I2C protocol to configure the audio chip working in master mode the audio interface as I2S with 16 bits per channel and sampling rate according to the wave file content In audio playing loop the main program reads 512 byte audio data from the SD card and then writes the data to DAC FIFO in the Audio Controller Before writing the data to the FIFO the program have to make sure the FIFO 15 not full The design also mixes the audio signal from the microphone in and line in for the Karaoke style effects by enabling the BYPASS and SITETONE functions in the audio chip Finally users can obtain the status of the SD music player from the 2x16 LCD module the 7 segment display and the LEDs The top and bottom row of the LCD module will display the file name of the music that 15 playing on the DE2 70 board and the value of music volume respectively The 7 segments display will show how long the music file has been played The LED will indicate the audio signal strength Demonstration Setup File Locations and Instructions e Project directory DE2 70 SD Card Audio Player e Bit stream used DE2 70 SD Card Audio Player sof e Nios II Workspace DE2 70 SD Card Audio PlayerNSoftware e Format your SD card into FAT 6 format e Put the played wave files to the root directory of the
33. Headers with diode protection In addition to these hardware features the DE2 70 board has software support for standard I O interfaces and a control panel facility for accessing various components Also software 1s provided for a number of demonstrations that illustrate the advanced capabilities of the DE2 70 board In order to use the DE2 70 board the user has to be familiar with the Quartus II software The necessary knowledge can be acquired by reading the tutorials Getting Started with Altera s DE2 70 Board and Quartus II Introduction which exists in three versions based on the design entry method used namely Verilog VHDL or schematic entry These tutorials are provided in the directory DE2 70 tutorials on the DE2 70 System CD ROM that accompanies the DE2 70 board and can also be found on Altera s DE2 70 web pages 2 2 Block Diagram of the DE2 70 Board Figure 2 2 gives the block diagram of the DE2 70 board To provide maximum flexibility for the user all connections are made through the Cyclone II FPGA device Thus the user can configure the FPGA to implement any system design DE2 70 User Manual 50Mhz 28Mhz Ext In USB 2 0 Host Device 24 bit Audio CODEC 10 100 Ethernet PHY MAC XSGA 10 bit Video DAC SD Card TV Decoder 2 Cyclone Il FPGA IrDA Transceiver User Green LEDs 9 Flash 8 Mbyte User Red LEDs 18 20 0 SDRAM 64 Mbyte SRAM 2 Mbyte 7 SEG Display 8 Expansion Headers 2 EPCS16 USB
34. K PIN_G18 Audio CODEC DAC LR Clock Table 5 12 Audio CODEC pin assignments 48 DE2 70 User Manual 59 RS 232 Serial Port The DE2 70 board uses the ADM3202 transceiver chip and a 9 pin D SUB connector for RS 232 communications For detailed information on how to use the transceiver refer to the datasheet which is available on the manufacturer s web site or in the Datasheet RS232 folder on the DE2 70 System CD ROM Figure 5 15 shows the related schematics and Table 5 13 lists the Cyclone II FPGA pin assignments RXD LEDR R44 330 AX UART RXD VCC33 TXD LEDG R45 330 AX UART TXD U7 ART RXD RxD I a SEE TEE jj OUT DI te 7 E R2OUT R2IN 53 gt s UART TXD 14 DD 1 UART CTS 0 6 gt 9 1u C 4 YF ADM3202 RS232 C2 5033 Figure 5 15 MAX232 RS 232 chip schematic UART_RXD PIN D21 UART Receiver UART_TXD PIN E21 UART Transmitter UART CTS PIN G22 UART Clear to Send UART RTS PIN F23 UART Request to Send Table 5 13 RS 232 pin assignments 5 10 PS 2 Serial Port The DE2 70 board includes a standard PS 2 interface and a connector for a PS 2 keyboard or mouse In addition users can use the PS 2 keyboard and mouse on the DE2 70 board simultaneously by an plug an extension PS 2 Y Cable Figure 5 16 shows the schematic of the PS 2 circuit Instructions for using a PS 2 mouse or keyboard can be found by performing an appropriate search on various educational web sites The
35. LCD is used to indicate the Recording Playing status The seg7 is used to display Recording Playing duration with time unit in 1 100 second The LED 15 used to indicate the audio signal strength Table 6 4 summarizes the usage of toggle switches for configuring the audio recorder and player EJ Ei Jm Hl AE ml mun A roe terme AAA cul E Bs FINES mam 218 wa i i er xr 2515 er Bir 7277 NM oo En 1 1 NI m zc ES amma m ma mms ET TEXSEEME m UE Lc uie n ENT n m a TOF BBC AH Carrs eri tiie Record Play Status UTE mi f ao a F Y x e Record Play Duration Signal Strength Play Sample rate Record Audio Source MIC Boost Zero Cross Detect Figure 6 18 Man Machine Interface of Audio Recorder and Player Figure 6 19 shows the block diagram of the design of the Audio Recorder and Player There are hardware part and software part in the block diagram The software part means the Nios II program that stored in SSRAM The software part is built by Nios II IDE in C programming language The hardware part is built by SOPC Builder under Quartus II The hardware part includes all the other blocks The AUDIO Controller is a user defined SOPC component It is designed to send audio 88 PIG DE2
36. O u AO IO_CLKINpO A1 BATS4S l 548 IO_AG Q uh 10 lO A7 f VRR Ta Co o aa lO A9 GPIO Do R51 47 A0 RA o 01416 G AN GPIO D1 R52 47 Ai E I o 18 DESC _ nn YyY CLKOUTnO O 20l A14 CLKOUTpO 22 lO A15 E REACH iO A20 Eon os lO A21 protection registors and diodes cu 285 98 28 iO A22 a O A23 A24 34 25 not shown for other ports A4 Co of asl 6 A A28 aolas 29 O A30 Meier A31 BOX Header 2X20M VCCIO5 VCCIO5 GPIO 1 GPIO D32 JS IO CLKINn1 aP BO CLKINp1 4 lO B1 al BAI lO B2 Fr B3 5 86 OE E Ps 0 2 VCC5 O OO ERES N ups ea a 3 IRSE een CLKOUTnh 19 o o 20 iO B14 OB al 0 0 1 _ oars e O O 8 O_B18 5 o 1 26 IO B19 protection registors and diodes 0 b18 EISE EI VCC33 I J not shown for other ports OB Fest om lO B24 5 o 3a lO B25 lO B26 IO 27 28 5 o 36 IO_B29 IO B30 o l o o 40 IO CJ O x ak D je m M N e Figure 5 11 Schematic diagram of the expansion headers 42 DE2 70 User Manual 3 A DE2 70 User Manual IO B 0 PIN G27 GPIO Connection 1 IO 0 Table 5 8 Pin assignments for the expansion headers D 4 DE2 70 User Manual 5 7 Using VGA The DE2 70 board includes a 16 pin D SUB connector for VGA output The VGA synchronization
37. OWN closest to the edge of the DE2 70 board position and logic 1 when in the UP position Clock inputs e 50 MHz oscillator e 28 62 MHZz oscillator e SMA external clock input DE2 70 User Manual Audio CODEC e Wolfson WM8731 24 bit sigma delta audio CODEC e Line level input line level output and microphone input jacks e Sampling frequency 8 to 96 KHz e Applications for MP3 players and recorders PDAs smart phones voice recorders etc VGA output e Uses the ADV7123 140 MHz triple 10 bit high speed video DAC e With 15 pin high density D sub connector e Supports up to 1600 x 1200 at 100 Hz refresh rate e Can be used with the Cyclone II FPGA to implement a high performance TV Encoder NTSC PAL SECAM TV decoder circuit Uses two ADV7180 Multi format SDTV Video Decoders e Supports worldwide NTSC PAL SECAM color demodulation One 10 bit ADC 4X over sampling for CVBS e Supports Composite Video CVBS RCA jack input e Supports digital output formats 8 bit ITU R BT 656 YCrCb 4 2 2 output HS VS and FIELD Applications DVD recorders LCD TV Set top boxes Digital TV Portable video devices and TV PIP picture in picture display 10 100 Ethernet controller e Integrated MAC and PHY with a general processor interface e Supports IOOBase T and 10Base T applications e Supports full duplex operation at 10 Mb s and 100 Mb s with auto MDIX Fully compliant with the IEEE 802 3u Specification e Supports IP TCP UDP checksum g
38. PGA at any time and it 15 also possible to change the non volatile data that 15 stored in the serial EEPROM chip Both types of programming methods are described below 1 JTAG programming In this method of programming named after the IEEE standards Joint Test Action Group the configuration bit stream 15 downloaded directly into the Cyclone II FPGA The FPGA will retain this configuration as long as power 15 applied to the board the configuration 15 lost when the power 15 turned off 2 AS programming In this method called Active Serial programming the configuration bit stream is downloaded into the Altera EPCS16 serial EEPROM chip It provides non volatile storage of the bit stream so that the information 15 retained even when the power supply to the DE2 70 board 15 turned off When the board s power is turned on the configuration data in the EPCS16 device is automatically loaded into the Cyclone II FPGA The sections below describe the steps used to perform both JTAG and AS programming For both methods the DE2 70 board is connected to a host computer via a USB cable Using this connection the board will be identified by the host computer as an Altera USB Blaster device The process for installing on the host computer the necessary software device driver that communicates with the USB Blaster is described in the tutorial Getting Started with Altera s DE2 70 Board This tutorial is available on the DE2 70 System CD ROM 30 DE2 70 User
39. SDRAM to SSRAM through the Multi Port SSRAM controller 4 VGA Controller continuously reads the raw image data from the SSRAM and sends them to the VGA port The control flow for video capturing is described below 1 Host computer issues a capture command to Nios II processor 2 Nios II processor interprets the command and controls Video In controller to capture the raw image data into the SSRAM After capturing 15 done Nios II processor copies the raw image data from the SSRAM to SDRAM U2 3 Host computer reads the raw image data from the SDRAM U2 Host computer converts the raw image data to RGB color space and displays it 29 DE2 70 User Manual Chapter 5 Using the DE2 70 Board This chapter gives instructions for using the DE2 70 board and describes each of its I O devices 5 1 Configuring the Cyclone II FPGA The procedure for downloading a circuit from a host computer to the DE2 70 board is described in the tutorial Quartus II Introduction This tutorial 15 found in the DE2 70 tutorials folder on the DE2 70 System CD ROM The user is encouraged to read the tutorial first and to treat the information below as a short reference The DE2 70 board contains a serial EEPROM chip that stores configuration data for the Cyclone II FPGA This configuration data 1s automatically loaded from the EEPROM chip into the FPGA each time power is applied to the board Using the Quartus II software it is possible to reprogram the F
40. W 9 0 are set to 0 Down Position Press KEYI on the DE2 70 board to start the music demo e Press KEYO on the DE2 70 board to reset the circuit Table 6 2 and 6 3 illustrate the usage of the switches pushbuttons KEYs PS 2 Keyboard e Switches and Pushbuttons KEYIO Reset Circuit Table 6 2 Usage of the switches pushbuttons KEYS e PS 2 Keyboard DE2 70 User Manual Table 6 3 Usage of the PS 2 Keyboard s keys Oer Line Out Keyboard Input LI 1111 T1 TAE T T T A Aa hi i m n LRL PII dove N CES MET p L a bed bud Figure 6 16 The Setup of the Music Synthesizer Demonstration 87 DE2 70 User Manual 6 11 Audio Recording and Playing This demonstration shows how to implement an audio recorder and player using the DE2 70 board with the built in Audio CODEC chip This demonstration is developed based on SOPC Builder and NIOS II IDE Figure 6 18 shows the man machine interface of this demonstration Two push buttons and six toggle switches are used for users to configure this audio system SWO is used to specify recording source to be Line in or MIC In SW1 is to enable disable MIC Boost when the recoding source is MIC In SW2 is used to enable disable Zero Cross Detection for audio playing SW3 SW4 and SW5 are used to specify recording sample rate as 96K 48K 44 1K 32K or 8K The 16x2
41. ag of six rubber silicon covers for the DE2 70 board stands The bag also contains some extender pins which can be used to facilitate easier probing with testing equipment of the board s I O expansion headers Clear plastic cover for the board 12V DC wall mount power supply The DE2 70 Board Assembly To assemble the included stands for the DE2 70 board Assemble a rubber silicon cover as shown in Figure 1 2 for each of the six copper stands on the DE2 70 board The clear plastic cover provides extra protection and is mounted over the top of the board by using additional stands and screws F Figure 1 2 The feet for the DE2 70 board 1 3 Here are the addresses where you can get help f you encounter problems Getting Help Altera Corporation 101 Innovat on Drive San Jose California 95134 USA Email university altera com Terasic Technologies No 356 Sec 1 Fusing E Rd Jhubei City HsinChu County Taiwan 302 Email support terasic com Web DE2 70 terasic com DE2 70 User Manual DE2 70 User Manual Chapter 2 Altera DE2 70 Board This chapter presents the features and design characteristics of the DE2 70 board 2 1 Layout and Components A photograph of the DE2 70 board is shown in Figure 2 1 It depicts the layout of the board and indicates the location of the connectors and key components Ethernet 10 100M Port USB Device Port Micin Lineln Line Out VGA Out RS 232 Port USB Blast
42. anel The DE2 70 Control Panel is based on a NIOS II system running in the Cyclone II FPGA with the SDRAM U2 or SSRAM The software part is implemented in C code the hardware part 15 implemented in Verilog code with SOPC builder which makes it possible for a knowledgeable user to change the functionality of the Control Panel The code is located inside the DE2_70_demonstrations directory on the DE2 System CD ROM To run the Control Panel users must first configure it as explained in Section 3 1 Figure 3 13 depicts the structure of the Control Panel Each input output device is controlled by the NIOS I Processor instantiated in the FPGA chip The communication with the PC is done via the USB Blaster link The NIOS II interprets the commands sent from the PC and performs the corresponding actions 23 DE2 70 User Manual SEG7 Controller T SEG Display SDRAM Controller SDRAM U1 Nios IT LCD Controller LCD USB Controller omms USB Mouse PS2 Controller c PS2 Keyboard PIO Controller LED Button FPGA SOPC NIOSI TIMER k s JTAG lt gt Blaster JTAG Hardware III Switch Seg7 SD Card Avalon MM Flash N Tristate Bridge gt Controller Flash 911181 329uu02J9 UT 5 N E eu SSRAM Pos 3 Tri state Bridge gt Controller L ogram Figure 3 13 The block diagram of the DE2 70 co
43. ble from the host computer to the USB Blaster connector on the DE2 70 board For communication between the host and the DE2 70 board it is necessary to install the Altera USB Blaster driver software If this driver 1s not already installed on the host computer it can be installed as explained in the tutorial Getting Started with Altera s DE2 70 Board This tutorial is available in the directory DE2 70 tutorials on the DE2 70 System CD ROM Connect the 12V adapter to the DE2 70 board Connect a VGA monitor to the VGA port on the DE2 70 board Connect your headset to the Line out audio port on the DE2 70 board Turn the RUN PROG switch on the left edge of the DE2 70 board to RUN position the PROG position 15 used only for the AS Mode programming 6 Turn the power on by pressing the ON OFF switch on the DE2 70 board nA A U N DE2 70 User Manual At this point you should observe the following All user LEDs are flashing All 7 segment displays are cycling through the numbers 0 to F The LCD display shows Welcome to the Altera DE2 70 The VGA monitor displays the image shown in Figure 2 3 Set the toggle switch SW17 to the DOWN position you should hear a 1 kHz sound Set the toggle switch SW17 to the UP position and connect the output of an audio player to the Line in connector on the DE2 70 board on your headset you should hear the music played from the audio player MP3 PC iPod or the like You can also connect a microphone to the Micr
44. ctly to 36 pins of the Cyclone II FPGA and also provides DC 5V VCC5 DC 3 3V VCC33 and two GND pins Among these 36 I O pins 4 pins are connected to the PLL clock input and output pins of the FPGA allowing the expansion daughter cards to access the PLL blocks in the FPGA The voltage level of the I O pins on the expansion headers can be adjusted to 3 3V 2 5V or 1 8V using Because the expansion I Os are connected to the BANK 5 of the FPGA and the VCCIO voltage VCCIOS of this bank is controlled by the header JP1 users can use a jumper to select the input voltage of VCCIOS to 3 3V 2 5V and 1 8V to control the voltage level of the I O pins Table 5 7 lists the jumper settings of the JP1 The pin outs of the JP1 appear in the Figure 5 10 Finally Figure 5 11 shows the related schematics Each pin on the expansion headers is connected to two diodes and a resistor that provide protection from high and low voltages The figure shows the protection circuitry for only two of the pins on each header but this circuitry 15 included for all 72 data pins Table 5 8 gives the pin assignments 41 DE2 70 User Manual Short Pins 1 and 2 Short Pins 3 and 4 Short Pins 5 and 6 Table 5 7 Voltage level setting of the expansion headers using 18V 2 5V 3 3V 2 4 o JP1 e Un Figure 5 10 JPI pin settings VCCIO5 GPIO 0 J4 IO_CLKINn
45. eneration and checking e Supports back pressure mode for half duplex mode flow control USB Host Slave controller e Complies fully with Universal Serial Bus Specification Rev 2 0 e Supports data transfer at full speed and low speed e Supports both USB host and device e Two USB ports one type A for a host and one type B for a device e Provides a high speed parallel interface to most available processors supports Nios II with a Terasic driver e Supports Programmed I O PIO and Direct Memory Access DMA DE2 70 User Manual Serial ports e One RS 232 port e One PS 2 port DB 9 serial connector for the RS 232 port e PS 2 connector for connecting a PS2 mouse or keyboard to the DE2 70 board IrDA transceiver e Contains a 115 2 kb s infrared transceiver e 32mA LED drive current e Integrated EMI shield e EC825 1 Class 1 eye safe Edge detection input Two 40 pin expansion headers 72 Cyclone II I O pins as well as 8 power and ground lines are brought out to two 40 pin expansion connectors e 40 pin header is designed to accept a standard 40 pin ribbon cable used for IDE hard drives e Diode and resistor protection 15 provided 2 3 Power up the DE2 70 Board The DE2 70 board comes with a preloaded configuration bit stream to demonstrate some features of the board This bit stream also allows users to see quickly if the board is working properly To power up the board perform the following steps l Connect the provided USB ca
46. er Port USB Host Port Video In 1 Video In 2 1 ig m L fl if i U dnm If nl nami v i n 9 nn b 06 4 BA eet TV Decoder NTSC PAL X2 V J 12V DC Power Supply riea 1 ED pem onda Le ea A ORT TE mt MAPS 4 lt gt PS2 Port Connector e WT 7 mnm g N jm or 0 ee U 5 Tim gx IPM d 2 j zum amp id in VGA 10 bit DAC Power ON OFF Switch 7 5I UE ime i I4 Siar B uud BR mt TD 2o ERN Ethernet 10 100M Controller USB Host Slave ee 8 2 P a em gt r Controller i i aec EA qi Fey AD mum mus Audio CODEC E im mimm e vig ANhLLO 2 90 Altera USB Blaster oe 50Mhz Oscillator Controller chipset WANNLY Ih nm Expansion Header 2 Altera EPCS16 Kr p sr LCD MOULE 2X16 Configuration Device Expansion Header 1 I I IA x aa EP2C70F896C6N K CABSTO731A KOREA M Tl RUN PROG Switch for 3 allie i eb ROG Switch for 5 E MEE ter HIS 4 SD Card Slot wuwsterasic com SD Card Not Included HH mpg umm su v Altera Cyclone m J EE FPCA with 70K LEs 16x2 LCD Module www altera com OALTERA uui que E 1 IrDA Transceiver 7 Segment Displays 8Mbyte Flash Memory RNII RHIO n J 5 Sor 126 LU Sass ERS Dail md LEORIS C LEDRI UNT LORS i Lt LEDR LEDRS LH LEDR3 T LEDRO tt LEDS LEDA 1063 11 5
47. et Memor www LEPBBIE COIT About SDRAM U2 Download Code Disconnect Exit Connected i Sandan Code success Figure 3 1 The DE2 70 Control Panel The concept of the DE2 70 Control Panel is illustrated in Figure 3 2 The Control Codes that performs the control functions is implemented in the FPGA board It communicates with the Control Panel window which is active on the host computer via the USB Blaster link The graphical interface is used to issue commands to the control codes It handles all requests and performs data transfers between the computer and the DE2 70 board 12 DE2 70 User Manual 7 SEG Display USB Blaster A R Control PS 2 Codes USB Device SD Card Soket LEDs Figure 3 2 The DE2 70 Control Panel concept The DE2 70 Control Panel can be used to light up LEDs change the values displayed on 7 segment and LCD displays monitor buttons switches status read write the SDRAM SSRAM and Flash Memory monitor the status of an USB mouse read data from a PS 2 keyboard and read SD CARD specification information The feature of reading writing a word or an entire file from to the Flash Memory allows the user to develop multimedia applications Flash Audio Player Flash Picture Viewer without worrying about how to build a Memory Programmer 32 Controlling the LEDs 7 Segment Displays and LCD Display A simple function of the Control Pane
48. g on the ADD and Clear buttons 76 DE2 70 User Manual Figure 6 9 illustrates the setup for this demonstration DEZ2 OIX a p 5 565 3 pone FE BB 133333333 5865655565 ocoO0oO0O00000000000000037 DD 22 0 2 0 20 2 0 20 DD i E i i 39333 333333 8333333353 KERLE EEE EEE EEE 55566 USB Driver Figure 6 9 The setup for the USB device demonstration 6 7 A Karaoke Machine This demonstration uses the microphone in line in and line out ports on the DE2 70 board to create a Karaoke Machine application The Wolfson WM8731 audio CODEC is configured in the master mode where the audio CODEC generates AD DA serial bit clock BCK and the left right channel clock LRCK automatically As indicated in Figure 6 10 the I2C interface is used to configure the Audio CODEC The sample rate and gain of the CODEC are set in this manner and the data input from the line in port is then mixed with the microphone in port and the result is sent to the line out port For this demonstration the sample rate is set to 48 kHz Pressing the pushbutton reconfigures the gain of the audio CODEC via the I2C bus cycling through one of the ten predefined gains volume levels provided by the device 77 DE2 70 User Manual I2C Audio Line out Configuration Push Button Bypass Mic in ADC to DAC Figure 6 10 Block diagram of the Karaoke Machine demonstrat
49. g the LCD tab leads to the window in Figure 3 5 Text can be written to the LCD display by typing it in the LCD box and pressing the Set button ALTERA TERAS IC Froduct Name DE 70 http www altera com Tasic Target Memor i www LeFasIC COM About SDRSM U2 Download Code Disconnect Exit Connected Set LCD Success Figure 3 5 Controlling LEDs and the LCD display The ability to set arbitrary values into simple display devices is not needed in typical design activities However it gives the user a simple mechanism for verifying that these devices are functioning correctly in case a malfunction is suspected Thus it can be used for troubleshooting purposes 33 Switches and Buttons Choosing the Button tab leads to the window in Figure 3 6 The function is designed to monitor the status of switches and buttons in real time and show the status in a graphical user interface It can be used to verify the functionality of the switches and buttons Press the Start button to start button switch status monitoring process and button caption is changed from Start to Stop In the monitoring process the status of buttons and switches on the board is shown in the GUI window and updated in real time Press Stop to end the monitoring process 15 DE2 70 User Manual LED 7 SEG LCD Button Memory USB PS2 SD CARD Audio Buttoni Switch pos u p ch sew na UR hittp www altera com
50. his interesting audio tool is designed to control the audio chip on the DE2 70 board for audio playing and recording It can play audio stored in a given WAVE file record audio and save the audio signal as a wave file The WAVE file must be uncompressed stereo 2 channels per sample and 16 bits per channel Its sample rate must be either 96K 48K 44 1K 32K or 8K Follow the steps below to exercise this tool WwW N e Choosing the Audio tab leads to the window in Figure 3 11 To play audio plug a headset or speaker to the LINE OUT port on the board Select the Play Audio item in the com box as shown in Figure 3 11 Click Open Wave to select a WAVE file The waveform of the specified wave file will be displayed in the waveform window The sampling rate of the wave file also is displayed in the Sample Rate Combo Box You can drag the scrollbar to browse the waveform In the waveform window the blue line represents left channel signal and green line represents right channel signal Click Start Play to start audio play The program will download the waveform to SDRAM UI configure the audio chip for audio playing and then start the audio playing process You will hear the audio sound from the headset or speaker To stop the audio playing simply click Stop Play 21 DE2 70 User Manual LED 7 SEG LCD Button Memory USB PS2 SD CARD Audio Audia Play gt http www altera com Sample
51. in the DE2 70 demonstrations folder from the DE2 70 System CD ROM For each of demonstrations described in the following sections we give the name of the project directory for its files which are subdirectories of the DE2 70 demonstrations folder Installing the Demonstrations To install the demonstrations on your computer perform the following 1 Copy the directory DE2 70 demonstrations into a local directory of your choice It is important to ensure that the path to your local directory contains no spaces otherwise the Nios II software will not work 6 1 DE2 70 Factory Configuration The DE2 70 board is shipped from the factory with a default configuration that demonstrates some of the basic features of the board The setup required for this demonstration and the locations of its files are shown below Demonstration Setup File Locations and Instructions e Project directory DE2 70 Default e Bit stream used DE2 70 Default sof or DE2 70 Default pof e Power on the DE2 70 board with the USB cable connected to the USB Blaster port If necessary that 1s if the default factory configuration of the DE2 70 board is not currently stored in EPCS16 device download the bit stream to the board by using either JTAG or AS programming e You should now be able to observe that the 7 segment displays are displaying a sequence of characters and the red and green LEDs are flashing Also Welcome to the Altera DE2 70 is shown on the LCD
52. ion Demonstration Setup File Locations and Instructions e Project directory DE2 70_i2sound e Bit stream used DE2 70_i2sound sof or DE2 70_i2sound pof e Connect a microphone to the microphone in port pink color on the DE2 70 board e Connect the audio output of a music player such as an MP3 player or computer to the line in port blue color on the DE2 70 board e Connect a headset speaker to the line out port green color on the DE2 70 board e Load the bit stream into the FPGA e You should be able to hear a mixture of the microphone sound and the sound from the music player e Press KEYO to adjust the volume it cycles between volume levels 0 to 9 78 DE2 70 User Manual Figure 6 11 The setup for the Karaoke Machine 6 5 Ethernet Packet Sending Receiving In this demonstration we will show how to send and receive Ethernet packets using the Fast Ethernet controller on DE2 70 board As illustrated in Figure 6 12 we use the Nios II processor to send and receive Ethernet packets using the DM9000A Ethernet PHY MAC Controller The demonstration can be set up to use either a loop back connection from one board to itself or two DE2 70 boards connected together On the transmitting side the Nios II processor sends 64 byte packets every 0 5 seconds to the DM9000A After receiving the packet the DM9000A appends a four byte checksum to the packet 79 DE2 70 User Manual and sends it to the Ethernet port On the receivi
53. isplays and also on the green LEDs If 75 DE2 70 User Manual the user clicks on the Clear button in the window panel of the software driver the host computer sends a different USB packet to the board which causes the Nios II processor to clear the hardware counter to zero Link to Host PC 1 Nios Il Setup Package CRUD a Philips Enumeration Information pilin HostPC Port SEG LEDs Communication Figure 6 8 Block diagram of the USB device demonstration Demonstration Setup File Locations and Instructions e Project directory DE2_70_NIOS_DEVICE_LED HW e Bit stream used DE2 70 NIOS DEVICE LED sof e Nios II Workspace DE2 70 NIOS DEVICE LEDNHWASoftware e Borland BC Software Driver DE2 70 NIOS DEVICE LEDNSW Connect the USB Device connector of the DE2 70 board to the host computer using a USB cable type A B Load the bit stream into FPGA e Run Nios II IDE with DE2 70 NIOS DEVICE LEDNHWASoftware as the workspace Click on Run A new USB hardware device will be detected Specify the location of the driver as DE2 70 NIOS DEVICE LED DiI2testinf Philips PDIUSBDI2 SMART Evaluation Board Ignore any warning messages produced during installation The host computer should report that a Philips PDIUSBDI2 SMART Evaluation Board is now installed e Execute the software DE2 70 NIOS DEVICE LED SW ISP1362DcUsb exe on the host computer Then experiment with the software by clickin
54. itt Trigger Debounced e a Figure 5 3 Switch debouncing 32 DE2 70 User Manual There are also 18 toggle switches sliders on the DE2 70 board These switches are not debounced and are intended for use as level sensitive data inputs to a circuit Bach switch 15 connected directly to a pin on the Cyclone II FPGA When a switch is in the DOWN position closest to the edge of the board it provides a low logic level 0 volts to the FPGA and when the switch 15 in the UP position it provides a high logic level 3 3 volts There are 27 user controllable LEDs on the DE2 70 board Eighteen red LEDs are situated above the 18 toggle switches and eight green LEDs are found above the pushbutton switches the 9 green LED is in the middle of the 7 segment displays Each LED is driven directly by a pin on the Cyclone II FPGA driving its associated pin to a high logic level turns the LED on and driving the pin low turns it off A schematic diagram that shows the pushbutton and toggle switches 15 given in Figure 5 4 A schematic diagram that shows the LED circuitry appears in Figure 5 5 A list of the pin names on the Cyclone II FPGA that are connected to the toggle switches 1s given in Table 5 1 Similarly the pins used to connect to the pushbutton switches and LEDs are displayed in Tables 5 2 and 5 3 respectively OVCC33 KEYO KEY1 KEY2 KEY3 pg MEYINE 6 b e LL KEYINS C13 C14 C15 C16 BUTTONO TOF Q 9
55. l is to allow setting the values displayed on LEDs 7 segment displays and the LCD character display Choosing the LED tab leads to the window in Figure 3 3 Here you can directly turn the individual LEDs on or off by selecting them or click Light All or Unlight All 13 ag MILEDGO viLEDG1 MILEDG2 MILEDGS MILEDG4 MILEDGS i LEDGE wiLEDG MiLEDGS Product Name DE 70 MiLEDRO wiLEDR1 viLEDR2 viLEDR3 viLEDR4 MILEDRS Light Al Unlight All http www altera com T1jasiC Target Me Wo vy Taras pom Connected Set Led 5 Success Figure 3 3 Choosing the 7 SEG tab leads to the window in Figure 3 4 In the tab sheet directly use the Up Down control and Dot Check box to specified desired patterns the 7 SEG patterns on the board will be updated immediately sni Panel 17 0 0 LED rf SEG mor About ISDRAM LI2 Download Code Controlling LEDs viLEDRB vILEDR ILEDRS wiLEDR8 viLEDRTO MILEDR11 wILEDR12 viLEDR13 MILEDR14 MILEDRIS LEDR16 MILEDR17 Disconnect Exit DE2 70 User Manual 4 dot det dot 7 der dot 7 det 7 ated sell sel bel sd Product Name DE 70 http www altera com Tasic Target M Me rior Www LET BEIG COM SDRAM U Download Lade Connected Set Led Success Disconnect Exit Figure 3 4 Controlling 7 SEG display 14 DE2 70 User Manual Choosin
56. l sub window Also users can select which video is displayed in main sub window via a toggle switch Figure 6 4 shows the basic block diagram of this demonstration There are three major blocks in the circuit called Composite_to_VGA PIP_Position_Controller and VGA_Multiplexer The Composite_to_VGA block consists all of the function blocks in the TV box demonstration project described in the section 6 3 The Composite_to_VGA block takes the video signals from the TV decoders as input and generate VGA interfaced signals as output The circuit in the FPGA is equipped with two Composite_to_VGA blocks converting the video signals from the TV decoder 1 and TV decoder 2 respectively To display two video signals in PIP mode on the LCD CRT monitor the output VGA data rate of the Composite_to_VGA block for the sub window must be two times as fast as the rate of the Composite_to_VGA block for the main window In addition the output timing of the VGA interface signal from the Composite_to_VGA block 15 controlled by the pip_position_controller block that determines the stating poison of the sub window Finally both of the two VGA interfaced signals will be multiplexed and sent to the LCD CRT monitor via the VGA_multiplexer block Video in 1 zu P TD data VGA data Composite_to TV decoder dn Ne PiP_position_ Sub window TD_clock Sub windon controller Control signal VGA data Sub VGA DAC
57. ng process the status of the USB mouse 15 updated and shown in the Control Panel s GUI window in real time Press Stop to terminate the monitoring process 18 DE2 70 User Manual ivy d i Tp nigi i L HIER yas S an mi Product Name DE 70 hittp www altera com 299 Y 215 L 1 Stop WV com Connected usb mause status checking Figure 3 8 USB Mouse Monitoring Tool 3 6 PS2 Device The Control Panel provides users a tool to receive the inputs from a PS2 keyboard in real time The received scan codes are translated to ASCII code and displayed in the control window Only visible ASCII codes are displayed For control key only Carriage Return ENTER key is implemented This function can be used to verify the functionality of the PS2 Interface Please follow the steps below to exercise the PS2 device Choosing the PS2 tab leads to the window in Figure 3 9 2 Plug a PS2 Keyboard to the FPGA board Then Press the Start button to start PS2Keyboard input receiving process Button caption 15 changed from Start to Stop 4 In the receiving process users can start to press the attached keyboard The input data will be displayed in the control window in real time Press Stop to terminate the monitoring process 19 DE2 70 User Manual LED 7 SEG LCD Button Memory USB PS2 SD CARD Audio Pg2 Keyboard Product Name DE 70 http ww
58. ng side the DM9000A checks every packet received to see if the destination MAC address in the packet is identical to the MAC address of the DE2 70 board If the packet received does have the same MAC address or is a broadcast packet the DM9000A will accept the packet and send an interrupt to the Nios II processor The processor will then display the packet contents in the Nios II IDE console window 64 Bytes Data 64 Bytes Data 4 Bytes Checksum nz 64 Bytes Data 4 Bytes Checksum Nios ll Interrupt Davicom CPU 4 DM9000A Read Data Ethernet 64 Bytes Data 4 Bytes Checksum a Figure 6 12 Packet sending and receiving using the Nios II processor Demonstration Setup File Locations and Instructions e Project directory DE2_70_NET e Bit stream used DE2_70_NET sof e Nios II Workspace DE2 70 NETNSoftware e Plug aCAT5 loop back cable into the Ethernet connector of DE2 70 Load the bit stream into the FPGA e Run the Nios II IDE under the workspace DE2 70 NETNSoftware Click on the Run button e You should now be able to observe the contents of the packets received 64 byte packets sent 68 byte packets received because of the extra checksum bytes 80 DE2 70 User Manual Figure 6 13 illustrates the setup for this demonstration 10 100Mbps CAT 5 Cable Loopback Device Ethernet Driver Figure 6 13 The setup for the Ethernet demonstration
59. nt display is controlled by the Seg 7 Controller which also is a user defined SOPC component Two PIO pins are connected to the I2C bus The I2C protocol is implemented by software Four PIO pins are connected to the SD CARD socket SD 1 Bit Mode 15 used to access the SD card and 15 implemented by software All of the other SOPC components in the block diagram are SOPC Builder built in components 100 MHZ Phase 65 deg SSRAM Chip SDRAM SDRAM Controller Chip Audio Socket 50 MHZ Audio Audio MIC In Controller Chip lt Line In Line Out System ID p UART PLL LCD Module Seg 7 Device SITE J 1281651811 uo EAYy Figure 6 14 Block diagram of the SD music player demonstration Figure 6 15 shows the software stack of this demonstration SD 1 Bit Mod block implements the SD 1 bit mode protocol for reading raw data from the SD card The FAT16 block implements FAT16 file system for reading wave files that stored in the SD card In this block only read function is implemented The WAVE Lib block implements WAVE file decoding function for receiving audio signal from wave files The 126 block implements PC protocol for configuring audio chip The SEG7 block implements displaying function for display elapsed playing time The Audio block implements audio FIFO checking function and audio signal sending receiving function 82 DE2 70 User Manual WAVE Lib FAT 16 SD 1 Bit Mode NIOS HAL
60. ntrol panel 24 DE2 70 User Manual Chapter 4 DE2 70 Video Utility The DE2 70 board comes with a video utility that allows users to access video components on the board from a host computer The host computer communicates with the board through the USB Blaster link The facility can be used to verify the functionality of video components on the board capture the video sent from the video in ports or display desired pattern on the VGA port This chapter first presents some basic functions of the Video Utility control panel then describes its structure in block diagram form and finally describes its capabilities 4 1 Video Utility Setup The Video Utility is located in the DE2 70 video utility folder in the DE2 70 System CD ROM To install it just copy the whole folder to your host computer Launch the Video Utility by executing the DE2 70 VIDEO exe Specific configuration files should be downloaded to your FPGA board before the Control Panel can request it to perform required tasks The configuration files include one sof file and one e f file To download the codes simply click the Download Code button on the program The program will call Quartus II and Nios II tools to download the control codes to the FPGA board through USB Blaseter US B 0 connection The sof file is downloaded to FPGA The e f file is downloaded to SDRAM UI To activate the Video Utility perform the following steps l Make sure Quartus II
61. oaded to either SDRAM U2 or SSRAM according to the user option To activate the Control Panel perform the following steps 1 Make sure Quartus II and NIOS II are installed successfully on your PC 2 Connect the supplied USB cable to the USB Blaster port connect the 12V power supply and turn the power switch ON 3 Setthe RUN PROG switch to the RUN position 4 Start the executable DE2 70 control panel exe on the host computer The Control Panel user interface shown in Figure 3 1 will appear 5 Select the target memory SDRAM U2 or SSRAM on the control panel Note The e f file will be downloaded to the target memory and the memory will be read only in later memory access operation 6 Click Download Code button Note the Control Panel will occupy the USB port until you 11 DE2 70 User Manual close that port you cannot use Quartus II to download a configuration file into the FPGA until you close the USB port 7 The Control Panel is now ready for use experiment by setting the value of some LEDs display and observing the result on the DE2 70 board Control FETTE EU GG JLEDGD _ LEDR6 ILEDG1 _ LEDR LILED G2 J LEDRS JLED G3 _ LEDRS ILEDG4 _JLEDR10 LEDS _LEDR11 LEDGE LEDR12 JLED G JLEDR13 JLED GSB JLEDR14 RUE CTI LILEDRO LEDR15 Product Name JLEDR1 JLEDR15 DE 70 JLEDR JLEDR17 ILEDR3 _ILEDR4 _ LEDRS http www altera com Light All Unlight AI llasic Targ
62. ocessor is able to keep track of the movement and record it in a frame buffer memory The VGA Controller will overlap the data stored in the frame buffer with a default image pattern and display the overlapped image on the VGA display 73 2 2 iV DE2 70 User Manual ANU S AYA Philips ISP1362 USB Host Mouse Port Altera System CPU Interconnect Fabric VGA Controller 4 ADV7123 Frame Buffer Figure 6 6 Block diagram of the USB paintbrush demonstration Demonstration Setup File Locations and Instructions Project directory DE2 70 NIOS HOST MOUSE VGA Bit stream used DE2 70 NIOS HOST MOUSE VGA sof Nios II Workspace DE2 70 NIOS HOST MOUSE VGANSoftware Connect a USB Mouse to the USB Host Connector type A of the DE2 70 board Connect the VGA output of the DE2 70 board to a VGA monitor both LCD and CRT type of monitors should work Load the bit stream into FPGA e Run the Nios II and choose DE2 70 NIOS HOST MOUSE VGANSoftwar as the workspace Click on the Run button You should now be able to observe a blue background with an Altera logo on the VGA display e Move the USB mouse and observe the corresponding movements of the cursor on the screen e Left click mouse to draw white dots lines and right click the mouse to draw blue dots lines on the screen 74 DE2 70 User Manual
63. on Once the programming operation is finished set the RUN PROG switch back to the RUN 31 DE2 70 User Manual position and then reset the board by turning the power switch off and back on this action causes the new configuration data in the EPCS16 device to be loaded into the FPGA chip USB Blaster Circuit PROG RUN Quartus II AS Mode Programmer Config Conta Pod AS Mode Auto my Power on Config EPCS16 Serial Configuration Device Figure 9 2 The AS configuration scheme In addition to its use for JTAG and AS programming the USB Blaster port on the DE2 70 board can also be used to control some of the board s features remotely from a host computer Details that describe this method of using the USB Blaster port are given in Chapter 3 52 Using the LEDs and Switches The DE2 70 board provides four pushbutton switches Each of these switches is debounced using a Schmitt Trigger circuit as indicated in Figure 5 3 The four outputs called KEYO KEYI KEY2 and KEY3 of the Schmitt Trigger devices are connected directly to the Cyclone II FPGA Each switch provides a high logic level 3 3 volts when it is not pressed and provides a low logic level 0 volts when depressed Since the pushbutton switches are debounced they are appropriate for use as clock or reset inputs in a circuit Pushbutton depressed Pushbutton released Before Debouncing Schm
64. on the DE2 70 System CD ROM The most challenging part of a USB application is in the design of the software driver needed Two complete examples of USB drivers for both host and device applications can be found in Sections 6 4 and 6 5 These demonstrations provide examples of software drivers for the Nios II processor VCC5 U VCC33 Q TG_DI0 15 a ai D85 D86 un Av OOOOOO0 VCCS BAT54S BAT54S a a As 10 BEAD H VCC5 1 a ch At H_SUSPEND H_SUSWKUP 23 LH A0 SUSPEND D SUSWKUP 4 4 t Do OTG_D15 18 B o 048 049 OTG_D14 17 515 VDD_5V U_VCC5 USB A TYPE DIS 18 pj Hoca 41 Arp Arp OTG D12 win en MS um Bed 0 10 OTG_D11 13 46 R112 A A22 OTG D10 12 211 H_DM2 7 7 Ri 22 DECIES 12 D10 2 I 10 58 HOCI 22 OTG_D7 an a PSE Lan R114 R115 OTG_D6 7 49 R116 22 OTG_D5 6 96 DM Ten V 22 15K 15K E05 OTG_DP1 NN D4 3158 ip 48 OU OTG Di rel OTGMODE 2 vn Se 5 eS ena eos AUI 47K s 53 li E oM Yn CP CAP1 m
65. ophone in connector on the DE2 70 board your voice will be mixed with the music played from the audio player Figure 2 3 The default VGA output pattern 10 DE2 70 User Manual Chapter 3 DE2 70 Control Panel The DE2 70 board comes with a Control Panel facility that allows users to access various components on the board from a host computer The host computer communicates with the board through an USB connection The facility can be used to verify the functionality of components on the board or be used as a debug tool while developing RTL code This chapter first presents some basic functions of the Control Panel then describes its structure in block diagram form and finally describes its capabilities 3 1 Control Panel Setup The Control Panel Software Utility is located in the DE2 70 control panel folder in the DE2 70 System CD ROM To install it just copy the whole folder to your host computer Launch the control panel by executing the DE2 70 Control Panel exe Specific control codes should be downloaded to your FPGA board before the control panel can request it to perform required tasks The control codes include one sof file and one elf file To download the codes just click the Download Code button on the program The program will call Quartus II and Nios II tools to download the control codes to the FPGA board through USB Blaster USB 0 connection The sof file is downloaded to FPGA The elf file is downl
66. pin assignments for the associated interface are shown in Table 5 14 49 52 UH PS2 KBCLK Ps2 msoar SS PS2 58 PS2 MSCLK lt gt D9 BAT54S Zr VCC33 R49 120 DE2 70 User Manual VCC5 VCC5 VCC5 O O R48 120 D10 D95 D96 BAT54S BAT54S BAT54S Fer emt 1 VCC33 VCC33 VCC33 Figure 5 16 PS 2 schematic PIN_F24 PS 2 Clock PIN_E24 PS 2 Data PIN_D26 PS 2 Clock reserved for second PS 2 device PIN_D25 PS 2 Data reserved for second PS 2 device Table 5 14 PS 2 pin assignments 5 11 Fast Ethernet Network Controller The DE2 70 board provides Ethernet support via the Davicom DM9000A Fast Ethernet controller chip The DM90004A includes a general processor interface 16 Kbytes SRAM a media access control MAC unit and a 10 100M PHY transceiver Figure 5 17 shows the schematic for the Fast Ethernet interface and the associated pin assignments are listed in Table 5 15 For detailed information on how to use the DM90004A refer to its datasheet and application note which are available on the manufacturer s web site or in the Datasheet Ethernet folder on the DE2 70 System CD ROM 50 DE2 70 User Manual N VCC33 Q R72 N VCC33 4 7K O 25MHZ ENET RESET e NGND SPEED EN ACT BEA em ENET CS n C17 BC36 BC37 dile ENET D 0 15 10u 0 1u 0 1u
67. s 9 ow 1 mm 3 mm 3 Table 5 10 VGA vertical timing specification 46 DE2 70 User Manual Table 5 11 ADV7123 pin assignments A 7 DE2 70 User Manual 5 8 Using the 24 bit Audio CODEC The DE2 70 board provides high quality 24 bit audio via the Wolfson WM8731 audio CODEC udio DECoder This chip supports microphone in line in and line out ports with a sample rate adjustable from 8 kHz to 96 kHz The WM8731 is controlled by a serial I2C bus interface which is connected to pins on the Cyclone II FPGA A schematic diagram of the audio circuitry 15 shown in Figure 5 14 and the FPGA pin assignments are listed in Table 5 12 Detailed information for using the WM8731 codec is available in its datasheet which can be found on the manufacturer s Web site or in the Datasheet Audio CODEC folder on the DE2 70 System CD ROM J11 LINE IN C38 PHONE JACK B VCC33 VCC33 R108 R109 NZ AGND o AGND AGND 12C_SDAT J10__MIC IN lle som a a Z 12C ADDRESS READ IS 0x34 ONG id x C40 I2C ADDRESS WRITE IS 0x35 U13 PHONE JACK P R104 680 NCL ee 10u 19 P AGND C42 R105 lt p OA_VCC33 ane J12 LINE OUT ZF AGND AGND AGND RHPOUT PHONE JACK G EXPOSED DACDAT C43 NZ AGND AGND Figure 5 14 Audio CODEC schematic AUD_ADCLRCK PIN_F19 Audio CODEC ADC LR Clock AUD_ADCDAT PIN_E19 Audio CODEC ADC Data AUD_DACLRC
68. sconnect Exit Video Capture success Dim 720x576 7 7 sec Figure 4 3 Video Capturing Tool 4 4 Overall Structure of the DE2 70 Video Utility The DE2 70 Video Utility is based on a NIOS II system running in the Cyclone II FPGA with the SDRAM U2 or SSRAM The software part is implemented in C code the hardware part is implemented in Verilog code with SOPC builder This tool is located inside the DE2 70 demonstrations directory on the DE2 70 System CD ROM Figure 4 4 depicts the block diagram of the Video Utility Each input output device is controlled by the NIOS II Processor instantiated The communication between the DE2 70 board and the host PC is via the USB Blaster link The NIOS II processor interprets the commands sent from the PC and performs the appropriate actions 28 DE2 70 User Manual NIOS II Program gt SDRAM I Controller SDRAM UI 5 SDRAM SDRAM U2 Controller VGA VGA NIOS JTAG Blaster Hardware Controller Multi Port SSRAM SSRAM Controller mn Avalon MM Slave VIDEO In K N VIDEO IN Controller 91161 1091 0919111 wIIJSAS Figure 4 4 Video Capture Block Diagram The control flow for video displaying 15 described below 1 Host computer downloads the raw image data to SDRAM U2 2 Host issues a display command to Nios II processor 3 Nios II processor interprets the command received and moves the raw image data from the
69. sed to display text by sending appropriate commands to the display controller which is called HD44780 Detailed information for using the display is available in its datasheet which can be found on the manufacturer s web site and from the Datasheet LCD folder on the DE2 70 System CD ROM A schematic diagram of the LCD module showing connections to the Cyclone II FPGA is given in Figure 5 9 The associated pin assignments appear in Table 5 6 Q1 8050 Q2 8550 E y VCC5 R34 1u VCC430 680 LCD ON R35 680 Q3 8050 VCC43 Q4 8550 VCC430 R38 DIO 7 R36 680 zlo iN eolto st oofaulelol z Slnlolo R39 MAA Mwy m LCD BLON R37 680 Q5 olololololololololololololo 47 8050 of ff oS J J DIS1 mnm D JNonvywmadr zaaaoaaaaoaaa 2 X 16 DIGIT LCD LCD 2x16 Figure 5 9 Schematic diagram of the LCD module 40 PAS fe ou DE2 70 User Manual AN S RYA LCD RW LCD Read Write Select O Write 1 Read LCD EN LCD Enable LCD RS LCD Command Data Select 0 Command 1 Data LCD ON LCD Power ON OFF LCD BLON LCD Back Light ON OFF Table 5 6 Pin assignments for the LCD module Note that the current LCD modules used on DE2 DE2 70 boards do not have backlight Therefore the LCD BLON signal should not be used in users design projects 5 6 Using the Expansion Header The DE2 70 Board provides two 40 pin expansion headers Each header connects dire
70. signals are provided directly from the Cyclone II FPGA and the Analog Devices ADV 7123 triple 10 bit high speed video DAC is used to produce the analog data signals red green and blue The associated schematic is given in Figure 5 12 and can support resolutions of up to 1600 x 1200 pixels at 100 MHz o eo r wl s elel o VGA VCC33 E c c E a 5 F O 5555 5 515515 R80 ATK gt gt gt gt gt gt gt gt gt gt R81 560 RSET BC47 BC48 VGA R 0 9 co o q O3 0 1u 0 1u a chi C 11111311 EBD VGA GO VGA VGA 2 VGA_R VGA G4 mm VGA G4 IOR F E VGA B VGA_G5 6 DET VGA G6 ADV7123 IOG p VGA_G7 8 Er R82 R83 R84 VGA G8 Q og VGA G9 N 10B 55 73 75 76 BLANK n en PUE ume 25 do 2L aL VGA HS R85 47 VGA VS R86 47 2 O VGA_VCC33 Figure 5 12 WGA circuit schematic The timing specification for VGA synchronization and RGB red green blue data can be found on various educational web sites for example search for VGA signal timing Figure 5 13 illustrates the basic timing requirements for each row horizontal that 1s displayed on a VGA monitor An active low pulse of specific duration time a in the figure is applied to the horizontal synchronization Async input of the monitor which signifies the end of one row of data and the start of the next The data RGB inputs on the monitor must be off driven to 0 V for a
71. sters in both of the TV decoders can be programmed by a serial I2C bus which 15 connected to the Cyclone II FPGA as indicated in Figure 5 18 Note that the I2C address of the TV decoder 1 U11 and TV decoder 2 U12 are 0x40 and 0x42 respectively The pin assignments are listed in Table 5 16 Detailed information on the ADV7180 is available on the manufacturer s web site or in the Datasheet TV Decoder folder on the DE2 70 System CD ROM 52 DE2 70 User Manual V_VCC33 VGND V_VCC33 9 ID1 7 V VCC18 VCC18 PV1 VCC18 oe IIT Q D83 C31 0 1u BAT54S U11 030 R91 1 74K 0 1u AIN1 J AIN2 ar 0 A TD1 DO AINS TD1_D1 TDi RESET n 4 TD1 D2 RESET D3 VGND C27 0 1u 6 8 TD1 D4 C28 VREFN D5 Q TD1 D6 29 0 1ul 0 tu gt TDI D7 VREFP ADV7180 a XTAL 120 VS VS FIELD 120 TDi HS XTAL1 HS gt V_VCC330 PWRDWN Die gt ED a 86 V_VCC33 VGND V_VCC33 D2 010 71 V VCC18 AV2_VCC18 2 VCC18 Q Q Q D84 37 0 1 BAT54S 48 E U12 C36 R96 1 74K 0 1u 3 AINT b AIN2 RCA JACK EIAS TD2 DO 3 TD2 D1 TD2 RESET n T A TD2 D2 gt RESET TD2 D3 VGND C33 0 1u 6 TD2 DA C34 VREFN TD2 D5 TD2 D6 35 0 1 0 1u gt TD2 D7 VREFP ADV7180 28MHZ XTAL 120 TD2 VS ag R98 A A120 TD2 HS XTAL1 H 20 ADDRESS IS 0x42 y vccaso PM IPC SCLK 34 126 5 Figure 5 18 TV Decoder schematic
72. that are used for clocking the user logic Also the 28 86 MHz oscillator is used to drive the two TV decoders The board also includes an SMA connector which can be used to connect an external clock source to the board In addition all these clock inputs are connected to the phase lock loops PLL clock input pin of the FPGA allowed users can use these clocks as a source clock for the PLL circuit The clock distribution on the DE2 70 board is shown in Figure 5 8 The associated pin assignments for clock inputs to FPGA I O pins are listed in Table 5 5 38 DE2 70 User Manual GPIO 0 GPIO 1 2 SD Card 2 3 SMA gt Connector AUDIO E 74 gt CODEC 50 MHz 4 gt Oscillator 4 gt PS 2 Cyclone II 2 FPGA 28 MHz Oscillator TV decoder 1 gt Ethernet TV decoder 2 VGA DAC SDRAM SDRAM SSRAM FLASH Figure 5 8 Block diagram of the clock distribution CLK 28 PIN E16 28 MHz clock input CLK 50 PIN AD15 50 MHz clock input CLK 50 2 PIN D16 50 MHz clock input CLK 50 3 PIN R28 50 MHz clock input CLK 50 4 PIN R3 50 MHz clock input EXT CLOCK PIN R29 External SMA clock input Table 5 5 Pin assignments for the clock inputs 39 DE2 70 User Manual 55 Using the LCD Module The LCD module has built in fonts and can be u
73. time period called the back porch b after the hsync pulse occurs which is followed by the display interval c During the data display interval the RGB data drives each pixel in turn across the row being displayed Finally there is a time period called the front porch d where the RGB signals must again be off before the next hsync pulse can occur The timing of the vertical synchronization vsync is the same as shown in Figure 5 13 except that a vsync pulse signifies the end of one frame and the start of the next and the data refers to the set of rows in the frame horizontal timing Table 5 9 and 5 10 show for different resolutions the durations of time periods a b c and d for both horizontal and vertical timing 45 DE2 70 User Manual Detailed information for using the ADV7123 video DAC is available in its datasheet which can be found on the manufacturer s web site or in the Datasheet VGA DAC folder on the DE2 70 System CD ROM The pin assignments between the Cyclone II FPGA and the ADV7123 are listed in Table 5 11 An example of code that drives a VGA display is described in Sections 6 2 6 3 and 6 4 Back porch b Front porch d Display interval c j HSYNC Sync a Figure 5 13 VGA horizontal timing specification DATA owes om Las v9 asa os s emm sow mom v1 er wa on s mo Table 5 9 VGA horizontal timing specification www ww ow rover wm ewe ww
74. to FPGA note 1 e Configure audio with the toggle switches 89 DE2 70 User Manual e Press KEY3 on the DE2 70 board to start stop audio recoding note 2 e Press KEY2 on the DE2 70 board to start stop audio playing note 3 Note 1 Execute DE2 70 AUDIONdemo batch audio bat will download sof and elf files 2 Recording process will stop if audio buffer 1s full 3 Playing process will stop if audio data is played completely Audio is from MIC Audio is from LINE IN Disable MIC Boost Enable MIC Boost Disable Zero cross Detection Enable Zero cross Detection Unlisted combination Table 6 4 Toggle switch setting for audio recorder and player 90 DE2 70 User Manual Chapter 7 Appendix 7 1 Revision History Version Change Log V1 0 Initial Version Preliminary V1 01 1 Add appendix chapter V1 05 Modify Chapter 1 V1 06 Modify Nios Il workspace V1 07 Modify the location of the DE2 70 control panel and DE2 70 Video Utility for DE2 70 system CD v1 2 V1 08 Added Quartus II 9 1 Nios II EDS 9 1 section V1 09 Modify section 4 4 content V1 04 Modify Section 5 4 72 Copyright Statement Copyright 2009 Terasic Technologies All rights reserved 91
75. w altera com Tasic Target Memor Www LET BSIC COM About SDRAM U2 Download Code Disconnect Exit Connected Figure 3 9 Reading the PS2 Keyboard 3 7 SDCARD The function is designed to read the identification and specification of the SD card The 1 bit SD MODE is used to access the SD card This function can be used to verify the functionality of SD CARD Interface Follow the steps below to exercise the SD card 1 Choosing the SD CARD tab leads to the window in Figure 3 10 First 2 Insert a SD card to the DE2 70 board then press the Read button to read the SD card The SD card s identification and specification will be displayed in the control window 20 DE2 70 User Manual LED 7 SEG LCD Button Memory USB PS2 SD CARD Audio SB CARD ob CARD Identification Manufacturer ID 3bEh BEM Applicatian ID 2D48h Praduct Name Product Revisian lh Serial No 00800595h Date Eode 075h SO CARD Specification CSD Version No 1 0 Read Access Time 20 ms Product Name Fead Access Time NSAC 1 x100 cycle DE 70 Max Data Transfer Rate 25 Mbits s Max Read Data Block Length 512 Byte Memory Capacity 122MB http www altera com Read Tasic Target Memory _ Www LESTIE DOM About ISDRAM U2 Download Code Disconnect Exit Connected ISD CARD read success Figure 3 10 Reading the SD card Identification and Specification 3 8 Audio Playing and Recording T
76. wnload Code Disconnect Exit Connected ISDRAM LI1 Random Write Success Figure 3 7 Accessing the SDRAM UI A 16 bit word can be written into the SDRAM by entering the address of the desired location specifying the data to be written and pressing the Write button Contents of the location can be read by pressing the Read button Figure 3 7 depicts the result of writing the hexadecimal value 06CA into location 200 followed by reading the same location The Sequential Write function of the Control Panel is used to write the contents of a file into the SDRAM as follows Specify the starting address in the Address box 2 Specify the number of bytes to be written in the Length box If the entire file is to be loaded then a checkmark may be placed in the File Length box instead of giving the number of bytes 3 To initiate the writing of data click on the Write a File to Memory button When the Control Panel responds with the standard Windows dialog box asking for the source file specify the desired file in the usual manner The Control Panel also supports loading files with a hex extension Files with a hex extension are ASCII text files that specify memory values using ASCII characters to represent hexadecimal values For example a file containing the line 0123456789ABCDEF defines four 8 bit values 01 23 45 67 89 AB CD EF These values will be loaded consecutively 17 DE2 70 User Manual into the memory

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