DNR-AI-201-100 Product Manual - United Electronic Industries
Contents
1. Product Disclaimer WARNING DO NOT USE PRODUCTS SOLD BY UNITED ELECTRONIC INDUSTRIES INC AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS Products sold by United Electronic Industries Inc are not authorized for use as critical components in life support devices or systems A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness Any attempt to purchase any United Electronic Industries Inc product for that purpose is null and void and United Electronic Industries Inc accepts no liability whatsoever in contract tort or otherwise whether or not resulting from our or our employees negligence or failure to detect an improper purchase Specifications in this document are subject to change without notice Check with UEI for current status Contents Table of Contents Chapter 1 Introduction 200 c eee 1 1 1 Organization of Manual nasasa eea 1 1 2 The Al 201 Interface Board 1 2 2 nee 3 1 3 FEAtUIES het vcd betwee ade en eed Ge eed Boia Po aaa weg ae 3 1 4 Specification 224 fe iaeia ae a detain dds aaa E bad WE alee i 4 1 5 Device Architecture 0 2 ete ee 5 1 6 MACAO aaaea a EET E ass oh a ents ation ara utah E AT 5 1 7 Layer Connectors and Wiring 0 060 e cette eee 6 1 7 1 Analog Input Ground Connections s sasaa a2. September 2013 DNx Al 201 Chap2x fm DNA DNR AI 201 Analog Input Board Chapter 2 15 Programming with the High Level API 2 6 Cleaning up The session object will clean itself up when it goes out of scope or when it is the Session destroyed To reuse the object with a different set of channels or parameters you can manually clean up the session as follows clean up the session aiSession CleanUp ee SE ee ee a ee Copyright 2013 Tel 508 921 4600 www ueidaq com Vers 4 6 pe ne noustries Ing Date September 2013 DNx Al 201 Chap2x fm Chapter 3 DNA DNR AI 201 Analog Input Board Chapter 3 Programming with the Low level API Programming with the Low level API The PowerDNA cube and PowerDNR RACKtangle and HalfRACK can be pro grammed using the low level API The low level API offers direct access to Pow erDNA DAQBios protocol and also allows you to access device registers directly However we recommend that when possible you use the UeiDaq Framework High Level API see Chapter 2 because it is easier to use You should need to use the low level API only if you are using an operating system other than Win dows For additional information about low level programming of the Al 201 please refer to the PowerDNA API Reference Manual document under Start Programs UEI PowerDNA Documentation Refer to the PowerDNA API Reference Manual on how to use the following low level functions of Al 201 as well as ot
3. UeiTemperatureScaleCelsius UeiAIChannelInputModeDifferential 2 4 Configuring You can configure the Al 201 to run in simple mode point by point or high the Timing throughput buffered mode ACB mode or high responsiveness DMAP mode In simple mode the delay between samples is determined by software on the host computer In DMAP mode the delay between samples is determined by the Al 201 on board clock and data is transferred one scan at a time between PowerDNA and the host PC In buffered mode the delay between samples is determined by the Al 201 on board clock and data is transferred in blocks between PowerDNA and the host PC The following sample shows how to configure the simple mode Please refer to the UeiDaq Framework User s Manual to learn how to use other timing modes configure timing of input for point by point simple mode aiSession ConfigureTimingForSimpleI0 2 5 Read Data Reading data is done using reader object s The following sample code shows how to create a scaled reader object and read samples create a reader and link it to the analog input session s stream CUeiAnalogScaledReader aiReader aiSession GetDataStream the buffer must be big enough to contain one value per channel double data 2 read one scan where the buffer will contain one value per channel aiReader ReadSingleScan data Copyright 2013 Tel 508 921 4600 www ueidaq com Vers 4 6 pee eee a een Date
4. 16 bits Number of Channels Single Ended 24 Differential 12 Maximum Sampling Rate 100 kS s aggregate Onboard FIFO Size 512 samples Input Range 15V Programmable Gains 1 2 5 10 by channel Input Impedance 10 MQ Input Bias Current 15nA Input Overvoltage 40V 2000V ESD powered or unpowered A D Conversion Time 2 us A D Settling Time 10us G 1 15us G 2 25us G 5 50us G 10 Nonlinearity 1LSB System Noise 1 2 LSB Isolation 350Vrms Effective Number of Bits 14 8 Total Harmonic Distortion N 91 dB onlinearity Noise Channel Crosstalk 85 dB 1 kS s Power Consumption 2 0W Physical Dimensions 3 875 x 3 875 98 x 98 mm Operating Temp tested 40 C to 85 C Operating Humidity 95 non condensing Vibration IEC 60068 2 6 IEC 60068 2 64 5 g 10 500 Hz sinusoidal 5 g rms 10 500 Hz broad band random Shock IEC 60068 2 27 50 g 3 ms half sine 18 shocks 6 orientations 30 g 11 ms half sine 18 shocks 6 orientations www ueidaqg com Table 1 1 DNx Al 201 100 Technical Specifications Vers 4 6 DNx Al 201 Chap1x fm 4 DNA DNR AI 201 Analog Input Board Chapter 1 5 Introduction 1 5 Device Figure 1 1 is a block diagram of the architecture of the Al 201 layer Architecture The DNx Al 201 layer is physically divided into isolated and non isolated sections The non isolated part is powered from DC DC converters located on the C
5. 228uV 5 3V 25us 2 20 91uV DNA AI 201 801 10 1 5V 50us 3 11 45uV 1 8 1 Single Ended An Al 201 layer operating in single ended mode digitizes across as many as 24 and Pseudo channels For single ended inputs you connect one wire from each signal Differential source to the High input of the input amplifier to the data acquisition system All signals share a common return path connected to analog ground AGND You should connect this common return path both to a ground near the signal source and also to the ground on the PC which forces it to be the same level as the signal ground This ground signal however is typically referenced to a remote source and because it is separated from the system ground it can float ata different level The maximum potential difference between common ground and PC ground should never exceed 350V Because the AGND line in a pseudo differential setup is not connected to the computer ground however it is not subject to the associated digital noise within the system 1 8 2 Differential An Al 201 layer operating in differential mode digitizes as many as 12 channels Each channel uses two lines on the input amplifier of the data acquisition system you connect one lead from the signal source to the channel s High input the positive input of the amp and connect the other signal lead to the channel s Low input the amp s negative input Each signal floats at its own level without an
6. Copyright 2013 Tel 508 921 4600 www ueidaq com Vers 4 6 United Electronic Industries Inc Date September 2013 DNx Al 201 Chap1x fm 9 DNA DNR AI 201 Analog Input Board Chapter 1 10 Introduction Additional Factors to Consider e Channel channel offset due to the multiplexed architecture is 10uV typical e Open TC detection circuitry on the DNA STP AI U adds 35uV 5uV offset on all channels may be compensated by using CJC temperature sensor calibration e CJC sensor is calibrated to better than 0 2 C accuracy at room tem perature and stays within 0 4 C accuracy within the 20 75 C tem perature range 1 8 4 Data The Al 201 layer is equipped with a single 18 bit A D converter This layer can Representa return either 16 bit 2s complement data in 16 bit words to save on network tion transmission size or 18 bit straight binary data in 32 bit words combined with levels on general purpose digital I O lines 16 bit data is represented as follows Bit Name Description Reset State 15 SIGN Sign Signal levels below OV 0 correspond with negative values sign bit is set 14 0 ADCDATA Upper 15 bits of data twos lt pos gt complemented lt pos gt represents a position in the output buffer Upon reset every entry in the output buffer is filled with its relative position number As an initializing step you should read the buffer and discard the data before proceeding with normal data
7. Copyright 2013 i Tel 508 921 4600 www ueidaq com Vers 4 6 EE Feroe NEUSIE ne Date September 2013 DNx Al 201 Chap1x fm DNA DNR AI 201 Analog Input Board Chapter 1 Introduction e 18V 18V lines on the Al 201 100 and Al 201 16 provide isolated volt age generated on the layer to power external sensors As maximum cur rent is limited to 15mA each we suggest using large current limiting resistors when using this source to power strain gages or RTDs On the Al 201 801 the reference is 2 5V 18V instead 1 7 1 Analog Input To avoid errors caused by common mode voltages on analog inputs follow the Ground recommended grounding guidelines in Figure 1 4 below Connections Type of Input Floating Grounded Input Typical Signal Sources Typical Signal Sources Configuration Thermocouples Instruments or sensors DC Voltage Sources with non isolated outputs Instruments or sensors with isolated outputs DNA STP 37 E Al DNA STP AI U pala Ea Differential Two resistors 10k lt R lt 100k provide Add this connection to ensure that both return paths to ground for bias currents grounds are at the same potential NOT RECOMMENDED DNA STP AI U Single Ended Ground Referenced Figure 1 4 Recommended Ground Connections for Analog Inputs Because all analog input channels in Al 201 202 207 208 225 layers are isolated as a group you can connect layer AGND to the ground of the signal source and eli
8. EXT CLK 18V 40mA max 20 2 AGND 1 AGND 18V 40mA on Al 201 100 is 2 5V on Al 201 801 Faia wise eis wba ele wes Figure 1 3 Pinout Diagram of the DNx Al 201 The following signals are located at the connector Aln0 Aln23 input channels If a channel is set to operate as single ended its voltage is measured between the selected channel line and the analog ground AGND line If Channel X is used as a differential measurement its inputs are connected between Channel A n X and Aln X 12 For example in differential mode channel Aln0 pairs with Aln12 Aln1 with Aln13 etc e AGND analog ground of the layer isolated from system ground e TCPOS and TCNEG dedicated channels to connect a thermocouple compensation device Use signal and return to measure in differential mode or just TCPOS to measure in single ended mode relative to AGND TCPOS should then be programmed as channel A n24 e CLKOUT this line by default is an output and is used as an external channel list clock to synchronize multiple PowerDNA cubes This line can also be used as a bi directional general purpose DIO e TRIGIN by default this is an input that provides an external trigger sig nal to the layer This line can also be used as bi directional general purpose DIO e EXTCLK by default this is an input that provides external an CV or CL clock to the layer logic This line can also be used as a bi directional general purpose DIO ee
9. Index This is an alphabetical listing of the topics covered in this manual Copyright 2013 Tel 508 921 4600 www ueidaq com Vers 4 6 United Electronic Industries Inc Date September 2013 DNx Al 201 Chap1x fm DNA DNR AI 201 Analog Input Board Chapter 1 Introduction Manual Conventions To help you get the most out of this manual and our products please note that we use the following conventions Tips are designed to highlight quick ways to get the job done or to reveal good ideas you might not discover on your own NOTE Notes alert you to important information CAUTION Caution advises you of precautions to take to avoid injury data loss and damage to your boards or a system crash Text formatted in bold typeface generally represents text that should be entered verbatim For instance it can represent a command as in the following example You can instruct users how to run setup using a command such as setup exe Text formatted in fixed typeface generally represents source code or other text that should be entered verbadim into the source code initialization or other file Examples of Manual Conventions Before plugging any I O connector into the Cube or RACKtangle be sure to remove power from all field wiring Failure to do so may cause severe damage to the equipment Usage of Terms Throughout this manual the term Cube refers to either a PowerDNA Cube product or to a PowerDNR RACKtangle rack mou
10. PU layer These converters provide 5V and 3 3 2 5V to power all non isolated electronics The isolating DC DC that produces 5V powers the isolated side of the layer Two high frequency boosters generate 18V 18V rails that are also available on the connector 15mA maximum each On the 201 801 this is a 2 5V 18V The DNx Al 201 employs a single successive approximation 18 bit converter with no pipeline delay Analog Input Connector ey ron B By a ore ai Control Logic 32 bit 66 MHz bus External Clocks and Triggers Figure 1 1 Architecture Block Diagram of the Al 224 Layer 1 6 Indicators A photo of the DNx AI 201 unit is illustrated below The front panel has two LED indicators e RDY indicates that the layer is receiving power and operational e STS can be set by the user using the low level framework DNR bus connector DNA bus ry connector STS LED aaas DB 37 female 37 pin I O connector Figure 1 2 The DNA AI 201 Analog Input Layer Copyright 2013 Tel 508 921 4600 www ueidaq com Vers 4 6 United Electronic Industries Inc Date September 2013 DNx AIl 201 Chap1x fm DNA DNR AI 201 Analog Input Board Chapter 1 6 Introduction 1 7 Layer Figure 1 3 below illustrates the pinout of the Al 201 Like other layers it uses a Connectors B size 37 pin D sub connector for all I O connections and Wiring AIN12 37 19 AINO CLK_OUT 22 4 J TRIG_IN 18V 40mA max 27 3
11. Session 12 D Data Representation 10 E ESD protection 3 G Gains 8 H High Level API 12 l Input Mode Differential 8 Pseudo differential 8 Single ended 8 DNA DNR AI 201 Analog Input Board Index J Jumper Settings 4 L Layer capabilities 8 Layout connector 8 Low level API 16 Model numbers 3 O Organization 1 Over voltage protection 3 P Pseudo differential 8 S Screw Terminal Panels 20 Setting Operating Parameters 3 Settings Channel List 19 Settings Configuration 17 Signals Low level 9 Single Ended 8 Specifications 4 Support ii T Thermocouple 9 Copyright 2013 Tel 508 921 4600 Date September 2013 United Electronic Industries Inc www ueidaq com Vers 4 6 DNx Al 201 ManuallX fm
12. XT STS LED status enable operations DQ LN MAPPED DQ LN STREAMING 1L lt lt 15 1L lt lt 14 DQ_LN_IRQEN DQ LN PTRIGEDGE1 DQ LN PTRIGEDGEO 1L lt lt 10 1L lt lt 9 1L lt lt 8 DQ LN_STRIGEDGE1 1L lt lt 7 DQ LN STRIGEDGEO 1L lt lt 6 DQ LN CVCKSRC1 DQ LN CVCKSRCO 1L lt lt 5 1L lt lt 4 DQ LN CLCKSRC1 DQ LN CLCKSRCO 1L lt lt 3 1L lt lt 2 source MSB source is 10 HW DQ LN ACTIVE DQ LN ENABLED aiec 1L lt lt 0 For streaming operations with hardware clocking select the following flags DQ LN ENABLE DQ LN CLCKSRCO DQ LN STREAMING DQ LN IRQEN DQ LN ACTIVE DQ_LN_ENABLE enables all operations with the layer DQ_LN_CLCKSRCO selects the internal channel list clock CL source as a timebase Al 201 supports CL clock only where the time between consecutive channel readings is calculated by the rule of maximizing setup time per channel If you d like to select the CL clock from an external clock source such as the SYNCx line set DQ_LN CLCKSRC1 as well Tel 508 921 4600 Date September 2013 Vers 4 6 DNx Al 201 Chap3 fm www ueidag com DNA DNR AI 201 Analog Input Board Chapter 3 18 Programming with the Low level API DQ_LN_CVCKSRCO selects the internal conversion clock CV source as a timebase Setting CV clock allows having an equal time period between conversions of different channels It is mostly used when you are interested ina phase sh
13. ZN United Electronic wy Industries The High Performance Alternative DNx Al 201 User Manual Sequential Sampling 16 bit 24 channel Analog I nput Layer for the PowerDNA Cube and PowerDNR RACKtangle Release 4 6 September 2013 PN Man DNx AI 201 913 Copyright 1998 2013 United Electronic I ndustries Inc All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form by any means electronic mechanical by photocopying recording or otherwise without prior written permission Information furnished in this manual is believed to be accurate and reliable However no responsibility is assumed for its use or for any infringement of patents or other rights of third parties that may result from its use All product names listed are trademarks or trade names of their respective companies See the UEI website for complete terms and conditions of sale http www ueidaq com cms terms and conditions Contacting United Electronic Industries Mailing Address 27 Renmar Avenue Walpole MA 02081 U S A For a list of our distributors and partners in the US and around the world please see http www ueidaq com partners Support Telephone 508 921 4600 Fax 508 668 2350 Also see the FAQs and online Live Help feature on our web site Internet Support Support support ueidag com Web Site www ueidaq com FTP Site ftp ftp ueidag com
14. asa 0c e eee eee 7 1 8 Layer Capabilities 0 00 c teens 8 1 8 1 Single Ended and Pseudo Differential 0 0 2 0 000s eee eee 8 1 8 2 Differential c42ch gate has Geer eee oe eee kee ieee ete es 8 1 8 3 Thermocouple Measurement 00 0 0 ee es 9 1 8 4 Data Representa tion 0 0 0 eee 10 Chapter 2 Programming with the High Level API 000 cee eee eee eeeee 12 2 1 Creating a SESS ON 2 cees ves cee bbe tender a a d aa aa ete diweended 12 2 2 Configuring the Resource String 0 0 cece eee 12 2 3 Configuring for Input aaaea cette ae 12 2 3 1 Thermocouple Measurement 0 0 cee eee 13 2 3 2 RTD Measurement 0000 eee 13 2 4 Configuring the Timing 0000 e eee teen eee 14 2 5 Read Datay a4 sadveue ieee dee heed Eek oe a eee eh eee dae 14 2 6 Cleaning up the Session 0 0000 c cette eee 15 Chapter 3 Programming with the Low level API 0 20 cece cece een eeees 16 3 1 Configuration SettingS 00 0 c cette eee 17 3 2 Channel List Settings 0 000 c cette ee 19 3 3 Layer Specific Commands and Parameters 0 00 c cece eee eens 19 PASS Copyright 2013 Tel 508 921 4600 www ueidaq com Vers 4 6 Q ee Date September 2013 DNx Al 201 ManualTOC fm DNA DNR AI 201 Analog Input Board DNA DNR AI 201 Analog Input Board Figures ii List of Figures 1 1 Architecture Block Diagram of the Al 224 Layer ccsceeeeeeenee
15. collection If you start receiving consecutive data from the layer like 0 1 2 etc it means that either the layer is not initialized properly or it is damaged To convert data into floating point use the following formula Volts Raw 0x8000 30V 2 16 15V 32 bit data however has different representation as shown below are Reset Bit Name Description State 31 ISO_EXT1 Current value of ISO_EXT1 line internal 0 use 30 ISO_EXTO Current value of ISO_EXTO line internal 0 use 29 ISO_INT1 Current value of ISO_INT1 line internal 0 use 28 ISO_INTO Current value of ISO_INTO line internal 0 use 27 ADCBUSY Current value of ADC 1 BUSY 0 internal use Copyright 2013 Tel 508 921 4600 www ueidaq com Vers 4 6 pates vere men Sun Date September 2013 DNx Al 201 Chap1x fm DNA DNR AI 201 Analog Input Board Chapter 1 Introduction Pa Reset Bit Name Description State 26 DIO2 Current value of DIO2 TRIGIN pin 0 25 DIO1 Current value of DIO1 EXTCLK pin 0 24 DIOO Current value of DIO1 CLKOUT pin 0 23 18 RSVO Reserved read as 0 0 17 16 MSB18 Bits 17 and 16 of the straight binary code 0 in 18 bit mode 0 in 16 bit mode 15 0 ADCDATA 16 LSBs in 18 bit mode twos 0 complement conversion result in 16 bit mode NOTE 16 bit mode 18BIT field 0 in configuration delivers data in two s complement format in 18 bit mode th
16. culate the maximum per channel rate as Per channel rate Aggregate rate Number of channels Copyright 2013 i Tel 508 921 4600 www ueidaq com Vers 4 6 Paed ous eRe eae Date September 2013 DNx Al 201 Chap3 fm 3 2 Channel List Settings 3 3 Layer Specific Commands and Parameters Copyright 2013 United Electronic Industries Inc DNA DNR AI 201 Analog Input Board Chapter 3 19 Programming with the Low level API The Al 201 layer has a very simple channel list structure as shown in Table 3 1 Table 3 1 Channel List Structure Bit Name Purpose 31 IDQ_LNCL_NEXT Tells firmware there is a next entry in the channel list 20 IDQ_LNCL_TSRQ Request timestamp as a next data point 19 DQ_LNCL_SLOW Double the settling time for this channel 15 DQ_LNCL_DIFF _ Differential 11 8 DQ LNCL_GAIN Gain 7 0 Channel number Gains are different for various options of the Al 201 layer as shown in Table 3 2 Table 3 2 Gains LayerType Range Gain GainNumber Al2oi 16 si5v 7 o 1 5V 10 1 150mV 100 2 15mV 1000 3 Al 201 100 15V 1 0 7 5V 2 1 3V 5 2 1 5V 10 3 Layer specific functions for the Al 201 layer are described in DaqLibHL h file DqAdv201Read This function works using underlying DgReadAIChannel but converts data using internal knowledge of input range and gain of every channel It uses the DOQCMD_IOCTL comma
17. de with round heavy shielded cable 3 ft 90 cm long weight of 10 ounces or 282 grams also available in 10ft and 20ft lengths DNA STP 37 The DNA STP 37 provides easy screw terminal connections for all DNA and DNR series I O boards which utilize the 37 pin connector scheme The DNA STP 37 is connected to the I O board via either DNA CBL 37 or DNA CBL 37S series cables The dimensions of the STP 37 board are 4 2w x 2 8d x1 0h inch or 10 6 x 7 1 x 7 6 cm with standoffs The weight of the STP 37 board is 2 4 ounces or 69 grams JP1 DB 37 male JP2 20 position JP3 20 position 37 pin connector terminal block terminal block to m Ene ojnic 34 RORURSS cocoocoooococoooaaad Pocoococoooococaaa caste SHIELD DNA STP AI U Universal screw terminal panel with embedded CJC DNA STP AI 207TC Screw terminal panel for use with the DNx Al 217 and thermocouples The panel provides open thermocouple detection as well as the cold junction com pensation measurement SSS see ee Copyright 2013 f Tel 508 921 4600 www ueidaq com Vers 4 6 eA E eero ie aogus eer Date September 2013 DNx Al 201 AppxA fm A A D resolution 10 B Block Diagram 5 C Cable s 20 Capabilities 8 Channel list channels 18 clock 17 18 structure 19 Commands and Parameters 19 Configuring the Resource String 12 Connectors and Wiring 6 Conventions 2 Creating a
18. e conversion results are delivered in straight binary 18 bit format To convert data into floating point use the following formula Volts Raw amp Ox3ffff 30V 2 18 15V 1 To apply two s complement to a base 2 integer invert the bits and then add one aa aa ee ee ee ae ae ee ee ee ee Se ee a Se ee ee a Copyright 2013 i Tel 508 921 4600 www ueidaq com Vers 4 6 a meotonig a Date September 2013 DNx Al 201 Chap1x fm DNA DNR AI 201 Analog Input Board Chapter 2 12 Programming with the High Level API Chapter 2 Programming with the High Level API This section describes how to control the DNx Al 201 using the UeiDaq Frame work High Level API UeiDag Framework is object oriented and its objects can be manipulated in the same manner from different development environments such as Visual C Visual Basic or LabVIEW The following section focuses on the C API but the concept is the same no matter what programming language you use Please refer to the UeiDaq Framework User Manual for more information on use of other programming languages 2 1 Creating a The Session object controls all operations on your PowerDNx device Therefore Session the first task is to create a session object create a session object for input CUeiSession aiSession 2 2 Configuring UeiDaq Framework uses resource strings to select which device subsystem the Resource and channels to use within a session The resource string sy
19. ect of noise pickup from signal leads and elim inate the possibility of ground differentials e When signals are less than approximately 100 mV Such low level sig nals can be easily overwhelmed by noise and ground differentials that only the differential mode can remove e When the signals are from high impedance sensors such as strain gauges Their high impedances can lead to higher common mode volt ages which differential inputs are able to remove rejection such as the DNx Al 225 or the DNx Al 207 The higher the speed of measurement the more noise can be expected The following table shows test results for noise for the Al 201 when used in conjunction with the STP AI U terminal in differential mode with high gains Although the DNx Al 201 is capable of performing thermocouple measurement such a task is best reserved for layers with higher resolution and better noise Table 1 3 Gain Performance of DNx Al 201 Layer with Various Thermocouple Types Gain 1000 Performance Gain 100 Performance Thermo couple Temperature 100 Points Temperature f 100 Points Type Range P P Noise RMS Noise Range P p Noise RMS Noise B 0 1810 3 1 Full 8 2 C 0 800 1 0 3 range 2 1 E 290 to 220 0 5 0 15 of 1 0 35 J 210 to 270 0 5 0 15 hermacoupig 1 0 35 K 26 to 360 0 5 0 2 1 5 0 5 N 270 to 450 0 3 1 R 50 to 1320 0 8 5 1 8 S 50 to 1450 0 8 2
20. eeeeeteteeeeeetnaeeeeetenea 5 1 2 The DNA AI 201 Analog Input Layer cceceeeeeneeeeeeeeeeeeeeeeeaeeeeeeeeaeeeeeeeeaeeeeeeenea 5 1 3 Pinout Diagram of the DNX AI 201 eeeccececeeeeeeeeeeecaeeeeeeeeeeeaeeeeeeeeeseaaeeeeeeeeesiaeeeseneees 6 1 4 Recommended Ground Connections for Analog INputs ccccsecteeeeeeeeessteeeeeneees 7 Zs sch nee Se aneii Tel 508 921 4600 www ueidaq com Vers 4 6 b j pene energie Date September 2013 DNx Al 201 ManualLOF fm DNA DNR AI 201 Analog Input Board Chapter 1 Introduction Chapter 1 Introduction This document outlines the feature set and use of the DNR and DNA AI 201 layer The Al 201 is a four channel strain gauge input module for the PowerDNA I O Cube DNA AI 201 and the PowerDNR HalfRACK RACKtangle and the FlatRACK chassis DNR AI 201 1 1 Organization This Al 201 User Manual is organized as follows of Manual e Introduction This chapter provides an overview of DNx Al 201 Analog Input Board features device architecture connectivity and logic e Programming with the High Level API This chapter provides an overview of the how to create a session configure the session and interpret results with the Framework API e Programming with the Low Level API This chapter is an overview of low level API commands for configuring and using the Al 201 series layer e Appendix A Accessories This appendix provides a list of accessories available for use with the DNx Al 201 board e
21. hers related to cube operation Function Description DgAdv201Read This function works using underlying DqReadAlChannel but converts data using internal knowledge of input range and gain of every channel Copyright 2013 Tel 508 921 4600 www ueidaq com Vers 4 6 United Electronic Industries Inc Date September 2013 DNx Al 201 Chap3 fm 16 3 1 Configuration Settings DNA DNR AI 201 Analog Input Board Chapter 3 Programming with the Low level API 17 Configuration setting are passed in DqCmdSetCfg andDgAcbInitOps functions Not all configuration bits apply to Al 201 layer The following bits make sense Configuration bits define define define define define define define define define define define define define define Copyright 2013 United Electronic Industries Inc DQ FIFO MODEFIFO 2L lt lt 16 continuous aquisition with FIFO For WRRD DMAP devices For RDFIFO devices stream the FIFO data automatically For WRFIFO do NOT send reply to WRFIFO unless needed enable layer irqs stop trigger edge MSB stop trigger edge 00 software fe Ode aeste Say 02 falling start trigger edge is MSB start trigger edge 00 software AI Tri Sing H 02 falling CV clock source MSB CV clock source is Jf 201 SGU 0 HN 11 EXT ie Cle clock A Cle clock 01 SW 11 E
22. ift between different channels DQ_LN ACTIVE is needed to switch on STS LED on the CPU layer You can select either the CL clock or the CV clock as a timebase If you select both clocks the CL clock is taken as a timebase and the CV clock determines the delay between converting channels i e settling time In the following picture CL refers to the CL Clock also known as the Channel List clock or the Scan Clock CV refers to the CV Clock also known as the Conversion Clock cV cV cV Time a Moment of Digitization Signal level at the moment of digitization Note that t shows the time between individual samples on the A D the time between CV clock cycles is limited by the board s maximum digitization rate and settling time If you need to increase the settling time between samples slow down the board by decreasing its digitization rate Next t is the minimal time between scans of the Channel List it depends on t4 and the number of entries in the Channel List The value of 1 t is the maximum scan rate in Hz The effective per channel sampling rate also depends on the number of channels in the Channel List In this case a layer acquires data across all channels sequentially at the selected speed which need not be the peak speed and this rate is called the aggregate rate When the Channel List contains two channels for example the per channel rate is one half the aggregate rate For multiple channels you can thus cal
23. low the gain limit When the gain is set too high the output will appear as an inverted approx imate of the actual signal scaled down under the gain limit Try a lower gain value or begin with one 2 3 1 Thermocouple For thermocouples use the object method CreateTCChannel which automat Measurement ically handles temperature calculations as follows Configure channel 0 to 2 scaling for thermocouples thermocouple Type K degrees F using CJC built in compensation from the STP AI U board in differential mode aiSession CreateTCChannel pdna 192 168 100 2 Dev0 Ai0 2 SPSO L507 ThermocoupleType TypeK TemperatureScale Fahrenheit ColdJunctionCompensationType BuiltIn Ore ele AIChannelInputMode Differential 2 3 2 RTD Resistance Temperature Detector RTD measurements are configured using Measurement the Session object method CreateRTDChannel RTD sensors are resistive sensors whose resistance varies with temperature Knowing the resistance of an RTD we can calculate the temperature using the Callendar Van Dusen equations RTD sensors are specified using the alpha a constant It is also known as the temperature coefficient of resistance which defines the resistance change factor per degree of temperature change The RTD type is used to select the proper coefficients A B and C for the Callendar Van Dusen equation which is used to convert resistance measurements to temperature To measu
24. minate the resistors shown in Figure 1 4 for floating differential input signals 1 RTD is a Resistance Temperature Detector a resistor that changes resistance with its temperature sometimes called Platinum Resistance Thermometers PRT because most of them are fabricated of platinum wire or thin film EE Feroe NEUSIE ne Date September 2013 DNx Al 201 Chap1x fm Copyright 2013 Tel 508 921 4600 www ueidaq com Vers 4 6 7 DNA DNR AI 201 Analog Input Board Chapter 1 8 Introduction 1 8 Layer A layer is capable of acquiring analog input voltage in the 15V range with gains Capabilities of 1 2 5 10 DNx Al 201 100 801 or 1 10 100 1000 DNx Al 201 16 A layer is capable of generating its own CL and CV clocks and trigger and deriving them from either local external lines from its connector or from the SYNCx bus You can connect a signal source to the layer using either differential or single ended wiring Because of this the ground plane is isolated from the system ground single ended and pseudo differential wiring use effectively the same wiring Table 1 2 Gains Settling Time R lution Card Gain Range ae Noise LSB ee d Resolution DNA AI 201 16 1 15V 62 5us 0 81 457uV 10 1 5V 100us 1 05 45uV 100 150mV 800us 1 58 40u V 1000 15mV 2 1ms 4 32 30u V DNA AI 201 100 1 15V 10us 1 04 457uV g 2 7 5V 15us 1 28
25. n on all input pins e All analog I O is fully opto isolated from the rest of the system e Additional dedicated differential channel for CJC compensation e Auto calibration software initiated e Precision digitally calibrated to 0 001 3ppm C on board reference e 3 configurable multi purpose DIO lines default configuration CLKOUT CLKIN TRIGIN value of the DIO lines delivered along with analog input sample e 1k samples input FIFO with 32 bit per sample timestamp e Interrupt request on any position in the input or channel list FIFO e On board EEPROM to store configuration and calibration data Input ground to system ground isolation 350Vims e Power consumption 1 6 2 2W e Weight of 120 g or 4 24 oz for DNA AIl 217 630 g or 22 2 oz with PPC5 e UEI Framework Software API may be used with all popular Windows programming languages and most real time operating systems such as RT Linux RTX or QNX and graphical applications such as LabVIEW MATLAB DASYLab and any application supporting Activex or OPC Copyright 2013 i Tel 508 921 4600 www ueidag com Vers 4 6 Se eve arp eee Date September 2013 DNx Al 201 Chap1x fm 3 DNA DNR AI 201 Analog Input Board Chapter 1 Introduction 1 4 Specification The technical specification for the DNx Al 201 100 board are listed in Table 1 1 EET ee Tel 508 921 4600 Date September 2013 Copyright 2013 United Electronic Industries Inc Resolution
26. nd with the DOIOCTL_CVTCHNIL function under the hood When this function is called for the first time the firmware stops any ongoing operation on the device specified and reprograms it accordingly with the channel list supplied This function uses the preprogrammed CL update frequency 10Hz You can reprogram the update frequency by calling the DqCmdSetClk command after the first call to DgAdv201Read Therefore you cannot call this function when the layer is involved in any streaming or data mapping operations If you specify a short timeout delay this function can time out when called for the first time because it is executed as a pending command and layer programming takes up to 10ms Once this function is called the layer continuously acquires data and every next call function returns the latest acquired data If one would like to cancel ongoing sampling call the same function with OxFFFFFFFF as a channel number Tel 508 921 4600 www ueidag com Vers 4 6 Date September 2013 DNx Al 201 Chap3 fm DNA DNR AI 201 Analog Input Board Appendix A 20 Appendix A A Accessories The following cables and STP boards are available for the Al 201 layer DNA CBL 37 This is a 37 conductor flat ribbon cable with 37 pin male D sub connectors on both ends The length is 3ft and the weight is 3 4 ounces or 98 grams DNA CBL 37S This is a 37 conductor round shielded cable with 37 pin male D sub connectors on both ends It is ma
27. ntax is similar to a String web URL lt device class gt lt IP address gt lt Device Id gt lt Subsystem gt lt Channel list gt For PowerDNA and RACKtangle the device class is pdna For example the following resource string selects analog input lines 0 1 2 3 on device 1 at IP address 192 168 100 2 pdna 192 168 100 2 Dev1 Ai0 3 as a range or as a list pdna 192 168 100 2 Dev1 Ai0 1 2 3 2 3 Configuring The Al 201 can be configured for voltage measurement input To program the for Input analog input circuitry configure the channel list using the session s object method CreateAlChannel The gain applied on each channel is specified by using low and high input limits For example the DNA AI 201 100 available gains are 1 2 5 10 and the maximum input range is 15V 15V To select the gain of 10 you need to specify input limits of 1 5V 1 5V Configure channels 0 1 to use gain of 10 in differential mode aiSession CreateAIChannel pdna 192 168 100 2 Dev0 Ai0 1 5g TES UeiAIChannelInputModeDifferential ne ee EEE a a a EE T E Copyright 2013 i Tel 508 921 4600 www ueidaq com Vers 4 6 pates ue ngusties ne Date September 2013 DNx Al 201 Chap2x fm DNA DNR AI 201 Analog Input Board Chapter 2 13 Programming with the High Level API Be mindful of your gain setting Note that when reading any of the channels in point by point mode the hardware actively keeps the data just be
28. nted system whichever is applicable The term DNR is a specific reference to the RACKtangle DNA to the PowerDNA I O Cube and DNx to refer to both Copyright 2013 i Tel 508 921 4600 www ueidaq com Vers 4 6 a a Date September 2013 DNx Al 201 Chap1x fm DNA DNR AI 201 Analog Input Board Chapter 1 Introduction 1 2 The Al 201 The DNA DNR AI 201 is a 24 channel single ended 12 channel differential A D Interface board The DNA boards are compatible with all of our popular CUBE series Board chassis while the DNR series boards are used in the RACKtangle I O series chassis Both versions provide identical electrical specifications and performance including 16 bit resolution with a maximum input range of 15V The board is fully isolated from the PowerDNA cube and is the ideal A D board for a wide variety of high speed high resolution data acquisition DAQ and control applications 1 3 Features The Al 201 layer has the following features e 24 single ended 12 differential inputs e 15V input range e DNx Al 201 16 version offers gains of 1 10 100 1000 per channel selectable maximum speed is 16kS sec on multiple channels e DNx Al 201 100 and 801 version offer gains of 1 2 5 10 per channel selectable maximum speed is 100kS sec on multiple channels e Completely configurable per channel settling time delay with better than 1uS resolution e 16 bit resolution no missing codes e 40V overvoltage 2kV ESD protectio
29. re the RTD resistance we need to know the amount of current flowing through it We can then calculate the resistance by dividing the measured voltage by the known excitation current To measure the excitation current we measure the voltage from a high precision reference resistor whose resistance is known The reference resistor is built into the terminal block if you are using a DNA STP AI U but you can provide your own external reference resistor if you prefer In addition you must configure the RTD type and its nominal resistance at 0 Celsius as shown in the example that follows LEE Se EEE ee eee eee EE EEE ee Se ee Copyright 2013 i Tel 508 921 4600 www ueidaq com Vers 4 6 See eve arp eee Date September 2013 DNx Al 201 Chap2x fm DNA DNR AI 201 Analog Input Board Chapter 2 14 Programming with the High Level API Add 4 channels 0 to 3 to the channel list and configure them to measure a temperature between 0 0 and 200 0 deg C The RTD sensor is connected to the DAQ device using two wires the excitation voltage is 5V and the reference resistor is the 20kOhms resistor built into the DNA STP AI U The RTD alpha coefficient is 0 00385 the nominal resistance at 0 C is 100 Ohms and the measured temperature will be returned in C aiSession CreateRTDChannel pdna 192 168 100 2 dev0 Ai0 3 0 1000 0 UeiTwoWires 52107 UeiRefResistorBuiltIn 20000 0 UeiRTDType3850 LOO RO
30. y reference to ground or other inputs When working with a DNx Al 201 layer in differential mode Aln0 and Aln12 form the High and Low inputs of differential inout Ch 0 next for differential input Ch 1 use Aln1 and Aln13 follow this pattern for all twelve differential input pairs Copyright 2013 i Tel 508 921 4600 www ueidaq com Vers 4 6 See eve arp eee Date September 2013 DNx Al 201 Chap1x fm DNA DNR AI 201 Analog Input Board Chapter 1 Introduction Two high impedance amplifiers monitor the voltage between the inputs and the PC ground A third amplifier measures the difference between the Positive and 1 8 3 Thermocouple Measurement Negative inputs eliminating any voltage common to both wires This method eliminates problems that can arise with a single ended system because this configuration attenuates noise common to both channel inputs common mode noise Thus it s wise to use twisted pair cable to bring signals to the data acquisition layer because that setup ensures that any noise generated along the wiring path is the same for each line and the amplifier subtracts this noise Although using differential inputs cuts in half the number of channels you can read with a given layer compared to single ended or pseudo differential setups there are several cases where you are well advised to use differential inputs such as e When signal leads are over a few meters in length The instrumentation amp can eliminate the eff
Download Pdf Manuals
Related Search