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LPC178x/7x - NXP Semiconductors

1. Symbol Conditions Thermal resistance in C W 15 TFBGA208 TFBGA180 6ja JEDEC 4 5 in x 4 in 0 m s 41 45 5 1 m s 35 38 3 2 5 m s 31 33 8 8 layer 4 5 in x 3 in 0 m s 34 9 38 1 m s 30 9 33 5 2 5 m s 28 29 8 6jc 8 3 8 9 jb 13 6 12 LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 70 of 123 NXP Semiconductors LPC178x 7x 10 Static characteristics 32 bit ARM Cortex M3 microcontroller Table 13 Static characteristics Tamb 40 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Supply pins Vpp 3v3 supply voltage 3 3 V external rail 2 4 3 3 3 6 V Vpp REG 3V3 regulator supply voltage 2 4 3 3 3 6 V 3 3 V VDDA analog 3 3 V pad supply 2 7 3 3 3 6 V voltage Vi vBAT input voltage on pin 41 12 1 3 0 3 6 V VBAT Vi VREFP input voltage on pin 2 7 3 3 VppA V VREFP Ipp REG 3V3 regulator supply current active mode code 3 3 V while 1 executed from flash all peripherals disabled PCLK CCLK 4 CCLK 12 MHz PLL 7 mA disabled CCLK 120 MHz PLL BIF 51 mA enabled active mode code while 1 executed from flash all peripherals enabled PCLK CCLK 4 CCLK 12 MHz PLL 5 6 14
2. LPC178x 7x LM3526 L USB PPWR2 FLAGA USB OVRCR2 VsSCORE Mini AB connector Vssio Fig 32 USB OTG port configuration port 1 OTG dual role device port 2 host USB PWRD2 VBUS USB_D 2 330 D USB A USB_D 2 330 D connector 15kQ 15 ind USB_UP_LED2 L e 002aag506 LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 99 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Vpp RSTOUT RESET N USB TX E1 N INT N DAT VP SEO VM USB TX DP1 USB TX DM1 RCV VP USB USB RX DP1 USB DM1 VM USB MINI AB connector 330 LPC178x 7x ADR PSW Vssio SPEED VSSCORE SUSPEND USB_SCL1 USB SDA1 USB INT1 USB UP LED1 _ 74 002aag507 Fig 33 USB OTG port configuration VP VM mode LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product
3. 40 15 10 35 60 85 temperature Conditions BOD disabled Fig 10 Power down mode Typical regulator supply current Ipp REGy av3 Versus temperature LPC178X 7X Product data sheet All information provided in this document is subject to legal disclaimers Rev 5 3 16 October 2015 NXP Semiconductors N V 2015 All rights reserved 74 of 123 LPC178x 7x 32 bit ARM Cortex M3 microcontroller NXP Semiconductors 002aah074 2 0 IBAT pA 1 6 1 2 0 8 0 4 40 15 10 35 60 85 temperature Conditions Vpp REG 3V3 VppA Vpp 3v3 0 VBAT 3 0 V Fig 11 Part powered off Typical battery supply current Igar versus temperature LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 75 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller 10 2 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the PCONP register All other blocks are disabled and no code is executed Measured on a typical sample at Tamb 25 C The peripheral clock was set to PCLK CCLK 4 with CCLK 12 MHz 48 MHz and 120 MHz The
4. COMPARATOR cz BLOCK C2 Cia Rvsi Vss VEXT 447 002aag613 The values of resistor components Remp and Rew vary with temperature and input voltage and are process dependent Fig 29 ADC interface to pins ADCO IN n Table 30 ADC interface components Component Range Description Remp 900103000 Switch on resistance for the comparator input switch Varies with temperature input voltage and process Rew 500 O to 2 Switch on resistance for channel selection switch Varies with temperature input voltage and process C1 110 fF Parasitic capacitance from the ADC block level C2 80 fF Parasitic capacitance from the ADC block level C3 1 6 pF Sampling capacitor 13 DAC electrical characteristics Table 31 10 bit DAC electrical characteristics VppA 2 7 V to 3 6 V Tamp 40 C to 85 C unless otherwise specified Symbol Parameter Min Typ Max Unit Ep differential linearity error 1 LSB EL adj integral non linearity z 1 5 LSB Eo offset error 0 6 gain error 0 6 96 CL load capacitance 200 pF RL load resistance 1 LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 97 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cor
5. 2 3 clk 7 2 8 Toy 3 8 BLS LOW to BLS HIGH PB 1 WAITWR WAITWR WAITWR ns time WAITWEN 3 x WAITWEN 3 WAITWEN 3 x 7 2 6 7 3 4 clk 4 9 tWEHDNV WE HIGH to data WRg 1 2 5 Toy clk 3 3 4 3 Toy cik ns invalid time twEHEOW WE HIGH to end of WR PB 1 1816 Toy clk 2 7 Toy clk 3 4 4 6 ns write time BLS HIGH to data PB 1 2 7 3 6 4 8 ns invalid time tWEHANV WE HIGH to address PB 1 2 4 3 0 3 9 ns invalid time LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 81 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Table 17 Dynamic characteristics Static external memory interface continued 30 pF Tamb 40 C to 85 Vpp sya 3 0 V to 3 6 V Values guaranteed by design Symbol Parameter Conditions Min Typ Max Unit tdeact deactivation time WRg PB 0 2 7 3 4 4 7 ns PB 1 tesLeLs CS LOW to BLS LOW WRg PB 0 8 2 8 3 7 Toy cik 5 1 Toig 5 1 WAITWEN 1 WAITWEN 1 WAITWEN
6. 0 Motor control PWM channel 0 feedback input lO SSPO SCK Serial clock for SSPO LCD VD 6 LCD data LCD VD 10 LCD data LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 18 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Table 3 description continued Not all functions are available on all parts See Table 2 Ethernet USB LCD QEI SD MMC DAC pins and Table 7 EMC pins Symbol 2 Description E Hos s 2 T 5 a r7 GONE l le zoER l l 9 B 5 m a a c P1 21 72 R8 6 50 lO P1 21 General purpose digital input output pin U lo USB TX DM 1 D transmit data for USB port 1 OTG transceiver PWMH 3 Pulse Width Modulator 1 channel 3 output lO SSPO SSEL Slave Select for SSPO MC ABORT Motor control PWM active low fast abort R Function reserved LCD VD 7 LCD data LCD VD 11 LCD data P1 22 74 U8 6 51 P1 22 General purpose digital input output pin PU USB RCV1 Differential receive data for USB port 1 OTG transceiver USB PWRD1 Pow
7. 0 SCK 1 A tps tpH MOSI DATA VALID ta tha 1 MISO DATA VALID tps tDH MOSI DATA VALID DATA VALID 1 tha CPHA 0 MISO DATA VALID DATA VALID 002 830 Fig 22 SSP slave timing SPI mode All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 89 of 123 NXP Semiconductors LPC178x 7x 11 7 LPC178X 7X 32 bit ARM Cortex M3 microcontroller I2C bus Table 25 Dynamic characteristic I2C bus pins Tamb 40 C to 85 Symbol Parameter Conditions Min Max Unit SCL clock Standard mode 0 100 kHz frequency Fast mode 0 400 kHz Fast mode Plus 0 1 MHz ir fall time 4151617 of both SDA and 300 ns SCL signals Standard mode Fast mode 20 0 1 Cp 300 ns Fast mode Plus E 120 ns LOW period of Standard mode 4 7 us the SCL clock Fast mode 1 3 us Fast mode Plus 0 5 us THIGH HIGH period of Standard mode 4 0 us the SCL clock Fast mode 0 6 us Fast mode Plus 0 26 us data hold time BIAI lt 0 us Fast mode 0 us Fast mode Plus 0 us tsu DaAT data set up 191010 Standard mode 250 ns time Fast mode 100 ns Fast mode Plus 50 ns See the 2 spe
8. ERE DR 67 Brownout detection 67 Code security Code Read Protection CRP 67 APB 68 AHB multilayer matrix 68 External interrupt inputs 68 Memory mapping control 68 Debug 68 continued gt gt NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 122 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller 8 Limiting 69 9 Thermal characteristics 70 10 Static 71 10 1 Power consumption 74 10 2 Peripheral power consumption 76 10 3 Electrical pin characteristics 78 11 Dynamic characteristics 80 11 1 Flash 80 11 2 External memory interface 81 11 3 External 87 11 4 Internal 5 87 11 5 VO pins mm Sede RR wee 87 11 6 2 88 11 7 1 2 90 11 8 126 91 11 9 pO M E e 92 11 10 93 12 ADC electrical characteristics 94
9. description continued Not all functions are available on all parts See Table 2 Ethernet USB LCD QEI SD MMC DAC pins and Table 7 EMC pins Symbol 8 9 Description S lt x x z O 4 5 r7 le e E a o t 5 E o g m a a P2 5 140 16 F12 97 P2 5 General purpose digital input output pin U PWM1 6 Pulse Width Modulator 1 channel 6 output 01 DTR Data Terminal Ready output for UART1 Can also be configured to be an RS 485 EIA 485 output enable signal for UART1 T2 MATO Match output for Timer 2 channel 0 R Function reserved TRACEDATA 0 Trace data bit 0 R Function reserved LCD LP Line synchronization pulse STN Horizontal synchronization pulse TFT P2 6 138 E17 F13 96 BI 2 6 General purpose digital input output pin PU PWM1 CAPO Capture input for PWM1 channel 0 U1 RI Ring Indicator input for UART1 T2_CAPO Capture input for Timer 2 channel 0 U2 OE RS 485 EIA 485 output enable signal for UART2 TRACECLK Trace clock LCD VD 0 LCD data LCD VD 4 LCD data P2 7 136 G16 G11 95 BI P2 7 General purpose digital input output pin PU CAN RD2 CAN receiver input U1 RTS Request to Send output for UART1 Can also be configured to be an RS 485 EIA 485 output enable signal for UART1 R Function res
10. BLS LOW to BLS HIGH PB 0 3 WAITWR WAITWR WAITWR ns time WAITWEN 3 WAITWEN 3 x WAITWEN 3 x 2 6 Toy cl 3 4 4 9 tgisugow BLS HIGH to end of WR 0 BI 2 6 3 3 Toy cik 4 4 Toyiclk ns write time BLS HIGH to data WR12 31 12 7 3 6 4 8 ns invalid time PB 0 1 Parameters are shown as RD or WD in Figure 16 as indicated in the Conditions column 2 Parameters specified for 40 of Vpp ava for rising edges and 60 of Vpp ava for falling edges 3 1 EMC_CLK see LPC178x 7x User manual UM10470 4 5 Latest of address valid CSx LOW OE LOW BLSx LOW PB 1 After End Of Read EOR Earliest of EMC_CSx HIGH OE HIGH BLSx HIGH PB 1 address invalid 6 End Of Write EOW Earliest of address invalid CSx HIGH BLSx HIGH PB 1 CSx EMC OE EMC BLSx EMC WE EMC Dx EMC Ax M RD __ gt EOR Fig 16 External static memory read write access PB 0 WR1 EOW 002aag214 LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 82 of 123 NXP Semiconductors LPC17
11. Ena m 0 C me me svete conten APB BRIDGE 1 i d connected to GPDMA 002aaf528 1 Not available on all parts See Table 2 Fig 1 Block diagram NXP Semiconductors N V 2015 All rights reserved 7 of 123 LPC178X 7X Product data sheet All information provided in this document is subject to legal disclaimers Rev 5 3 16 October 2015 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller 6 Pinning information LPC178X_7X 6 1 Pinning Fig 2 LPC178x 7xFBD208 002aaf518 Pin configuration LQFP208 Fig 3 ball A1 index area 2 4 6 8 10 12 14 16 13 5 7 9 11 13 15 17 OOOO OOOO 178 7 OOOO OOOO OOOO OOOO m o gt 4 A I m Uu 2 002aaf529 Transparent top view Pin configuration TFBGA208 All information provided in this document is subject to legal disclaimers
12. PwMi 1 Pulse Width Modulator 1 channel 1 output U1 TXD Transmitter output for UART1 R Function reserved R Function reserved R Function reserved R Function reserved LCD PWR LCD panel power enable LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 21 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Table 3 description continued Not all functions are available on all parts See Table 2 Ethernet USB LCD QEI SD MMC DAC pins and Table 7 EMC pins Symbol 9 9 Description E S lt o O 4 5 r7 Ww Wwe bs a e Ju o 5 E o g m a a P2 1 152 E14 C14 106 BI P2 1 General purpose digital input output pin U 1 2 Pulse Width Modulator 1 channel 2 output U1 RXD Receiver input for UART1 R Function reserved R Function reserved R Function reserved Function reserved LCD LE Line end signal P2 2 150 D15 E11 105 3 I lO P2 2 General purpose digital input output pin PU PWM1 3 Pulse Width Modulator 1 channel 3 output 01
13. specialized 2 pad UO RXD Receiver input for UARTO PO 2 202 C4 D5 1141 BI PO 2 General purpose digital input output pin PU UO TXD Transmitter output for UARTO U3 TXD Transmitter output for PO 3 204 D6 1142 BI PO 3 General purpose digital input output pin PU UO RXD Receiver input for UARTO U3 RXD Receiver input for UART3 PO 4 168 B12 A11 116 BI l PO 4 General purpose digital input output pin PU 125 SCK 125 Receive clock It is driven by the master and received by the slave Corresponds to the signal SCK in the 5 specification CAN RD2 CAN receiver input 2_ Capture input for Timer 2 channel 0 R Function reserved R Function reserved R Function reserved O LCD VD 0 LCD data LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 10 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Table 3 description continued Not all functions are available on all parts See Tab
14. Ethernet MIIM data input and output 125 125 receive master clock P1 18 66 P7 15 46 B P1 18 General purpose digital input output pin PU OQ USB UP LED1 It is LOW when the device is configured non control endpoints enabled or when the host is enabled and has detected a device on the bus It is HIGH when the device is not configured or when host is enabled and has not detected a device on the bus or during global suspend It transitions between LOW and HIGH flashes when the host is enabled and detects activity on the bus PWM1 1 Pulse Width Modulator 1 channel 1 output T1 Capture input for Timer 1 channel 0 R Function reserved lO SSP1 MISO Master In Slave Out for SSP1 P1 19 68 U6 P5 47 B P1 19 General purpose digital input output pin PU USB TX E1 Transmit Enable signal for USB port 1 OTG transceiver USB PPWR1 Port Power enable signal for USB port 1 T1 CAP1 Capture input for Timer 1 channel 1 MC 0A Motor control PWM channel 0 output lO SSP1 SCK Serial clock for SSP1 U2 OE RS 485 EIA 485 output enable signal for UART2 P1 20 70 07 K6 49 HB 1 20 General purpose digital input output pin PU USB TX DP1 D transmit data for USB port 1 transceiver PWM1 2 Pulse Width Modulator 1 channel 2 output QEI PHA Quadrature Encoder Interface PHA input
15. Features The MCI provides all functions specific to the SD MMC memory card These include the clock generation unit power management control and command and data transfer e Conforms to Multimedia Card Specification v2 11 Conforms to Secure Digital Memory Card Physical Layer Specification v0 96 Can be used as a multimedia card bus or a secure digital memory card bus host The SD MMC can be connected to several multimedia cards or a single secure digital memory card DMA supported through the GPDMA controller Fast general purpose parallel I O Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers Pins may be dynamically configured as inputs or outputs Separate registers allow setting or clearing any number of outputs simultaneously The value of the output register may be read back as well as the current state of the port pins LPC178x 7x use accelerated GPIO functions All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 51 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller GPIO registers are accessed through the AHB multilayer bus so that the fastest possible I O timing can be achieved Mask registers allow treating sets of port bits as a group leaving other bits unchanged All GPIO registers are by
16. LCD VD 4 LCD data LCD VD 3 LCD data LCD VD 8 LCD data LCD VD 18 LCD data LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 24 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Table 3 description continued Not all functions are available on all parts See Table 2 Ethernet USB LCD QEI SD MMC DAC pins and Table 7 EMC pins Symbol Description 1 Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Reset state P2 13 10 1 P2 13 General purpose digital input output pin This pin includes a 10 ns input glitch filter c EINT3 External interrupt 3 input lO 80 DAT 3 Data line for SD card interface 125 TX SDA Transmit data It is driven by the transmitter and read by the receiver Corresponds to the signal SD in the S bus specification R Function reserved LCD VD 5 LCD data LCD VD 9 LCD data LCD VD 19 LCD data P2 14 91 R12 l B yu P2 14 General purpose digital input output pin PU CS2 LOW active Chip Select 2 signal O 2 5 12 1 data input output this pin does not use specialized
17. Product data sheet Rev 5 3 16 October 2015 NXP Semiconductors N V 2015 All rights reserved 116 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Table 35 Revision history continued Document ID Release date Data sheet status Change notice Supersedes LPC178X_7X v 5 20140501 Product data sheet LPC178X_7X v 4 1 Modifications Removed overbar from NMI Table 3 Added minimum reset pulse width of 50 ns to RESET pin Updated Table note 14 for RTCX pins 32 kHz crystal must be used to operate RTC Added boundary scan information to description for RESET pin Updated pin description of STCLK Table 13 Added Table note 3 VDDA and VREFP should be tied to VDD 3V3 if the ADC and DAC are not used Table 23 Removed reference to RESET pin from Table note 1 Table 24 Removed Toy Pcik spec already given by the maximum chip frequency Changed min clock cycle time for SSP slave from 120 to 100 Updated Table note 1 and Table note 3 Table 29 Added Table note 1 VDDA and VREFP should be tied to VDD 3V3 if the ADC and DAC are not used Section 7 21 1 Features Changed max speed for SSP master from 60 to 33 e and added typical specs Table 17 Table 18 Table 19 SOT570 2 obsolete replaced with SOT570 3 Table 17 Updated timing specs to CL 30 pF Added typical specs Table note 3 Changed Tey
18. T3_CAPO Capture input for Timer channel 0 LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 25 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Table 3 description continued Not all functions are available on all parts See Table 2 Ethernet USB LCD QEI SD MMC DAC pins and Table 7 EMC pins Symbol 2 Description co N S x a x O 4 5 a r7 e LL LL bs a a o o g amp m e a P2 23 64 05 BI P2 23 General purpose digital input output pin U DYCS3 SDRAM chip select 3 lO 55 0 SSEL Slave Select for SSPO CAP1 Capture input for Timer channel 1 P2 24 53 5 lO P2 24 General purpose digital input output pin PU SDRAM clock enable 0 P2 25 54 4 2 BI P2 25 General purpose digital input output pin PU CKE1 SDRAM clock enable 1 P2 26 57 T4 l lO P2 26 General purpose digital input output pin PU CKE2 SDRAM clock enable 2 lO 55 0 MISO Master In Slave Out for SSPO MATO Match output for Timer 3 channel 0 P2 27 47 BI 2 27 General purpose
19. 1 CCLK to 1 Table 18 Updated timing specs to CL 30 pF Added typical specs Removed All programmable delays EMCDLYCTL are bypassed from table title Table 19 Updated timing specs to CL 30 pF Added typical specs Removed All programmable delays EMCDLYCTL are bypassed from table title LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 117 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Table 35 Revision history continued Document ID Release date Data sheet status Change notice Supersedes LPC178X_7X v 4 1 20121115 Product data sheet LPC178X 7X v 4 Modifications LCD timing characteristics updated in Table 27 Dynamic characteristics LCD and Figure 26 added Removed table note peak current is limited to 25 times the corresponding maximum current in Table 9 Removed deep power down spec Table 13 and associated table note Updated min value for twgugow Table 15 Removed Fig 21 Internal RC oscillator frequency versus temperature Updated 12 bit and 8 bit values for Table 29 Changed data sheet status to Product LPC178X 7X v 4 20120501 Preliminary data sheet LPC178X 7X v 3 Modifications
20. Editorial updates BOD values added in Section 7 34 2 Parameters tcsi gi 1 5 toEHANV tdeact BLsHEOW tBLsHpNv Updated in Table 17 C 10 pF added to Table 24 Table 26 Table 28 Ipp REG 3va corrected in Table 13 for conditions Deep sleep mode Power down mode and Deep power down mode Igar corrected in Table 13 for condition Deep power down mode Power consumption data in Figure 9 and Figure 10 corrected I O voltage Vpp sva specified in Table 17 Table 18 Table 19 Table 24 Table 28 Vpp ava range corrected in Table 23 Parameter C changed to 10 pF for EMC timing in Table 17 to Table 20 USB and Ethernet dynamic characteristics removed Timing characteristics follow USB 2 0 Specification full speed and IEEE standard 802 3 standards see Section 7 15 and Section 7 14 for compliance statements Pad characteristics updated in Table 3 Parameter Igar updated in Table 13 Figure 11 added SDRAM timing corrected in Figure 19 EEPROM erase and programming times added Table 16 Data sheet status changed to preliminary LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 118 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Table 35 Revision history continued Document ID Release date Data sheet stat
21. P4 19 Row 1 PO 31 2 USB D 2 3 P3 24 4 PO 30 5 P2 19 6 P1 21 7 P1 23 8 P2 21 9 VDD REG 3V3 10 P1 29 11 PO 1 12 P4 16 13 P4 17 14 P2 12 Row P 1 P2 24 2 P2 25 3 P2 18 4 Vss 5 P1 19 6 P2 20 7 P1 24 8 P1 26 9 P2 16 10 1 28 11 P2 17 12 PO 11 13 P4 4 14 4 18 7 Functional description LPC178X 7X 7 1 Architectural overview The ARM Cortex M3 includes three AHB Lite buses the system bus the I code bus and the D code bus The and D code core buses are faster than the system bus and are used similarly to Tightly Coupled Memory TCM interfaces one bus dedicated for instruction fetch I code and one bus for data access D code The use of two core buses allows for simultaneous operations if concurrent operations target different devices All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 40 of 123 NXP Semiconductors LPC178x 7x LPC178X 7X 7 2 7 3 7 4 7 5 7 6 32 bit ARM Cortex M3 microcontroller The LPC178x 7x use a multi layer AHB matrix to connect the ARM Cortex M3 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slaves ports of the matrix to be accessed simultaneously by different bus mas
22. is the maximum difference between the center of the steps of the actual transfer curve of the non calibrated ADC and the ideal transfer curve See Figure 28 See Figure 29 10 8 bit resolution is achieved by ignoring the lower four bits of the ADC conversion result All information provided in this document is subject to legal disclaimers NXP Semiconductors 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 95 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller 4095 offset error Eo gain error Ec 4094 4093 4092 4091 4090 7 code out 1LSB ideal ii 1 2 3 4 5 6 7 4090 4091 Via LSBideal 1 LSB offset error Eo Example of an actual transfer curve 4092 4 VREFP Vss 4096 093 4094 4095 4096 002 436 1 2 The ideal transfer curve 3 Differential linearity error Ep 4 Integral non linearity 5 Center of a step of the actual transfer curve Fig 28 12 bit ADC characteristics LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 96 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller LPC178x 7x Rem p 900 3000 ADC ADO n
23. specialized 2 pad lO SSP1 SSEL Slave Select for SSP1 P4 22 123 K14 4 22 General purpose digital input output PU wo A 22 External memory address line 22 U2 TXD Transmitter output for UART2 lO SSP1 MISO Master In Slave Out for SSP1 P4 23 129 J15 lO PA 23 General purpose digital input output pin PU EMC A 23 External memory address line 23 U2 RXD Receiver input for UART2 lO SSP1 MOSI Master Out Slave In for SSP1 P4 24 183 B8 C8 127 I lO PA 24 General purpose digital input output pin PU lo EMC_OE LOW active Output Enable signal 4 25 179 B9 D9 124 Bl lO P4 25 General purpose digital input output pin PU WE LOW active Write Enable signal P4 26 119 115 lO 4 26 General purpose digital input output pin PU Jo BLSO0 LOW active Byte Lane select signal 0 P4 27 139 G15 F14 lO P4 27 General purpose digital input output pin PU Jo EMC BLS1 LOW active Byte Lane select signal 1 P4 28 170 C11 D10 118 lO PA 28 General purpose digital input output pin PU Jo EMC BLS2 LOW active Byte Lane select signal 2 U3 TXD Transmitter output for UART3 T2 MATO Match output for Timer 2 channel 0 R Function reserved LCD VD 6 LCD data LCD VD 10 LCD data LCD VD 2 LCD data L
24. twa data output valid time on 25 TX SDA l 6 ns input tsu D data input set up time on 125 SDA 5 ns th D data input hold time on pin 25 RX SDA 2 ns CCLK 100 MHz peripheral clock to the 125 interface PCLK CCLK 4 125 clock cycle time Tey 1600 ns corresponds to the SCK signal in the 2 specification LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 91 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Toy clk tr tr 125 TX SCK twH twL 12S_TX_SDA twa 125 TX WS la 002aag202 V Q Fig 24 5 timing transmit Toy clk gt tf tr je 125 SCK 125 RX SDA I amp tsu D gt lt thD Y 125 RX WS lt tsu D I tsu D 002 203 Fig 25 5 timing receive 11 9 LCD Remark The LCD controller is available on parts LPC1788 87 86 85 Table 27 Dynamic characteristics LCD C 10 pF Tamb 40 C to 85 Vpp sya 3 0 V to 3 6 V Values guaranteed by design Symbol Parameter Conditions Min Max Unit folk clock frequency on pin LCD_DCLK 50 MHz data output valid delay time
25. 13 DAC electrical characteristics 97 14 Application information 98 14 1 Suggested USB interface solutions 98 14 2 Crystal oscillator XTAL input and component 102 14 3 XTAL Printed Circuit Board PCB layout 104 14 4 Standard I O pin configuration 104 14 5 Reset pin 105 14 6 Reset pin configuration for RTC operation 105 15 Package 107 16 Soldering 111 17 114 18 References 115 19 Revision 116 20 Legal 120 20 1 Data sheet status 120 20 2 120 20 3 120 20 4 121 21 Contact 121 22 2 ma 122 Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information NXP Semiconductors N V 2015 All rights reserved For more information please visit http Awww nxp com For sales office addresses please send an email to salesaddresses
26. 4 2 0 25 5 8 0 25 8 4 h RAS row address strobe hold time LI CLKDLY 1 x CLKDLY 1 x CLKDLY 1 x ns 0 25 0 6 0 25 1 2 0 25 2 9 la CASV column address strobe valid 141 CLKDLY 1 x CLKDLY 1 x CLKDLY 1 x ns delay time 0 25 4 2 0 25 5 8 0 25 8 4 th cas column address strobe hold LI CLKDLY 1 x CLKDLY 1 x CLKDLY 1 x ns time 0 25 0 6 0 25 1 2 0 25 2 9 tawv write valid delay time LI CLKDLY 1 x CLKDLY 1 x CLKDLY 1 x ns 0 25 4 9 0 25 6 6 0 25 4 9 9 thw write hold time LI CLKDLY 1 x CLKDLY 1 x CLKDLY 1 x ns 0 25 0 9 0 25 1 7 0 25 4 3 6 la av address valid delay time CLKDLY 1 x CLKDLY 1 x CLKDLY 1 x ns 0 25 4 7 0 25 6 6 0 25 4 9 6 thia address hold time CLKDLY 1 x CLKDLY 1 x CLKDLY 1 x ns 0 25 0 4 0 25 0 8 0 25 2 4 Read cycle parameters tsu D data input set up time BI FBCLKDLY 1 FBCLKDLY 1 x ns 0 25 0 3 0 25 3 1 th D data input hold time 12 FBCLKDLY 1 x FBCLKDLY 1 FBCLKDLY 1 x ins 0 25 3 7 0 25 4 3 0 25 5 2 Write cycle parameters ta av data output valid delay time LI CLKDLY 1 x CLKDLY 1 x CLKDLY 1 x ns 0 25 4 8 0 25 6 8 0 25 9 8 tha data output hold time CLKDLY 1 x CLKDLY 1 x CLKDLY 1 x ns 0 25 0 4 0 25 0 0 25 1 1 1 Refers to SDRAM clock signal CLKx 2 CLKDLY CLKOUTnDLY where n 0 1 3 The data input set up time has to be se
27. 5 3 16 October 2015 110 of 123 NXP Semiconductors LPC178x 7x 16 Soldering 32 bit ARM Cortex M3 microcontroller Footprint information for reflow soldering of LQFP208 package SOT459 1 I gt 1 EAS x A IM I E A A 1 r i ENS NN 10222 m ELS 22 ZA 1 1 ZZ ZA 1 1 2 ZZ ned I ets Hy Gy ZZ ZZA By EA 224 ER ica 2 ZZ 2222 ZA prc E ZZ rs pem 1 1 Y 7 E Weasacgm dot 17 Yi Vi A i D2 8x _ 01 a Bx gt lt Ax gt Generic footprint pattern Refer to the package outline drawing for actual layout Z solder land 2 Occupied area DIMENSIONS in mm P1 P2 Ax Ay Bx By D1 D2 Gx Gy Hx Hy 0 500 0 560 31 300 31 300 28 300 28 300 1 500 0 280 0 400 28 500 28 500 31 550 31 550 sot459 1_fr Fig 45 Reflow soldering of the LQFP208 package LPC178X_7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 111 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Footprint information for reflow sold
28. R Function reserved LCD VD 3 LCD data LCD VD 7 LCD data P2 10 110 N15 M13 76 10 PU P2 10 General purpose digital input output pin This pin includes a 10 ns input A LOW on this pin while RESET is LOW forces the on chip boot loader to take over control of the part after a reset and go into ISP mode EINTO External interrupt 0 input NMI Non maskable interrupt input P2 11 108 T17 M12 75 10 PU 2 11 General purpose digital input output pin This pin includes a 10 ns input glitch filter EINT1 External interrupt 1 input SD DATT 1 Data line 1 for SD card interface 125 TX SCK Transmit Clock It is driven by the master received by the slave Corresponds to the signal SCK in the S bus specification R Function reserved R Function reserved R Function reserved LCD CLKIN LCD clock P2 12 106 N14 N14 73 10 PU P2 12 General purpose digital input output pin This pin includes a 10 ns input glitch filter EINT2 External interrupt 2 input SD DAT 2 Data line 2 for SD card interface 125 TX WS Transmit Word Select It is driven by the master and received by the slave Corresponds to the signal WS in the S bus specification
29. disabled CCLK 120 MHz PLL 5107 100 enabled Sleep mode 5 mA Deep sleep mode SII 550 Power down mode 519 280 battery supply current RTC running 10 part powered down Vpp REGy 3v3 0 V VitvBar 3 0 V Vpp ava 0 V 1 uA part powered m lt 10 nA Vpp REG va 3 3 V Vi VBAT 3 0 V LPC178X_7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 71 of 123 NXP Semiconductors LPC178x 7x Table 13 Static characteristics continued Tamb 40 C to 85 C unless otherwise specified 32 bit ARM Cortex M3 microcontroller Symbol Parameter Conditions Min Typ Max Unit Standard port pins RESET lit LOW level input current Vj 0 V on chip pull up 0 5 10 nA resistor disabled HIGH level input Vi Vpp ava on chip 0 5 10 nA current pull down resistor disabled loz OFF state output Vo 0 V Vo Vpp avay 0 5 10 nA current on chip pull up down resistors disabled Vi input voltage pin configured to provide 151116 0 5 0 V a digital function 7 Vo output voltage output active 0 Vpp 3v3 V Vin HIGH level input 0 7Vpp ava V voltage LOW level input voltage 0 3Vpp ava V V
30. gt 12 ns tha data output hold time 0 5 ns LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 92 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller LCD DCLK LCD 002 25 The LCD panel clock is shown with the default polarity The clock be inverted via the IPC bit in the LCD POL register Typically the LCD panel uses the falling edge of the LCD DCLK to sample the data Fig 26 LCD timing 11 10 SD MMC LPC178X 7X Remark The SD MMC card interface is available on parts LPC1788 87 86 and parts LPC1778 77 76 Table 28 Dynamic characteristics SD MMC C 10 pF Tamb 40 C to 85 Vpp sya 3 0 V to 3 6 V Values guaranteed by design Symbol Parameter Conditions Min Unit folk clock frequency on pin SD_CLK data transfer mode 25 MHz on pin 50 CLK identification mode 25 MHz tsu D data input set up time on pins SD CMD SD DAT 3 0 as 6 ns inputs th D data input hold time pins SD_CMD SD DAT 3 0 as 6 ns inputs tav data output valid on pins SD SD DAT 3 0 as 23 ns delay time outputs tha data output hold time pins SD_CMD SD DAT 3 0 as 35 ns outputs lt SD_CLK SD_CM
31. with or without using the PLL The main oscillator also provides the clock source for the alternate PLL1 The main oscillator operates at frequencies of 1 MHz to 25 MHz This frequency can be boosted to a higher frequency up to the maximum CPU operating frequency by the main PLL The clock selected as the PLL input is PLLCLKIN The ARM processor clock frequency is referred to as CCLK elsewhere in this document The frequencies of PLLCLKIN and CCLK are the same value unless the PLL is active and connected The clock frequency for each peripheral can be selected individually and is referred to as PCLK Refer to Section 7 33 2 for additional information All information provided in this document is subject to legal disclaimers NXP Semiconductors 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 61 of 123 NXP Semiconductors LPC178x 7x 7 33 1 3 7 33 1 4 7 33 2 LPC178X 7X 32 bit ARM Cortex M3 microcontroller RTC oscillator The RTC oscillator provides a 1 Hz clock to the RTC and a 32 kHz clock output that can be output on the CLKOUT pin in order to allow trimming the RTC oscillator without interference from a probe Watchdog oscillator The Watchdog Timer has a dedicated watchdog oscillator that provides a 500 kHz clock to the Watchdog Timer The watchdog oscillator is always running if the Watchdog Timer is enabled The Watchdog oscillator clock can be output on the CLKOUT pin in orde
32. 2 4 ns 1 The minimum clock cycle time and therefore the maximum frequency of the SSP in master mode is limited by the pin electronics to the value given The SSP block should not be configured to generate a clock faster than that At and below the maximum frequency SSPCLKDIV x 1 SCR x CPSDVSR fmain 5The clock cycle time derived from the SPI bit rate is a function of the main clock frequency fmain the SSP peripheral clock divider SSPCLKDIV the SSP SCR parameter specified in the SSPOCRO register and the SSP CPSDVSR parameter specified in the SSP clock prescale register 2 Tamb 40 C to 85 Vpp sva 3 0 V to 3 6 V 3 12 x The maximum clock rate in slave mode is 1 12th of the PCLK rate 4 Tamb 25 Vpp 3v3 3 3 V All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 88 of 123 NXP Semiconductors LPC178x 7x LPC178X 7X 32 bit ARM Cortex M3 microcontroller SCK CPOL 0 SCK CPOL 1 Toy clk twa MOSI DATA VALID tps 1 1 MISO DATA VALID DATA VALID MOSI DATA VALID tps tbH 0 MISO DATA VALID 002aae829 Fig 21 SSP master timing in SPI mode SCK
33. 28 General purpose digital input output pin PU yo D 28 External memory data line 28 PWM1 5 Pulse Width Modulator 1 output 5 T1 CAP1 Capture input for Timer 1 channel 1 P3 29 11 BI lO PS 29 General purpose digital input output pin PU D 29 External memory data line 29 PWM1 6 Pulse Width Modulator 1 output 6 MATO Match output for Timer 1 channel 0 P3 30 19 H3 lO PS 30 General purpose digital input output pin PU yo D 30 External memory data line 30 U1 RTS Request to Send output for UART1 also be configured to be an RS 485 EIA 485 output enable signal for UART1 T1 MAT1 Match output for Timer 1 channel 1 P3 31 25 J3 lO PS 31 General purpose digital input output pin PU VO D 31 External memory data line 31 R Function reserved T1 MAT2 Match output for Timer 1 channel 2 P4 0 to lO Port 4 Port 4 is a 32 bit I O port with individual direction P4 31 controls for each bit The operation of port 4 pins depends upon the pin function selected via the pin connect block P4 0 75 09 16 52 B 4 0 General purpose digital input output pin PU yo A 0 External memory address line 0 LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors 2015 All rights reserved Product d
34. 28 x 1 4 mm SOT459 1 LPC1786 LPC1786FBD208 LQFP208 plastic low profile quad flat package 208 leads body 28 x 28 x 1 4 mm SOT459 1 LPC1785 LPC1785FBD208 LQFP208 plastic low profile quad flat package 208 leads body 28 x 28 x 1 4 mm SOT459 1 LPC1778 LPC1778FBD208 LQFP208 plastic low profile quad flat package 208 leads body 28 x 28 x 1 4 mm SOT459 1 LPC1778FET208 TFBGA208 plastic thin fine pitch ball grid array package 208 balls body SOT950 1 1571570 7 LPC1778FET180 180 thin fine pitch ball grid array package 180 balls body 12 12 0 8 mm SOT570 3 LPC1778FBD144 LQFP144 plastic low profile quad flat package 144 leads body 20 x 20 x 1 4 mm SOT486 1 LPC1777 LPC1777FBD208 LQFP208 plastic low profile quad flat package 208 leads body 28 x 28 x 1 4 mm SOT459 1 LPC1776 LPC1776FBD208 LQFP208 plastic low profile quad flat package 208 leads body 28 x 28 x 1 4mm SOT459 1 LPC1776FET180 TFBGA180 thin fine pitch ball grid array package 180 balls body 12 12 0 8mm SOT570 3 LPC1774 LPC1774FBD208 LQFP208 plastic low profile quad flat package 208 leads body 28 x 28 x 1 4 mm SOT459 1 LPC1774FBD144 LQFP144 plastic low profile quad flat package 144 leads body 20 x 20 x 1 4 mm SOT486 1 LPC178X_7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 5 of 123
35. 5 bit I O port with individual direction controls for each bit The operation of port 5 pins depends upon the pin function selected via the pin connect block P5 0 9 FA 5 6 P5 0 General purpose digital input output pin PU EMC A 24 External memory address line 24 lO 55 2 MOSI Master Out Slave In for SSP2 T2 MAT2 Match output for Timer 2 channel 2 P5 1 30 4 H1 21 B P5 1 General purpose digital input output pin PU A 25 External memory address line 25 lO 55 2 MISO Master In Slave Out for SSP2 T2 MATS Match output for Timer 2 channel 3 5 2 117 114 112 81 101 5 2 General purpose digital input output R Function reserved R Function reserved T3 MAT2 Match output for Timer channel 2 R Function reserved lO 12 0 SDA 12 0 data input output this pin uses a specialized 12 pad that supports 2 Fast Mode Plus LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 32 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Table 3 description continued Not all functions are available on all parts See Table 2 Ethernet USB LCD QEI SD MMC DAC pins and Table 7 EMC pins Symbol Description 1
36. 7x 7 33 3 7 33 4 7 33 4 1 LPC178X 7X 32 bit ARM Cortex M3 microcontroller The alternate PLL accepts an input clock frequency from the main oscillator in the range of 10 MHz to 25 MHz only When used as the USB clock the input frequency is multiplied up to a multiple of 48 MHz 192 MHz or 288 MHz as described above Wake up timer The LPC178x 7x begin operation at power up and when awakened from Power down mode by using the 12 MHz IRC oscillator as the clock source This allows chip operation to resume quickly If the main oscillator or the PLL is needed by the application software will need to enable these features and wait for them to stabilize before they are used as a clock source When the main oscillator is initially activated the wake up timer allows software to ensure that the main oscillator is fully functional before the processor uses it as a clock source and starts to execute instructions This is important at power on all types of reset and whenever any of the aforementioned functions are turned off for any reason Since the oscillator and other functions are turned off during Power down mode any wake up of the processor from Power down mode makes use of the wake up Timer The wake up timer monitors the crystal oscillator to check whether it is safe to begin code execution When power is applied to the chip or when some event caused the chip to exit Power down mode some time is required for the oscillator to p
37. Conditions Min Typ Max Unit Read cycle parameters 2 CS LOW to address RD 2 7 3 5 4 7 ns valid time tesom CS LOWto OELOW RD2 2 7 3 4 Toy cik 4 6 ns time WAITOEN WAITOEN WAITOEN CS LOW to BLS LOW n RDg 1 13 2 8 3 8 5 1 ns time OE LOW to OE HIGH RD 13 WAITRD WAITRD WAITRD ns time WAITOEN 1 WAITOEN 1 WAITOEN 1 x T oy clk 2 26 Toy clk 2 83 Tey 3 7 tam memory access time 1314 WAITRD WAITRD WAITRD ns WAITOEN 1 WAITOEN 1 WAITOEN 1 x clk 8 6 11 9 18 0 th D data input hold time BIS 4 1 5 8 ns CS HIGH to BLS HIGH PB 1 2 8 3 7 5 1 ns time tcsHoeH CS HIGH to OE HIGH 13 2 7 3 5 4 6 ns time toenany HIGH to address I3 0 1 0 1 0 16 ns invalid time tdeact deactivation time RD7 3 4 4 7 ns Write cycle parametersP2l tcstav CS LOW to address WR 2 7 3 5 4 7 ns valid time tesLDV CS LOW to data valid 2 8 3 9 5 1 ns time tcs wEL CS LOW to WE LOW WR3 PB 1 2 7 Tey clk x 3 54 4 6 ns time 1 WAITWEN 1 WAITWEN 1 WAITWEN CS LOW to BLS LOW WR4 PB 1 13 28 3 9 5 1 ns time twetweH LOW to WE HIGH WRs PB 1 13 WAITWR WAITWR WAITWR ns time WAITWEN 1 x WAITWEN 1 x wey 1 x
38. General purpose digital input output pin VO 125 TX SDA 125 transmit data It is driven by the transmitter and read by the receiver Corresponds to the signal SD in the S bus specification lO SSP1 MOSI Master Out Slave In for SSP1 T2_MAT3 Match output for Timer 2 channel 3 RTC EV2 Event input 2 to Event Monitor Recorder R Function reserved R Function reserved LCD VD 17 LCD data PO 10 98 110 69 BI PO 10 General purpose digital input output pin PU U2 TXD Transmitter output for UART2 I2C2 SDA 1262 data input output this pin does not use a specialized 2 pad MATO Match output for Timer channel 0 PO 11 100 R14 P12 70 B lO PO 11 General purpose digital input output pin PU U2 RXD Receiver input for UART2 VO 12 2 SCL 12 2 clock input output this pin does not use specialized 2 pad T3 1 Match output for Timer 3 channel 1 PO 12 41 Ri J4 29 BI PO 12 General purpose digital input output pin PU Jo USB 2 Port Power enable signal for USB port 2 lO SSP1 MISO Master In Slave Out for SSP1 ADCO IN 6 A D converter 0 input 6 When configured as ADC input the digital function of the pin must be disabled LPC178X 7X All information provided in this document is subject to legal disclaimers N
39. Modulator 0 output 1 O U1_TXD Transmitter output for UART1 LPC178X_7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 27 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Table 3 description continued Not all functions are available on all parts See Table 2 Ethernet USB LCD QEI SD MMC DAC pins and Table 7 EMC pins Symbol Description o 54 a a O S a m 7 LL LL bs a e Ju 2 o s o g m a a c P3 17 143 F15 lO P3 17 General purpose digital input output pin U VO D 17 External memory data line 17 PWMO 2 Pulse Width Modulator 0 output 2 U1 RXD Receiver input for UART1 P3 18 151 C15 PS 18 General purpose digital input output pin PU yo EMC D 18 External memory data line 18 PWMO 3 Pulse Width Modulator 0 output 3 U1 CTS Clear to Send input for UART1 P3 19 161 B14 P3 19 General purpose digital input output pin PU EMC D 19 External memory data line 19 PWMO 4 Pulse Width Modulator 0 outp
40. NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 8 of 123 NXP Semiconductors LPC178x 7x LPC178X 7X 32 bit ARM Cortex M3 microcontroller ball A1 LPC178x 7x index area 12934 5 6 78 9 1011121314 OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO gt 002aaf519 Transparent top view Fig 4 Pin configuration TFBGA180 LPC178x 7x 002aaf520 Fig5 Pin configuration LQFP144 6 2 Pin description pins on the 178 7 are 5 V tolerant and have input hysteresis unless otherwise indicated in the table below Crystal pins power pins and reference voltage pins are not 5 V tolerant In addition when pins are selected to be ADC inputs they are no longer 5 V tolerant and the input voltage must be limited to the voltage at the ADC positive reference pin VREFP All port pins Pn m are multiplexed and the multiplexed functions appear in Table 3 in the order defined by the FUNC bits of the corresponding IOCON register up to the highest used function number Each port pin can support up to eight mul
41. RMII MII interface R Function reserved T2_CAPO Capture input for Timer 2 channel 0 P1 15 182 A8 A8 126 BI P1 15 General purpose digital input output pin PU ENET RX CLK ENET REF CLK Ethernet Receive Clock MII interface or Ethernet Reference Clock RMII interface R Function reserved lO I2C2 SDA 12 2 data input output this pin does not use a specialized 2 pad LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 17 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Table 3 description continued Not all functions are available on all parts See Table 2 Ethernet USB LCD QEI SD MMC DAC pins and Table 7 EMC pins Symbol Description o a 9 SO S a r7 la l zoER e 5 5 o g m m A P1 16 180 D10 B8 125 1 16 General purpose digital input output pin U ENET MDC Ethernet MIIM clock 125 TX MCLK 12S transmit master clock P1 17 178 9 C9 123 BI P1 17 General purpose digital input output pin PU lO MDIO
42. Vpi differential input 0 D 20 10 2 V sensitivity voltage VcM differential common includes Vp range 20 0 8 2 5 V mode voltage range Vih rs se single ended receiver 20108 2 0 V switching threshold voltage VoL LOW level output Ri of 1 5 to 3 6 V 20 0 18 V voltage for low full speed HIGH level output of 15 to GND 2028 3 5 V voltage driven for low full speed Cirans transceiver capacitance pin to GND 20 20 pF Oscillator pins see Section 14 2 Vi XTAL1 input voltage on pin 0 5 1 8 1 95 V XTAL1 Vo XTAL2 output voltage on pin 0 5 1 8 1 95 V XTAL2 Vi RTCX1 input voltage on pin 0 5 3 6 V RTCX1 Vo RTCX2 output voltage on pin 0 5 3 6 V RTCX2 1 Typical ratings are not guaranteed The values listed are at room temperature 25 nominal supply voltages 2 For USB operation 3 0 V lt Vpp ava lt 3 6 V Guaranteed by design 3 and VREFP should be tied to Vpp ava if the ADC and DAC are not used 4 RTC typically fails when Vitygar drops below 1 6 V 5 VppREq 3v3 9 3 V Tamb 25 C for all power consumption measurements 6 Boost control bits in the PBOOST register set to 0x0 see LPC178x 7x User manual UM10470 7 Boost control bits in the PBOOST register set to 0 3 see LPC178x 7x User manual UM10470 8 IRC running at 12 MHz main oscillator and PLL disabled POLK CCLK 4 9 BOD disa
43. a Quadrature Encoder Interface four general purpose timers two general purpose PWMs with six outputs each and one motor control PWM an ultra low power RTC with separate battery supply and event recorder a windowed watchdog timer a CRC calculation engine up to 165 general purpose I O pins and more The analog peripherals include one eight channel 12 bit ADC and a 10 bit DAC The pinout of LPC178x 7x is intended to allow pin function compatibility with the LPC24xx and LPC23xx For additional documentation see Section 18 References 2 Features and benefits W Functional replacement for the LPC23xx and LPC24xx family devices System ARM Cortex M3 processor running at frequencies of up to 120 MHz A Memory Protection Unit MPU supporting eight regions is included ARM built in Nested Vectored Interrupt Controller NVIC NXP Semiconductors LPC178x 7x LPC178X 7X 32 bit ARM Cortex M3 microcontroller Multilayer AHB matrix interconnect provides a separate bus for each AHB master AHB masters include the CPU USB Ethernet and the General Purpose DMA controller This interconnect provides communication with no arbitration delays unless two masters attempt to access the same slave at the same time Split APB bus allows for higher throughput with fewer stalls between the CPU and DMA A single level of write buffering allows the CPU to continue without waiting for completion of APB writ
44. and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third party customer s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Limiting values Stress above one or more limiting values as defined in the Absolute Maximum Ratings System of IEC 60134 will cause permanent damage to the device Limiting values are stress ratings only and proper operation of the device at these or any other conditions above those given in the Recommended operating conditions section if present or the Characteristics sections of this document is not warranted Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale as published at http www nxp com profile terms unless otherwise agreed in a valid written individual a
45. and then it wakes up the CPU The WIC eliminates the need to periodically wake up the CPU and poll the interrupts resulting in additional power savings Peripheral power control A power control for peripherals feature allows individual peripherals to be turned off if they are not needed in the application resulting in additional power savings Power domains The LPC178x 7x provide two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the backup registers On the LPC178x 7x I O pads are powered by Vpp ava while Vpp REy ava powers the on chip voltage regulator which in turn provides power to the CPU and most of the peripherals Depending on the LPC178x 7x application a design can use two power options to manage power consumption All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 65 of 123 NXP Semiconductors LPC178x 7x LPC178X 7X 32 bit ARM Cortex M3 microcontroller The first option assumes that power consumption is not a concern and the design ties the Vpp ava Vpp nEg 3va Pins together This approach requires only one 3 3 V power supply for both pads the CPU and peripherals While this solution is simple it does not support powering down the pad ring the fly while keeping the CPU and peri
46. channel General Purpose DMA controller GPDMA on the AHB multilayer matrix that can be used with the SSP 125 UART CRC engine Analog to Digital and Digital to Analog converter peripherals timer match signals GPIO and for memory to memory transfers Serial interfaces Ethernet MAC with MII RMII interface and associated DMA controller These functions reside on an independent AHB USB 2 0 full speed dual port device host OTG controller with on chip PHY and associated DMA controller Five UARTS with fractional baud rate generation internal FIFO DMA support and RS 485 EIA 485 support One UART UART1 has full modem control I O and one UART USARTA supports IrDA synchronous mode and a smart card mode conforming to 1507816 3 Three SSP controllers with FIFO and multi protocol capabilities The SSP controllers can be used with the GPDMA All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 2 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Three enhanced C bus interfaces one with a true open drain output supporting the full 2 specification and Fast mode Plus with data rates of 1 Mbit s two with standard port pins Enhancements include multiple address recognition and monitor mode I S bus Inter IC Sound interface for digital audio input or
47. data sheet Rev 5 3 16 October 2015 100 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller USB_D 1 USB_UP_LED1 Vpp Vssio VSSCORE USB A connector USB PWRD1 USB OVRCR1 USB PPWR1 LM3526 L LPC178x 7x USB PPWR2 USB OVRCR2 USB PWRD2 VBus USB_D 2 330 D USB A connector USB D 2 330 D 15kQ 15 0 Vssio VSSCORE VDD USB_UP_LED2 d 002aag508 Fig 34 USB host port configuration port 1 and port 2 as hosts LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 101 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller USB UP LED1 USB D 1 USB A connector USB PWRD1 USB OVRCR1 USB PPWR1 LPC178x 7x USB UP LED2 L Vpp USB CONNECT2 A Vssio VSSCORE USB_D 2 330 D bd USB B 330 USB D2 D connector VBUS VBus 002aag509 Fig 35 USB device port configuration port 1 host and port 2 device 14 2 Crystal oscillator XTAL in
48. master or slave mode Capable of handling 8 bit 16 bit and 32 bit word sizes Mono and stereo audio data supported The sampling frequency can range from 16 kHz to 48 kHz 16 22 05 32 44 1 48 kHz Configurable word select period in master mode separately for 125 input and output Two 8 word FIFO data buffers are provided one for transmit and one for receive Generates interrupt requests when buffer levels cross a programmable boundary Two DMA requests controlled by programmable buffer levels These are connected to the GPDMA block Controls include reset stop and mute options separately for 126 input and 125 output CAN controller and acceptance filters The LPC178x 7x contain one CAN controller with two channels The Controller Area Network CAN is a serial communications protocol which efficiently supports distributed real time control with a very high level of security Its domain of application ranges from high speed networks to low cost multiplex wiring The CAN block is intended to support multiple CAN buses simultaneously allowing the device to be used as a gateway switch or router between two of CAN buses in industrial or automotive applications Each CAN controller has a register structure similar to the NXP SJA1000 and the PeliCAN Library block but the 8 bit registers of those devices have been combined in 32 bit words to allow simultaneous access in the ARM environment The main operational dif
49. masters and slaves Multi master bus no central master Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allows devices with different bit rates to communicate via one serial bus Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer The 2 can be used for test and diagnostic purposes Both I C bus controllers support multiple address recognition and a bus monitor mode All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 54 of 123 NXP Semiconductors LPC178x 7x 7 23 7 23 1 7 24 7 24 1 LPC178X 7X 32 bit ARM Cortex M3 microcontroller 126 serial I O controllers The LPC178x 7x contain one 125 interface The 125 provides a standard communication interface for digital audio applications The I S bus specification defines a 3 wire serial bus using one data line one clock line and one word select signal The basic 125 connection has one master which is always the master and one slave The 12 interface on the LPC178x 7x provides a separate transmit and receive channel each of which can operate as either a master or a slave Features The interface has separate input output channels each of which can operate in
50. not available EMC OE EMC WE LPC178X 7X All information provided in this document is subject to legal disclaimers Rev 5 3 16 October 2015 NXP Semiconductors N V 2015 All rights reserved 45 of 123 Product data sheet NXP Semiconductors LPC178x 7x 7 10 1 7 11 LPC178X 7X 32 bit ARM Cortex M3 microcontroller The LPC178x 7x EMC is an ARM PrimeCell MultiPort Memory Controller peripheral offering support for asynchronous static memory devices such as RAM ROM and flash In addition it can be used as an interface with off chip memory mapped devices and peripherals The EMC is an Advanced Microcontroller Bus Architecture AMBA compliant peripheral See Table 6 for EMC memory access Features Dynamic memory interface support including single data rate SDRAM Asynchronous static memory device support including RAM ROM and flash with or without asynchronous page mode Low transaction latency Read and write buffers to reduce latency and to improve performance 8 16 32 data and 16 20 26 address lines wide static memory support 16 bit and 32 bit wide chip select SDRAM memory support Static memory features include Asynchronous page mode read Programmable Wait States Bus turnaround delay Output enable and write enable delays Extended wait Four chip selects for synchronous memory and four chip selects for static memory devices e Po
51. nxp com Date of release 16 October 2015 Document identifier LPC178X 7X
52. reconfigured accordingly Power down mode Power down mode does everything that Deep sleep mode does but also turns off the power to the IRC oscillator and the flash memory This saves more power but requires waiting for resumption of flash operation before execution of code or data access in the flash memory can be accomplished When the chip enters Power down mode the IRC the main oscillator and all clocks are stopped The RTC remains running if it has been enabled and RTC interrupts may be used to wake up the CPU The flash is forced into Power down mode The PLLs are automatically turned off and the clock selection multiplexers are set to use the system clock sysclk the reset state The clock divider control registers are automatically reset to zero If the Watchdog timer is running it will continue running in Power down mode All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 64 of 123 NXP Semiconductors LPC178x 7x 7 33 4 4 7 33 4 5 7 33 5 7 33 6 LPC178X 7X 32 bit ARM Cortex M3 microcontroller On the wake up of Power down mode if the IRC was used before entering Power down mode it will take IRC 60 ps to start up After this four IRC cycles will expire before the code execution can then be resumed if the code was running from SRAM In the meantime the flash wake up timer then coun
53. to data in 10 transmission and the acknowledge A Fast mode I C bus device can be used in a Standard mode I2C bus system but the requirement tsu DaT 250 ns must then be met This will automatically be the case if the device does not stretch the LOW period of the SCL signal If such a device does stretch the LOW period of the SCL signal it must output the next data bit to the SDA line tymax 15 1000 250 1250 ns according to the Standard mode I2C bus specification before the SCL line is released Also the acknowledge timing must meet this set up time All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 90 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller SDA SCL S 1 fscL tsu DAT 70 tHD DAT Fig 23 I C bus pins clock timing 002aa 425 11 8 l S bus interface Table 26 Dynamic characteristics I2S bus interface pins C 10 pF Tamb 40 to 85 C 3 0 V to 3 6 V Values guaranteed by design Symbol Parameter Conditions Min Max Unit common to input and output t rise time 6 7 ns tr fall time l 8 0 ns twn pulse width HIGH pins 12S TX and 1 25 l28 RX SCK tw pulse width LOW pins 25 TX SCKand HU 25 ns l28 RX SCK output
54. with TTL levels and hysteresis This pad can be powered by VBAT 5 V tolerant pad 5 V tolerant if Vpp ava present if Vpp ava not present or configured for an analog function do not exceed 3 6 V providing digital I O functions with TTL levels and hysteresis and analog input When configured as a ADC input digital section of the pad is disabled 5 V tolerant fast pad 5 V tolerant if Vpp sva present if Vpp ava not present do not exceed 3 6 V providing digital I O functions with TTL levels and hysteresis 5 V tolerant pad 5 V tolerant if Vpp ava present if not present or configured for an analog function do not exceed 3 6 V providing digital I O with TTL levels and hysteresis and analog output function When configured as the DAC output digital section of the pad is disabled Open drain 5 V tolerant digital I O pad compatible with I2C bus 400 kHz specification It requires an external pull up to provide output functionality When power is switched off this pin connected to the I2C bus is floating and does not disturb the 12C lines Open drain configuration applies to all functions on this pin Not 5 V tolerant Pad provides digital and USB functions It is designed in accordance with the USB specification revision 2 0 Full speed and Low speed mode only 5 V tolerant pad 5 V tolerant if Vpp ava present if Vpp ava not present do not exceed 3 6 V with 5 ns glitch filter providing digital I O functions wit
55. 0 0 4008 8000 0 4008 0000 SRAM bit band alias address 0x4001 8000 X It band alias addressin 5 e 02200 0000 0x4001 4000 0x4001 0000 0x4000 C000 timer 1 0x4000 8000 timer 0 0x4000 4000 0x4000 0000 N reserved 2 0x200A 0000 AHB peripherals lt 052008 0000 M reserved E 7 0x2000 8000 7 1 16 kB peripheral 1 1 0x2000 4000 16 kB peripheral SRAMO 0 5 0 2000 0000 reserved gt ox1FFF 2000 8 kB boot ROM Ox1FFF 0000 Up reserved 2 0 1001 0000 code D code 64 kB main static RAM 1 memory space 0x1000 0000 0x200A 0000 0x2009 C000 0x2009 8000 0x2009 4000 0x2009 0000 0x2008 C000 reserved 2 0 0008 0000 0 0000 0400 256 words 0x2008 8000 tive interrupt vect chi 1 0x0000 0000 512 kB on chip flash 0x2008 4000 0 GB 0x0000 0000 0x2008 0000 002aaf574 1 Not available on all parts See Table 2 and Table 6 Fig 6 LPC178x 7x memory pamasa SUSU S LOZ AN SIojonpuoorues dXN EZL 40 t 40 9npuooliul9S dXN X X87 241 19 041u050491UI JJ X91102 WHV 14 26 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller 7 8 Nested Vectored Interrupt Controller NVIC The NVIC is an integral part of the Cortex M3 The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts 7 8 4 Features Controls system exceptions a
56. 14 Fig 42 TFBGA208 package LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 108 of 123 NXP Semiconductors LPC178x 7x TFBGA1890 thin fine pitch ball grid array package 180 balls 32 bit ARM Cortex M3 microcontroller SOT570 3 lt D B A ball A1 index area DA E A 2 Y detail X Y 1 gt amp OvMICIAB gt j e gt 4 1 26 b gt wO P i M OOOOOOOOOOO L J OOOOO a OO OO B OOOOOOOOOOOO Y ball A1 1 3 5 7 9 _ 1 index area 2 75 43 228 10 5 10 mm scale DIMENSIONS mm are the original dimensions UNIT A A4 A2 b D E e 2 w y y max 1 20 0 40 0 80 0 50 12 1 12 1 mm nom 1 06 0 35 0 71 0 45 12 0 12 0 0
57. 17 PO 22 Row P 1 P1 31 2 P1 30 3 P2 27 4 P2 28 5 P2 24 6 Vpp av3 7 P1 18 8 Vpp av3 9 P1 23 10 VSSREG 11 VDD REG 3V3 12 Vss 13 P2 15 14 4 17 15 4 18 16 4 19 17 Vpp ava Row R 1 PO 12 2 PO 13 3 PO 28 4 P2 25 5 P3 24 6 PO 30 7 P2 19 8 P1 21 9 Vss 10 1 26 11 2 16 12 P2 14 13 P2 17 14 11 15 P4 4 16 P4 5 17 P4 20 E Row T 1 27 31 P3 26 4 P2 26 5 Vss P3 23 PO 14 8 P2 20 9 P1 24 10 1 25 11 4 2 12 P1 27 LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 37 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Table 4 Pin allocation table TFBGA208 Not all functions are available on all parts See Table 2 and Table 7 EMC pins Symbol Ball Symbol Ball Symbol Ball Symbol 13 P1 28 14 PO 1 15 PO 10 16 2 13 17 P2 11 Row U 1 USB D 2 2 P3 25 3 P2 18 4 PO 29 5 P2 23 6 P1 19 7 P1 20 8 P1 22 9 P40 10 11 P2 21 12 P2 22 13 Vpp ava 14 1 29 15 PO 0 16 P4 3 17 P4 16 Table 5 Pin allocation table TFBGA180 Not all funct
58. 2 2 VA 1 101 I i CEE L D2 8x _ D1 gt lt gt Generic footprint pattern Refer to the package outline drawing for actual layout solder land Occupied area DIMENSIONS in mm P1 P2 Ax Ay Bx By D1 D2 Gx Gy Hx Hy 0 500 0 560 23 300 23 300 20 300 20 300 1 500 0 280 0 400 20 500 20 500 23 550 23 550 Fig 47 Reflow soldering of the LQFP144 package LPC178X_7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 113 of 123 NXP Semiconductors LPC178x 7x 17 Abbreviations 32 bit ARM Cortex M3 microcontroller Table 34 Abbreviations Acronym Description ADC Analog to Digital Converter AHB Advanced High performance Bus AMBA Advanced Microcontroller Bus Architecture APB Advanced Peripheral Bus BOD BrownOut Detection CAN Controller Area Network DAC Digital to Analog Converter DMA Direct Memory Access EOP End Of Packet ETM Embedded Trace Macrocell GPIO General Purpose Input Output GPS Global Positioning System HVAC Heating Venting and Air Conditioning IRC Internal RC IrDA Infrared Data Association JTAG Joint Test Action Group MAC Media Access Control MIIM Media
59. 2 pad T2_CAPO Capture input for Timer 2 channel 0 P2 15 99 Bu 2 15 General purpose digital input output pin PU Jo EMC CS3 LOW active Chip Select 3 signal 2 SCL 12 1 clock input output this pin does not use specialized 2 pad T2_CAP1 Capture input for Timer 2 channel 1 P2 16 87 11 P9 P2 16 General purpose digital input output pin PU EMC CAS LOW active SDRAM Column Address Strobe P2 17 95 R13 P11 P2 17 General purpose digital input output pin PU RAS LOW active SDRAM Row Address Strobe P2 18 59 6 P2 18 General purpose digital input output pin PU CLK 0 SDRAM clock 0 P2 19 67 7 5 l6 P2 19 General purpose digital input output pin PU CLK 1 SDRAM clock 1 P2 20 73 8 P6 l lO P2 20 General purpose digital input output pin PU DYCS0 SDRAM chip select 0 P2 21 81 Uli N8 lO P2 21 General purpose digital input output pin PU DYCS1 SDRAM chip select 1 P2 22 85 U12 lO P2 22 General purpose digital input output pin PU EMC DYCS2 SDRAM chip select 2 lO SSPO SCK Serial clock for SSPO
60. 2 4 or 8 bpp palettized color displays for color STN and TFT 16 bpp true color non palettized for color STN and TFT 24 bpp true color non palettized for color TFT Programmable timing for different display panels 256 entry 16 bit palette RAM arranged as 128 x 32 bit RAM Frame line and pixel clock signals AC bias signal for STN data enable signal for TFT panels Supports little and big endian and Windows CE data formats LCD panel clock may be generated from the peripheral clock or from a clock input pin All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 48 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller 7 14 Ethernet Remark The Ethernet block is available on parts LPC1788 86 and LPC1778 76 The Ethernet block contains a full featured 10 Mbit s or 100 Mbit s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration Features include a generous suite of control registers half or full duplex operation flow control control frames hardware acceleration for transmit retry receive packet filtering and wake up on LAN activity Automatic frame transmission and reception with scatter gather DMA off loads many operations from the CPU The Ethernet block and the CPU share the ARM Cortex M3 D code
61. 3 0 5 P1 1 6 Vss 7 P4 30 8 4 24 9 P4 25 10 P4 29 11 P1 6 12 PO 4 13 Vpp ava 14 P3 19 15 4 14 16 P4 13 17 2 0 Row LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 35 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Table 4 Pin allocation table TFBGA208 Not all functions are available on all parts See Table 2 and Table 7 EMC pins Ball Symbol Ball Symbol Ball Symbol Symbol 1 P3 13 2 JTAG_TDI 3 P5 4 4 PO 2 5 P3 9 6 P3 22 7 P1 8 8 P1 10 9 Vpp 3va 10 3 21 11 P4 28 12 PO 5 13 PO 7 14 PO 9 15 P3 18 16 P4 12 17 Vopb ava Row D 1 JTAG TRST 2 P3 28 3 JTAG TDO SWO 4 P3 12 5 P3 11 6 PO 3 7 Vpp 3v3 8 P3 8 9 P1 2 10 1 16 11 Vpp REG 3V3 12 VSSREG 13 PO 6 14 P1 7 15 P2 2 16 P1 13 17 P2 4 Row E 1 PO 26 2 JTAG_TCK 3 JTAG TMS SWDIO 4 P3 3 SWDCLK 5 6 7 8 9 10 11 12 l 13 14 P2 1 15 16 2 3 17 2 6 Row 1 PO 25 2 P3 4 3 P3 29 4 P5 0 5 6 7 8 9 10 11 12 l 13 14 1 15 P3 17 16 P2 5 17 P3 16 Row G 1 P3 5 2 PO 24 3 Vp
62. 32 165 Y Y LPC1776FBD208 LPC1776FBD208 551 256 64 16 80 4032 Y 5 32 165 Y Y LPC1776FET180 1776 180 551 256 64 16 80 4032 Y 5 16 141 Y Y LPC1774FBD208 LPC1774FBD208 551 128 32 8 40 2048 N D 5 32 165N N N LPC1774FBD144 LPC1774FBD144 551 128 32 8 40 2048 N D 4121 8 109 IN N 1 Maximum data bus width of the External Memory Controller EMC depends on package size Smaller widths may be used 2 USARTA not available LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 6 of 123 LPC178x 7x 32 bit ARM Cortex M3 microcontroller NXP Semiconductors 5 Block diagram JTAG interface TEST DEBUG INTERFACE debug LPC178x 7x CLOCK GENERATION POWER CONTROL SYSTEM FUNCTIONS USB DEVICE HOST OTG 1 ARM CORTEX M3 GPDMA 1 CONTROLLER ETHERNET EMULATION TRACE MODULE clocks and controls D code master master bus l code bus system bus MULTILAYER AHB MATRIX SRAM 96 80 40 kB slave AHB TO AHB TO 4032 B GPIO APB slave group 0 9m m 19 k gt ssomrenuer 32 kHz OSCILLATOR BACKUP REGISTERS RTC POWER DOMAIN APB BRIDGE 0 FLASH ACCELERATOR 2046 B FLASH EEPROM 512 256 128 64 kB APB slave group 1
63. 50 ns on this resets the device causing I O ports and peripherals to take on their default states and processor execution to begin at address 0 This pin also serves as the debug select input LOW level selects the JTAG boundary scan HIGH level selects the ARM SWD debug mode RSTOUT 29 H2 20 BI OH Reset status output A LOW output this indicates that the device is in the reset state for any reason This reflects the RESET input pin and all internal reset sources ALARM 37 N1 H5 26 OL O RTC controlled output This pin has a low drive strength and is powered by VBAT It is driven HIGH when an alarm is generated RTOX1 34 K2 02 23 14 Input to the RTC 32 kHz ultra low power oscillator circuit 15 RTCX2 36 12 25 14 Output from the RTC 32 kHz ultra low power oscillator circuit 15 USB D 2 52 N2 37 B lO USB port 2 bidirectional D line LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 33 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Table 3 description continued Not all functions are available on all parts See Table 2 Ethernet USB LCD QEI SD MMC DAC pins and Table 7 EMC pins co e Sym
64. 7 11 1 7 12 7 12 1 7 13 7 13 1 7 14 7 14 1 7 15 7 15 1 7 15 1 1 7 15 2 7 15 2 1 7 15 8 7 15 3 1 7 16 7 16 1 7 17 7 17 1 7 18 7 18 1 7 19 7 19 1 7 20 7 20 1 LPC178X 7X General 1 Features and benefits 1 4 Ordering 5 Block diagram 7 Pinning 8 PINNING ce ede x mI bees 8 Pin description 9 Functional description 40 Architectural overview 40 ARM Cortex M3 41 On chip flash program memory 41 EEPROM RD RR RR ERR 41 On chip 41 Memory Protection Unit 41 Memory 42 Nested Vectored Interrupt Controller NVIC 44 EGatUres ie 44 Interrupt 44 Pin connect block 44 External memory controller 44 Features or RE LEAL I LS 46 General purpose DMA controller 46 47 CRC engine 47 2 2242 2 PRICES 47 LCD 48 Eeat res S pe 48 Etlietriel iue e Gud 49 F
65. 8 10 4 10 4 0 15 0 05 0 12 0 1 min 0 95 0 30 0 65 0 40 11 9 11 9 OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC JEITA PROJECTION ISSUE DATE 08 07 09 SOT570 3 cto 4 Fig 43 TFBGA180 package LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 109 of 123 NXP Semiconductors LPC178x 7x LQFP144 plastic low profile quad flat package 144 leads body 20 x 20 x 1 4 mm 32 bit ARM Cortex M3 microcontroller SOT486 1 22 1 DIMENSIONS mm the original dimensions detail X UNIT Ai Ao bp c 1 45 1 35 Note 1 Plastic or me al protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC JEITA PROJECTION ISSUE DATE SOT486 1 136E23 MS 026 EQ on Fig 44 LQFP144 package LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev
66. 8x 7x 32 bit ARM Cortex M3 microcontroller EMC_Ax EMC_CSx EMC_OE EMC_BLSx EMC_WE RD5 RD5 gt aR RD WR2 WRe RDs 6 Dx EOR EOW 002aag215 Fig 17 External static memory read write access PB 1 EMC Ax 5 BLSx WE Dx 002aag216 Fig 18 External static memory burst read cycle LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 83 of 123 NXP Semiconductors LPC178x 7x Table 18 32 bit ARM Cortex M3 microcontroller 30 pF Tamb 40 C to 85 C Vpp sya 3 0 V to 3 6 V Values guaranteed by design Dynamic characteristics Dynamic external memory interface read strategy bits RD bits 00 Symbol Parameter Min Typ Max Unit Common to read and write cycles clock cycle time 12 5 ns ta sv chip select valid delay time CLKDLY 1 x CLKDLY 1 x CLKDLY 1 x ns 0 25 4 1 0 25 5 7 0 25 8 4 this chip select hold time CLKDLY 1 x CLKDLY 1 x CLKDLY 1 x ns 0 25 0 5 0 25 1 1 0 25 2 7 ta RASV row address strobe valid delay LI CLKDLY 1 x CLKDLY 1 x CLKDLY 1 x ns time 0 25
67. All information provided in this document is subject to legal disclaimers Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors and its suppliers accept no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or customer product design It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design
68. B transceiver PO 29 61 U4 K5 42 PO 29 General purpose digital input output pin USB D 1 USB port 1 bidirectional D line EINTO External interrupt O input PO 30 62 R6 N4 43 lO PO 30 General purpose digital input output pin USB D 1 USB port 1 bidirectional D line EINT1 External interrupt 1 input PO 31 51 T2 36 R lO PO 31 General purpose digital input output pin USB D 2 USB port 2 bidirectional D line P1 0 to 1 Port 1 is a 32 bit I O port with individual direction P1 31 controls for each bit The operation of port 1 pins depends upon the pin function selected via the pin connect block P1 0 196 5 136 BI P1 0 General purpose digital input output pin PU NET TXD0 Ethernet transmit data 0 RMII MII interface R Function reserved T8 CAP1 Capture input for Timer channel 1 lO SSP2 SCK Serial clock for SSP2 LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 15 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Table3 Pin description continued Not all functions are available on all parts See Table 2 Ethernet USB LC
69. CD QEI SD MMC DAC pins and Table 7 EMC pins Symbol 8 9 Description x x 2 S a 7 zoER l 5 5 9 g m a A PO 25 14 Fi E4 10 BI ii lO PO 25 General purpose digital input output pin ADCO IN 2 A D converter 0 input 2 When configured as an ADC input the digital function of the pin must be disabled lO 125 SDA Receive data It is driven by the transmitter and read by the receiver Corresponds to the signal SD in the specification U3 TXD Transmitter output for PO 26 12 Ei Di 8 1 PO 26 General purpose digital input output pin PU ADCO IN 3 A D converter 0 input 3 When configured as an ADC input the digital function of the pin must be disabled DAC OUT D A converter output When configured as the DAC output the digital function of the pin must be disabled RXD Receiver input for UART3 PO 27 50 11 L3 35 B 271 General purpose digital input output pin lO 12 0 SDA 12 0 data input output this pin uses a specialized I2C pad lO USB SDA1 I2C serial data for communication with an external USB transceiver PO 28 48 R3 1 34 lO PO 28 General purpose digital input output pin 12 0 SCL 1260 clock input output this pin uses specialized 2 pad lO USB SCL1 12 serial clock for communication with an external US
70. CTS Clear to Send input for UART1 T2 MATS Match output for Timer 2 channel 3 R Function reserved 3 Trace data bit R Function reserved LCD DCLK LCD panel clock P2 3 144 E16 E13 100 BI I P2 3 General purpose digital input output pin PU Jo PWM1 4 Pulse Width Modulator 1 channel 4 output U1 DCD Data Carrier Detect input for UART1 T2 2 Match output for Timer 2 channel 2 R Function reserved TRACEDATA 2 Trace data bit 2 R Function reserved LCD FP Frame pulse STN Vertical synchronization pulse TFT P2 4 142 017 E14 99 BI P2 4 General purpose digital input output pin PU PWM1 5 Pulse Width Modulator 1 channel 5 output 01 DSR Data Set Ready input for UART1 T2 MAT1 Match output for Timer 2 channel 1 R Function reserved TRACEDATA 1 Trace data bit 1 R Function reserved LCD ENAB M STN AC bias drive TFT data enable output LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 22 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Table 3
71. D Transmitter output for USARTA input output in smart card mode CAN TD1 CAN1 transmitter output PO 23 18 1 F5 13 lO PO 23 General purpose digital input output pin PU ADCO IN 0 A D converter 0 input 0 When configured as ADC input the digital function of the pin must be disabled 125 RX SCK Receive Clock It is driven by the master and received by the slave Corresponds to the signal SCK in the S bus specification Capture input for Timer channel 0 PO 24 16 92 El 11 19 lO PO 24 General purpose digital input output pin PU ADCO IN 1 A D converter 0 input 1 When configured as an ADC input the digital function of the pin must be disabled lO 125 WS Receive Word Select It is driven by the master and received by the slave Corresponds to the signal WS in the PS bus specification T8 1 Capture input for Timer 3 channel 1 LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 14 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Table 3 description continued Not all functions are available on all parts See Table 2 Ethernet USB L
72. D 0 SD DATn 0 tsu D th D SD CMD SD DATn I 002aag204 Fig 27 SD MMC timing All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 93 of 123 NXP Semiconductors LPC178x 7x 12 ADC electrical characteristics 32 bit ARM Cortex M3 microcontroller LPC178X_7X Table 29 12 bit ADC characteristics Vppa 2 7 V to 3 6 V Tamb 40 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit ViA analog input voltage 0 VppA V 12 bit resolution Ep differential linearity 1211314 1 LSB error EL adj integral non linearity 6 LSB Eo offset error 216 5 LSB Ec gain error 2107 5 LSB absolute error 218 lt 8 LSB fakApc ADC clock frequency 12 4 MHz c ADC ADC conversion single conversion 400 kSa frequency mode mple s s burst mode 375 kSa mple s s Cia analog input 5 capacitance Rysi voltage source 9 1 interface resistance 8 bit resolution 0 Ep differential linearity T2314 1 LSB error integral non linearity 215 LSB Eo offset error 216 1 LSB gain error 2107 1 LSB ET absolute error 2118 lt 1 5 LSB fdkApc ADC clock
73. D QEI SD MMC DAC pins and Table 7 EMC pins Symbol e Description o A E a a O T 5 a r7 E l le zoER l 5 5 E o g ao m e a P1 1 194 A5 135 BI P1 1 General purpose digital input output pin U ENET TXD1 Ethernet transmit data 1 RMII MII interface R Function reserved O T3_MAT3 Match output for Timer 3 channel 3 lO 55 2 MOSI Master Out Slave In for SSP2 P1 2 185 D9 B7 Bu P1 2 General purpose digital input output pin PU TXD2 Ethernet transmit data 2 MII interface SD CLK Clock output line for SD card interface PWMO 1 Pulse Width Modulator 0 output 1 P1 3 177 10 9 BI P1 3 General purpose digital input output pin PU TXD3 Ethernet transmit data 3 MII interface lO SD CMD Command line for SD card interface PWMO 2 Pulse Width Modulator 0 output 2 P1 4 192 C6 133 BI 1 4 General purpose digital input output pin PU TX EN Ethernet transmit data enable RMII MII interface Function reserved T3 MAT2 Match output for Timer channel 2 lO 55 2 MISO Master In Slave Out for SSP2 P1 5 156 17 B13 P1 5 General purpose digital input output pin PU Jo ENET TX ER Ethernet Transmit Error MII interface SD PWR Power Supply Enable for exte
74. DAC The LPC178x 7x contain one DAC The DAC allows to generate a variable analog output The maximum output value of the DAC is VREFP LPC178X_7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 52 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller 7 19 1 Features 10 bit DAC Resistor string architecture Buffered output Power down mode Selectable output drive Dedicated conversion timer DMA support 7 20 UARTs Remark USART4 is not available on part LPC1774FBD144 The LPC178x 7x contain five UARTs In addition to standard transmit and receive data lines UART1 also provides a full modem control handshake interface and support for RS 485 9 bit mode allowing both software address detection and automatic address detection using 9 bit mode The UARTS include a fractional baud rate generator Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz 7 20 1 Features Maximum UART data bit rate of 7 5 MBit s 16 B Receive and Transmit FIFOs Register locations conform to 16C550 industry standard Receiver FIFO trigger points at 1 B 4 B 8 B and 14 B Built in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values Auto baud capability Fractional divide
75. DMA error and DMA count raw interrupt status can be read prior to masking 7 12 CRC engine The Cyclic Redundancy Check CRC generator with programmable polynomial settings supports several CRC standards commonly used To save system power and bus bandwidth the CRC engine supports DMA transfers 7 12 1 Features LPC178X 7X Supports three common polynomials CRC CCITT CRC 16 and CRC 32 CRC CCITT x 6 x12 5 1 CRC 16 x16 15 2 1 32 3 25 23 2 2 0 8 1 Bit order reverse 1 s complement programmable setting for input data sum Programmable seed number setting Supports CPU PIO or DMA back to back transfer All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 47 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Accept any size of data width per write 8 16 or 32 bit 8 bit write 1 cycle operation 16 bit write 2 cycle operation 8 bit x 2 cycle 32 bit write 4 cycle operation 8 bit x 4 cycle 7 13 LCD controller Remark The LCD controller is available on parts LPC1788 87 86 85 The LCD controller provides all of the necessary control signals to interface directly to a variety of color and monochrome LCD panels Both STN single and dual
76. EG 32 D12 H3 22 G Ground 0 V reference for internal logic 84 4 18 59 172 10 10 119 Vssa 22 2 15 G Analog ground 0 V power supply and reference for the ADC and DAC This should be the same voltage as Vss but should be isolated to minimize noise and error XTAL1 44 M4 12 31 14 Input to the oscillator circuit and internal clock generator circuits 16 XTAL2 46 N4 K4 33 Output from the oscillator amplifier 16 LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 34 of 123 NXP Semiconductors LPC178x 7x 6 7 8 9 10 11 12 13 14 15 16 32 bit ARM Cortex M3 microcontroller PU internal pull up enabled for Vpp Req 3v3 3 3 V pulled up to 3 3 V IA inactive no pull up down enabled F floating floating pins if not used should be tied to ground or power to minimize power consumption Input O Output OL Output driving LOW G Ground S Supply 5 V tolerant pad 5 V tolerant if Vpp sva present if Vpp svs not present do not exceed 3 6 V providing digital I O functions with TTL levels and hysteresis 5 V tolerant standard pad 5 V tolerant if Vpp ava present if Vpp aya not present do not exceed 3 6 V providing digital I O functions
77. General purpose digital input output pin PU Tio EMC_A 18 External memory address line 18 LPC178X_7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 30 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Table 3 description continued Not all functions are available on all parts See Table 2 Ethernet USB LCD QEI SD MMC DAC pins and Table 7 EMC pins Symbol 8 g Description 4q amp m8 E 8 S je E g 3 49 E a ia e 2 e P4 19 111 P16 14 lO P4 19 General purpose digital input output pin PU yo EMC A 19 External memory address line 19 P4 20 109 R17 lO PA 20 General purpose digital input output pin PU EMC A 20 External memory address line 20 lO I2C2 SDA 12 2 data input output this pin does not use a specialized 2 pad lO SSP1 SCK Serial Clock for SSP1 4 21 115 M15 lO 4 21 General purpose digital input output pin PU A 21 External memory address line 21 lO I2C2 SCL 12 2 clock input output this pin does not use
78. Hz 10 pF lt 3000 18 pF 18 pF 20 pF lt 200 Q 39 pF 39 pF 30 pF lt 1000 57 pF 57 pF 10 MHz to 15 MHz 10 pF 1600 18 pF 18 pF 20 pF 600 39 pF 39 pF 15 MHz to 20 MHz 10 pF 800 18 pF 18 pF Table 33 Recommended values for Cy4 Cyz in oscillation mode crystal and external components parameters high frequency mode Fundamental oscillation Crystal load Maximum crystal External load frequency Fosc capacitance C series resistance Rs capacitors Cx 15 MHz to 20 MHz 10 pF 1800 18 pF 18 pF 20 pF 1000 39 pF 39 pF 20 MHz to 25 MHz 10 pF lt 1600 18 pF 18 pF 20 pF lt 800 39 pF 39 pF 14 3 XTAL Printed Circuit Board PCB layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip Take care that the load capacitors 4 and in case of third overtone crystal usage have a common ground plane The external components must also be connected to the ground plane Loops must be made as small as possible in order to keep the noise coupled in via the PCB as small as possible Also parasitics should stay as small as possible Smaller values of C44 and should be chosen according to the increase in parasitics of the PCB layout 14 4 Standard pin configuration Figure 38 shows the possible pin modes for standard I O pins with analog input function Digital output driver Open drai
79. Independent Interface Management OHCI Open Host Controller Interface OTG On The Go PHY Physical Layer PLC Programmable Logic Controller PLL Phase Locked Loop PWM Pulse Width Modulator RMII Reduced Media Independent Interface SEO Single Ended Zero SPI Serial Peripheral Interface SSI Serial Synchronous Interface SSP Synchronous Serial Port TCM Tightly Coupled Memory TTL Transistor Transistor Logic UART Universal Asynchronous Receiver Transmitter USB Universal Serial Bus LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 114 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller 18 References 1 LPC178x 7x User manual UM10470 http Awww nxp com documents user_manual UM10470 pdf 2 LPC177x 8x Errata sheet http www nxp com documents errata sheet ES LPC177X 8X pdf 3 Technical note ADC design guidelines http www nxp com documents technical note TN00009 pdf LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 115 of 123 NXP Semiconductors LPC178x 7x 32 bi
80. LPC178x 7x 32 bit ARM Cortex M3 microcontroller 7 11 1 Features Eight DMA channels Each channel can support an unidirectional transfer 16 DMA request lines Single DMA and burst DMA request signals Each peripheral connected to the DMA Controller can assert either a burst DMA request or a single DMA request The DMA burst size is set by programming the DMA Controller Memory to memory memory to peripheral peripheral to memory and peripheral to peripheral transfers are supported Scatter or gather DMA is supported through the use of linked lists This means that the source and destination areas do not have to occupy contiguous areas of memory Hardware DMA channel priority AHB slave DMA programming interface The DMA Controller is programmed by writing to the DMA control registers over the AHB slave interface One AHB bus master for transferring data The interface transfers data when a DMA request goes active 32 bit AHB master bus width Incrementing or non incrementing addressing for source and destination Programmable DMA burst size The DMA burst size can be programmed to more efficiently transfer data Internal four word FIFO per channel Supports 8 16 and 32 bit wide transactions Big endian and little endian support The DMA Controller defaults to little endian mode on reset An interrupt to the processor can be generated on a DMA completion or when a DMA error has occurred Raw interrupt status The
81. LPC178x 7x 32 bit ARM Cortex M3 microcontroller up to 512 kB flash and 96 kB SRAM USB Device Host OTG Ethernet LCD EMC Rev 5 3 16 October 2015 Product data sheet Bus 2 1 General description The LPC178x 7x is an ARM Cortex M3 based microcontroller for embedded applications requiring a high level of integration and low power dissipation The ARM is a next generation core that offers better performance than the ARM7 at the same clock rate and other system enhancements such as modernized debug features and a higher level of support block integration The ARM Cortex M3 CPU incorporates a 3 stage pipeline and has a Harvard architecture with separate local instruction and data buses as well as a third bus with slightly lower performance for peripherals The ARM Cortex M3 CPU also includes an internal prefetch unit that supports speculative branches The LPC178x 7x adds a specialized flash memory accelerator to accomplish optimal performance when executing code from flash The LPC178x 7x operates at up to 120 MHz CPU frequency The peripheral complement of the LPC178x 7x includes up to 512 kB of flash program memory up to 96 kB of SRAM data memory up to 4032 byte of EEPROM data memory External Memory Controller EMC LCD LPC178x only Ethernet USB Device Host OTG a General Purpose DMA controller five UARTs three SSP controllers three 2 interfaces
82. M1 channel 1 TO MAT1 Match output for Timer 0 channel 1 MC 2B Motor control PWM channel 2 output B 04 TXD Transmitter output for USARTA input output in smart card mode LCD VD 15 LCD data LCD VD 23 LCD data P1 30 42 P2 30 P1 30 General purpose digital input output pin PU USB PWRD 2 Power Status for USB port 2 USB VBUS Monitors the presence of USB bus power This signal must be HIGH for USB reset to occur ADCO IN 4 A D converter 0 input 4 When configured as ADC input the digital function of the pin must be disabled lO I2CO0 SDA 12 0 data input output this pin does not use a specialized 2 pad 03 OE RS 485 EIA 485 output enable signal for P1 31 40 P1 K2 28 B 1 31 General purpose digital input output pin PU USB OVRCR2 Over Current status for USB port 2 lO SSP1 SCK Serial Clock for SSP1 ADCO IN 5 A D converter 0 input 5 When configured as an ADC input the digital function of the pin must be disabled lO 12 0 SCL 12 0 clock input output this pin does not use specialized 2 pad P2 0 to Port 2 Port 2 is a 32 bit I O port with individual direction P2 31 controls for each bit The operation of port 1 pins depends upon the pin function selected via the pin connect block P2 0 154 B17 D12 107 BI P2 0 General purpose digital input output pin PU
83. NXP Semiconductors LPC178x 7x Table 2 LPC178x 7x ordering options 32 bit ARM Cortex M3 microcontroller All parts include two CAN channels three SSP interfaces three interfaces one IS interface DAC and an 8 channel 12 bit ADC o ox 8 z 5 a 5 z o 2 8 2 9 2 0 o ge 21 Bg n2 9m ogo 88 9 5 solos LPC178x LPC1788FBD208 LPC1788FBD208 CPSE 512 64 16 x2 96 4032 Y 5 32 165 Y Y Y LPC1788FET208 LPC1788FET208 551 512 64 16 x2 96 4032 Y H O D 5 32 165 Y Y Y LPC1788FET180 1788 180 551 512 64 16 x2 96 4032 Y H O D 5 16 14 Y YY LPC1788FBD144 LPC1788FBD144 551 512 64 16 x2 96 4032 Y 5 8 109 Y Y Y LPC1787FBD208 LPC1787FBD208 551 512 64 16 x2 96 4032 5 32 165 Y Y Y LPC1786FBD208 LPC1786FBD208 551 256 64 16 80 4032 Y 5 32 4165 Y Y Y LPC1785FBD208 LPC1785FBD208K 256 64 16 80 4032 N H O D 5 32 165 Y Y LPC177x LPC1778FBD208 LPC1778FBD208 551 512 64 16 x2 96 4032 Y 5 32 165 N Y Y LPC1778FET208 1778 208 551 512 64 16 x2 96 4032 Y H O D 5 32 4165 N Y Y LPC1778FET180 1778 180 551 512 64 16x2 96 4032 Y H O D 5 16 141 N Y Y LPC1778FBD144 LPC1778FBD144 551 512 64 16x 2 96 4032 Y H O D 5 8 109 N Y Y LPC1777FBD208 LPC1777FBD208 551 512 64 16 x2 96 4032 5
84. O 11 Added function LCD VD 13 to pin PO 19 Added function LCD VD 14 to pin PO 20 Added function 04 SCLK to pin PO 21 Added function Added function MOSI to pin P5 0 Added function SSP2 MISO to pin 5 1 Added EMC dynamic characteristics LPC178X 7X v 1 20110524 Objective data sheet LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 119 of 123 NXP Semiconductors LPC178x 7x 20 Legal information 32 bit ARM Cortex M3 microcontroller 20 1 Data sheet status Document status 1l2 Product status Definition Objective short data sheet Development This document contains data from the objective specification for product development Preliminary short data sheet Qualification This document contains data from the preliminary specification Product short data sheet Production This document contains the product specification 1 Please consult the most recently issued document before initiating or completing a design 2 term short data sheet is explained in section Definitions 3 The product status of device s described in this document may have changed since this document was published and may differ in case of multiple devices The latest product status information is
85. October 2015 76 of 123 NXP Semiconductors LPC178x 7x LPC178X 7X 32 bit ARM Cortex M3 microcontroller Table 14 Power consumption for individual analog and digital blocks continued Tamb 25 C Vpb REG 3V3 Vpp ava VppA 3 3 V PCLK CCLKA Peripheral Conditions Typical supply current in mA 12 MHz 48 MHz 120 2 21 EMC 0 82 3 17 7 63 RTC 0 01 0 01 0 05 USB PLL1 0 62 0 97 1 67 Ethernet PCENET bit set 0 54 2 08 5 03 to 1 in the PCONP register 1 Boost control bits in the PBOOST register set to 0 0 see LPC178x 7x User manual UM10470 2 Boost control bits in the PBOOST register set to 0x3 see LPC178x 7x User manual UM10470 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 77 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller 10 3 Electrical pin characteristics LPC178X_7X 002aaf112 3 6 24 mA Conditions Vpp REG 3V3 Vpp ava 3 3 V standard port pins Fig 12 Typical HIGH level output voltage versus HIGH level output source current m 002aaf111 loL 85 mA 25 40 am 10 5 0 0 0 2 0 4 0 6 V Condition
86. PC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 31 of 123 NXP Semiconductors LPC178x 7x Table3 description continued 32 bit ARM Cortex M3 microcontroller Not all functions are available on all parts See Table 2 Ethernet USB LCD QEI SD MMC DAC pins and Table 7 EMC pins Symbol Description o a S lt o O O 5 a r7 ij e IN e Ju o s s o g m a a c P4 29 176 B10 B9 122 4 29 General purpose digital input output pin U lo BLS3 LOW active Byte Lane select signal 3 RXD Receiver input for UART3 T2 MAT1 Match output for Timer 2 channel 1 I2C2 SCL 12 2 clock input output this pin does not use specialized 2 pad LCD VD 7 LCD data LCD VD 11 LCD data LCD VD 3 LCD data P4 30 187 B7 C7 130 3 4 30 General purpose digital input output pin PU Jo CS0 LOW active Chip Select 0 signal P4 31 193 A4 E7 134 BI PA 31 General purpose digital input output pin PU 51 LOW active Chip Select 1 signal P5 0 to P5 4 5 Port 5 is a
87. Reset state 21 Pin LOFP208 TFBGA208 Ball TFBGA180 9 Pin LQFP144 P5 3 m AR band 4 0 P5 3 General purpose digital input output pin R Function reserved R Function reserved R Function reserved 04 RXD Receiver input for USART4 O 12 0 SCL 1260 clock input output this pin uses specialized I C pad that supports 2 Fast Mode Plus P5 4 206 C3 C4 143 BI P5 4 General purpose digital input output pin PU OE RS 485 EIA 485 output enable signal for UARTO R Function reserved T3_MAT3 Match output for Timer 3 channel 3 04 TXD Transmitter output for USART4 input output in smart card mode JTAG TDO 2 D3 B1 1 Bl Test Data Out for JTAG interface Also used as Serial wire trace SWO output JTAG TDI 4 C2 3 Bl Test Data In for JTAG interface PU JTAG TMS 6 2 4 BI Test Mode Select for JTAG interface Also used as Serial wire SWDIO PU debug data input output JTAG TRST 8 D1 D4 5 Bl Test Reset for JTAG interface PU JTAG TCK 10 E2 D2 7 B Test Clock for JTAG interface This clock must be slower than SWDCLK 1 6 of the CPU clock CCLK for the JTAG interface to operate Also used as serial wire clock RESET 35 2 24 External reset input with 20 ns glitch filter A LOW going pulse PU as short as
88. S CAS DYCS 3 0 CS 3 0 CLK 1 0 CKE 3 0 EMC OE EMC WE DQN 3 0 LPC1778FBD208 D 81 0 A 25 0 BLS 3 0 EMC RAS EMC CAS EMC DYCS 3 0 EMC CS 3 0 CLK 1 0 CKE 3 0 EMC OE EMC WE DQN 3 0 LPC1778FET208 EMC 0 31 0 A 25 0 EMC BLS 3 0 RAS CAS DYCS 3 0 EMC CS 3 0 CLK 1 0 CKE 3 0 EMC OE EMC WE DQN 3 0 LPC1778FET180 EMC D 15 0 EMC A 19 0 EMC BLS 1 0 RAS CAS DYCS 1 0 CS 1 0 CLK 1 0 CKE 1 0 EMC OE EMC WE EMC_DQM 1 0 LPC1778FBD144 D T7 0 EMC A 15 0 CS 1 0 not available EMC OE EMC WE LPC1777FBD208 0 31 0 A 25 0 BLS 3 0 RAS CAS DYCS 3 0 EMC CS 3 0 CLK 1 0 CKE 3 0 EMC OE EMC WE EMC DQN 3 0 LPC1776FBD208 EMC 0 31 0 A 25 0 EMC BLS 3 0 EMC RAS EMC CAS EMC DYCS 3 0 CS 3 0 CLK 1 0 CKE 3 0 EMC OE EMC WE EMC DQN 3 0 LPC1776FET180 EMC D 15 0 EMC A 19 0 EMC BLS 3 0 EMC RAS EMC CAS EMC DYCS 1 0 EMC CS 3 0 CLK 1 0 CKE 1 0 EMC OE EMC WE DQW 1 0 LPC1774FBD208 D 81 0 25 0 BLS 3 0 EMC RAS EMC CAS EMC DYCS 3 0 EMC CS 3 0 CLK 1 0 CKE 3 0 EMC OE EMC WE DQN 3 0 LPC1774FBD144 D T7 0 EMC A 15 0 CS 1 0
89. SB clock through that route The source for each clock must be selected via the CLKSEL registers and can be further reduced by clock dividers as needed PLLO accepts an input clock frequency from either the IRC or the main oscillator If only the Main PLL is used then its output frequency must be an integer multiple of all other clocks needed in the system PLL1 takes its input only from the main oscillator requiring an external crystal in the range of 10 to 25 MHz In each PLL the Current Controlled Oscillator CCO operates in the range of 156 MHz to 320 MHz so there are additional dividers to bring the output down to the desired frequencies The minimum output divider value is 2 insuring that the output of the PLLs have a 50 duty cycle If the USB is used the possibilities for the CPU clock and other clocks will be limited by the requirements that the frequency be precise and very low jitter and that the PLLO output must be a multiple of 48 MHz Even multiples of 48 MHz that are within the operating range of the PLL are 192 MHz and 288 MHz Also only the main oscillator in conjunction with the PLL can meet the precision and jitter specifications for USB It is due to these limitations that the Alternate PLL is provided All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 62 of 123 NXP Semiconductors LPC178x
90. SSEL Slave Select for SSP1 USB CONNECT SoftConnect control for USB port 2 Signal used to switch an external 1 5 resistor under software control Used with the SoftConnect USB feature PO 15 128 J16 H13 89 BI PO 15 General purpose digital input output pin PU Jo 01 TXD Transmitter output for UART1 lO SSPO SCK Serial clock for SSPO PO 16 130 J14 H14 90 BI PO 16 General purpose digital input output pin PU 1 U1 RXD Receiver input for UART1 lO SSPO SSEL Slave Select for SSPO PO 17 126 K17 112 87 BI P0 17 General purpose digital input output pin PU U1 CTS Clear to Send input for UART1 lO 55 0 MISO Master In Slave Out for SSPO PO 18 124 K15 J13 86 BI PO 18 General purpose digital input output pin PU 01 DCD Data Carrier Detect input for UART1 lO 55 0 MOSI Master Out Slave In for SSPO PO 19 122 117 J10 85 BI PO 19 General purpose digital input output pin PU 01 DSR Data Set Ready input for UART1 SD CLK Clock output line for SD card interface lO I2C1 SDA 12 1 data input output this pin does not use a specialized 2 pad LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 13 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Co
91. XP Semiconductors 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 12 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Table 3 description continued Not all functions are available on all parts See Table 2 Ethernet USB LCD QEI SD MMC DAC pins and Table 7 EMC pins Symbol 8 9 Description x x 2 O S a r7 ij E Js e IN e Ju o 5 E o g m a a c PO 13 45 R2 5 32 PO 13 General purpose digital input output pin U USB UP LED2 USB port 2 GoodLink LED indicator It is LOW when the device is configured non control endpoints enabled or when the host is enabled and has detected a device on the bus It is HIGH when the device is not configured or when host is enabled and has not detected a device on the bus or during global suspend It transitions between LOW and HIGH flashes when the host is enabled and detects activity on the bus lO SSP1 MOSI Master Out Slave In for SSP1 ADCO IN 7 A D converter 0 input 7 When configured as ADC input the digital function of the pin must be disabled PO 14 69 7 5 48 B PO 14 General purpose digital input output pin PU lo USB_HSTEN2 Host Enabled status for USB port 2 lO SSP1
92. access time board delay time delay time of feedback clock gt 0 LPC178X_7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 85 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller EMC_CLKn Te dk delay 0 EMC DYCSn EMC RAS EMC CAS EMC WE CKEOUTR EMC A 22 0 DQMOUTR D 31 0 write D 31 0 read 002aah129 Fig 19 Dynamic external memory interface signal timing Table 20 Dynamic characteristics Dynamic external memory interface programmable clock delays C 30 pF Tamb 40 C to 85 Vpp sya 3 0 V to 3 6 V Values guaranteed by design Symbol Parameter Conditions Min Unit tg delay time Programmable delay block 0 CMDDLY 0 1 0 2 ns or CLKOUTnDLY bit 0 1 Programmable delay block 1 CMDDLY 1 0 2 0 5 ns or CLKOUTnDLY bit 1 1 Programmable delay block 2 CMDDLY 20 5 13 ns or CLKOUTnDLY bit 2 1 Programmable delay block 3 CGMDDLY 111 2 2 9 ns or CLKOUTnDLY bit 3 1 Programmable delay block 4 CMDDLY 1 24 6 0 ns or CLKOUTnDLY bit 4 1 1 The programmable delay blocks are controlled by the EMCDLYCTL register in the EMC register block All delay times are incremental delays for each element starti
93. and Rs Capacitance Cp in Figure 37 represents the parallel package capacitance and should not be larger than 7 pF Parameters Fosc Rg and Cp are supplied by the crystal manufacturer LPC1xxx ji XTALIN XTALOUT 4 mo Cpe XTAL 4 k Rs 600 gt 5 5 002 424 Fig 37 Oscillator modes and models oscillation mode of operation and external crystal model used for 1 evaluation Table 32 Recommended values for Cy4 Cyz in oscillation mode crystal and external components parameters low frequency mode Fundamental oscillation Crystal load Maximum crystal External load frequency Fosc capacitance C series resistance Rg capacitors Cx1 Cx2 1 MHz to 5 MHz 10 pF lt 300 0 18 pF 18 pF 20 pF lt 3000 39 pF 39 pF 30 pF lt 300 0 57 pF 57 pF LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 103 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Table 32 Recommended values for Cy4 Cyz in oscillation mode crystal and external components parameters low frequency mode Fundamental oscillation Crystal load Maximum crystal External load frequency Fosc capacitance C series resistance Rg capacitors Cx1 Cx2 5 MHz to 10 M
94. and Table 7 EMC pins Ball Symbol Ball Symbol Ball Symbol Ball Symbol 13 2 6 14 4 27 Row G 1 Vpp REG 3V3 2 VREFP P3 7 P3 15 5 P3 3 6 8 i 9 10 11 P2 7 12 P4 10 13 Vss 14 2 8 Row H 1 P5 1 2 RSTOUT 3 VssnEG Vss 5 RTC_ALARM 6 7 8 9 10 11 P2 9 12 P4 9 13 PO 15 14 PO 16 LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 39 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Table 5 Pin allocation table TFBGA180 Not all functions are available on all parts See Table 2 and Table 7 EMC pins Symbol Ball Symbol Ball Symbol Ball Symbol Row J 1 RESET 2 3 RTCX2 4 PO 12 5 PO 13 6 7 8 9 10 PO 19 11 P4 8 12 PO 17 13 PO 18 14 Vpp ava3 Row 1 VBAT 2 1 31 3 P1 30 4 XTAL2 5 PO 29 6 P1 20 7 P3 26 8 Vpp 3v3 9 P4 3 10 4 6 11 0 21 12 4 7 13 P4 26 14 PO 20 RowL 1 P2 29 2 XTAL1 3 PO 27 4 Vpp 3v3 5 P1 18 6 4 0 7 1 25 8 VssnEG 9 Vss 10 PO 10 11 Vpp 3v3 12 5 2 13 Vss 14 PO 22 Row M 1 PO 28 2 P2 28 3 P3 25 4 P3 23 5 PO 14 6 P1 22 7 P4 1 8 P4 2 9 P1 27 10 0 11 P2 13 12 P2 11 13 P2 10 14
95. and system bus through the AHB multilayer matrix to access the various on chip SRAM blocks for Ethernet data control and status information The Ethernet block interfaces between an off chip Ethernet PHY using the Media Independent Interface MII or Reduced MII RMII protocol and the on chip Media Independent Interface Management MIIM serial bus 7 14 1 Features LPC178X 7X Ethernet standards support Supports 10 Mbit s or 100 Mbit s PHY devices including 10 Base T 100 Base TX 100 Base FX and 100 Base T4 Fully compliant with IEEE standard 802 3 Fully compliant with 802 3x Full Duplex Flow Control and Half Duplex back pressure Flexible transmit and receive frame options Virtual Local Area Network VLAN frame support e Memory management Independent transmit and receive buffers memory mapped to shared SRAM DMA managers with scatter gather DMA and arrays of frame descriptors Memory traffic optimized by buffering and pre fetching e Enhanced Ethernet features Receive filtering Multicast and broadcast frame support for both transmit and receive Optional automatic Frame Check Sequence FCS insertion with Circular Redundancy Check CRC for transmit Selectable automatic transmit frame padding Over length frame support for both transmit and receive allows any length frames Promiscuous receive mode Automatic collision back off and frame retransmi
96. ata sheet Rev 5 3 16 October 2015 29 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Table 3 description continued Not all functions are available on all parts See Table 2 Ethernet USB LCD QEI SD MMC DAC pins and Table 7 EMC pins Symbol 8 8 Description 5 t 8 S E S 3 ig ia e EJ 79 010 M7 55 BI lO 4 1 General purpose digital input output pin U A 1 External memory address line 1 P4 2 83 M8 58 lO 4 2 General purpose digital input output pin PU EMC A 2 External memory address line 2 4 3 97 016 K9 68 PA 3 General purpose digital input output pin PU A 3 External memory address line 3 P4 4 103 R15 P13 72 lO 4 4 General purpose digital input output pin PU yo EMC A 4 External memory address line 4 4 5 107 16 H10 74 Bl lO 4 5 General purpose digital input output pin PU EMC A 5 External memory address line 5 4 6 113 14 K10 78 lO PA 6 General purpose digital input output pin PU yo EMC A 6 External memory address line 6 P4 7 121 116 K12 84 BI 4 7 General purpose digital input output pin PU yo EMC A 7 External memory address
97. ations to automotive specifications and standards customer a shall use the product without NXP Semiconductors warranty of the product for such automotive applications use and specifications and b 21 Contact information 32 bit ARM Cortex M3 microcontroller whenever customer uses the product for automotive applications beyond NXP Semiconductors specifications such use shall be solely at customer s own risk and c customer fully indemnifies NXP Semiconductors for any liability damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors standard warranty and NXP Semiconductors product specifications 20 4 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners I C bus logo is a trademark of NXP Semiconductors For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com LPC178X_7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 121 of 123 NXP Semiconductors LPC178x 7x 22 Contents 32 bit ARM Cortex M3 microcontroller ooh 6 1 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 8 1 7 8 2 7 9 7 10 7 10 1 7 11
98. attery power while the rest of the device is powered up When operating from a battery the RTC will continue working down to 2 1 V Battery power can be provided from a standard 3 V lithium button cell An ultra low power 32 kHz oscillator provides a 1 Hz clock to the time counting portion of the RTC moving most of the power consumption out of the time counting function The RTC includes a calibration mechanism to allow fine tuning the count rate in a way that will provide less than 1 second per day error when operated at a constant voltage and temperature The RTC contains a small set of backup registers 20 bytes for holding data while the main part of the LPC178x 7x is powered off The RTC includes an alarm function that can wake up the LPC178x 7x from all reduced power modes with a time resolution of 1 s Features Measures the passage of time to maintain a calendar and clock Ultra low power design to support battery powered systems Provides Seconds Minutes Hours Day of Month Month Year Day of Week and Day of Year All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 59 of 123 NXP Semiconductors LPC178x 7x 7 32 7 32 1 7 33 7 33 1 LPC178X 7X 32 bit ARM Cortex M3 microcontroller Dedicated power supply pin can be connected to a battery or to the main 3 3 V Periodi
99. available on the Internet at URL http www nxp com 20 2 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information Short data sheet A short data sheet is an extract from a full data sheet with the same product type number s and title A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information For detailed and full information see the relevant full data sheet which is available on request via the local NXP Semiconductors sales office In case of any inconsistency or conflict with the short data sheet the full data sheet shall prevail Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer unless NXP Semiconductors and customer have explicitly agreed otherwise in writing In no event however shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet 20 3 Disclaimers Limited warranty and liability Informatio
100. bled 10 On pin 0 Tamb 25 11 On pin VBAT Vpp nEg sva Vpp ava 3 3 V Tamp 25 C 12 All internal pull ups disabled All pins configured as output and driven LOW Vpp avs 3 3 V Tamb 25 13 Vppa 3 3 V Tamb 25 14 VivngrP 3 3 V Tamp 25 C 15 Including voltage on outputs in 3 state mode 16 Vpp sva supply voltages must be present 17 3 state outputs go into 3 state mode in Deep power down mode 18 Allowed as long as the current limit does not exceed the maximum current allowed by the device 19 To Vss 20 3 0V lt Vpp 3v3 98 6 V LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 73 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller 10 1 Power consumption 2 051 15 002 05 IDD REG 3V3 mA VDD REG 3V3 3 6 V 3 3V d SN 1 1 30V 24 V 0 7 40 15 10 35 60 85 temperature Conditions BOD disabled Fig 9 Deep sleep mode Typical regulator supply current Ipp reg 3v3 Versus temperature 2 052 900 002 5 IDD REG 3V3 uA 600 L VDD REG 3V3 3 6 V 3 3 V 8 0 V 300 249
101. bol ale 8 7 Description Sx a D 2 a S gt m a STE TETS z amp 5 5 E o g m a a c VBAT 38 M3 K1 27 RTC power supply 3 0 V on this pin supplies power to the RTC Vpp REGy3va 26 H4 G1 18 S 3 3 V regulator supply voltage This is the power supply for the 86 P11 9 60 on chip voltage regulator that supplies internal logic 174 D11 E9 121 VppA 20 4 F2 14 S Analog 3 3 V pad supply voltage This can be connected to the same supply as Vpp ava but should be isolated to minimize noise and error This voltage is used to power the ADC and DAC Note This pin should be tied to 3 3 V if the ADC and DAC are not used Vpp 3v3 15 G3 2 41 S 3 3 V supply voltage This is the power supply voltage for I O 60 P6 L4 62 other than pins in the VBAT domain 71 P8 8 77 89 U13 111 102 112 P17 14 114 125 K16 E12 138 146 C17 E10 165 B13 C5 181 C9 198 D7 VREFP 24 G2 17 S ADC positive reference voltage This should be the same voltage as but should be isolated to minimize noise and error The voltage level on this pin is used as a reference for ADC and DAC Note This pin should be tied to 3 3 V if the ADC and DAC are not used Vss 33 H4 44 G Ground 0 V reference for digital IO pins 63 T5 4 65 77 R9 L9 79 93 P12 L13 103 114 N16 G13 117 133 14 D13 139 148 E15 C11 169 12 B4 189 B6 200 A2 Vssn
102. buffer memory and a DMA controller The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer The status of a completed USB transfer or error condition is indicated via status registers An interrupt is also generated if enabled When enabled the DMA controller transfers data between the endpoint buffer and the USB RAM Features Fully compliant with USB 2 0 Specification full speed Supports 32 physical 16 logical endpoints with a 4 kB endpoint buffer RAM Supports Control Bulk Interrupt and Isochronous endpoints Scalable realization of endpoints at run time Endpoint Maximum packet size selection up to USB maximum specification by software at run time Supports SoftConnect and GoodLink features While USB is in the Suspend mode the LPC178x 7x can enter one of the reduced power modes and wake up on USB activity Supports DMA transfers with all on chip SRAM blocks on all non control endpoints Allows dynamic switching between CPU controlled and DMA modes Double buffer implementation for Bulk and Isochronous endpoints USB host controller The host controller enables full and low speed data exchange with USB devices attached to the bus It consists of register interface serial interface engine and DMA controller The register interface complies with the Open Host Controller Interface OHCI specification Features OHCI compliant All informati
103. c interrupts can be generated from increments of any field of the time registers Backup registers 20 bytes powered by VBAT RTC power supply is isolated from the rest of the chip Event monitor recorder The event monitor recorder allows recording of tampering events in sealed product enclosures Sensors report any attempt to open the enclosure or to tamper with the device in any other way The event monitor recorder stores records of such events when the device is powered only by the backup battery Features Supports three digital event inputs in the VBAT power domain An event is defined as a level change at the digital event inputs For each event channel two timestamps mark the first and the last occurrence of an event Each channel also has a dedicated counter tracking the total number of events Timestamp values are taken from the RTC Runs in VBAT power domain independent of system power supply The event recorder monitor can therefore operate in Deep power down mode Very low power consumption Interrupt available if system is running Aqualified event can be used as a wake up trigger State of event interrupts accessible by software through GPIO Clocking and power control Crystal oscillators The LPC178x 7x include four independent oscillators These are the main oscillator the IRC oscillator the watchdog oscillator and the RTC oscillator Following reset the LPC178x 7x will operate from t
104. channel 1 CLKOUT Selectable clock output R Function reserved LCD VD 13 LCD data LCD VD 21 LCD data P1 28 90 P10 63 BI 1 28 General purpose digital input output pin PU USB SCL1 USB port 1 12C serial clock transceiver PWM1 CAPO Capture input for PWM1 channel 0 TO MATO Match output for Timer 0 channel 0 MC 2A Motor control PWM channel 2 output lO 55 0 SSEL Slave Select for SSPO LCD VD 14 LCD data LCD VD 22 LCD data LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 20 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Table 3 description continued Not all functions are available on all parts See Table 2 Ethernet USB LCD QEI SD MMC DAC pins and Table 7 EMC pins Symbol 8 9 Description S lt x 0 OG 4 5 a r7 e Ww Wwe a e Ju o s in J o g m a a c P1 29 92 U14 N10 64 B P1 29 General purpose digital input output pin U ivo USB SDA1 USB port 1 2 serial data OTG transceiver 1_ 1 Capture input for PW
105. cification UM10204 for details 2 Parameters are valid over operating temperature range unless otherwise specified 3 tHD DAT is the data hold time that is measured from the falling edge of SCL applies to data in transmission and the acknowledge 4 Adevice must internally provide a hold time of at least 300 ns for the SDA signal with respect to the of the SCL signal to bridge the undefined region of the falling edge of SCL 5 Cp total capacitance of one bus line in pF 6 The maximum t for the SDA and SCL bus lines is specified at 300 ns The maximum fall time for the SDA output stage t is specified at 250 ns This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA SCL bus lines without exceeding the maximum specified tr 7 In Fast mode Plus fall time is specified the same for both output stage and bus timing If series resistors are used designers should allow for this when considering bus timing 8 The maximum typ pat could be 3 45 us and 0 9 us for Standard mode and Fast mode but must be less than the maximum of typ par OF typ Ack by a transition time see UM10204 This maximum must only be met if the device does not stretch the LOW period ti ow of the SCL signal If the clock stretches the SCL the data must be valid by the set up time before it releases the clock 9 tSU DAT is the data set up time that is measured with respect to the rising edge of SCL applies
106. combined current of several peripherals running at the same time can be less than the sum of each individual peripheral current measured separately Table 14 Power consumption for individual analog and digital blocks Tamb 25 C Vpp REG 3V3 Vpp ava VpDA 3 3 V PCLK CCLKA Peripheral Conditions Typical supply current in mA 12 211 48 MHz 120 2121 0 0 01 0 06 0 15 0 02 0 07 0 16 Timer2 0 02 0 07 0 17 Timer3 0 01 0 07 0 16 TimerO Timer2 Timer3 0 07 0 28 0 67 UARTO 0 05 0 19 0 45 UART1 0 06 0 24 0 56 UART2 0 05 0 2 0 47 UART3 0 06 0 23 0 56 USART4 0 07 0 27 0 66 UARTO UART1 UART2 UART3 0 29 1 13 2 74 USART4 PWMO PWM1 0 08 0 31 0 75 Motor control PWM 5 0 04 0 15 0 36 2 0 0 01 0 03 0 08 I2C1 0 01 0 03 0 1 I2C2 0 01 0 03 0 08 I2C0 1261 1262 0 02 0 1 0 26 SSPO 0 03 0 1 0 26 SSP1 0 02 0 11 0 27 DAC 0 3 0 31 0 33 ADC 12 MHz clock 1 51 1 61 1 7 CAN1 0 11 0 44 1 08 CAN2 0 1 0 4 0 98 CAN1 CAN2 0 15 0 59 1 44 DMA 11 1 4 27 10 27 QEI 0 02 0 11 0 28 GPIO 0 4 1 72 4 16 LCD 0 99 3 84 9 25 125 0 04 0 18 0 46 LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16
107. cond during the rising and falling edges of the RESET signal All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 105 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller To eliminate the loss of time counts in the RTC due to voltage swing or ramp rate of the RESET signal connect an RC filter between the RESET pin and the external reset input 10 KQ RESET pin T e External T 0 1 uF RESET input 002aag552 Fig 40 Reset input with RC filter LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 106 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller 15 Package outline LQFP208 plastic low profile quad flat package 208 leads body 28 x 28 x 1 4mm SOT459 1 detail X pin 1 index DIMENSIONS mm are the original dimensions UNIT A1 A2 bp 1 45 1 35 Note 1 Plastic or metal protrusions of 0 25 mm maximum per s
108. cument is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 44 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Table 7 External memory controller pin configuration Part Data bus pins Address bus Control pins pns SRAM SDRAM LPC1788FBD208 0 31 0 25 0 BLS 3 0 EMC RAS EMC CAS EMC DYCS 3 0 EMC CS 3 0 CLK 1 0 CKE 3 0 EMC OE EMC WE DQN 3 0 LPC1788FET208 D 31 0 25 0 BLS 3 0 EMC RAS EMC CAS EMC DYCS 3 0 EMC CS 3 0 CLK 1 0 CKE 3 0 EMC OE EMC WE DQN 3 0 LPC1788FET180 EMC D 15 0 EMC A 19 0 BLS 1 0 EMC RAS EMC CAS EMC DYCS 1 0 CS 1 0 CLK 1 0 CKE 1 0 EMC OE EMC WE DQW 1 0 LPC1788FBD144 D T7 0 EMC A 15 0 EMC BLS 3 2 not available CS 1 0 EMC OE EMC WE LPC1787FBD208 D 81 0 A 25 0 BLS 3 0 EMC RAS EMC CAS EMC DYCS 3 0 EMC CS 3 0 CLK 1 0 CKE 3 0 EMC OE EMC WE EMC DQN 3 0 LPC1786FBD208 EMC 0 31 0 A 25 0 BLS 3 0 RAS CAS DYCS 3 0 EMC CS 3 0 CLK 1 0 CKE 3 0 EMC OE EMC WE DQN 3 0 LPC1785FBD208 D 31 0 A 25 0 BLS 3 0 RA
109. digital input output PU SDRAM clock enable 3 lO 55 0 MOSI Master Out Slave In for SSPO T3_MAT1 Match output for Timer 3 channel 1 P2 28 49 P4 M2 BI P2 28 General purpose digital input output pin PU Data mask 0 used with SDRAM and static devices P2 29 43 N3 L1 2 29 General purpose digital input output pin PU 1 Data mask 1 used with SDRAM and static devices P2 30 31 L4 P2 30 General purpose digital input output pin PU 2 Data mask 2 used with SDRAM and static devices lO I2C2 SDA 12 2 data input output this pin does not use a specialized 2 pad 2 Match output for Timer 3 channel 2 P2 31 39 2 Bu P2 31 General purpose digital input output pin PU Data mask used with SDRAM and static devices VO I2C2 SCL 12 2 clock input output this pin does not use specialized 2 pad T3_MAT3 Match output for Timer 3 channel 3 P3 0 to lO Port3 Port 3 is a 32 bit I O port with individual direction P3 31 controls for each bit The operation of port 3 pins depends upon the pin function selected via the pin connect block LPC178X_7X All information provided in this document is subject
110. e 32 bit prescaler Counter or timer operation Two 32 bit capture channels per timer that can take a snapshot of the timer value when an input signal transitions A capture event may also generate an interrupt Four 32 bit match registers that allow Continuous operation with optional interrupt generation on match Stop timer on match with optional interrupt generation Reset timer on match with optional interrupt generation Up to four external outputs corresponding to match registers with the following capabilities Set LOW on match Set HIGH on match Toggle on match Do nothing on match e Up to two match registers can be used to generate timed DMA requests 7 26 Pulse Width Modulator PWM LPC178X 7X The LPC178x 7x contain two standard PWMs The PWM is based on the standard Timer block and inherits all of its features although only the PWM function is pinned out on the LPC178x 7x The Timer is designed to count cycles of the system derived clock and optionally switch pins generate interrupts or perform other actions when specified timer values occur based on seven match registers The PWM function is in addition to these features and is based on match register events The ability to separately control rising and falling edge locations allows the PWM to be used for more applications For instance multi phase motor control typically requires three non overlapping PWM outputs with individua
111. e time sector or multiple 95 100 105 ms consecutive sectors torog programming 12 0 95 1 1 05 ms time 1 Number of program erase cycles 2 Programming times are given for writing 256 bytes from RAM to the flash Data must be written to the flash in blocks of 256 bytes Table 16 EEPROM characteristics Tamb 40 85 2 7 V to 3 6 V Symbol Parameter Conditions Min Typ Max Unit folk clock frequency 200 375 400 kHz Nendu endurance 100000 500000 cycles tret retention time powered 10 years unpowered 10 years ter erase time 64 bytes 1 8 ms tprog programming 64 bytes n 1 1 ms time 1 EEPROM clock frequency 375 kHz Programming erase times increase with decreasing EEPROM clock frequency All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 80 of 123 NXP Semiconductors LPC178x 7x Table 17 Dynamic characteristics Static external memory interface 30 pF Tamb 40 C to 85 2 11 2 External memory interface 32 bit ARM Cortex M3 microcontroller 3 0 V to 3 6 V Values guaranteed by design Symbol Parameter
112. eatures odede aoaie aiae PLE ERG 49 USB 50 USB device 50 Features iu sos 50 USB host 50 coge ene wed a ugue 50 USB OTG 51 F atures 2 52 tack 51 SD MNC card interface 51 Feat fes noc Rm 51 Fast general purpose parallel 51 Feat res oi edece taia ees end 52 12 bit ADC 52 Eeat les cse 52 10 bit DAC codecs t 52 Features PPP 53 VARTS o eed IRE pue wes 53 Eeat les ec E ERE Ele 53 All information provided in this document is subject to legal disclaimers 7 21 7 21 1 7 22 7 22 1 7 23 7 23 1 7 24 7 24 1 7 25 7 25 1 7 26 7 26 1 7 27 7 28 7 28 1 7 29 7 30 7 30 1 7 31 7 31 1 7 32 7 32 1 7 33 7 33 1 7 33 1 1 7 33 1 2 7 33 1 3 7 33 1 4 7 33 2 7 33 3 7 33 4 7 33 4 1 7 33 4 2 7 33 4 3 7 33 4 4 7 33 4 5 7 33 5 7 33 6 7 34 7 34 1 7 34 2 7 34 3 7 34 4 7 34 5 7 34 6 7 34 7 7 35 SSP serial I O controller 53 Fealutes coa frei aun 54 serial I O controllers 54 54 125 serial I O controllers 55 eres 55 CAN controller and accep
113. equivalent to discharging a 100 pF capacitor through a 1 5 series resistor LPC178X 7X All information provided in this document is subject to legal disclaimers Rev 5 3 16 October 2015 NXP Semiconductors N V 2015 All rights reserved 69 of 123 Product data sheet NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller 9 Thermal characteristics The average chip junction temperature T C can be calculated using the following equation Tj Pp X Rag 4 1 Tamb ambient temperature Rina the package junction to ambient thermal resistance C W e Pp sum of internal and I O power dissipation Table 10 Thermal characteristics Vpp 3 0 V to 3 6 V Tamb 40 C to 85 C unless otherwise specified Symbol Parameter Min Typ Max Unit Tjmax maximum junction 125 temperature Table 11 Thermal resistance LQFP packages Tamp 40 to 85 C unless otherwise specified Symbol Conditions Thermal resistance in C W 15 96 LQFP208 LQFP144 4 5 x 4 in 0 m s 27 4 31 5 1 m s 25 7 28 1 2 5 m s 24 4 26 2 Single layer 4 5 in x 3 in 0 m s 35 4 43 2 1 m s 31 2 35 7 2 5 m s 29 2 32 8 6jc 8 8 7 8 6jb 15 4 13 8 Table 12 Thermal resistance value TFBGA packages Tamp 40 C to 85 C unless otherwise specified
114. er Status for USB port 1 host power switch T1 MATO Match output for Timer 1 channel 0 MC 0B Motor control PWM channel 0 output B lO 55 1 MOSI Master Out Slave In for SSP1 LCD VD 8 LCD data LCD VD 12 LCD data P1 23 76 P9 7 53 1 23 General purpose digital input output pin PU USB RX DP1 D receive data for USB port 1 OTG transceiver PWM1 4 Pulse Width Modulator 1 channel 4 output QEI PHB Quadrature Encoder Interface PHB input MC FB1 Motor control PWM channel 1 feedback input lO 55 0 MISO Master In Slave Out for SSPO LCD VD 9 LCD data LCD VD 13 LCD data P1 24 78 9 P7 54 B P1 24 General purpose digital input output pin PU USB RX DM1 D receive data for USB port 1 transceiver PWM1 5 Pulse Width Modulator 1 channel 5 output QEI IDX Quadrature Encoder Interface INDEX input MC FB2 Motor control PWM channel 2 feedback input lO 55 0 MOSI Master Out Slave in for SSPO LCD VD 10 LCD data LCD VD 14 LCD data LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 19 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Table 3 description continued Not all functions are available
115. ering of TFBGA180 package SOT570 3 see detail X solder land SL 90006099 solder paste deposit SP a N 5 ne 25 95 2 eS lt 25 55 solder land plus solder paste E solder resist opening SR occupied area detail X Dimensions in mm P SL SP SR Hx Hy 0 80 0 40 0 40 0 50 12 30 12 30 44 04 30 Issue date 15 08 27 sot570 3_fr Recommend stencil thickness 0 1 mm Fig 46 Reflow soldering of the TFBGA180 package LPC178X_7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 112 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Footprint information for reflow soldering of LQFP144 package SOT486 1 a Hx Gx gt P2 gt Ad f A IE IE ZI A L ARR i 1 i E L 22 E EE ZZA 2221 1 ZA 22 1 222 222 Gy 2 222 By 2 222 I escas 2 224 d 2202 ZZ 222 TL Es 7777 ZZ 2244 1 AG oo ae ho EO C
116. erved R Function reserved R Function reserved LCD VD 1 LCD data LCD VD 5 LCD data P2 8 134 15 G14 93 BI P2 8 General purpose digital input output pin PU CAN TD2 CAN transmitter output U2 TXD Transmitter output for UART2 01 CTS Clear to Send input for UART1 ENET MDC Ethernet MIIM clock R Function reserved LCD VD 2 LCD data LCD VD 6 LCD data LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 23 of 123 NXP Semiconductors LPC178x 7x Table 3 Pin description continued 32 bit ARM Cortex M3 microcontroller Not all functions are available on all parts See Table 2 Ethernet USB LCD QEI SD MMC DAC pins and Table 7 EMC pins Symbol Pin LQFP208 1 Reset state 21 Description P2 9 em I Ball TFBGA208 I Ball TFBGA180 Pin LQFP144 P2 9 General purpose digital input output pin USB 1 USB1 SoftConnect control Signal used to switch an external 1 5 resistor under the software control Used with the SoftConnect USB feature U2 RXD Receiver input for UART2 04 RXD Receiver input for USART4 ENET MDIO Ethernet MIIM data input and output
117. es 11 5 l O pins Table 23 Dynamic characteristic I O pinsll C 10 pF Tamb 40 C to 85 C 3 0 V to 3 6 V Symbol Parameter Conditions Min Typ Max Unit tr rise time pin configured as 3 0 5 0 ns output tr fall time pin configured as 2 5 5 0 ns output 1 Applies to standard port pins LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 87 of 123 NXP Semiconductors LPC178x 7x 11 6 SSP interface LPC178X 7X 32 bit ARM Cortex M3 microcontroller Table 24 Dynamic characteristics SSP pins in SPI mode 10 pF Tamb 40 C to 85 C Vpp sya 3 0 V to 3 6 V Values guaranteed by design Symbol Parameter Conditions Min Max Unit SSP master Tey clk clock cycle time full duplex 80 ns mode when only 30 ns transmitting tps data set up time in SPI mode 21 148 ns 1 data hold time in SPI mode 21 2 ns twa data output valid inSPlmode B 6 3 ns time tha data output hold time inSPlmode 21 24 ns SSP slave Tey clk clock cycle time BI 100 A ns tps data set up time in SPI mode BIA 14 8 ns data hold time in SPI mode 34 2 ns data output valid in SPI mode BIA 6 3 ns time tha data output hold time inSPlmode BIA
118. es if the APB was not already busy Cortex M3 system tick timer including an external clock input option Standard JTAG test debug interface as well as Serial Wire Debug and Serial WireTrace Port options Embedded Trace Macrocell ETM module supports real time trace Boundary scan for simplified board testing Non maskable Interrupt NMI input Memory Up to 512 kB on chip flash program memory with In System Programming ISP and In Application Programming IAP capabilities The combination of an enhanced flash memory accelerator and location of the flash memory on the CPU local code data bus provides high code performance from flash Up to 96 kB on chip SRAM includes 64 kB of main SRAM on the CPU with local code data bus for high performance CPU access Two 16 kB peripheral SRAM blocks with separate access paths for higher throughput These SRAM blocks may be used for DMA memory as well as for general purpose instruction and data storage Up to 4032 byte on chip EEPROM LCD controller supporting both Super Twisted Nematic STN and Thin Film Transistors TFT displays Dedicated DMA controller Selectable display resolution up to 1024 x 768 pixels Supports up to 24 bit true color mode External Memory Controller EMC provides support for asynchronous static memory devices such as RAM ROM and flash as well as dynamic memories such as single data rate SDRAM with an SDRAM clock of up to 80 MHz Eight
119. eserved Product data sheet Rev 5 3 16 October 2015 28 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Table 3 description continued Not all functions are available on all parts See Table 2 Ethernet USB LCD QEI SD MMC DAC pins and Table 7 EMC pins Symbol Description o a Re ee O T 5 a r7 GONE l Ile zoER l s J o g m a a P3 25 56 U2 M3 39 lO P3 25 General purpose digital input output pin U VO D 25 External memory data line 25 PWM1 2 Pulse Width Modulator 1 output 2 TO MATO Match output for Timer 0 channel 0 P3 26 55 13 7 38 lO PS 26 General purpose digital input output pin PU yo EMC D 26 External memory data line 26 PWM1 3 Pulse Width Modulator 1 output 3 TO MAT1 Match output for Timer 0 channel 1 STCLK System tick timer clock input The maximum STCLK frequency is 1 4 of the ARM processor clock frequency CCLK P3 27 203 A1 BI lO P3 27 General purpose digital input output pin PU D 27 External memory data line 27 O PWM1 4 Pulse Width Modulator 1 output 4 T1 Capture input for Timer 1 channel 0 28 5 D2 l lO PS
120. eset has four sources on the LPC178x 7x the RESET pin the Watchdog reset Power On Reset POR and the BrownOut Detection BOD circuit The RESET pinis a Schmitt trigger input pin Assertion of chip Reset by any source once the operating voltage attains a usable level starts the Wake up timer See description in Section 7 33 3 causing reset to remain asserted until the external Reset is de asserted the oscillator is running a fixed number of clocks have passed and the flash controller has completed its initialization When the internal Reset is removed the processor begins executing at address 0 which is initially the Reset vector mapped from the boot block At that point all of the processor and peripheral registers have been initialized to predetermined values Brownout detection The LPC178x 7x include 2 stage monitoring of the voltage on the Vpp nEG ava pins If this voltage falls below 2 2 V typical the BOD asserts an interrupt signal to the Vectored Interrupt Controller This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt if not software can monitor the signal by reading a dedicated status register The second stage of low voltage detection asserts a reset to inactivate the LPC178x 7x when the voltage on the Vpp REG sva pins falls below 1 85 V typical This reset prevents alteration of the flash as operation of the various elements of the chip wou
121. ference is that the recognition of received Identifiers known in CAN terminology as Acceptance Filtering has been removed from the CAN controllers and centralized in a global Acceptance Filter Features Two CAN controllers and buses Data rates to 1 Mbit s on each bus 32 bit register and RAM access Compatible with CAN specification 2 0B ISO 11898 1 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 55 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Global Acceptance Filter recognizes 11 bit and 29 bit receive identifiers for all CAN buses Acceptance Filter can provide FullCAN style automatic reception for selected Standard Identifiers FullCAN messages can generate interrupts 7 25 General purpose 32 bit timers external event counters The LPC178x 7x include four 32 bit timer counters The timer counter is designed to count cycles of the system derived clock or an externally supplied clock It can optionally generate interrupts generate timed DMA requests or perform other actions at specified timer values based on four match registers Each timer counter also includes two capture inputs to trap the timer value when an input signal transitions optionally generating an interrupt 7 25 1 Features A 32 bit timer counter with a programmabl
122. frequency 36 MHz c ADC ADC conversion 1 16 Msa frequency mple S Cia analog input 5 pF capacitance Rysi voltage source 9 1 interface resistance 1 Vppa and VREFP should be tied to Vpp ava if the ADC and DAC are not used 2 Conditions 0 V VppA 3 3 V 3 The ADC is monotonic there no missing codes 4 The differential linearity error Ep is the difference between the actual step width and the ideal step width See Figure 28 5 The integral non linearity E is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors See Figure 28 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 94 of 123 NXP Semiconductors LPC178x 7x LPC178X 7X 6 7 8 9 32 bit ARM Cortex M3 microcontroller The offset error Eo is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve See Figure 28 The gain error is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error and the straight line which fits the ideal transfer curve See Figure 28 The absolute error
123. greement In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply NXP Semiconductors hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant conveyance or implication of any license under any copyrights patents or other industrial or intellectual property rights NXP Semiconductors 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 120 of 123 NXP Semiconductors LPC178x 7x Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from competent authorities Non automotive qualified products Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified the product is not suitable for automotive use It is neither qualified nor tested in accordance with automotive testing or application requirements NXP Semiconductors accepts no liability for inclusion and or use of non automotive qualified products in automotive equipment or applications In the event that customer uses the product for design in and use in automotive applic
124. h TTL levels and hysteresis Open drain 5 V tolerant digital I O pad compatible with I2C bus 1 MHz specification It requires an external pull up to provide output functionality When power is switched off this pin connected to the I2C bus is floating and does not disturb the 12C lines Open drain configuration applies to all functions on this pin 5 V tolerant pad 5 V tolerant if Vpp sva present if Vpp svs not present do not exceed 3 6 V with 20 ns glitch filter providing digital I O function with TTL levels and hysteresis This pad can be powered from VBAT Pad provides special analog functionality A 32 KHz crystal oscillator must be used with the RTC An external clock 32 kHz can t be used to drive the RTCX1 pin If the RTC is not used these pins can be left floating When the main oscillator is not used connect XTAL1 and XTAL2 as follows XTAL1 can be left floating or can be grounded grounding is preferred to reduce susceptibility to noise XTAL2 should be left floating Table4 Pin allocation table TFBGA208 Not all functions are available on all parts See Table 2 and Table 7 EMC pins Symbol Ball Symbol Ball Symbol Ball Symbol Row A 1 P3 27 2 Vss 3 P1 0 4 4 31 5 P1 4 6 P1 9 7 P1 14 8 P1 15 9 P1 17 10 P1 3 11 P4 15 12 13 P3 20 14 P1 11 15 PO 8 16 P1 12 17 P1 5 Row B 1 P3 2 2 P3 10 3 P3 1 4 P
125. hanism that allows remapping the interrupt vector table to alternate locations in the memory map This is controlled via the Vector Table Offset Register contained in the NVIC The vector table may be located anywhere within the bottom 1 GB of Cortex M3 address space The vector table must be located on a 128 word 512 byte boundary because the NVIC on the LPC178x 7x is configured for 128 total interrupts Debug control Debug and trace functions are integrated into the ARM Cortex M3 Serial wire debug and trace functions are supported in addition to a standard JTAG debug and parallel trace functions The ARM is configured to support up to eight breakpoints and four watch points All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 68 of 123 LPC178x 7x 32 bit ARM Cortex M3 microcontroller NXP Semiconductors 8 Limiting values Table 9 Limiting values In accordance with the Absolute Maximum Rating System IEC 60134 1 Symbol Parameter Conditions Min Max Unit Vpp ava supply voltage 3 3 V external rail 24 3 6 V Vpp REG 3v3 regulator supply voltage 3 3 V 2 4 3 6 V VppA analog 3 3 V pad supply voltage 0 5 4 6 V Vi VBAT input voltage on pin VBAT for the RTC 0 5 4 6 V Vi VREFP input voltage on pin VREFP 0 5 4 6 V ViA analog i
126. he Internal RC oscillator until switched by software This allows systems to operate without any external crystal and the boot loader code to operate at a known frequency See Figure 7 for an overview of the LPC178x 7x clock generation All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 60 of 123 NXP Semiconductors LPC178x 7x 7 33 1 1 7 33 1 2 LPC178X 7X 32 bit ARM Cortex M3 microcontroller LPC178x 7x IRC oscillator MAIN PLLO pll_clk main oscillator osc_clk gt sysclk ALT PLL1 alt CPU CLOCK DIVIDER colk CCLKSEL PERIPHERAL clk CPU clock select CLOCK DIVIDER P EMC CLOCK DIVIDER CLKSRCSEL system clock select Sysclk USB CLOCK DIVIDER use IK alt pll USBCLKSEL USB clock select 002aaf531 Fig 7 LPC178x 7x clock generation block diagram Internal RC oscillator The IRC may be used as the clock that drives the PLL and subsequently the CPU The nominal IRC frequency is 12 MHz The IRC is trimmed to 1 96 accuracy over the entire voltage and temperature range Upon power up or any chip reset the LPC178x 7x use the IRC as the clock source Software may later switch to one of the other available clock sources Main oscillator The main oscillator can be used as the clock source for the CPU
127. hys hysteresis voltage 0 4 V VoH HIGH level output 4 mA Vpp ava V voltage 0 4 VoL LOW level output lo 4 mA 0 4 V voltage HIGH level output Vpp ava 0 4 V 4 mA current LOW level output VoL 0 4 V 4 mA current lous HIGH level short circuit 0 18 45 mA output current lots LOW level short circuit Vpp ava 18 50 mA output current pull down current 5 10 50 150 uA lou pull up current Vi20V 15 50 85 Vpp 3v3 lt Vi lt 5V 0 0 0 I C bus pins 0 27 and PO 28 HIGH level input 0 7Vpp ava V voltage Vit LOW level input voltage 0 3Vpp ava V Vhys hysteresis voltage 0 05 x V VoL LOW level output lois mA 0 4 V voltage li input leakage current Vpp ava 19 2 4 uA Vi 5V 10 22 uA USB pins loz OFF state output 0V Vi 333V 20 10 current VBus bus supply voltage 20 5 25 V LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 72 of 123 NXP Semiconductors LPC178x 7x Table 13 Static characteristics continued Tamb 40 C to 85 C unless otherwise specified 32 bit ARM Cortex M3 microcontroller Symbol Parameter Conditions Min Typ Max Unit
128. ide are not included OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC JEITA PROJECTION SOT459 1 136E30 MS 026 Ed Q 2 Fig 41 LQFP208 package ISSUE DATE LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 107 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller TFBGA208 plastic thin fine pitch ball grid array package 208 balls body 15 x 15 x 0 7 mm SOT950 1 D T B A ball A1 index area A 2 r JUU 1 Ai detail X Y E 1 gt je e b 1 U i T R N i M L K Jl o oo o e2 H G F E D c B A Y ball A1 index area 0 5 10 mm scale DIMENSIONS mm are the original dimensions A UNIT Ai A2 b D E e e1 e2 v w y y 04 0 8 0 5 151 15 1 mm 12 149 149 08 128 128 0 15 0 08 012 0 1 OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC JEITA PROJECTION ISSUE DATE 06 06 01 S019301 i EI Q 06 06
129. ions are available on all parts See Table 2 and Table 7 EMC pins Symbol Ball Symbol Ball Symbol Ball Symbol Row A 5 P1 1 6 P3 8 7 P1 10 8 P1 15 9 P1 3 10 11 PO 4 12 P1 11 13 PO 9 14 1 12 i Row B 1 JTAG_TDO SWO 2 P3 11 3 P3 10 4 Vss 5 P1 0 6 P1 8 7 P1 2 8 P1 16 9 P4 29 10 P1 6 11 PO 5 12 PO 7 13 P1 5 14 P4 13 Row 1 P3 13 2 TMS SWDIO 3 JTAG TDI 4 P5 4 5 Vpp 3v3 6 P1 4 7 4 30 8 4 24 9 1 17 10 4 15 11 Vss 12 PO 8 13 P1 7 14 2 1 Row D 1 PO 26 2 JTAG 3 P3 4 4 TRST SWDCLK 5 PO 2 6 P3 0 7 P1 9 8 P1 14 9 4 25 10 4128 11 PO 6 12 P2 0 13 Vss 14 P1 13 z P Row E 1 PO 24 2 Vpp ava 3 P3 5 4 PO 25 5 P5 0 6 P3 1 7 4 31 8 4 14 9 VpD REG 3V3 10 Vpp sva 11 P2 2 12 Vpp ava 13 2 3 14 P2 4 Row 1 P3 14 VDDA Vssa 4 P3 6 5 PO 23 8 9 10 4 12 11 4 11 12 P2 5 LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 38 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Table 5 Pin allocation table TFBGA180 Not all functions are available on all parts See Table 2
130. k of the device while maintaining operation of the RTC and a small set of registers for storing data during any of the power down modes Sleep mode When Sleep mode is entered the clock to the core is stopped Resumption from the Sleep mode does not need any special sequence other than re enabling the clock to the ARM core All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 63 of 123 NXP Semiconductors LPC178x 7x 7 33 4 2 7 33 4 3 LPC178X 7X 32 bit ARM Cortex M3 microcontroller In Sleep mode execution of instructions is suspended until either a Reset or interrupt occurs Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution Sleep mode eliminates dynamic power used by the processor itself memory systems and related controllers and internal buses The DMA controller can continue to work in Sleep mode and has access to the peripheral RAMs and all peripheral registers The flash memory and the main SRAM are not available in Sleep mode they are disabled in order to save power Wake up from Sleep mode will occur whenever any enabled interrupt occurs Deep sleep mode In Deep sleep mode the oscillator is shut down and the chip receives no internal clocks The processor state and registers peripheral registers and inter
131. l control of all three pulse widths and positions All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 56 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Two match registers can be used to provide a single edge controlled PWM output One match register controls the PWM cycle rate by resetting the count upon match The other match register controls the PWM edge position Additional single edge controlled PWM outputs require only one match register each since the repetition rate is the same for all PWM outputs Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle when an PWMMRO match occurs Three match registers can be used to provide a PWM output with both edges controlled Again the PWMMRO match register controls the PWM cycle rate The other match registers control the two PWM edge positions Additional double edge controlled PWM outputs require only two match registers each since the repetition rate is the same for all PWM outputs With double edge controlled PWM outputs specific match registers control the rising and falling edge of the output This allows both positive going PWM pulses when the rising edge occurs prior to the falling edge and negative going PWM pulses when the falling edge occurs prio
132. ld otherwise become unreliable due to low voltage The BOD circuit maintains this reset down below 1 V at which point the power on reset circuitry maintains the overall reset Both the 2 2 V and 1 85 V thresholds include some hysteresis In normal operation this hysteresis allows the 2 2 V detection to reliably interrupt or a regularly executed event loop to sense the condition Code security Code Read Protection CRP This feature of the LPC178x 7x allows user to enable different levels of security in the system so that access to the on chip flash and use of the JTAG and ISP can be restricted When needed CRP is invoked by programming a specific pattern into a dedicated flash location IAP commands are not affected by the CRP There are three levels of the Code Read Protection CRP1 disables access to chip via the JTAG and allows partial flash update excluding flash sector 0 using a limited set of the ISP commands This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased CRP2 disables access to chip via the JTAG and only allows full flash erase and update using a reduced set of the ISP commands Running an application with level CRP3 selected fully disables any access to chip via the JTAG pins and the ISP This mode effectively disables ISP override using P2 10 pin too It is up to the user s application to provide if needed flash update mechanism using IAP calls or call rein
133. le 2 Ethernet USB LCD QEI SD MMC DAC pins and Table 7 EMC pins Symbol 8 9 Description S lt x 0 O 4 5 r7 LL LL o 5 4 x m a 8 PO 5 166 C12 B11 115 I PO 5 General purpose digital input output pin U 125 RX WS 125 Receive word select It is driven by the master and received by the slave Corresponds to the signal WS in the 2S bus specification CAN TD2 CAN transmitter output T2_CAP1 Capture input for Timer 2 channel 1 R Function reserved R Function reserved R Function reserved LCD VD 1 LCD data PO 6 164 D13 011 113 PO 6 General purpose digital input output pin PU 125 RX SDA 125 Receive data It is driven by the transmitter and read by the receiver Corresponds to the signal SD in the S bus specification lO SSP1 SSEL Slave Select for SSP1 O T2 MATO Match output for Timer 2 channel 0 U1 RTS Request to Send output for UART1 also be configured to be an RS 485 EIA 485 output enable signal for UART1 R Function reserved R Function reserved LCD VD 8 LCD data PO 7 162 C13 B12 112 I O PO 7 General purpose digital input output pin 125 TX SCK 125 transmit clock It is driven by the master and received by the slave Corresponds to the signal SCK in the S bus specifica
134. lect 0 up to 64 0x9000 0000 Ox93FF FFFF Static memory chip select 1 up to 64 0x9800 0000 OX9BFF FFFF Static memory chip select 2 up to 64 0x9C00 0000 OX9FFF FFFF Static memory chip select up to 64 MB Four dynamic memory chip selects 0xA000 0000 OXAFFF FFFF Dynamic memory chip select 0 up to 256 0xB000 0000 OXBFFF FFFF 0xC000 0000 OXCFFF FFFF Dynamic memory chip select 1 up to 256MB Dynamic memory chip select 2 up to 256MB 0 0000 0000 OXDFFF FFFF Dynamic memory chip select 3 up to 256MB 0xE000 0000 to OxEOOF FFFF Cortex M3 Private Peripheral Bus 0 000 0000 OxEOOF FFFF Cortex MG related functions includes the NVIC and System Tick Timer LPC178X_7X The LPC178x 7x incorporate several distinct memory regions shown in the following figures Figure 6 shows the overall map of the entire address space from the user program viewpoint following reset The interrupt vector area supports address remapping The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals The APB peripheral area is 1 MB in size and is divided to allow for up to 64 peripherals Each peripheral of either type is allocated 16 kB of space This allows simplifying the address decoding for each peripheral All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights
135. lected with the following margin tsu p delay time of feedback clock SDRAM access time board delay time gt 0 4 The data input hold time has to be selected with the following margin inp SDRAM access time board delay time delay time of feedback clock gt 0 LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 84 of 123 NXP Semic onductors LPC178x 7x Table 19 32 bit ARM Cortex M3 microcontroller 30 pF Tamb 40 C to 85 C Vpp sya 3 0 V to 3 6 V Values guaranteed by design Dynamic characteristics Dynamic external memory interface read strategy bits RD bits 01 Symbol Parameter Min Typ Max Unit Common to read and write cycles clock cycle time 10125 gt ns ta sv chip select valid delay time CMDDLY 1 x CMDDLY 1 x CMDDLY 1 x ns 0 25 4 4 6 0 25 6 4 0 25 4 9 5 this chip select hold time CMDDLY 1 x CMDDLY 1 x CMDDLY 1 x ns 0 25 0 9 0 25 1 7 0 25 3 9 ta RASV row address strobe valid CMDDLY 1 x CMDDLY 1 x CMDDLY 1 x ns delay time 0 25 4 6 0 25 6 4 0 25 9 5 h RAS row address strobe hold CMDDLY 1 x CMDDLY 1 x CMDDLY 1 x ns time 0 25 1 0 0 25 1 8 0 25 4 4 0 ta CASV column address s
136. ler if the PWM mode is not enabled 7 27 Motor control PWM LPC178X 7X The LPC178x 7x contain one motor control PWM The motor control PWM is a specialized PWM supporting 3 phase motors and other combinations Feedback inputs are provided to automatically sense rotor position and use that information to ramp speed up or down An abort input is also provided that causes the All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 57 of 123 NXP Semiconductors LPC178x 7x 7 28 7 28 1 7 29 LPC178X 7X 32 bit ARM Cortex M3 microcontroller PWM to immediately release all motor drive outputs At the same time the motor control PWM is highly configurable for other generalized timing counting capture and compare applications The maximum PWM speed is determined by the PWM resolution n and the operating frequency f PWM speed 1 2 see Table 8 Table 8 PWM speed at operating frequency 120 MHz PWM resolution PWM speed 6 bit 1 875 MHz 8 bit 0 468 MHz 10 bit 0 117 MHz Quadrature Encoder Interface QEI Remark The QEI is available on parts LPC1788 87 86 and LPC1778 77 76 A quadrature encoder also known as a 2 channel incremental encoder converts angular displacement into two pulse signals By monitoring both the number of pulses and the relative phase of the two sig
137. line 7 4 8 127 J17 011 88 PA 8 General purpose digital input output pin PU EMC A 8 External memory address line 8 4 9 131 H17 H12 91 4 9 General purpose digital input output pin PU yo EMC A 9 External memory address line 9 P4 10 135 G17 G12 94 01 lO PA 10 General purpose digital input output pin PU yo EMC A 10 External memory address line 10 P4 11 145 14 11 101 BI lO 4 11 General purpose digital input output pin PU yo EMC A 11 External memory address line 11 4 12 149 C16 F10 104 BI lO 4 12 General purpose digital input output pin PU EMC A 12 External memory address line 12 4 13 155 B16 B14 108 BI 4 13 General purpose digital input output pin PU EMC A 13 External memory address line 13 4 14 159 B15 E8 110 BI lO 4 14 General purpose digital input output pin PU yo A 14 External memory address line 14 P4 15 173 11 C10 120 BI 4 15 General purpose digital input output pin PU EMC A 15 External memory address line 15 P4 16 101 U17 12 lO 4 16 General purpose digital input output pin PU uo EMC A 16 External memory address line 16 P4 1 7 104 P14 N13 lO 4 17 General purpose digital input output pin PU A 17 External memory address line 17 P4 18 105 P15 14 lO 4 18
138. n in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to the removal or replacement of any products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might incur for any reason whatsoever NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof LPC178X 7X
139. n mode enabled disabled Digital input Pull up enabled disabled Digital input Pull down enabled disabled Digital input Repeater mode enabled disabled Analog input The default configuration for standard pins is input with pull up enabled The weak MOS devices provide a drive capability equivalent to pull up and pull down resistors LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 104 of 123 NXP Semiconductors LPC178x 7x 14 5 14 6 LPC178X 7X 32 bit ARM Cortex M3 microcontroller pin configured as digital output driver open drain enable output enable data output VDD urup E strong pull down VDD Vss VDD weak pull up pull up enable t d m weak pin configured eoa E pull down as digital input pull down enable data input 4 select analog input pin configured y as analog input analog input 002aaf272 Fig 38 Standard pin configuration with analog input Reset pin configuration Vpp Vpp 20 ns RC TL roset lt i GLITCH FILTER PIN ESD Vss 002aaf274 Fig 39 Reset pin configuration Reset pin configuration for RTC operation Under certain circumstances the RTC may temporarily pause and lose fractions of a se
140. nal SRAM values are preserved throughout Deep sleep mode and the logic levels of chip pins remain static The output of the IRC is disabled but the IRC is not powered down to allow fast wake up The RTC oscillator is not stopped because the RTC interrupts may be used as the wake up source The PLL is automatically turned off and disconnected The clock divider registers are automatically reset to zero The Deep sleep mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks Since all dynamic operation of the chip is suspended Deep sleep mode reduces chip power consumption to a very low value Power to the flash memory is left on in Deep sleep mode allowing a very quick wake up Wake up from Deep sleep mode can initiated by the NMI External Interrupts EINTO through EINT3 GPIO interrupts the Ethernet Wake on LAN interrupt Brownout Detect an RTC Alarm interrupt a USB input pin transition USB activity interrupt a CAN input pin transition or a Watchdog Timer time out when the related interrupt is enabled Wake up will occur whenever any enabled interrupt occurs On wake up from Deep sleep mode the code execution and peripherals activities will resume after four cycles expire if the IRC was used before entering Deep sleep mode If the main external oscillator was used the code execution will resume when 4096 cycles expire PLL and clock dividers need to be
141. nals the user can track the position direction of rotation and velocity In addition a third channel or index signal can be used to reset the position counter The quadrature encoder interface decodes the digital pulses from a quadrature encoder wheel to integrate position over time and determine direction of rotation In addition the QEI can capture the velocity of the encoder wheel Features Tracks encoder position ncrements decrements depending on direction Programmable for 2x or 4x position counting Velocity capture using built in timer Velocity compare function with less than interrupt Uses 32 bit registers for position and velocity Three position compare registers with interrupts Index counter for revolution counting Index compare register with interrupts Can combine index and position interrupts to produce an interrupt for whole and partial revolution displacement Digital filter with programmable delays for encoder input signals Can accept decoded signal inputs clk and direction Connected to APB ARM Cortex M3 system tick timer The ARM Cortex M3 includes a system tick timer SYSTICK that is intended to generate a dedicated SYSTICK exception at a 10 ms interval In the LPC178x 7x this timer can be clocked from the internal AHB clock or from a device pin All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights
142. nd peripheral interrupts On the LPC178x 7x the NVIC supports 40 vectored interrupts 32 programmable interrupt priority levels with hardware priority level masking Relocatable vector table Non Maskable Interrupt NMI Software interrupt generation 7 8 2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags Individual interrupt flags may also represent more than one interrupt source Any pin on port 0 and port 2 regardless of the selected function can be programmed to generate an interrupt on a rising edge a falling edge or both 7 9 Pin connect block The pin connect block allows selected pins of the microcontroller to have more than one function Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt s being enabled Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined Most pins can also be configured as open drain outputs or to have a pull up pull down or no resistor enabled 7 10 External memory controller Remark Supported memory size and type and EMC bus width vary for different parts see Table 2 The EMC pin configuration for each part is shown in Table 7 LPC178X_7X All information provided in this do
143. ng from delay block 0 See the LPC178x 7x user manual for details LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 86 of 123 NXP Semiconductors LPC178x 7x 11 3 External clock 32 bit ARM Cortex M3 microcontroller Table 24 Dynamic characteristic external clock see Figure 36 Tamb 40 C to 85 over specified ranges Symbol Parameter Min Typ Max Unit fosc oscillator frequency 1 12 25 MHz Toy clk clock cycle time 40 83 3 1000 ns clock HIGH time 0 4 ns clock LOW time 0 4 ns clock rise time ns tcHcL clock fall time ns 002aaa907 Fig 20 External clock timing with an amplitude of at least Virus 200 mV 11 4 Internal oscillators Table 22 Dynamic characteristic internal oscillators Tamb 40 to 85 2 7 V x VppinEG ava lt 3 6 Symbol Parameter Min Typ Unit fosc RC internal RC oscillator frequency 11 88 12 12 12 MHz fiRTC RTC input frequency 32 768 kHz 1 Parameters are valid over operating temperature range unless otherwise specified 2 Typical ratings are not guaranteed The values listed are at room temperature 25 nominal supply voltag
144. nput voltage on ADC related 0 5 5 1 V pins Vi input voltage 5 V tolerant digital 0 5 45 5 V pins Vpp av3 gt 2 4 Vpp ava 0 V 0 5 3 6 V other I O pins 0 5 Vpp ava V 0 5 Ipp supply current per supply pin 100 mA Iss ground current per ground pin 100 mA latch I O latch up current 0 5Vpp ava lt Vi 100 mA lt 1 5Vpp sva Tj lt 125 storage temperature non operating 65 150 C Ptot pack total power dissipation per package based on package 1 5 W heat transfer not device power consumption Vesp electrostatic discharge voltage human body 5 4000 V model all pins 1 The following applies to the limiting values a This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge Nonetheless it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum b Parameters are valid over operating temperature range unless otherwise specified voltages are with respect to Vss unless otherwise noted 2 Including voltage on outputs in 3 state mode 3 Not to exceed 4 6 V 4 The maximum non operating storage temperature is different than the temperature for required shelf life which should be determined based on the required shelf lifetime Please refer to the JEDEC spec for further details 5 Human body model
145. nse MII interface or Ethernet Carrier Sense Data Valid RMII interface R Function reserved O T3_MAT1 Match output for Timer 3 channel 1 lO 55 2 SSEL Slave Select for SSP2 P1 9 188 A6 D7 131 BI P1 9 General purpose digital input output pin PU ENET RXDO0 Ethernet receive data 0 RMII MII interface R Function reserved T3_MATO Match output for Timer 3 channel 0 P1 10 186 7 129 BI P1 10 General purpose digital input output pin PU RXD1 Ethernet receive data 1 RMII MII interface R Function reserved T3_CAPO Capture input for Timer channel 0 1 11 163 14 12 lO 1 11 General purpose digital input output pin PU RXD2 Ethernet Receive Data 2 MII interface 650 DAT 2 Data line 2 for SD card interface PWMO 6 Pulse Width Modulator 0 output 6 P1 12 157 16 14 P1 12 General purpose digital input output pin PU ENET RXD3 Ethernet Receive Data interface 650 DAT S3 Data line for SD card interface PWMO Capture input for PWMO channel 0 P1 13 147 016 014 8 P1 13 General purpose digital input output pin PU ENET RX DV Ethernet Receive Data Valid MII interface P1 14 184 7 08 128 BI lO P1 14 General purpose digital input output pin PU ENET RX ER Ethernet receive error
146. o additional 16 kB each SRAM blocks situated on a separate slave port on the AHB multilayer matrix This architecture allows CPU and DMA accesses to be spread over three separate RAMs that can be accessed simultaneously Memory Protection Unit MPU The LPC178x 7x have a Memory Protection Unit MPU which can be used to improve the reliability of an embedded system by protecting critical data within the user application The MPU allows separating processing tasks by disallowing access to each other s data disabling access to memory regions allowing memory regions to be defined as read only and detecting unexpected memory accesses that could potentially break the system All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 41 of 123 NXP Semiconductors LPC178x 7x Table 6 32 bit ARM Cortex M3 microcontroller The MPU separates the memory into distinct regions and implements protection by preventing disallowed accesses The MPU supports up to eight regions each of which can be divided into eight subregions Accesses to memory locations that are not defined in the MPU regions or not permitted by the region setting will cause the Memory Management Fault exception to take place 7 7 Memory map LPC178x 177x memory usage and details Address range General Use Address range details and descri
147. on all parts See Table 2 Ethernet USB LCD QEI SD MMC DAC pins and Table 7 EMC pins Symbol 2 Description co N T 4 lt x O O 5 a 7 Gj le e S e Ju o s J a e o P1 25 80 T10 L7 56 BI lO 1 25 General purpose digital input output pin U lo USB LS1 Low Speed status for USB port 1 OTG transceiver USB HSTEN 1 Host Enabled status for USB port 1 T1 MAT1 Match output for Timer 1 channel 1 _1 Motor control PWM channel 1 output A CLKOUT Selectable clock output LCD VD 11 LCD data LCD VD 15 LCD data P1 26 82 R10 P8 57 BI P1 26 General purpose digital input output pin PU USB SSPND1 USB port 1 Bus Suspend status transceiver PWM1 6 Pulse Width Modulator 1 channel 6 output TO_CAPO Capture input for Timer 0 channel 0 MC 1B Motor control PWM channel 1 output B lO SSP1 SSEL Slave Select for SSP1 LCD VD 12 LCD data LCD VD 20 LCD data P1 27 88 T12 M9 61 P1 27 General purpose digital input output pin PU 1 USB INT1 USB port 1 OTG transceiver interrupt OTG transceiver USB OVRCR1 USB port 1 Over Current status TO CAP1 Capture input for Timer 0
148. on provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 50 of 123 NXP Semiconductors LPC178x 7x 7 15 3 7 15 3 1 7 16 7 16 1 7 17 LPC178X 7X 32 bit ARM Cortex M3 microcontroller Two downstream ports Supports per port power switching USB OTG controller USB OTG is a supplement to the USB 2 0 Specification that augments the capability of existing mobile devices and USB peripherals by adding host functionality for connection to USB peripherals The OTG Controller integrates the host controller device controller and a master only 2 interface to implement OTG dual role device functionality The dedicated 2 interface controls an external OTG transceiver Features Fully compliant with On The Go supplement to the USB 2 0 Specification Revision 1 0a Hardware support for Host Negotiation Protocol HNP Includes a programmable timer required for HNP and Session Request Protocol SRP Supports any OTG transceiver compliant with the OTG Transceiver Specification CEA 2011 Rev 1 0 SD MMC card interface Remark The SD MMC card interface is available on parts LPC1788 87 86 85 and parts LPC1778 77 76 The Secure Digital and Multimedia Card Interface MCI allows access to external SD memory cards The SD card interface conforms to the SD Multimedia Card Specification Version 2 11
149. output It can be used with the GPDMA CAN controller with two channels BW Digital peripherals SD MMC memory card interface Up to 165 General Purpose I O GPIO pins depending on the packaging with configurable pull up down resistors open drain mode and repeater mode All GPIOs are located on an AHB bus for fast access and support Cortex M3 bit banding GPIOs can be accessed by the General Purpose DMA Controller Any pin of ports 0 and 2 can be used to generate an interrupt Two external interrupt inputs configurable as edge level sensitive All pins on port 0 and port 2 can be used as edge sensitive interrupt sources Four general purpose timers counters with a total of eight capture inputs and ten compare outputs Each timer block has an external count input Specific timer events can be selected to generate DMA requests Quadrature encoder interface that can monitor one external quadrature encoder Two standard PWMy timer blocks with external count input option One motor control PWM with support for three phase motor control Real Time Clock RTC with a separate power domain The RTC is clocked by a dedicated RTC oscillator The RTC block includes 20 bytes of battery powered backup registers allowing system status to be stored when the rest of the chip is powered off Battery power can be supplied from a standard 3 V lithium button cell The RTC will continue working when the battery voltage drops to as low a
150. p ava 4 VppA 5 6 7 8 9 10 11 12 l 13 14 5 3 15 P4 27 16 2 7 17 Row 1 PO 23 2 P3 14 3 P3 30 4 Vpb REG 3V3 5 6 Y 8 9 10 11 12 l 13 14 Vss 15 P2 8 16 P2 9 17 P4 9 Row J 1 P3 6 Vssa P3 31 4 P5 1 5 8 9 10 11 12 l LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 36 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Table 4 allocation table TFBGA208 Not all functions are available on all parts See Table 2 and Table 7 EMC pins Ball Symbol Ball Symbol Ball Symbol Ball Symbol 13 14 PO 16 15 P4 23 16 PO 15 17 4 8 Row K 1 VREFP 2 RTCX1 3 RSTOUT 4 VSSREG 13 i 14 P4 22 15 PO 18 16 17 PO 17 RowL 1 P3 7 2 RTCX2 3 Vss 4 P2 30 5 6 7 8 9 10 l 11 12 13 14 5 2 15 P4 26 16 17 PO 19 Row M 1 P3 15 2 RESET 3 VBAT 4 XTAL1 5 6 7 8 9 10 d b 12 l js 14 4 6 15 P4 21 16 PO 21 17 PO 20 Row N 1 RTC ALARM 2 P2 31 3 P2 29 4 XTAL2 5 6 7 8 9 10 l 11 12 13 14 2 12 15 P2 10 16 Ves
151. panel and TFT panels can be operated The display resolution is selectable and can be up to 1024 x 768 pixels Several color modes are provided up to a 24 bit true color non palettized mode An on chip 512 byte color palette allows reducing bus utilization i e memory size of the displayed data while still supporting a large number of colors The LCD interface includes its own DMA controller to allow it to operate independently of the CPU and other system functions A built in FIFO acts as a buffer for display data providing flexibility for system timing Hardware cursor support can further reduce the amount of CPU time needed to operate the display 7 13 1 Features LPC178X 7X AHB master interface to access frame buffer e Setup and control via a separate AHB slave interface Dual 16 deep programmable 64 bit wide FIFOs for buffering incoming display data Supports single and dual panel monochrome Super Twisted Nematic STN displays with 4 bit or 8 bit interfaces Supports single and dual panel color STN displays Supports Thin Film Transistor TFT color displays Programmable display resolution including but not limited to 320 x 200 320 x 240 640 x 200 640 x 240 640 x 480 800 x 600 and 1024 x 768 Hardware cursor support for single panel displays 15 gray level monochrome 3375 color STN and 32 K color palettized TFT support 1 2 or 4 bits per pixel bpp palettized displays for monochrome STN 1
152. pherals alive The second option uses two power supplies a 3 3 V supply for the I O pads Vpp ava and a dedicated 3 3 V supply for the CPU Vpp REG sva Having the on chip voltage regulator powered independently from the pad ring enables shutting down of the pad power supply the fly while the CPU and peripherals stay active The VBAT pin supplies power only to the RTC domain The RTC operates at very low power which can be supplied by an external battery The device core power Vpp REG 3v3 is used to operate the RTC whenever Vpp REG ava is present There is no power drain from the RTC battery when Vpp neg ava is at nominal levels and Vpp REG 3v3 gt 178 7 to I O pads Vss to core VDD REG 3V3 REGULATOR to memories typical 3 3 V peripherals oscillators MAIN POWER DOMAIN ULTRA LOW VBAT POWER POWER typical 3 0 V SELECTOR REGULATOR BACKUP REGISTERS RTCX1 32 kHz RICX OSCILLATOR REAL TIME CLOCK 1 POWER DOMAIN VDDA VREFP Vssa Fig 8 Power distribution ADC POWER DOMAIN 002aaf530 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 66 of 123 NXP Semiconductors LPC178x 7x 7 34 7 34 1 7 34 2 7 34 3 LPC178X 7X 32 bit ARM Cortex M3 microcontroller System control Reset R
153. ption 0x0000 0000 to Ox1FFF FFFF On chip non volatile memory 0x0000 0000 0x0007 FFFF For devices with 512 kB of flash memory 0x0000 0000 0x0003 FFFF For devices with 256 kB of flash memory 0x0000 0000 0x0001 FFFF For devices with 128 kB of flash memory 0x0000 0000 0x0000 FFFF For devices with 64 kB of flash memory On chip main SRAM 0x1000 0000 0x1000 FFFF For devices with 64 kB of main SRAM 0x1000 0000 0x1000 7FFF For devices with 32 kB of main SRAM 0x1000 0000 0x1000 3FFF For devices with 16 kB of main SRAM Boot ROM Ox1FFF 0000 0x1FFF 1FFF 8 kB Boot ROM with flash services 0x2000 0000 to Ox3FFF FFFF On chip SRAM typically used for peripheral data 0x2000 0000 0x2000 1FFF Peripheral RAM bank 0 first 8 0x2000 2000 0x2000 3FFF Peripheral RAM bank 0 second 8 kB 0x2000 4000 0x2000 7FFF Peripheral RAM bank 1 16 kB AHB peripherals 0x2008 0000 0x200B FFFF See Figure 6 for details 0x4000 0000 to Ox7FFF FFFF APB Peripherals 0x4000 0000 0x4007 FFFF APBO Peripherals up to 32 peripheral blocks of 16 kB each 0x4008 0000 0x400F FFFF APB1 Peripherals up to 32 peripheral blocks of 16 kB each 0x8000 0000 to OxDFFF FFFF Off chip Memory via the External Memory Controller Four static memory chip selects 0x8000 0000 Ox83FF FFFF Static memory chip se
154. put and component selection The input voltage to the on chip oscillators is limited to 1 8 V If the oscillator is driven by a clock in slave mode it is recommended that the input be coupled through a capacitor with Cj 100 pF To limit the input voltage to the specified range choose an additional capacitor to ground Cg which attenuates the input voltage by a factor Cg In slave mode a minimum of 200 mV RMS is needed LPC178X_7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 102 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller LPC1xxx 5 100pF F 002aae835 Fig 36 Slave mode operation of the on chip oscillator In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF Figure 36 with an amplitude between 200 mV RMS and 1000 mV RMS This corresponds to a square wave signal with a signal swing of between 280 mV and 1 4 V The XTALOUT pin in this configuration can be left unconnected External components and models used in oscillation mode are shown in Figure 37 and in Table 32 and Table 33 Since the feedback resistance is integrated on chip only a crystal and the capacitances Cy and Cy need to be connected externally in case of fundamental mode oscillation the fundamental frequency is represented by L C
155. r 10 Mbit s slave Compatible with Motorola SPI 4 wire Texas Instruments SSI and National Semiconductor Microwire buses Synchronous serial communication Master or slave operation 8 frame FIFOs for both transmit and receive 4 bit to 16 bit frame DMA transfers supported by GPDMA I C bus serial I O controllers The LPC178x 7x contain three I C bus controllers I C bus is bidirectional for inter IC control using only two wires a Serial Clock Line SCL and a Serial Data Line SDA Each device is recognized by a unique address and can operate as either a receiver only device e g an LCD driver or a transmitter with the capability to both receive and send information such as memory Transmitters and or receivers can operate in either master or slave mode depending on whether the chip has to initiate a data transfer or is only addressed The 2 is a multi master bus and can be controlled by more than one bus master connected to it Features All IC bus controllers can use standard GPIO pins with bit rates of up to 400 kbit s Fast I C bus The 2 0 interface uses special open drain pins with bit rates of up to 400 kbit s e The 2 interface supports Fast mode Plus with bit rates up to 1 Mbit s for I2CO using pins P5 2 P5 3 Easy to configure as master slave or master slave Programmable clocks allow versatile rate control Bidirectional data transfer between
156. r for baud rate control auto baud capabilities and FIFO control mechanism that enables software flow control implementation Support for RS 485 9 bit EIA 485 mode and multiprocessor addressing UARTs have support for both transmit and receive UART1 equipped with standard modem interface signals This module also provides full support for hardware flow control auto CTS RTS USARTA includes an IrDA mode to support infrared communication USARTA supports synchronous mode and a smart card mode conforming to 1507816 3 7 21 SSP serial controller The LPC178X 7x contain three SSP controllers The SSP controller is capable of operation on a SPI 4 wire SSI or Microwire bus It can interact with multiple masters and slaves on the bus Only a single master and a single slave can communicate on the bus LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 53 of 123 NXP Semiconductors LPC178x 7x 7 21 1 7 22 7 22 1 LPC178X 7X 32 bit ARM Cortex M3 microcontroller during a given data transfer The SSP supports full duplex transfers with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master In practice often only one of these data flows carries meaningful data Features Maximum SSP speed of 33 Mbit s master o
157. r to allow observe its frequency In order to allow Watchdog Timer operation with minimum power consumption which can be important in reduced power modes the Watchdog oscillator frequency is not tightly controlled The Watchdog oscillator frequency will vary over temperature and power supply within a particular part and may vary by processing across different parts This variation should be taken into account when determining Watchdog reload values Within a particular part temperature and power supply variations can produce up to a 17 frequency variation Frequency variation between devices under the same operating conditions can be up to 30 Main PLL PLLO and Alternate PLL PLL1 PLLO also called the Main PLL and PLL1 also called the Alternate PLL are functionally identical but have somewhat different input possibilities and output connections These possibilities are shown in Figure 7 The Main PLL can receive its input from either the IRC or the main oscillator and can potentially be used to provide the clocks to nearly everything on the device The Alternate PLL receives its input only from the main oscillator and is intended to be used as an alternate source of clocking to the USB The USB has timing needs that may not always be filled by the Main PLL Both PLLs are disabled and powered off on reset If the Alternate PLL is left disabled the USB clock can be supplied by PLLO if everything is set up to provide 48 MHz to the U
158. r to the rising edge 7 26 1 Features e LPC178X 7x has two PWM blocks with Counter or Timer operation may use the peripheral clock or one of the capture inputs as the clock source Seven match registers allow up to 6 single edge controlled or 3 double edge controlled PWM outputs or a mix of both types The match registers also allow Continuous operation with optional interrupt generation on match Stop timer on match with optional interrupt generation Reset timer on match with optional interrupt generation Supports single edge controlled and or double edge controlled PWM outputs Single edge controlled PWM outputs all go high at the beginning of each cycle unless the output is a constant low Double edge controlled PWM outputs can have either edge occur at any position within a cycle This allows for both positive going and negative going pulses Pulse period and width can be any number of timer counts This allows complete flexibility in the trade off between resolution and repetition rate All PWM outputs will occur at the same repetition rate Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses Software must release new match values before they can become effective May be used as a standard 32 bit timer counter with a programmable 32 bit presca
159. reserved Product data sheet Rev 5 3 16 October 2015 42 of 123 XL X8L12d1 Lp 19npoJd 9100 1990190 91 676 sieuire osip 1291416 s jueuunoop S14 uoneuuojul APB1 peripherals LPC178x 7x APBO peripheral 0x4010 0000 Pp 4GB_ 0x4008 0000 240 od OxFFFF FFFF S494 fecened i reservi 24 reserve a EE oxE010 0000 31 24rseN d 0060000 T 30 17 private peripheral bus oxE004 0000 23 12 1 ox4ooc 0000 167 SD MMC D au reserved 22 19 reserved 151 1 0 000 0000 0 400 000 1 1 n 0x4004 8000 Ox400B 8000 14 motor control PWM x EMC 4 x dynamic chip select 3 ia EMCA x static chip select 2 16 CAN common 0x4004 0000 0x400B 0000 i 15 CAN AF registers 0x4003 C000 S reserved A dici 0x4400 0000 14 CAN AF RAM 0x4003 8000 peripheral bit band alias addressing 0x4200 0000 13 ADC 0x4003 4000 0x400A 4000 0x400A 0000 2 reserved ES 12 0x4003 0000 x 0x4010 0000 a 2 0 4009 000 SS APB1 peripherals 0x4009 8000 0x4009 4000 0x4009 0000 4 peripherals 0x4008 0000 10 GPIO interrupts 0x4002 8000 vee aei 0x4000 0000 RTC event recorder 2 0 2900 0000 backup registers 0x4002 4000 timer 3 timer 2 reserved reserved 0x4002 0000 012800 0000 X 0x4008 C000 2 0 4001 000 pe gt 0 2400 000
160. reserved Product data sheet Rev 5 3 16 October 2015 58 of 123 NXP Semiconductors LPC178x 7x 7 30 7 30 1 7 31 7 31 1 LPC178X 7X 32 bit ARM Cortex M3 microcontroller Windowed WatchDog Timer WWDT The purpose of the watchdog is to reset the controller if software fails to periodically service it within a programmable time window Features Internally resets chip if not periodically reloaded during the programmable time out period Optional windowed operation requires reload to occur between a minimum and maximum time period both programmable Optional warning interrupt can be generated at a programmable time prior to watchdog time out Enabled by software but requires a hardware reset or a watchdog reset interrupt to be disabled Incorrect feed sequence causes reset or interrupt if enabled Flag to indicate watchdog reset Programmable 24 bit timer with internal prescaler Selectable time period from 256 4 to Tcy wDCLK x 224 x 4 in multiples of Tey WDCLK x 4 The Watchdog Clock WDCLK source is a dedicated watchdog oscillator which is always running if the watchdog timer is enabled RTC and backup registers The RTC is a set of counters for measuring time when system power is on and optionally when it is off The RTC on the LPC178x 7x is designed to have very low power consumption The RTC will typically run from the main chip power supply conserving b
161. rnal SD card power supply PWMO 3 Pulse Width Modulator 0 output 3 P1 6 171 B11 10 lO P1 6 General purpose digital input output pin PU ENET TX CLK Ethernet Transmit Clock MII interface l O SD DAT 0 Data line 0 for SD card interface PWMO 4 Pulse Width Modulator 0 output 4 P1 7 153 D14 BI P1 7 General purpose digital input output pin PU ENET COL Ethernet Collision detect interface 80 DAT 1 Data line 1 for SD card interface PWMO 5 Pulse Width Modulator 0 output 5 LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 16 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Table 3 description continued Not all functions are available on all parts See Table 2 Ethernet USB LCD QEI SD MMC DAC pins and Table 7 EMC pins Symbol 2 Description S lt sh o T 5 a a GONE l le zoER E a B o E m a 8 P1 8 190 C7 B6 132 P1 8 General purpose digital input output pin U ENET CRS ENET CRS DV Ethernet Carrier Se
162. roduce a signal of sufficient amplitude to drive the clock logic The amount of time depends on many factors including the rate of Vpp sva ramp in the case of power on the type of crystal and its electrical characteristics if a quartz crystal is used as well as any other external circuitry e g capacitors and the characteristics of the oscillator itself under the existing ambient conditions Power control The 178 7 support a variety of power control features There are four special modes of processor power reduction Sleep mode Deep sleep mode Power down mode and Deep power down mode The CPU clock rate may also be controlled as needed by changing clock sources reconfiguring PLL values and or altering the CPU clock divider value This allows a trade off of power versus processing speed based on application requirements In addition the peripheral power control allows shutting down the clocks to individual on chip peripherals allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application Each of the peripherals has its own clock divider which provides even better power control The integrated PMU Power Management Unit automatically adjusts internal regulators to minimize power consumption during Sleep Deep sleep Power down and Deep power down modes The LPC178x 7x also implement a separate power domain to allow turning off power to the bul
163. rtex M3 microcontroller Table3 Pin description continued Not all functions are available on all parts See Table 2 Ethernet USB LCD QEI SD MMC DAC pins and Table 7 EMC pins Symbol 8 9 Description S lt x 0 OG 4 5 a r7 IN o 5 E o g m a a c PO 20 120 M17 14 83 BI PO 20 General purpose digital input output pin U lo 01 Data Terminal Ready output for UART1 Can also be configured to be an RS 485 EIA 485 output enable signal for UART1 lO SD CMD Command line for SD card interface 2 SCL 12 1 clock input output this pin does not use a specialized 2 pad 0 21 118 16 82 BI PO 21 General purpose digital input output pin PU U1 RI Ring Indicator input for UART1 SD PWR Power Supply Enable for external SD card power supply 04 OE RS 485 EIA 485 output enable signal for UART4 CAN RD1 CANI receiver input VO 04 SCLK USART 4 clock input or output in synchronous mode PO 22 116 17 114 80 l PO 22 General purpose digital input output pin PU U1 RTS Request to Send output for UART1 Can also be configured to be an RS 485 EIA 485 output enable signal for UART1 VO 80 DAT 0 Data line 0 for SD card interface 04 TX
164. s Vpp REG 3V3 Vpp ava 3 3 V standard port pins Fig 13 Typical LOW level output current loj versus LOW level output voltage VoL All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 78 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller 002aaf108 Conditions Vpp REG 3V3 3 3 V standard port pins Fig 14 Typical pull up current ly versus input voltage Vi 002aaf109 90 Conditions VDD REG 3V3 Vpp ava 3 3 V standard port pins Fig 15 Typical pull down current lg versus input voltage Vi LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 79 of 123 NXP Semiconductors LPC178x 7x 11 Dynamic characteristics 32 bit ARM Cortex M3 microcontroller 11 1 Flash memory LPC178X 7X Table 15 Flash characteristics Tamb 40 to 85 unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Nendu endurance 10000 100000 cycles tret retention time powered 10 years unpowered 20 years ter eras
165. s 2 1 V An RTC interrupt can wake up the CPU from any reduced power mode Event Recorder that can capture the clock value when an event occurs on any of three inputs The event identification and the time it occurred are stored in registers The Event Recorder is located in the RTC power domain and can therefore operate as long as there is RTC power Windowed Watchdog Timer WWDT Windowed operation dedicated internal oscillator watchdog warning interrupt and safety features CRC Engine block can calculate a CRC on supplied data using one of three standard polynomials The CRC engine can be used in conjunction with the DMA controller to generate a CRC without CPU involvement in the data transfer B Analog peripherals 12 bit Analog to Digital Converter ADC with input multiplexing among eight pins conversion rates up to 400 kHz and multiple result registers The 12 bit ADC can be used with the GPDMA controller 10 bit Digital to Analog Converter DAC with dedicated conversion timer and GPDMA support B Power control Four reduced power modes Sleep Deep sleep Power down and Deep power down LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 3 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller The Wake up Interrupt Controller WIC allows
166. se digital input output pin PU D 6 External memory data line 6 P3 7 27 L1 G3 19 lO P3 7 General purpose digital input output pin PU yo DJ 7 External memory data line 7 P3 8 191 08 6 PS 8 General purpose digital input output pin PU yo D 8 External memory data line 8 P3 9 199 C5 4 P3 9 General purpose digital input output pin PU EMC D 9 External memory data line 9 P3 10 205 B2 B3 lO PS 10 General purpose digital input output pin PU yo EMC D 10 External memory data line 10 P3 11 208 D5 B2 lO P3 11 General purpose digital input output pin PU yo EMC_D 11 External memory data line 11 P3 12 1 04 1 lO P3 12 General purpose digital input output pin PU yo EMC D 12 External memory data line 12 P3 13 7 Ci lO 13 General purpose digital input output pin PU yo D 13 External memory data line 13 P3 14 21 H2 Fi lO PS 14 General purpose digital input output pin PU EMC D 14 External memory data line 14 P3 15 28 Mi G4 15 General purpose digital input output pin PU O D 15 External memory data line 15 P3 16 137 F17 lO 16 General purpose digital input output pin PU EMC D 16 External memory data line 16 PWMO 1 Pulse Width
167. ssion Includes power management by clock switching Wake on LAN power management support allows system wake up using the receive filters or a magic frame detection filter All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 49 of 123 NXP Semiconductors LPC178x 7x 7 15 7 15 1 7 15 1 1 7 15 2 7 15 2 1 LPC178X 7X 32 bit ARM Cortex M3 microcontroller Physical interface Attachment of external PHY chip through standard MII or RMII interface PHY register access is available via the MIIM interface USB interface Remark The USB Device Host OTG controller is available on parts LPC1788 87 86 85 and LPC1778 77 76 The USB Device only controller is available on parts LPC1774 The Universal Serial Bus USB is a 4 wire bus that supports communication between a host and one or more up to 127 peripherals The host controller allocates the USB bandwidth to attached devices through a token based protocol The bus supports hot plugging and dynamic configuration of the devices All transactions are initiated by the host controller Details on typical USB interfacing solutions can be found in Section 14 1 USB device controller The device controller enables 12 Mbit s data exchange with a USB host controller It consists of a register interface serial interface engine endpoint
168. t ARM Cortex M3 microcontroller 19 Revision history Table 35 Revision history Document ID Release date Data sheet status Change notice Supersedes LPC178X 7X v 5 3 20151016 Product data sheet LPC178X 7X v 5 2 Modifications e Corrected max value of tyo data output valid time SPI mode to 6 3 ns Was 3 ToypcLk 2 5 ns See Table 24 Dynamic characteristics SSP pins SPI mode LPC178X 7X v 5 2 20150818 Product data sheet LPC178X 7X v 5 1 Modifications Updated max value of tyo data output valid time in SPI mode to 2 5 ns See Table 24 Dynamic characteristics SSP pins in SPI mode Added a column for GPIO pins and device order part number to the ordering options table See Table 2 LPC178x 7x ordering options LPC178X 7X v 5 1 20140501 Product data sheet LPC178X 7X v 5 Modifications Updated parameter in Table 18 Dynamic characteristics Dynamic external memory interface read strategy bits RD bits 00 Minimum value changed to FBCLKDLY 1 x 0 25 0 3 Maximum value removed e Removed max value from parameter thp in Table 17 Removed min value from parameter tgeact in Table 17 Specified ADC conversion rate in burst mode in Table 29 12 bit ADC characteristics LPC178X 7X All information provided in this document is subject to legal disclaimers
169. tance filters 55 F atureS yc cece Rp 55 General purpose 32 bit timers external event COUNTES e 56 i xe 56 Pulse Width Modulator PWM 56 Fealutes essere ch RR 57 Motor control PWM 57 Quadrature Encoder Interface QEI 58 is 58 ARM Cortex M3 system tick timer 58 Windowed WatchDog Timer WWDT 59 Features s s en Ex em 59 RTC and backup registers 59 Feat fes ii2ll2eile cesa kr 59 Event monitor recorder 60 Feat fes osos se EE RE 60 Clocking and power control 60 Crystal oscillators 60 Internal RC oscillator 61 Main 5 61 RTC oscillator 62 Watchdog oscillator 62 Main PLL PLLO and Alternate PLL 1 62 Wake up timer 63 Power 63 Sleep mode 63 Deep sleep mode 64 Power down mode 64 Deep power down mode 65 Wake up Interrupt Controller WIC 65 Peripheral power control 65 Power domains 65 System 67
170. te and half word addressable Entire port value can be written in one instruction Support for Cortex M3 bit banding Support for use with the GPDMA controller Additionally any pin on Port 0 and Port 2 providing a digital function can be programmed to generate an interrupt on a rising edge a falling edge or both The edge detection is asynchronous so it may operate when clocks are not present such as during Power down mode Each enabled interrupt can be used to wake up the chip from Power down mode 7 17 1 Features Bit level set and clear registers allow a single instruction to set or clear any number of bits in one port Direction control of individual bits All I O default to inputs after reset Pull up pull down resistor configuration and open drain configuration can be programmed through the pin connect block for each GPIO pin 7 18 12 bit ADC The LPC178x 7x contain one ADC It is a single 12 bit successive approximation ADC with eight channels and DMA support 7 18 1 Features 12 bit successive approximation ADC Input multiplexing among eight pins Power down mode Measurement range Vss to VREFP 12 bit conversion rate up to 400 kHz Individual channels can be selected for conversion Burst conversion mode for single or multiple inputs Optional conversion on transition of input pin or Timer Match signal Individual result registers for each ADC channel to reduce interrupt overhead DMA support 7 19 10 bit
171. ters ARM Cortex M3 processor The ARM Cortex M3 is a general purpose 32 bit microprocessor which offers high performance and very low power consumption The ARM Cortex M3 offers many new features including a Thumb 2 instruction set low interrupt latency hardware division hardware single cycle multiply interruptable continuable multiple load and store instructions automatic state save and restore for interrupts tightly integrated interrupt controller with wake up interrupt controller and multiple core buses capable of simultaneous accesses Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously Typically while one instruction is being executed its successor is being decoded and a third instruction is being fetched from memory The ARM Cortex MS processor is described in detail in the Cortex M3 Technical Reference Manual that can be found on official ARM website On chip flash program memory The LPC178x 7x contain up to 512 kB of on chip flash program memory A new two port flash accelerator maximizes performance for use with the two fast AHB Lite buses EEPROM The LPC178x 7x contains up to 4032 byte of on chip byte erasable and byte programmable EEPROM data memory On chip SRAM The LPC178x 7x contain a total of up to 96 kB on chip static RAM data memory This includes the main 64 kB SRAM accessible by the CPU and DMA controller on a higher speed bus and up to tw
172. tex M3 microcontroller 14 Application information 14 4 Suggested USB interface solutions Remark The USB controller is available as a device Host OTG controller on parts LPC1788 87 86 85 and LPC1778 77 76 and as device only controller on parts LPC1774 USB UP LED USB CONNECT L A SoftConnect switch LPC17xx R1 1 5 VBus UsB D Ps 339 gt USB B Hor gt connector USB D S Vss 002aad939 Fig 30 USB interface on a self powered device Vpp 3v3 R2 LPC17xx R1 USB_UP_LED 1 5 kQ USB D Rs 332 USB B USB 5 33 0 Vss 002aad940 Fig 31 USB interface on a bus powered device LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 98 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Vpp R1 R2 R3 R4 RSTOUT RESET_N ADR PSW OE_N INT_N SPEED SUSPEND USB_SCL1 USB_SDA1 USB_INT1 USB_D 1 USB_D 1 VDD USB_UP_LED1 R7
173. the CPU to automatically wake up from any priority interrupt that can occur while the clocks are stopped in Deep sleep Power down and Deep power down modes Processor wake up from Power down mode via any interrupt able to operate during Power down mode includes external interrupts RTC interrupt 2 pin interrupt and NMI Brownout detect with separate threshold for interrupt and forced reset On chip Power On Reset POR Clock generation Clock output function that can reflect the main oscillator clock IRC clock RTC clock CPU clock USB clock or the watchdog timer clock On chip crystal oscillator with an operating range of 1 MHz to 25 MHz 12 MHz Internal RC oscillator IRC trimmed to 196 accuracy that can optionally be used as a system clock An on chip PLL allows CPU operation up to the maximum CPU rate without the need for a high frequency crystal May be run from the main oscillator or the internal RC oscillator A second dedicated PLL may be used for USB interface in order to allow added flexibility for the Main PLL settings W Versatile pin function selection feature allows many possibilities for using on chip peripheral functions W Unique device serial number for identification purposes Single 3 3 V power supply 2 4 V to 3 6 V Temperature range of 40 C to 85 C Available as LQFP208 TFBGA208 TFBGA180 and LQFP144 package 3 Applications Communica
174. tion lO 655 1 SCK Serial Clock for SSP1 T2 MAT1 Match output for Timer 2 channel 1 RTC EVO Event input 0 to Event Monitor Recorder R Function reserved R Function reserved LCD VD 9 LCD data LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 11 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Table 3 description continued Not all functions are available on all parts See Table 2 Ethernet USB LCD QEI SD MMC DAC pins and Table 7 EMC pins Symbol Description o a Rie ee 8 T 5 a r7 la l Jle E cil Vra um l 5 5 9 g m a a PO 8 160 A15 C12 111 4 IA PO 8 General purpose digital input output pin 125 TX WS 125 Transmit word select It is driven by the master and received by the slave Corresponds to the signal WS in the 2S bus specification lO SSP1 MISO Master In Slave Out for SSP1 T2 MAT2 Match output for Timer 2 channel 2 RTC EV1 Event input 1 to Event Monitor Recorder R Function reserved Function reserved LCD VD 16 LCD data PO 9 158 C14 A13 109 I O PO 9
175. tions Point of sale terminals web servers multi protocol bridges Industrial Medical Automation controllers application control robotics control HVAC PLC inverters circuit breakers medical scanning security monitoring motor drive video intercom W Consumer Appliance Audio decoders alarm systems displays printers scanners small appliances fitness equipment Automotive After market car alarms GPS fleet monitors LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 4 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller 4 Ordering information Table 1 Ordering information Type number Package Name Description Version LPC1788 LPC1788FBD208 LQFP208 plastic low profile quad flat package 208 leads body 28 x 28 x 1 4 mm SOT459 1 LPC1788FET208 TFBGA208 plastic thin fine pitch ball grid array package 208 balls body SOT950 1 15 15 0 7 mm LPC1788FET180 TFBGA180 thin fine pitch ball grid array package 180 balls body 12712 0 8 mm SOT570 3 LPC1788FBD144 LQFP144 plastic low profile quad flat package 144 leads body 20 x 20 x 1 4 mm SOT486 1 LPC1787 LPC1787FBD208 LQFP208 plastic low profile quad flat package 208 leads body 28 x
176. tiplexed functions IOCON register FUNC values which are reserved are noted as R in the pin configuration table All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 9 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Table3 Pin description Not all functions are available on all parts See Table 2 Ethernet USB LCD QEI SD MMC DAC pins and Table 7 EMC pins Symbol 69 Description co N T E ER lt lt Eh D O A 5 a e LL LL G l 5 9 g m a a c PO 0 to Port 0 Port 0 is a 32 bit I O port with individual direction PO 31 controls for each bit The operation of port 0 pins depends upon the pin function selected via the pin connect block PO 0 94 015 M10 66 BI PO 0 General purpose digital input output pin PU CAN RD1 CAN receiver input U3 TXD Transmitter output for UART3 lO I2C1 SDA 12 1 data input output this pin does not use a specialized 2 pad UO TXD Transmitter output for UARTO PO 1 96 T14 N11 67 B 1 General purpose digital input output pin PU Jo CAN TD1 transmitter output U3 RXD Receiver input for UART3 2 SCL I C1 clock input output this pin does not use
177. to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 26 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller Table 3 description continued Not all functions are available on all parts See Table 2 Ethernet USB LCD QEI SD MMC DAC pins and Table 7 EMC pins Symbol e Description i amp J 8 S je E S 3 49 amp 3 8 e P3 0 197 B4 06 137 0 General purpose digital input output pin U D 0 External memory data line 0 P3 1 201 B3 E6 140 B lO P3 1 General purpose digital input output pin PU EMC D 1 External memory data line 1 P3 2 207 B1 2 144 Bl lO P3 2 General purpose digital input output pin PU yo D 2 External memory data line 2 P3 3 3 E4 05 2 lO 3 General purpose digital input output pin PU yo EMC D 3 External memory data line 3 P3 4 13 F2 9 lO P3 4 General purpose digital input output pin PU D 4 External memory data line 4 P3 5 17 01 ES 12 I lO P3 5 General purpose digital input output pin PU D 5 External memory data line 5 P3 6 23 J FA 16 lO P3 6 General purpo
178. trobe valid CMDDLY 1 x CMDDLY 1 x CMDDLY 1 x ns delay time 0 25 4 6 0 25 6 5 0 25 4 9 6 h CAS column address strobe hold CMDDLY 1 x CMDDLY 1 x CMDDLY 1 x ns time 0 25 1 0 0 25 1 8 0 25 4 1 tawv write valid delay time CMDDLY 1 x CMDDLY 1 x CMDDLY 1 x ns 0 25 5 1 0 25 7 1 0 25 10 6 thw write hold time CMDDLY 1 x CMDDLY 1 x CMDDLY 1 x ns 0 25 1 4 0 25 2 4 0 25 4 9 la Av address valid delay time CMDDLY 1 x CMDDLY 1 x CMDDLY 1 x ns 0 25 5 1 0 25 7 2 0 25 10 6 th A address hold time CMDDLY 4 1 x CMDDLY 1 x CMDDLY 1 x ns 0 25 0 8 0 25 1 5 0 25 4 3 6 Read cycle parameters tsu D data input set up time FBCLKDLY 1 x FBCLKDLY 1 l ns 0 25 0 9 0 25 4 3 1 thio data input hold time BI FBCLKDLY 1 x FBCLKDLY 1 FBCLKDLY 1 x ins 0 25 3 7 0 25 4 3 0 25 5 2 Write cycle parameters taav data output valid delay time CMDDLY 1 x CMDDLY 1 x CMDDLY 1 x ns 0 25 5 1 0 25 7 4 0 25 10 8 tha data output hold time CMDDLY 1 x CMDDLY 1 x CMDDLY 1 x ns 0 25 0 02 0 25 0 6 0 25 2 3 1 2 Refers to SDRAM clock signal The data input set up time has to be selected with the following margin tsu p delay time of feedback clock SDRAM access time board delay time gt 0 3 The data input hold time has to be selected with the following margin inp SDRAM
179. ts 12 MHz IRC clock cycles to make the 100 us flash start up time When it times out access to the flash will be allowed Users need to reconfigure the PLL and clock dividers accordingly Deep power down mode In Deep power down mode power is shut off to the entire chip with the exception of the RTC module and the RESET pin To optimize power conservation the user has the additional option of turning off or retaining power to the 32 kHz oscillator It is also possible to use external circuitry to turn off power to the on chip regulator via the Vpp REGy ava pins and or the I O power via the Vpp ava pins after entering Deep Power down mode Power must be restored before device operation can be restarted The LPC178x 7x can wake up from Deep power down mode via the RESET pin or an alarm match event of the RTC Wake up Interrupt Controller WIC The WIC allows the CPU to automatically wake up from any enabled priority interrupt that can occur while the clocks are stopped in Deep sleep Power down and Deep power down modes The WIC works in connection with the Nested Vectored Interrupt Controller NVIC When the CPU enters Deep sleep Power down or Deep power down mode the NVIC sends a mask of the current interrupt situation to the WIC This mask includes all of the interrupts that are both enabled and of sufficient priority to be serviced immediately With this information the WIC simply notices when one of the interrupts has occurred
180. us Change notice Supersedes LPC178X 7X v 3 20111220 Objective data sheet LPC178X 7X v 2 Modifications Removed BOOT function from pin P3 14 and Ipp REGy ava updated for Deep power down mode in Table 13 Maximum SDRAM clock of 80 MHz specified in Section 2 Table 18 and Table 19 Power consumption data added Figure 9 and Figure 10 Removed parameter Zpgy Table 13 Specified maximum value for parameter C in Table 33 and remove typical value Specified setting of boost bits in Table 14 Table note 5 and in Table 13 Table note 6 USB connection diagrams updated Figure 33 to Figure 36 Current drain condition on battery supply specified in Section 7 33 6 Table note 10 in Table 13 updated ADC characteristics updated Table 31 Section 14 6 Reset pin configuration for RTC operation added EEPROM size for parts LPC1774 corrected in Table 2 and Figure 1 Changed function LCD VD 5 on pin PO 10 to Reserved Changed function LCD VD 10 on pin PO 11 to Reserved Changed function LCD VD 13 on pin PO 19 to Reserved Changed function LCD VD 14 on pin PO 20 to Reserved ADC interface model updated see Table 32 and Figure 30 LPC178X 7X v 2 20110527 Objective data sheet LPC178X 7X v 1 Modifications Symbol names in Table 3 to Table 5 abbreviated Reserved functions added in Table 3 Added function LCD VD 5 to pin PO 10 Added function LCD VD 10 to pin P
181. ut 4 01 DCD Data Carrier Detect input for UART1 P3 20 167 A13 PS 20 General purpose digital input output pin PU D 20 External memory data line 20 PWMO 5 Pulse Width Modulator 0 output 5 01 DSR Data Set Ready input for UART1 P3 21 175 C10 lO PS 21 General purpose digital input output pin PU yo EMC D 21 External memory data line 21 PWMO 6 Pulse Width Modulator 0 output 6 U1 DTR Data Terminal Ready output for UART1 Can also be configured to be an RS 485 EIA 485 output enable signal for UART1 P3 22 195 C6 lO PS 22 General purpose digital input output pin PU D 22 External memory data line 22 PWMO Capture input for PWMO channel 0 U1 RI Ring Indicator input for UART1 P3 23 65 T6 4 45 lO 23 General purpose digital input output pin PU uo D 23 External memory data line 23 1_ Capture input for PWM1 channel 0 TO_CAPO Capture input for Timer 0 channel 0 P3 24 58 R5 NS 40 B lO PS 24 General purpose digital input output pin PU wo D 24 External memory data line 24 PWM1 1 Pulse Width Modulator 1 output 1 TO CAP1 Capture input for Timer 0 channel 1 LPC178X 7X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights r
182. voke ISP command to enable flash update via UARTO All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 67 of 123 NXP Semiconductors LPC178x 7x 32 bit ARM Cortex M3 microcontroller CAUTION If level three Code Read Protection CRP3 is selected no future factory testing be performed on the device 7 34 4 7 34 5 7 34 6 7 34 7 7 35 LPC178X 7X APB interface The APB peripherals are split into two separate APB buses in order to distribute the bus bandwidth and thereby reducing stalls caused by contention between the CPU and the GPDMA controller AHB multilayer matrix The LPC178x 7x use an AHB multilayer matrix This matrix connects the instruction I code and data D code CPU buses of the ARM Cortex M3 to the flash memory the main 64 kB SRAM and the Boot ROM The GPDMA can also access all of these memories Additionally the matrix connects the CPU system bus and all of the DMA controllers to the various peripheral functions External interrupt inputs The LPC178x 7x include up to 30 edge sensitive interrupt inputs combined with one level sensitive external interrupt input as selectable pin function The external interrupt input can optionally be used to wake up the processor from Power down mode Memory mapping control The Cortex M3 incorporates a mec
183. wer saving modes dynamically control CKE outputs to SDRAMs Dynamic memory self refresh mode controlled by software Controller supports 2048 0 to A10 4096 0 to A11 and 8192 0 to A12 row address synchronous memory parts That is typical 512 MB 256 MB and 128 MB parts with 4 8 16 or 32 data bits per device Separate reset domains allow the for auto refresh through a chip reset if desired Note Synchronous static memory devices synchronous burst mode are not supported General purpose DMA controller The GPDMA is an AMBA AHB compliant peripheral allowing selected peripherals to have DMA support The GPDMA enables peripheral to memory memory to peripheral peripheral to peripheral and memory to memory transactions The source and destination areas can each be either a memory region or a peripheral and can be accessed through the AHB master The GPDMA controller allows data transfers between the various on chip SRAM areas and supports the SD MMC card interface all SSPs the 125 all UARTs the A D Converter and the D A Converter peripherals DMA can also be triggered by selected timer match conditions Memory to memory transfers and transfers to or from GPIO are supported All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 5 3 16 October 2015 46 of 123 NXP Semiconductors

LPC178x/7x - NXP Semiconductors

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