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DAQ Lab-PC-1200/AI Register-Level Programmer Manual

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1. RESET Reset input Input This signal is used to reset the control register and all internal registers when it is in high level At this time ports are all made into the input mode high impedance status all port latches are cleared to and all ports groups are set to mode Chip select Input When the CS is in low level data transmission is enabled with input CPU When it is in high level the data bus is made into the high impedance status where no write nor read operation is performed d Internal registers hold their previous status however Read input Input When RD is in low level data is transferred from MSM82C55A to CPU Write input Input When WR is in low level data or contro words are transferred from CPU to MSM82C55A Port select input address Input By combination of AO and A1 either one is selected from among port A port B port C and control register These pins are usually connected to low order 2 bits of the address bus 7 Port Input and These are universal 8 bit I O ports The direction of inputs out output puts can be determined by writing control word Especially port can be used as a bidirectional port when it is set to mode 2 PB7 PBO Port B Input and These are universal 8 bit I O ports The direction of inputs out output puts can be determined by writing a control word Input
2. 5 Tables 3 1 and 3 2 show the analog output voltage versus the input digital code in unipolar and bipolar mode respectively Table 3 2 Analog Output Voltage Versus Digital Code Unipolar Mode Straight Binary Coding Digital Code Decimal Hex Voltage Output 0 0000 ON 1 0001 2 4414 mV 2 048 0800 5 0V 4 095 OFFF 9 9976 V Table 3 3 Analog Output Voltage Versus Digital Code Bipolar Mode Two s Complement Coding Digital Code Decimal Hex Voltage Output 2 048 800 5 0 V 1 024 00 2 5 0 0000 0 0 V 1 024 0400 2 5 2 047 07FF 4 9976 V Programming the Update Mode of the Analog Output Circuitry Lab PC 1200 Al RLPM The analog output circuitry on the Lab PC 1200 AI uses double buffered DACs Therefore the output voltages DACOOUT and DACIOUT on the I O connector do not have to be updated immediately with each write to the DAC Data Registers You can update the analog output in 3 18 National Instruments Corporation Chapter 3 Programming synchronization with counter A2 or the external update timing signal EXTUPDATE This is useful for waveform generation applications because the timed update pulses eliminate the timing jitter associated with software writes to the DAC Data Registers You can operate the analog output circuitry in three ways immediate update update on OUTA2 or update on EXTUPDATE Use the following seque
3. Lab PC 1200 Al Register Level Programmer Manual Multifunction 1 0 Board for AT Bus Computers instruments December 1997 Edition Part Number 341309A 01 oftware is the Instrument Internet Support E mail support8natinst com FTP Site ftp natinst com Web Address http www natinst com Bulletin Board Support BBS United States 512 794 5422 BBS United Kingdom 01635 551422 BBS France 01 48 65 15 59 Fax on Demand Support 512 418 1111 Telephone Support USA Tel 512 795 8248 Fax 512 794 5678 International Offices Australia 03 9879 5166 Austria 0662 45 79 90 0 Belgium 02 757 00 20 Brazil 011 288 3336 Canada Ontario 905 785 0085 Canada Qu bec 514 694 8521 Denmark 45 76 26 00 Finland 09 725 725 11 France 01 48 14 24 24 Germany 089 741 31 30 Hong Kong 2645 3186 Israel 03 6120092 Italy 02 413001 Japan 03 5472 2970 Korea 02 596 7456 Mexico 5 520 2635 Netherlands 0348 433466 Norway 32 84 84 00 Singapore 2265886 Spain 91 640 0085 Sweden 08 730 49 70 Switzerland 056 200 51 51 Taiwan 02 377 1200 United Kingdom 01635 523545 National Instruments Corporate Headquarters 6504 Bridge Point Parkway Austin Texas 78730 5039 USA Tel 512 794 0100 Copyright 1997 National Instruments Corporation rights reserved Important Information Warranty Copyright Trademarks The Lab PC 1200 AI is warranted against defects in materials and workmanship for a period of one year from the date of
4. 4 3 Table 4 3 Lab PC 1200 AI EEPROM Map 4 11 Lab PC 1200 Al RLPM viii National Instruments Corporation About This Manual This manual contains information about the internal operation and programming of the Lab PC 1200 AI The Lab PC 1200 and Lab PC 1200AI boards are low cost multifunction analog digital and timing boards The Lab PC 1200 AI is a member of the National Instruments AT Series of expansion boards for AT ISA bus computers Additionally the Lab PC 1200 has two 12 bit DACS with voltage outputs These boards are designed for high performance data acquisition DAQ and control for applications in laboratory testing production testing and industrial process monitoring and control This manual assumes you are familiar with the Lab PC 1200 AI User Manual If you will be using National Instruments software with the Lab PC 1200 AI you do not need to read this manual For information on the Lab PC 1200 AI installation signal connections and theory of operation consult your user manual Organization of This Manual The Lab PC 1200 AI Register Level Programmer Manual is organized as follows e Chapter 1 General Description describes the general characteristics and gives a configuration overview of the Lab PC 1200 AI e Chapter 2 Register Map and Descriptions describes in detail the address and function of each of the Lab PC 1200 AI registers e Chapter 3 Programming contains programming instructions
5. 0 of group B 1 Mode 1 0 Output output of high order 1 Input 4 bits of port C Definition of input output of 8 bits of port A 0 Output 1 Input Control word identification flag Be sure to set 1 for the control 9 Mode definition of group word to define a mode and input Modeo output When set to O it becomes the control word for bit set reset Precaution for mode selection The output registers for ports and C are cleared to each time data is written in the command register and the mode is changed but the port B state is un defined 286 Lab PC 1200 Al RLPM D 10 Bit Set Reset Function When port C is defined as output port it is possible to set set output to 1 or reset set output to 0 any one of 8 bits without affecting other bits as shown next page National Instruments Corporation Don t Care L Control word identification flag Be sure to set to 0 for bit set reset When set to 1 it becomes the control word to define a mode and input output Interrupt Control Function When the MSM82C55A is used in mode 1 or mode 2 the interrupt signal for the CPU is provided The interrupt request signal is output from port C When the internal flip flop INTE is set beforehand at this time the desired interrupt request signal is output When it is reset beforehand however the interrupt request sig nal is not output The set r
6. 82C53 counting is down counting the counting being in steps of 2 in mode 3 Counter values can be read during counting by 1 direct reading and 2 counter latching read on the fly Direct reading Counter values can be read by direct reading opera tions Since the counter value read according to the timing of the RD and CLK signals is not guaranteed it is necessary to stop the counting by a gate input signal or to interrupt the clock input temporarily by an external circuit to ensure that the counter value is correctly read Counter latching In this method the counter value is latched by writing a counter latch command thereby enabling a stable value to be read without effecting the counting in any way at all An example of a counter latching program is given below Counter latching executed for counter 1 Read Load 2 byte setting MVIA 0100 Denotes counter latching OUT n3 Write in control word address n3 The counter value at this point is latched IN n1 Reading of the LSB of the counter value latched from counter 41 ni Counter 1 address BS Reading of MSB from counter MOV C A Lab PC 1200 Al RLPM O MSM82C53 2RS GS JS Example of Practical Application e 82 53 used as a 32 bit counter 82C53 2 Use counter 1 and counter 2 Counter 1 mode 0 upper order 16 bit counter value Counter 2 mode 2 lower order 16 bit counter value This setting en
7. SS wee eee ES Table 3 Data Conversion pc qeu o fosie e 1 vevezee o ee EUN pen por por 21 7 on 9 Tweete os por os 7 124 National Instruments Corporation 9 Lab PC 1200 Al RLPM Appendix Fujitsu 88341 88342 Data Sheet MB88341 MB88342 Figure 8 Cascade Connection Example 7 125 Lab PC 1200 Al RLPM 10 National Instruments Corporation Appendix Fujitsu MB88341 MB88342 Data Sheet MB88341 MB88342 APPLICATION DESCRIPTION The MB88341 and 88342 are suitable for electronic volumes and replacement for adjustment potentiometers in addition to normal D A converter applications Figure 8 illustrates an application example for TV set Figure 9 Application Example for TV Set DATA SO Video Color Control CLOCK Microcontroller SC TO Strobe Sound Control 7 126 National Instruments Corporation A 11 Lab PC 1200 Al RLPM Appendix Fujitsu MB88341 MB88342 Data Sheet MB88341 MB88342 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS f BE Ea E dua CHEN Operating Ambient Temperature Storage Temperature Permanent device damage may occur if the above ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet Exposure to absolu
8. 3 15 DAQ operation using internal timing 3 8 to 3 13 Counter AO and Counter BO 3 10 Counter A1 3 11 National Instruments Corporation Counter B1 and Interval Counter Register 3 11 to 3 12 servicing DAQ operation 3 12 to 3 13 triggering DAQ operation 3 12 digital I O circuitry 3 20 examples 3 2 to 3 3 general purpose counter timers 3 21 initializing Lab PC 1200 AI circuitry 3 3 to 3 4 Lab PC 1200 AI companion disk 3 2 Lab PC 1200 AI companion diskette 3 2 register programming considerations 3 1 PROMOUT bit description 2 19 reading from EEPROM 3 7 R registers See also specific register groups programming considerations 3 1 See also programming register map 2 2 to 2 3 resetting Lab PC 1200 AI circuitry 3 3 RSE NRSE bit analog input calibration 4 5 configuring analog input circuitry 3 6 description 2 16 S sample interval defined 3 8 scan interval defined 3 8 SCANEN bit configuring analog input circuitry 3 6 description 2 5 SCANUP bit configuring analog input circuitry 3 6 description 2 15 SCLK bit description 2 13 National Instruments Corporation Index reading single byte from EEPROM 3 4 storing user defined constants 4 2 writing bits to CALDAC 3 4 writing single byte to EEPROM 3 3 SDATA bit description 2 13 storing user defined constants 4 2 SE DIFF bit analog input calibration 4 5 configuring analog input circuitry 3 6 description 2 11 sin
9. 7 121 Lab PC 1200 Al RLPM A 6 National Instruments Corporation Appendix Fujitsu MB88341 MB88342 Data Sheet MB88341 MB88342 Figure 5 Shift Register Format Last In First In LSB DI e Eelere MSB DO 8 Data 4 bit Address To Data Latch To Address Latch Decoder Figure 6 Data Latch Address Map Data Latch 1 Data Latch 2 Data Latch 3 Data Latch 4 Data Latch 5 Data Latch 7 S Available on MB88341 only Data Latch 48 Data Latch 49 Data Latch 10 Data Latch 11 Data Latch 6 D A Converter 6 Data Latch 12 7 122 National Instruments Corporation A 7 Lab PC 1200 Al RLPM Appendix Fujitsu 88341 88342 Data Sheet MB88341 MB88342 Figure 7 R 2R Resistor Ladder D A Converter Configuration D a t a L a t 7 123 Lab PC 1200 Al RLPM A 8 National Instruments Corporation Appendix Fujitsu MB88341 MB88342 Data Sheet MB88341 MB88342 Table 2 Address Decoding fh EISE BARRERA R 7 ac be EE EEN R p gt 2 Fc e 7 3 3 3 3 0 9 eme ia
10. Lab PC 1200 Al RLPM 2 28 National Instruments Corporation Chapter 2 Register Map and Descriptions Timer Interrupt Clear Register Write to the Timer Interrupt Clear Register to clear the interrupt request asserted when a low pulse is detected on the counter A2 output or on EXTUPDATE line Address 0C hex Type Write only Word Size 8 bit Bit Map Not applicable no bits used Counter 0 Data Register Use the Counter BO Data Register to write data and read back the contents of 82 53 counter 0 Counter BO either supplies the time base clock for counter or is reserved for external usage Address 18 hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 DI DO Bit Name Description 7 0 D lt 7 0 gt Data 8 bit counter BO contents National Instruments Corporation 2 29 Lab PC 1200 Al RLPM Chapter 2 Register Map and Descriptions Counter B1 Data Register Use the Counter B1 Data Register to write data and read back the contents of 82C53 B counter 1 Counter Bl is either the interval timer for a DAQ operation or is reserved for external usage Address 19 hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 DI DO Bit Name Description 7 0 D lt 7 0 gt Data 8 bit counter B1 contents Counter B2 Data Register Use the Counter B2 Data Register t
11. Setthe HFINTEN bitin Command Register 6 to enable interrupt generation when the A D FIFO becomes half full 2 048 samples If HFINTEN is set an interrupt is generated whenever the FIFOHF bit is cleared in Status Register 2 Set the ERRINTEN bit in Command Register 3 to enable interrupt generation when an error condition is detected If ERRINTEN is set an interrupt is generated whenever either the OVERFLOW or OVERRUN bits are set in Status Register 1 Set the DQINTEN bit in Command Register 6 to enable interrupt generation when DAQ operation is terminated by counter A1 If DQINTEN is set an interrupt is generated whenever is set in Status Register 2 Set the TCINTEN bit in Command Register 3 to enable interrupt generation when a DMA TC is received If TCINTEN is set an interrupt is generated whenever DMA TC is set in Status Register 1 Lab PC 1200 Al RLPM 3 16 National Instruments Corporation Chapter 3 Programming DAQ DMA Programming You can program the Lab PC 1200 AI so that the FIFO generates a DMA request whenever one or more A D conversions are available in the FIFO To use DMA the AT DMA controller must be properly configured Perform the following steps to configure the board Configure the analog input circuitry Set the DMAEN bit in Command Register 3 3 Program the AT DMA controller 4 Trigger the operation H The controller automatically transfers data from the AI FIFO into
12. 25 C f 1 2 Voc 5V Symbol Test Max Units Conditions Cour Output Capacitance SO 8 pF Vout 0V Input SCK SI CS WP HOLD 6 pF VIN ON 3834 PGM 09 1 Notes 1 Vu min and max are for reference only and are not tested 2 This parameter is periodically sampled and not 100 tested 2 118 Lab PC 1200 Al RLPM Xicor X25020 Data Sheet Appendix Xicor X25020 Data Sheet X25020 EQUIVALENT A C LOAD CIRCUIT AT 5V Vcc A C TEST CONDITIONS E Input Pulse Levels Vccx0 1toVccx0 9 Input Rise and Fall Times 10ns 2 16 Input and Output Timing Level Vccx0 5 3834 PGM T10 OUTPUT 3 07KQ OOpF EH 3834 FHD F12 1 A C CHARACTERISTICS Over recommended operating conditions unless otherwise specified Data Input Timing Symbol Parameter Min Max Units fsck Clock Frequency 0 1 MHz tcvc Cycle Time 1000 ns Dean CS Lead Time 500 ns tL AG CS Lag Time 500 ns twH Clock HIGH Time 400 ns twL Clock LOW Time 400 ns 150 Data Setup Time 100 ns Data Hold Time 100 ns Data In Rise Time 2 us Va Data In Fall Time 2 us tup HOLD Setup Time 200 ns tcp HOLD Hold Time 200 ns tcs CS Deselect Time 500 ns Write Cycle Time 10 ms 3834 PGM T11 2 Data Output Timing Symbol Parameter Min Max Units fsck Clock Frequency 0 1 MHz
13. Write Enable Latch The X25020 contains a write enable latch This latch must be SET before a write operation will be completed internally The WREN instruction will set the latch and the WRDI instruction will reset the latch This latch is automatically reset upon a power up condition and after the completion of a byte page or status register write cycle Status Register The RDSR instruction provides access to the status register The status register may be read at any time even during a write cycle The status register is format ted as follows 16 5 2 gt 21110 x BP1 WL WP 3834 PGM T02 BPO and 1 are set by the WRSR instruction WEL and WIP are read only and automatically set by other operations The Write In Process WIP bit indicates whether the X25020 is busy with a write operation When settoa 1 a write is in progress when set to a 0 no write is in progress During a write all other bits are set to 1 The Write Enable Latch WEL bit indicates the status of the write enable latch When setto a 1 thelatch is set when set to a 0 the latch is reset The Block Protect BPO and BP1 bits are nonvolatile and allow the user to select one of four levels of protec tion The X25020 is divided into four 512 bit segments One two or all four of the segments may be protected That is the user may read the segments but will b
14. 137 00 0 Factory Gain 2 unipolar value offset 136 00 0 Factory Gain 5 unipolar value offset 135 00 0 Factory Gain 10 unipolar value offset 134 00 0 Factory Gain 20 unipolar value offset 133 00 0 Factory Gain 50 unipolar value offset 132 00 0 Factory Gain 100 unipolar value offset 131 00 0 Not used 130 00 0 Not used 129 00 0 Not used 128 00 0 Not used Lab PC 1200 Al RLPM 4 12 National Instruments Corporation Chapter 4 Calibration Table 4 3 Lab PC 1200 Al EEPROM Map Continued Location Hex Decimal Description 127 B3 179 Point to AI bipolar frame 126 A3 155 Point to AI unipolar frame 125 AF 175 Point to AO bipolar frame 124 9F 151 Point to AO unipolar frame 123 AB 171 Point to bipolar Gain frame 122 9B 147 Point to unipolar Gain frame 121 00 163 Point to bipolar offset frame 120 00 139 Point to unipolar offset frame 119 00 0 Not used 118 00 0 Not used 117 00 0 User 1 AI CALDACO value 116 00 0 User 1 AI CALDACI value 115 00 0 User 1 AI CALDAC2 value 114 00 0 User 1 AI CALDAC3 value 113 00 0 User 1 AO CALDAC4 value 112 00 0 User 1 AO CALDACS value 111 00 0 User 1 AO CALDAC6 value 110 00 0 User 1 AO CALDAC7 value 109 00 0 User 1 Gain 1 value gain 108 00 0 User 1 Gain 1 25 value gain 107 00 0 User 1 Gain 2 value gain 106 00 0 User 1 Gain 5 value gain 105 00 0 User 1 Gain 10 value gain 104 00 0 User 1 Gain 20 value gain 103 00 0
15. 3 Take 1 024 samples from channel 1 at a gain of 1 Take the mean and call it mean 4 Adjust CALDAC6 so that postgain offset tolerance Vref 10V 4 095 lt gain calibration Perform the calibration for gains not equal to 1 as you did for bipolar input Remember that the voltage reference V multiplied by the gain used should be less than 9 5 V Postgain Offset Calibration For postgain offset calibration use the following procedure 1 1 024 samples from channel 1 still connected to V at a gain of 1 Take the mean and call this mean 2 Adjust CALDACS so that Jl postgain calibration tolerance National Instruments Corporation 4 7 Lab PC 1200 Al RLPM Chapter 4 Calibration Analog Output Calibration Lab PC 1200 Only To null out error sources that affect the accuracy of the output voltages generated you must calibrate the analog output circuitry by adjusting the following potential sources of error e Analog output offset error e Analog output gain error Offset error in the analog output circuitry equals the total of the voltage offsets contributed by each component in the circuitry This error appears as a voltage difference between the desired voltage and the actual output voltage generated and is independent of the D A voltage setting To correct this offset error the routine sets the D A to 0 V and adjusts CALDAC7 or CALDACO for DACO or D
16. Byte Write Operation Sequence cs 01 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK INSTRUCTION BYTE ADDRESS DATA BYTE s AAA 0 000000000000000 HIGH IMPEDANCE SO 3834 FHD F14 1 2 116 National Instruments Corporation B 7 Lab PC 1200 Al RLPM Appendix Xicor X25020 Data Sheet X25020 Figure 5 Page Write Operation Sequence cs 0 1 2 3 4 5 6 7 8 9 10 t 12 13 14 15 16 17 18 19 20 21 22 23 SCK INSTRUCTION BYTE ADDRESS DATA BYTE 1 s cs 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK DATA BYTE 2 DATA BYTE 3 DATA BYTE 4 000000000000000000000000 3834 FHD 7 1 E Figure 6 Write Status Register Operation Sequence cs 0 12 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK INSTRUCTION DATA BYTE 5 Se d 6 5 d HIGH IMPEDANCE so 3834 ILL F15 1 2 117 Lab PC 1200 Al RLPM B 8 National Instruments Corporation National Instruments Corporation Appendix B X25020 ABSOLUTE MAXIMUM RATINGS Temperature under Bias 659 to 135 Storage Temperature 65 C to 150 Voltage on any Pin with Respectto Vss D C Output Current Lead Temperature Soldering 10 seconds RECOMMENDED OPERATING CONDITIONS COMMENT Stresses above those listed under Absolute Maximum Ratings m
17. L Input Voltage Hr Input Voltage DC CHARACTERISTICS Parameter Symbol Conditions L Output Voltage IOL 4mA 1 H Output Voltage Input Leak Current OLVIN Vcc 4 5 to 5 5V Output Leak Current 0S Vout Vcc 40 to 85 C CS 2 Vcc 0 2V Standby Supply Current VIH Vcc 02V Vit amp 0 2V Operating Supply Current 125 ns 0pF 255 Lab PC 1200 Al RLPM C 4 National Instruments Corporation Appendix C OKI MSM82C53 Data Sheet 1 0 MSM82C53 2RS GS JS AC CHARACTERISTICS Voc 4 5V 5 5V 40 85 C MSM82C53 2 Parameter in Conditions Address Set up Time before reading Address Hold Time after reading Read Pulse Width Read Recovery Time Address Set up Time before writing Address Hold Time after writing Write Pulse Width Data Input Set up Time before writing Data Input Hold Time after writing Write Recovery time Clock Cycle Time Clock H Pulse Width Clock LU Pulse Width Clock H Gate Pulse Width 1 L Gate Pulse Width timing Gate Input Set up Time before clock Gate Input Hold Time after clock Output Delay Time after reading Output Floating Delay Time after reading Output Delay Time after gate Output Delay Time after clock O
18. MB88342 PF MB88341 MB88342 16 LEAD PLASTIC FLAT PACKAGE Case No 16 02 010 0 25 400 008110 15 7 80 0 40 209 012 5 30 0 30 016 350 8 89 REF 1988 FUJITSU LIMITED F160055 4C Lab PC 1200 Al RLPM 20 089 2 25 SEATED HEIGHT 002 0 05 MIN STAND OFF 016 0 40 268 680 o 59 020 008 0 50 0 20 002 0 05 096 99100156 95 020 0 50 007 0 18 Dimensions in inches millimeters 7 135 National Instruments Corporation Appendix Fujitsu MB88341 MB88342 Data Sheet MB88341 MB88342 MB88342 PFV 20 LEAD PLASTIC FLAT PACKAGE Case No 20 03 049 008 004 SEATED HEIGHT n2184 256 004 1650 010 e AT 0041010 252 008 6 40 0 20 213 5 40 NOM 173 004 CT 4 40 0 10 a 0256 0047 22 2 ote 006 502015106 0 65 0 12 01 d 0227909 Details of 004 004 0 10 0 10 ISTAND L 230589 020 008 0 50 0 20 REF Dimensions in 1989 FUJITSU LIMITED 200125 22 This dimension does not include resin protrusion inches millimeters 7 136 National Instruments Corporation A 21 Lab PC 1200 Al RLPM Xicor X25020 Data Sheet This appendix contains the manufacturer data sheet for the X25020 SPI serial EEPROM manufactured by Xicor Inc This EEPROM is used on
19. 1200 Al RLPM 2 14 National Instruments Corporation Command Register 6 Chapter 2 Register Map and Descriptions Use Command Register 6 to enable A D interrupts and to configure the A D and D A circuitry Address OE hex Type Write only Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 SCANUP DQINTEN HFINTEN 0 DACIUNI BI DACOUNI BI ADCUNI BI RSE NRSE Bit Name Description 7 SCANUP Scan Up This bit selects the order in which the analog input channels are scanned Clear this bit to select down counting highest numbered channel scanned first Set this bit to select up counting channel 0 scanned first 6 DQINTEN DAQ Interrupt Enable This bit enables and disables the end of a DAQ operation interrupt Set this bit to generate an interrupt whenever the OUTA bit in Status Register 2 becomes set Service this interrupt by resetting counter 1 Clear this bit to disable interrupt generation 5 HFINTEN Half Full Interrupt Enable This bit enables and disables the FIFO half full interrupt Set this bit to generate an interrupt whenever the FIFOHF bit in Status Register 2 becomes cleared Service this interrupt by reading data from the FIFO Clear this bit to disable interrupt generation 4 0 Always leave this bit cleared 3 DACIUNI BI DACI Unipolar Bipolar This bit sets the analog voltage National Instruments Corporation output range for DACI Set this bit to configure DACI
20. 2 0 are sampled sequentially If you clear SCANEN a single analog channel specified by MA lt 2 0 gt is sampled during the entire DAQ operation In DIFF mode the number of analog inputs reduces to four The single ended input channels 0 and 1 pins 3 and 4 become differential input channel 0 The single ended input channels 2 and 3 pins 5 and 6 become differential input channel 2 There are no odd differential input channels 2 6 National Instruments Corporation Chapter 2 Register Map and Descriptions Command Register 2 Command Register 2 contains eight bits that control the Lab PC 1200 AI analog input trigger modes analog output update modes and the coding scheme of the DACs Address 01 hex Type Write only Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 LDACI LDACO 2SDACI 2SDACO TBSEL SWTRIG HWTRIG PRETRIG Bit Name Description 7 LDACI Load DACI This bit determines how DACI will be updated If you set this bit DACI updates its output at regular intervals as determined by counter A2 or the EXTUPDATE signal at the I O connector If you clear this bit the voltage output of DACI is immediately updated when data is loaded into the DACI High Byte Register 6 LDACO Load DACO This bit determines how will be updated If you set this bit DACO updates its output at regular intervals as determined by counter A2 or the EXTUPDATE signal at the I O connector If you
21. 2 SWTRIG Software Trigger This bitis a software trigger fora operation You can trigger a DAQ operation by setting this bit The terminal count signal of counter A1 or a cleared SWTRIG terminates a DAQ process 1 HWTRIG Hardware Trigger This bit enables or disables the posttrigger mode using the EXTTRIG signal at the connector If you set this bit you can use the signal to trigger a operation in place of SWTRIG process is terminated by a terminal count signal of counter A1 or by writing to the A D FIFO Clear Register You must clear PRETRIG to use this mode 0 PRETRIG Pretrigger This bit enables or disables the pretrigger mode using the EXTTRIG signal at the I O connector If you set this bit you can use the signal at the I O connector to terminate a DAQ operation by using counter 1 Data acquisition is terminated by a terminal count on 1 You must clear the HWTRIG to use this mode Lab PC 1200 Al RLPM 2 8 National Instruments Corporation Chapter 2 Register Map and Descriptions Command Register 3 The Command Register 3 contains four bits that enable and disable interrupts for a DAQ operation and for digital I O Address 02 hex Type Write only Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 0 0 FIFOINTEN ERRINTEN CNTINTEN TCINTEN DIOINTEN DMAEN Bit Name Description 7 6 0 Always leave these bits cleared 5 FIFOINT
22. 3 18 DAC interrupt programming 3 20 update mode of analog output circuitry 3 18 to 3 20 Analog Output Register Group DACH Low Byte DACO High Byte DACI Low Byte and DACI High Byte Registers bipolar output calibration procedure 4 0 DAC interrupt programming 3 19 description 2 25 programming update mode of analog output circuitry 3 19 to 3 20 unipolar output calibration procedure 4 10 overview 2 24 register map 2 2 analog output voltage versus digital code bipolar mode two s complement coding table 3 18 unipolar mode straight binary coding table 3 18 bipolar input calibration 4 5 to 4 6 gain calibration 4 6 higher gains 4 6 postgain offset calibration 4 6 pregain offset coarse calibration 4 5 pregain offset fine calibration 4 5 bipolar input polarity selecting 3 5 to 3 6 bipolar mode two s complement coding table 3 18 National Instruments Corporation bipolar output calibration 4 8 to 4 9 gain calibration 4 9 offset calibration 4 9 bipolar output polarity selecting 3 18 bits 2SDACO 2 7 to 2 8 2SDACI 2 7 ADCUNI BI 2 6 3 16 CALDACLD 2 13 3 4 CNTINT 2 17 3 20 CNTINTEN 2 9 3 19 3 20 CW lt 7 0 gt 2 34 D lt 7 0 gt A D FIFO Register 2 22 Counter AO Data Register 2 27 Counter Al Data Register 2 27 Counter A2 Data Register 2 28 Counter BO Data Register 2 29 Counter B1 Data Register 2 30 Counter B2 Data Register 2 30 DACO Low Byte DACO High Byte DAC
23. Calibration 1 Write a value V to DACO or DACI Choose a value of V between 3 and 4 5 V 2 Take 1 024 readings from analog input channel 2 still connected to DACOOUT or DACIOUT at a gain of 1 Take the mean and call it mean gain neg vref Write the value or DACI 4 Take 1024 readings from analog input channel 2 at a gain of 1 Take the mean and call it mean gain 5 Adjust CALDACS or CALDAC10 so that mean gain ref mean gain neg ref e 40951 gain calibration tolerance 5V Offset Calibration 1 Connect DACOOUT pin 10 or DAC1OUT 12 to analog input channel 2 pin 3 2 Write a 0 to or DACI 3 Take 1 024 readings from analog input channel 2 at a gain of 1 Take the mean and call it offset 4 Adjust CALDAC7 or CALDACO so that loffsetl offset calibration tolerance Unipolar Output Calibration Procedure If your board is configured for unipolar output which provides the 0 to 10 V range complete the following procedure This procedure assumes that DAC coding is in the 0 to 4 095 range that is you have selected the straight binary coding scheme Set analog input to bipolar mode for analog output unipolar offset calibration For gain calibration set the analog input mode to unipolar Initialize all of the CALDACS for analog output 7 10 to 128 before starting the gain calibration procedure This sets each CALDAC to mid scale N
24. Mode 0 WR D7 Do CS Ai Ao Port output Strobe Input Operation Mode 1 282 Lab PC 1200 Al RLPM D 6 National Instruments Corporation Appendix D OKI MSM82C55A Data Sheet y O MSMB82C55A 2RS GS VJS Strobe Output Operation Mode 1 INTR ACK Port output Bidirectional Bus Operation Mode 2 283 National Instruments Corporation D 7 Lab PC 1200 Al RLPM Appendix D OKI MSM82C55A Data Sheet O MSM82C55A 2RS GS VJS OUTPUT CHARACTERISTICS REFERENCE VALUE 1 Output H Voltage vs Output Current 40 85 C Vcc 5 0V gt gt 2 En 8 A 5 a 2 0 2 3 4 5 Output current mA 2 Output L Voltage VoL vs Output Current 191 Vec 5 0V 40 85 Output L voltage VoL V Output current Jo mA Note The direction of flowing into the device is taken as positive for the output current 284 Lab PC 1200 Al RLPM D 8 National Instruments Corporation Appendix D 1 0 MSM82C55A 2RS GS VJS FUNCTIONAL DESCRIPTION OF PIN 07 00 Bidirectional data bus Input and output Input Output Function These are three state 8 bit bidirectional buses used to write and read data upon receipt of the WR and RD signals from CPUand also used when control words and bit set reset data are trans ferred from CPU to MSM82C55A
25. ToP 40 85 o Operating Temperature L Input Voltage H Input Voltage DC CHARACTERISTICS MSM82C55A 2 Parameter Symbol Conditions D 1 Min Max L Output Voltage lot 2 5mA Ion 40 uA H Output Voltage 2 5 Vcc 4 5V to Input Leak Current TM 9 lt lt Vee SEN Output Leak Current 0 lt Vour 40 to gt mE 85 C CS 2 Vcc 02V js Vin 2 Vcc 0 2 E Vit S 02V L Average Supply wire cycie Current active 82C55A2 BMHzCPU timing Supply Current standby 280 Appendix D OKI MSM82C55A Data Sheet 0 MSMB82C55A 2RS GS VJS AC CHARACTERISTICS 45 to 5 5V 40 to 80 C MSMB2C55A 2 Parameter rks Min Max Rema Setup Time of address to the falling edge of RD Hold Time of address to the rising edge of RD RD Pulse Width Delay Time from the falling edge of RD to the output of defined data Delay Time from the rising edge of RD to the floating of data bus Time from the rising edge of RD or WR to the next falling edge of RD or WR Setup Time of address before the falling edge of WR Hold Time of address after the rising edge or WR WR Pulse Width Setup Time of bus data before the rising edge of WR Holt Time of bus da
26. User 1 Gain 50 value gain 102 00 0 User 1 Gain 100 value gain National Instruments Corporation 4 13 Lab PC 1200 Al RLPM Chapter 4 Calibration Table 4 3 Lab PC 1200 Al EEPROM Map Continued Location Hex Decimal Description 101 00 0 User 1 Gain 1 value offset 100 00 0 User 1 Gain 1 25 value offset 99 00 0 User 1 Gain 2 value offset 98 00 0 User 1 Gain 5 value offset 97 00 0 User 1 Gain 10 value offset 96 00 0 User 1 Gain 20 value offset 95 00 0 User 1 Gain 50 value offset 94 00 0 User 1 Gain 100 value offset 93 00 0 Not used 92 00 0 Not used 91 00 0 User 2 AI CALDACO value 90 00 0 User 2 AI CALDACI value 89 00 0 User 2 AI CALDAC2 value 88 00 0 User 2 AI CALDAC3 value 87 00 0 User 2 AO CALDAC4 value 86 00 0 User 2 AO CALDACS value 85 00 0 User 2 AO CALDAC6 value 84 00 0 User 2 AO CALDAC7 value 83 00 0 User 2 Gain 1 value gain 82 00 0 User 2 Gain 1 25 value gain 81 00 0 User 2 Gain 2 value gain 80 00 0 User 2 Gain 5 value gain 79 00 0 User 2 Gain 10 value gain 78 00 0 User 2 Gain 20 value gain 77 00 0 User 2 Gain 50 value gain 76 00 0 User 2 Gain 100 value gain Lab PC 1200 Al RLPM National Instruments Corporation Chapter 4 Calibration Table 4 3 Lab PC 1200 Al EEPROM Map Continued Location Hex Decimal D
27. and These are universal 8 bit I O ports The direction of inputs out output puts can be determined by writing a control word as 2 ports with 4 bits each When port A or port B is used in mode 1 or mode 2 port A only they become control pins Especially when port C is used as an output port each bit can be set reset independently 5 V power supply BASIC FUNCTIONAL DESCRIPTION Group A and Group B When setting a mode to a port having 24 bits set it by dividing it into two groups of 12 bits each When used in mode 1 or mode 2 however port C has bits to be defined as ports for contro signal for operation ports port A for group A and port B for group B of their respective groups Group A Port A 8 bits and high order 4 bits Port A B C of port C PC4 The internal structure of 3 ports is as follows Group B Port 8 bits and low order 4 bits of Port A One 8 bit data output latch buffer and port C PC3 PCO amp bit data input latch Port B One 8 bit data input output latch buf Mode 0 1 2 fer and one 8 bit data input buffer There are 3 types of modes to be set by grouping Port C One 8 bit data output latch buffer and as follows one amp bit data input buffer no latch Mode 0 Basic input operation output operation for input Available for both groups A and B Mode 1 Strobe input operation output opera Single bit set reset function for port tion When port C is defined a
28. board is configured for unipolar input which has an input range of 0 to 10 V complete the following steps This procedure assumes that your readings are in the 0 to 4 095 range that is you have selected the straight binary coding scheme In unipolar mode the offset can be negative and while doing offset adjustment all of the acquired samples can be 0 V This results in incorrect offset calibration To correct this problem initialize CALDACS to 0 to 4 6 National Instruments Corporation Chapter 4 Calibration create a maximum positive offset Initialize the other CALDACS 3 4 and 6 to 128 as before Pregain Offset Calibration Follow the same steps as in the Bipolar Input Calibration Procedure section for pregain offset coarse and pregain offset fine calibration Remember to configure the analog input for bipolar mode when performing pregain offset calibration Reconfigure the analog input for unipolar mode for gain and postgain offset calibration After the pregain offset calibration there will be a residual positive postgain offset remaining because the postgain CALDAC is biased to one extreme Gain Calibration For gain calibration use the following procedure 1 Take 1 024 samples from channel 0 still connected to AGND at a gain of 1 Take the mean and call it postgain offset 2 Connect the voltage reference M A between ACHT pin 2 and AGND pin 11 Choose a voltage reference between 8 0 and 9 5 V
29. buffer in system memory when properly configured Programming the Analog Output Circuitry Lab PC 1200 Only This section explains how to configure the analog output circuitry and how to update the analog output voltage Configuring the Analog Output Circuitry You must configure the analog output circuitry after initializing the Lab PC 1200 AI and anytime the characteristics of the analog output signals change Program the appropriate register bits as follows 1 Select the output polarity unipolar or bipolar and the coding of the digital code straight binary or two s complement 2 Set or clear the DACIUNI BI and DACOUNI BI bits in Command Register 6 and the 2SDAC1 and 2SDACO bits in Command Register 2 If you select a unipolar output polarity the straight binary coding is recommended If you select a bipolar output polarity the two s complement coding is recommended Use the following formula to calculate the output voltage versus digital code for a unipolar analog output configuration and straight binary coding The digital code is a decimal value ranging from 0 to 4 095 Code Vout 10 0 2 096 National Instruments Corporation 3 17 Lab PC 1200 Al RLPM Chapter 3 Programming The following formula calculates the output voltage versus digital code for a bipolar analog output configuration and two s complement coding The digital code is a decimal value ranging from 2 048 to 2 047 Code 2 048
30. data you must set these pointers to point to the appropriate user area Notice that if you point the AI bipolar frame to user area 1 you must also point the corresponding gain and offset pointers to the user area 1 gain and offset frames respectively CFP Note NI DAQ uses these pointers to load a set of calibration constants into the CALDAC each time you run a function pertaining to the Lab PC 1200 AI Hence if you use NI DAQ along with your register level code you must assign these pointers correctly or NI DAQ will load incorrect values into the CALDACs Lab PC 1200 Al RLPM 4 10 National Instruments Corporation Chapter 4 Calibration Table 4 3 Lab PC 1200 Al EEPROM Location Hex Decimal Description 179 00 0 Factory AI CALDACO bipolar value 178 00 0 Factory AI CALDACI bipolar value 177 00 0 Factory AI CALDAC2 bipolar value 176 00 0 Factory AI CALDAC3 bipolar value 175 00 0 Factory AO CALDACA bipolar value 174 00 0 Factory AO CALDACS bipolar value 173 00 0 Factory AO CALDAC6 bipolar value 172 00 0 Factory AO CALDACT bipolar value 171 00 0 Factory Gain 1 bipolar value gain 170 00 0 Factory Gain 1 25 bipolar value gain 169 00 0 Factory Gain 2 bipolar value gain 168 00 0 Factory Gain 5 bipolar value gain 167 00 0 Factory Gain 10 bipolar value gain 166 00 0 Factory Gain 20 bipolar value gain 165 00 0 Factory Gain 50 bipolar value gain 164 00 0 Fact
31. for operating the Lab PC 1200 AI circuitry and examples of the programming steps necessary to execute an operation e Chapter 4 Calibration contains instructions for creating user defined calibration constants for the Lab PC 1200 AI CALDACSs e Appendix A Fujitsu MB88341 MB688342 Data Sheet contains the manufacturer data sheet for MB88341 MB88342 R 2R type 8 bit D A converter manufactured by Fujitsu Microelectronics Inc The 88341 D A converter is used on the Lab PC 1200 AI e Appendix B Xicor X25020 Data Sheet contains the manufacturer data sheet for the X25020 SPI serial EEPROM manufactured by Xicor Inc This EEPROM is used on the Lab PC 1200 AI National Instruments Corporation ix Lab PC 1200 AI RLPM About This Manual e Appendix C OKI MSM82C53 Data Sheet contains the manufacturer data sheet for the 5 82 53 CMOS programmable interval timer manufactured by OKI Semiconductor Inc This counter timer is used on the Lab PC 1200 AI e Appendix D OKI MSM62C55A Data Sheet contains the manufacturer data sheet for the MSM82C55A CMOS programmable peripheral interface manufactured by OKI Semiconductor Inc This interface is used on the Lab PC 1200 AI e Appendix E Customer Communication contains a form you can use to comment on the product documentation This appendix also contains information on how to access technical assistance for your National Instruments product Glossary contains an alphabe
32. illustrated in Appendix D OKT 8 82 55 Data Sheet Examples for using the digital I O circuitry in the Lab PC 1200 AI User Manual You can generate interrupts through PCO and PC3 on the I O connector Enable digital I O interrupts by setting the DIOINTEN bit in Command Register 3 There are no status bits associated with the digital I O interrupts You clear this interrupt by clearing PCO and PC3 Lab PC 1200 Al RLPM 3 20 National Instruments Corporation Chapter 3 Programming Programming the General Purpose Counter Timers You can use Counter Timer Group B of the 82C53 timing circuitry as general purpose counters when they are not being used for internal timing To program the general purpose counters set the mode of the 82C53 by writing to the Counter B Mode Register then write and read from the three data registers counter BO counter B1 and counter B2 See Appendix C OKI MSM82C53 Data Sheet for information on the various modes of the 82C53 Examples for using the general purpose counters are given in the Lab PC 1200 AI User Manual You cannot generate interrupts with the general purpose counter timers National Instruments Corporation 3 21 Lab PC 1200 Al RLPM Calibration This chapter contains instructions for creating user defined calibration constants for the Lab PC 1200 AI CALDACS This information is important if you do not want to use NI DAQ to create user defined calibration constants to be
33. in Command Register 2 and then writing to the A D FIFO Clear Register After writing to the A D FIFO Clear Register any remaining data in the FIFO will have been cleared 3 14 National Instruments Corporation Chapter 3 Programming Programming a DAQ Operation Using EXTTRIG in Pretrigger Mode If you want to use in a pretrigger mode you must trigger the DAQ operation using SWTRIG and you must program counter A1 as described in Programming a DAQ Operation Using Internal Timing However the number of samples that you want to occur after the EXTTRIG trigger is equal to N 1 where N is the programmed count in counter 1 The number of samples that can occur after the EXTTRIG trigger ranges from 3 to 65 536 Use the following sequence to use EXTTRIG in a pretrigger mode 1 During configuration of the analog input circuitry set the PRETRIG bit in Command Register 2 2 Clearthe analog input circuitry program the appropriate counters and trigger the DAQ operation as described in Programming a DAQ Operation Using Internal Timing 3 Gate on counter A1 with a low to high transition on EXTTRIG The first rising edge on EXTTRIG should occur after you trigger the operation using SWTRIG This rising edge gates on counter 1 The operation stops after the programmed count in counter A1 has expired Programming a DAQ Operation Using OUTB1 If you want to drive your own interval scanning pulse on OUTBI inste
34. in laboratory testing production testing and industrial process monitoring and control You can use the TTL compatible digital I O lines for switching external devices such as transistors and solid state relays for reading the status of external digital logic and for generating interrupts You can use the counter timers to synchronize events generate pulses and measure frequency and time The Lab PC 1200 AI used in conjunction with the computer is a versatile cost effective platform for laboratory test measurement and control This manual is intended for programming at the register level Even if you are an experienced register level programmer consider using NI DAQ or other National Instruments application software to program the Lab PC 1200 AI If NI DAQ does not support your operating system or you have other reasons to write your own register level programs continue reading this manual National Instruments Corporation 1 1 Lab PC 1200 Al RLPM Chapter 1 General Description Board Configuration Overview This section is a reference to the Lab PC 1200 AI configuration options You should already have unpacked and installed your Lab PC 1200 AI Refer to your Lab PC 1200 AI User Manual if you have not already performed these tasks Analog Input Configuration The Lab PC 1200 AI is completely software configurable and at startup defaults to the following configuration e Referenced single ended input mode e 5 a
35. low level at the rising edge of RD INTR Interrupt request output This is the interrupt request signal for the CPU of the data fetched into the input latch It is in dicated by high level only when the internal INTE flip flop is set This signal turns to high level at the rising edge of the STB IBF 1 at this time Mode 1 Input Group A Note Although belonging to group B PC operates as the control signal of group A functionally 288 Lab PC 1200 Al RLPM D 12 and low level at the falling edge of the RD when the INTE is set INTE A of group A is set when the bit for PC is set while INTEg of group B is set when the bit for is set Following is a description of the output opera tion of mode 1 OBF Output buffer full flag output This signal when turned to low level indicates that data is written to the specified port upon receipt of the WR signal from the CPU This sig nal turns to low level at the rising edge of the WR and high level at the falling edge of the ACK ACK Acknowledge input This signal when turned to low level indicates that the terminal has received data INTR Interrupt request output Thisis the signal used to interrupt the CPU when a terminal receives data from the CPU via the MSMB82C554A 5 It indicates the occurrence of the interrupt in high level only when the inter nal INTE flip flop is set This signal turns to high level at the rising edge of the OBF 1 at t
36. products and manuals We are interested in the applications you develop with our products and we want to help if you have problems with them To make it easy for you to contact us this manual contains a comment form for you to complete This form is in Appendix E Customer Communication at the end of this manual Xii National Instruments Corporation General Description This chapter describes the general characteristics and gives a configuration overview of the Lab PC 1200 AI General Characteristics Thank you for purchasing the Lab PC 1200 AI low cost high performance multifunction analog digital and timing boards for AT ISA bus computers The Lab PC 1200 AI boards have eight analog input channels that you can configure as eight single ended or four differential inputs a 12 bit successive approximation ADC two 12 bit DACS with voltage outputs 24 lines of TTL compatible digital I O and three 16 bit counter timers for timing I O Additionally the Lab PC 1200 has two 12 bit DACs with voltage outputs The Lab PC 1200 AI is a member of the National Instruments AT Series of expansion boards for AT ISA bus computers The 1200 Series boards are completely switchless and jumperless DAQ boards This allows DMA interrupts and base I O addresses to be assigned by your system to avoid resource conflicts with other boards in your system These boards are designed for high performance data acquisition and control for applications
37. sta tus until then IBF Input buffer full flag output This signal when turned to high level indicates that data from the pin has been fetched into the input latch This signal turns to high level at the falling edge of the STB and low level at the ris ing edge of the RD INTR Interrupt request output This signal is used to interrupt the CPU and its operation in the same as in mode 1 There are two INTE flip flops internally available for input and output to select either interrupt of input or output operation The 1 is used to control the interrupt request for output operation and it can be reset by the bit set for PC6 INTE2 is used to control the interrupt request for the in put operation and it can be set by the bit set for 4 National Instruments Corporation Appendix D OKI MSM82C55A Data Sheet 1 O MSM82C55A 2RS GS VJS Mode 2 1 0 Operation Port C Function Allocation in Mode 2 Confirmed to the group B mode INTRA STBA IBFA Following is an example of the relation between the control word and the pin when used in mode 2 When input in mode 2 for group A and in mode 1 for group B As all of 8 bits of port C be control pins in this case D3 and DO bits are treated as Don t Care When group A is set to mode 2 this bit is treater Don t rested aci Do d No UO specification is required for mode 2 since it is a bidirec tional operation Th
38. the MB88341 88342 device is composed by the digital block MCU interface and analog block D A converter The digital block consists of a 12 bit shift register a 4 bit address latch decoder and 12 8 8 bit data latches The analog block includes 12 B 8 bit D A converters connecting to the data latches For electrically stable operation the power supply and ground lines are separate between the digital block for MCU interface and analog block for D A converter DEVICE OPERATION Figure 4 shows the input output timing 12 bit address data is serially input into the shift register through the DI pin synchronously with the rising edge of CLK The format of the shift register is shown in Figure 5 The lower 8 bits D7 to DO are data bits to be converted and the upper 4 bits are address bits D11 to D8 to selecta data latch to be written A high level on the LD pin loads the address tatch decoder with the 4 bit address to select a data latch and writes the 8 bit data into a selected data latch Figure 6 shows the data latch address map and Table 2 address decoding 8 bit data written into individual data latches are converted into analog DC voltages dividing the supply voltage Voo Vss through R 2R resistor ladders of D A converters Figure 7 shows the R 2R resistor ladder D A converter configuration and Table 3 analog DC voltages corresponding to each digital data Figure 4 Input Output Timing AOx Previous Data X New Data
39. the channels as described before with each write to the Start Convert Register You obtain A D conversion results by reading the A D FIFO Register First you must read the status registers to determine the state of the A D FIFO The useful status bits are OVERRUN OVERFLOW and DAVAIL in Status Register 1 and FIFOHF in Status Register 2 The DAVAIL bit will be set if there is at least one conversion result stored in the A D FIFO The DAVAIL bit should become set within a maximum of 12 us after you initiate an A D conversion If DAVAIL is set you can follow the Status Register read by reading the A D FIFO If the FIFOHF bit is cleared you can follow the Status Register read with 4 096 consecutive readings of the A D FIFO This corresponds to 2 048 samples since each sample requires two readings of the A D FIFO If either the OVERFLOW or the OVERRUN bit is set an error has occurred You have either lost at least one conversion by overflowing the A D FIFO or you have attempted to initiate a conversion before the previous one has completed You must read the A D FIFO twice to obtain the result The first reading returns the low byte of the 16 bit data and the second reading returns the high byte Reading the A D FIFO removes the A D conversion result from the A D FIFO If the DAVAIL bit is cleared then the A D FIFO is empty and further reading of the A D FIFO returns meaningless data National Instruments Corporation 3 7 Lab PC 1200 Al RL
40. there is no inter ruption until the terminal count is reached even if the gate input is switched to L level in the mean time And although counting continues even if a new count value is written during the counting counting is started at the new count value if another trigger is applied by the gate input Mode 2 rate generator The counter output is switched to level by the mode setting When the gate input is at H level counting is started by the next clock after the count value has been written And if the gate input is at L level counting is started by using the rising edge of the gate input as a trigger after the count value has been set An L level output pulse appears at the counter output during a single clock duration once every n clock inputs where n is the set count value If a new count value is written during while counting is in progress counting is started at the new count value following output of the pulse currently being counted And if the gate input is switched to L level during counting the counter output is forced to switch to H level the counting being restarted by the rising edge of the gate input Mode 3 square waveform rate generator The counter output is switched to H level by the mode setting Counting is started in the same way as described for mode 2 above The repeated square wave output appearing at the counter output contains half the number of co
41. tois Output Disable Time 500 ns ty Output Valid from Clock LOW 360 ns tHO Output Hold Time 0 ns ino Output Rise Time 300 ns Teo Output Fall Time 300 ns ttz HOLD HIGH to Output in Low Z 100 ns tuz HOLD LOW to Output in High Z 100 ns 3834 PGM T12 1 Notes 3 twc is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self timed internal nonvolatile write cycle 2 119 Lab PC 1200 Al RLPM B 10 National Instruments Corporation Appendix Xicor X25020 Data Sheet X25020 Serial Output Timing cs SCK ipis so MSBOUT Y MSB 1 OUT nou s CE n SS 7777722224 TET 3834 FHD F09 1 Serial Input Timing SCK Ki in KAX AXX cse XXXX VVYVVNW VV VV V XXXXXX ween XXX EI HIGH IMPEDANCE SO 3834 FHD F10 2 120 National Instruments Corporation 11 Lab PC 1200 Al RLPM Appendix Xicor X25020 Data Sheet X25020 Hold Timing cs SCK 50 SI HOLD 3834 FHD F11 SYMBOL TABLE WAVEFORM INPUTS OUTPUTS Must be Will be Steady steady Maychange Will change D from LOW from LOW to HIGH to HIGH May change Will change UN from from HIGH to LOW to LOW Don t Care Changing Changes State Not Allowed Known N A Center Line DK is High Impedance 2 121 Lab PC 1200 Al RLPM B 12 National Instruments Corporation Appendix Xicor X25020 D
42. 00 0 User 4 AI CALDACO value 38 00 0 User 4 AI CALDACI value 37 00 0 User 4 AI CALDAC2 value 36 00 0 User 4 AI CALDAC3 value 35 00 0 User 4 AO CALDACA value 34 00 0 User 4 AO CALDACS value 33 00 0 User 4 AO CALDAC6 value 32 00 0 User 4 AO CALDAC7 value 31 00 0 User 4 Gain 1 value gain 30 00 0 User 4 Gain 1 25 value gain 29 00 0 User 4 Gain 2 value gain 28 00 0 User 4 Gain 5 value gain 27 00 0 User 4 Gain 10 value gain 26 00 0 User 4 Gain 20 value gain 25 00 0 User 4 Gain 50 value gain 24 00 0 User 4 Gain 100 value gain Lab PC 1200 Al RLPM National Instruments Corporation Chapter 4 Calibration Table 4 3 Lab PC 1200 Al EEPROM Map Continued Location Hex Decimal Description 23 00 0 User 4 Gain 1 value offset 22 00 0 User 4 Gain 1 25 value offset 21 00 0 User 4 Gain 2 value offset 20 00 0 User 4 Gain 5 value offset 19 00 0 User 4 Gain 10 value offset 18 00 0 User 4 Gain 20 value offset 17 00 0 User 4 Gain 50 value offset 16 00 0 User 4 Gain 100 value offset 15 00 0 Not used 14 00 0 Not used 13 00 0 Not used 12 00 0 Not used 11 00 0 Not used 10 00 0 Not used 9 00 0 Not used 8 00 0 Not used 7 00 0 Not used 6 00 0 Not used 5 00 0 Not used 4 00 0 Not used 3 00 0 Not used 2 00 0 Not used 1 00 0 Not used 0 00 0 Not used National Instruments Corporation Lab PC 1200 Al RLPM Fujitsu MB88341 MB88342 Data She
43. 1200 AI that are used for calibration These DACS are described in Tables 4 1 and 4 2 for analog input and output calibration respectively The tolerance in both tables is simply the adjustment range divided by 255 8 bit In Table 4 1 V refers to the reference voltage value that you provide during the gain calibration procedure In Table 4 2 V refers to the voltage that you write to either DACO or DACI during the gain calibration procedure Table 4 1 Calibration DAC Characteristics for Analog Input Circuitry DAC Name Function Adjustment Range Tolerance CALDAC3 Pregain offset coarse 820 LSBs gain 100 3 2 LSBs CALDAC4 Pregain offset fine 8 LSBs gain 100 0 04 LSBs 5 Postgain offset 82 LSBs 0 32 LSBs CALDAC6 Gain 2 of 0 008 of Table 4 2 Calibration DAC Characteristics for Analog Output Circuitry DAC Name Function Adjustment Range Tolerance CALDAC7 Offset DACO 31 LSBs 0 12 LSBs CALDAC8 Gain DACO 2 of Vy or 0 008 of Ma CALDAC9 Offset DAC1 31 LSBs 0 12 LSBs CALDAC10 Gain DACI 2 of 0 008 of National Instruments Corporation 4 3 Lab PC 1200 Al RLPM Chapter 4 Calibration Analog Input Calibration Lab PC 1200 Al RLPM To null out error sources you must calibrate the analog input circuitry by adjusting the following potential sources of error not necessarily in this order e Offset error at the inpu
44. 2 National Instruments Corporation Chapter 2 Register Map and Descriptions A D FIFO Clear Register Write to this register to reset the ADC FIFO This operation clears the FIFO clears the DAVAIL bit and sets the FIFOHF bit All error bits in Status Register are cleared Address 08 hex Type Write only Word Size 8 bit Bit Map Not applicable no bits used Start Convert Register Write to the Start Convert Register to initiate a single A D conversion Address 03 hex Type Write only Word Size 8 bit Bit Map Not applicable no bits used DMATC Interrupt Clear Register Writing to the DMA Terminal Count DMATC Clear Register clears the interrupt request asserted when a DMA terminal count pulse is detected Address OA hex Type Write only Word Size 8 bit Bit Map Not applicable no bits used National Instruments Corporation 2 23 Lab PC 1200 Al RLPM Chapter 2 Register Map and Descriptions Analog Output Register Group Lab PC 1200 Only Use the four registers of the Analog Output Register Group to load the two 12 bit DACs DACO controls analog output channel 0 DACI controls analog output channel 1 Write to these DACS individually Bit descriptions of the registers making up the Analog Output Register Group are on the following pages i Note DACx represents DACH and DACI registers LDACx represents LDACO and LDACI bits Lab PC 1200 Al RLPM 2 24 National Instruments Corporatio
45. 2 5 GATAO bit 2 17 GATBO signal 3 9 GATBI signal 3 9 general purpose counter timers programming 3 21 H HFINTEN bit National Instruments Corporation I 7 Index DAQ interrupt programming 3 16 description 2 15 HWTRIG bit clearing analog input circuitry 3 5 description 2 8 programming DAQ operation 3 14 initializing Lab PC 1200 AI circuitry 3 3 to 3 4 input mode selecting 3 5 input polarity selecting 3 5 to 3 6 interrupts DAC interrupt programming 3 20 DAQ interrupt programming 3 16 Interval Counter Register Group DAQ operation using internal timing 3 8 to 3 9 Interval Counter Data Register 2 36 Interval Counter Strobe Register 2 36 overview 2 35 programming 3 11 to 3 12 register map 2 3 interval scanning acquisition mode 3 8 to 3 9 INTSCAN bit DAQ operations using OUTBI 3 15 description 2 12 programming Counter B1 3 12 L Lab PC 1200 AI assigning resources 3 2 companion disk 3 2 general characteristics 1 1 initializing circuitry 3 3 to 3 4 LDACO bit description 2 7 programming update mode of analog output circuitry 3 19 Lab PC 1200 Al RLPM Index LDACI bit description 2 7 programming update mode of analog output circuitry 3 19 lt 2 0 gt bits configuring analog input circuitry 3 6 description 2 6 manual See documentation 0 OKI 5 82 53 data sheet C 1 OKI 5 82 55 data sheet D 1 OUTAO signal performing single A D conversio
46. 2 Data Register description 2 28 programming update mode of analog output circuitry 3 19 Counter B Mode Register 2 31 Counter BO Data Register DAQ operations using internal timing 3 9 description 2 29 programming 3 10 Counter B1 Data Register DAQ operations using internal timing 3 8 to 3 9 description 2 30 programming 3 11 to 3 12 Counter B2 Data Register 2 30 National Instruments Corporation 1 5 counter timers See 82 53 Counter Timer Register Groups and B 82C55A Digital I O Register Group customer communication xii E 1 to E 2 CW lt 7 0 gt bits 2 34 D D 7 0 bits A D FIFO Register 2 22 Counter 0 Data Register 2 27 Counter A1 Data Register 2 27 Counter A2 Data Register 2 28 Counter Data Register 2 29 Counter B1 Data Register 2 30 Counter B2 Data Register 2 30 DACO Low Byte DACO High Byte DAC1 Low Byte and DACI High Byte Registers 2 25 Interval Counter Data Register 2 36 Port A Register 2 33 Port B Register 2 33 Port C Register 2 34 D 11 8 bits A D FIFO Register 2 21 to 2 22 DACO Low Byte DACO High Byte DAC1 Low Byte and DACI High Byte Registers 2 25 D lt 15 8 gt bits 2 22 D lt 15 12 gt bits 2 25 DAC interrupt programming 3 20 DACO Low Byte DACO High Byte DACI Low Byte and DACI High Byte Registers bipolar output calibration procedure 4 9 DAC interrupt programming 3 20 description 2 25 programming update mode of analog output circuit
47. 2 PF e Conversion method R 2R resistor ladder MB88341 8 bit x 12 channel D A converter MB88342 8 bit x 8 D A converter Serial data input Serial data output for cascade connection PLASTIC SOP PLASTIC SOP FPT 20P M01 FPT 16P M02 60 ps DAC output settling time Two separate power supply ground lines for digital and analog blocks MB88341 PFV MB88342 PFV Single 45V power supply Wide operating temperature range 20 C to 485 C gt Silicon gate CMOS process e Three package options MB88341 20 pin plastic DIP Suffix 20 plastic SOP Suffix PF PLASTIC SSOP 20 pin plastic SSOP Suffix PFV FPT 20P M03 88342 16 pin plastic DIP Suffix P 16 plastic SOP Suffix PF 20 plastic SSOP Suffix PFV This eves contains crutty o protect he E to to high static voltages or electi However is advised that te any vokage higher than maximum rated voltages to this high impedance circuit Copyright 1989 FUJITSU LIMITED 7 117 Lab PC 1200 Al RLPM A 2 National Instruments Corporation 88341 MB88342 Appendix A Fujitsu MB88341 MB88342 Data Sheet SSS 7 118 Figure 1 Pin Assignment MB88341 P MB88341 PF MB88341 PFV Top View Top View 6 6 6 Top View 88342 MB88342 PFV 13 Top View Top View 12 5 1 Top View National Instruments Corporation 3 Lab P
48. 4 to select the analog input mode and to allow certain signals to be externally driven at the I O connector Use Command Register 5 for software calibration of the A D circuitry Use Command Register 6 to enable and disable interrupt operations and to configure the A D and D A circuitry Status Register 1 reports the status of a DAQ operation and the status of analog output during waveform generation Status Register 2 reports the status of a DAQ operation and gives access to the output of the EEPROM Upon power up all of the Command Registers are cleared Bit descriptions for the registers in the Configuration and Status Register Group are on the following pages Lab PC 1200 Al RLPM 2 4 National Instruments Corporation Chapter 2 Register Map and Descriptions Command Register 1 Use Command Register 1 to select the input channel you want to scan the gain for the analog input circuitry the DAQ scanning mode and the coding used for the output of the ADC Address 00 hex Type Write only Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 GAIN2 GAINI GAINO TWOSCMP MA2 MAI Bit Name Description 7 SCANEN Scan Enable This bit enables or disables multiple channel scanning during data acquisition Set this bit to scan the analog channels as specified by lt 2 0 gt and SE DIFF bit 3 of Command Register 4 Clear this bit to sample
49. 5 to 4 6 unipolar input calibration procedure 4 6 to 4 7 analog output calibration 4 8 to 4 10 bipolar output calibration procedure 4 8 to 4 9 unipolar output calibration procedure 4 9 to 4 10 calibration DACs CALDACSs 4 3 analog input circuitry characteristics table 4 3 analog output circuitry characteristics table 4 3 writing calibration constant to CALDAC 3 4 EEPROM map table 4 10 to 4 17 initializing Lab PC 1200 AI circuitry 3 3 to 3 4 storing user defined constants 4 1 to 4 3 CLKBI signal 3 11 CNTINT bit DAC interrupt programming 3 20 description 2 17 CNTINTEN bit DAC interrupt programming 3 20 description 2 9 programming update mode of analog output circuitry 3 19 Command Register 1 configuring analog input circuitry 3 6 description 2 5 to 2 6 Command Register 2 clearing analog input circuitry 3 4 to 3 5 description 2 7 to 2 8 programming DAQ operation 3 14 programming update mode of analog output circuitry 3 19 Command Register 3 DAC interrupt programming 3 20 DAQ interrupt programming 3 16 Lab PC 1200 Al RLPM description 2 9 to 2 10 Command Register 4 configuring analog input circuitry 3 6 description 2 11 to 2 12 programming DAQ operations 3 14 3 15 Command Register 5 calibration process 3 3 to 3 4 description 2 13 to 2 14 Command Register 6 configuring analog input circuitry 3 6 DAQ interrupt programming 3 16 description 2 15 to 2 16 configuration 1 2 to 1 3 analog
50. 8 bit port B data National Instruments Corporation 2 33 Lab PC 1200 Al RLPM Chapter 2 Port C Register Map and Descriptions Register You can use port C as an 8 bit I O port like port A and port B if neither port A nor port B is used in handshaking mode If either port A or port B is configured for mode 1 or mode 2 some of the bits in port C are used for handshaking signals See Appendix D OK MSM82C55A Data Sheet for a description of the individual bits in the Port C Register Address 12 hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 D7 D6 5 D4 D3 D2 DI DO Bit Name Description 7 0 D lt 7 0 gt Data 8 bit port C data Digital Control Register You can use the Digital Control Register to configure port A port B and port C as inputs or outputs and you can select simple mode basic I O or handshaking mode strobed I O for transfers See Appendix D OKI MSM82C55A Data Sheet for a description of the individual bits in the Digital Control Register Address 13 hex Type Write only Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 CW7 CW6 CWS 4 CW3 CW2 CWI CWO Bit Name Description 7 0 CW lt 7 0 gt Control Word 8 bit control word Lab PC 1200 Al RLPM 2 34 National Instruments Corporation Chapter 2 Register Map and Descriptions Interval Counter Register Group Use the 8 bit Interval Counter only in the singl
51. 928 PLCC QFJ28 P S450 Three independent 16 bit down counters 932 pin V Plastic SOP SSOP32 P 430 VK e to 6V single power supply FUNCTIONAL BLOCK DIAGRAM COUNTER COUNTER 3 2 INTERNAL BUS CONTROL WORD REGISTER 253 Lab PC 1200 Al RLPM C 2 National Instruments Corporation Appendix C OKI MSM82C53 Data Sheet I O MSM82C53 2RS GS JS 11 PIN CONFIGURATION MSM82C53 2RS Top View 24 pin Plastic DIP MSM82C53 2GS Top View 32 pin Plastic Small Outine Package NC denotes connected EE MSM82C53 2JS Top View 28 pin Plastic Leaded Chip Carrier 19 GATE2 254 National Instruments Corporation C 3 Lab PC 1200 Al RLPM Appendix C OKI MSM82C53 Data Sheet O MSMB82C53 2RS GS JS ABSOLUTE MAXIMUM RATINGS Limits Parameter Symbol Conditions jm MSM82C53 2RS 5 82 53 265 MSMB82C53 2JS Ssupply Voltage Vcc 0 5 to 7 Input Voltage VIN Respect to GND 0 5 to 0 5 Output Voltage 0 5 to Veg 0 5 Storage Temperature Tstg 55 to 150 Power Dissipation Pp Ta 259 0 9 0 7 0 9 OPERATING RANGES Supply Voltage 3to6 Vit 02V Vin Vcc 02V operating frequency 2 6 MHz Operating Temperature 40 to 85 RECOMMENDED OPERATING CONDITIONS Supply Voltage Operating Temperature
52. A Mode Register This step sets the output of counter Al OUTAL low Note Continue to steps 2 and 3 only for controlled DAQ operations 2 Write the least significant byte of the sample count to the Counter A1 Data Register 3 Write the most significant byte of the sample count to the Counter A1 Data Register Programming Counter B1 and the Interval Counter Register If you are doing interval scanning data acquisition you must program counter the clock input of counter B1 is the same as that used for counter in order to synchronize the individual conversions and the scan interval The scan interval is equal to N the value programmed into counter multiplied by the clock period used for counter 0 The scan interval should be longer than the total conversion time In a multiple channel interval DAQ operation the total conversion time is equal to the number of channels being scanned multiplied by the sample interval In a single channel interval DAQ operation the total conversion time is equal to the number loaded into the Interval Counter Register multiplied by the sample interval For single channel interval scanning data acquisition the number that you program into the Interval Counter Register should be smaller than the total number of desired samples For example if you want to acquire 2 000 samples in batches of 100 load the Interval Counter Register with 100 and the sample counter count
53. ACI respectively until the output voltage is 0 V Gain error in the analog output circuitry is the product of the gains contributed by each component in the circuitry This error appears as a voltage difference between the desired voltage and the actual output voltage generated and is dependent on the D A voltage setting To correct this gain error the routine sets the D A to a positive voltage and adjusts CALDAC8 or CALDACIO for DACO or DACI respectively until the output voltage corresponds to M A You must calibrate the analog input circuitry before calibrating the analog output circuitry because the output calibration procedure depends on the analog input circuitry Also for analog output calibration set the analog input circuitry calibration to referenced single ended RSE bipolar mode Refer to Tables 4 1 and 4 2 for calibration tolerances Bipolar Output Calibration Procedure Lab PC 1200 Al RLPM If your board is configured for bipolar output which provides the 5 to 5 V range complete the following procedure This procedure assumes that DAC coding is in the 2 048 to 2 047 range that is you have selected the two s complement coding scheme Initialize all of the CALDACS for analog output 7 8 9 and 10 to 128 before you start the calibration procedure This sets each CALDAC at midscale Perform gain calibration before offset calibration 4 8 National Instruments Corporation Chapter 4 Calibration Gain
54. AQ hardware and application hints National Instruments Corporation Xi Lab PC 1200 Al RLPM About This Manual e Software manuals Examples of software manuals you may are the LabVIEW or LabWindows CVI manual sets and the NI DAQ manuals After you set up your hardware system use either the LabVIEW LabWindows CVI or NI DAQ manuals to help you write your application If you have a large and complicated system it is worthwhile to look through the software manuals before you configure your hardware e Accessory installation guides or manuals If you are using accessory products read the terminal block and cable assembly installation guides or accessory board user manuals They explain how to physically connect the relevant pieces of the system Consult these guides when you are making your connections e SCXI Chassis Manual If you are using SCXI read this manual for maintenance information on the chassis and installation instructions Related Documentation The following National Instruments document contains information that you may find helpful as you read this manual e Application Note 025 Field Wiring and Noise Considerations for Analog Signals The following document also contains information that you may find helpful as you read this manual e Your computer s technical reference manual Customer Communication Lab PC 1200 Al RLPM National Instruments wants to receive your comments on our
55. AQ operation 3 12 to 3 13 straight binary mode 2 21 to 2 22 two s complement binary mode 2 22 ADCUNI BI bit configuring analog input circuitry 3 6 description 2 16 analog input circuitry calibration 4 4 to 4 7 Lab PC 1200 Al RLPM Index bipolar input calibration procedure 4 5 to 4 6 unipolar input calibration procedure 4 6 to 4 7 configuration 1 2 programming for single A D conversions 3 4 to 3 7 clearing analog input circuitry 3 4 to 3 5 configuring analog input circuitry 3 5 to 3 6 performing single A D conversions 3 7 Analog Input Register Group A D FIFO Clear Register clearing analog input circuitry 3 4 to 3 5 description 2 23 programming DAQ operation 3 14 A D FIFO Register description 2 21 to 2 22 obtaining A D conversion results 3 7 overflow condition 3 13 servicing DAQ operation 3 12 to 3 13 two s complement binary mode 2 22 DMATC Interrupt Clear Register 2 23 overview 2 20 register map 2 2 Start Convert Register description 2 23 performing single A D conversions 3 7 analog output circuitry calibration 4 8 to 4 10 bipolar output calibration procedure 4 8 to 4 9 unipolar output calibration procedure 4 9 to 4 10 configuration 1 2 to 1 3 programming 3 17 to 3 20 Lab PC 1200 Al RLPM 1 2 analog output voltage versus digital code bipolar mode two s complement coding table 3 18 unipolar mode straight binary coding table 3 18 configuring analog output circuitry 3 17 to
56. Al Companion Disk The companion disk provides code to execute the ISA Plug and Play algorithm and assign resources to the card This process is normally performed by your computer s operating system such as Windows 95 but for programming environments that do not execute the Plug and Play algorithm such as MS DOS the board will not be operable The code provided can be used to execute the Plug and Play algorithm for environments such as MS DOS The code was compiled with Microsoft Visual C version 1 5 as an MS DOS application Assigning Lab PC 1200 Al Resources Lab PC 1200 Al RLPM The companion disk code allows you to assign any of the allowable resources for the base I O address interrupt channel and DMA channel Table 3 1 lists the acceptable resources for the Lab PC 1200 AI board The function PNPProgramSrom located in the file util c assigns the resources to the board This function as written assigns all boards interrupt channel 5 DMA channel 3 and base I O address 0x220 0x20 e j where j is the board number Thus the first Lab PC 1200 AI board will be assigned base I O address 0x220 the next 0x240 and so on This function should be changed accordingly for your application Table 3 1 Lab PC 1200 AI Allowable Resources Base I O Address IRQ Channels DMA Channels 0x100 0x3e0 3 4 5 6 7 9 1 3 in 0x20 increments 3 2 National Instruments Corporation Chapter 3 Programmin
57. C 1200 Al RLPM Appendix Fujitsu 88341 88342 Data Sheet Figure 2 Logic Symbol AEN AEN Shift Clock Input Data Input Load Strobe Input Figure 3 Block Diagram cw T D A Converter 1 Analog Block D A Converter Lab PC 1200 Al RLPM 4 88341 MB88342 AO1 AO12 DAC Output Data Output MB88342 has 1 to AO8 R 2R Type 8 bit D A Converter 12 Vss MB88342 has AO1 to 8 7 119 National Instruments Corporation Appendix Fujitsu MB88341 MB88342 Data Sheet MB88341 MB88342 PIN DESCRIPTION Figure 1 and Table 1 show the pin assignment and pin description of the MB88341 and MB88342 Table1 Pin Description Lomo Jee re Nome amp Funeiion ES ETHER RENTE EE 5 DC power supply pin for the digital MCU interface enD 9 16 Groundpin EK MOU we 79 f e sv oc power suppi pin tor no alg biok 01a soneron S AN e ab Shift clock input to the internal 12 bit shift register At the rising edge of CLK data the DI pin is shifted into the LSB of the shift register and contents of the shift register are shifted right to the MSB Load strobe input for a 12 bit address data A high level on the LD pin latches a 4 bit address upper 4 bits D11 to D8 of the internal 12 bit shift register into the internal address latch decoder a
58. C3 PCO bits Note that the status of port C varies according to the combination of modes like this National Instruments Corporation Appendix D OKI MSM82C55A Data Sheet VO MSM82C55A 2RS GS VJS 5 Port C Status Read When port C is used for the control signal that is in either mode 1 or mode 2 each control signal and Group A Mode 1 input Mode 0 bus status signal can be read out by reading the content of port C The status read out is as follows Status read on the data bus Mode 1 output Mode 0 Mode 0 Mode 1 input Mode 0 Mode 1 output Mode 1 input Mode 1 input Mode 1 input Mode 1 output Mode 1 output Mode 1 input Mode 1 Output Mode 1 output Mode 2 Mode 0 Mode 2 Mode 1 input Mode 2 Mode 1 output 6 Reset of 82 55 Be sure to keep the RESET signal at power ON in the high level at least for 50 us Subsequently it Note Comparison of MSMB2C55A 5 and MSMB2C55A 2 MSM82C55A 5 becomes the input mode at a high level pulse above 500 ns After a write command is executed to the command register the internal latch is cleared in PORTA PORTC For instance OOH is output at the beginning of a write command when the output port is assigned However if PORTB is not cleared at this time PORTB is unstable In other words PORTB only outputs inef
59. Counter B1 is clocked by the same timebase used for counter 0 If the 1 MHz clock is used for the timebase of counter AO then the period of counter or the scan interval is the value programmed into counter times 1 us Alternatively a programmable timebase for counter A0 is available by using counter BO Counter BO has a fixed unalterable 2 MHz clock as its own timebase Therefore its period is the value programmed into counter multiplied by 500 ns The minimum period that can be selected for counter BO is 1 us The period of counter or the sample interval is then equal to the period of counter BO multiplied by the value programmed into counter The maximum sample interval is approximately 35 minutes You can use counter BO in any DAQ operation as an alternative timebase for the sample interval Programming a DAQ operation requires setting up the four available counters setting up the Interval Counter Register in single channel interval scanning mode and then triggering the DAQ operation If you are using counter BO or counter internally for a operation be sure that GATBO or GATBI are not being driven externally through the I O connector or are being driven high Perform the following steps to program a DAQ operation 1 Clear the analog input circuitry 2 Configure the analog input circuitry 3 Setup the four available counters and the Interval Counter Register if necessary 4 Trigger th
60. EF 007 0 18 Dimensions in 1988 FUJITSU LIMITED F200035 4C inches millimeters 7 132 National Instruments Corporation A 17 Lab PC 1200 Al RLPM Fujitsu MB88341 MB88342 Data Sheet MB88341 MB88342 88341 20 1 PLASTIC FLAT PACKAGE Case No FPT 20P M03 pm SEATED HEIGHT 0 257029 256 004 KAT 004010 252 008 6 404 0 20 213 5 40 NOM 1735 004 4 40 0 10 3 i ong 002 o 12 005 pose o 006 90110157 002 t 9880 72 0 22 005 230 5 85 REF Details of A part STAND 10 104010 om Dimensions in 1989 FUJITSU LIMITED F20012S 2C This dimension does not include resin protrusion inches millimeters Lab PC 1200 Al RLPM 7 133 18 National Instruments Corporation Appendix Fujitsu MB88341 MB88342 Data Sheet MB88341 MB88342 MB88342 P 16 LEAD PLASTIC DUAL IN LINE PACKAGE Case No DIP I6P M04 008 0 20 r 170 0319 550 OR a C D T 244 010 300 7 62 6 2010 25 TYP INDEX 2 7 010 002 0 25 0 05 172 4 36 MAX 118 3 00 MIN 0500 27 100 2 54 1 0 4620 08 020 0 51 MIN Dimensions in 1988 FUMTSU LIMITED D160335 2 inches millimeters 7 134 National Instruments Corporation A 19 Lab PC 1200 Al RLPM Appendix Fujitsu 88341 88342 Data Sheet
61. EN FIFO Interrupt Enable This bit enables and disables the generation of an interrupt when an A D conversion result is available to be read from the A D FIFO If you set FIFOINTEN an interrupt is generated whenever the DAVAIL bit becomes set in Status Register 1 Service this interrupt by reading the data from the FIFO 4 ERRINTEN Error Interrupt Enable This bit enables and disables the generation of an interrupt when an A D error condition is detected If you set ERRINTEN an interrupt is generated whenever the OVERFLOW or OVERRUN bit becomes set in Status Register 1 Service the interrupt by writing to the A D FIFO Clear Register 3 CNTINTEN Counter Interrupt Enable This bit enables the counter A2 output or the EXTUPDATE signal to generate an interrupt If you set CNTINTEN an interrupt occurs whenever the CNTINT bit becomes set in Status Register 1 Clear this interrupt by writing to the Timer Interrupt Clear Register This interrupt allows waveform generation on the analog output because the same signal that sets the interrupt also updates the DAC output if the corresponding LDAC bit in Command Register 2 is set 2 TCINTEN DMA Terminal Count Interrupt Enable This bit enables generation of an interrupt when a DMA terminal count pulse is received If TCINTEN is set an interrupt request National Instruments Corporation 2 9 Lab PC 1200 Al RLPM Chapter 2 Register and Descriptions Lab PC 1200 Al RLPM DIOINTEN DMAE
62. I Low Byte and DACI High Byte Registers 2 25 Interval Counter Data Register 2 36 Port A Register 2 33 Port B Register 2 33 Port C Register 2 34 D 11 8 2 21 to 2 22 2 25 D lt 15 8 gt 2 22 D lt 15 12 gt 2 25 DACOUNI BI 2 16 3 17 DACIUNI BI 2 15 3 17 DAVAIL 2 18 3 5 3 7 DIOINTEN 2 10 DITHEREN 2 13 4 5 DMAEN 2 10 3 17 DMATC 2 17 DQINTEN 2 15 3 16 ECLKDRY 2 12 ECLKRCYV 2 11 3 5 3 14 EEPROMCS 2 13 3 3 4 2 National Instruments Corporation I 3 Index 2 12 3 12 3 15 ERRINTEN 2 9 3 16 2 17 FIFOHF 2 19 3 5 3 7 FIFOINTEN 2 9 3 16 lt 2 0 gt 2 5 3 6 2 17 HFINTEN 2 15 3 16 HWTRIG 2 8 3 5 3 14 INTSCAN 2 12 3 12 3 15 LDACO 2 7 3 19 LDACI 2 7 3 19 lt 2 0 gt 2 6 3 6 OUTAI 2 19 OVERFLOW 2 18 3 5 3 7 3 13 OVERRUN 2 18 3 5 3 7 3 13 PRETRIG 2 8 3 15 PROMOUT 2 19 3 4 RSE NRSE 2 16 3 6 4 5 SCANEN 2 5 3 6 SCANUP 2 15 3 6 SCLK 2 13 3 3 to 3 4 4 2 SDATA 2 13 4 2 SE DIFF 2 11 3 6 4 5 SWTRIG 2 8 3 4 to 3 5 3 12 3 15 TBSEL 2 8 3 10 TCINTEN 2 9 to 2 10 TWOSCMP 2 5 to 2 6 3 6 WRTPRT 2 14 3 3 4 2 board configuration 1 2 to 1 3 bulletin board support E 1 C CALDACLD bit description 2 13 writing calibration constant to CALDAC 3 4 calibration analog input calibration 4 4 to 4 7 Lab PC 1200 Al RLPM Index bipolar input calibration procedure 4
63. N is generated when the DMA controller transfer count register decrements from 0 to FFFF hex The interrupt is serviced by writing to the DMATC Interrupt Clear Register DIO Interrupt Enable This bit enables or disables generation of an interrupt when either Port A or Port B is ready to transfer data and an interrupt request is set via or PCO of 82C55A See Appendix D OKT 82 55 Data Sheet for details Clear this interrupt by clearing PC3 or PCO If you clear DIOINTEN the interrupts from PC3 or PCO are disabled DMA Enable tThis bit enables or disables Analog Input DMA transfers If DMAEN is set a DMA request is generated whenever an A D conversion result is available If DMAEN is cleared no DMA request will be generated See the DAQ DMA Programming section in Chapter 3 Programming for more information 2 10 National Instruments Corporation Chapter 2 Register Map and Descriptions Command Register 4 Use this register to select the analog input mode to enable interval scanning and to allow the I O connector pins to externally drive certain DAQ signals Address OF hex Type Write only Word Size 8 bit Bit Map 7 6 3 4 3 2 1 0 0 0 0 ECLKRCV SE DIFF ECLKDRV EOIRCV INTSCAN Bit Name Description 7 5 0 Always leave these bits cleared 4 ECLKRCV External Clock Receive This bit disables or enables the external signal EXTCONV If you set this bit tran
64. N is the value programmed into counter and N is the value programmed into counter AO The sample interval can then be programmed to be between 2 us and 65 535 2 us Use the following equation to determine the sample interval sample interval Nos Np 500 ns Use the following programming sequence to program counter BO as an alternative timebase for counter writes are 8 bit operations 1 Setthe TBSEL bit in Command Register 2 2 Write 0x36 select counter BO mode 3 to the Counter B Mode Register 3 Write the least significant byte of the sample interval Nj to the Counter BO Data Register 4 Write the most significant byte of the sample interval N to the Counter BO Data Register 3 10 National Instruments Corporation Chapter 3 Programming Programming Counter A1 You must program counter A1 even if you are planning on doing a freerun DAQ operation In a freerun DAQ operation set the output of counter A1 low to gate counter AO on and thus allow conversions to occur The number of samples you want to acquire in a controlled DAQ operation is equal to N 2 where is the value programmed into counter Al Therefore the number of samples can range from 3 to 65 537 Use the following equation to determine the number of samples number of samples N 2 Use the following sequence to program counter A1 All writes are 8 bit operations 1 Write 0x70 select counter A1 mode 0 to the Counter
65. P QFP44 P 910 VK 944 Plastic QFP QFP44 P 910 VIK CIRCUIT CONFIGURATION ul 2 E vV 3 D a lt 2 2 278 Lab PC 1200 Al RLPM D 2 National Instruments Corporation Appendix D OKI MSM82C55A Data Sheet 4 O0 MSM82C55A 2RS GS VJS PIN CONFIGURATION MSMB2C55A 2RS Top View 40 pin Plastic DIP MSM82C55A 2GS 44 pin Plastic Quad Flat Package 4 1 2 3 4 5 6 7 8 9 o 11 121314 15 16 171 MSM82C55A 2 VJS Top View 44 pin Plastic Leaded Chip Carrier 279 National Instruments Corporation D 3 Lab PC 1200 Al RLPM Appendix D Lab PC 1200 Al RLPM D 4 National Instruments Corporation OKI MSM82C55A Data Sheet O MSM82C55A 2RS GS VJS 1 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Conditions Unit MSMB82C55A 2RS MSM82C55A 2GS MSM82C55A 2v JS Ssupply Voltage Ta 25 C 0 5to 7 with respect 0 5 to Vec 0 5 to GND 0 5 to Veg 0 5 V Input Voltage Output Voltage Storage Temperature 55 to 150 Pp Ta 25 1 0 0 7 1 0 w Power Dissipation OPERATING RANGE Symbol Supply Voltage 3106 Operating Temperature ToP 40to 85 c RECOMMENDED OPERATING RANGE Parameter ms vm Vcc 45 5 5 5 Supply Voltage
66. PM Chapter 3 Programming Programming a DAQ Operation Using Internal Timing Lab PC 1200 Al RLPM A sequence of timed A D conversions is referred to in this manual as a DAQ operation The parameters of concern in a DAQ operation are the sample interval scan interval and the total number of samples A sample interval indicates the time to elapse between A D conversions on each channel in the sequence The scan interval is the time that elapses between the channel scanning cycles The scan interval is only used in interval scanning mode There are four different internal counters that can help you time these parameters counter counter A1 counter BO and counter There are three different operation modes interval scanning controlled and freerun acquisition mode The Lab PC 1200 AI can perform both single channel data acquisition and multiple channel data acquisition In a controlled acquisition mode only one counter is required to time the sample intervals In this mode you can perform a specified number of conversions after which the hardware ends the DAQ operation The number of conversions in a single DAQ operation in this case is limited to a 16 bit count or 65 535 samples Use counter A0 to time the sample intervals without any delays Use counter A1 as the sample counter Each sample is taken with the same sample interval Counter 0 is clocked by a 1 MHz clock The period of counter or the sample int
67. TRA Uo Group A Mode 1 input Group B Mode 1 output 3 Mode 2 Strobe bidirectional bus 1 operation STB Strobe input 290 Lab PC 1200 Al RLPM mode 2 it is possible to transfer data in 2 direc tions through a single 8 bit port This operation is akin to a combination between input and output operations Port C waits for the control signal in this case too Mode 2 is available only for group A however Next 8 description is made on mode 2 OBF Output buffer full flag output This signal when turned to low level indicates that data has been written to the internal out put latch upon receipt of the WR signal from the CPU At this time port A is still in the high im pedance status and the data is not yet output to the outside This signal turns to low level at the rising edge of the WR and high level at the falling edge of the ACK ACK Acknowledge input When a low level signal is input to this pin the high impedance status of port A is cleared the buffer is enabled and the data written to the in ternal output latch is output to port A When the input returns to high level port A is made into the high impedance status D 14 When this signal turns to low level the data out put to the port from the pin is fetched into the internal input latch The data is output to the data bus upon receipt of the RD signal from the CPU but it remains in the high impedance
68. a single analog channel specified by lt 2 0 gt and SE DIFF during the entire DAQ operation 6 4 GAIN lt 2 0 gt Gain These three bits select the gain setting as follows GAIN lt z2 0 gt Selected Gain 000 1 001 Invalid 010 2 011 5 100 10 101 20 110 50 111 100 3 TWOSCMP Two s Complement This bit selects the coding format of the ADC output Set this bit to sign extend the 12 bit data National Instruments Corporation 2 5 Lab PC 1200 Al RLPM Chapter 2 Register and Descriptions from the ADC to 16 bits two s complement Clear this bit to make bits 12 through 15 return 0 straight binary 2 0 lt 2 0 gt Multiplexer Address These three bits select which of the eight input channels are scanned The analog input multiplexers depend on these bits and also on SCANEN SCANUP bit 7 of Command Register 6 and SE DIFF Input channels are selected as follows Selected Analog Input Channels Single Ended Mode Differential Mode Scan Scan Scan lt 2 0 gt Disabled Enabled Disabled Enabled 000 0 0 0 001 1 0 2 010 2 2 4 011 3 2 6 100 4 4 0 101 5 4 2 110 6 6 4 111 7 6 6 Lab PC 1200 Al RLPM In single ended mode SE DIFF cleared if you set SCANEN and clear SCANUP analog channels lt 2 0 gt through 0 are sampled sequentially In single ended mode SE DIFF cleared if you set SCANEN and set SCANUP analog channels 0 through MA
69. ables counting up to a maximum of 237 C 12 263 National Instruments Corporation OKI MSM82C55A Data Sheet This appendix contains the manufacturer data sheet for the MSM82C55A CMOS programmable peripheral interface manufactured by OKI Semiconductor Inc This interface is used on the Lab PC 1200 AI 1 Copyright OKI Semiconductor Inc Reprinted with permission of copyright owner rights reserved OKI Semiconductor Microprocessor Data Book 1993 National Instruments Corporation D 1 Lab PC 1200 Al RLPM Appendix D OKI MSM82C55A Data Sheet OKI semiconductor MSM82C55A 2RS GS VJS CMOS PROGRAMMABLE PERIPHERAL INTERFACE GENERAL DESCRIPTION The MSM82C55A is a programmable universal 1 0 interface device which operates as high speed and on low power consumption due to 3 silicon gate CMOS technology It is the best fit as an 1 0 port in a system which employs the 8 bit parallel processing MSM80C85A CPU This device has 24 bit UO pins equivalent to three 8 bit I O ports and all inputs outputs TTL interface compatible FEATURES e High speed and low power consumption due to Bit set reset function Port C silicon gate CMOS technology TTL compatible 3 V to 6 V single power supply Compatible with 8255A 5 Full static operation 40 pin Plastic DIP DIPAO P 600 e Programmable 24 bit UO ports 44 pin PLCC QFJ44 P S650 e Bidirectional bus operation Port A 44 pin V Plastic QF
70. ack the contents of 82C53 A counter 1 Counter A1 is the sample counter for a operation Address 15 hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 DO Bit Name Description 7 0 D lt 7 0 gt Data 8 bit counter A1 contents National Instruments Corporation 2 27 Lab PC 1200 Al RLPM Chapter 2 Register Map and Descriptions Counter A2 Data Register Use the Counter A2 Data Register to write data and read back the contents of 82C53 A counter A2 Counter A2 is the DAC update timer for waveform generation Address 16 hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 DI DO Bit Name Description 7 0 D lt 7 0 gt Data 8 bit counter A2 contents Counter A Mode Register The Counter A Mode Register determines the operation mode for each of the three counters on the 82C53 A chip The Counter A Mode Register selects the counter involved its read write mode its operation mode that is any of the 82C53 six operation modes and the counting mode binary or BCD counting The Counter A Mode Register is an 8 bit register Bit and programming descriptions for each of these bits are in Appendix C OKI MSM82C53 Data Sheet Address 17 hex Type Write only Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 SCI SCO RLO M2 MI 0 BCD
71. ad of using counter B1 to time the scan interval you can follow the same sequence of steps as described in Programming a DAQ Operation Using Internal Timing except for the section describing the programming of counter B1 Use the following sequence of steps to use OUTBI in place of counter B1 1 Program the Interval Counter Register if necessary 2 Setthe INTSCAN bit in Command Register 4 3 Set the EOIRCV bit in Command Register 4 If you want to externally time the scan interval you should also externally time the sample interval through EXTCONV to synchronize the sample interval and the scan interval Refer to Chapter 3 Signal Connections in the Lab PC 1200 AI User Manual for timing specifications National Instruments Corporation 3 15 Lab PC 1200 Al RLPM Chapter 3 Programming DAQ Interrupt Programming Five different interrupts can be generated by the analog input circuitry as follows e When a conversion is available to be read from the A D FIFO e When the A D FIFO is half full e When an error condition overflow or overrun is detected e When a operation is terminated by counter Al e Whena DMA TC pulse is received You can enable these five interrupts individually Set the FIFOINTEN bit in Command Register 3 to enable interrupt generation when a conversion is available to be read from the A D FIFO If FIFOINTEN is set an interrupt is generated whenever the DAVAIL bit in Status Register 1 is set
72. ast significant bit meters 1 Mega the standard metric prefix for 1 million or 10 when used with units of measure such as volts and hertz 2 mega the prefix for 1 048 576 or 220 when used with B to quantify data or computer memory multiplexer select bits megabytes of memory a unit for data transfer that means 1 million or 105 bytes s million samples most significant bit G 4 National Instruments Corporation NRSE 0 operating system OUT OUTAI OVERFLOW OVERRUN P Plug and Play devices Plug and Play ISA PRETRIG PROMOUT R RAM resolution rms RSE RSE NRSE S 5 5 5 SCANEN National Instruments Corporation G 5 Glossary nonreferenced single ended mode all measurements are made with respect to a common NRSE measurement system reference but the voltage at this reference can vary with respect to the measurement system ground base level software that controls a computer runs programs interacts with users and communicates with installed hardware or peripheral devices counter output output A1 bit overflow error status bit overrun error status bit devices that do not require dip switches or jumpers to configure resources on the devices also called switchless devices a specification prepared by Microsoft Intel and other PC related companies that result in PCs with plug in boards that can be fully configured in software without jumpers or switches on the boards pr
73. ata Sheet X25020 ORDERING INFORMATION x25000 P T V Device Vece Limits Blank 5V 10 to 5 5V 2 7 2 7V to 5 5V Temperature Range Blank Commercial 0 C to 70 C Industrial 40 C to 85 C Military 55 C to 125 C Package P 8 Lead Plastic DIP S 8 Lead SOIC V 8 Lead TSSOP Part Mark Convention X25020 X Blank 8 Lead SOIC P 8 Lead Plastic DIP S 8 Lead SOIC Blank 5V 10 0 C to 70 C 410 40 C to 85 C D 3V to 5 5V 0 C to 70 C E 3V to 5 5V 40 C to 85 C 2 7V to 5 5V 0 C to 70 C G 2 7V to 5 5V 40 C to 85 _ _ LIMITED WARRANTY Devices sold by Xicor Inc are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only Xicor Inc makes no warranty express statutory implied or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement Xicor Inc makes no warranty of merchantability or fitness for any purpose Xicor Inc reserves the right to discontinue production and change specifications and prices at any time and without notice Xicor Inc assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor Inc product No other circuits patents lic
74. ation Control Word and Count Value Program Each counter operation mode is set by control word programming The control word format is out lined below 07 06 DS D4 D3 02 Di Select Read Load Counter CS 0 AO A1 1 1 RD 1 WR 0 Select Counter SCO SC1 Selection of set counter sco Set Contents MENU Counter 1 selection Counter 2 selection combination Read Load RL1 RLO Loading format setting o o Reading Loading of Least Significant byte LSB Reading Loading of Most Significant byte MSB Reading Loading of LSB followed by MSB Count value Reading Lab PC 1200 Al RLPM Data bus in high impedance status Mode M2 M1 MO setting Operation waveform mode x denotes not specified e BCD Operation count mode setting Binary Count 16 bits Binary BCD Count 4 decades Binary Coded Decimal After setting Read Load Mode and BCD in each counter as outlined above next set the desired count value In some Modes counting is started immediately after the count value has been written This count value setting must conform with the Read Load format set in advance Note that the internal counters are reset to OOOOH during control word setting The counter value can t be read If the two bytes LSB and MSB are written at this stage RLO and RL1 1 1
75. ational Instruments Corporation 4 9 Lab PC 1200 Al RLPM Chapter 4 Calibration EEPROM Map Gain Calibration 1 Write 0 to DACO or DAC1 Choose a value between 8 0 and 9 5 V 2 1 024 readings from analog input channel 2 still connected to DACOOUT or DACIOUT at a gain of 1 Take the mean and call it mean gain zero 3 Write the value v to DACO or DAC1 Choose a value between 8 0 and 9 5 V 4 Take 1 024 readings from analog input channel 2 at a gain of 1 Take the mean and call it mean gain vo 5 Adjust CALDACS or CALDAC10 so that Vref gain vref mean gain zero 10V calibration tolerance 4 0951 gain Offset Calibration 1 Connect DACOOUT pin 10 or DACIOUT pin 12 to analog input channel 2 pin 3 2 Write a0 to DACO or DACI 3 Take 1 024 readings from analog input channel 2 at a gain of 1 Take the mean and call it offset 4 Adjust CALDAC7 or CALDACO so that loffsetl offset calibration tolerance Table 4 3 shows part of the EEPROM map for the Lab PC 1200 AI Locations 180 255 contain information about the Lab PC 1200 AI that NI DAQ uses These locations are not shown and you should not access them The factory bipolar area contains locations 156 179 and the factory unipolar area contains 132 155 The user areas are in the lower half of the EEPROM The pointers from 120 127 are initialized to point to factory locations To use user area calibration
76. ay cause permanent damage to the device This is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied Exposure to absolute maximum rating con ditions for extended periods may affect device reliability Temp Min Max Supply Voltage Limits Commercial 0 C 70 25020 5V 10 Industrial 40 85 X25020 3 to 5 5V Military 559 125 25020 2 7 2 7 to 5 5V 3834 05 1 3834 PGM 06 1 D C OPERATING CHARACTERISTICS Over the recommended operating conditions unless otherwise specified Limits Symbol Parameter Min Max Units Test Conditions lcc Supply Current Active 3 mA SCK Vcc x 0 1 x 0 9 1MHz SO Open Isp Vcc Supply Current 150 CS VIN Vss or 0 3V Standby lu Input Leakage Current 10 pA Vin Vss to Voc ILo Output Leakage Current 10 VouT Vss to Vcc Vi Input LOW Voltage 1 Vccx03 V Input HIGH Voltage 0 7 gt 0 5 V VoL Output LOW Voltage 0 4 V lo 2mA Output HIGH Voltage Vcc 0 8 V 1mA 3834 PGM 07 3 POWER UP TIMING Symbol Parameter Min Max Units Power up to Read Operation 1 ms tpuw Power up to Write Operation 5 ms 3834 PGM T08 CAPACITANCE Ta
77. cations engineers answer your questions more efficiently National Instruments Products Hardware revision Interrupt level of hardware DMA channels of hardware Base I O address of hardware Programming choice National Instruments software Other boards in system Base I O address of other boards DMA channels of other boards Interrupt level of other boards Other Products Computer make and model Microprocessor Clock frequency or speed Type of video board installed Operating system version Operating system mode Programming language Programming language version Other boards in system Base I O address of other boards DMA channels of other boards Interrupt level of other boards Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products This information helps us provide quality products to meet your needs Title Lab PC 1200 AI Register Level Programmer Manual Edition Date December 1997 Part Number 341309A 01 Please comment on the completeness clarity and organization of the manual If you find errors in the manual please record the page numbers and describe the errors Thank you for your help Name Title Company Address E Mail Address Phone Fax Mail to Technical Publications Faxt0 T
78. ces to share the same bus The X25020 also features two additional inputs that provide the end user with added flexibility By asserting the HOLD input the X25020 will ignore transitions on its inputs thus allowing the host to service higher priority interrupts The WP inputcan be usedas a hardwire input tothe X25020 disabling all write attempts thus providing a mechanism for limiting end user capability of altering the memory The X25020 utilizes Xicor s proprietary Direct Write cell providing a minimum endurance of 100 000 cycles per byte and a minimum data retention of 100 years FUNCTIONAL DIAGRAM STATUS REGISTER so Si SCK cs HOLD COMMAND DECODE CONTROL AND TIMING LOGIC Direct Write and Block Lock Protection is a trademark of Xicor Inc Xicor Inc 1994 1995 Patents Pending 3834 1 4 5 26 95 T17 C6 D9 TD Lab PC 1200 Al RLPM XDECODE 256 BYTE LOGIC ARRAY DATA REGISTER 3834 FHD F01 2 111 Characteristics subject to change without notice B 2 National Instruments Corporation 25020 Appendix PIN DESCRIPTIONS Serial Output SO SO is a push pull serial data output pin During a read cycle data is shifted out on this pin Data is clocked out by the falling edge of the serial clock Serial Input SI is the serial data input All opcodes byte ad dresses and data to be written to the memory are input on this pin Data is latched by
79. clear this bit the voltage output of DACO is immediately updated when data is loaded into the DACO High Byte Register 5 2SDACI Two s Complement DAC1 This bit selects the binary coding scheme used for the DACI data If you set this bit a two s complement binary coding scheme is used for interpreting the 12 bit data Two s complement is used with bipolar output mode If you clear this bit a straight binary coding scheme is used Straight binary is used with unipolar output mode 4 2SDACO Two s Complement DACO This bit selects the binary coding scheme used for the DACO data If you set this bit two s complement binary coding scheme is used for interpreting the 12 bit data Two s complement is used with bipolar output mode If you clear this bit a straight National Instruments Corporation 2 7 Lab PC 1200 Al RLPM Chapter 2 Register Map and Descriptions binary coding scheme is used Straight binary is used with unipolar output mode 3 TBSEL Time Base Select This bit selects the clock source for counter 0 the sample interval timer If you clear this bit a 1 MHz clock drives counter 0 and the interval between samples is the value loaded into counter AO multiplied by 1 us If you set this bit the output of counter BO is used as the clock source The timebase for counter BO is fixed at 2 MHz The sample interval is the value loaded into counter AO multiplied by the period of the output signal from counter BO
80. cted to AGND ata gain of 1 Take the mean and call it postgain offset 2 Connect the voltage reference between ACHT pin 2 and AGND pin 11 Choose a voltage reference between 3 0 and 4 5 V 3 Take 1 024 samples from channel 1 at a gain of 1 Take the mean and call it mean 4 Adjust CALDAC6 so that I meanl postgain offset tolerance Vref 5V 2 047 gain calibration Postgain Offset Calibration 1 Take 1 024 samples from channel 0 still connected to AGND ata gain of 1 Take the mean and call this postgain offset 2 Adjust CALDACS so that Ipostgain offsetl lt postgain calibration tolerance Calibration at Higher Gains If you have performed gain calibration at a gain of 1 and the gain is changed to a value not equal to 1 2 5 10 20 50 or 100 you will get a maximum gain error of 0 5 In addition the postgain offset will change so you must recalibrate both the postgain offset CALDACS as well as gain CALDACO at that gain If you perform gain and postgain offset calibrations at all other gains and store these values in the EEPROM the maximum gain error will be 0 0246 at all gains Follow the same steps as given in the Gain Calibration section but use a gain not equal to 1 i Note When you use a gain not equal to 1 remember that the voltage reference multiplied by the gain should be less than 4 5 V Unipolar Input Calibration Procedure Lab PC 1200 Al RLPM If your
81. date the analog output circuitry National Instruments Corporation 3 19 Lab PC 1200 Al RLPM Chapter 3 Programming 2 Wirite the least significant byte of the update period to the Counter A2 Data Register 3 Write the most significant byte of the update period to the Counter A2 Data Register The update cycle starts immediately after you write the most significant byte to the Counter A2 Data Register If you are using EXTUPDATE the update cycle starts after setting OUTA2 high and on the first falling edge of EXTUPDATE DAC Interrupt Programming Set the CNTINTEN bit in Command Register 3 to enable interrupt generation on the rising edge of either OUTA2 or EXTUPDATE If CNTINTEN is set then an interrupt is generated whenever the CNTINT bit in Status Register 1 is set You service this interrupt by writing a new value to DACO or DACI Low Byte and High Byte Registers To clear the interrupt write to the Timer Interrupt Clear Register This allows continuous waveform generation The DAC output voltage is then updated by a high to low transition on either OUTA2 or EXTUPDATE Programming the Digital 1 0 Circuitry Digital I O on the Lab PC 1200 AI uses the 82C554 integrated circuit Programming the digital I O circuitry involves setting the mode of the 82 55 by writing to the Digital Control Register and then writing and reading from the three port registers port A port B and port C The various modes of the 82 55 are
82. difference is measured DIO interrupt enable bit G 2 National Instruments Corporation DITHEREN DMA DOS DQINTEN E ECLKDRV ECLKRCV EEPROM EEPROMCS EOIRCV ERRINTEN EXTCONV EXTGATAO F FIFO FIFOHF FIFOINTEN ft G gain GAIN GATAO National Instruments Corporation G 3 Glossary dither enable bit direct memory access a method by which data can be transferred to from computer memory from to a device or memory on the bus while the processor does something else DMA is the fastest method of transferring data to from computer memory disk operating system DAQ interrupt enable bit external clock drive bit external clock receive bit electrically erasable programmable read only memory ROM that be erased with an electrical signal and reprogrammed EEPROM chip select bit external output interval clock receive bit error interrupt enable bit external conversion signal external gate AO bit first in first out memory buffer the first data stored is the first data sent to the acceptor FIFOs are often used on DAQ devices to temporarily store incoming or outgoing data until that data can be retrieved or output For example an analog input FIFO stores the results of A D conversions until the data can be retrieved into system memory a process that requires the servicing of interrupts and often the programming of the DMA controller This process can take several milliseconds in some cases Dur
83. e 1 Write 0x34 select counter AO mode 2 to the Counter A Mode Register 2 Clear the ECLKRCV bit in Command Register 4 You must set up counter to force OUTAO high and enable conversions initiated by EXTCONV You also need to ensure that the ECLKRCV bit in Command Register 4 is cleared to enable EXTCONV After you trigger the DAQ operation using either SWTRIG or EXTTRIG in posttrigger mode the first EXTCONV pulse may not cause an A D conversion See Chapter 3 Signal Connections in the Lab PC 1200 AI User Manual for specifications regarding EXTCONV Programming a DAQ Operation Using EXTTRIG in Posttrigger Mode Lab PC 1200 Al RLPM If you want to use EXTTRIG in posttrigger mode instead of SWTRIG to trigger a DAQ operation you can follow the same sequence of steps described in Programming a DAQ Operation Using Internal Timing except for the section describing triggering of the DAQ operation Use the following sequence to trigger a DAQ operation using EXTTRIG 1 Set the HWTRIG bit in Command Register 2 2 Trigger a DAQ operation with a rising edge on EXTTRIG When you set the HWTRIG bit in Command Register 2 the next rising edge on EXTTRIG will trigger a operation Further transitions on EXTTRIG do not affect anything In a freerun DAQ operation or in a controlled DAQ operation triggered by EXTTRIG in which you want to stop the operation prematurely you can stop conversions by first clearing the HWTRIG bit
84. e unableto alter write data withinthe selected segments The partitioning is controlled as illustrated below Status Register Bits Array Addresses BP1 BPO Protected 0 0 None 0 1 CO FF 1 0 80 FF 1 1 00 FF 3834 PGM Table 1 Instruction Set Instruction Name Instruction Format Operation 0000 0110 0000 0100 WREN WRDI Set the Write Enable Latch Enable Write Operations Reset the Write Enable Latch Disable Write Operations RDSR 0000 0101 Read Status Register WRSR 0000 0001 Write Status Register L READ 0000 0011 Read Data from Memory Array beginning at selected address WRITE 0000 0010 Write Data to Memory Array beginning at Selected Address 1 10 32 Bytes 3834 T04 Instructions are shown MSB leftmost position Instructions are transferred MSB first 2 113 Lab PC 1200 Al RLPM B 4 National Instruments Corporation National Instruments Corporation X25020 Appendix B Clock and Data Timing Data input on the SI line is latched on the rising edge of SCK Data is output on the SO line by the falling edge of SCK Read Sequence When reading from the E2PROM memory array CS is first pulled LOW to select the device The 8 bit READ instruction istransmitted to the X25020 followed by the 8 bit address After the READ opcode and address are sent
85. e ADC contribute to the gain error of the analog input circuitry With the instrumentation amplifier set to a gain of 1 the gain of the analog input circuitry is ideally 1 The gain error is the deviation of the gain from and appears as a multiplication of the input voltage being measured To eliminate this error source you must measure the input first with the inputs grounded and then with the inputs connected to the external voltage source Then adjust CALDAC6 until the measured difference between the two voltages is equal to the value of the external voltage source After the Lab PC 1200 AI is calibrated at a gain of 1 there is only a small residual gain error 40 596 max at the other gains To reduce this error calibrate the board at all other gains and for corresponding values stored in the EEPROM User gain area 4 4 National Instruments Corporation Chapter 4 Calibration In both bipolar and unipolar modes calibration of postgain offset does not affect the gain characteristics However gain calibration does affect postgain offset Therefore you must perform gain calibration before postgain calibration Perform the calibration procedure for both bipolar and unipolar mode with dither enabled by setting the DITHEREN bit in Command Register 5 and in referenced single ended mode clear the RSE NRSE bit in Command Register 6 and the SE DIFF bit in Command Register 4 Refer to Table 4 1 for calibration tolerances Bipolar Inpu
86. e FIFO is at least half full If this bit is high the FIFO is less than half full 1 1 Output Counter A1 This bit indicates the status of the output signal of counter 1 If the user sets the counter A1 mode for a terminal count OUTAI low indicates counter 1 has not started counting or that counting is in progress OUTA high indicates that counter 1 has finished counting 0 PROMOUT EEPROM Output This bit allows access to the serial National Instruments Corporation output pin of the EEPROM During calibration procedures the software reads the calibration data from the EEPROM through PROMOUT and writes the data to the calibration DACs 2 19 Lab PC 1200 Al RLPM Chapter 2 Register Map and Descriptions Analog Input Register Group The three registers making up the Analog Input Register Group control the analog input circuitry and the FIFO Reading the FIFO Register returns stored A D conversion results Writing to the Start Convert Register initiates a single A D conversion Writing to the A D FIFO Clear Register clears the analog input circuitry Bit descriptions for the registers of the Analog Input Register Group are on the following pages Lab PC 1200 Al RLPM 2 20 National Instruments Corporation Chapter 2 Register Map and Descriptions A D FIFO Register The 12 bit A D conversion results are sign extended to 16 bit data in either two s complement or straight binary format and are stored into a 4 K
87. e channel interval scanning mode SCANEN 0 and INTSCAN 1 Refer to the DAQ Operations section in Chapter 4 Theory of Operation of your Lab PC 1200 AI User Manual for an explanation of interval scanning mode The Interval Counter consists of two 8 bit registers the Interval Counter Data Register and the Interval Counter Strobe Register Load the Interval Counter Data Register with the count Writing to the Interval Counter Strobe Register loads this count into the Interval Counter The Interval Counter decrements with each conversion When the count reaches 0 the Interval Counter autoinitializes restoring the original count value Bit descriptions for the registers in the Interval Counter Register Group are on the following pages National Instruments Corporation 2 35 Lab PC 1200 Al RLPM Chapter 2 Register and Descriptions Interval Counter Data Register Load the Interval Counter Data Register with the desired number of samples to be acquired within a scan interval of a single channel DAQ operation Address E hex Type Write only Word Size 8 bit Bit Map Ju 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 DI DO Bit Name Description 7 0 D lt 7 0 gt Data Interval counter count Interval Counter Strobe Register Writing to the Interval Counter Strobe Register strobes the contents of the Interval Counter Data Register into the Interval Counter This action arms the Interval Counter w
88. e following two steps eight times to serially write one byte to the EEPROM 1 Wirite a single bit of the 8 bit value MSB first by setting or clearing the SDATA bit in Command Register 5 The SCLK bit in Command Register 5 should be cleared during this step 2 Setthe SCLK bit in Command Register 5 National Instruments Corporation 3 3 Lab PC 1200 Al RLPM Chapter 3 Programming Repeat the following three steps eight times to serially read one byte from the EEPROM 1 Setthe SCLK bit in Command Register 5 2 Clearthe SCLK bit in Command Register 5 3 Reada single bit of the 8 bit value MSB first by reading the PROMOUT bit of Status Register 2 After reading a single calibration constant from the EEPROM you must write this value to the appropriate CALDAC Use the following steps to write a single byte to a CALDAC 1 Wirite the 4 bit address of the desired CALDAC address 0x3 0xA LSB first CALDACLD should be cleared during this step 2 Write the 8 bit calibration constant MSB first 3 Setthe CALDACLD bit in Command Register 5 4 Clearthe CALDACLD bit in Command Register 5 Repeat the following steps the appropriate number of times to serially write required bits to the CALDAC 1 Wirite a single bit of the value by setting or clearing the SDATA bit in Command Register 5 SCLK should be cleared during this step 2 Setthe SCLK bit in Command Register 5 Repeat the calibration operation for each CALDAC to fu
89. e gate input at level that is upon completion of writing the MSB when there are two bytes the clock input counting is started When the terminal count is reached the output is switched to H level and is maintained in this status until the control word and count value are set again Counting is interrupted if the gate input is switched to L level and restarted when switched back to H level When Count Values are written during counting the operation is as follows National Instruments Corporation C 9 Appendix C 1 byte Read Load When the new count value is written counting is stopped immediately and then restarted at the new count value by the next clock 2 byte Read Load When byte 1 LSB of the new count value is written counting is stopped immediately Counting is restarted at the new count value when byte 2 MSB is written e Mode 1 programmable one shot The counter output is switched to level by the mode setting Note that in this mode counting is not started if only the count value is written Since counting has to be started in this mode by using the leading edge of the gate input as a trigger the counter output is switched to 71 level by the next clock after the gate input trigger This L level status is maintained during the set count value and is switched back to level when the terminal count is reached Once counting has been started
90. e operation Service the operation Perform the configuration steps and clear the analog input circuitry as described in Programming the Analog Input Circuitry for Single A D Conversions section of this chapter National Instruments Corporation 3 9 Lab PC 1200 Al RLPM Chapter 3 Programming Programming Counter 0 and Counter 0 Lab PC 1200 Al RLPM You must always program counter AO for a DAQ operation using internal timing A high to low transition on OUTAO counter output initiates a conversion You can program counter AO to generate a pulse once every us where N is the value programmed into counter AO and the clock input is a 1 MHz signal The minimum number that you can use for N is 2 The sample interval can then be programmed to be between 2 us and 65 535 us Use the following equation to determine the sample interval sample interval N I us Use the following sequence to program counter 0 the sample interval counter All writes are 8 bit write operations 1 Write 0x34 select counter AO mode 2 to the Counter A Mode Register 2 Write the least significant byte of the sample interval to the Counter 0 Data Register 3 Write the most significant byte of the sample interval to the Counter Data Register You can achieve a larger option of sample intervals by using counter BO along with counter AO The resulting sample interval is then N multiplied by N multiplied by 500 ns where
91. ear Register 0C Write only 8 bit 82C53 Counter Timer Register Group B Counter Data Register 18 Read Write 8 bit Counter B1 Data Register 19 Read Write 8 bit Counter B2 Data Register 1 Read Write 8 bit Counter B Mode Register 1B Write only 8 bit Lab PC 1200 Al RLPM 2 2 National Instruments Corporation Chapter 2 Register Map and Descriptions Table 2 1 Lab PC 1200 Al Register Map Continued Address Offset Register Name Hex Type Size 82 55 Digital I O Register Group Port A Register 10 Read Write 8 bit Port B Register 11 Read Write 8 bit Port C Register 12 Read Write 8 bit Digital Control Register 13 Write only 8 bit Interval Counter Register Group Interval Counter Data Register 1E Write only 8 bit Interval Counter Strobe Register 1F Write only 8 bit Register Description Overview The remainder of this chapter discusses each of the Lab PC 1200 AI registers in the order shown in Table 2 1 Each register group is introduced followed by a detailed bit description of each register on the Lab PC 1200 AI For a detailed bit description of each register concerning the 82C53 A or B chip or the 82C55A chip on the Lab PC 1200 AI refer to Appendix C MSM62C53 Data Sheet or Appendix D OKI MSM82C55A Data Sheet The individual register description gives the address type word size and bit map of the register followed by a description of each bit The register bit map shows a diagra
92. echnical Publications National Instruments Corporation National Instruments Corporation 6504 Bridge Point Parkway 512 794 5678 Austin Texas 78730 5039 Glossary Prefix Meanings Value p pico 10 12 n nano 10 9 u micro 10 6 m milli 10 3 k kilo 103 M mega 106 G giga 10 Numbers Symbols positive of or plus negative of minus per gt degree Q ohm 2SDAC two s complement DAC bit A A amperes A D analog to digital ADC analog to digital converter an electronic device often an integrated ADC resolution ADCUNI BI address AI ANSI National Instruments Corporation G 1 circuit that converts an analog voltage to a digital number the resolution of the ADC which is measured in bits An ADC with 16 bits has a higher resolution and thus a higher degree of accuracy than a 12 bit ADC ADC unipolar bipolar bit character code that identifies a specific location or series of locations in memory analog input American National Standards Institute Lab PC 1200 Al RLPM Glossary B BCD binary bipolar bus C C CALDAC CALDACLD CMOS CNTINT CNTINTEN CW D D A DAC DACOUNI BI DACIUNI BI DAQ DAVAIL dB DC DIFF DIOINTEN Lab PC 1200 Al RLPM bit one binary digit either 0 or 1 byte eight related bits of data an eight bit binary number Also used to denote the amount of me
93. enses are implied U S PATENTS Xicor products are covered by one or more of the following U S Patents 4 263 664 4 274 012 4 300 212 4 314 265 4 326 134 4 393 481 4 404 475 4 450 402 4 486 769 4 488 060 4 520 461 4 533 846 4 599 706 4 617 652 4 668 932 4 752 912 4 829 482 4 874 967 4 883 976 Foreign patents and additional patents pending LIFE RELATED POLICY In situations where semiconductor component failure may endanger life system designers using this product should design the system with appropriate error detection and correction redundancy and back up features to prevent such an occurence Xicor s products are not authorized for use in critical components in life support devices or systems 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the support device or system or to affect its safety or effectiveness 2 122 National Instruments Corporation 13 Lab PC 1200 Al RLPM OKI MSM82C53 Data Sheet This appendix contai
94. eoe ect tree tee iue 2 15 Status Register se eet eee eerte eet 2 17 Status Register nre e RED OU Pes 2 19 Analog Input Register Group eese enne enne 2 20 A D FIFO 2 21 A D FIFO Clear 2 23 Start Convert Register eiie ee p ttr 2 23 DMATC Interrupt Clear Register A 2 23 Analog Output Register Group Lab PC 1200 Only 2 24 Low Byte DACO High Byte DAC1 Low Byte and DACI High Byte 2 25 National Instruments Corporation V Lab PC 1200 Al RLPM Contents 82C53 Counter Timer Register Groups and RA 2 26 Counter AO Data 2 27 Counter Al Data 2 27 Counter 2 Data Register 2 28 Counter A Mode Reester 2 28 Timer Interrupt Clear Register sees 2 29 Counter BO Data 2 29 Counter B1 Data Register eee 2 30 Counter B2 Data Reester enne 2 30 Counter B Mode 2 31 82C55A Digital I O Register Group 2 32 Port A Register uite eee her eege 2 33 Port B Register eene I etin 2 33 Port C ere
95. er A1 with 2 000 In this example 20 scan intervals are required to convert 2 000 samples The Interval Counter Register is an 8 bit register Therefore you can convert up to 255 samples National Instruments Corporation 3 11 Lab PC 1200 Al RLPM Chapter 3 Programming in a single scan interval Use the following sequence to program the Interval Counter Register 1 Write the desired number of samples of a single channel that will be acquired during a scan interval to the Interval Counter Data Register 2 Write 0x01 to the Interval Counter Strobe Register to latch the Interval Counter Register Use the following sequence to program counter B1 for interval data acquisition of the writes are 8 bit operations 1 Setthe INTSCAN bit in Command Register 4 2 Clear the EOIRCV bit in Command Register 4 3 Wirite 0x74 select counter B1 mode 2 to the Counter B Mode Register 4 Write the least significant byte of the scan interval to the Counter B1 Data Register 5 Write the most significant byte of the scan interval N to the Counter B1 Data Register Triggering the DAQ Operation To start the DAQ operation set the SWTRIG bit in Command Register 2 which enables counter AO to start counting In a freerun DAQ operation or in any other type of DAQ operation in which you want to stop the operation prematurely you can stop the DAQ operation by clearing the SWTRIG bit CF Note In interval DAQ operations the fir
96. errupt programming 3 16 description 2 15 E ECLKDRV bit 2 12 ECLKRCV bit clearing analog input circuitry 3 5 description 2 11 programming DAQ operation 3 14 EEPROM accidental overwriting note 4 1 calibration map table 4 10 to 4 17 reading single byte from EEPROM 3 7 storing user defined constants 4 2 writing single byte to EEPROM 3 7 EEPROMCS bit description 2 13 reading single byte from EEPROM 3 4 storing user defined constants 4 2 e mail support E 2 EOIRCY bit DAQ operations using OUTBI 3 15 description 2 12 programming counter 3 12 ERRINTEN bit DAQ interrupt programming 3 16 description 2 9 EXTCONV signal clearing analog input circuitry 3 4 to 3 5 programming DAQ operation 3 14 National Instruments Corporation EXTGATAO bit 2 17 signal clearing analog input circuitry 3 5 programming DAQ operation posttrigger mode 3 14 pretrigger mode 3 15 EXTUPDATE signal DAC interrupt programming 3 20 programming update mode of analog output circuitry 3 19 to 3 20 F fax and phone numbers for technical support E 2 Fax on Demand support E 2 FIFOHF bit clearing analog input circuitry 3 5 description 2 19 single A D conversions 3 7 FIFOINTEN bit DAQ interrupt programming 3 16 description 2 9 freerun data acquisition mode 3 8 FTP support E 1 Fujitsu MB88341 MB88342 data sheet 1 G GAIN lt 2 0 gt bits configuring analog input circuitry 3 6 description
97. erval is equal to the value programmed into counter AO multiplied by lus The minimum period that can be selected for counter AO is 2 us The sample interval period or Counter AO must be at least 10 us to avoid an overrun error Choose your sample interval according to the specifications in Chapter 4 Theory of Operation of your Lab PC 1200 AI User Manual to maintain 12 bit accuracy In freerun acquisition mode only one counter is required for a DAQ operation Counter A0 continuously generates the conversion pulses as long as GATEAO is held at a high logic level The software keeps track of the number of conversions that have occurred and turns off counter after the required number of conversions have been obtained or after some other user defined criteria have been met The number of conversions in a single DAQ operation in this case is unlimited In an interval scanning acquisition mode you need two counters Use counter to time the scan interval Within the scan interval each conversion occurs at regular sample intervals timed by counter In multiple channel data acquisition the conversions stop after the sample counter 1 counts down to 0 single channel interval data acquisition the conversions stop after the programmed count in the Interval Counter 3 8 National Instruments Corporation Chapter 3 Programming Register has expired An interval scanning DAQ operation consists of back to back scan intervals
98. es tte 2 34 Digital Control 2 200 040010 2 34 Interval Counter Register Group 2 35 Interval Counter Data Register AA 2 36 Interval Counter Strobe Register oo eee cece eeseeeeceseeeeeeeeeeeeeneeees 2 36 Chapter 3 Programming Register Programming Constderatong eese 3 1 Programming Examples e eee tgp e Gir e ONE 3 1 Lab PC 1200 AI Companion Disk esee 3 2 Assigning Lab PC 1200 AI 3 2 Initializing the Lab PC 1200 AI Circuitry eese 3 3 Programming the Analog Input Circuitry for Single A D Conversions 3 4 Clearing the Analog Input Circuitry 2 3 4 Configuring the Analog Input 3 5 Performing Single A D Conversions 3 7 Programming a Operation Using Internal Timing eene 3 8 Programming Counter AO and Counter BU 3 10 Programming Counter A 3 11 Programming Counter B1 and the Interval Counter Register 3 11 Triggering the Operation 3 12 Servicing the DAQ Operapon 3 12 Programming Operation Using External Tumng sees 3 13 Programming Operation Using 3 14 Programming DAQ Operation Using EXTTRIG in Posttrigger 3 14 Programming Operation Us
99. escription 75 00 0 User 2 Gain 1 value offset 74 00 0 User 2 Gain 1 25 value offset 73 00 0 User 2 Gain 2 value offset 72 00 0 User 2 Gain 5 value offset 71 00 0 User 2 Gain 10 value offset 70 00 0 User 2 Gain 20 value offset 69 00 0 User 2 Gain 50 value offset 68 00 0 User 2 Gain 100 value offset 67 00 0 Not used 66 00 0 Not used 65 00 0 User 3 AI CALDACO value 64 00 0 User 3 AI CALDACI value 63 00 0 User 3 AI CALDAC2 value 62 00 0 User 3 AI CALDAC3 value 61 00 0 User 3 AO CALDAC4 value 60 00 0 User 3 AO CALDACS value 59 00 0 User 3 AO CALDAC6 value 58 00 0 User 3 AO CALDAC7 value 57 00 0 User 3 Gain 1 value gain 56 00 0 User 3 Gain 1 25 value gain 55 00 0 User 3 Gain 2 value gain 54 00 0 User 3 Gain 5 value gain 53 00 0 User 3 Gain 10 value gain 52 00 0 User 3 Gain 20 value gain 51 00 0 User 3 Gain 50 value gain 50 00 0 User 3 Gain 100 value gain National Instruments Corporation 4 15 Lab PC 1200 Al RLPM Chapter 4 Calibration Table 4 3 Lab PC 1200 Al EEPROM Map Continued Location Hex Decimal Description 49 00 0 User 3 Gain 1 value offset 48 00 0 User 3 Gain 1 25 value offset 47 00 0 User 3 Gain 2 value offset 46 00 0 User 3 Gain 5 value offset 45 00 0 User 3 Gain 10 value offset 44 00 0 User 3 Gain 20 value offset 43 00 0 User 3 Gain 50 value offset 42 00 0 User 3 Gain 100 value offset 41 00 0 Not used 40 00 0 Not used 39
100. eset of the internal flip flop is made by the bit set reset operation for port C virtually Bit set gt INTE is set gt Interrupt allowed Bit reset gt INTE is reset gt Interrupt inhibited Control Word Appendix D OKI MSM82C55A Data Sheet 1 0 MSM82C55A 2RS GS VJS Definition of set reset Reset for a desired bit Definition of bit wanted to be set or reset Operational Description by Mode 1 Mode 0 Basic input output operation Mode 0 makes the MSM82C55A operate as a bas ic input port or output port No control signals such as interrupt request etc are required in this mode All 24 bits can be used as two 8 bit ports and two 4 bit ports Sixteen combinations are then possible for inputs outputs The inputs are not latched but the outputs are Group D4 D3 D2 Output Low Order 4 Bits of Port C High Order 4 Bits of Port C Output Output Output Output Output Output Input Output L Output Input Output Output Output Input Input 4 Output Input Output Output Output Input Output Input Output Input Input Output 1 2 3 4 5 6 7 8 Output RI DES L Input Input Input jolojojojojolojo Input Output Output Output 1 Input Output Output Input Input Output Input Output Input 1 34 Out
101. et This appendix contains the manufacturer data sheet for the 88341 88342 2 type 8 bit D A converter manufactured by Fujitsu Microelectronics Inc The MB88341 D A converter is used on the Lab PC 1200 AI 1 Copyright Fujitsu Microelectronics Inc Reprinted with permission of copyright owner rights reserved Fujitsu Microelectronics Inc 1990 Linear Products 1990 Data Book National Instruments Corporation A 1 Lab PC 1200 Al RLPM Appendix Fujitsu MB88341 MB88342 Data Sheet October 1989 co Paton 1 0 FUJITSU MB88341 MB88342 2 TYPE 8 BIT D A CONVERTER DESCRIPTION 88341 MB88342 P The Fujitsu MB88341 and MB88342 are R 2R type 8 bit resolution digital to analog converters DAC designed for interface with a wide range of general 4 bit and 8 bit microcomputers including Fujitsu s MB8840 50 series and MB88400 500 series 4 bit single chip microcomputers The MB88341 has an 8 bit x 12 D A converter and the MB88342 has an 8 bit x 8 channel D A converter Digital data are input serially by individual channel units The loaded digital data are convertered into analog DC voltages by the D A converter in 60 ys settling time The MB88341 and MB88342 are suitable for electronic volumes and replacement for potentiometers for adjustment in addition to normal D A converter applications PLASTIC DIP PLASTIC DIP DIP 20P M02 DIP 16P M04 FEATURES MB88341 PF MB8834
102. etrigger bit EEPROM output bit random access memory the smallest signal increment that can be detected by a measurement system Resolution can be expressed in bits in proportions or in percent of full scale For example a system has 12 bit resolution one part in 4 096 resolution and 0 0244 of full scale read load select bit root mean square referenced single ended mode all measurements are made with respect to a common reference measurement system or a ground Also called a grounded measurement system referenced single ended nonreferenced single ended bit seconds samples counter select bit scan enable bit Lab PC 1200 Al RLPM Glossary SCANUP SCLK SDATA SE DIFF S s SWTRIG T TBSEL TTL TWOSCOMP U unipolar V V W WRTPRT X X Lab PC 1200 Al RLPM scan up bit serial clock bit serial data bit single ended differential bit samples per second used to express the rate at which a board samples an analog signal software trigger bit time base select bit transistor transistor logic two s complement bit a signal range that is always positive for example 0 to 10 V volts write protect bit don t care bit 6 6 National Instruments Corporation Index Numbers 2SDACO bit 2 7 to 2 8 2SDACI bit 2 7 82C53 Counter Timer Register Groups A and B configuration 1 3 Counter Mode Register description 2 28 performing single A D conversion 3 7 progra
103. fective data unstable value according to the device during the period from after a write command is executed till the first data is written to PORTB MSM82C55A 2 After a write command is executed to the command register the internal latch is cleared in All Ports PORTA PORTB PORTC is ontput at the beginning of a write command when the output port is assigned National Instruments Corporation D 17 293 Lab PC 1200 Al RLPM Customer Communication For your convenience this appendix contains forms to help you gather the information necessary to help us solve your technical problems and a form you can use to comment on the product documentation When you contact us we need the information on the Technical Support Form and the configuration form if your manual contains one about your system configuration to answer your questions as quickly as possible National Instruments has technical assistance through electronic fax and telephone systems to quickly provide the information you need Our electronic services include a bulletin board service an FTP site a fax on demand system and e mail support If you have a hardware or software problem first try the electronic support systems If the information available on these systems does not answer your questions we offer fax and telephone support through our technical support centers which are staffed by applications engineers Electronic Services Bulletin Board Su
104. for a unipolar 0 to 10 V output voltage range Clear this bit to configure DACI for a bipolar 5 to 5 V output voltage range 2 15 Lab PC 1200 Al RLPM Chapter 2 Register Map and Descriptions 2 DACOUNUBI DACO Unipolar Bipolar This bit sets the analog voltage output range for DACO Set this bit to configure DACO for a unipolar 0 to 10 V output voltage range Clear this bit to configure DACO for a bipolar 5 to 5 V output voltage range 1 ADCUNI BI Unipolar Bipolar This bit sets the analog voltage input range for data acquisition Set this bit to select a unipolar 0 to 10 V voltage input range Clear this bit to select a bipolar 5 to 5 V voltage input range 0 RSE NRSE Referenced Single Ended Nonreferenced Single Ended This bit and bit 3 of Command Register 4 SE DIFF selects one of three input modes of the Lab PC 1200 AI The status of RSE NRSE is only important with the single ended analog input modes Set this bit to select the nonreferenced single ended mode Clear this bit to select the referenced single ended mode For an explanation of the three input modes refer to the Lab PC 1200 AI User Manual Lab PC 1200 Al RLPM 2 16 National Instruments Corporation Status Register 1 Chapter 2 Register Map and Descriptions Status Register 1 indicates the status of the current DAQ operation and the status of analog output during waveform generation These bits indicate if a DAQ operat
105. g Initializing the Lab PC 1200 Al Circuitry Initializing the Lab PC 1200 AI circuitry involves two steps reset and calibration The Lab PC 1200 AI circuitry is reset on power up Calibration of the analog input and output circuitry involves reading the factory defined calibration constants from the onboard EEPROM and loading them into the appropriate calibration DACs For information on using user defined calibration constants refer to Chapter 4 Calibration When reset the Lab PC 1200 AI is left in the following state of the command registers are cleared N All of the interrupts are disabled and cleared 3 82 55 digital I O is in Mode 0 input 4 The analog output DACs are reset to 0 0 V Lab PC 1200 only Calibrating the Lab PC 1200 AI involves two steps reading eight factory defined calibration constants from the EEPROM and writing each value to the appropriate CALDAC Choose the desired factory defined calibration constants as explained in Chapter 5 Calibration of your Lab PC 1200 AI User Manual Use the following sequence of steps to read a single byte from the EEPROM 1 Setthe EEPROMCS and WRTPRT bits in Command Register 5 2 Serially write the READ instruction 0x03 to the EEPROM to start a read operation Serially write the 8 bit address 4 Serially read one byte of data from the EEPROM Clear EEPROMCS and WRTPRT bits in Command Register 5 to end the read operation Repeat th
106. gital I O lines on the I O connector You can program these ports as two groups of 12 signals or as three individual 8 bit ports You can also configure them as either input or output pins Use the Digital Control Register to configure the three ports For further information on the 82 55 refer to Appendix D OKI MSM82C55A Data Sheet Bit descriptions for the registers in the Digital I O Register Group are on the following pages Lab PC 1200 Al RLPM 2 32 National Instruments Corporation Chapter 2 Register Map and Descriptions Port A Register Use the Port A Register to write and to read the eight digital I O lines constituting port A on the I O connector lt 0 7 gt See Appendix D 5 82 55 Data Sheet for information on how to configure port A for input or output Address 10 hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 DO Bit Name Description 7 0 D lt 7 0 gt Data 8 bit port A data Port B Register Use the Port B Register to write and to read the eight digital I O lines constituting port B that is PB lt 0 7 gt See Appendix D OKI 5 82 55 Data Sheet for information on how to configure port B for input or output Address 11 hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 DI DO Bit Name Description 7 0 D lt 7 0 gt Data
107. gle A D conversions programming 3 7 clearing analog input circuitry 3 4 to 3 5 configuring analog input circuitry 3 5 to 3 6 performing single A D conversions 3 7 Start Convert Register description 2 23 performing single A D conversions 3 7 Status Register 1 description 2 17 to 2 18 servicing DAQ operation 3 13 Status Register 2 2 19 SWTRIG bit clearing analog input circuitry 3 4 to 3 5 description 2 8 programming DAQ operation in pretrigger mode 3 15 triggering DAQ operation 3 12 T TBSEL bit DAQ operations using internal timing 3 10 description 2 8 TCINTEN bit 2 9 to 2 10 technical support E 1 to E 2 telephone and fax numbers for technical support E 2 Timer Interrupt Clear Register Lab PC 1200 Al RLPM Index DAC interrupt programming 3 20 description 2 29 triggering DAQ operation 3 12 TWOSCMP bit configuring analog input circuitry 3 6 description 2 5 to 2 6 U unipolar input calibration 4 6 to 4 7 gain calibration 4 7 postgain offset calibration 4 7 pregain offset calibration 4 7 unipolar input polarity selecting 3 5 to 3 6 unipolar mode straight binary coding table 3 18 unipolar output calibration 4 9 to 4 10 gain calibration 4 10 offset calibration 4 10 unipolar output polarity selecting 3 17 update mode of analog output circuitry programming 3 18 to 3 20 user defined calibration constants 4 1 to 4 3 Lab PC 1200 Al RLPM 1 10 W WRTPRT bit description 2 14
108. hen HOLD is released The HOLD input may be tied HIGH either directly to Voc or tied to Vcc through a resistor Lab PC 1200 Al RLPM Xicor X25020 Data Sheet Appendix Xicor X25020 Data Sheet X25020 Operational Notes Data Protection The X25020 powers up in the following state The following circuitry has been included to prevent The device is in the low power standby state inadvertent writes A HIGH to LOW transition on CS is required to The write enable latch is reset upon power up enter an active state and receive an instruction AWREN instruction must be issued to set the write SO pin is high impedance enable latch s The write enable latch is reset CS must come HIGH at the proper clock count in order to start a write cycle Figure 1 Read Array Operation Sequence cs 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 SCK INSTRUCTION BYTE ADDRESS s VU XEXEMXEXZAOAKLA X AX XX XX DATA OUT HIGH IMPEDANCE so MSB 3834 FHD F04 1 Figure 2 Read Status Register Operation Sequence 10 11 4 5 6 7 8 9 12 13 14 SCK INSTRUCTION 5 HIGH IMPEDANCE 3834 ILL F13 2 115 Lab PC 1200 Al RLPM 6 National Instruments Corporation Appendix Xicor X25020 Data Sheet X25020 Figure 3 Write Enable Latch Sequence SCK zs HIGH IMPEDANCE 50 3834 ILL FOS Figure 4
109. hich decrements with each conversion pulse Address 1F hex Type Write only Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 Bit Name Description 7 0 0 Each of these bits must be 0 for proper operation of the Lab PC 1200 AI 0 1 This bit must be 1 for proper operation of the Lab PC 1200 AI Lab PC 1200 Al RLPM 2 36 National Instruments Corporation Programming This chapter contains programming instructions for operating the Lab PC 1200 AI circuitry and examples of the programming steps necessary to execute an operation If you are not using NI DAQ you must first initialize your board The initialization steps are unique for PC and Macintosh users so refer to the section pertaining to your platform Programming the Lab PC 1200 AI involves writing to and reading from registers on the board You will find a listing of these registers in Chapter 2 Register Map and Descriptions of this manual Register Programming Considerations The Lab PC 1200 AI supports 8 bit I O transfers thus all the read and write operations are 8 bit operations You must do 16 bit transfers in two consecutive 8 bit operations Several write only registers on the Lab PC 1200 AI contain bits that control several independent pieces of the onboard circuitry In the set or clear instructions specific register bits should be set or cleared without changing the current state of the remaining bits in the
110. his time and low level at the falling edge of WR when the INTEg is set INTE of group A is set when the bit for is set while INTEg of group B is set when the bit for PC is set Mode 1 output National Instruments Corporation Appendix D OKI MSM82C55A Data Sheet 14 3 0 MSMB82C55A 2RS GS VJS Port C Function Allocation in Mode 1 Combination of Input Output Group A Input Group B Input Group A Input Group B Output Group A Output Group B Input Group A Output Group B Output Note 1 0 is a bit not used as the control signal but it is available as a port of mode 0 Examples of the relation between the control words and pins when used in mode 1 is shown below When group is mode 1 output and group B is mode 1 input M NS De National Instruments Corporation Ds D4 Selection of UO of PC4 and PCs lois As all of PCo PC3 bits become a control pin in this case this bit is Don t when not defined as a control pin n Input Output D 13 Group A Mode 1 output Group B Mode 1 input 289 Lab PC 1200 Al RLPM Appendix D OKI MSM82C55A Data Sheet O MSM82C55A 2RS GS VJS b When group A is mode 1 input and group B is mode 1 output Selection of 1 0 of PC6 and PC7 when not de fined as a control pin 1 Input Output STBA IBFA IN
111. ill interrupt a write to the X25020 If the internal write cycle has already been initiated WP going LOW will have no affect on a write 3834 FHD F02 1 PIN NAMES Symbol Description cs Chip Select Input 50 Serial Output SI Serial Input SCK Serial Clock Input WP Write Protect Input Vss Ground Voc Supply Voltage HOLD Hold Input 3834 1 1 Xicor 25020 Data Sheet 2 112 National Instruments Corporation 3 Lab PC 1200 Al RLPM Appendix Xicor 25020 Data Sheet X25020 PRINCIPLES OF OPERATION The X25020 is a 256 x 8 2 designed to interface directly with the synchronous serial peripheral interface SPI of many popular microcontroller families The X25020 contains an 8 bit instruction register It is accessed via the SI input with data being clocked in on therising SCK CS mustbe LOW andthe HOLD and WP inputs must be HIGH during the entire operation Table 1 contains a list of the instructions and their opcodes Allinstructions addresses and data are trans ferred MSB first Datainputis sampled on the first rising edge of SCK after CS goes LOW SCK is static allowing the user to stop the clock and then resume operations If the clock line is shared with other peripheral devices on the SPI bus the user can assert the HOLD input to place the X25020 into a PAUSE condition After releasing HOLD the X25020 will resume operation from the point when HOLD was first asserted
112. in and no unwanted conversions will occur while you are clearing the analog input circuitry The analog input circuitry can be cleared by writing to the A D FIFO Clear Register which leaves the analog input circuitry in the following state 1 Analog input status bits OVERRUN OVERFLOW and DAVAIL are cleared and FIFOHF is set 2 Pending interrupt requests from the analog input circuitry are cleared The command registers are not cleared so you do not necessarily have to reconfigure the Lab PC 1200 AI before initiating another sequence Configuring the Analog Input Circuitry Configure the analog input circuitry after initializing the Lab PC 1200 AI and any time the characteristics of the analog input signals change Program the appropriate register bits as follows not necessarily in this order e Select the appropriate input mode DIFF NRSE or RSE e Select the input polarity bipolar or unipolar and coding of the resulting conversions straight binary or two s complement e Select the analog input channels to be scanned and gain You determine the input mode by identifying the types of signal sources that you are using For more information about determining the input mode consult the Lab PC 1200 AI User Manual Select the input mode by setting National Instruments Corporation 3 5 Lab PC 1200 Al RLPM Chapter 3 Programming Lab PC 1200 Al RLPM or clearing the RSE NRSE and SE DIFF bits in Command Regi
113. ing EXTTRIG in Pretrigger Mode 3 15 Programming Operation Using OUR 3 15 DAQ Interrupt Programming 3 16 Lab PC 1200 Al RLPM vi National Instruments Corporation Contents DMA Programming enne treten nennen 3 17 Programming the Analog Output Circuitry Lab PC 1200 3 17 Configuring the Analog Output Circuitry essen 3 17 Programming the Update Mode of the Analog Output Circuitry 3 18 DAC Interrupt Drogerammung eene eren nennen 3 20 Programming the Digital UO Circuitry eese nennen 3 20 Programming the General Purpose Counter Timers eere 3 21 Chapter 4 Calibration Storing User Defined Constant sese eee nennen nene rennen 4 1 Calibration DAES ie detenti egentem sedit 4 3 Analog Input Calibration retener enne 4 4 Bipolar Input Calibration Procedure 4 5 Pregain Offset Coarse Calibration see 4 5 Pregain Offset Fine Calibration sess 4 5 Gain Calibration e eere re ren ree eee dea 4 6 Postgain Offset Calibration essen 4 6 Calibration at Higher 4 6 Unipolar Input Calibration Procedure 2 4 6 Pregain Offset Calibration 22 4 7 Gain Calibration ue et ete nete metes 4 7 Postgain Offset Calibration eess
114. ing this time data accumulates in the FIFO for future retrieval With a larger FIFO longer latencies can be tolerated In the case of analog output a FIFO permits faster update rates because the waveform data can be stored on the FIFO ahead of time This again reduces the effect of latencies associated with getting the data from system memory to the DAQ device FIFO half full bit FIFO interrupt enable bit feet the factor by which a signal is amplified sometimes expressed in decibels gain bits gate AO bit Lab PC 1200 Al RLPM Glossary H h hex HFINTEN HWTRIG Hz IEEE in INTSCAN IRQ ISA K k K kbytes s kS Kword L LDAC LSB SH Mbytes s MS MSB Lab PC 1200 Al RLPM hour hexadecimal FIFO half full interrupt enable bit hardware trigger bit hertz Institute of Electrical and Electronics Engineers inches interval scanning bit input output the transfer of data to from a computer system involving communications channels operator interface devices and or data acquisition and control interfaces interrupt request industry standard architecture kilo the standard metric prefix for 1 000 or 10 used with units of measure such as volts hertz and meters kilo the prefix for 1 024 210 used with B in quantifying data or computer memory a unit for data transfer that means 1 000 or 10 bytes s 1 000 samples 1 024 words of memory Load DAC bit le
115. input configuration 1 2 analog output configuration 1 2 to 1 3 counter configuration 1 3 digital I O configuration 1 3 Configuration and Status Register Group Command Register 1 configuring analog input circuitry 3 6 description 2 5 to 2 6 Command Register 2 clearing analog input circuitry 3 4 to 3 5 description 2 7 to 2 8 programming DAQ operation 3 14 programming update mode of analog output circuitry 3 19 Command Register 3 DAC interrupt programming 3 20 DAQ interrupt programming 3 16 description 2 9 to 2 10 Command Register 4 configuring analog input circuitry 3 6 description 2 11 to 2 12 programming DAQ operations 3 14 Command Register 5 calibration process 3 3 to 3 4 description 2 13 to 2 14 National Instruments Corporation Command Register 6 configuring analog input circuitry 3 6 DAQ interrupt programming 3 16 description 2 15 to 2 16 overview 2 4 register map 2 2 Status Register 1 description 2 17 to 2 18 servicing DAQ operation 3 13 Status Register 2 2 19 controlled acquisition mode 3 8 Counter Mode Register description 2 28 performing single A D conversion 3 7 programming update mode of analog output circuitry 3 19 to 3 20 Counter 0 Data Register DAQ operation using internal timing 3 8 description 2 27 performing single A D conversion 3 7 programming 3 10 Counter A1 Data Register DAQ operations using internal timing 3 8 description 2 27 programming 3 11 Counter
116. ion is in progress or if data is available whether any errors have been found and the analog output interrupt status Address 00 hex Type Read only Word Size 8 bit Bit Map 7 6 gt 4 3 2 1 0 X EXTGATAO GATAO DMATC CNTINT OVERFLOW OVERRUN DAVAIL Bit Name Description 7 X Don t care bits 6 EXTGATAO External Gate A0 This bit indicates the status of the external trigger signal EXTTRIG during a DAQ operation in posttrigger mode If this bit is set EXTTRIG has triggered a DAQ operation Clear this bit by writing to the A D FIFO Clear Register 5 Gate A0 This bit indicates the status of the GATEAO input for counter AO Use this bit as a busy indicator for DAQ operations because conversions are enabled as long as GATEAO is high and counter is programmed appropriately A DAQ operation is terminated when GATAO is cleared 4 DMATC DMA Terminal Count This bit reflects the status of the DMA terminal count If this bitis set and the TCINTEN bit in Command Register 3 is set the current interrupt was generated by a DMA terminal count pulse This bit is cleared by writing to the DMATC Interrupt Clear Register 3 CNTINT Counter Interrupt This bit reflects the status of the National Instruments Corporation interrupt caused by counter A2 output or the EXTUPDATE signal A low to high transition on counter A2 output or on EXTUPDATE sets this bit You can generate an inte
117. is bit is therefore treated as Care Group A mode 2 Group B mode 1 input 291 National Instruments Corporation D 15 Lab PC 1200 Al RLPM Appendix D MSM82C55A Data Sheet O MSM82C55A 2RS GS VJS 4 Mode combinations that define no control bit at port C When Group A is Different in Mode from Group B Group A and group B can be used by setting them in different modes each other at the same time When either group is set to mode1 or mode 2 it is possible to set the one not defined as a control pin in port C to both input and output as a port which operates in mode O at the 3rd and Oth bits of the control word Mode 1 i Mode 0 input Mode 0 output Mode 0 Mode 1 input Mode 0 Mode 1 Mode 0 output Mode 1 input Mode 1 input Mode 1 input Mode 1 output Mode 1 output 292 Lab PC 1200 Al RLPM Mode 1 output Mode 2 When the 1 0 bit is set to input in this case it is pos sible to access data by the normal port C read operation When set to output PC7 4 bits can be ac cessed by the bit set reset function only Meanwhile 3 bits from PC2 to PCO can be accessed by normal write operation D 16 EG Controlled at the 3rd bit D3 of the control word WEE EN Controlled at the Oth bit DO of the contro word The bit set reset function can be used for all of P
118. lly calibrate the Lab PC 1200 AI Programming the Analog Input Circuitry for Single A D Conversions This section explains how to clear the analog input circuitry how to configure the analog input circuitry and how to perform single A D conversions Clearing the Analog Input Circuitry Before clearing the analog input circuitry perform the following steps 1 Clear SWTRIG in Command Register 2 2 Ensure that EXTCONV from the I O connector does not cause any conversions Lab PC 1200 Al RLPM 3 4 National Instruments Corporation Chapter 3 Programming 3 Ensure that EXTTRIG from the I O connector does not cause any conversions Clearing the analog input circuitry does not stop a DAQ operation that was started by the SWTRIG bit in Command Register 2 Therefore you should clear this bit before clearing the analog input circuitry While clearing the analog input circuitry do not externally drive the EXTCONV pin on the I O connector or if you do drive it high Another option is to set the ECLKRCV bit in Command Register 4 This disables any transitions on the pin and no unwanted conversions will occur while you are clearing the analog input circuitry While clearing the analog input circuitry do not externally drive the EXTTRIG pin on the I O connector or if you do drive it high Another option is to make sure the HWTRIG bit in Command Register 2 is cleared This disables any transitions on the EXTTRIG p
119. m of the register with the most significant bit MSB bit 7 for an 8 bit register shown on the left and the least significant bit LSB bit 0 shown on the right A rectangle labeled with the bit name inside its rectangle represents each bit An asterisk after the bit name indicates that the bit is inverted negative logic In a few of the registers several bits are labeled with an X indicating don t care bits When you read a register these bits may appear set or cleared but should be ignored because they have no significance When you write to a register these bit locations should always be written with a 0 The bit map field for some write only registers states not applicable no bits used Writing to these registers causes some event to occur on the Lab PC 1200 AT such as clearing the analog input circuitry The data is ignored when writing to these registers therefore any bit pattern will suffice Note Always write a 0 to don t care bits National Instruments Corporation 2 3 Lab PC 1200 Al RLPM Chapter 2 Register Map and Descriptions Configuration and Status Register Group The eight registers of the Configuration and Status Register Group allow general control and monitoring of the Lab PC 1200 AI A D and D A circuitry Command Register 1 and Command Register 2 contain bits that control the operation modes of the A D and D A circuitry Command Register 3 enables or disables interrupt operations Use Command Register
120. mming update mode of analog output circuitry 3 19 to 3 20 Counter 0 Data Register DAQ operation using internal timing 3 8 description 2 27 performing single A D conversion 3 7 programming 3 10 Counter A1 Data Register DAQ operations using internal timing 3 8 description 2 27 programming 3 11 Counter 2 Data Register description 2 28 programming update mode of analog output circuitry 3 20 Counter B Mode Register 2 31 Counter BO Data Register DAQ operations using internal timing 3 9 description 2 29 programming 3 10 Counter B1 Data Register DAQ operations using internal timing 3 8 to 3 9 description 2 30 programming 3 11 to 3 12 Counter B2 Data Register 2 30 National Instruments Corporation OKI 5 82 53 data sheet C 1 overview 2 26 programming general purpose counter timers 3 19 to 3 20 register map 2 2 Timer Interrupt Clear Register DAC interrupt programming 3 20 description 2 29 82 55 Digital I O Register Group Digital Control Register 2 34 OKI 5 82 55 data sheet D 1 overview 2 32 Port A Register 2 33 Port B Register 2 33 Port C Register 2 34 register map 2 3 A A D conversions single See single A D conversions programming A D FIFO Clear Register clearing analog input circuitry 3 5 description 2 23 programming DAQ operation 3 14 A D FIFO Register description 2 21 to 2 22 obtaining A D conversion results 3 7 overflow condition 3 13 servicing D
121. mory required to store one byte of data binary coded decimal a number system with a base of 2 a signal range that includes both positive and negative values for example 5 V to 5 V the group of conductors that interconnect individual circuitry in a computer Typically a bus is the expansion vehicle to which I O or other devices are connected Examples of PC buses are the ISA and PCI bus Celsius calibration DAC calibration DAC load bit complementary metal oxide semiconductor counter interrupt status bit counter interrupt enable bit control word digital to analog digital to analog converter an electronic device often an integrated circuit that converts a digital number into a corresponding analog voltage or current DACO unipolar bipolar bit DAC unipolar bipolar bit data acquisition 1 collecting and measuring electrical signals from sensors transducers and test probes or fixtures and inputting them to a computer for processing 2 collecting and measuring the same kinds of electrical signals with A D and or DIO boards plugged into a computer and possibly generating control signals with D A and or DIO boards in the same computer data available bit decibel the unit for expressing a logarithmic measure of the ratio of two signal levels dB 20log10 V1 V2 for signals in volts direct current differential mode an analog input consisting of two terminals both of which are isolated from computer ground whose
122. n Chapter 2 Register Map and Descriptions DACO Low Byte DACO High Byte DAC1 Low Byte and DAC1 High Byte Registers Write to DACO Low Byte and then to DACO High Byte to load DACO Write to DACI Low Byte and then to DAC High Byte to load DACI If you clear the LDACx bit in Command Register 2 then the corresponding analog output channel is updated immediately after you write to the DACx High Byte register If you set the LDACx bit then the corresponding analog output channel is updated when an active low pulse occurs on the output of counter 2 or on the EXTUPDATE line on the I O connector Address 04 hex DACO Low Byte 05 hex DACO High Byte 06 hex DACI Low Byte 07 hex DACI High Byte Type Write only all Word Size 8 bit all Bit Map DACxH 7 6 5 4 3 2 1 0 D15 D14 D13 D12 D11 D10 D9 D8 DACxL 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 DO Bit Name Description DACxH 7 4 D lt 15 12 gt Data Zero in straight binary mode sign extension in two s complement mode 3 0 D lt 11 8 gt Data These four bits are loaded into the specified DAC high byte DACxL 7 0 D 7 0 Data These eight bits are loaded into the specified DAC low byte should be loaded first followed by the corresponding high byte National Instruments Corporation 2 25 Lab PC 1200 Al RLPM Chapter 2 Register and Descriptions 820653 Counter Timer Register Groups a
123. n mode 4 Counting is L Level Falling Edge Rising Edge Counting not possible Counting possible Start of counting Retriggering Counting not possible rt of ti Counti ossibl Counter output forced to H level Start of counting ounting possible eo Counting not possible t of nti Counting possible Counter output forced to H level Start of counting g possi Counting not possible Counting possible Start of counting Retriggering n 4 n 2 3 2 1 0 2 1 0 OUT GATE Hi WR 4 i 1 1 GATE l 4 4 4 4 3 2 1 0 OUT 261 Lab PC 1200 Al RLPM C 10 National Instruments Corporation Appendix C OKI MSM82C53 Data Sheet O MSM82C53 2RS GS JS WR l 4 l 2 4 3 2 1 4 3 2 1 2 1 2 OUT GATE H l l f l GATE l f 4 3 2 1 4 4 3 2 1 OUT 4 l f l wa Lal Lin 3 4 2 4 2 4 2 4 2 3 2 3 3 LOSUO L l 5 4 2 5 2 5 4 2 5 2 4 OUT 5 l l OUT GATE H l l f 4 4 3 2 1 0 OUT 5 4 3 2 1 0 OUT Ins 4 l f GATE 4 3 2 1 4 3 2 1 0 OUT 4 Note n is the value set in the counter Figures in these diagrams refer to counter values 262 National Instruments Corporation C 11 Lab PC 1200 Al RLPM Appendix C MSM82C53 Data Sheet Reading of Counter Values
124. nal Instruments if errors are suspected In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it EXCEPT AS SPECIFIED HEREIN NATIONAL INSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE CUSTOMER S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA PROFITS USE OF PRODUCTS OR INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control The warranty provided herein does not cover damages defects malfunctions or service failures caused by owner s failure to follow the National Instruments installation operation or maintenance instructions owner s modification of the product owner s abuse misuse or negligent acts and power failure or surges fire flood accident actions of third parties or other eve
125. nalog input range Table 1 1 lists the available analog I O configurations for the Lab PC 1200 AI and shows the default settings Table 1 1 Analog Input Settings Parameter Configuration Analog Input Range Bipolar 5 V default settings Unipolar 0 to 10 V Analog Input Mode Referenced single ended RSE default setting Nonreferenced single ended NRSE Differential DIFF The analog input circuitry is software configurable Analog Output Configuration Lab PC 1200 Only At startup the two channels of analog output of the Lab PC 1200 default to the following configuration e 5 V analog input range Table 1 2 lists the available analog I O configurations for the Lab PC 1200 and shows the default settings Table 1 2 Analog Output Settings Parameter Configuration Analog Output Range Bipolar 5 V default settings Unipolar O to 10 V Lab PC 1200 Al RLPM 1 2 National Instruments Corporation Chapter 1 General Description The analog output circuitry is software configurable Digital 1 0 Configuration The Lab PC 1200 AI uses the MSM82C55A PPI which provides 24 digital lines in the form of three ports A B and C On power up all three ports reset to mode 0 input Appendix D OKI MSM62C55A Data Sheet has the 82 55 data sheets that you need to program the digital I O Counter Configuration You can use the MSM82C53 counter timers for general purpo
126. nce to program for immediate update mode 1 Clear the LDACI or LDACO bit in Command Register 2 2 Wirite the low byte to the DACO or DACI Low Byte Register 3 Write the high byte to the DACO or DACI High Byte Register The analog output voltage is updated immediately after you write the high byte to the DACO or DACI High Byte Register Use the following sequence to program for update on OUTA2 or EXTUPDATE 1 Setthe LDACI or LDACO bit in Command Register 2 2 Setthe CNTINTEN bit in Command Register 3 to enable timer interrupts Program counter A2 4 Service the interrupts for waveform generation You must program counter 2 even if you are using EXTUPDATE If you are using EXTUPDATE you must set OUTA2 high to enable updates caused by EXTUPDATE If you are using counter A2 do not drive EXTUPDATE externally or if you do drive it high You can not block EXTUPDATE through software The clock for counter 2 is the same as that used for counter so you can use a 1 MHz clock or the output of counter BO to clock counter A2 The update period is equal to the value programmed into counter A2 times the period of the clock You should set the update period to be longer than the time it takes to write a new value to the DAC Registers Use the following sequence to program counter A2 1 Write OxB4 select counter A2 mode 2 to the Counter A Mode Register i Note Continue to steps 2 and 3 if you are using counter A2 to up
127. nd write operations by setting this bit You can disable the EEPROM by clearing this bit Notice that this bit is inverted on the Lab PC 1200 AI to make EEPROMCS as explained in Chapter 5 Calibration in your Lab PC 1200 AI User Manual 6 SDATA Serial Data This bit is a serial data input for both the calibration DACs and the EEPROM 5 SCLK Serial Clock This bit is a serial clock for both the calibration DACs and the EEPROM A low to high transition of this bit clocks data into the EEPROM during a write operation and the calibration DAC A high to low transition of the bit clocks data out of the EEPROM during a read operation 4 CALDACLD Calibration DAC Load This bit updates the calibration DACs After you load the calibration DAC address data set CALDACLD high to update the selected CALDAC output signal 3 DITHEREN Dither Enable This bit enables or disables the dither National Instruments Corporation circuitry When you set this bit 0 5 LSB of white Gaussian noise is added to the selected analog input signal By enabling dither and using averaging you can achieve greater input resolution 2 13 Lab PC 1200 Al RLPM Chapter 2 Register Map and Descriptions 2 WRTPRT Write Protect This bit controls the write protect input signal for the EEPROM When you set this bit you enable normal write operations When you clear this bit you disable write operations 1 0 0 Always leave these bits cleared Lab PC
128. nd B The nine registers of the two counter timer register groups access the two onboard 82C53 counter timers Each 82C53 has three counters For convenience the two counter timer groups and their respective 82C53 integrated circuits have been designated A and B The three counters of group A control onboard DAQ timing and waveform generation You can use the three counters of group B for general purpose timing functions Each 82C53 has three independent 16 bit counters and one 8 bit Mode Register The Mode Register sets the mode of operation for each of the three counters Writing to the Timer Interrupt Clear Register clears the interrupt request asserted when a low pulse is detected on the output of counter A2 or on the line Bit descriptions for the registers in the Counter Timer Register Groups are in the following pages Lab PC 1200 Al RLPM 2 26 National Instruments Corporation Chapter 2 Register Map and Descriptions Counter A0 Data Register Use the Counter AO Data Register to write data and read back the contents of 82C53 A counter 0 Counter 0 is the sample interval counter for a operation Address 14 hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 DI DO Bit Name Description 7 0 D lt 7 0 gt Data 8 bit counter AO contents Counter A1 Data Register Use the Counter A1 Data Register to write data and read b
129. nd writes data lower 8 bits D7 to DO of the shift register into an internal data latch selected by the latched address Serial address data input to the internal 12 bit shift register The address data format is thatupper 4 bits D11 to D8 indicate an address and lower 8 bits D7 to DO indicate data The 011 MSB is the first in bit and DO LSB is the last in bit Serial address data output from the internal 12 bit shift register This is an output pin of the MSB bit data of the 12 bit shift register This pin allows a cascade connection of the device 8 bit resolution D A converter outputs MB88341 12 channels AO1 to AO12 MB88342 8 channels AO1 to AO8 Note Pin numbers in parentheses are applied to MB88342 PFV 7 120 National Instruments Corporation A 5 Lab PC 1200 Al RLPM Appendix Fujitsu 88341 88342 Data Sheet MB88341 MB88342 FUNCTIONAL DESCRIPTION OVERVIEW The MB88341 and 88342 are R 2R resistor ladder type 8 bit resolution digital to analog converter DAC devices The MB88341 has 12 channels and MB88342 has 8 channels of D A converters 8 bit digital data are loaded into internal data latches by individual DAC channel units The loaded digital data are converted into analog DC voltages through the internal D A converter in 60 us settling time For cascade connection a serial data output is provided DEVICE CONFIGURATION As illustrated in Figure 3 block diagram
130. ns 3 7 programming Counter and Counter B0 3 10 OUTA bit 2 19 signal DAC interrupt programming 3 20 programming update mode of analog output circuitry 3 19 OUTBI for programming DAQ operation 3 15 OVERFLOW bit clearing analog input circuitry 3 5 description 2 18 overflow condition in DAQ operations 3 13 single A D conversions 3 7 OVERRUN bit clearing analog input circuitry 3 5 description 2 18 overflow condition in DAQ operations 3 13 single A D conversions 3 7 Lab PC 1200 Al RLPM 1 8 polarity selecting analog input circuitry 3 5 to 3 6 analog output circuitry 3 17 to 3 18 Port A Register 2 33 Port B Register 2 33 Port C Register 2 34 PRETRIG bit description 2 8 programming DAQ operation in pretrigger mode 3 15 programming See also registers analog input circuitry for single A D conversions 3 4 to 3 7 clearing analog input circuitry 3 4 to 3 5 configuring analog input circuitry 3 5 to 3 6 performing single A D conversions 3 7 analog output circuitry 3 17 to 3 20 configuring analog output circuitry 3 17 to 3 18 DAC interrupt programming 3 20 update mode of analog output circuitry 3 18 to 3 20 assigning Lab PC 1200 AI resources 3 2 DAQ DMA programming 3 17 DAQ interrupt programming 3 16 DAQ operation using external timing 3 13 to 3 15 EXTCONV instead of Counter AO 3 14 EXTTRIG in posttrigger mode 3 14 EXTTRIG in pretrigger mode 3 15 OUTBI instead of Counter
131. ns the manufacturer data sheet for the 5 82 53 CMOS programmable interval timer manufactured by OKI Semiconductor Inc This counter timer is used on the Lab PC 1200 AI 1 Copyright OKI Semiconductor Inc Reprinted with permission of copyright owner rights reserved OKI Semiconductor Microprocessor Data Book 1993 National Instruments Corporation C 1 Lab PC 1200 Al RLPM Appendix C OKI MSM82C53 Data Sheet OKI semiconductor MSM82C53 2RS GS JS CMOS PROGRAMMABLE INTERVAL TIMER GENERAL DESCRIPTION The MSM82C53 2RS GS JS are programmable universal timers designed for use in microcomputer syste ms Based on silicon gate CMOS technology it requires a standby current of only 1004A max when the chip is in the nonselected state During timer operation power consumption is still very low with only 8 mA at 8 MHz of current required The devices consist of three independent counters and can count up to a maximum of 8 MHz 5 82 53 2 The timer features six different counter modes and binary count BCD count functions Count values can be set in byte or word units and all functions are freely programmable FEATURES Maximum operating frequency of 8 MHz MSM82C53 2 Six counter modes available for each counter High speed and low power consumption achieved Binary and decimal counting possible through silicon gate CMOS technology 24 pin Plastic DIP DIP24 P 600 Completely static operation
132. nts outside reasonable control Under the copyright laws this publication may not be reproduced or transmitted in any form electronic or mechanical including photocopying recording storing in an information retrieval system or translating in whole or in part without the prior written consent of National Instruments Corporation LabVIEW NI DAQ and SCXI are trademarks of National Instruments Corporation Product and company names listed are trademarks or trade names of their respective companies WARNING REGARDING MEDICAL AND CLINICAL USE OF NATIONAL INSTRUMENTS PRODUCTS National Instruments products are not designed with components and testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans Applications of National Instruments products involving medical or clinical treatment can create a potential for accidental injury caused by product failure or by errors on the part of the user or application designer Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified medical personnel and all traditional medical safeguards equipment and procedures that are appropriate in the particular situation to prevent serious injury or death should always continue to be used when National Instruments products are being used National Instruments products are NOT intended to be a substitute for a
133. nts taken from programs NI DAQ NI DAQ is used in this manual to refer to the NI DAQ driver software unless otherwise noted PC PC refers to all PC compatible computers with PCI bus unless otherwise noted SCXI SCXI stands for Signal Conditioning eXtensions for Instrumentation and is a National Instruments product line designed to perform front end signal conditioning for National Instruments plug in DAQ boards National Instruments Documentation The Lab PC 1200 AI Register Level Programmer Manual is one piece of the documentation set for your DAQ system You could have any of several types of manuals depending on the hardware and software in your system Use the different types of manuals you have as follows e Getting Started with SCXI If you are using SCXI this is the first manual you should read It gives an overview of the SCXI system and contains the most commonly needed information for the modules chassis and software e Your SCXI hardware user manuals If you are using SCXI read these manuals next for detailed information about signal connections and module configuration They also explain in greater detail how the module works and contain application hints e Your DAQ hardware user manuals These manuals have detailed information about the DAQ hardware that plugs into or is connected to your computer Use these manuals for hardware installation and configuration instructions specification information about your D
134. ny form of established process procedure or equipment used to monitor or safeguard human health and safety in medical or clinical treatment Contents About This Manual Organization of This ix Conventions Used in This 2 4441 1 enne X National Instruments Documentation essere eene ener xi Related Documentation ete tie temet ORE THER FIR eee coe xii Customer entente nennen tette terere treni eene xii Chapter 1 General Description General Characteristics ie en e at e OO e rb Deer Dr co IE pede 1 1 Board Configuration Overview 1 2 Analog Input Configuration 1 2 Analog Output Configuration Lab PC 1200 Only 1 2 Digital I O Configuration tete pte ipti 1 3 Counter Configuration ette ebd ceteri deb detis e entire e teeth tiii 1 3 Chapter 2 Register Map and Descriptions Register Map reete ep Pee tinere pietre rie E e em 2 1 Register Description Overview treten nennen 2 3 Configuration and Status Register Group 2 4 Command Register 1 essere nennen 2 5 Command Register 2 eoe tete EE 2 7 Command Register EE 2 9 Command Register 4 Loose eene tpe t erg reed 2 11 Command Register 3 2 ciet ie rette EEN 2 13 Command Register 6
135. o the EEPROM For information on user areas in the EEPROM refer to the EEPROM memory map at the end of this chapter 1 Set the EEPROMCS and WRTPRT bits in Command Register 5 2 Serially write the WRITE instruction 0x06 to the EEPROM to enable a write operation 3 Clear the EEPROMCS bit in Command Register 5 4 Setthe EEPROMCS bit in Command Register 5 5 Serially write the WRITE instruction 0x02 to the EEPROM to start a write operation Serially write the 8 bit user area address to the EEPROM Serially write the 8 bit calibration constant to the EEPROM 8 Clear EEPROMCS and WRTPRT bits in Command Register 5 Repeat the following two steps eight times to serially write one byte to the EEPROM 1 Clearthe SCLK bit in Command Register 5 Write a single bit of the 8 bit value MSB first by setting or clearing the SDATA bit in Command Register 5 2 Setthe SCLK bit in Command Register 5 4 2 National Instruments Corporation Chapter 4 Calibration After you store a single calibration constant you must wait a minimum of 10 ms before accessing the EEPROM again Alternatively you may use the RDSR Read status register instruction of the X25020 and poll the WIP write in process bit If this bit is 1 then the previous write is still in progress You must wait until this bit reads 0 then you may proceed with the next write Calibration DACs There are eight 8 bit calibration DACs CALDACs on the Lab PC
136. o write data and read back the contents of 82C53 B counter 2 Counter B2 is reserved for external usage Address 1A hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 D7 D6 D6 D4 D3 D2 DI DO Bit Name Description 7 0 D lt 7 0 gt Data 8 bit counter B2 contents Lab PC 1200 Al RLPM 2 30 National Instruments Corporation Chapter 2 Register Map and Descriptions Counter B Mode Register The Counter B Mode Register determines the operation mode for each of the three counters on the 82C53 B chip The Counter B Mode Register selects the counter involved its read write mode its operation mode that is any of the 82C53 six operation modes and the counting mode binary or BCD counting The Counter Mode Register is an 8 bit register Bit descriptions for each of these bits are in Appendix C MSM82C53 Data Sheet Address 1B hex Type Write only Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 SCI SCO RLI RLO M2 MI BCD National Instruments Corporation 2 31 Lab PC 1200 Al RLPM Chapter 2 Register and Descriptions 82C55A Digital 1 0 Register Group The four registers of the Digital I O register group access the 82 55 peripheral interface The 82 55 is a general purpose peripheral interface containing 24 programmable I O pins These pins represent the three 8 bit I O ports A B and C of the 82 55 and the 24 di
137. onnector as an output signal If you set this bit OUTBI on the I O connector is selected as an input signal and allows you to externally drive the interval scanning circuitry Interval Scan This bit selects the DAQ mode When you set this bit the Lab PC 1200 AI performs interval data acquisition If you clear this bit freerun or controlled data acquisition occurs For an explanation of the different modes refer to Chapter 4 Theory of Operation in the Lab PC 1200 AI User Manual Also this bit selects the clock source for counter used in interval scanning If interval scanning is disabled INTSCAN 0 then counter is available for user applications You can then drive CLKBI externally at the I O connector If interval scanning is enabled INTSCAN 1 the clock source of counter 0 also drives CLKB1 This source can further be selected by using the TBSEL bit in Command Register 2 2 12 National Instruments Corporation Command Register 5 Chapter 2 Register Map and Descriptions Use Command Register 5 for software calibration of the A D and D A circuitry for interaction with the EEPROM and for enabling dither Address 1C hex Type Write only Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 EEPROMCS SDATA SCLK CALDACLD DITHEREN WRTPRT 0 0 Bit Name Description 7 EEPROMCS EEPROM Chip Select This bit enables and disables the EEPROM You can enable the EEPROM for both read a
138. or example to read the 16 bit A D conversion result you must make two consecutive 8 bit readings of the FIFO The first reading returns the low byte of the 16 bit data and the second returns the high byte of the data National Instruments Corporation 2 1 Lab PC 1200 Al RLPM Chapter 2 Register Map and Descriptions Table 2 1 Lab PC 1200 Al Register Address Offset Register Name Hex Type Size Configuration and Status Register Group Command Register 1 00 Write only 8 bit Command Register 2 01 Write only 8 bit Command Register 3 02 Write only 8 bit Command Register 4 Write only 8 bit Command Register 5 1 Write only 8 bit Command Register 6 Write only 8 bit Status Register 1 00 Read only 8 bit Status Register 2 ID Read only 8 bit Analog Input Register Group A D FIFO Register 0A Read only 8 bit A D FIFO Clear Register 08 Write only 8 bit CONFIGMEM Register 03 Write only 8 bit DMA TC Interrupt Clear Register 0A Write only 8 bit Analog Output Register Group DACO Low Byte Register 04 Write only 8 bit DACI1 High Byte Register 05 Write only 8 bit DAC1 Low Byte Register 06 Write only 8 bit DACI1 High Byte Register 07 Write only 8 bit 82C53 Counter Timer Register Group A Counter Data Register 14 Read Write 8 bit Counter A1 Data Register 15 Read Write 8 bit Counter A2 Data Register 16 Read Write 8 bit Counter A Mode Register 17 Write only 8 bit Timer Interrupt Cl
139. ory Gain 100 bipolar value gain 163 00 0 Factory Gain 1 bipolar value offset 162 00 0 Factory Gain 1 25 bipolar value offset 161 00 0 Factory Gain 2 bipolar value offset 160 00 0 Factory Gain 5 bipolar value offset 159 00 0 Factory Gain 10 bipolar value offset 158 00 0 Factory Gain 20 bipolar value offset 157 00 0 Factory Gain 50 bipolar value offset 156 00 0 Factory Gain 100 bipolar value offset 155 00 0 Factory AI CALDACO unipolar value 154 00 0 Factory AI CALDACI unipolar value National Instruments Corporation 4 11 Lab PC 1200 Al RLPM Chapter 4 Calibration Table 4 3 Lab PC 1200 Al EEPROM Map Continued Location Hex Decimal Description 153 00 0 Factory AI CALDAC2 unipolar value 152 00 0 Factory AI CALDAC3 unipolar value 151 00 0 Factory AO CALDAC4 unipolar value 150 00 0 Factory AO CALDACS unipolar value 149 00 0 Factory AO CALDAC6 unipolar value 148 00 0 Factory AO CALDAC7 unipolar value 147 00 0 Factory Gain 1 unipolar value gain 146 00 0 Factory Gain 1 25 unipolar value gain 145 00 0 Factory Gain 2 unipolar value gain 144 00 0 Factory Gain 5 unipolar value gain 143 00 0 Factory Gain 10 unipolar value gain 142 00 0 Factory Gain 20 unipolar value gain 141 00 0 Factory Gain 50 unipolar value gain 140 00 0 Factory Gain 100 unipolar value gain 139 00 0 Factory Gain 1 unipolar value offset 138 00 0 Factory Gain 1 25 unipolar value offset
140. pport National Instruments has BBS and FTP sites dedicated for 24 hour support with a collection of files and documents to answer most common customer questions From these sites you can also download the latest instrument drivers updates and example programs For recorded instructions on how to use the bulletin board and FTP services and for BBS automated information call 512 795 6990 You can access these services at United States 512 794 5422 Up to 14 400 baud 8 data bits 1 stop bit no parity United Kingdom 01635 551422 Up to 9 600 baud 8 data bits 1 stop bit no parity France 01 48 65 15 59 Up to 9 600 baud 8 data bits 1 stop bit no parity FTP Support To access our FTP site log on to our Internet host ftp natinst com aS anonymous and use your Internet address such as joesmith anywhere com as your password The support files and documents are located in the support directories National Instruments Corporation E 1 Lab PC 1200 Al RLPM Fax on Demand Support Fax on Demand is a 24 hour information retrieval system containing a library of documents on a wide range of technical information You can access Fax on Demand from a touch tone telephone at 512 418 1111 E Mail Support Currently USA Only You can submit technical support questions to the applications engineering team through e mail at the Internet address listed below Remember to include your name address and phone number so we can contact you with sol
141. put Input Input 4 Input Input Output Output Input Input Output Input ojlo ojojo ojoj o o o Input Input Input Output 4 alato Input Note When used in mode for both groups A and B National Instruments Corporation D 11 Input Input Input 287 Lab PC 1200 Al RLPM Appendix D OKI MSM82C55A Data Sheet O MSM82C55A 2RS GS VJS 1 1 22 2 Mode 1 Strobe input output operation In mode 1 the strobe interrupt and other control signals are used when input output operations are made from a specified port This mode is available for both groups A and B In group A at this time port A is used as the data line and port C as the con trol signal Following is a descrption of the input operation in mode 1 STB Strobe input When this signal is low level the data output from terminal to port is fetched into the internal latch of the port This can be made independent from the CPU and the data is not output to the data bus until the RD signal arrives from the CPU IBF Input buffer full flag output This is the response signal for the STB This signal when turned to high level indicates that data is fetched into the input latch This signal turns to high level at the falling edge of STB and to
142. r CALDACS 3 10 in EEPROM addresses 117 110 then store the seven gain constants for CALDAC6 in EEPROM locations 109 102 followed by the seven postgain offset values for each gain in locations 101 94 Table 4 3 shows the Lab PC 1200 AI EEPROM map National Instruments Corporation 4 1 Lab PC 1200 Al RLPM Chapter 4 Calibration Lab PC 1200 Al RLPM Note that the location for gain 1 25 is provided however the corresponding value is ignored Also note that within each user area the AI CALDAC 3 value is the analog input gain calibration constant for the gain at which the calibration is performed This value must also be duplicated in the corresponding location in the GAIN X value in that user area For example if the calibration is performed at gain 5 then the calibration constant must be written in both locations 114 and 106 for user area 1 Similarly the postgain offset value for that gain must be duplicated in the corresponding GAIN X value offset location When the Lab PC 1200 AI is shipped the contents of factory area for bipolar mode are copied in all the user areas Consequently there will be constants in the user areas that will be very accurate when the Lab PC 1200 AI is used in the bipolar mode for both analog input and output To save your user defined calibration constants in the EEPROM you need programming instructions for writing to the EEPROM Use the following sequence of steps to store a calibration constant t
143. reading single byte from EEPROM 3 7 storing user defined constants 4 2 X Xicor X25020 data sheet B 1 National Instruments Corporation
144. red scanning order 2 Setthe gain and the highest channel number in the scan sequence in Command Register 1 Clear the SCANEN bit during this first write to Command Register 1 3 Write to Command Register 1 again but this time set SCANEN bit This latches the channel number into the scan counter You must write all other bits in Command Register 1 as you did in the first write which set the gain and highest channel number 3 6 National Instruments Corporation Chapter 3 Programming Performing Single A D Conversions After configuring the analog input circuitry you can perform single A D conversions and then read the conversion result from the A D FIFO Perform the following steps 1 Set counter AO so that OUTAO is high 2 Initiate a conversion by writing to the Start Convert Register 3 Read the conversion result from the A D FIFO You must program counter so that OUTAO is high You can do this by writing 0 14 select counter AO mode 2 to Counter A Mode Register This enables the conversions initiated by writing to the Start Convert Register Initiate a conversion by writing to the Start Convert Register When you initiate an A D conversion the ADC stores the result in the A D FIFO at the end of its conversion cycle approximately 10 us later You can acquire a specific number of samples by writing to the Start Convert Register that same number of times In multiple channel data acquisition the hardware scans
145. register However writing to these registers affects all register bits simultaneously Because you cannot read these registers to determine their current status you should maintain a software copy of the write only registers To change the state of a single bit without disturbing the remaining bits set or clear the bit in the software copy and then write the modified software copy to the register Programming Examples The programming examples in this section demonstrate the programming steps needed to perform several different operations The instructions are language independent that is they tell you to read or write a given register or to detect if a given bit is set or cleared without presenting the actual code The information given is not intended to be used without proper modification in a practical solution National Instruments Corporation 3 1 Lab PC 1200 Al RLPM Chapter 3 Programming Before you can implement any of the examples into a real application you must know the base memory address for your board To process any interrupts you must write and install an applicable interrupt service routine Note In this chapter all numbers preceded by 0 are hexadecimal Common terms that you will see used in the programming examples are listed below Write address data Generic function call for a I O space Write of data to address Read address Generic function call for a I O space Read from address Lab PC 1200
146. rrupt if you set CNTINTEN in Command Register 3 Clear this bit by writing to the Timer Interrupt Clear Register 2 17 Lab PC 1200 Al RLPM Chapter 2 Register Map and Descriptions Lab PC 1200 Al RLPM OVERFLOW OVERRUN DAVAIL Overflow This bit indicates if an overflow error has occurred If this bit is cleared no error was encountered If this bit 1s set the A D FIFO has overflowed because the DAQ servicing operation could not keep up with the sampling rate Overrun This bit indicates if an overrun error has occurred If this bit is cleared no error occurred This bit 16 set if a convert command is issued to the while the last conversion is still in progress Data Available This bit indicates if conversion output is available If this bit is set the ADC is finished with the last conversion and the result can be read from the FIFO This bit is cleared if the FIFO is empty 2 18 National Instruments Corporation Chapter 2 Register Map and Descriptions Status Register 2 Status Register 2 reports the status of a DAQ operation and the FIFO half full output and gives access to the output of the EEPROM Address 1D hex Type Read only Word Size 8 bit Bit Map SE 6 5 4 3 2 1 0 X X X X X FIFOHF OUTAI PROMOUT Bit Name Description 7 3 X Don t care bits 2 FIFOHF FIFO Half Full This bit indicates the status of the FIFO half full output If this bit is low th
147. ry 3 19 to 3 20 unipolar output calibration procedure 4 10 DACOUNI BI bit Lab PC 1200 Al RLPM Index configuring analog output circuitry 3 17 description 2 16 DACIUNI BI bit configuring analog output circuitry 3 17 description 2 15 DAQ interrupt programming 3 16 DAQ operation programming controlled data acquisition mode 3 8 definition of DAQ operation 3 8 freerun data acquisition mode 3 8 interval scanning data acquisition mode 3 8 to 3 9 using external timing 3 13 to 3 15 EXTCONV instead of Counter AO 3 14 in posttrigger mode 3 14 in pretrigger mode 3 15 OUTBI instead of Counter 3 15 using internal timing 3 8 to 3 13 Counter AO and Counter BO 3 10 Counter A1 3 11 Counter B1 and Interval Counter Register 3 11 to 3 12 servicing DAQ operation 3 12 to 3 13 triggering DAQ operation 3 12 DAVAIL bit clearing analog input circuitry 3 5 description 2 18 single A D conversions 3 7 Digital Control Register 2 34 digital I O circuitry configuration 1 3 programming 3 20 DIOINTEN bit 2 10 DITHEREN bit analog input calibration 4 5 description 2 13 DMA programming 3 17 DMAEN bit DAQ DMA programming 3 16 Lab PC 1200 Al RLPM description 2 10 DMATC bit 2 17 DMATC Interrupt Clear Register 2 23 documentation conventions used in manual x xi National Instruments documentation xi xii organization of manual ix x related documentation xii DQINTEN bit DAQ int
148. s an output port it is pos Available for both groups A and B sible to set to turn to high level or reset to turn to Mode 2 Bidirectional bus operation low level any one of 8 bits individually without affect Available for group A only National Instruments Corporation ing other bits 285 MSM82C55A Data Sheet Lab PC 1200 Al RLPM Appendix D OKI MSM82C55A Data Sheet O MSM82C55A 2RS GS VJS i OPERATIONAL DESCRIPTION Control Logic Operations by addresses and control signals e g read and write etc are as shown in the table below Setting of Contro Word The control register is composed of 7 bit latch circuit and 1 bit flag as shown below E 0 0 0 1 Port Data Bus Input 0 1 0 1 Port B gt Data Bus 1 0 0 1 Port C gt Data Bus 0 0 0 0 1 Data Bus gt Port A Output 0 1 0 0 1 Data Bus gt Port B 1 0 0 0 1 Data Bus gt Control 1 1 0 0 1 Data Bus Contro Register 1 1 0 1 0 Illegal Condition Others x 1 Tox Data bus is in the high impedance status Group A Control Bits Group B Control Bits Definition of input Definition of input output of low order 4 bits of port C 0 Output 1 Input Definition of input output of 8 bits of port B Output 1 Input Mode definition 9
149. se applications such as pulse and square wave generation event counting and pulse width time lapse and frequency measurement Appendix C OKI MSM82C53 Data Sheet has 82C53 data sheet that you need to program the counters timers National Instruments Corporation 1 8 Lab PC 1200 Al RLPM Register Map and Descriptions This chapter describes in detail the address and function of each of the Lab PC 1200 AI registers Register Map Table 2 1 shows the register map for the Lab PC 1200 AI and lists the register name address type read only write only or read write and size in bits Table 2 1 divides the Lab PC 1200 AI registers into seven groups The Configuration and Status Register Group controls the overall operation of the Lab PC 1200 AI The Analog Input Register Group reads output from the 12 bit successive approximation ADC and can initiate conversions The Analog Output Register Group accesses the two 12 bit DACs on the Lab PC 1200 only The two Counter Timer Register Groups A and B access each of the two onboard 82C53 counter timer integrated circuits The Digital I O Register Group consists of the four registers of the onboard 82 55 PPI integrated circuit that are used for digital I O The Interval Counter registers are used in single channel interval scanning acquisition The Lab PC 1200 AI registers are 8 bit registers To transfer 16 bit data you must perform two consecutive memory readings or writings F
150. seeseseeeesesresssrssesrssesresrerrrreerrressesesee 4 7 Analog Output Calibration Lab PC 1200 Online 4 8 Bipolar Output Calibration Procedure seen 4 8 Gain Calbration cem cte chs e o eR ERR D 4 0 Offset Calibration i atero tient td e rer tit eei 4 9 Unipolar Output Calibration Procedure eee 4 9 Gain mtem ped 4 10 Offset Calibrations ci ace tete eR ee 4 10 erans Re omes 4 10 Appendix A Fujitsu MB88341 MB88342 Data Sheet Appendix B Xicor X25020 Data Sheet Appendix C OKI MSM82C53 Data Sheet National Instruments Corporation Vii Lab PC 1200 Al RLPM Contents Appendix D OKI MSM82C55A Data Sheet Appendix E Customer Communication Glossary Index Tables Table 1 1 Analog Input Settings 0 eee ee 1 2 Table 1 2 Analog Output Senge 1 2 Table 2 1 Lab PC 1200 AI Register Map 2 2 Table 3 1 Lab PC 1200 AI Allowable Resources eee 3 2 Table 3 2 Analog Output Voltage Versus Digital Code Unipolar Mode Straight Binary Coding sees 3 18 Table 3 3 Analog Output Voltage Versus Digital Code Bipolar Mode Two s Complement Coding sess 3 18 Table 4 1 Calibration DAC Characteristics for Analog Input Circuitry 4 3 Table 4 2 Calibration DAC Characteristics for Analog Output Circuitry
151. shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace equipment that proves to be defective during the warranty period This warranty includes parts and labor The media on which you receive National Instruments software are warranted not to fail to execute programming instructions due to defects in materials and workmanship for a period of 90 days from date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period National Instruments does not warrant that the operation of the software shall be uninterrupted or error free A Return Material Authorization RMA number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty National Instruments believes that the information in this manual is accurate The document has been carefully reviewed for technical accuracy In the event that technical or typographical errors exist National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition The reader should consult Natio
152. sion is initiated before the previous conversion is finished This condition may result in one or more missing A D conversions This condition occurs if the sample interval is smaller than the conversion time of the ADC which is 10 us Programming a DAQ Operation Using External Timing You can use three external timing signals EXTTRIG EXTCONV and to time DAQ operation Use EXTTRIG to initiate a DAQ operation posttrigger mode or to terminate an ongoing DAQ operation pretrigger mode In posttrigger mode you use EXTTRIG in place of writing to the SWTRIG bit in Command Register 2 Use the EXTCONV signal to time the individual A D conversions in place of counter 0 If you are performing an interval scanning DAQ operation and are timing the individual A D conversions using EXTCONV you must time the scan interval through OUTBI in place of using counter For signal specifications of these external timing signals see Chapter 3 Signal Connections in the Lab PC 1200 AI User Manual National Instruments Corporation 3 13 1200 RLPM Chapter 3 Programming a DAQ Operation Using EXTCONV Note If you want to use EXTCONV instead of counter AO for sample interval timing you can follow the same sequence of steps described in Programming a DAQ Operation Using Internal Timing except for programming counters 0 and BO Replace the steps for programming counters and BO with the following sequenc
153. sitions on EXTCONV will not effect data acquisition If you clear this bit a falling edge on EXTCONV initiates an A D conversion if ECLKDRV is cleared 3 SE DIFF Single Ended Differential This bit along with bit 0 of Command Register 6 RSE NRSE selects one of three analog input modes of the Lab PC 1200 AI You can select the single ended mode by clearing this bit and you can select the differential mode by setting this bit Refer to the Lab PC 1200 AI User Manual for an explanation of the different modes The following table illustrates how to choose the various input modes by using SE DIFF and RSE NRSE RSE NRSE SE DIFF Input Mode 0 0 RSE reset condition 1 0 NRSE X 1 DIFF National Instruments Corporation 2 11 Lab PC 1200 Al RLPM Chapter 2 Register Map and Descriptions Lab PC 1200 Al RLPM ECLKDRV EOIRCV INTSCAN External Clock Drive When you clear this bit default power up you can drive the EXTCONV pin at the I O connector to cause conversions if ECLKRCV is also cleared When you set this bit you enable internally timed conversions and the conversion pulses are driven onto the EXTCONV pin for synchronizing channels on SCXI modules if used with SCXI External Output Interval Clock Receive This bit selects the clock source for interval scanning If you clear this bit counter B1 drives the interval scanning circuitry This will also configure OUTBI on the I O c
154. st scan interval is not synchronized with counter B1 Therefore you may wish to discard the conversions acquired in the first scan interval Servicing the DAQ Operation Lab PC 1200 Al RLPM When you start a DAQ operation you must service the operation by reading the A D FIFO Register You can either read the A D FIFO every time a conversion is available or when the A D FIFO is half full You read the A D FIFO as explained in the section Performing Single A D Conversions You can also use interrupts to service the DAQ operation In order to process interrupts you must install an interrupt handler See Programming Options earlier in this chapter for information on installing interrupt handlers 3 12 National Instruments Corporation Chapter 3 Programming Two error conditions overflow or overrun may occur during a DAQ operation If these error conditions occur the OVERFLOW and or the OVERRUN bits are set in Status Register 1 Check these bits every time you read Status Register 1 to check the DAVAIL bit An overflow condition occurs if more than 4 096 A D conversions have been stored in the A D FIFO without the A D FIFO being read that is the A D FIFO is full and cannot accept any more data This condition occurs if the software loop reading the A D FIFO is not fast enough to keep up with the A D conversion rate When an overflow occurs at least one A D conversion result is lost An overrun condition occurs if a second A D conver
155. ster 6 and Command Register 4 respectively You determine the input polarity according to the voltage range of the analog input signal For more information about determining the input polarity consult the Lab PC 1200 AI User Manual The conversion coding should be selected according to the input polarity Select the input polarity by setting or clearing the ADCUNI BI bit in Command Register 6 Select the respective coding by setting or clearing the TWOSCMP bit in Command Register 1 If you will be performing single channel data acquisition select the desired analog channel and gain by setting or clearing the GAIN lt 2 0 gt and MA lt 2 0 gt bits in Command Register 1 You must also clear SCANEN in Command Register 1 If you will be doing multiple channel data acquisition set MA 2 0 to specify the highest numbered channel in the scan sequence Set or clear the SCANUP bit in Command Register 6 for the desired scanning order For example if you set MA 2 0 to 011 binary and clear the SCANUP bit the following scan sequence is used channel 3 channel 2 channel 1 channel 0 channel 3 channel 2 and 50 on If you set MA 2 0 to 011 binary and set the SCANUP bit the following scan sequence is used channel 0 channel 1 channel 2 channel 3 channel 0 channel 1 and 50 on Select the analog input channel and gain for multiple channel data acquisition in the following order 1 Setorclear the SCANUP bit for the desi
156. stored in the user areas of the Lab PC 1200 AI EEPROM Since the calibration process is quite complicated the user is advised to use NI DAQ whenever possible If NI DAQ does not support your operating system only then should you try to write register level code to perform calibration Also if you accidentally overwrite the factory area you will permanently lose factory calibration information and may have to send your unit back to National Instruments for recalibration Note National Instruments is not liable for accidental overwriting of the calibration EEPROM in the field For information concerning writing register level programs to write to the CALDACs refer to Chapter 3 Programming For information on calibration equipment requirements refer to the Lab PC 1200 AI User Manual Storing User Defined Constants You should store only one set of user defined calibration constants in one user area One set of calibration constants consists of twenty constants six for CALDACS 3 4 and 7 10 seven for CALDAC6 and seven for CALDACS one at each gain setting Therefore one set of calibration constants can calibrate the Lab PC 1200 AI analog input and analog output circuitry in either bipolar or unipolar polarity and at all gains Store your user defined calibration constants in the same format as that shown for the factory defined calibration constants in Table 4 1 For example if you use user area 1 store the calibration constants fo
157. t Calibration Procedure If your board is configured for bipolar input which provides the 5 to 5 V range complete the following procedures This procedure assumes that ADC readings are in the 2 048 to 42 047 range that is you have selected the two s complement coding scheme Because adjusting the gain affects the postgain offset adjustment you must calibrate gain before calibrating postgain offset Also initialize all of the CALDACS for analog input 3 4 5 and 6 to 128 before starting the calibration procedure This sets each CALDAC at midscale Pregain Offset Coarse Calibration 1 Connect ACHO pin 1 on the rear panel 50 pin I O connector to AGND pin 11 2 1 024 readings from channel 0 at a gain of 1 Take the mean of these readings and call it mean 3 Take 1 024 readings from channel 0 at a gain of 100 Take the mean of these readings and call it mean100 4 Adjust CALDAC3 so that mean100 pregain offset coarse calibration tolerance Pregain Offset Fine Calibration 1 Repeat steps 1 3 of the pregain offset coarse procedure 2 Adjust CALDAC4 so that 1 mean100 pregain offset fine calibration tolerance At this point the pregain offset is nulled out However there is a residual postgain offset remaining National Instruments Corporation 4 5 Lab PC 1200 Al RLPM Chapter 4 Calibration Gain Calibration 1 Take 1 024 samples from channel 0 still conne
158. t of the instrumentation amplifier e Offset error at the input of the ADC e Gain error of the analog input circuitry Offsets at the input to the instrumentation amplifier contribute gain dependent error to the analog input system This offset is multiplied by the gain of the instrumentation amplifier To calibrate this offset you must ground the inputs of the instrumentation amplifier measure the input at two different gains and adjust CALDAC3 and CALDAC4 until the measured offset in LSBs is independent of the gain setting Calibration of this pregain offset is done in bipolar mode for both bipolar and unipolar analog input configurations Offset error at the input of the ADC is the total of the voltage offsets contributed by the circuitry from the output of the instrumentation amplifier to the ADC input including the ADC s own offsets Offset errors appear as a voltage added to the input voltage being measured To calibrate this offset you must connect either AGND in bipolar mode or an external voltage source in unipolar mode to the inputs of the ADC and adjust CALDACS until the measured voltage is equal to either AGND or external voltage source gain error respectively If the three analog input offset DACs are adjusted in this way there is no significant residual offset error and reading a grounded channel returns on average less than 0 5 LSB regardless of the gain setting All the stages up to and including the input of th
159. ta Output Delay Time 70 Figure 10 Test Conditions O Test Point 7 129 Lab PC 1200 Al RLPM A 14 National Instruments Corporation Appendix Fujitsu MB88341 MB88342 Data Sheet MB88341 MB88342 Figure 11 Input Output Timing 8 Zeta 0 2 AO Ze Previous Data New Data Valid 7 130 National Instruments Corporation A 15 Lab PC 1200 Al RLPM Appendix PACKAGE DIMENSIONS 88341 Fujitsu MB88341 MB88342 Data Sheet MB88341 MB88342 20 LEAD PLASTIC DUAL IN LINE PACKAGE 9707 00824 64 INDEX 1 INDEX 2 034 912 0 86 19 30 050 1 27 _ 100 2 54 Case No DIP 20P M02 0 20 030 244 010 10 25 0 05 1 277330 172 4 36 118 3 00 MIN 018 003 020 0 51 MIN MAX TYP 1988 FUJITSU LIMITED 0200035 3C Lab PC 1200 Al RLPM 10 46 0 08 Dimensions in inches millimeters 4 16 7 131 National Instruments Corporation Appendix Fujitsu MB88341 MB88342 Data Sheet MB88341 MB88342 88341 20 LEAD PLASTIC FLAT PACKAGE Case No 20 01 089 2 25 MAX SEATED HEIGHT 01 0 25 5 0 00812 70 0 20 002 0 05 MIN 307 016 7 80 0 40 l 268 01616 80 049 209 012 00 0 20 o 5 30 0 30 LL 020 008 0 50 0 20 050 1 27 005 0 13 002 0 05 T 006 L 00100 15 0 02 001 020 0 50 450 11 43 R
160. ta after the rising edge of WR Delay Time from the rising edge of WR to the output of defined data Setup Time of port data before the falling edge of RD Hold Time of port data after the rising edge of RD ACK Pulse Width STB Pulse Width Setup Time of port data before the rising edge of 5 Hold Time of port data after the rising edge of STB L Delay Time from the falling edge of ACK to the output of defined data Delay Time from the rising edge of ACK to the floating of port Port A in mode 2 Delay Time from the rising edge of WR to the falling edge of OBF Delay Time from the falling edge of ACK to the rising edge of OBF Delay Time from the falling edge of STB to the rising edge of IBF Delay Time from the rising edge of RD to the falling edge of IBF Delay Time from the falling edge of RD to the falling edge of INTR Delay Time from the rising edge of STB to the rising edge of INTR Delay Time from the rising edge of ACK to the rising edge of INTR Delay Time from the falling edge of WR to the falling edge of INTR Note Timing is measured at 0 8 V and Vy 2 2 V for both input and outputs 281 National Instruments Corporation D 5 Lab PC 1200 Al RLPM Appendix D OKI MSM82C55A Data Sheet O MSM82C55A 2RS GS VJS Basic Input Operation Mode 0 RD Port input CS A4 Basic Output Operation
161. take note of the following precaution Although the count values may be set in the three counters in any sequence after the control word has been set in each counter count values must be set consecutively in the LSB MSB order in any one counter 258 National Instruments Corporation O MSM82C53 2RS GS JS Example of contro word and count value setting Counter 0 Read Load LSB only Mode 3 Binary count count value 3H Counter 1 Read Load MSB only Mode 5 Binary count count value AAOOH Counter 2 Read Load LSB and MSB Mode 0 BCD count count value 1234 MVI A 1EH OUT n3 MVI A 6AH OUT n3 MVI A B1H OUT n3 MVI A 03H OUT Counter 0 control word setting Counter 1 control word setting Counter 2 control word setting Counter count value setting MVI A AAH OUT ni MVI A s Counter 1 count value setting OUT n2 MVI A 12H OUT n2 Counter 2 count value setting LSB then MSB Note nO 1 n2 n3 Counter 0 address Counter 1 address Counter 2 address Control word register address The minimum and maximum count values which can be counted in each mode are listed below O executes 10000H count ditto in other modes 1 cannot be counted 1 executes 10001H count Mode Definition 260 Mode 0 terminal count The counter output is set to L level by the mode setting If the count value is then written in the counter with th
162. te maximum rating conditions for extended periods may 25 GND 0V Ta 25 GND 0V Should not exceed Vcc affect device reliability RECOMMENDED OPERATING CONDITIONS S Supply Voltage for Digital Block Supply Voltage for Analog Block Monotonicity No load Operating Ambient Temperature 7 127 Lab PC 1200 Al RLPM 12 National Instruments Corporation Appendix Fujitsu MB88341 MB88342 Data Sheet MB88341 MB88342 DC CHARACTERISTICS Recommended operating conditions unless otherwise noted Digital Block MCU Interface 222 E fw All inputs including CLK fixed at Vcc Standby Supply Current pA or GND All outputs open Input Low SE geen EE np Deeg Analog Block D A Converter 2 22 Supply Current mul dew l5 ee mumm deje em No load 7 128 National Instruments Corporation A 13 Lab PC 1200 Al RLPM Appendix Fujitsu MB88341 MB88342 Data Sheet MB88341 MB88342 AC CHARACTERISTICS Recommended operating conditions unless otherwise noted Clock Low Time 8 a Clock High Time Clock Rise Time Clock Fall Time Data Setup Time Data Hold Time Load Strobe High Time Load Strobe Setup Time Load Strobe Hold Time DAC Output Settling Time Da
163. ted to the two lower order bits of the address bus CLKO 2 Clock input Supply of three clock signals to the three counters incorpo rated in MSM82C53 GATEO 2 Gate input Control of starting interruption and restarting of counting in the three respective counters in accordance to the set con tro word contents Counter output Output of counter output waveform in accordance with the set mode and count value SYSTEM INTERFACING ADDRESS BUS 16 bits CONTROL BUS DATA BUS 1 AO cs 82C53 2 COUNTER 0 COUNTER 1 COUNTER 42 OUT GATE CLK OUTGATECLK OUT GATE CLK 258 National Instruments Corporation C 7 Lab PC 1200 Al RLPM Appendix C MSM82C53 Data Sheet O MSM82C53 2RS GS JS DESCRIPTION OF BASIC OPERATIONS Data transfers between the internal registers and the external data bus is outlined in the following table Data bus to counter 0 Writing Data bus to counter 1 Writing Data bus to counter 2 Writing Data bus to control word register Writing Data bus from counter 0 Reading Data bus from counter 1 Reading Data bus from counter 2 Reading x denotes not specified DESCRIPTION OF OPERATION 82C53 functions are selected by a control word from the CPU In the required program sequence the control word setting is followed by the count value setting and execution of the desired timer oper
164. the Lab PC 1200 AI Copyright Xicor Inc Reprinted with permission of copyright owner rights reserved Xicor Inc 1995 Nonvolatile Solutions Data Book National Instruments Corporation B 1 Lab PC 1200 Al RLPM Appendix Xicor 25020 Data Sheet APPLICATION NOTES AVAILABLE ANO e AN18 AN31 AN37 e 40 2K X25020 256 x 8 Bit SPI Serial E2PROM With BLOCK LOCK PROTECTION FEATURES 1MHz Clock Rate SPI Modes 0 0 amp 1 1 e 256 X 8 Bits 4 Byte Page Mode Low Power CMOS 150L4A Standby Current 3mA Active Write Current 2 7V To 5 5V Power Supply Block Lock Protection Protect 1 4 1 2 or all of 2 Array Built in Inadvertent Write Protection Power Up Power Down protection circuitry Write Latch Write Protect Pin Self Timed Write Cycle 5ms Write Cycle Time Typical High Reliability Endurance 100 000 cycles per byte Data Retention 100 Years ESD protection 2000V on all pins 8 Pin Mini DIP Package 8 Lead SOIC Package 8 Lead TSSOP DESCRIPTION The X25020 is a CMOS 2048 bit serial E2PROM inter nally organized as 256 x 8 The X25020 features a serial interface and software protocol allowing operation on a simple three wire bus The bus signals are a clock input SCK plus separate data in SI and data out SO lines Access to the device is controlled through a chip select CS input allowing any number of devi
165. the data stored in the memory at the selected address is shifted out on the SO line The data stored in memory atthe next address can be read sequentially by continuing to provide clock pulses The address is automatically incremented to the next higher address after each byte of data is shifted out When the highest address is reached FF the address counter rolls over to address 00 allowing the read cycle to be continued indefinitely The read operation is termi nated by taking CS HIGH Refer to the read array operation sequence illustrated in Figure 1 To read the status register CS line is first pulled LOW to select the device followed by the 8 bit RDSR instruc tion After the read status register opcode is sent the contents of the status register are shifted out on the SO line Figure 2 illustrates the read status register se quence Write Sequence Prior to any attempt to write data into the X25020 the write enable latch must first be set by issuing the WREN instruction See Figure 3 CS is firsttaken LOW then the WREN instruction is clocked into the X25020 After all eight bits of the instruction are transmitted CS mustthen be taken HIGH If the user continues the write operation without taking CS HIGH after issuing the WREN instruction the write operation will be ignored 2 114 To write data to the memory array the user issues the WRITE instruction followed by the address and then the data
166. the rising edge of the serial clock Serial Clock SCK The Serial Clock controls the serial bus timing for data input and output Opcodes addresses or data present on the SI pin are latched on the rising edge of the clock input while data on the SO pin change after the falling edge of the clock input Chip Select CS When CS is HIGH the X25020 is deselected and the SO output pin is at high impedance and unless an internal write operation is underway the X25020 will be in the standby power mode CS LOW enables the X25020 placing it in the active power mode It should be noted that after power up a HIGH to LOW transition on CS is required prior to the start of any operation Write Protect WP When WP is LOW nonvolatile writes to the X25020 are disabled but the part otherwise functions normally When WP is held HIGH all functions including nonvola Hold HOLD HOLD is used in conjunction with the CS pin to select the device Once the partis selected and a serial sequence is underway HOLD may be used to pause the serial communication with the controller without resetting the serial sequence To pause HOLD mustbe brought LOW while SCK is LOW To resume communication HOLD is brought HIGH again while SCK is LOW If the pause feature is not used HOLD should be held HIGH at all times PIN CONFIGURATION DIP SOIC tile writes operate normally WP going LOW while CS is still LOW w
167. tical list and description of terms used in this manual including abbreviations acronyms metric prefixes mnemonics and symbols e The Index contains an alphabetical list of key terms and topics covered in this manual including the page where you can find each one Conventions Used in This Manual lt gt ar 1200 Series bold bold italic italic Lab PC 1200 Al RLPM The following conventions are used in this manual Angle brackets containing numbers separated by an ellipsis represent a range of values associated with a bit or signal name for example DBIO lt 3 0 gt This icon to the left of bold italicized text denotes a note which alerts you to important information 1200 Series refers to both the Lab PC 1200 and the Lab PC 1200AI Bold text denotes the names of menus menu items dialog boxes dialog box buttons or options Bold italic text denotes a note caution or warning Italic text denotes emphasis a cross reference or an introduction to a key concept X National Instruments Corporation About This Manual monospace Text in this font denotes text or characters that you should literally enter from the keyboard sections of code programming examples and syntax examples This font is also used for the proper names of disk drives paths directories programs subprograms subroutines device names functions operations variables filenames and extensions and for statements and comme
168. to be written This is minimally a thirty two clock operation CS must go LOW and remain LOW forthe duration of the operation The host may continue to write up to 4 bytes of data to the X25020 The only restriction is that the 4 bytes must reside on the same page If the address counter reaches the end of the page and the clock continues the counter will roll over to the first address of the page and overwrite any data that may have been written For the write operation byte or page write to be completed CS can only be brought HIGH after bit 0 of data byte Nis clocked in Ifitis brought HIGH at any other time the write operation will not be completed Refer to Figures 4 and 5 below for a detailed illustration of the write sequences and time frames in which CS going HIGH are valid To write to the status register the WRSR instruction is followed by the data to be written Data bits 0 1 4 5 6 and 7 must be O Figure 6 illustrates this sequence While the write is in progress following a status register or write sequence the status register may be read to check the WIP bit During this time the WIP bit will be HIGH Hold Operation The HOLD input should be HIGH at Vi under normal operation If a data transfer is to be interrupted HOLD can be pulled LOW to suspend the transfer until it can be resumed The only restriction is the SCK input must be LOW when HOLD is first pulled LOW and SCK must also be LOW w
169. unts as the set count value If the set count value n is an odd number the repeated square wave output consists of only 1 2 clock inputs at level and n 1 2 clock inputs at L level If a new count value is written during counting the new count value is reflected immediately after the Lab PC 1200 Al RLPM OKI MSM82C53 Data Sheet Appendix C OKI MSM82C53 Data Sheet O MSM82C53 2RS GS JS change H to L or L to H in the next stopped when the gate input is switched to L counter output to be executed The counting opera level and restarted from the set count value when tion at the gate input is done the same as in mode 2 switched back to H level Mode 4 software trigger strobe Mode 5 hardware trigger strobe The counter output is switched to H level by the The counter output is switched to H level by the mode setting Counting is started in the same way mode setting Counting is started and the gate input as described for mode 0 A single L pulse equiva used in the same way as in mode 1 lent to one clock width is generated at the counter The counter output is identical to the mode 4 out output when the terminal count is reached put This mode differs from 2 in that the 41 level out The various roles of the gate input signals in the put appears one clock earlier in mode 2 and that above modes are summarized in the following table pulses are not repeated i
170. utions and suggestions support natinst com Telephone and Fax Support National Instruments has branch offices all over the world Use the list below to find the technical support number for your country If there is no National Instruments office in your country contact the source from which you purchased your software to obtain support Country Australia Austria Belgium Brazil Canada Ontario Canada Quebec Denmark Finland France Germany Hong Kong Israel Italy Japan Korea Mexico Netherlands Norway Singapore Spain Sweden Switzerland Taiwan United Kingdom United States Lab PC 1200 Al RLPM Telephone 03 9879 5166 0662 45 79 90 0 02 757 00 20 011 288 3336 905 785 0085 514 694 8521 45 76 26 00 09 725 725 11 01 48 14 24 24 089 741 31 30 2645 3186 03 6120092 02 413091 03 5472 29770 02 596 7456 5 520 2635 0348 433466 32 84 84 00 2265886 9 640 0085 08 730 49 70 056 200 51 51 02 377 1200 01635 523545 512 795 8248 E 2 Fax 03 9879 6277 0662 45 79 90 19 02 757 03 11 011 288 8528 905 785 0086 514 694 4399 45 76 26 02 09 725 725 55 01 48 14 24 14 089 714 60 35 2686 8505 03 6120095 02 41309215 03 5472 2977 02 596 7455 5 520 3282 0348 430673 32 84 86 00 2265887 91 640 0533 08 73043 70 056 200 51 55 02 737 4644 01635 523154 512 794 5678 National Instruments Corporation Technical Support Form Photocopy this form and update it each time you make changes to
171. utput Delay Time after address Note Timing measured at V 0 8V and Vy 2 2V for both inputs and outputs TIME CHART Write Timing 256 National Instruments Corporation 6 5 Lab PC 1200 Al RLPM Appendix C OKI MSM82C53 Data Sheet E 1 0 MSM82C53 2RS GS JS Read Timing VALID HIGH IMPEDANCE HIGH IMPEDANCE Clock amp Gate Timing 257 Lab PC 1200 Al RLPM C 6 National Instruments Corporation Appendix C OKI MSM82C53 Data Sheet 1 0 M9SM82C53 2RS GS JS 13 DESCRIPTION OF PIN FUNCTIONS Pin Symbol Input output Function Bidirectional Input output Three state 8 bit bidirectional data bus used when writing data bus control words and count values and reading count values upon reception of WR and RD signals from CPU Chip select Data transfer with the CPU is enabled when this pin is at low input level When at high level the data bus thru D7 is switched to high impedance state where neither writing nor reading can be executed Internal registers however remain unchanged Read input Data can be transferred from 5 82 53 to CPU when this pin is at low level td Write input Data can be transferred from CPU to MSM82C53 when this pin is at low level Address input One of the three internal counters or the control word regis ter is selected by 1 combination These two pins are normally connec
172. word deep A D FIFO buffer Two consecutive 8 bit readings of the A D FIFO Register return an A D conversion value stored in the A D FIFO The first reading returns the low byte of the 16 bit value and the second reading returns the high byte The value read is removed from the A D FIFO thereby freeing space for another A D conversion value to be stored The A D FIFO is empty when all values it contains are read The DAVAIL bit in Status Register 1 should be read before the A D FIFO Register is read If the A D FIFO contains one or more A D conversion values the DAVAIL bit is set and the A D FIFO Register can be read to retrieve a value If the DAVAIL bit is cleared the A D FIFO is empty Therefore reading the A D FIFO Register returns meaningless information The values returned by reading the A D FIFO Register are available in two different binary formats straight binary or two s complement binary The binary format used is selected by the TWOSCMP bit in Command Register 1 The bit pattern returned for either format is as follows Address hex Type Read only Word Size 8 bit Bit Map Straight binary mode High Byte 7 6 5 4 3 2 1 0 0 0 0 0 D11 D10 D9 D8 Low Byte 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 DO Bit Name Description High Byte 7 4 0 These bits always return O in straight binary mode 3 0 D lt 11 8 gt Data These bits contain the high byte of the straight binar
173. y result of a 12 bit A D conversion Values made up of D 11 0 range from 0 to 4 095 decimal 0000 to National Instruments Corporation 2 21 Lab PC 1200 Al RLPM Chapter 2 Register and Descriptions OFFF hex Straight binary mode is useful for unipolar analog input readings because all values read reflect a positive polarity input signal Low Byte 7 0 D lt 7 0 gt Data These bits contain the low byte of the straight binary result of a 12 bit A D conversion The first of the two consecutive readings of the A D FIFO Register returns this byte Bit Map Two s complement binary mode High Byte 7 6 5 4 3 2 1 0 D15 D14 D13 D12 D11 D10 D9 D8 Low Byte 7 6 5 4 3 2 1 0 D7 D6 DS D4 D3 D2 DI DO Bit Name Description High Byte 7 0 D lt 15 8 gt Data These data bits contain the high byte of the 16 bit sign extended two s complement result of a 12 bit A D conversion Values made up of D lt 15 0 gt therefore range from 2 048 to 2 047 decimal F800 to 07FF hex Two s complement mode is useful for bipolar analog input readings because the values read reflect the polarity of the input signal Low Byte 7 0 D lt 7 0 gt Data These data bits contain the low byte of the 16 bit Lab PC 1200 Al RLPM sign extended two s complement result of a 12 bit A D conversion The first of the two consecutive readings of A D FIFO Register returns this byte 2 2
174. your software or hardware and use the completed copy of this form as a reference for your current configuration Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently If you are using any National Instruments hardware or software products related to this problem include the configuration forms from their user manuals Include additional pages if necessary Name Company Address Fax Phone Computer brand Model Processor Operating system include version number Clock speed MHz RAM MB Display adapter Mouse ve no Other adapters installed Hard disk capacity MB Brand Instruments used National Instruments hardware product model Revision Configuration National Instruments software product Version Configuration The problem is List any error messages The following steps reproduce the problem Lab PC 1200 Al Hardware and Software Configuration Form Record the settings and revisions of your hardware and software on the line to the right of each item Complete a new copy of this form each time you revise your software or hardware configuration and use this form as a reference for your current configuration Completing this form accurately before contacting National Instruments for technical support helps our appli

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