smt365 user manual - Sundance Multiprocessor Technology Ltd.
Contents
1. define SMT365CP0 volatile unsigned int 0x90000000 define SMT365CP1 volatile unsigned int 0x90008000 define SMT365CP2 volatile unsigned int 0x90010000 define SMT365CP3 volatile unsigned int 0x90018000 define SMT365CP4 volatile unsigned int 0x90020000 define SMT365CP5 volatile unsigned int 0x90028000 define SMT365CPO_STA volatile unsigned int 0x90004000 define SMT365CP1 STA volatile unsigned int 0x9000C000 define SMT365CP2_STA volatile unsigned int 0x90014000 define SMT365CP3_STA volatile unsigned int 0x9001C000 define SMT365CP4 STA volatile unsigned int 0x90024000 define SMT365CP5_STA volatile unsigned int 0x9002C000 define SMT365GB_STAT volatile unsigned int 0x90034000 define SMT365SDB_STA volatile unsigned int 0x90038000 define SMT365STAT volatile unsigned int 0x9003C000 define SMT365SDBA volatile unsigned int 0x90040000 define SMT365SDBB volatile unsigned int 0x90050000 define SMT365SDBC volatile unsigned int 0x90060000 define SMT365SDBD volatile unsigned int 0x90070000 define SMT365SDBA STA volatile unsigned int 0x90048000 define SMT365SDBB_STA volatile unsigned int 0x90058000 define SMT365SDBC_STA volatile unsigned int 0x90068000 define SMT365SDBD_STA volatile unsigned int 0x90078000 define SMT365SDBA_INPUTFLAG volatile unsigned int 0x90044000 define SMT365SDBB_INPUTFLAG volatile unsigned int 0x90054000 define SMT365SDBC_INPUTFLAG volatile unsigned int 0x2. Version 2 3 Page 25 of 28 SMT365 User Manual SHB pinout SHB generic pin out QSH Pin number QSH Pin number M 1 USERDEFO USERDEF1 USERDEF2 USERDEF3 Note W is a short for Full Word i e 32 bit Word Hw is a short for Half word i e 16 bit Word Version 2 3 32 bits SDB interface Page 26 of 28 SMT365 User Manual Pin Signal Signal Pin 1 SDBA_CLK SDBA_DATAO 2 3 SDBA_DATA1 SDBA_DATA2 4 5 SDBA_DATA3 SDBA_DATA4 6 7 SDBA_DATA5 SDBA_DATA6 8 9 SDBA_DATA7 SDBA_DATA8 10 11 SDBA DATA9 SDBA_DATA10 12 SDBA_DATA11 SDBA_DATA12 SDBA_DATA13 SDBA_DATA14 17 SDBA_DATA15 SDBA_UO 18 19 SDBA_U1 20 21 SDBA_WEN 22 23 SDBA_REQ SDBA_ACK 24 25 26 27 E z 28 29 E 30 31 z E 32 33 34 35 36 37 SDBA_CLK SDBA_DATA16 38 SDBA_DATA17 SDBA_DATA18 SDBA_DATA19 SDBA_DATA20 SDBA_DATA21 SDBA_DATA22 SDBA_DATA23 SDBA_DATA24 SDBA_DATA25 SDBA_DATA26 SDBA_DATA27 SDBA_DATA28 SDBA_DATA29 SDBA_DATA30 53 SDBA_DATAS1 SDBA_UO 54 55 SDBA_U1 56 57 E SDBA_WEN 58 59 SDBA_REQ SDBA_ACK 60 J Not implemented Version 2 3 Page 27 of 28 SMT365 User Manual Bibliography 1 2 Sundance Help file SMT6400 help file DSP support package
3. 22 out of 40 39 22 out of 56 Number of SLICEs 64 3309 out of 5120 32 3547 out of 10752 Number of BUFGMUXs 6 1 out of 16 6 1 out of 16 Number of TBUFs 22 576 out of 2560 10 576 out of 5376 Version 2 3 Page 19 of 28 SMT365 User Manual Code Composer This module is fully compatible with the Code Composer Studio debug and development environment This extends to both the software and JTAG debugging hardware The driver to use is the tixds64xx 11 dvr CCS version 3 0 or later is required as the reprogramming utility SMT6001 requires it a Troubleshooting Our Knowledge data base and FAQ sections may help you to resolve some known issues Application Development Depending on the complexity of your application you can develop code for SMT365 modules in several ways SMT6400 For simple applications the Sundance SMT6400 software support package project examples and its associated header files SmtTim h and ModSup h can suffice The SMT6400 product is installed by the Sundance Wizard and it is free of charge 3L Diamond This module is fully supported by 3L Diamond which Sundance recommends for all but the simplest of applications An SMT365 has to be declared as appropriate in configuration files as one processors of type e SMT365 4 1 4MB ZBTRAM XC2V1000 or SMT365_4 2 4MB ZBTRAM XC2V2000 e SMT365 8 1 8MB ZBTRAM XC2V1000 or SMT365_8 2 8MB ZBTRAM XC2V2000 e SMT365_16_1 16M
4. SMT365 User Manual Certificate Number FM 55022 User Manual QCF42 Version 3 0 5 2 01 Sundance Multiprocessor Technology Ltd 2001 Version 2 3 Page 2 of 28 SMT365 User Manual Revision History Date Comments Engineer Version 27 01 03 Updated interrupt registers global status register JPA 1 0 4 30 01 03 Corrected CPLD header pin out GP 1 0 5 14 03 03 Added location of SDBs on the board JPA 1 0 6 11 04 03 Corrected I O connector block pin out GP 1 0 7 08 05 03 Added link to General firmware specification SHB and JPA 1 0 8 SDB specification added fpga pinout convention 19 08 03 Page 30 NSDRAMCS mapped on emif_ctrl lt 5 gt JPA 1 0 9 Updated Reprogramming chapter 20 10 03 Added information about SHB Word SHB32x firmware JPA 1 1 0 version 01 12 03 SHB Word SHB32x firmware version available for both JPA 1 1 1 SMT365 1 and 2 modules SDL interface availability FPGA space availability 11 03 04 Updated Flash section JPA 1 1 2 Added board s weight 04 05 04 Corrected figure 1 Flash logical sections JPA 1 1 3 Updated EMIFB CE3 space control register value Updated EMIFA CE1 address range Updated FPGA space availability section 25 10 04 Create the FPGA configuration section SM 1 1 4 04 08 05 Update the user manual supports the new firmware SM 2 0 implementation 13 12 05 Details added on EMIF registers settings JV 2 1 15 02 06 Changed GEL file contents GP 2 2
5. and SMT6500 help file FPGA support package TMS320C6000 Peripherals Reference Guide literature number SPRU190 It describes common peripherals available on the TMS320C6000 digital signal processors This book includes information on the internal data and program memories the external memory interface EMIF the host port multichannel buffered serial ports direct memory access DMA clocking and phase locked loop PLL and the power down modes TIM 40 MODULE SPECIFICATION Including TMS320C44 Addendum SDB Technical Specification SHB Technical Specification TMS320C4x User s Guide literature number SPRU063 It describes the C4x 32 bit fixed point processor developed for digital signal processing as well as parallel processing applications Covered are its architecture internal register structure instruction set pipeline specifications and operation of its six DMA channels and six communication ports Software and hardware applications are included Xilinx Virtex Il datasheet TMSC6416 datasheet Version 2 3 A Application Development 19 Architecture Description 8 B Bibliography 27 Block Diagram 7 Boot Mode 8 C Code Composer 19 Comports 14 CONFIG amp NMI 16 E EMIF Control Registers 9 F Firmware versions 13 Flash 12 FPGA space availability 18 G Global Bus 14 I IOF lines 18 J JTAG chains 22 L LED register 15 LEDs 14 Page 28 of 28 SMT365
6. D8 D7 RW 0 RW 0 RW 0 RW 0 Version 2 3 Page 16 of 28 SMT365 User Manual CONFIG amp NMI The TIM specification describes the operation of an open collector type signal CONFIG that is driven low after reset This signal on a standard C4x based TIM is connected to the processor s IIOF3 pin On the SMT365 the CONFIG signal is asserted after power on and can be released by writing the value 1 lt lt 6 to the config register Conversely CONFIG may be re asserted by writing 0 to this bit It is not possible for software to read the state of the CONFIG signal The NMI signal from the TIM connector can be routed to the DSP NMI pin WARNING Several software components include code sequences that assume setting GIE 0 in the DSP CSR will inhibit all interrupts NMI violates that assumption If an NMI occurs during such code sequences it may not be safe to return from the interrupt This may be particularly significant if you are using the compiler s software pipelining facility Config Register 31 8 7 o iji NMI CONFIG Field Description i NFIG CONFIG dive CONFIG low 1 tri state CONFIG NMI O Disconnect NMI from the DSP 1 Connect NMI from TIM to the DSP Config and NMI DSP lines are described in the SMT6400 help file Version 2 3 Page 17 of 28 SMT365 User Manual Timer The TIM TCLKO and TCLK1 signals can be routed to the DSP s TOUT TINP pins The signal direction mu
7. DSP has two external memory interfaces EMIF that are 64 bits wide and 16 bits wide The DSP contains several registers that control the external memory interface EMIF A full description of these registers can be found in the DSP C6000 Peripherals Reference Guide The standard bootstrap will initialise these registers to use the following resources Memory space Resource Address range EMIFA Internal program memory 1MB 0x00000000 OxOOOFFFFF CEO ZBTRAM 2x 8MB sections 0x80000000 0x807FFFFF CE1 Virtex 0x90000000 Ox900FFFFF Memory space Resource Address range EMIFB CE1 15 3 section of flash 0x64000000 0x641FFFFF 2MB each CE2 2 9 4 section of flash 0x68000000 0x681FFFFF 2MB each Version 2 3 Page 10 of 28 SMT365 User Manual The EMIF settings are set by the boot code so no GEL file is necessary See TI documentation for help on creating GEL file A GEL file example Menuitem SMT365_Init hotmenu SMT365_Reset GEL_Reset SMT365_emif_init hotmenu SMT365_emif_init int 0x01800000 0x0001277C EMIFA_GCTL int 0x01800008 0x000000E0 EMIFA CEO int 0x01800004 0x00000030 EMIFA_CE1 int 0x01800018 0x55227000 EMIF_SDRAMCTL int 0x01800048 0x0000001A EMIF CEO SEC Version 2 3 Page 11 of 28 SMT365 User Manual ZBTRAM Memory space CEO is used to access 8MB of ZBTRAM over the EMIFA It is mapped as
8. User Manual Index N Notational Conventions 5 O Operating Conditions 20 P Power consumption 20 R Register Descriptions 5 S Serial Ports 22 SHB 14 SHB pinout 25 SMT6400 19 SMT6500 19 T Table of contents 3 Timer 17 V Version Control 13 Virtex memory map 23 W Weight 20 Z ZBTRAM 11
9. Version 2 3 Page 3 of 28 SMT365 User Manual Table of Contents Revision HISTOrY scierie is 2 Table of Contents ra sde asset aoma de at dan arm ester etes avec RA KIHIKO SEZ II 3 Contacting SUNGANCE inici 4 Notational Conventions ciinicicniacic nicnnii ici ii 5 In 5 kaa Bs WANA eee sta atcha WAA AAA Saha WA hate ae eet 5 SOB SR 0 5 Register Descriptions rs ste nel aan DT aa Bt oa 5 OUTING Description snixiorormmrra as e 6 Intended A dinte saine alli 6 Block Dig PAM Enr nan a AA nines 7 Architecture DescriptiON wcoicicociimna a wakana nu nunua aaa au nanunua mawaa uuuaa 8 e oe AUA ENEA 8 Boot MOSS oot aerah eat ee oes eure e anne care he kecey ahaa ete nikinunua kana 8 EMIF Control Register cusco taco tilda 9 Ann A AUA AAA 11 FLASH EE ia 12 O A O NO 13 V TSION COMMON a A tdi 13 Firmware VerSiONS score d 13 Reprogramming the firmware and boot code eccceeeeeeeeseeeeeeeeeeeeeeeeeeeeeeees 13 COMPON Suns ri 14 Fa Ey PP NET PRO PROS IL 14 Pde git ELU LEE re err a ee ee ads 14 Global DUS ee 14 LED Setting cons tbc 14 LED REGISTE sanar 15 CONFIG amp NMI lt oxcooionrriarraa cuneunteanseanierneundeeiendnenmnunsiwwinensen 16 Cong A N AA E nai 16 Version 2 3 Page 4 of 28 SMT365 User Manual IO SAI AC aa UA AA AAA AAA AAA 18 FPGA space avalia yi asa Kawawa 18 Code COMPOS siria 19 Application Developments 19 SM T640 a WAWE WA WW AU WAWA AAA 19 3L DAMON erent ere mn eee oo 19 SM16500 ne Re ile Ra ane D a 19 Op
10. all memory will be directly accessible to the DSP Version 2 3 Page 12 of 28 SMT365 User Manual FLASH An 8MB Flash ROM is connected to the DSP in the EMIFB CE1 amp CE2 memory spaces The ROM holds boot code for the DSP configuration data for the FPGA and optional user defined code The flash is 16 bit wide The boot code is stored in 8 bit mode as this is the way the DSP boots The FPGA data and user application are stored in 16 bit The EMIFB CE1 and CE2 space control registers should be programmed with the value OxFFFFFFO3 to access the flash in 8 bit mode and OxFFFFFF13 in 16 bit mode As the DSP only provides 20 address lines on its EMIFB both CE1 amp CE2 are used to access this device This in itself allows the direct access of 4MB A paging mechanism is used to select which half of the 8MB device is visible in this 4MB window As the EMIFB CE1 amp CE2 memory spaces alias throughout the available range the flash device can be accessed using the address range 0x67E00000 0x681FFFFF This gives a 4MB continuous memory space The flash can be divided into the four logical sections shown in the following figure paging bit is bit 21 0x67C00000 Page0 A a 2 MBytes Section 1 CE1 0x67E00000 Page1 Vi 2 MBytes Section 2 0x68000000 Page0 2 a 2 MBytes Section 3 a 0x68200000 Page 2 MBytes Section 4 0x68400000 Figure 1 Flash logical sections To change the state of the page bit y
11. 4 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 NC URDO URD1 URD2 URD3 URD4 URD5 URD6 URD7 URCLK URENB URCLAV URSOC UXDO UXD1 UXD2 UXD3 UXD4 UXD5 UXD6 UXD7 UXCLK UXENB UXCLAV UXSOC UXAO DR1 FSR1 FSX1 DX1 CLKS2 CLKX2 CLKR2 FSX2 DX2 FSR2 DR2 UXA1 UXA2 UXA3 UXA4 GPIO8 URAO URA1 CLKR1 CLKX1 CLKS1 CLKSO CLKXO CLKRO FSX0 DXO FSRO DRO URA2 URA4 URA3 FPGA and CPLD JTAG The following shows the pin outs for JP2 CPLD and JP3 FPGA JTAG connectors Signal Pin Pin Signal V33 1 TMS TCK TDO GND TDI FPGA configuration The CPLD and the FPGA have two different JTAG chains You can configure the FPGA by the JTAG connector using for instance the Xilinx parallel cable IV The lines MO M1 and M2 are not connected to the CPLD These lines are hardwired connected to the FPGA at high logic level 1 So the FPGA is configured in Slave Serial mode Version 2 3 Page 23 of 28 SMT365 User Manual Virtex Memory Map See general firmware description The memory mapping is as follows
12. 90064000 define SMT365SDBD_INPUTFLAG volatile unsigned int 0x90074000 define SMT365SDBA_OUTPUTFLAG volatile unsigned int 0x9004C000 define SMT365SDBB_OUTPUTF LAG volatile unsigned int 0x9005C000 define SMT365SDBC_OUTPUTF LAG volatile unsigned int 0x9006C000 define SMT365SDBD_OUTPUTFLAG volatile unsigned int 0x9007C000 define GLOBAL_BUS volatile unsigned int 0x900A0000 define GLOBAL BUS CTRL volatile unsigned int 0x90080000 Version 2 3 Page 24 of 28 SMT365 User Manual define GLOBAL BUS START volatile unsigned int 0x90088000 define GLOBAL BUS LENGTH volatile unsigned int 0x90090000 define SMT365TCLK volatile unsigned int 0x900C0000 define SMT365TIMCONFIG volatile unsigned int 0x900C8000 define SMT365LED volatile unsigned int 0x900D0000 define SMT365INTCTRL4 volatile unsigned int 0x900E0000 define SMT365INTCTRL4_EX volatile unsigned int 0x900E4000 define SMT365INTCTRL5 volatile unsigned int 0x900E8000 define SMT365INTCTRL5_EX volatile unsigned int 0x900EC000 define SMT365INTCTRL6 volatile unsigned int 0x900F0000 define SMT365INTCTRL6_EX volatile unsigned int 0x900F4000 define SMT365INTCTRL7 volatile unsigned int 0x900F8000 define SMT365INTCTRL7_EX volatile unsigned int 0x900FC000
13. B ZBTRAM XC2V1000 or SMT365_16 2 16MB ZBTRAM XC2V2000 SMT6500 This is the support package for the FPGA It may be used to develop your application in the FPGA of the module Version 2 3 Page 20 of 28 SMT365 User Manual Operating Conditions Safety The module presents no hazard to the user EMC The module is designed to operate within an enclosed host system that provides adequate EMC shielding Operation within the EU EMC guidelines is only guaranteed when the module is installed within an appropriate host system The module is protected from damage by fast voltage transients introduced along output cables from outside the host system Short circuiting any output to ground does not cause the host PC system to lock up or reboot General Requirements The module must be fixed to a TIM40 compliant carrier board The SMT365 TIM is in a range of modules that must be supplied with a 3 3V power source In addition to the 5V supply specified in the TIM specification these new generation modules require an additional 3 3V supply to be presented on the two diagonally opposite TIM mounting holes The lack of this 3 3V power supply should not damage the module although it will obviously be inoperable prolonged operation under these circumstances is not recommended The SMT365 is compatible with all Sundance TIM carrier boards It is a 5V tolerant module and as such it may be used in mixed systems with older TIM modules carrier boa
14. a 64 bit memory The speed of the ZBTRAM is dependent on the processor variant Using the C6416 the ZBTRAM will operate at 133MHz maximum It operates at one quarter or one sixth of the core clock speed The EMIFA CEO memory space control register should be programmed with the value Ox000000 EO0 Note that depending upon the application the best performance may be obtained whilst running the DSP at a lower clock speed l e at 600MHZ the external EMIF will only run at 100MHz core clock 6 as we are constrained by the TI imposed limit of 133MHz But if the core were running at 533MHz then the EMIF would be at the maximum limit possible of 133MHz a quarter of 533 This speed adjustment is not a user option but must be adjusted during manufacture Note also that the DSP only has 20 address pins on the EMIFA and cannot therefore directly address more than 8MB of SRAM the ZBTRAM is a type of SRAM with non multiplexed address pins It requires the use of a paging mechanism to access more On the SMT365 there is a single page bit which is connected directly to the most significant bit of the ZBTRAM bit 20 This bit is controlled by a register accessed on EMIFB CE3 address space 0x6C04000X A write to the addresses shown below data don t care will have the following effect Address ZBTRAM Address bit 20 state 0x6C040000 0 0x6C040001 1 Note that for smaller ZBTRAM chipsets there is no need to set this bit as
15. al registers of the EMIF Then it configures the FPGA from the data held in the flash ROM Note that two control register bits are needed for this purpose one to put the FPGA into a waiting for configuration state and another to actually transfer the configuration data The PROG pin causes the FPGA to enter the non configured state is accessed at address 0x6C02000X Writing to address Ox6C020000 will assert this pin and address 0x6C0200001 will de assert this pin The configuration data clock is accessed at address 0x6C080001 Each bit of the FPGA s configuration bit stream must be serially clocked through this address The bootloader is executed It will continually check the six comports until data appears on one of them This will next load a program in boot format from this comport Note that the bootloader will not read data arriving on other comports Finally the control is passed to the loaded DSP application The DSP will take approximately about 1000ms to configure the FPGA following reset assuming a 600MHz clock The external devices implemented in the FPGA such as comports must not be used during this configuration Version 2 3 Page 9 of 28 SMT365 User Manual It is safest to wait for the configuration to complete Note that comports will appear to be not ready until the FPGA has been configured The FPGA programming algorithm is not described here It can be found in the boot code EMIF Control Registers The
16. ctor Comport 0 amp 3 Timer amp Control 15 I O pins FPGA Controller Virtex Il XC2V1000 2000 FF896 432 624 I O pins 1 5V core 3 3V 1 0 Global Bus 74 I O pins J2 Bottom Primary TIM connector Comport 1 2 48 5 J3 Global Bus connector Version 2 3 Page 8 of 28 SMT365 User Manual Architecture Description DSP The Texas Instruments DSP can run at up to 600MHz The DSP is doted of 8MBytes of Zero Bus Turnaround RAM ZBTRAM The DSP is a TMS320C6416 type This is a fixed point digital signal processor provided by Texas Instruments The processor will run with zero wait states from internal SRAM The internal memory is 1MB in size and can be partitioned between normal SRAM and L2 cache An on board crystal oscillator provides the clock used for the DSP which them multiplies this by twelve internally Boot Mode The DSP is connected to the on board flash ROM that contains the Sundance bootloader and the FPGA bitstream Following reset the DSP will automatically load the data from the flash ROM into its internal program memory at address 0 and then start executing from there All this code is the Sundance bootloader and it is made up of two parts FPGA configuration and processor configuration FPGA configuration uses data in the ROM to configure the FPGA A processor configuration sets the processor into a standard state by writing into the DSP intern
17. des a single global bus interface This is only accessible from the DSP The addresses of the global bus registers are shown in the Virtex Memory Map and are described in the SMT6400 help file LED Setting The SMT365 has 9 LEDs One shows the FPGA configuration status and the other 8 are under DSP control Version 2 3 Page 15 of 28 SMT365 User Manual Four output TTL I O pins are available on connector JP1 for control or debugging Their values can be controlled by bits in the LED register The GPIO pins 12 to 15 are connected to the leds D2 to D5 respectively Four of the LEDs D7 to D10 are controlled by bits in the LED register Writing 1 illuminates the LEDs writing 0 turn it off The TTL I O are available on the connector JP2 for control or debugging They can be controlled by bits in the same register LED D6 always displays the state of the FPGA DONE pin This LED is off when the FPGA is configured DONE 1 and on when it is not configured DONE 0 This LED should go on when the board is first powered up and go off when the FPGA has been successfully programmed this is the standard operation of the boot code resident in the flash memory device If the LED does not light at power on check that you have the mounting pillars and screws fitted properly If it stays on the DSP is not booting correctly or is set to boot in a non standard way LED Register 0x900D0000 31 4 3 2 1 0 LED LED LED LED D10 D9
18. erating GCONAIMON S uuioninaaanr cata nee esse 20 A O ne ou ns ec eee ee 20 EMG us AAA AAA AAA 20 General Requirements sra ds 20 Power CONSUMPHONE SSSR s 20 a 20 Connector PositionS www wa KIKA KIHEHE WAKIKE KUKIWA KIKE KI KIKI KU KIWE Kaka Ka saa 21 Serial Ports amp Other DSP N O de ann es 22 FPGA and CPLD JTAG iia 22 FPGA configuration dani 22 Virtex Memory Mapas 23 SHB PIU Ei a ed T 25 SHB Genere DINO ussicicanaca int venequsinedvendteesuanleetinciteuccdaaes 25 32 bits SDB IMM sotano 26 Bibliography naciona 27 GOK SPRINT EIRE 28 Contacting Sundance You can contact Sundance for additional information by login onto the Sundance support forum Version 2 3 Page 5 of 28 SMT365 User Manual Notational Conventions DSP The terms DSP C64xx and TMS320C64xx will be used interchangeably throughout this document SDB The term SDB will be used throughout this document to refer to the Sundance Digital Bus interface SHB The term SHB will be used throughout this document to refer to the Sundance High speed Bus interface Register Descriptions The format of registers is described using diagrams of the following form 31 24 23 16 15 8 7 0 OFLAGLEVEL R 00000000 RW 10000000 R 00000000 R 10000000 The digits at the top of the diagram indicate bit positions within the register and the central section names bits or bit fields The bottom row describes what may be done to the field and its value after re
19. ou need to write to the following address as shown the data written is irrelevant Address Flash page selected 0x6C000000 Page 0 1 and 3 sections enabled 0x6C000001 Page 1 2 and 4 sections enabled The EMIFB CE3 space control register should be programmed with the value OxOOCFFFO3 for optimum access speed to the CPLD Version 2 3 Page 13 of 28 SMT365 User Manual This mechanism is identical in operation to that needed for the largest ZBTRAM chipsets Virtex FPGA The FPGA Field Programmable Gate Array is a Xilinx Virtex Il device XC2V2000 or XC2V 1000 Is is mapped on EMIFA CE1 as a 32 bit SDRAM It implements the following communication resources e Six comport interfaces e Two 32 bit Sundance digital bus interfaces e One global bus interface Version control Revision numbers for both the boot code and FPGA firmware are stored in the Flash ROM during programming as zero terminated ASCII strings The SMT6001 utility can be used to display the version numbers of the bootloader and the FPGA data Firmware versions The SMT6001 utility includes the latest version of the bootloader and the latest version of the FPGA data that implements the FPGA architecture described in the SMT6500 help file Note that the new firmware does not support the 16 bit SDB interfaces Only two 32 bit SDB interfaces are presented on the TIM connectors Customers who wish to use the old firmware that supported 16 bit o
20. ptions can obtain it from our support web forum Reprogramming the firmware and boot code The contents of the flash ROM are managed using the SMT6001 utility This includes the latest firmware and bootloader along with complete documentation on how to reprogram the ROM The utility assumes that you have Code Composer Studio installed and that it has been configured correctly for the installed TIMs The Sundance Wizard can help you with this To confirm that the ROM has been programmed correctly you should run the confidence test in the BoardInfo utility SMT6300 Version 2 3 Page 14 of 28 SMT365 User Manual Comports The DSP has six comports numbered 0 to 5 The addresses of the ComPort registers are described in the SMT6400 help file SHB The SMT365 has two SHB connectors both of which are connected to the DSP to give 32 bit SDB interfaces These interfaces operate with a fixed clock rate of 100MHz Architecture SDBO and SDB2 on the DSP are presented on the TIM s SHB connectors SHBA and SHBB respectively rsd J Eg CHSC nr r e r e ea ec e s sr s OTHE SEHeESHESHS SHS HE HSE HEH HH HES 000000000000 Peete eeeeSeseeeeeseeeeo ese eee SHER SHBA ose FoTHEHFHHEHEFHEFSHSHEHEFCHHE HEHE HES ee SMT36S VI sisisi siiis fe 2AA Sundance unaanza The addresses of the SDB registers are shown in the Virtex Memory Map and are described in the SMT6400 help file Global bus The SMT365 provi
21. rds and I O modules Use of the TIM on SMT327 cPCI motherboards may require a firmware upgrade If LED D6 on the SMT365 remains illuminated once the TIM is plugged in and powered up the SMT327 needs the upgrade The latest firmware is supplied with all new boards shipped Please contact Sundance directly if you have an older board and need the upgrade The external ambient temperature must remain between 0 C and 40 C and the relative humidity must not exceed 95 non condensing Power Consumption The power consumption of this TIM is dependent on the operating conditions in terms of core activity and I O activity The maximum power consumption is 10W Weight SMT365 weigh approximately 56 25 grams SMT365 User Manual Page 21 of 28 Version 2 3 Connector Positions SHBB CPLD amp FPGA TAG He E SMT365VI lc 12882 Sundance Technology Uta OLD LUMNNONNNNONNIRE 3 core Ss i pd es exon es D ENT LT mw 3 E CTA mn 3 QUE ya E gi us 8 z cda sa ea FE FS s ES Version 2 3 Serial Ports amp Other DSP I O Page 22 of 28 SMT365 User Manual The DSP contains various I O ports These signals are connected to a 0 1 pitch DIL pin header The pin out of this connector is shown here z O Fn DD gt r O wv TTL1 TTLO GND GND GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIOO CLK 6 CLK 4 TTL3 TTL2 V33 V33 GPIO15 GPIO1
22. set Shaded fields are reserved and should only ever be written with zeroes R Readable by the CPU W Writeable by the CPU RW Readable and writeable by the CPU Binary digits indicate the value of the field after reset Version 2 3 Page 6 of 28 SMT365 User Manual Outline Description The SMT365 is a DSP module size 1 TIM offering the following features TMS320C6416 processor running at 600MHzZ Six 20MB s comports 8MB of ZBTRAM 133MHz 8MBytes Flash ROM Global Bus connector D oO O0 O 0 LO 2 SHB connectors for high speed data transfer Intended Audience There are two existing versions of the firmware for the SMT365 These two versions differ by the number and the type of communication resources comport and SDB interfaces provided For each of the versions of the different firmware is loaded in the FPGA Firmware version 1 0 or Firmware version 2 0 This user manual covers the version 2 0 of the firmware for the SMT365 implemented with the model described in the SMT6500 help file The changes between the firmware version 1 0 and version 2 0 are described in the section Firmware versions Version 2 3 Page 7 of 28 SMT365 User Manual Block Diagram The following drawing shows the block diagram of the SMT365 module The main components of the SMT365 are a Texas Instruments DSPs One Xilinx FPGA Virtex Il device 8MB of ZBTRAM DC DC converters 1 5V and 1 4V J1 TOP Primary TIM conne
23. st be specified together with the routing information in the timer control register 31 6 5 4 3 0 Reserved TCLK1 TCLKO Reserved Field Description TIM TCLKO i i TCLKO 0 CLKO is an input 1 Enable TIM TCLKO as an output TCLKA O TIM TCLK is an input 1 Enable TIM TCLK1 as an output If the TIM TCLKx pin is selected as an output the DSP TOUTx signal will be used to drive it The TIM TCLKx pin will always drive the DSP TINPx input The Timer control register is described in the SMT6400 help file Version 2 3 Page 18 of 28 SMT365 User Manual IIOF interrupt The firmware can generate pulses on the external interrupt lines of the TIM Only the interrupt line IIOF1 and IIOF2 are connected from to the DSP and the HOST e IOF1 is connected from the DSP side to the HOST side so the DSP interrupts the HOST e llOF2 is connected from the HOST side to the DSP side so the HOST interrupts the DSP The IIOF interrupt lines are described in the SMT6400 help file FPGA space availability Latest firmware version is designed in VHDL following the model described in the SMT6500 help file Depending on the FPGA fitted on board two firmware versions are available e SMT365 32 2 Virtex Il 2000 32 bit SDB interfaces e SMT365_32_1 Virtex Il 1000 32 bit SDB interfaces The table below gives the device utilization summary after place and route SMT365 v1000 32 SMT365 v2000 32 Number of RAMB16s 55
Download Pdf Manuals
Related Search