boosting simulation performance of uvm registers in high
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1. if transform complete 0 begin int max burst length if axi master cfg extended burst enabled max burst length 4096 bus width else 16 burst length bytes to send 1 max burst length bus width 1 lt max burst length bytes to send 1 bus width 1 max burst length burst size bus width bytes sent burst length bus width if rw reg item kind UVM WRITE rw reg item kind UVM BURST WRITE begin for int i 0 i lt burst length i begin for int curr byte 0 curr byte lt reg or mem bits 8 curr byte burst size begin reg data q 0 reg data q 0 gt gt curr byte 8 axi data q push back reg data q 0 amp 1 bl lt lt axi rw item size 8 1 end void reg data q pop front end end end E Populate the bus transaction axi rw item axi item t type id create axi rw item addr burst_addr axi rw item burst length burst length 1 axi rw item burst burst length gt 1 AXI_INCR AXI_FIXED axi_rw_item size burst_size if rw reg item kind UVM WRITE rw reg item kind UVM BURST WRITE begin axi rw item read or write AXI TRANS WRITE axi rw item data words axi data a end else if rw reg item kind UVM READ rw reg item kind UVM BURST READ axi rw item read or write AXI TRANS READ After transformation is complete we update the uvm reg bus op c object to hold the number of bits consumed and pass2. int n_access extra n_access uvm sequence item bus req bus reg q uvm reg bus op rw access Xget bus infoX rw map info n bits lsb skip UVM DA TO QUEUE addrs map info addr if rw element kind UVM MEM foreach addrs i addrs i addrs i map_info mem_range stride rw offset if rw element kind UVM FIELD begin extra bits lsb bus width bits if adapter supports byte enable begin int idx extra bits 8 9 int access bits extra bits 8 n bits byte en 0 while access bits gt 0 begin byte en idx 1 bl access bits 8 end end for int i 0 i lt addr skip i void addrs pop front foreach rw value val_idx rw value val_idx rw value val_idx lt lt extra_bits end n bits total n bits rw value size rw access byte en byte en rw_access kind rw kind rw access n bits n bits total rw_access addr addrs 0 adapter m set item rw bus req q adapter reg2bus arr rw access adapter m set item null if bus req q size 0 begin foreach rw value val idx begin foreach value uvm reg data L value rw value val_idx foreach addrs i begin foreach addr uvm reg data t data data value gt gt curr byte 8 amp 1 bl lt lt bus width 8 1 uvm info get type name sformatf Writing h 0h at h Oh via map s data addrs i rw map get full name UVM FULL if rw element kind
3. reg write reg read bus seq item Sequence running directly on the ma Sequence bus access Figure 1 Verification Environment with UVM Registers Integrated 2 CURRNET UVM REGISTERS FRONT DOOR ACCESS IMPLEMENTATION The way the UVM register library front door access is currently designed is illustrated as follows 1 a field register or memory write read call shall invoke a field register or memory do_write do_read 2 a field register or memory do_write do_read will invoke a map do_write do_read 3 a map do_write do_read will invoke a map do_bus_write do_bus_read which will invoke the adapter reg2bus for converting a register transaction to the corresponding bus transaction to be executed afterwards The current SystemVerilog 5 implementation of the map do_bus_write and similarly do_bus_read method in the UVM register library is as follows task uvm reg map do bus write uvm reg item rw uvm sequencer base sequencer uvm reg adapter adapter get bus info rw map info n bits lsb skip addrs map info addr foreach rw value val_idx begin if rw element kind UVM FIELD begin end foreach addrs i begin uvm sequence item bus red uvm reg bus op rw access uvm reg data logic t data value gt gt curr byte 8 amp 1 bl lt lt bus width 8 1 if rw element kind UVM FIELD for int z 0 z lt bus width z
4. rw access byte en z byte en curr byte z rw access kind rw kind rw access addr addrs i rw access data data rw access byte en byte en rw access n bits n bits gt bus width 8 bus width 8 n bits bus red adapter reg2bus rw access bus req set sequencer sequencer rw parent start item bus req rw prior rw parent finish item bus red end end endtask The method first captures the information of the item accessing it i e address es of the item number of bits to update address offset and data It captures some additional information in case of a field access It also captures the corresponding bus width The dynamic array value holds the write data in case of a write or to hold the read data in case of read In case of read write value will be a single element array In case of burst read burst write i e item is a memory value will hold multiple elements The queue addrs is a queue holding the address es of an item The number of elements in addrs depends on the item s width with respect to the bus width If the item s width is smaller than or equal to the bus width the addrs queue will hold single element otherwise the number of elements in the array will be equal to the item s width divided by the bus width As shown in the above implementation the do bus write will loop over value elements Then in each iteration loop over each item addresses In each inner i
5. UVM FIELD begin for int z 0 z lt bus_width zt rw access byte en z byte en curr bytet z end rw access kind rw kind rw access addr addrs i rw access data data rw access n bits n bits gt bus width 8 bus width 8 n bits rw access byte en byte en adapter m set item rw bus req adapter reg2bus rw access adapter m set item null if bus req null uvm fatal RegMem adapter adapter get name didnt return a bus transaction bus req q push back bus req curr byte bus width n bits bus width 8 end foreach addr foreach addrs i addrs i addrs i map_info mem_range stride end foreach value end foreach bus req q i begin uvm sequence item bus red bus req q il bus req set sequencer sequencer rw parent start item bus reg rw prior if rw parent null amp amp rw access addr addrs 0 rw parent mid do rw rw parent finish item bus red bus req end event wait on if adapter provides responses begin uvm sequence item bus rsp uvm access e op rw parent get base response bus rsp adapter bus2reg bus rsp rw access end else begin adapter bus2reg bus req rw access end if rw parent null amp amp rw access addr addrs addrs size 1 rw parent post do rw rw status rw access status if rw status UVM NOT OK break end endtask do bus write
6. endtask The proposed implementation avoids chopping data in bus width chunks and lets the adapter s reg2bus method decide the amount of data it is going to put in a bus transaction according to its bus capabilities We start doing the same regular tasks getting item and bus information The total amount of bits to be accessed and the start address were then marked and passed to the register item transaction We keep on looping conditionally until there are no more bits to access In each iteration the adapter reg2bus would consume as many bits as it could from the register item transaction according to its bus capabilities converting the register item transaction to a suitable transaction for the bus lying underneath The reg2bus then notifies the do_bus_write with the amount of bits it consumed via the sync object uvm_reg_bus_op_c_write which the do_bus_write gets a handle of via the resources DB uvm config db The uvm reg bus op c is a very simple class used for sharing data between the reg2bus adapter method and the 3 Resource DB was introduced in UVM for data sharing Please refer to the UVM user manual for more information do bus write The reason it is needed is because only the reg2bus knows how many bits it consumed however the info is required by the do_bus_write to know if it needs to re iterate The problem could have gone away if reg2bus returns an array of bus transactions however the curren
7. more details 1 1 4 Integrating UVM Registers in the testbench environment Typically UVM register models are integrated in the testbench environment by doing the following steps s Build register database by constructing the register blocks in the test and pass their handles to testbench components via configuration objects e Build a register adaption layer a component to translate register transactions to bus transactions and vice versa This can be achieved by extending the uvm reg adapter base class and providing an implementation for reg2bus and bus2reg methods e Construct the register adapter object in the testbench environment and connect it as well as the agent sequencer to the register map via the set_sequencer method e Build a predictor component acting as a listener on the bus by extending the uvm_reg_predictor class implementing its write method The predictor is used to convert bus transactions to register transactions then update the corresponding register model or if desired compare the register model value to the actual hardware register value e Construct the predictor object in the testbench environment and connect it to the bus agent monitor analysis port using normal UVM Transaction Level Modeling TLM analysis port connections The following figure represents a verification environment with UVM registers integrated 4 Register Model Register Model based sequence Sequence
8. byte bus width begin int ones 0 byte en chunk rw byte en gt gt curr byte amp 4 The set_type_override method is used to override specific types with others using the OOP factory terminology 1 bl lt lt bus_width 1 for int i 0 ic bus_width i if byte en chunk i 1 ones 1 if ones gt 0 begin bytes sent ones burst length 1 end end rg field get parent parent reg bytes rg get n bits 1 8 1 burst size parent reg bytes gt bus width bus width parent reg bytes if rw reg item kind UVM WRITE begin for int curr byte 0 curr byte lt burst size burst length curr byte burst size begin reg data q 0 reg data q 0 gt gt curr byte 8 axi data q push back reg data q 0 1 end void reg data q pop front end end C Unaligned address or bytes to send smaller than bus width Fixed burst with single beat else begin for int i 2 i lt bus width i i 2 if byte_addr i i 2 bytes to send lt i begin burst length 1 burst size i 2 bytes_sent 1 27 transform complete 1 if rw reg item kind UVM WRITE rw reg item kind UVM BURST WRITE begin axi data q push back reg data q 0 amp 1 bl lt lt burst size 8 1 reg data q 0 reg data q 0 gt gt burst size 8 end break end end D Accessing register or memory with number of bytes greater than or equal to bus width
9. for int j 0 k 0 j lt read data q size j k begin rw value k 0 for int curr byte 0 curr byte lt UVM REG BYTENABLE WIDTH curr_byte bus_width if curr byte gt 0 begin j if j gt read data q size break end read data q j read data q j amp 1 lt lt bus width 8 1 rw value k read data q j lt lt curr byte 8 if rw element kind UVM FIELD rw value k rw value k gt gt extra bits amp l lt lt n_bits 1 if rw status UVM IS OK amp amp read data qlj 1 bx rw status UVM HAS X end end if rw parent null amp amp rw_access addr addrs addrs size 1 rw parent post do rw end endtask APPENDIX B DEMONSTRATION OF SOME OF THE REQUIRED MODIFICATIONS IN THE UVM REGISTERS LIBRARY FOR HANDLING HIGH SPEED BUSES EFFICIENTLY typedef uvm sequence item uvm sequence item q virtual class uvm reg adapter extends uvm object virtual function uvm sequence item q reg2bus arr const ref uvm reg bus op rw endfunction endclass task uvm reg map do bus write uvm reg item rw uvm sequencer base sequencer uvm reg adapter adapter uvm reg addr t addrs uvm_reg map system_map get_root_map int unsigned bus width get n bytes int unsigned bus width bits bus width 8 uvm reg byte en t byte en 1 uvm reg map info map info int n_bits int lsb skip addr_skip n bits total extra_bits int unsigned curr byte
10. it to the resource DB then return the bus transaction uvm reg bus op c 1 new uvm reg bus op c 1 n bits bytes sent 8 if rw reg item kind UVM WRITE rw reg item kind UVM BURST WRITE uvm config db uvm_reg bus op c set null x rw access adapter write uvm reg bus op c 1 else uvm config db uvm_reg_bus_op_c set null ux rw access adapter read uvm_reg bus op c 1 return axi_rw_item endfunction In some circumstances you may have limitations or constraints on the bus that certain kinds of bus capabilities could not be utilized the above code can be easily extended to take bus limitations and constraints into consideration when generating the burst All what is needed would be a handle of the bus configuration object being passed to the adapter the reg2bus would check if a chosen burst feature is not supported and re iterate if needed 3 2 2 bus2reg for an AMBA AXI Typically bus2reg implementation would be relatively simple since we will be listening to lower level transactions i e read and write beats and not high level bursts Therefore it will convert lower level bus beats transactions to register transactions It may need to listen to higher level read AXI bursts to get the whole burst data for the do_bus_read method as shown below virtual function void bus2reg uvm_sequence item bus item ref uvm reg bus op rw if cast axi rw beat bus item begin if
11. number of commercial UVM register generator tools that can capture register specification from spreadsheet IP XACT and XML inputs Below we provide a quick overview of the different UVM classes used to build your register database 1 1 1 Field A group of bits providing specific functionality in a hardware register It is modeled in the UVM register library using the uvm_reg_field class and configured using the uvm_reg_field configure method 1 1 2 A hardware register model grouping fields at different offsets within the register It is modeled in the UVM register library by extending the uvm_reg base class adding rand objects of uvm_reg_field type and configured using the uvm reg configure method Register 1 1 3 A memory block with well defined address range It is modeled in the UVM register library by extending the uvm mem base class defining the memory block specifications inside the constructor new and configured using the uvm mem configure method 1 1 4 Block Groups registers memories and sub blocks It is modeled in the UVM register library by extending the uvm_reg_block base class then instantiating and configuring registers memories and sub blocks inside its build method 115 Map Locates the address offset of registers memories and sub blocks within a block It is modeled in the UVM register library by instantiating an object of uvm reg map class in a block Registers and memories are added t
12. AD IMPLEMENTATION task do bus read uvm reg item rw uvm_sequencer base sequencer uvm reg adapter adapter typedef uvm reg data t data q t data _ q t read data q int unsigned bus_width get n bytes int unsigned bus width bits bus width 8 uvm reg byte en t byte en 1 uvm_reg map info map info uvm reg addr t start address addrs int lsb addr_skip n bits n bits total extra bits uvm sequence item bus red bus red 4 uvm reg bus op rw access uvm reg bus op c uvm_reg bus op c read new Xget bus infoX rw map info n bits lsb addr_skip UVM DA TO OUEUE addrs map_info addr if rw element kind UVM FIELD begin extra bits lsb bus width bits if adapter supports byte enable begin int idx extra bits 8 o int access bits extra bits 8 n bits byte_en Shy while access bits gt 0 begin byte_en idx 1 bl access bits 8 end end for int i 0 i lt addr skip i void addrs pop front end n_bits_total n_bits rw value size start_address addrs 0 TW access byte en byte en rw_access kind rw kind rw_access n bits n bits total uvm reg bus op c reg2bus read sm get 1 while rw access n bits gt 0 begin rw_access addr start_address adapter m set item rw bus red adapter reg2bus rw access if bus req null uvm fatal RegMem adapter adapter get name didnt re
13. BOOSTING SIMULATION PERFORMANCE OF UVM REGISTERS IN HIGH PERFORMANCE SYSTEMS Ahmed Yehia Mentor Graphics Corp Cairo Egypt ahmed_yehia mentor com ABSTRACT Registers and memory blocks are key parts of any design a typical design could hold hundreds of them Verifying the behavior of registers and memory blocks is an essential part in the verification process There are many techniques for modeling and verifying hardware registers and memory blocks In this paper we focus on verifying hardware registers using register packages Verification and modeling of hardware registers and memory blocks via register packages is not a new trend Many register packages from various vendors written in different languages currently exist and used in the industry The Accellera VIP TSC committee has made a significant progress in releasing the Universal Verification Methodology UVM 1 defining standards for creation integration and extension of verification environments The UVM register library is an open source library being part of the UVM library which allows modeling and verification of hardware registers and memory blocks Yet the way the UVM register library is currently designed to layer registers and memories transactions on top of bus transactions well suits low speed buses On the other hand it may not be efficient for high performance buses introducing undesired simulation performance degradation In the paper we give a quick ov
14. Scast axi rw burst bus item if axi rw burst read or write AXI TRANS READ begin typedef uvm reg data t data q t data da t read data q foreach axi_rw_burst data_words i read data q push back axi_rw_burst data_words i uvm config db data_q t set null nx bus2reg read data q read data q end else uvm info RegMem adapter this get_name bus2reg Casting failed UVM FULL return end rw kind axi rw beat read or write AXI TRANS WRITE UVM WRITE UVM READ rw addr axi rw beat addr rw data axi rw beat data rw status UVM IS OK endfunction 4 COST BENEFIT ANALYSIS AND EXPERIMENTAL RESULTS 4 1 Lines of code and complexity As demonstrated above when taking a look at the proposed implementation of do bus writer lido bus read w r t the current implementation you shall notice that lines of code and complexity are relatively close While lines of code of proposed implementation may be smaller since some of the overhead to chop data into bus bursts is moved to the reg2bus and bus2reg methods yet using the resource DB and semaphores to share data between do bus write do bus read and reg2bus bus2reg methods and to support concurrent writes or reads working around reg2bus prototype limitation add some complexities These complexities shall be eliminated if the reg2bus prototype returns an array of bus transactions On the other hand the implementa
15. ent alternative to do_bus_write making it suitable for high performance buses then we show how a powerful implementation of reg2bus and bus2reg methods shall look like in this case for an AMBA AXI bus 3 1 Efficient Alternative to Current do bus write Implementation for High Speed Buses task uvm reg map do bus write uvm reg item rw uvm sequencer base sequencer uvm reg adapter adapter uvm reg bus op c uvm reg bus op c write new get bus info rw map info n bits lsb skip addrs map info addr if rw element kind UVM FIELD begin end n bits total n bits rw value size start address addrs 0 rw access byte en byte en rw access kind rw kind rw access n bits n bits total uvm reg bus op ci reg2bus write sm get 1 while rw access n bits gt 0 begin rw access addr start address adapter m set item rw bus red adapter reg2bus rw access adapter m set item null bus req q push back bus reg uvm config db fi uvm reg bus op c get null nn rw acc adapt write uvm reg bus op c write start address uvm reg bus op c write n bits 8 get addr unit bytes rw access n bits uvm reg bus op c write n bits end uvm reg bus op c reg2bus write sm put 1 foreach bus req q i begin uvm sequence item bus red bus req q il bus_req set_sequencer sequencer rw parent start_item bus_req rw prior rw parent finish item bus_req end
16. erview of the UVM register library on how it could be used to model and verify hardware registers and memory blocks showing the simulation performance bottlenecks observed when performing on high speed buses We then present an efficient overlay layer that can be easily integrated on top of the UVM register library making the library suitable for high as well as low performance systems Then we show how an efficient yet powerful registers to AMBA AXI bus transactions adapter would look like in this case Finally we provide a cost benefit analysis on current and proposed implementations 1 INTRODUCTION Naming some of the UVM register library features e Address management e Modeling registers and memory blocks e Front door and back door access to Device under Verification DUV e Implicit and explicit prediction of registers and memory blocks values e Coverage model API Usually the integration of a register library in a testbench environment requires four abstract steps 1 building the register database 2 writing registers and memory blocks test sequences 3 configuring registers coverage as needed and 4 integrating registers models and test sequences to the testbench verification components 11 Building the Register Database Although register models could be built up manually typically register models are automatically generated using register model generators which prevent manual coding errors There are a
17. may be little trickier more details in Appendix A In the test or when building your register block just override uvm reg map With your new register map class name using the set type override method class my reg block extends uvm reg block virtual function void build uvm reg map type id set type override my reg map get type 1 endfunction endclass 3 2 Efficient implementation of reg2bus and bus2reg for an AMBA AXI bus 3 2 1 reg2bus implementation for an AMBA AXI bus Typically reg2bus will be working on high level bus transactions e g write read bursts in case of an AMBA AXI protocol A Capture the required info for optimal burst type selection virtual function uvm sequence item reg2bus const ref uvm reg bus op rw rw reg item get item reg data q rw reg item value burst addr rw addr map rw reg item local map bus width map get n bytes bytes to send rw n bits 1 8 1 lt 4096 rw n bits 1 8 1 4096 In the code below we capture different scenarios 1 field access 2 register or memory access with unaligned address or number of bytes smaller than bus width and 3 register or memory access with number of bytes greater than or equal to bus width B Field access accomodating for fields wider than bus width by sending INCR bursts if amp rw byte en 0 begin for int curr byte 0 curr byte lt UVM REG BYTENABLE WIDTH curr
18. nk and avoiding making use of bus powerful features when found As a result the amount of transactions generated is maximized which in turn would maximize context switching during simulation that would badly affect simulation performance We presented an alternative implementation that avoids chopping data passing the decision making to the adapter translating from register transactions to bus transactions letting it decide how many of the data it could consume in one transaction This way the bottleneck is moved to the adapter and the corresponding bus architecture The current prototype of the reg2bus in the UVM library allows returning only one transaction although it would have been much better if the method returns array of transactions A cost benefit analysis showed that in terms of lines of code count code complexity and use model current and proposed implementations are similar However when it comes to simulation performance the proposed implementation can super exceed the current implementation on high performance buses 6 REFERENCES 1 UVM User Manual uvmworld org 2 UVM Reference uvmworld org 8 UVM Open Source Kit uvmworld org 4 UVM OVM Cookbook verificationacademy com uvm ovm 5 IEEE Standard for SystemVerilog Unified Hardware Design Specification and Verification Language IEEE Std 1800 2009 2009 6 AMBA AXI reference infocenter arm com APPENDIX A OVERLAY REGISTER MAP DO BUS RE
19. o the address map using uvm reg map add reg and uvm reg map add mem respectively Memory 1 2 Writing Register and Memory Sequences Usually a verification engineer would like to access registers and memories writing or reading their contents The UVM register library provides write read burst write and burst read APIs for accessing registers and memories These methods get called in the sequence body method reflecting the test scenario of a user The map will locate the address of the register or the memory being accessed then handover the register transaction to an adapter which will convert them to a corresponding transaction of the bus lying underneath this is what is called the front door access The advantage of this flow is that registers and memories test sequences can be written in a generic way independent of the bus architecture lying underneath This enables verification environment reuse and portability The UVM package comes with a library of automatic sequences doing basic registers and memories tests that can be reused when necessary 1 3 Configuring Registers Coverage The UVM register library does not come with coverage models for registers however they provide the necessary API to control the instantiation and sampling of coverage models built by the user Coverage models will not be covered by this paper as they are out of its scope please refer to the registers section in the UVM user manual for
20. t method prototype in the UVM library returns only one bus transaction The hereby proposed implementation aims to be an overlay layer on top of the UVM package no edits in UVM source are required for it to function properly thus the proposed means for sharing data Since the overhead of accessing the configuration database for every bus transaction could be tangible especially for low speed buses a better solution is to extend the UVM register library to support a register to bus method that returns an array of transactions Appendix B demonstrates the extended enhancements required in the UVM register library to leverage from a register to bus reg2bus_arr method that returns an array of bus transactions for handling high as well as low performance buses while maintaining backward compatibility with current implementation The implementation of uvm_reg_bus_op_c class is as follows class uvm reg bus op c static semaphore reg2bus read sm static semaphore reg2bus write sm static semaphore bus2reg read sm int n bits function new if reg2bus write sm null reg2bus write sm new 1 if reg2bus read sm null reg2bus read sm new 1 if bus2reg read sm null bus2reg read sm new 1 endfunction endclass All what needs to be done is to extend the uvm reg map class and implement the do bus write and do bus read methods as shown above Implementation of do bus read would be similar to do bus write but
21. teration the method constructs a register transaction to be converted to bus transaction via the adapter s reg2bus method This methodology may be suitable for low performance buses however it could be inefficient for high performance buses not utilizing bus powerful features lying underneath Imagine the scenario where one is operating on an AMBA AXI 6 bus and wants to write to a 2KB memory block the current implementation will send 512 different bursts on an AMBA AXI bus of 32 bit width this looks like an inefficient way to operate on an AMBA AXI Instead 32 bursts 16 beats each could be sent or even a single burst of 512 beats if your system permits extended burst length Each time you send an extra burst on AMBA AXT bus you lose at least two cycles in the case of a write and one cycle in the case of a read Maximizing the number of bursts maximizes context switching in simulation which may have severe consequences on simulation performance imagining a test performing hundreds of these operations An item is typically a field register or a memory location 2 Analysis assuming simple AMBA AXI where data phase follows address phase by at least one clock cycle 3 ALTERNATIVE IMPLEMENTATION TO CURRENT UVM REGISTERS FRONT DOOR ACCESS As stated previously the current do bus write implementation creates an undesired bottleneck when performing on high performance buses In the following subsections we represent an effici
22. that generates an array of bus transactions Appendix B demonstrates the required extensions in detail 43 Experimental Results The following figure describes how simulation performance is affected when executing unnecessary bursts attempting to perform a write to a 2KB memory on an AMBA AXI bus of 32 bit width As shown below simulation performance of the proposed implementation can be five times better than the current implementation The current implementation will send 512 different AXI bursts point A on the graph represents normalized simulation CPU time and cycles for the current implementation The proposed implementation can send one burst with 512 different beats reducing context switching and eliminating extra cycles reducing simulation time and cycles to point B on the graph Current Implementation 0 6 Proposed Implementation s Simulation cycles Simulation time cycles norm 0 4 norm a3 m Simulation cpu i time norm 0 T 1 4 16 64 256 1024 Number of bursts Figure 2 Effect of Executing Unnecessary AMBA AXI Bursts on Simulation Performance accessing a 2KB memory block 5 CONCLUSION The paper has shed some light on current UVM registers front door access implementation In summary the current implementation inserts undesired bottleneck when performing on high performance buses by chopping data in bus width chunks generating a simple transaction for each chu
23. tion of bus2reg reg2bus methods in the proposed implementation would be more complex if one wants to benefit from a high performance bus powerful features Or rather stick with simple implementation of these methods for a trade off with simulation performance 42 Simulation Performance The number of simulation cycles depends on the number of transactions executed the greater the number of executed transactions the greater the simulation cycles and hence longer the simulation time will be The proposed implementation attempts to send the smallest amount of bus transactions possible On the other hand the current implementation sends the maximum amount Simulation performance is affected by the amount of context switching in your code Each time you generate and execute an extra transaction context is switched from the UVM registers context to the bus driver context thus maximizing the number of transaction executed which would hurt simulation performance This makes the proposed implementation suitable for high performance buses as it just moves the bottleneck from the UVM registers to the adapter implementation and the corresponding bus architecture On Low performance buses the overhead of accessing the resource DB for every bus transaction could be tangible resulting in a slight performance degradation w r t current implementation An ultimate resolution is to extend the UVM register library to support a register to bus method
24. turn a bus transaction bus Ced q push back bus red uvm config db fi uvm reg bus op c get null rw access adapter read uvm reg bus op c read if uvm reg bus op c read null uvm fatal RegMem adapter adapter get name Means of communication is broken between adapter reg2bus and reg mem map do bus write if uvm reg bus op c read n bits 0 uvm fatal RegMem adapter adapter get name Adapter returned n bits of zero this could result in an infinite loop start_address uvm reg bus op c read n bits 8 get addr unit bytes rw access n bits uvm reg bus op c read n bits end uvm reg bus op c reg2bus read sm put 1 foreach bus req q i begin uvm sequence item bus red bus red q il bus req set sequencer sequencer rw parent start item bus reg rw prior if rw parent null amp amp rw access addr addrs 0 begin rw parent pre do 1 rw parent mid do rw end rw parent finish item bus req bus req end event wait on uvm reg bus op c bus2reg read sm get 1 if adapter provides responses begin uvm sequence item bus rsp uvm access e op rw parent get base response bus rsp adapter bus2reg bus rsp rw access end else begin adapter bus2reg bus req rw access end uvm config db f data da t get null bus2reg read data a read data q uvm reg bus op c bus2reg read sm put 1 rw status rw access status
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