Solar Sudden Ionospheric Disturbance Monitor
Contents
1. seseeesssseeseeeeereeeesssssssssssseeeseceereeesssssssssss 12 Feur I Ando OUMU oi E E E O 13 Fiseure IA DATA Output Creuen ET Eve aba Ua eae aee eave 14 Fisure 45 DA TAO Output Calibration N OlES sc eee e a vto tb tate ie tab etta tota es 14 Figure 16 SIDMON Component PIacerenL 5u eee nere toda vanes re eeu repeat etel end te eee ees 15 Figure L7 BREOBDOARD Component Pldcerebl 5 eio ober tot Ree aera ai eee 15 Froure 13 SIDMON PCB Lop Lay uet ederet a anion ee Dota ecu SU RU Ua Un 16 Figure 19 SIDMON PCB Boton LaL aetati vo ett eure so det x T 16 Fisure 20 PREOBOARD PEB Top ay Ct oue osa roc eI Diei tre Peowe ud a uet css iueaiates 17 Figure 21 FREQBOARD PCB Bottom Layer ite roba eto Eee tee oae re tre tu he to A py Lieute 22 55 25 Vot Power Supply acest eu abc br pese bue sb doped i stulte d e suique uites 20 Prsure 2 gt Pre POst AMPH let scatet tho folie atte a ode attotet aen toii duet bi tone uet 21 Figure 24 Audio and Analog Data Outputs essere eene nnne 22 Figute 25 Frequency Tuning BOO osos oerte detta ees eahe dtd getestet epum te gases be di aad cede eset enu dE PESE 29 SIDMON Chassis Controls Status and Connections Figure 1 SIDMON Front Panel Connectors Status Controls Details See Circuit AUDIO Powered Speakers 1 8 stereo jack Audio Output Line in out level Xl X5 X10 Post Gain Switch 3 pos Post Amp Circuit RF GAIN ADJUST Preamp 200KO Rs ANTENNA INPUT2. SID Detector 5 5 Volt Power Supply Deacument Numbers Dasignad by Bill Clark amp Ray PMitchall layout Figure 22 5 5 Volt Power Supply 20 Pre Post Amplifiers Fraguancy Board NOTE Berauss the header nf the Freg hoard is aoldsrsd om revers side of hoard Mapping between hnarda 172 271 3 4 423 ste Ahtshha lhput SIGNALS POWERING INPUT F OB 1 1 3 NEG Sv F oB 2 4 C351 FRE O A F oB 5 7 Pos BV FoB a3 10 10 FREO OUT FoR 8 5 4 3 4ND FoB 6 3 7 TLE2na2rP FOB is Frequency hoard PIN PREO 4 aighal ia not commected used Tor calikrati un Sho Casas Dnhh sctiona Ir5 2 SISNAL DETECT p n POST AMP SAN SWITCH 11814A Document Numbers Dasigqnad by Bill Clark amp Ray Mitchall layout Date 5 62 7005 l8 452555 sheet 2 3 Figure 23 Pre Post Amplifier Zl Audio and Analog Data Outputs SIGNAL DETECT 4 7 HnN P OLAR IpA3Gtz E14 p T LINE OUT AUDIO OUTPUT ae SIGNAL STRENGTH 3 Daas 1 ILEO 1 7 LT148n LT1490 z ccu DATA OUTPUT F n n n ri ANALO DATA OUTPUT Audio and Analog Data Outputs TITLE S810 Detector Document Numbers Dasignad by Gill Clark amp Ray Mitchall layout Figure 24 Audio and Analog Data Outputs 22 Frequency Tuning Board MOTE Headstaoldsted of testas aids of board Mapping between hnarda 172 271 3 4 453 ste z FREO GUT SS eed Input MB 2 2 4 NEG Sv MB 4 3 FREG amp MB B 3
3. 10 POS 5Y MB 7 H LLL SIGNAL IN FREG OUT MB 10 6 4 7 4ND MB 5 4 3 SSH ALS POWERS AD MB ia Pd ath rh n ard PINAY SIGNAL IN Dn 1uF IE10D FREn A a m BPOA BPDE FREQ A lt _ im Eo pm mmm 3 v AND AND Bane AND AND MA227SB CCP v C C 5v SND AND 5y 5v BRIA BPIB thos LPOB R2nD2 FREQ GUT FEA FCB Em 3 iu 2 im R200 Inital R saistot walu sa Tor 24 3 H2 R101 R201 14301 R102 R202 B al R103 R203 5441 R104 R204 751 R100 R200 101 fdultitum Top Adj FREQENCY TUNING BOARD TITLE FreqBoard Document Numbers BEL Dasiqnad by Gill Clark amp Ray Mitchall Layout 1 Date b 02 720B5 18s 48 55p sheet 1 1 Figure 25 Frequency Tuning Board 23
4. dude dura 17 Appendix D Test Potnts GIOS Sily pencurian Ee ebd eem Ve Gates ye eive Ru r vecdsbrads 18 pehdrc E Pans LE ks cootra dnte ha dn Tyee E 19 PRT Es CMI AICS ii astra masa mtu usb ae te hain a ie aetna ae den aM anu ed PME M d DUE 20 5 2 Volt Power SUDDLy esekien ann A ETa EER ESS 20 Pre Post AMPIE A 21 Audio and Analog Data Qutp ts sessi E 22 Frequency Tonine BOSE sireno n eater i Coto Reese dedit tu 23 Table of figures Peme dq PINION ROME Ele laoreet casio otio cee Sree tette E bote ne at 3 Lioute 25 5IDMON Rear T ael ccce Nuit m Es bn xD Sein tette tu tM UE Es up ma cM TUS 3 Fisure 2 5IDMON Circuit DOG ioci per PER E cusa osito Gd r 4 Pictte 4 POWER SUPP 55e pot iat A ite aaaupecniieh atassutuen se hauanuaeceen oes 5 Fisure 2 Preamp ere a Geile dlveuatusseer Go debut ie E bus ecd debut latte E bag eee 6 Ligure O Fier CIT CUT eo ooeie a reer em vac fat eevee er ene ree ere eer 7 Picure Zo Power Supply Filter C aps oieucistietdtidiueleu aeta iode ee tst adea eerie 7 Figure 8 Connections on SIDMON and Frequency boards cccccccccccessssseeeeeeeeeeeeaeeesseeceeeeeenaas 8 Figure 9 Test Fixture left Schematic right the homemade attenuator circuit 9 Fisure 10 Example ot Tunns a SIDMON incor oss tetaws eae paed ness toe tee rence QUUM ces erent eeaeneosen 10 PS ure LE oci Gri do 11 Figure 12 Amplitude Modulation Detection Circuit
5. EE SND POWER INPUT 8 AC 100 mA 1M4an 1 n S 1H3un 1 r1 ul D4 14001 F A Figure 4 Power Supply The input is a 2 5mm x 5 0mm jack that accepts the 9 10 volt AC wall transformer The fuse F1 is a re settable 250mA circuit breaker If there is a short circuit the fuse will open and remain open until the power is removed and the fuse cools down The AC to DC voltage conversion is achieved by a half wave rectifier diodes D and D2 and smoothed by capacitors C and C Higher frequencies bypassed by Cs and C6 The DC working voltage on these caps should be rated at two times the input voltage plus we added 50 more as a precaution therefore WVDC 2 5 x Va input voltage 25 VDC The power supply is a typical design per recommendations from the manufacture s application sheets for the 5 volt supply IC 78L05 and 5 volt supply IC 79L05 We used the L versions of the regulator for their characteristics of both lower dropout voltages and over current regulation properties The diodes D3 D4 Ds De prevent a reverse voltage situation that can result when the capacitors are charged up and power reapplied on the input Caps C3 C4 C7 and Cg are part of the filtering and recommended design by the manufacturer The two status LED s visible on the front panel show independently that both power supplies are functioning The LED color assignments are as follows 5V is green 5V is yellow Ove
6. Ray Mitchell amp Gill Clark Auquet 2004 kmri ep Emu Hiri d REOR Hanh 5y 10 6 wu eos On ROR OR Stanfard University PL Solar SIO Project GHD Figure 17 FREQBOARD Component Placement 15 Appendix B SIDMON PCB Artwork Figure 18 SIDMON PCB Top Layer Figure 19 SIDMON PCB Bottom Layer 16 Appendix C FREQBOARD PCB Artwork O Figure 20 FREQBOARD PCB Top Layer Figure 21 FREQBOARD PCB Bottom Layer 17 Appendix D Test Points Glossary SIDMON PREAMP PREAMP Return signal from Frequency board should have been output of Op Amp ICA G 1 STRENGTH Integrated signal DC level DATA OUTPUT Shifted DC level FREQBOARD Test Point Name 5 Volt supply 5 Volt supply Ground 0 volt reference FREQ A First stage frequency filter used for calibration FREQ B Second stage frequency filter used for calibration Same as FILTER_OUT Test Point signal on SIDMON board 18 Appendix E Parts List 80 C315C104M5U O 1uF Monolithic C18 C20 C103 C104 C105 MOUSER 271267K pe RT MOUSER a7i 40 2K Hook R20 271499K gHo9K RI 612 EG2308 651 1803578 Analog output mating Screw terminal N A external part mates with J4 19 Appendix F Schematics 5 5 Volt Power Supply E pzzoRN 44 1H 4nn4 E a Reasttabls Fus F1 TIF PS wo zWITEH P LEEW AND POWER INPUT 8 WAC 100 mA wg D4 1N4001 pzzvEgL amp TITLE
7. Solar Sudden onospheric Disturbance Monitor Technical Manual Authors Ray Mitchell Chief Engineer Bill Clark Senior Circuit Design Lead Document Status PRELIMINARY Draft Version 1 0 02 Aug 2006 Table of Contents SIDMON Chassis Controls Status and Connections 0 cee cece eeccecceccecceccecceccscescesceecescescescesceecs 3 Introduction To The SIDNION Circuit BO and sisi choi ep irme ati APER RE PER exe od oou e aderant 4 COUT OVONIE W ee ee a a ere ee ee 4 Power SUPPLY EE monlaeaanaNad 5 Preamp e CU ed entier ose uenti S 6 PrCquenCy BOOdEQ nico iode aed canes iar cance ara cee 7 Frequency Board Tuning Resistor Table cccccccsssseseseceeeeceaeeeeseseeeeseeeaeeeeeees 8 SIDMON amp Frequency Board Connectors ccccccccccccccsssesseeeeeeeeecaeeseseeeeeeeenaas 8 How 10 Tune 4 Frequency Board a eiconsectet etatdannenvesnenaedaeare une 9 POSE aii IEOUTE casse obtiev tutes tiep E 11 Amplitude Modulation Detection Circuit ccccccccccccssssseeeeceeeeeeseaeesseeeeeeeeeaaas 12 Audo OUT DU uie ban eh Ye PODES URINE oam Brutal ass Id bam idu quU Ead use tudt 13 Appendix A Component PIaCOHIE BLU re sosco bio dro erus oti Eg reo nen secede drop det et eid lo uoo nr i 15 Appendix B SIDMONCPCB ATW Obk eet eer detto oue Hie adco aen io utI ceo e de ROME aed 16 Appendix C EREODOARD PCB Artwork ied air nti deir edu ade Se eaa rela eA we xod
8. TNC Connector POWER ON Power Status Power Supply Green LED 5v Yellow LED 5v Figure 2 SIDMON Rear Panel Connectors Status Controls Details See Circuit POWER INPUT Mates w 2 1 mm x 5 5 mm plug Power Supply 9 10 VAC input voltage 7 Serial Number Area Top line Serial number S Middle Serial Number FB Bottom Frequency Station ID DATA OUTPUT Mates w Phoenix connector part DATAQ Output Circuit 803578 3 81 2P PLUG 180DEG Chassis Dimensions 5 25 13 34 cm L x 3 63 9 22 cm W x 1 825 4 636 cm 3 Introduction To The SIDMON Circuit Board This document describes the circuit design and theory of operation of the SID Monitor circuit for instructions how to calibrate and use the SID monitor please refer to the user s manual KLOD x19 is EM dis sis 5 most M arty 7 CE or reamp Ad J AE E Bi FILTER DU zi J7 dm 1 Sce ELl 1 t o 349 i 4 49 M Solar SID Project Stantord university o amp I HTTP1 Solar Center Stantord Edu F Designed ty Rey Mitchell amp Bil Clark Augie 2004 Figure 3 SIDMON Circuit Board 9 Circuit Overview Starting at the lower left of the SIDMON circuit board and working around the various signal processing stages or sections in numeric order OThe Power Supply Section takes input from the 9 10 VAC from the transformer and produces both regulated positive and nega
9. and spikes Cie stabilizes the voltage on the input to form a stable reference Stage 2 IC6 G 2 is a voltage shifter with a gain of The shifter works because the input is tied to 5 volts through R the inverter input makes the output to go to 5 Volts the midpoint between R12 and Ry form a summing point therefore translates the input DC level to 5 volts to 5 volts a 10 volt range thus making the overall signal easy enough for the DATAQ to read over it s 20 volt 10 bit range approximately 0 0195 volts per bits 2 3 Vnoon 1 667 V j 1 3 ee i Local Nighttime is Figure 15 DATAQ Output Calibration Notes The reason why user s manual suggests setting the RF gain to 1 25 to 1 5 volts at noontime is because while developing the SIDMON we had to resolve the problem of determining how much headroom was required to record M and X class flares while not sacrificing resolution for the C Flares The value of 1 5 volts was derrived by approximately using the first 1 3 of the graph to allow for noon the highest point on the graph for daytime allowing the other 2 3 of the graph to be able to record the largest flares and this level 1s usually still much higher than sunrise and sunset levels Vnoon 1 3 10 volts absolute range 5volts 1 667 Volts 14 Appendix A Component Placement Solar SID Project Stanford University HTTP Solar Center Stanford du DATA OUTPUT Designed bur
10. d x10 note that the actual gains of the amplifier are different than labeled on the box admittedly this appears to be dishonest Initially the plan was to make them the same but as the design went on it was decided to keep the labels on the box simple and make the make up gains on the output look like 1x 5x and 10x instead of the internal circuits be consistent with their external labeling For those still curious When the gains were set as advertised the resultant output voltages were not x1 x5 and x10 with respect to the switch setting This was an empirical design and then we found out later that it wasn t completely consistent with other frequency cards that have different gain characteristics It is only an approximation and in the end I have to say that this decision was done mainly for aesthetic appearances 11 Amplitude Modulation Detection Circuit 5 ae wT Ip5 f1 1 4 TLE2032rP l Ip5 2 SIGNAL DETECT gt Mm SIGNAL STRENGTH ano From Post Gain gt n 1uF R13 L zu 101 1Ha14A Rzn C21 2 M per r ano b n STRENGTH Figure 12 Amplitude Modulation Detection Circuit zn 21 This circuit is called an Absolute Value Circuit Full Wave Precision Rectifier taken from the Op Amp Design Cookbook Third Edition by Walter G Jung pp236 237 We found the circuit would sometimes go into oscillation very easily thus Cj 22 pF was necessary to eliminate the oscillation
11. es or even eliminating the RC circuit so that real time monitoring of lightning and possible GRB Gamma Ray Bursts would be possible 1t would also require to increase the cadence of the data logging etc Audio Output SIGNAL DETECT 47 NONPOLAR Ir4t2 cid nod ie RING LINE OUT AUDIO OUTPUT Figure 13 Audio Output IC4 G 2 is a unity gain buffer C44 isolates the DC component to the line out level audio output to be connected to amplified speakers do not connect directly to an 8 ohm speakers or headphones without an amplifier The connector is a stereo connector with the left and right channels connected together As of the writing of this document it is still unknown why plugging in the speaker would cause a dip in the signal strength level perhaps there is some ground loop problem that has not been detected both devices are powered by wall transformers Whatever the cause audio monitoring lowers the signal strength 13 DATAQ Output Circuit 51 SIGNAL STRENGTH 3 S ILE 31 O 1 g ICE 7 1 i E i LT1490 i LT1490 D12 a D13 DATA nuTPUT T D 1uF Jg n D 1uF nl x E zh rH r4 51 P 1 y d ANALOG DATA OUTPUT Ff a T iB Ld AND AND n aun F T Figure 14 DATAQ Output Circuit R 11 Riu 5 Dl a The LT1490 op amp allows voltages to swing from rail to rail Stage 1 IC6 G 1 has a gain of 33 127 A Rg Ryo 267K 2 8 06KQ A 33 127 Cj and C 3 dampen fluctuations
12. is board When this board is changed the SIDMON has to go through the same procedures of antenna alignment and qualification procedures as outlined in the user s manual as if it were a new monitor C101 C104 4 ruF D 1uF gi Dw Figure 7 Power Supply Filter Caps Not much to say about this pretty standard design principles used The power supply bypass capacitors were installed per manufacturer s specifications The 4 7 uF for large DC fluctuations and 0 1 uF for smaller AC spikes Frequency Board Tuning Resistor Table With the components as outlined in the schematic it is possible only to tune a very narrow range of VLE stations 24 0 NAA 24 8 NLK and 25 2 NML Frequencies above or below this range are unreachable To tune to other frequencies you need to run the filter design software from MAXIM to determine the correct values for the resistors Use 1 resistors We used the Butterworth filter with 4 poles requires 2 stages to implement the filter Frequency Range Rio R201 Rio R202 Rio R203 Rios R204 Sets Gain Sets Center frequency Sets Q Sets Center Frequency 18 3 19 0 KHz 200 0 KQ 115 0 KQ 549 0 KQ 90 9 KO 24 0 25 2 KHz 200 0 KQ 76 8 KQ 549 0 KQ 75 0 KO Resistor values untested also to do add more frequencies to this table All resistors are 1 or better Rioo and R oo are 10K Potentiometers in series with R0 and R202 respectively Calculate resistors in the sequence give
13. lest output signal possible then attenuate the signal further with a simple 2 resistor circuit See figure above Step 3 Connect probe ground lead to a GND point on the SIDMON I usually like to connect the ground clip to the top of the TNC connector see picture on next page Step 4 Use the oscilloscope probe connected to a frequency counter or oscilloscope w a built in counter to probe the FREQBOARD at the test point labeled input Adjust the RF gain control R3 on the main SIDMON board to a voltage level of 100 millivolts peak to peak Step 5 Verify the proper frequency is present Adjust the frequency generator and error of 100 Hz is okay Be sure to verify throughout the tuning process that the signal generator is on the desired frequency and hasn t drifted off I found for best results let the signal generator warm up and stabilize for a couple of hours before tuning the FREQBOARD Procedure continued on next page How to Tune a Frequency Board Procedure continued from the previous page Figure 10 Example of Tuning a SIDMON Step 6 Put the oscilloscope probe on the test point labeled Freq A As shown above Additional comment The picture above shows the finalized FREQBOARD that is to say the two pots are locked down with fingernail polish to finalize the settings and prevent further adjustment as per the instructions of the final step leave the pots unpainted until that time Step 7 Adjust Roo t
14. make up for the loss in the impedance match by increasing the RF gain The first stage of the preamp IC3 G1 TLE2082CP is a non inverted input with a gain of 201x The output DC decoupled runs to the next stage which is an inverted input has a gain that has an adjustable potentiometer R3 from O to 20x giving a total gain from the preamp stage of 0 to 4 020x The RF gain R3 potentiometer adjustment will be made by the end user and is covered in the user s manual IC3 G 1 Non Inverted op amp gain formula A Amplification A R5 R9 R5 1KQ 200KQ 1KQ A 201 Fixed gain IC3 G 2 Inverted op amp gain formula A R3 R7 00 to 200KQ IOK 2 A 0 to 20 Adjustable gain Frequency Board INPUT C105 R101 R201 SIGNAL IN gt 0 1uF IE1nn FRE 0 4 3 i4 FRED A B4o2 ie a ee al 1 JE 1 Baga FREQ GUT q 11 uA ET VE 2il i E d 10 E E Rigg R200 vw HMA amp ZZ BSBELDP v tt C G ND AND 5w Bv Figure 6 Filter Circuit The Frequency board called Freqboard is tuned before shipping The design is based on the MA X275 continuous analog filter configured as a bandpass filter The filter tuning is based on four resistors per filter and there are two filters Resistors Roo R104 are for the first filter and R200 R204 are for the second filter or stage The Frequency board is a separate PCB to make it easier to change the SIDMON s VLF frequency It would be simple process to swap th
15. n below Equations from MAXIM 274 275 Data Sheet R2 Rxo2 Rxoo 2 10 Fo Where Fo is the desired center frequency this resistor 1s R in the MAXIM document it is in series with Roo R o4 Ro SKQ Rxo4 might be less than 5KQ because of internal 5KQ resistor limits BPO loading Rxo3 Q 10 5 Fo Limits 5KQ lt Ryos lt 4MQ Roi 2 10 5 Fo Hor Hor is the gain of LPO_ at DC SIDMON amp Frequency Board Connectors SIGNAL IN amp T FREO GUT lt gt FREQ L gt SIGNAL IM SIDMON FREQBOARD Figure 8 Connections on SIDMON and Frequency boards Signal Description Pin SIDMON Side Neg 5V GND Pos 5V Signal Input 10 Freq A for tuning 6 no connection Freq B Frequency Out 100 Po 5V 79 How to tune a Frequency Board Tools Supplies you ll need e Frequency generator e Oscilloscope e Frequency counter e Small screwdriver preferably non metallic contact with a metal screwdriver seems to affect the readings keep this in mind while tuning e BNC patch cords oscilloscope probe etc e TNC male to BNC female adaptor connector e Resistor Attenuator test fixture 200 Ohm Signal Generator Input Output To SIDMON de Figure 9 Test Fixture left Schematic right the homemade attenuator circuit Step 1 Plug the FREQBOARD in the SIDMON and turn on the power Step 2 Set the frequency generator output to the smal
16. n finalize the pots Rioo and R200 by painting them with some fingernail polish Of course if the burn in process reveals a problem e g no sunrise sunset effect then repeat tuning procedure One caveat to be aware of sometimes the VLF stations go down for maintenance it might not be the receiver s fault 10 Post amp Circuit FREQ OUT gt Ee S v M H D 1uF C13 TO Amplitude Modulation Detection Circuit Caa Connections 1l FILTER nu POST AMP GAIN SWITCH Figure 11 Post Gain Amp The post gain amplifier takes the Frequency Out signal now separated from the broadband signal and this stage amplifies it The stage was included as a contingency because we were not sure if we needed another gain boost so this was to deal with unknown and variable conditions of a weak signal or poor antenna design We decided to make this a selector switch instead of adding another potentiometers to avoid confusion So far all monitors are using x1 with perhaps a few exceptions I have found the x5 and x10 settings are good to boost the gain enough to make the input signal audible for antenna orientation It is important to change this setting back to x1 for data logging A R 7 R 7 A 1OOKQ R where R is one of Rya Ris or Rig Switch Setting Resistor Value Actual Gain A Label on an chassis XI R4 499KO 2 004 xs 00K 5 000 17KO 21 277 The gain slide switch is a DP3T labeled on the chassis x1 x5 an
17. o achieve the peak signal response A peak response is the highest possible response of the filter as seen on the oscilloscope Watch the amplitude on the scope while turning the pot in either a clockwise or counter clockwise direction one of these directions will cause the signal amplitude to rise At some point the amplitude crosses it maximum and begins to fall Simply reverse the direction of the pot and the signal will again rise back up Find the setting on the pot that gives the peak response to the input frequency Step 8 Repeat step 7 for test point Freq B and adjust pot R200 It is normal to adjust the volts division several times during this operation as the gain will be around 4x per stage If you hear a clicking sound coming from the pot while turning then you have reached the end of travel of the pot try reversing directions If you traveled to either limit of the pot and still did not find the peak response then the frequency you are attempting to tune is not possible with the current resistor values on the FREQBORD Step 9 The SIDMON is now ready to test or burn in we recommend a minimum of 24 hours to verify that the signal is being received and to discover any other electronic failures such as caps plugged in backwards etc To burn in the SIDMON follow the setup procedure in the User s Manual i e adjust the RF gain and pointing the antenna towards the transmitter etc Step 10 If the burn in is successful the
18. rall the current draw on the power supply is small in the 100 200 milliamps range It was necessary to design the power supply with lots of filtering in order to provide clean DC power to all of the RF filters and amplification stages Preamp Circuit Antenna Input i IE36 2 TLE2042 CP R3 7Ool Figure 5 Preamp Note this circuit does not include any lightning suppressors it is the responsibility of the user to install them Another protection mechanism suggested by an engineer but after the PC boards were made was a signal limiter clamp made from two signal diodes 1N914 s back to back across the input of the first stage op amp As of the writing of this manual we have not seen any problems with over voltage and not added these components to the boards however it is worth mentioning for consideration The antenna input is inputted through a TNC connector Capacitor Cg isolates DC voltage on the input as well as performing a high pass filter RC function consisting of Cg 0 1 uF and R4 2 2K 2 is a high pass filter about 723 Hz to help reject 50 60 Hz power line hum fo 1 QxRC 1 Qu x 22KO x 0 1pF 1 Qn x 22x10 x 0 1x10 fo 723 Hz The R resistor could also serve as an AC impedance match to the antenna however this value cannot be optimized due to the variability of antenna design and consequences to the f frequency response of the high pass filter thus it 1s better for the user to
19. s Test point Signal Detect 1s the full wave rectified signal that 1s sent to the audio buffer circuit See Audio Output for more information Test point Signal Strength 1s the integrated signal to produce the signal strength this is a DC level The RC circuit R33 and C21 has an RC time constant is approximately between 5 and 9 seconds T RC 20KQ x 470 uF 20x10 x 470x10 T 2 9 4 Seconds This is approximate because capacitors have lower precision tolerances and we added a discharge resistor Roo to provide a small load to discharge the capacitor C21 in order to make the circuit respond to a lowering level faster than allowing its internal resistance to discharge the capacitor The design of this filter was chosen carefully to reject short lived signal bursts such as lightning but allow longer persistent signal strength changes such as those caused by solar flares to affect the overall signal strength characteristics Without this filter in place the resultant graph was too noisy to reliably detect solar flares especially smaller class C flares Engineers would often ask me why not filter in software and the answer is that we only sample once every 5 seconds thus we would need to take more sample and run some sort of median or averaging algorithm to filter out the noise This eliminates post processing and allows direct viewing of the data However engineers might be interested in experimenting with the RC valu
20. tive 5 volt supplies The TNC input feeds the broadband signal in from the antenna into the OQ Preamp Stage with the RF gain control The signal is then routed into the amp Frequency Board Filter Stage called FREQBOARD This section extracts the desired VLF transmitter station frequency as Amplitude Modulation AM from the broadband signal The AM signal leaves the FREQBOARD and routed to the Post Amp Stage for a user selectable signal boost the post amp switch labeled x1 x5 and x10 The signal is routed to the Signal Detect Stage that performs a full wave rectification of the signal making the waveform all positive 1 e the absolute value of all signal components The detected signal is then routed to the Audio Output Stage where the line level audio signal is sent out the 1 8 audio output jack and monitored through power speakers Also the detected signal from is routed into the Signal Strength Stage An integrator Resistor Capacitor circuit converts the detected AM signal into an average DC level indicating overall signal strength The DC level analog output exits the SID Monitor via the 2 position Phoenix connector that is connected to the DATAQ module ADC that converts the analog level to digital values that are then transmitted via RS 232 to the computer and recorded by the software S VAC Input 1 Power Supply pzzsgN 7 14001 La R sasttahl Fuss 250 mA gru esos 51 TIF ELE Pih Y uc SWITCH P L
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