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1. DO LN TSCOPY 1L 18 copy timestamp along with the data DQ LN MAPPED 1L 15 For WRRD DMAP devices DQ LN STREAMING 1L 14 For RDFIFO devices stream th FIFO data automatically For WRFIFO do NOT send reply to WRFIFO unless needed DQ LN RECYCLE 1L 13 if there is no data taken available overwrite reuse data DQ LN GETRAW 1L 12 force module to return raw unconverted data DO LN TMREN 1L 11 enable module periodic timer DQ LN IRQEN 1L lt lt 10 enable module irqs DO LN PTRIGEDGE1 1L lt lt 9 stop trigger edge MSB DO LN PTRIGEDGEO 1L 8 stop trigger edg 00 software O01 rising 02 falling DQ LN STRIGEDGE1 1L lt lt 7 start trigger edge MSB DQ LN STRIGEDGEO 1L 6 start trigger edg 00 software 01 rising 02 falling DQ LN CVCKSRCI 1L 5 CN clock source MSB DQ LN CVCKSRCO 1L 4 CV clock source 01 SW 10 HW 11 EXT DQ LN CLCKSRCI 1L 3 CL clock source MSB DQ LN CLCKSRCO 1L 2 CL clock source 01 SW 10 HW 11 EXT DO LN ACTIVE 1L 1 STS LED status DQ LN ENABLED 1L 0 enable operations DQ LN ACTIVE is needed to switch on the STS LED on CPU module DO LN ENABLE enables all operations within the module DQ LN CLCKSRCO selects the internal channel list clock CL so
2. The address space 192 168 1 0 192 168 1 255 is used The IP address block 192 168 2 1 to 192 168 2 255 is available and is in the private range Let us choose 192 168 100 1 192 168 100 255 for the PC s secondary NIC NX Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Qy ee Industries Inc Date October 2010 File DNR 12 6 1G_Chap4 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 4 41 Installation and Configuration IP 192 168 100 3 Netmask 255 255 255 0 Gateway 192 168 100 3 Using Network Connections in the control panel Start gt gt Programs gt gt Control Panel gt gt Network Connections Right click the adapter to bring up the Properties window Open the TCP IP properties of the adapter and edit to your liking Refer to the Appendix at the end of this document Configuring a Second Ethernet Card for step by step instructions on how to do this Confirm the network configuration at the Command Prompt Start gt gt Programs gt gt Accessories gt gt Command Prompt C gt ipconfig Ethernet adapter NIC1 Local Area Connection Connection specific DNS Suffix LE AddresSSa c e 2 2 2 o oe 2 192 168 1210 Subnet Mask a s so a s e 255 255 255 0 Default Gateway 192 168 1 1 Ethernet adapter NIC2 Local Area Connection 2 Connection specific DNS Suffix IPVAGQVESS x 3 ox
3. 192 168 1 1 Linux users can use the more verbose ifconfig command instead In the following example the subnet range 192 168 1 0 192 168 1 255 is used by NIC1 IP Addressing The range of usable addresses is defined by the IP address and subnet maskAn IP address is a number that lies within the range of 0 0 0 0 and 255 255 255 255 Here the IP address is 192 168 1 10 The subnet mask indicates where an address stops For example a subnet mask 255 255 255 240 has 15 usable addresses 255 255 255 255 255 2554 255 240 Here the subnet is 255 255 255 0 or 255 addresses The subnet limits from anything anything anything O up to the max The usable range for 192 168 1 10 255 255 255 0 is 192 168 1 1 to 192 168 1 254 192 168 1 0 and 192 168 1 255 are reserved for Router and Broadcast messages The usable range for 192 168 0 4 255 255 0 0 is 192 168 0 1 to 192 168 255 255 The usable range for 192 168 100 2 255 255 255 0 is 192 168 100 1 to 192 168 100 254 Not every IP address from 0 0 0 0 to 255 255 255 255 is usable however these three ranges of IP addresses are guaranteed open for private use 10 0 0 0 10 255 255 255 172 T16 0 0 172 31 255 255 192 168 0 0 192 168 255 255 You need not use th ntire set STEP 2 Install the secondary NIC card STEP 3 Setup a network that does not overlap the existing one
4. DO LNCL TSRQ insert a timestamp into the output data DQ LNCL SLOW double the settling time for this channel DQ LNCL DIFF acquire the channel in differential mode rather than single ended or pseudo differential The channel number occupies the first eight bits of the channel list entry The maximum number of channels on one device cannot be larger than 256 Tel 508 921 4600 www ueidaq com Vers 1 5 Date October 2010 File DNR 12 6 1G Chap7 fm 7 4 2 Configuration Flags Standard part Please notice that for n DNR X 1G RACKtangle and HalfRACK Systems Chapter 7 88 Programming Module specific Functions Bits 11 8 contain gain information The number of gains and the gain are specific for every module type See powerdna h for module specific gain macros Configuration flags occupy a 32 bit configuration word The upper part of the configuration word contains module specific flags lower 16 bits of module configuration word nultiple subsystem modules you should pass multiple configuration uint32s in config io define define define define define defin defin defin defin defin defin defin defin 0 Oo defin defin 0 o defin defin 0 0 NX Copyright 2010 United Electronic Industries Inc
5. Figure 7 2 Core Module Interconnection Diagram e DIOO CLKIN pin 3 on the FJIO1 DB 37 connector By default this pin is an input connected to the ISO EXTO synchronization line and through this line to the NIS logic Tel 508 921 4600 Date October 2010 www ueidaq com Vers 1 5 File DNR 12 6 1G Chap7 fm DQ LN CLCKS DO LN STR DO LN PTR G H P G m iDGE DNR X 1G RACKtangle and HalfRACK Systems Chapter 7 Programming Module specific Functions DIO1 TRIGIN pin 4 on the FJIO1 DB 37 connector By default this pin is an input connected to the ISO_EXT1 synchronization line and through this line to the NIS logic DIO2 CLKOUT pin 22 on the FJIO1 DB 37 connector By default this pin is an output connected to the ISO INTO line from the NIS logic The PowerDNA API exposes six specially designated functions to control these lines as follows NOTE DqAdvSetClockSource This function selects external clock source for CL or CV clock Clock can be selected from internal sources EXTx lines signals from the isolated side and SYNCx interface signals inputs DgAdvSetTriggerSource This function selects external clock source for start and stop trigger Clock can be selected from internal sources EXTx lines signals from the isolated side and SYNCx interface signals inputs DqAdvAssignIsoDio This function selects direction and signal assignment for ex
6. Cal Date Aug 17 2004 v Enabled Input Range 15 15 Volts 8 Name Value Aln Aln1 Aln2 Aln3 Aln4 Aln5 Aln amp Aln AIn8 Alng Anio Aln11 Aln12 Aln13 Aln14 Aln15 Aln16 Figure 4 8 Typical Screen for Analog Input Board The screenshot above is from the PowerDNA Explorer Demo The demo is just a simulator for users without hardware or for new users who want to explore the PowerDNA Explorer program without reading writing to real hardware Run this program and hover your mouse over the buttons to read the tool tips and learn through interacting with the program Some quick notes V Tousethe I O board the Enabled check box should be set V To read froma board click the second to last button Read Input Data V To write to the board change the value and click the third or fourth button with the red arrow on top of the cube Store Configuration The icon with the blue arrow above it restores the configuration V To change the IP change the number deselect the field and Store Configuration Take care not to set the IP Address to outside of the network s configuration subnet or to an IP address that is currently in use as the system will then become unreachable See Chapter 3 PowerDNA Explorer for additional information and instruction Tel 508 921 4600 www ueidaq com Vers 1 5 Da
7. 00 00 0c cc tenes 20 2 9 DC Power Thresholds ocos ccsereris ecitar rietta eee 20 Chapter 3 The DNR 6 1G HalfRACK System sees nnn 21 3 1 System OVeIVIGW osue pue UNE PAGE RUPES ABRE eR xa e RON REL A etin ARR a 21 3 2 Specifications usd xy x GR RARE XV RAE RR RU RU Rte da 23 3 3 Key Features coule does duae bid Isa bia vee abe eddeddu Ed EA 24 3 4 DNR 6 1G HalfRACK System Enclosure llis 25 3 4 1 Cooling Alr Flows cis e464 re ee AA E RIAAN Gad RR Reit 26 3 4 2 DNR 6 Power CPU NIC and I O Modules 002 000 ee eae 27 3 5 DNR POWER DC Module 0 000 cece eee 30 3 6 DNR CPU NIC Module 0 0 0 eee 30 3 7 DNR IO Modules 0 2 00 0c bce te tn rh na 30 3 8 DC Power Thresholds 0 0 2 2 0 0 c ete nn 31 Chapter 4 Installation and Configuration 0 0 0 cee eee 32 4 1 Initial Installation Guide llle 32 4 1 1 Inspect Package ides RR RR pe Ee ERR REIdG Een 32 4 1 2 Install Software 2 0 0 20 ess 32 4 2 Initial Boot pz 2 623404 EIER Due ER doped EAR RS e p udi 34 4 2 1 IP Addresses on the IOM 0 0 tee 36 4 3 Improving Network Performance 2 000 e eect eee 38 4 4 2 Troubleshooting ss 24 beet hae Aa babar debet Deed bad Deed 43 4 5 PowerDNA Explorer Quick Start 22i 43 4 5 1 Updating Firmware isses RR E a a 46 4 5 2 Firmware Update Instructions 2 0000 cece eee eee 47 4 6 Mounting and Field Connections
8. Chapter 4 35 Installation and Configuration STEP 5 As soon as the system powers up it runs through self diagnostic mode and generates output on the terminal program A typical readout might be as shown in Figure 4 1 Multi threaded TTY ede x File TTY Transfer Help Parity Data Bits Stop Bits Local Echo NoReading zl e x None x e fi IV Display Eros No Wiiting CR gt CRAFF NoEvents Font Comm E vents Flow Control Timeouts Disconnect IZ Autowrap In eat protect on 24 protect on 249 Flash protect ON from BxFFFABBBB to xFFFA3ZFFF protect on 253 flash protect ON from BxFFFRA8BBB to xFFFA3FFF protect on 253 Flash afterinit test done 32 MB In serial Out serial Err serial Net Freescale TSEC PHY is Realtek RTL8212 icc 12 gt Gig E controller found Freescale TSEC Hit any key to stop autoboot Starting application at xFF8 6106 Welcome to PowerDNAt PowerDNA lt C gt UEI 2001 2087 Running PowerDNA Firmware on MPC8347 Built on 15 58 88 Mar 18 2008 Initialize uC OS II Real Time Kernel v 288 5 starting filesystem 08 init cs init devices CM 4 PPC834 7 detected 6 device detected fiddress Irq Model Option Phy Virt S N Pri DeuN AxA BB a 42 1 phys 4612345 16 GxAGB5a066 A 42 1 phys 0002345 20 1 GxAGG6 a a8 42 1 phys 6420004 38 2 GxAGGBEG66 A 42 1 phus 6612345 46 3 GxAGBCHG8G A 26 1 phys 9037428 58
9. Copyright 2010 United Electronic Industries Inc DNR X 1G RACKtangle and HalfRACK Systems Chapter 3 22 The DNR 6 1G HalfRACK System e DNR GPS e Any future additions to the PowerDNR I O module product line Note Refer to www ueidaq com for a description of each I O module All standard PowerDNA accessories are also available for use in a DNR 6 1G HalfRACK system NOTE UEIPAC UEISIM and UEIModbus deployments are now available for use with DNR 6 HalfRACK systems with the following model names e UEIPAC UEIPAC 600R e UEISIM UEISIM 600R e UEIModbus UEIModbus 600R Tel 508 921 4600 www ueidaq com Vers 1 5 Date October 2010 File DNR 12 6 1G_Chap3 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 3 23 The DNR 6 1G HalfRACK System 3 2 Specifi The technical specifications of the DNR 6 1G HalfRACK system are listed cations below Technical Specifications Standard Interfaces To Host Computer Two independent 1000Base T Gigabit Ethernet ports 100 10Base T compatible Distance from host 100 meters max Other Interfaces One USB 2 0 controller port One USB 2 0 slave port Config General RS 232 9 pin D Sync Custom cable to sync multiple racks DNR 6 1G 6 slots Ethernet data 20 megabytes per second transfer rate Analog data up to 6 megasample per sec 16 bit samples transfer rate DMAP I O mode update 1000 I O channels analog and or digital in less than 1 millisecond
10. DO LNCL SSO specifies the subsystem to which the channel belongs Do not use for single subsystem modules DO LNCL IRQ causes the module to fire an IRQ upon processing this entry Required for special real time cases DO LNCL NOWAIT causes the module to temporarily forget about the CV clock and start execution of the next channel list entry right after the current one is completed DQ LNCL SKIP prohibits storing the data specified in this channel list entry into the data output FIFO or prohibits advancing the data input FIFO pointer This flag is used to increase the settling time DQ LNCL CLK causes the channel list machine to wait for the next channel list clock Normally the state machine executes the whole channel list on a single CL clock DQ LNCL CTR perform a pulse on the selected line This flag is used for synchronization purposes DQ LNCL WRITE write the output to the double register but do not propagate the physical signal to the output DQ LNCL UPDALL clock all output channel double registers to update them simultaneously This entry is usually used with the DO LNCL WRITE entry when you need to write data to the output channels sequentially and update them at the same time In this situation you should use the DQ LNCL WRITE flag for every entry To update all outputs with previously written values combine the DO LNCL WRITE flag with the DO LNCL UPDALL flag
11. Firmware Update over LAN To upload firmware with PowerDNA Explorer over LAN do the following Turn on power on the DNR POWER DC module Connect the DNR CPU 1000 module to its network Start PowerDNA Explorer on the Microsoft Windows desktop from Start gt gt Programs gt gt UEI gt gt PowerDNA gt gt PowerDNA Explorer Choose Network gt gt Scan Network Select the DNR X 1G system to be updated Select Network gt gt Update Firmware from the menu PowerDNA Explorer File Network View Help 3 Address Ranges et Scan Network Ctil N 9 18 Reload Config Ctrl R Store Config In P lOM 10238 SCOPI Tt 1008 DNA CM 100 Base T Read Input Data fer 342 10238 xiii 23 F8 90 7B 19 40 Update Fi e Ctil F M aMI1o2186 100 2 f Mode Configuration Figure 4 10 Update Firmware Menu Item STEP 7 Click on Yes when you see the prompt Are you sure you want to update firmware STEP 8 Double click on the romimage X X X mot where X X X is the version file FAS Copyright 2010 United Electronic Industries Inc vy Tel 508 921 4600 www ueidaq com Vers 1 5 Date October 2010 File DNR 12 6 1G Chap4 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 4 48 Installation and Configuration STEP 9 Enter the password to continue More information about passwords can be found in the Interfacing to the DNR CPU 1000 Module Using a Serial Interfa
12. NX Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Qy ee Industries Inc Date October 2010 File DNR 12 6 1G_Chap2 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 2 8 The DNR 12 1G RACKtangle System e Four 8 volt cooling fans mounted on the rear of the enclosure NOTE Note that the rightmost module Module 11 is 2 slots wide to accommodate future designs and or custom modules Also note that the DNR 12 enclosure has reversible mounting flanges designed for rack or surface mounting Rubber feet are supplied for desktop or tabletop mounting The enclosure is a rigid mechanical structure with complete EMI shielding Unused slots are filled with blank brackets and filler panels The DC DC power module provides output voltages of 24 3 3 2 5 1 5 and 1 2 VDC for the logic CPU and 8 VDC to power the four cooling fans PAS Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 e V Bectronic Industries Inc Date October 2010 File DNR 12 6 1G_Chap2 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 2 9 The DNR 12 1G RACKtangle System a ee Grounding Fingers A 2 MS Figure 2 5 Optional DNR IO Filler Panel for empty slots i j 5 o L I o o Lift Lever ME REN to eject o board from D o backplane amp connector E aa me om Press lever c down to insert b
13. STEP 4 STEP 5 STEP 1 STEP 2 STEP 3 STEP 4 Copyright 2010 United Electronic Industries Inc DNR X 1G RACKtangle and HalfRACK Systems 6Select Use the following DNS server addresses and Make sure the Preferred DNS server box and the Alternate DNS server boxes are blank Obtain DNS server address automatica Use the following DNS server addresses Preferred DNS server cs 2 x 7 Altemate DNS server 5 x Advanced Cancel Click OK click OK in the TCP IP Properties window click OK in the Local Area Connection window and click Close in the Local Area Status window Close the Network and Dial up Connections window Set Up Your Ethernet Card NIC If you installed your Ethernet interface before or at the same time as you installed Windows NT then the system should have automatically detected it and you should proceed to the next section Install and Configure TCP IP Optionally you may follow steps 1 3 below to confirm that your interface is recognized If you obtained an Ethernet interface after Windows NT was already on your computer do the following From the Start menu select Settings and then select Control Panel Double click on the Network icon Click on the tab labeled Adapters You should then see an entry for your Ethernet card If you do not see one continue to step 4 to install it Otherwise click OK and skip ahead to Install and Configure TCP IP Click Add
14. b d Tel 508 921 4600 www ueidaq com Vers 1 5 Date October 2010 File DNR 12 6 1G Chap7 fm 7 4 4 PowerDNA Module Signaling DIO 0 pin 3 CLKIN DIO 1 pin 4 TRIGIN aMMa DIO 2 pin 22 OKT NX Copyright 2010 United Electronic Industries Inc bd DNR X 1G RACKtangle and HalfRACK Systems Chapter 7 91 Programming Module specific Functions CNAMES xxx contains channel names The length of the channel names depends on the module type Only 512 bytes are allocated for channel names Thus Al 205 module four channels can have channel names as long as 32 characters while DIO 403 channel names 48 channels cannot be longer then 10 characters There is a set of functions written to read write and store these parameters into E PROM Functions DqCmdGet Parameters DqCmdSetParameters access modal parameters while DqCmdSaveParameters stores parameters into E PROM clocking lines This section defines procedures for setting up triggering synchronization and Most PowerDNA modules have the following interconnection diagram IS Logic DgAdvAssignlsoDio selects direction level and connection between signals DqAdvSetClockSource DqAdvSet TriggerSource DgAdvAssignlsoSync DqAdvAssignSynox TMR1 CL IN CV IN CL OUT CV OUT Start Trig Stop trig Time Stamp
15. 1 5 File DNR 12 6 1G_Chap2 fm Zs Copyright 2010 www ueidaq com United Electronic Industries Inc vy DNR X 1G RACKtangle and HalfRACK Systems Chapter 2 The DNR 12 1G RACKtangle System 2 3 Key Features The following table is a list of key features of a DNR 12 1G PowerDNR system Copyright 2010 United Electronic Industries Inc Easy to Configure and Deploy Over 25 different 1 O boards available Over 5 quadrillion possible configurations Built in signal conditioning Gigabit Ethernet based Bracket kit for mounting to wall or in 19 racks Industrial quality rubber feet for solid table top mounting Passive backplane ensures extremely low MTTR Standard Off the shelf products and delivery True Real time Performance 1 msec updates guaranteed with 1000 O Upto 6 million samples per second Use QNX RTX RT Linux RTAI Linux LabVIEW RT Flexible Connectivity e 1000Base T with Cat 5 cable e 10 100Base FX Fiber interface available see DNR FPPC family Supports WIFI GSM Cell networks e Built in USB 2 0 slave and controller ports Compact Size 51215 Kk 81 22 Ti 300 analog inputs per rack 384 analog outputs per rack 576 digital 1 O bits per rack 96 counter quadrature channels per rack 144 ARINC 429 channels per rack 48 RS 232 422 485 ports per rack Low Power Less than 50 watts per typical rack including 1 O AC 9 36 VDC or battery powered Stand alone a
16. 4 2 l nitialBoot up Perform an initial boot in preparation for configuring the network using the following procedure STEP 1 Familiarize yourself with your DNR system front panel layout Note that all con nections are made on the front of the unit no rear access is required in a rack mounted configuration STEP 2 Attach the serial cable to the host PC and to the RS 232 port on the front panel of the DNR CPU 1000 Module a Runaterminal emulation program MTTTY on the PC Any terminal emulation program except HyperTerminal may be used MTTTY Minicom TeraTerm etc b Verify that COM parameters are set at 57600 baud 8 bits no parity 1 stop bit c Click Connect in MTTTY or use the commands on one of the other terminal emulation programs to establish communication with the DNR X 1G system STEP 3 Connect power to the system 9 36V DC by plugging the Molex type power connector from the power supply into the mating connector on the DNR POWER DC module The power source may be the bundled DNA PSU 24 100 100 watt powerbrick or a user supplied source Note that the DNA PSU 24 100 plugs into a 100 240V 47 63 Hz outlet and outputs up to 4 17A at 24 VDC STEP 4 Turn on the ON OFF power switch on the DNR POWER DC Power Module front panel NX Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Qy ee Industries Inc Date October 2010 File DNR 12 6 1G_Chap4 fm DNR X 1G RACKtangle and HalfRACK Systems
17. Aln11 0 0057 Aln12 0 0062 Aln13 0 0066 Aln14 0 0071 Aln15 0 0076 Aln16 0 008 Aln17 0 0085 AIn18 inansa Figure 5 12 Screen from Network gt gt Read Input Data At the screen shown above you can add edit channel names After editing names choose Network gt gt Store Config to save changes to the module This is true for all modules Also if you have changed a configuration value but have not chosen Network gt gt Store Config to save them previous values can be re read from the module using Network gt gt Reload Config Al 205 and Al 225 module screens are same as the Al 201 module but with different input ranges and number of channels In addition digital and analog output modules have settings specific to their module types We ll use the DIO 405 as an example to start with then show how the DI 401 DO 402 and DIO 403 are different NOTE Use Network gt gt Read Input Data to see immediate input values in Input tabs Use Network gt gt Store Config to save values to the module Tel 508 921 4600 Date October 2010 Vers 1 5 File DNR 12 6 1G_Chap5 fm www ueidaq com DNR X 1G RACKtangle and HalfRACK Systems Chapter 5 66 PowerDNA Explorer PowerDNA Explorer File Network View Help Os s Host PC 9 lom_20977 DIO 405 0 DIO 405 ng D In Out 12 input 12 output lines SN 0023192 Mfg Date Jan
18. October 2010 File DNR 12 6 1G_Chap7 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 7 83 Programming Module specific Functions Some commands such as mr mw set and store require entering a user password Once the password is entered these commands become enabled until firmware reset There are two levels of password protection available The first is user level and the second is super user level Super user level is currently used only for updating firmware over the Ethernet link DQ pswd user sets up a user level password First you ll be asked about your old password and then if it matches to enter the new password twice DQ pswd su sets up super user level password First you ll be asked about old super user password and then if it matches to enter the new super user password twice DNR 12 and DNR 6 systems come with the default password set to powerdna Some DaqBIOS commands require clearing up user or super user password Use DqCmdSetPassword before calling these functions The PowerDNA API Reference Manual notes which functions are password protected Another useful command is devtb1 This command displays all l O modules found and initialized by firmware along with assigned device numbers Use these device numbers in host software to address these devices Priority determines the order in which device drivers are located in the device stack A device with a lower priority number receives a
19. The module specific I O boards are functionally identical to the corresponding modules for the PowerDNA Cube The only differences between the two types relate to the mounting arrangements Note Top Rear Cover Not Shown Backplane Ce 3C Mounting Brackets 2 Reversible for T rack or surface Add rubber feet 4 mounting for tabletop mounting ad Fingers Ee Sa 9 Je eF A C Figure 2 4 Typical PowerDNR DNR 12 ENCL Enclosure Exploded View As shown in Figure 2 4 and Figure 2 9 the PowerDNR DNR 12 enclosure is designed to house the following items One isolated DNR POWER DC DC DC Power Module Power Monitor with status indicating LEDs a local on off switch and 4 pin Molex Power In connector One DNR CPU 1000 dual slot CPU NIC module with indicating LEDs two Ethernet connectors Main and Diagnostic Ports sync connector reset pushbutton SD card slot USB controller slave ports future use and a DB 9 connector for a serial port One DNR BUFFER Board for buffering address control clock lines for future use not currently addressable Up to 12 PowerDNR front pull out I O modules boards functionally identical to PowerDNA I O boards but designed for mounting in a DNR rack enclosure One DNR BP 12 Backplane with two temperature sensors e DNR IO FILLER blank filler panels for all unused slots
20. The system system automatically senses the slot location of each board If you want to enhance repair or otherwise modify a specific I O board however you must send the module back to the factory or to your local distributor This process requires that you request an RMA number from UEI before shipping To do so you must provide the following information 1 Model Number of the unit 2 Serial Number of the unit 3 Reason for return Calibrating the board s Defective board for repair Upgrade with additional board s UEI will process the request and issue an RMA along with an estimate of the work and associated costs required to handle your request 4 10 Configuring a The CPU Core Module has two Ethernet ports NIC1 and NIC2 Either port can NIC Port for be assigned as the Main Operation Port or as a Diagnostics Port Diagnostic The main and diagnostics ports are interchangeable The user application can Mode open both ports independently and use separate handles to access each of them A port becomes a diagnostics port and prevent changes in the state of the ongoing operation after it is locked in as a diagnostics port This allows great flexibility in IOM wiring if either port or its cabling fails you can use the other port as the main port If all layers are in configuration mode and the lock is not set the diagnostics port functions as an equivalent of the main port Any command that can be executed on the main por
21. The first address range is dedicated for devices located on the CS2 line and it accommodates sixteen modules with 64k memory map each The second address range is designated for fast devices located in the CS3 line and it accommodates fifteen devices with 16MB memory map each 7 2 Startup After reset the processor starts monitor execution from flash memory The Sequence monitor initializes the processor and the address map retrieves information from the parameter sector of the flash memory and tests system memory and other system resources If the fwgo parameter is set to autorun the monitor waits for three seconds for you to send Ctrl A which is transmitted over the serial interface If sent the monitor aborts loading firmware into memory and brings up the monitor command prompt to load new firmware for example Otherwise the monitor reads the firmware from the flash memory and stores it in RAM Then the monitor executes the firmware NX Copyright 2010 Tel 508 921 4600 www ueidag com Vers 1 5 Qy ee Industries Inc Date October 2010 File DNR 12 6 1G_Chap7 fm fwad fwgo fwsz fwcp fwst OxFFI 0x1 DNR X 1G RACKtangle and HalfRACK Systems Chapter 7 Programming Module specific Functions The following parameters are critical for firmware to be copied and started from the proper address E40000 0x100000 0x20000 0x20400 7 3 Setting Core Module Parameters NX Copyright 2010 United
22. VIn 7 8 8 8 7 5 8 5 Varies with layer type DCs that use input power 1 Turn on V The value of Vin at which the corresponding DC DCs are turned on 2 Turn off V The value of Vin at which the corresponding DC DCs are turned off NOTE ADNR 6 1GB CPU NIC core module consumes only 70mW when Vin is below 7V Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Q ape E e Date October 2010 File DNR 12 6 1G_Chap3 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 4 32 Installation and Configuration Chapter 4 Installation and Configuration Installation consists of e DNR 6 1G or DNR 12 1G hardware setup e PowerDNA PowerDNR software package installation e Configuration NOTE Throughout this chapter several figures include graphic representations of DNR 12 systems Each such figure could also be shown with a DNR 6 system instead of a DNR 12 unit 4 1 Initial This section describes the procedure recommended for performing an initial Installation hardware and software setup when you first receive a DNR X 1G system Guide 4 1 1 Inspect Inspect the contents of the shipping package With a standard DNR X 1G Package system you should find e A DNR 12 ENCL or DNR 6 ENCL enclosure preinstalled with a DNR CPU 1000 module DNR POWER DC module blank filler panels if specified plus your selection of I O Boards A DNR 12 system also includes a DNR BUFFER module not required with a DNR 6 e A DNA PSU 24 100 100 watt un
23. a lOM_19675 lOM_20977 0 AI 201 i 1 Al 201 i 2 Al 201 i 3 AI 201 Figure 5 9 Example of the Device Tree When an item is selected in the tree the settings panel changes to reflect the settings for that device The first time an item is selected the device is queried as though you had invoked the Read command On subsequent selections of the same item the last settings are re displayed Thus if you made changes but did not write them to the device the changes are remembered Invoking the Read command will re read the device and overwrite the current settings in the settings panel Devices whose settings have changed but have not been written are displayed in bold italics in the tree to provide a visual cue Changed devices that become missing on a subsequent invocation of Scan Network turn red in the tree Unchanged items that become missing are simply removed from the tree 5 2 7 Settings Panel The settings panel presents a set of controls that allow you to change the settings of the device currently selected in the device tree 5 2 7 1 IOM Settings The settings panel has the following controls when an IOM is selected in the tree PowerDNA Explorer i O x File Network View Help 5 6 6 Q9 m HostPC ET Name mmm aaan l E AUIE MMII MAC 00 0C 94 00 51 C1 IP 10 102 226 87 Mode Configuration Figure 5 10 Example of IOM Settings Panel for a DN
24. accuracy 0 25Hz update rate for All output voltages nput current for the 9 36VDC for the DNR Enclosure AII voltages from the NIC Module 24V 3 3V 2 5V Temperature of the DNR backplane 2 sensors Onboard FPGA logic chip is CYCLONE EP1C3 C6T 144 TI MSP4300 microcontroller used for logic reprogramming Input Output connector is a 128 pin component that provides 9 36VDC for all modules from an external power source Copyright 2010 United Electronic Industries Inc Tel 508 921 4600 www ueidaq com Vers 1 5 Date October 2010 File DNR 12 6 1G_Chap2 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 2 17 The DNR 12 1G RACKtangle System 8 Indicating LEDs Ejection Leven a On Off Switch T Connector Grounding M Fingers d hidden R Power lh SS Figure 2 13 DNR POWER DC Module PAS Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 e V Bectronic Industries Inc Date October 2010 File DNR 12 6 1G_Chap2 fm 9 36 VDC 80 W max DNR X 1G RACKtangle and HalfRACK Systems Chapter 2 The DNR 12 1G RACKtangle System A functional block diagram of the DNR POWER DC Module is shown in Figure 2 14 below Input Voltage Source Input Current Monitor 3 3V DC DC 2 5V LDO i 24V DC DC L 1 5V DC DC 8V FAN D
25. guaranteed CPU Freescale 8347 400 MHz 32 bit Memory 128 MB not including on board Flash Status LEDs Power supplies within spec One second system heart beat Attention Read Write Power Com munications Active Environmental Temp operating Tested to 40 C to 70 C Temp storage 40 C to 85 C Humidity 0 to 95 non condensing Vibration IEC 60068 2 64 10 500 Hz 3 g rms Broad band random IEC 60068 2 6 10 500 Hz 3 g Sinusoidal Shock IEC 60068 2 27 50 g 3 ms half sine 18 shocks at 6 orientations 50 g 11 ms half sine 18 shocks at 6 orientations MTBF 130 000 hours Physical Dimensions DNR 6 series 5 25 x 6 2 x 17 5 3U in a 19 rack Voltage 9 36 VDC AC adaptor included Fuse Internal 10 A Power Dissipation 13 W at 24 VDC not including I O boards Power Monitoring l O board power All internal power supplies monitored to 1 ac curacy All PS voltages may be read by host LED annunciators indicate out of range Input current Monitored by host LED indicates overcurrent Input voltage Monitored by host LED indicates out of range NX Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Qy ee Industries Inc Date October 2010 File DNR 12 6 1G_Chap3 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 3 24 The DNR 6 1G HalfRACK System 3 3 Key Features The following table is a list of key features of a DNR 6 1G HalfRACK sy
26. loads rom8347 mot loads stores firmware into the flash while downloading it PAS Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Qy ee Industries Inc Date October 2010 File DNR 12 6 1G_Chap4 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 4 49 Installation and Configuration STEP 5 Transfer the Motorola firmware file Use 7ransfer Send File and select Program Files UEI PowerDNA Firmware_PPC romimage_3_x_y mot A progress bar will appear in the lower left corner of MTTTY indicating progress STEP 6 Wait for the upload to complete it may take a few minutes STEP 7 After the process finishes enter the wjmp command The DNR CPU 1000 will then be updated and running the new firmware At this point only the PG light on the DNR CPU 1000 panel remains lit 4 6 Mounting and You can mount the DNR 12 1G on a flat horizontal surface such as a tabletop or Field floor a flat vertical surface such as a wall or in a standard 19 inch rack For Connections horizontal surface mounting use the rubber feet supplied with the standard enclosure or bolt the case directly to the surface For mounting on a vertical wall surface attach flanges to both ends of the enclosure with the flanges aligned flush with the rear of the enclosure then fasten the flanges to the surface with screws or bolts For mounting in a standard 19 inch rack attach flanges to both ends of the enclosure with the flanges aligned flush with
27. loss The above is a successful response A Request Timed Out message would indicate an error STEP 7 The system should now be configured as shown in Figure 4 6 NIC1 192 168 1 10 NIC2 192 168 100 3 Diagnostic Port Diagnostic Primary Port a Port P Figure 4 6 Typical Configuration for a Single DNR X 1G with a LAN Switch STEP 8 You may now use PowerDNA Explorer to access the system See Chapter 3 v Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 e i Date October 2010 File DNR 12 6 1G_Chap4 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 4 43 Installation and Configuration 4 4 2 Trouble The following checklist may assist you in troubleshooting a system shooting V ThePG Power Good LED is on the 9 36V DC power supply is plugged into the DNR POWER DC Power Module panel V The green lights on NIC ports are blinking the CAT5e cables are connected V Use the command prompt to ping system IP e g ping 192 168 100 2 a Disable temporarily the firewall on the secondary NIC b Check the secondary NIC s network settings c Check the system s network settings Use MTTTY and click Connect Press Enter to display the DQ gt or gt prompt No prompt indicates that you are not connected Verify that the serial cable is firmly connected to the RS 232 port Verify the settings 57600 baud no parity 8 data bit
28. 00 000 eee te tees 49 4 6 1 Physical Dimensions islseeeeeee nh 49 Z Copyright 2008 Tel 508 921 4600 www ueidaq com Vers 1 5 ww United Electronic Industries Inc Table of Contents Date October 2010 File DNR12 6 1G ManualTOC fm 4 7 WING 4 44 4 224 a ace dee eee seein te ead sian Eine d mak d obit au pre td 50 4 8 Peripheral Terminal Panel Wiring llli 51 4 9 Repairing and Upgrading Your DNR system 0 0000 cece eee 51 4 10 Configuring a NIC Port for Diagnostic Mode l i 51 Chapter 5 PowerDNA Explorer 2 000 ee 58 5 1 The Main Window 0 002 ra 58 5 2 Menu Bal 226 stair oU wade ae hen RR We UTOR INA Tec TE eR ond edd 58 5 2 1 MEME IP e a a a ae S aaa S A aa a AEGEE NEE A E E A 58 5 2 2 Network Menu 0 0 200 ns 59 5 2 3 View Menu 00 0000 rrr 61 5 2 4 Help Menlo Ee ORAT ore CRUS ao ER whe Ran 62 5 2 5 Rol e cT Um 62 5 2 6 Device Tree ou Uc EARA Lee ME b EA IER EE 62 5 2 7 Settings Panel 0 00 cee ee hh 63 5 2 8 Digital Input Output Module Settings 2 222200 cee eee 65 5 3 Analog Output Module Settings 2000 70 5 4 Analog Input Module Settings 0 2 0 0 0 cee ee eee 71 5 5 Counter Timer Module Settings 2000 e eee ete 72 Chapter 6 The DNR CPU 1000 Core Module ccc cece ees 75 6 1 Device Architecture of DNR Core Module 2220200 cece eee
29. 0x3012 Serial sets the DNR 12 6 serial number factory programmed do not change MAC sets the DNR 12 6 MAC Ethernet address factory programmed do not change fwct defines the behavior of the monitor upon boot up Valid values for autorun are zero stay in monitor after initial boot sequence or one copy firmware to SDRAM memory location and execute from there runtype for the DNR 12 6 should be 2 portnum and umports should be zero Srv sets the host IP address You have to set the host IP address only if raw Ethernet protocol is in use used in homogenous IOM networks only This parameter is ignored when the DNR 12 6 system is used over the UDP protocol or from the host IP specifies the IOM IP address This is the most important parameter the user must change to allow the DNR 12 6 system to be visible on the network The DNR 12 6 responds to every UDP packet containing a DaqBIOS prolog sent to this address Since the current release does not support DHCP the user should set up the IP address gateway specifies where the DNR 12 6 should send an IP packet if a requested IP packet exists outside of the DNR 1 62 network defined by the network mask Ask your system administrator if you use your DNR 12 6 on the office network netmask specifies what type of subnet the DNR 12 6 is connected to The factory sets netmask to Type C IP network 254 nodes maximum udp specifies what port
30. 0x4 Module5 7 0x5 Module6 8 OxD POWER 1GB OxE CPU NIC 9 N A BUFFER 10 0x6 Module 11 0x7 Module8 12 0x8 Module9 13 0x9 Module10 14 OxA Module11 15 OxB Module12 Copyright 2010 United Electronic Industries Inc Tel 508 921 4600 Date October 2010 www ueidaq com Vers 1 5 File DNR 12 6 1G_Chap2 fm 2 5 DNR POWER DC Module DNR X 1G RACKtangle and HalfRACK Systems Chapter 2 16 The DNR 12 1G RACKtangle System The DNR POWER DC Module is a dedicated DC DC source and control module available only for use with a PowerDNR rack enclosure It is always mounted in the leftmost slot of the DNR chassis and is recognized on the PowerDNR bus with an ID of 0x020 at address 0xA00C0000 The non isolated side NIS logic complies with full common logic interface CLI implementation The key features of the DNR POWER Module are Input power 9 36 VDC 80W maximum protected by resettable fuses and EMI chokes Power supply on off switch with guard Output power sources all with greater than 90 efficiency 24V 1A 24W 3 3V 5A 16 5W including the 2 5V derived voltage 2 5V 3A derived from 3 3V source 1 5V 5A 7 5W including the 1 2V derived voltage 8V 0 5A 4W for fans DC DC for 24V 3 3V and 1 5V are synchronized from the single spread spectrum clock source in the CPU NIC Module for lower EMI noise level Fan control Forced ON and status ON OFF Monitoring and LED indicators 1
31. 1 2 Diagnostic This port enables the user to monitor the health of the DNR system during Network operation using a separate diagnostic port This port may also be assigned as Interface Port the primary Ethernet port if NIC1 is not available for use NIC2 6 1 3 RS 232 Port This port provides a serial communication link between the DNR X 1G system and a standard RS 232 terminal 6 1 4 UBS 2 0 Dual The USB A and B ports are intended for future use and are not software Port supported at present Controller and Slave 6 1 5 32MB Flash The DNR X 1G system is provided with 32MB of flash memory Memory 6 1 6 128MB of The system is supplied with 128MB of SDRAM SDRAM 6 1 7 SYNC Port A high speed system to system synchronization connector permits triggers or clocks to be shared among multiple systems Two systems may be connected together directly and larger groups may use the SYNC interface to share timing signals among many racks and systems The trigger and clock inputs will accept signals from standard digital logic that is powered in the range of 3 3V to 5V The inputs also have internal pull up resistors to an internal 5V supply making the inputs also compatible with a low side drive open collector output The Sync and trigger outputs have 5V logic levels The sync connector s ground and 5V power connections are provided by its own isolated DC DC converter 6 1 8 SD Card A slot for inserting a user provided Secure Digital card is p
32. 21 2005 Cal Date Jan 21 2005 vj Enabled Reference 240 V 0 Level 72 V 1 Level 168 V Output Name Value Doutt2 0 DOutl 3 lo DOutl 4 0 DOutl 5 0 DOutl 6 3 DOutl 7 Doutt 8 DOutt 8 DOut20 0 DOut21 jo DOut22 o DOut23 0 Figure 5 13 Example DIO 405 Inputs Zs Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 e V Bectronic Industries Inc Date October 2010 File DNR 12 6 1G_Chap5 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 5 67 PowerDNA Explorer PowerDNA Explorer Iof x File Network View Help BOO m HostPC 9 0M 20977 Model DIO 405 SS DDIO 405 Info D In Out 12 input 12 output lines BL ee SN 0023192 Mfg Date Jan 21 2005 Cal Date Jan 21 2005 v Enabled Reference 240 V Level 72 v Level 168 V put Output Initialization Shutdown m EJ Ja eOooooooo Figure 5 14 Example DIO 405 Outputs Reference is a reference voltage 0 level 1 level are hysteresis values described fully in the DIO 401 2 5 manuals Input Output Initialization Shutdown tabs switch between settings for init and shutdown states as well as operation mode configuration and display of current data All tabs contain the following columns The unnamed first column contains the channels Name is a user defined string Value contains 0 or 1 It is a drop down menu for outp
33. 6 Password Dialog Box for Store Config and Store All Configs ssussss 61 5 7 Password Dialog Box for Update Firmware eesssssssssseee e 61 5 8 Example of a Wiring Diagram Display sse 62 5 9 Example of the Device Tree ssssssssssssssssssesseeeeee nennen nennen nnne 63 5 10 Example of IOM Settings Panel for a DNR 12 1G esseee 63 5 11 Example of I O Device Settings ssssseeene emen 64 5 12 Screen from Network gt gt Read Input Data 65 5 13 Example DIO 405 Inputs sssssssssssssseeeeeeeeernenenen nennen nnns 66 5 14 Example DIO 405 Outputs cece cece ecee cece cee eeeee aaa an ARa AEAN 67 5 15 Example of DIO 403 INputs 2 ccc cece eceeecceee cee ce eee ee eee ee cece acaaeaaeaeeeeeeeeeeeseeteeeeenieaaeees 68 5 16 Example of DIO 403 Outputs ssssssssssssseeeeeeeeeeee rennen enne nnne 68 5 17 Example of DIO 403 Configuration esssssene meme 69 5 18 Example DIO 403 In Outputs sssssssssssssssneeeeeemner nennen nennen 69 5 19 Example AO 302 Module sssssssssessseseeeeeenenee eene nnn enne 70 5 20 Example Al 201 Module reru a EN a ke ARE ERR E A RAE 71 5 21 Example CT 601 Module ssssssssssssssessese eene emere nennen nennen 72 5 22 Example Quadrature Controls ccccceeeeceeeececeeceeeeeeeeeeeeeececeaacaecaeeeeeeee
34. 76 6 1 1 Primary Network Interface MII Port NIC1 0 00000 eee eee 77 6 1 2 Diagnostic Network Interface Port NIC2 0 000 a ee eee 77 6 1 3 RS 232 POI duse gg OES pale CR CR gL EUR ink s 77 6 1 4 UBS 2 0 Dual Port Controller and Slave 0 0 00 77 6 1 5 32MB Flash Memory ks e ER baw ae XE RS ohare he X xa ack ete 77 6 1 6 128MB of SDRAM i coef deed riiai i aea de Made aA EA 77 6 1 7 SYNC POI cccucs hoagie ates Aaa aee tees dgaes EE Paw Son uU qe s 77 6 1 8 SD Card s as wh ae ved aw adda e hed alee eink betes A ee aa aaa 77 6 1 9 WEDS os icd ear EE eue d dx Hee hue PAAR xq raa 77 6 1 10 Watchdog Timer With Real time Clock Battery Backed TT 6 2 11 CPU NIC Pinouts lsssslsssssele e 78 Chapter 7 Programming Module specific Functions 00 eee eee eee 79 7 1 OVOIVIOW 2 aane ngia abate peda ee Rx eet Ade pea veleern d Te tale oes 79 7 2 Startup Sequence 0 0 0 ce eee 79 7 3 Setting Core Module Parameters llle 80 7 3 1 Setting Parameters Via Serial Interface 0 202 cease 83 7 3 2 Clock and Watchdog Access lisse ens 85 7 4 Common Module Layer Interface lille 86 7 4 1 ORCI 86 7 4 2 Configuration Flags lssesseeeeee n 88 7 4 3 EEPROM User Area Access 0000 00 cece eee less 89 7 4 4 PowerDNA Module Signaling llle 91 PR O Copyright 2008 Tel 508 921 4600 www ueidaq com Vers 1 5 mee Eectr
35. 95 98 Me was already on your computer then do the following STEP 1 From the Start menu select Settings and then select Control Panel STEP 2 Double click on the System icon then click on the tab labeled Device Manager NX Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Qy ee Industries Inc Date October 2010 File DNR 12 6 1G_Appx fm DNR X 1G RACKtangle and HalfRACK Systems 104 STEP 3 Double click on Network adapters to display a list of the network interfaces that are installed on your computer If you see two entries other than the Dial Up Adapter one is your second Ethernet card Skip ahead to Install TCP IP If you do not see your second Ethernet card continue to step 4 to install it System Properties i21 x General Device Manager Hardware Profiles Performance View devices by type C View devices by connection H CDROM H E Disk drives E al Display adapters Floppy disk controllers Hard disk controllers 4 483 Keyboard E Modem H Monitor H A Mouse EE FENetaork Adapters Bg AMD PCNET Family Ethernet Adapter PCI amp ISA Bg Dial Up Adapter STEP 4 If an entry for your second Ethernet card appears here you probably do not need to run any software included with your card but keep the software handy just in case you need it later to resolve a problem STEP 5 Note the name of your second Ethernet card STEP 6 Close the System Properties window the
36. Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Qy ee Industries Inc Date October 2010 File DNR 12 6 1G_Chap4 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 4 37 Installation and Configuration To change the IP using the terminal program enter the following commands DO gt set ip 192 168 0 65 Enter user password gt powerdna DO store DO reset Sets this system IP to 192 168 0 65 The default password is powerdna Saves the newly changed configuration Reboots the system for the new IP to take effect In this manner you can set any parameters listed with the show command Connect the DNR X 1G system to your switch with a CAT5e cable If you can establish communication with a DNR CPU 1000 but later want to modify the IP address you can also do so from within PowerDNA Explorer After the exploratory process go to the field where the application displays the IP address You then enter the new IP address and hit Return This action downloads the new IP address into the system s non volatile memory You might also need to change the gateway and network mask to match settings on your LAN v Copyright 2010 l Tel 508 921 4600 United Electronic Industries Inc Date October 2010 www ueidaq com Vers 1 5 File DNR 12 6 1G_Chap4 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 4 38 Installation and Configuration How to change the
37. HalfRACK Systems Chapter 5 72 PowerDNA Explorer Input Range shows the specified input range It cannot be changed and thus is informational only The Data table contains the values currently coming into the device The table is initially blank until you invoke Refresh Data unless auto refresh is activated in the preferences dialog The table has three columns The unnamed first column contains the channel names Name is a user defined string Value shows the current value 5 5 Counter We ll use the CT 601 as an example Timer Module Settings PowerDNA Explorer of x File Network View Help PONHES Host PC s 9 lom_20030 Model CT 601 lt 0 CT 601 Info SK 0021169 Mfg Date Jun 4 2004 Cal Date Jun 4 2004 vi Enabled Counter 1 mode Bin Counter w Stop Min Gate Pulse Width psec C Input Pre inversion Min Clock Pulse Width psec C Gate Pre inversion Prescaler Value 33 _ Output Post inversion Use External Clock Counter Value 1773034 Counter 2 mode Quadrature w Figure 5 21 Example CT 601 Module The CT 601 module has 8 counters Each counter can be set to one of four different modes Quadrature Bin Counter Pulse Width Modulation PWM or Pulse Period When you change the mode of a counter using the mode combo box the controls for that counter will change to those appropriate for the mode PAS Copyright 2010 Tel 508 921 4600 www ueidaq
38. Menu Address Ranges brings up the Address Ranges dialog allowing you to specify where to scan for devices Address Ranges x IP Addresses 192 168 100 2 192 168 100 10 6334 Figure 5 3 Address Ranges Dialog Box The Address Ranges dialog allows you to specify the IP addresses and UDP port to use to find devices You can specify individual addresses as well as address ranges The specified items appear in a list to which you can add or delete This list defaults to a single range item that specifies the range 192 168 100 2 192 168 100 10 Edit Address Range x To make a single address leave the to field blank Address 192 168 100 2 to 192 168 100 10 UDP Port 6334 on cuen Figure 5 4 Edit Address Ranges Dialog Box NX Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Qy ee Industries Inc Date October 2010 File DNR 12 6 1G_Chap5 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 5 60 PowerDNA Explorer Scan Network scans the network for devices and populates the device tree How much of the network is scanned depends on the settings in the Network Ranges dialog amp PowerDNA Explorer File Network View Help 5 6 65 99 T TEN ss System Windows XP 3 IOM 20977 IP 10 102 226 7 Figure 5 5 After a Network gt gt Scan Network If you choose Scan Network when the device tree is already populated any new devices discovered will be added to the tree An
39. OK Error Modules 1 6 24VDC OK Error Modules 7 12 3 3VDC OK Error Modules 7 12 Module Groups Figure 3 6 DC Power Module LEDs When Flashing Module Needs Attention Temp High OK User Controlled Off Read Write Activity Serial Comm Activity Serial Port 3 3VDC OK Error 24VDC OK Error Power Good Note On a UEIPAC CPU NIC module the LEDs are user programmable Ethernet Ports NIC1 Main NIC2 Secondary USB 2 0 Slave Port Type B Connector reserved for future use USB 2 0 Controller Port Type A Connector reserved for future use Figure 3 7 DNR CPU 1000 Module LEDs FAS Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 yee Date October 2010 File DNR 12 6 1G_Chap3 fm Ready Power ON Copyright 2010 United Electronic Industries Inc DNR X 1G RACKtangle and HalfRACK Systems Chapter 3 29 The DNR 6 1G HalfRACK System Status Figure 3 8 Typical I O Module LEDs Two sensors mounted on the backplane monitor internal temperatures continuously turning fans on if the internal temperature exceeds 45 C off if it falls below 45 C and shutting down power if a high limit is exceeded All UEI PowerDNA modules are available in both PowerDNA and Power DNR package designs A feature of the design is that the address of a module is determined by the position of the module within the enclosure nu
40. Ode xS wo a o9 a v 192 1068 100 3 subnet Mask s s e s ge 4 o 255 255 255 0 Default Gateway 192 168 100 3 STEP 4 Setup the DNR X 1G system to use the same subnet namely Cube IP 192 168 100 2 this is the factory default Gateway 192 168 100 3 Netmask 255 255 255 0 To do this from a serial terminal emulation program enter the following commands when you see the DQ command prompt DO set ip Sets this Cube s IP address to 192 168 100 2 192 168 100 2 Sets this Gateway to DQ set gateway 192 168 100 3 192 168 100 3 Sets the subnet mask to 255 255 255 0 DO set netmask 255 255 2550 Saves the newly changed configuration DQ store Reboots the system for the new IP to DO reset take effect STEP 5 Connect the DNR X 1G to your PC s second NIC using a CAT5 cable The green LEDs should light up STEP 6 Ping the system to make sure that it is alive NX Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Qy DU Bectronic Industries Inc Date October 2010 File DNR 12 6 1G_Chap4 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 4 42 Installation and Configuration C gt ping n 1 192 168 100 2 Pinging 192 168 100 2 with 32 bytes of data Reply from 192 168 100 2 bytes 32 time ims TTL 128 Ping statistics for 192 168 100 2 Packets Sent 1 Received 1 Lost 0 0
41. X 1G RACKtangle and HalfRACK Systems Chapter 1 1 Introduction Chapter 1 Introduction This document describes the features performance specifications and operating functions of the DNR 12 1G RACKtangle and the DNR 6 1G HalfRACK gata acquisition systems Both systems are identical except for the size of the enclosure and the number of IO modules Both are designed for use with an Ethernet Gigabit 1000 Base T communication network 1 4 Organization This DNR X 1G User Manual which describes both types of systems is of Manual organized as follows NX Copyright 2010 United Electronic Industries Inc b d Chapter 1 Introduction This chapter describes the organization of the document and the conventions used throughout the manual Chapter 2 DNR 12 1G RACKtangle System This chapter provides an overview of a DNR 12 1G system component modules features accessories and a list of all items you need for initial operation Chapter 3 DNR 6 1G HalfRACK System This chapter provides an overview of a DNR 6 1G system component modules features and accessories It is essentially the same as the DNR 12 1G system except for enclosure size and number and arrangement of modules Chapter 4 Installation and Configuration This chapter summarizes the recommended procedures for installing configuring starting up and troubleshooting a DNR X 1G system Chapter 5 PowerDNA Explorer for the DNR X 1G This chapter
42. X 1G RACKtangle and HalfRACK Systems Chapter 2 14 The DNR 12 1G RACKtangle System Ready Power ON Status Figure 2 12 Typical I O Module LEDs Two sensors mounted on the backplane over the Power Module and over the CPU board monitor internal temperatures continuously turning fans on if the internal temperature exceeds 45 C off if it falls below 45 C and shutting down power if a high limit is exceeded All UEI PowerDNA modules are available in both PowerDNA and Power DNR package designs A feature of the design is that the address of a module is determined by the position of the module within the enclosure numbered from left to right A typical module address is OxAO00nxxxx where A00 is the BASE address n is the module position number starting from O at the left xxxx is the address of the module With this addressing method the address of a given I O board module automatically changes if you move it from one position to another within the enclosure NX Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Qy ee Industries Inc Date October 2010 File DNR 12 6 1G_Chap2 fm The slots or module positions are numbered as follows DNR X 1G RACKtangle and HalfRACK Systems Chapter 2 15 The DNR 12 1G RACKtangle System Physical Position Position Module L R Number Description 1 OxC POWER DC 2 0x0 Module1 3 0x1 Module2 4 0x2 Module3 5 0x3 Module4 6
43. and follow the on screen instructions Select your Ethernet card from the list shown or if it is not included in the list click Have Disk and insert the diskette that came with the card Even if your card does appear in the list it s a good idea to use the diskette to make sure you have the latest drivers Restart your computer if Windows gives you the option to do so Wait for the system to restart before continuing with the next section B Install and Configure TCP IP From the Start menu select Settings and then Control Panel Double click on the Network icon then click the Protocols tab In the list of Network Protocols look for TCP IP Protocol If you don t see it click Add select TCP IP Protocol and then click OK Select TCP IP Protocol in the list of Network Protocols and then click Properties A Microsoft TCP IP Properties window will open i Tel 508 921 4600 www ueidaq com Vers 1 5 Date October 2010 File DNR 12 6 1G_Appx fm DNR X 1G RACKtangle and HalfRACK Systems Network 21x Identification Services Protocols Adapters Bindings Network Protocols Add Remove Properties Update STEP 5 Click on the IP Address tab if it is not already selected STEP 6 Make sure that the radio button next to Specify an IP address is selected STEP 7 Enter 192 168 100 1 for IP Address 255 255 255 0 for Subnet Mask and leave blank the Gateway Address in the Default Gateway box A Copy
44. cno Figure 5 8 Example of a Wiring Diagram Display 5 2 4 Help Menu About PowerDNA Explorer shows the About box which shows the program icon program name version number company name and copyright notice 5 2 5 Toolbar The toolbar contains the following buttons Scan Network Reload Config Store Config Store All Configs Read Input Data and Show Wiring Diagram They duplicate the functionality of the corresponding menu items as described above 5 2 6 Device Tree When the application is first launched the tree contains just a root item representing the host computer When you select Scan Network from the Network menu or the toolbar the device tree is populated with all central controllers IOMs and device boards accessible from the network as filtered through the Network Ranges dialog Central controllers if any appear as children of the Host PC item IOMs that are connected to the PC without use of a central controller also appear as direct children of the Host PC item NX Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Qy ee Industries Inc Date October 2010 File DNR 12 6 1G_Chap5 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 5 63 PowerDNA Explorer Each item has an icon indicating whether it is a central controller IOM or board The text label for each item is the device s model number name and serial number Boards are also labeled with their position number in parentheses
45. com Vers 1 5 b d Dnited Elecironic Industries Ino Date October 2010 File DNR 12 6 1G_Chap5 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 5 73 PowerDNA Explorer Counter 0 mode Quadrature Start Min Gate Pulse Width 0 psec Input Pre inversion Min Clock Pulse Width 0 psec Gate Pre inversion Output Post inversion Relative Position counts Figure 5 22 Example Quadrature Controls Counter 0 mode Bin Counter x Start Min Gate Pulse Width d usec Input Pre inversion Min Clock Pulse Width gf usec _ Gate Pre inversion Prescaler Value _33i _ Output Post inversion _ Use External Clock Counter Value Figure 5 23 Example Bin Counter Controls Counter 0 mode PWM x Start Duty Cycle 50 Output Post inversion Output Frequency 1000 Hz Actual Freq 1000 Hz Example Pulse Width Modulation PWM controls Figure 5 24 Example Pulse Width Modulation PWM Controls Counter 0 mode Pulse Period x Start Min Gate Pulse Width 0 psec _ Input Pre inversion Min Clock Pulse Width 0 psec Gate Pre inversion Period Counter 0 _ Output Post inversion Positive Count Period Frequency Hz Negative Count Period Figure 5 25 Example Pulse Period Controls After setting the configuration for a counter you can choose Network gt Store Config to store the settings on the device Clicking the Start butt
46. for portability Unused slots should be filled with blank filler panels The DC DC power module provides output voltages of 24 3 3 2 5 1 5 and 1 2 VDC for the logic CPU and 8 VDC to power the three cooling fans 3 4 4 Cooling Air As shown in Figure 3 4 cooling is drawn into the rear of the enclosure routed Flow forward over the electronic circuit boards up to the top of the enclosure and then out the top rear of the enclosure The system is designed to maintain positive pressure cooling within the enclosure at all times p q O L N L T om Figure 3 4 DNR 6 Air Flow FAS Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 bd United Electronic Industries Inc Date October 2010 File DNR 12 6 1G Chap3 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 3 The DNR 6 1G HalfRACK System 3 4 2 DNR 6 Power This section describes basic modules included in every DNR 6 1G system the CPU NIC and CPU NIC module the DC DC power module and I O modules Note that I O Modules modules used in both DNR 6 and DNR 12 systems are identical The DNR 6 enclosure however only accepts six I O modules IempO Sensor on backplane Tem
47. in Figure 4 14 11 31 in 3 50 5 23 in 5 50 in 10 50 in Note For wall mounting align flanges flush with rear of enclosure For rack mounting refer to UEI for more information about spacer panels flange brackets and other accessories that may be required Figure 4 14 Physical Dimensions of DNR 6 ENCL Enclosure 4 7 Wiring 1000Base T Wiring Configurations A typical wiring configuration for a 1000Base T network is shown in the following figure Straight through To diagnostic ports via LAN switch TT TY 13195 YYYT1 Figure 4 15 System Configuration with LAN Switch NX Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 We DU Bectronic Industries Inc Date October 2010 File DNR 12 6 1G_Chap4 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 4 51 Installation and Configuration 4 8 Peripheral Refer to the applicable I O board manuals for proper wiring to boards p Terminal Panel Wiring 4 9 Repairing DNR X 1G systems come from the factory fully configured and calibrated n Individual modules are designed for field replacement and are not suited for field and Upgrading repairs Should you encounter a problem with a DNR system you can quickly Your DNR remove and replace individual boards or other system modules in the field You can also rearrange the locations of boards within the enclosure at any time
48. mode DO LN RECYCLE this flag affects output operation If this flag is set and module does not receive output data it will recycle old data until new data is available otherwise the module will stop at the last value output DQ LN GETRAW tells the module to return uncalibrated unconverted data This flag makes sense only for modules with software calibration Al 225 for example Moving calibration and conversion of data to host unloads the IOM processor DQ LN TMREN use a real time timer to retrieve data from the PowerDNA cube When this mode is selected the firmware programs the module to store one channel list worth of data in the buffer On a timer tick the firmware transfers this data from the module output buffer to the packet This function is used when the hardware allows only a selected set of update rates but you need something in between For example Al 225 can convert data with fixed frequency equal 6 875Hz 2 where n 0 9 To receive an exactly 500Hz data stream from this module specify that this module be updated upon a timer tick DQ LN IRQEN use interrupts to retrieve data from the module output buffer via packets This is preferable mode of operation 7 4 5 EEPROM User Every I O module has an E2PROM chip that contains 2048 bytes of module Area Access Specific information Model and option numbers identify every module The model number is hard coded inside module log
49. module PowerDNA Explorer File Network View Help DELE EA Host PC 9 lom_19675 4 Model 40 302 Taaa VTS Io ere s 0 Al 201 Info A Out 8 channel se Le LC ICI SS C A 2001 sw 0021031 E lt 21A0 302 EL UU I s e IOM 20977 d Mfg Date Dec 1 2003 2 c Cal Date Jan 19 2004 lvi Enabled Output Range 10 10 Volts v Output Shutdown Name Value AOutD E 0 0 AOut 0 0 AOut2 0 0 AOut3 0 0 AOut4 0 0 AOut m 0 0 AOut6 m 00 AOut E mu j 00 Figure 5 19 Example AO 302 Module Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 United Electronic Industries Inc Date October 2010 File DNR 12 6 1G_Chap5 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 5 71 PowerDNA Explorer You can change output initialization and shutdown values You can also change Output Range using the combo box and this only affects values displayed in initialization and shutdown tabs You can then choose Network gt gt Store Config to apply all changes to the module Output Range is a popup allowing you to choose between 10 0V 0 10V and 10 10V Output Initialization Shutdown tabs switch between settings for init and shutdown states as well as operation mode configuration The Output Initialization and Shutdown tabs contain the channel list table which has the followi
50. provides a general description of the menus and screens of PowerDNA Explorer when used with a DNR X 1G system Chapter 6 The DNR CPU 1000Core Module CPU NIC This chapter describes the DNR CPU 1000 module which contains a PowerPPC CPU and a GigE Network Interface Module Chapter 7 Programming Board specific Functions This chapter describes tools and facilities used for programming board specific functions Appendix A Configuring Additional Ethernet Cards This appendix describes procedures for installing and configuring additional Ethernet cards for use with various popular operating Systems Appendix B Field Replacement of Fuses This appendix describes procedures for replacing fuses in the field Index This is an alphabetical listing of topics covered in the manual identified by page number Tel 508 921 4600 www ueidaq com Vers 1 5 Date October 2010 File DNR 12 6 1G Chap1 fm 69 ie e 6 DNR X 1G RACKtangle and HalfRACK Systems Chapter 1 Introduction Manual Conventions To help you get the most out of this manual and our products please note that we use the following conventions Tips are designed to highlight quick ways to get the job done or reveal good ideas you might not discover on your own NOTE Notes alert you to important information CAUTION advises you of precautions to take to avoid injury data loss and damage to your boards or a system crash Text formatted in bold typ
51. the firmware should use if a network packet originated from this DNR 12 6 without a previous request from the host side If the DNR 12 6 replies to a DaqBIOS packet it uses the source IP address from the IP packet header and source UDP port from UDP packet header Let s assume that you want to connect a DNR 12 6 to the dedicated network secondary NIC adapter in the host PC Let s also assume that host IP address on this dedicated network is IP address 192 168 100 28 Network mask 255 255 255 0 Gateway ignored NX Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Qy ee Industries Inc Date October 2010 File DNR 12 6 1G_Chap7 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 7 85 Programming Module specific Functions DNS ignored Internet Protocol TCP IP Properties EN 7 xi General You can get IP settings assigned automatically if your network supports this capability Otherwise you need to ask your network administrator for the appropriate IP settings C Obtain an IP address automatically IP address 192 168 100 28 Subnet mask 255 255 255 0 Default gateway 1 i Obtain DNS server address automatically Use the following DNS server addresses Preferred DNS server Alternate DNS server Advanced Figure 7 1 TCP IP Properties Set DNR 12 6 system address to any address in the range of 192 168 100 1 th
52. 4 GxAGGDEG8G 8 40 1 phys 9037659 68 5 Current time 87 43 09 02 22 1988 Power DNA version 3 4 6 development Built on 15 58 88 Mar 18 2888 396MHz MPC8347 DCache 32k uC OS v 280 is running Enter help for help ras Status Comm Status 493 ERROR BREAK cts DSR RING v PLSD CD CTSHold I XOFFHold TXChar aga event ERR DSR Hold XOFF Sent TX Chars 0 BREAK PLSD Hold EOF Sent PX Chars 0 Figure 4 1 Typical MTTTY Screen The boot process displays the model serial number and slot positions of boards in the rack enclosure Type show CR to display information on system configuration as illustrated in Figure 4 2 Copyright 2010 United Electronic Industries Inc Tel 508 921 4600 www ueidaq com Vers 1 5 Date October 2010 File DNR 12 6 1G_Chap4 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 4 36 Installation and Configuration DQ gt show name IOM 3 7 716 model 80x38012 serial 6637716 fuct 1 2 6 6 mac 66 6C 94 66 93 4E sru 192 168 109 2 ip 192 168 100 108 gateway 192 168 100 1 netmask 255 255 255 0 mac2 00 0C 94 F 93 4E sru2 192 168 100 102 ip2 192 168 166 116 gateway2 192 168 166 1 netmask2 255 255 255 0 udp 6334 license Manufactured 1 31 2668 Calibrated 1 31 2668 Dno E Figure 4 2 Show System Configuration All parameters can be changed most notably the IP address gateway and subnet mask n
53. 5 the DNR 6 enclosure is designed to house the following items One isolated DNR POWER DC DC DC Power Module Power Monitor with status indicating LEDs a local on off switch and 4 pin Molex Power In connector PAN Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Qy V1 Bectronic Industries Inc Date October 2010 File DNR 12 6 1G_Chap3 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 3 26 The DNR 6 1G HalfRACK System One DNR CPU 1000 dual slot CPU NIC module with indicating LEDs two Ethernet connectors Main and Diagnostic Ports sync connector reset pushbutton SD card slot USB controller slave ports future use and a DB 9 connector for a serial port Up to 6 PowerDNR front pull out I O modules boards functionally identical to PowerDNA I O boards but designed for mounting in a DNR rack enclosure One DNR BP 6 Backplane with two temperature sensors e DNR IO FILLER blank filler panels for all unused slots Three 8 volt cooling fans mounted on the rear of the enclosure NOTE Note that the rightmost module Module 6 is 2 slots wide to accommodate future designs and or custom modules Rubber feet are supplied for desktop or tabletop mounting If flange mounting is desired contact UEI for more information The enclosure is a rigid mechanical structure with complete EMI shielding A convenient carrying handle is also provided
54. ACK Systems Chapter 7 Programming Module specific Functions If internal sources are selected for those signals all external signal configurations do not affect module clocking The same interface applies to the CPU module The CPU module has one external input and one output routable to the SYNCx interface as well as multiple clocks It is possible to include an IEEE 1588 implementation with an atomic clock 1us resolution in the future NOTE For a detailed description of the PowerDNx Protocol and the various Operating Modes for the Cube including a discussion of Host IOM Communication Operation of the DAQBIOS Protocol Real Time Operation with an IOM and Asynchronous operation with an IOM refer to the document entitled PowerDNx Protocol and Operating Modes for PPCx PPCx 1G Cubes and DNR x 1G HalfRACK and RACKtangle Chassis Document PN Man DAQBIOS Protocol 1010 Version 1 0 93 Copyright 2010 United Electronic Industries Inc Tel 508 921 4600 www ueidaq com Vers 1 5 Date October 2010 File DNR 12 6 1G_Chap7 fm DNR X 1G RACKtangle and HalfRACK Systems Appendix A A 1 Configuring a To configure a second Ethernet card for your system use the following Second procedure Ethernet Card Under Windows XP A Set Up Your Ethernet Card NIC If you already have an Ethernet card installed skip ahead to the next section Configure TCP IP If you have just added an Ethernet card to install it do
55. C DC 1 2V LDO FAN1 2 CONTROL FAN3 4 CONTROL SR SERES Y YYYY 2 5V NIC 24 bit ADC LTC2498 13 sources 2 5V 2 5VNIC 3 3V 3 3VNIC 3 3V NIC 24Vm 24VNIC VIN 1 5V 1 2V 8V FAN lin 24V NIC TEMP1 TCPOS TEMP2 TCNEG Voltage sources use 1 23 1 TEMP dividers on the front end except for the Vin which uses a 1 45 3 divider TEMRE Standard NIC logic plus e Access to ADC data readings e Fan 1 2 and 3 4 ON OFF control e Fan ON OFF status e12 LEDs ON OFF control LED block 12 status LEDs Figure 2 14 Functional Block Diagram of DNR POWER DC Module DNR Bus Connector As shown in Figure 2 14 the DNR POWER DC Module operates as follows A 9 36VDC voltage input Vin from an external source is connected to the board through a replaceable slow blow fuse The board monitors the input current and passes Vin to the DNR bus as Vout Vout also is connected to DC DC converters that produce 24 VDC 3 3VDC and 1 5VDC output voltages which are also placed on the DNR bus Both 3 3 and 1 5VDC voltages are connected to low dropout regulators that in turn generate the 2 5VDC and 1 2VDC output voltages on the bus The 24VDC source is fed to a low dropout regulator that produces 8VDC to drive the cooling fans through fan controller chips Copyright 2010 Tel 508 921 4600 www ueidaq com United Electronic Ind
56. Chap6 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 6 76 The DNR CPU 1000 Core Module 6 1 Device The DNR CPU 1000 Core Module architecture can be represented as follows Architecture of DNR Core Module 1000 BASE T Figure 6 2 FreeScale PowerPC CPU NIC Controller Architecture The core of the system is a Freescale formerly Motorola PowerPC MPC8347 32 bit 400 MHz processor which controls the following components e Primary Network Interface MII Port NIC1 Diagnostic Network Interface Port NIC2 e RS 232 serial port e UBS 2 0 dual port Controller and Slave for future use e 32MB flash memory 128MB of SDRAM SYNC port e Control logic LEDs SD Card Slot Card not included e Watchdog timer with real time clock battery backed Not all components are available for control from the CPU The CPU can program flash memory set the LEDs set up the watchdog timer set the real time clock and use 256 bytes of backed up memory in the watchdog timer chip All functions are available at the firmware level only described in iom c iom h Zs Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Qy ee Industries Inc Date October 2010 File DNR 12 6 1G_Chap6 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 6 77 The DNR CPU 1000 Core Module 6 1 1 Primary This port provides communication between the DNR system and the primary Network LAN network Interface MII Port NIC1 6
57. Control Panel window should still be open STEP 7 Open the Add New Hardware control panel and follow the on screen instructions We recommend that you allow Windows to search for and install your card automatically STEP 8 Restart your computer if Windows gives you the option to do so Then continue with Install TCP IP Install TCP IP To determine whether TCP IP software is already installed on your computer follow these steps STEP 1 From the Start menu select Settings and then Control Panel STEP 2 Double click on the Network icon Click on the Configuration tab if it is not already selected NX Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Y United Electronic Industries Inc Date October 2010 File DNR 12 6 1 G_Appx fm DNR X 1G RACKtangle and HalfRACK Systems Network 2 xi Configuration Identification Access Control The following network components are installed E Client for Microsoft Networks iu SMD PENET Family Ethernet Adapter PCI ISA if Dial Up Adapter Y TCP IP gt AMD PCNET Family Ethernet Adapter PCI ISA TCP IP gt Dial Up Adapter Add Remove Properties STEP 3 Look in the box labeled The following network components are installed STEP 4 If you see IPX SPX compatible Protocol or NetBEUI in the list select it then click the Remove button to delete it These protocols are used by some networked applications especially games but they may interfere with y
58. ED ELECTRONIC INDUSTRIES INC AS CRITICAL COMPO NENTS IN LIFE SUPPORT DEVICES OR SYSTEMS Products sold by United Electronic Industries Inc are not authorized for use as critical components in life support devices or systems A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness Any attempt to purchase any United Electronic Industries Inc product for that purpose is null and void and United Electronics Industries Inc accepts no liability whatsoever in con tract tort or otherwise whether or not resulting from our or our employees negligence or failure to detect an improper purchase Chapter 1 Introduction uuuleeleseeseeseeeeese Ren 1 1 1 Organization of Manual 1 2 2 00 00 ce ren 1 Chapter 2 The DNR 12 1G RACKtangle System 200 c cece 3 2 1 PowerDNR DNR 12 1G System 2 te eae 3 2 2 Specifications si e pia riria aa ee aaa yew AURA Adah RR Rd ede D e m eee 5 2 3 Modi cte DT 6 24 DNR 12 1G PowerDNR System Enclosure 000 eee eee eee eae 7 2 4 1 Cooling AIF EIOW Luce an REEL AERE ERREUR RE Re RU Gs 11 2 4 2 DNR Power CPU NIC and I O Modules 12 2 5 DNR POWER DC Module lssseeeeee era CEEE E 16 2 6 DNR CPU NIC Module nosas raient eara men 19 2 7 DNR Buffer Module 0 0000 cette eee 20 2 8 DNR IO Modules
59. Electronic Industries Inc b d These parameters can be reviewed by using the show command while you are at the monitor gt prompt fwad is the initial address where firmware is stored This address should be set before storing firmware or executing it fwgo defines whether the monitor should load firmware or display a command prompt fwsz defines the size of the stored firmware Default value is 0x100000 one megabyte fwcp defines the address to which the monitor copies firmware from flash memory The default is 0x20000 The firmware is compiled to run from this address fwst defines the firmware entry point The firmware entry point follows the vector table and is located with an offset 0x400 from the beginning of the firmware code These parameters are pre programmed at the factory and there is no known reason for you to change them The monitor command wjmp causes the monitor to load and execute firmware After reset the processor reads the boot up sequence located at Oxfffff100 This command sequence is a part of U Boot code U Boot initializes all major subsystems of the CM including DDRAM and Ethernet interface After initializing U Boot performs a command list stored in its environment sector under the bootcmd entry Standard commands to launch firmware are either fwjmp or go Oxffc10000 depending on the version of U Boot installed U Boot then gives up control to the firmware c
60. I O layers 51 Modifying the IP Address 36 Mounting 49 MTTTY Screen 35 N Network Mask 37 O Organization of Manual 1 21 P PowerDNA Explorer 58 Analog Input Layer Settings 71 Analog Output Layer Settings 70 Counter Timer Layer Settings 72 Device Tree 62 DIO Layer Settings 65 File Menu 58 Help 62 Layer Settings 64 Main Window 58 Menu Bar 58 Network Menu 59 Settings Panel 63 Toolbar 62 View Menu 61 Programming Layer Functions 79 R Repairs 51 Reset Button 48 S Self Diagnostics 35 Seting CM Parameters 80 Setting Parameters Via Serial Interface 83 Setup Program 33 Software Install Linux 34 Specifications 5 23 Startup Sequence 79 Support ii Support email support ueidaq com ii Support FTP Site ftp ftp ueidaq com ii Support Web Site www ueidaq com ii Copyright 2008 all rights reserved United Electronic Industries Inc Tel 508 921 4600 Date October 2010 Vers 1 5 File DNR12 6 1G ManuallX fm www ueidaq com DNR X 1G RACKtangle and HalfRACK Systems System Front Panel Layout 34 Updating Firmware 46 Upgrades 51 T Terminal Emulation Program 34 W U Windows u Boots Registry 34 rr cn ee X X Nu A H X X uug Copyright 2008 all rights reserved Tel 508 921 4600 www ueidaq com Vers 1 5 DNE Eleckonie ndustiesing Date Oct
61. ILED STS_POST_DC24 and STS_POST_DCCORE can be changed during operation if the corresponding failure occurs status flags STS POST MEM FAIL 1L 0 Memory test failed STS POST EEPROM FAIL 1L 1 EEPROM read failed STS POST LAYER FAILED 1L 2 Layer failure STS POST FLASH FAILED 1L 3 Flash checksum error STS POST SDCARD FAILED 1L 4 SD card is not present T R STS POST DC24 1L 5 DC gt 24 layer failed STS POST DCCORE 1L lt lt 6 Core voltage problem STS POST BUSTEST FAILED 1L 7 Bus test failed hwtest c STS POST BUSFAIL DATA 1L 8 Bus test failed on data tst STS POST BUSFAIL ADDR 1L 9 Bus test failed on addr tst STS POST OVERHEAT 1L 10 Overheat detected STS POST STICKY STS POST MEM FAIL STS POST BUSTEST FAILED STS POST BUSFAIL DATA STS POST BUSFAIL ADDR logic define also define define also define also define running define running define define define define define support error reporting define The third word contains the logic status flags They are read and assembled from the various registers of the common layer interface CLI upon request Not all layers implement full functionality and layers operating normally should not
62. IP address of the secondary diagnostic Ethernet port To change the IP address of the secondary port NIC2 use the terminal program as with the primary port but instead use the command set ip2 aaa bbb ccc ddd where aaa bbb ccc ddd is the new IP address for the secondary port Then proceed the same as with the primary port 4 3 Improving To improve DNR X 1G network performance we recommend that instead of Network connecting to a company wide network you use separate commercially Performance 9Vailable network interface controller NIC cards and where possible set up a single dedicated mini network for DNR X 1G racks for both operation and diagnostics as shown in Figure 4 4 As an alternative you can configure two separate networks one for operation and one for diagnostic purposes as shown in Figure 4 5 If you do not need to connect to a company LAN and have only a single DNR X 1G in your system you can connect it directly to your host as shown in Figure 4 3 NIC1 192 168 1 10 Primary Port ple NIC2 192 168 100 3 Diagnostic Port Figure 4 3 Single DNR X 1G Direct Connected to Host without LAN Switch FAS Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 V1 Bectronic Industries Inc Date October 2010 File DNR 12 6 1G_Chap4 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 4 39 Installation and Configuration Figure 4 4 shows a two rack single network system with a LAN sw
63. K button to return to the Network control panel STEP 11 Click OK to exit the Network control panel STEP 12 Restart your computer if Windows gives you the option to do so A Copyright 2010 i Tel 508 921 4600 www ueidaq com Vers 1 5 United Electronic Industries Inc Date October 2010 File DNR 12 6 1G_Appx fm DNR X 1G RACKtangle and HalfRACK Systems Appendix B Field Replacement of Fuses on DNA and DNR Boards Some boards used in UEI DAQ I O systems require field replacement of fuses when unexpected overloads occur Locations of these fuses are shown in Figure 9 1 through Figure 9 3 Part numbers for the replacement fuses are listed Table B 1 Table B 1 DNA DNR Replacement Fuses UEI Fuse UEI Part ID Board Rating No Description Mfr Mfr P N F1 5A 925 5125 FUSE 5A 125V SLO SMD SILVER T R Littlefuse 0454005 MR F2 5A 925 5125 FUSE 5A 125V SLO SMD SILVER T R Littlefuse 0454005 MR F3 DC 5A 925 5125 FUSE 5A 125V SLO SMD SILVER T R Littlefuse 0454005 MR F3 1GB 10A 925 1125 FUSE 10A 125V FAST NANO2 SMD Littlefuse 0451010 MRL F4 5A 925 5125 FUSE 5A 125V SLO SMD SILVER T R Littlefuse 0454005 MR 5A 125V SLO SMD SILVER FUSE UEI P N 92505125 o o D c c Oo O i t Q m 9 o amp E e a 8 S O O T c S Z D N Ed Lu e z QO QO Figure 9 1 Location of Fuse for PL 61x PL 62x and PL 63x Boards PAN Copyright 2010 Tel 508 921 4600 www ue
64. QRDCFG structures returned PAS Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 hk diss Industries Inc Date October 2010 File DNR 12 6 1G_Chap4 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 4 53 Installation and Configuration typedef struct uint8DEV device host fills this field uint8 ss subsystem host uint32 status device status device returns following fields uine32 cfg configuration including clocks uint32 rate clock divider in 15 5ns intervals uint32 clsize size of the channel list uint32 cl channel list variable size DORDCFG pDORDCFG Note Use device 0x80 to indicate that this is the last device in the list DQCMD RDSTS This command returns the status of the IOM and each and every layer in the stack upon request int DAQLIB DqCmdReadStatus int Iom uint8 DeviceNum uint32 Entries uint32 Status uint32 StatusSize Parameters int Iom A pointer to the DQIOME structure unit8 DeviceNum Array of layer numbers to retrieve status from uint32 Entries Number of entries in DeviceNum array uint32 Status Buffer to store values received from the device uint32 StatusSize Size of buffer in 32 bit chunks Returns number of 32 bit values copied into Status There are special device numbers to access status of various layers OxFE returns IOM statu
65. R 12 1G Name shows the IOM name It can be changed Model shows the model number of the IOM FW Ver shows the version of the firmware installed on the PowerDNA cube S N shows the serial number of the IOM FAS Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Q DU Bectronic Industries Inc Date October 2010 File DNR 12 6 1G_Chap5 fm 5 2 7 2 WO Device DNR X 1G RACKtangle and HalfRACK Systems Chapter 5 64 PowerDNA Explorer MAC shows the MAC address It cannot be changed and thus is informational only IP Address shows the IP address of the IOM It can be changed Mode shows the mode the IOM is in nitialization Configuration Operation or Shutdown These modes are described in the section OM Modes Figure 5 11 shows the screen for displaying I O device settings Layer Settings 2 PowerDNA Explorer File Network View Help lolx E e el em Host PC e g IOM 19575 9 9 lom_20977 s 0 AI 201 i 1 AI 201 lt 2 AI 201 lt 3 AI 201 NX Copyright 2010 United Electronic Industries Inc b d Model Info SM Mfg Date Cal Date AI 201 4 In 24 channel MUT as A Aug 1 2004 EIU IU U U B Aug 17 2004 be a vi Enabled Figure 5 11 Example of I O Device Settings Each I O device has the following settings Model shows the model number of the device Info shows some key features of the device A fo
66. T 0 DIO 403 Info D In Out 48 channel 6 ports of 8 R a SIN 0021391 Mfg Date Nov 30 0002 Cal Date Nov 30 0002 vi Enabled 2 1 plod Input IL jl DIO1 Input mr mr ro RN DIO2 Output vi Livii Lii DIO3 mmt L J DIO4 Input OO jl DIOS i OO Figure 5 18 Example DIO 403 In Outputs FAS Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Qy V Bectronic Industries Inc Date October 2010 File DNR 12 6 1G_Chap5 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 5 70 PowerDNA Explorer Configuration tab gets sets the current input output directions per port It contains the following columns The unnamed first column contains the channels Name is a user defined string In Out contains toggle switches to select whether the channel is to be used for input or for output Initialization Shutdown tabs allow you to set port as input or output and set output values They contain the following columns The unnamed first column contains the channel names Name is a user defined string Mode specifies whether the channel is input or output 7through 0 contain the values 0 or 1 They are checkmarks for output channels that allow you to select 0 unchecked or 1 checked 5 3 Analog We ll use the AO 302 as an example Output Module NOTE Use Network gt gt Read Input Data to see immediate input values in Input Settings tabs Use Network gt gt Store Config to save values to the
67. ZN United Electronic wy Industries The High Performance Alternative DNR 12 1G RACKtangle and DNR 6 1G HalfRACK Data Acquisition Systems User Manual October 2010 Edition PN Man DNR X 1G 1010 Version 1 5 Copyright 1998 2010 United Electronic Industries Inc All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form by any means electronic mechanical by photocopying recording or otherwise without prior written permis sion Information furnished in this manual is believed to be accurate and reliable However no responsibility is assumed for its use or for any infringement of patents or other rights of third parties that may result from its use All product names listed are trademarks or trade names of their respective companies See the UEI website for complete terms and conditions of sale http www ueidaq com company terms aspx Contacting United Electronic Industries Mailing Address 27 Renmar Avenue Walpole MA 02081 U S A For a list of our distributors and partners in the US and around the world please see http www ueidaq com partners Support Telephone 508 921 4600 Fax 508 668 2350 Also see the FAQs and online Live Help feature on our web site Internet Support Support support ueidag com Web Site www ueidaq com FTP Site ftp ftp ueidaq com Product Disclaimer WARNING DO NOT USE PRODUCTS SOLD BY UNIT
68. al Interface section of this manual DNR X 1G systems come with the default password set to powerdna NX Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Qy ee Industries Inc Date October 2010 File DNR 12 6 1G_Chap5 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 5 61 PowerDNA Explorer Authenticate IOM 22813 Enter user password to unlock IO module IOM 22813 L on cas Figure 5 6 Password Dialog Box for Store Config and Store All Configs Authenticate IOM 22813 xi Enter super user password to unlock IO module IOM 22813 Figure 5 7 Password Dialog Box for Update Firmware 5 2 3 View Menu Show Wiring Diagram is a friendly reminder of the connector pins for a specific board All boards have this feature and we display this one as an example The wiring diagrams in PowerDNA Explorer match the wiring diagrams in this manual in the sections for each board PAS Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 e V Bectronic Industries Inc Date October 2010 File DNR 12 6 1G_Chap5 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 5 62 PowerDNA Explorer Wiring Diagram x Al 201 37 pin D sub Aln14 EER EEA Anz AGND RARA acnp Aln15 EER EES Ans Aln16 EMERY aina AIn17 BEE Ans AGND ER ER acnp Aln18 BJE Ane Aln19 BAJRA Ain7 Aln20 BAEN Ane 5 Aln23 RAE An 11 CIkOut PAREY extend 19v EXBEB extck 18v EE acnp EE
69. and are cleared by reading their status DQCMD_IOCTL This command is used to retrieve data from the layer When a port is in diagnostic mode it returns current data but cannot reprogram the channel list The channel list is used to inform the handler the ID of the channel from which data should be retrieved The following functions which rely on the DQCMD IOCTL command for transport are supported Table 4 2 List of Functions and Associated Layers Function Associated Layer Type s DqAdv201Read Al 201 and Al 202 DqAdv205Read Al 205 DqAdv207Read Al 207 DqAdv225Read Al 225 DqAdv3xxWrite Al 302 308 and AI 332 DqAdv4OxRead DIO 401 405 404 406 DqAdv403Read DIO 403 DqAdv416GetAIl DIO 416 Voltage current and circuit breaker state monitoring DqAdv432GetAIl DIO 432 Voltage current and circuit breaker state monitoring DqAdv448Read DIO 448 DqAdv448ReadAdc DIO 448 Voltage monitoring DqAdv501GetsStatistics SL 501and SL 508 Received error counters DqAdv566GetStatistics ARINC 429 566 Received error counters DqAdv601Read CT 601 Counters states of input lines DqAdv604Read QUAD 604 Positions states of input lines Sequence of Operation To use the diagnostic port without affecting performance of the main port UEI recommends that you use the following sequence of operations Open main port Open diagnostics port Perform hardware reset optional and re open ports if neede
70. ards are also available in PowerDNR versions for use in DNR 12 1G systems VO Buffer vo7 8 woo Vo 10 vo12 VO vo i 3 H 1 BRE EE E AA 3 Figure 2 1 Typical PowerDNR DNR 12 1G RACKtangle System As illustrated in Figure 2 4 on page 7 and Figure 2 9 on page 12 a standard PowerDNR rack system consists of the following modules One or more DNR 12 ENCL rack mounted Enclosures e DNR POWER DC Power Module one for each enclosure e DNR CPU 1000 Module Freescale MPC8347 CPU and 1 GB Ethernet 1000 Base T Network Interface Module one for each enclosure e DNR BUFFER Board Module one for each enclosure e DNR IO FILLER panels one for each unused l O slot Note These slot covers are optional and not included in the price of the rack e DNR PSU 24 100 100 Watt 120 230 VAC to 24VDC External Power Supply one for each enclosure with cable and Molex connector for plug in to the DNR POWER DC Module front panel To configure a complete data acquisition system insert up to 12 DNR I O modules into each PowerDNR rack enclosure which may be specified in any combination of the following types e DNR AI 201 202 205 207 208 211 225 e DNR AO 308 308 350 308 353 308 420 332 e DNR DIO 401 402 403 404 405 406 416 432 433 448 e DNR CT 601 DNR QUAD 604 e DNR SL 501 DNR CAN 503 NX Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Qy ee Industries Inc Date Oct
71. ce section of this manual DNR X 1G systems come with the default password set to powerdna Authenticate IOM_00000 x Enter user password to unlock IO module IOM 00000 powerdna Figure 4 11 Password Dialog Box STEP 10 Wait for the progress dialog to complete The system will then be updated and running the new firmware Firmware Update Progress x Writing flash of IOM 00000 T Cancel Figure 4 12 Firmware Update Progress Dialog Box Each system is updated in three steps First the firmware is transferred to the system Second the firmware is written to the flash memory During this step the R W light on the front of the cube is lit in addition to the PG light Third the system is reset During this step the ATT COM and PG lights are lit and the R W light will turn on and off periodically When the system is finished resetting only the PG light is lit Firmware Update via Serial Port To upload firmware over the serial port using a terminal client MTTTY do the following STEP 1 Establish communication between the PC and a DNR CPU 1000 CPU over the serial link STEP 2 Use the hardware Reset switch on the front of the DNR CPU 1000 Module to reset the CPU Module or type reset all STEP 3 While the system is starting up again press ESC to go into u_boot STEP 4 Type the command shown below to erase firmware download area in the Flash memory gt erase 1 192 202 gt
72. ck the correct computer IP setting based on the device that it finds connected to the Ethernet port Under this configuration your primary IP setting is configured for Obtain IP Address Automatically for connection to your company Network and your secondary IP setting Alternate Configuration is configured for 192 168 100 1 with a subnet mask of 255 255 255 0 for connection to the PowerDNA cube or DNR 12 6 The following steps allow you to configure your alternate IP address starting at the Control Panel STEP 1 Double click on Network Connections STEP 2 Double click on Local Area Connections STEP 3 Click on the Properties button STEP 4 Select nternet Protocol TCP IP and click on the Properties button STEP 5 Select the Alternate Configuration tab NX Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Qy ee Industries Inc Date October 2010 File DNR 12 6 1G_Appx fm DNR X 1G RACKtangle and HalfRACK Systems STEP 6 Select User Configured STEP 7 Enter 192 168 100 1 for the P address STEP 8 Enter 255 255 255 0 for the Subnet mask STEP 9 Close all open configuration windows using OK or Close Use the following screen to configure the Alternate Configuration tab located under the Windows XP network configuration screen located in the Windows XP Control Panel Local Area Connection Properties Network Connections General Authentication Advanced Connect using Mg Intel R 82553 Fas
73. d Lock diagnostic port into DQSETLOCK DIAG When operation is configured on the main port read the status of the diag nostics port to verify that the configuration was programmed correctly Once operation on the main port is started the diagnostics port becomes available for data retrieval 7 Read status of the diagnostics port to make sure that all layers of interest successfully entered operating mode without error 8 In the cycle a Retrieve the current status once a second IRN D Tel 508 921 4600 www ueidaq com Vers 1 5 Date October 2010 File DNR 12 6 1G_Chap4 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 4 57 Installation and Configuration b Check the flags for error conditions c Retrieve additional data if any flags are set 9 Stop operation and unlock diagnostics port 10 Resume normal operation with main port PAS Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 e V Bectronic Industries Inc Date October 2010 File DNR 12 6 1G_Chap4 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 5 58 PowerDNA Explorer Chapter 5 PowerDNA Explorer The PowerDNA Explorer simplifies configuration and setup of a PowerDNR DNR X 1G RACKtangle system under Microsoft Windows This section describes the various menus screens in PowerDNA Explorer NOTE The PowerDNA Explorer DEMO lets you safely explore the menus and I O board screens without using any real hardware NOTE Throughou
74. d the number and order of I O modules it can accept All standard PowerDNA I O boards are available in PowerDNR versions for use in DNR 6 1G systems Figure 3 1 Typical DNR 6 1G HalfRACK System As illustrated in Figure 3 3 and Figure 3 5 on page 27 a standard DNR 6 1G PowerDNR Half RACK system consists of the following modules One or more DNR 6 ENCL rack mounted enclosures e DNR POWER DC Power Module one for each enclosure e DNR CPU 1000 Module Freescale MPC8347 CPU and 1 GB Ethernet 1000 Base T Network Interface Module one for each enclosure e DNR IO FILLER panels one for each unused l O slot Note These slot covers are optional and not included in the price of the rack e DNR PSU 24 100 100 Watt 120 230 VAC to 24VDC External Power Supply one for each enclosure with cable and Molex connector for plug in to the DNR POWER DC Module front panel To configure a complete data acquisition system insert up to 6 DNR I O modules into each PowerDNR rack enclosure which may be specified in any combination of the following types e DNR AI 201 202 205 207 208 211 225 e DNR AO 308 308 350 308 353 308 420 332 e DNR DIO 401 402 403 404 405 406 416 432 433 448 e DNR CT 601 DNR QUAD 604 e DNR SL 501 DNR CAN 503 e DNR 429 566 DNR 429 512 NX Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Qy ee Industries Inc Date October 2010 File DNR 12 6 1G_Chap3 fm
75. download from the UEI website at www ueidaq com 2 9 DC Power Table 2 1 lists the DC power threshold specifications for DNR 12 1G 12 slot Thresholds RACKtangle systems Table 2 1 DC Power Thresholds for DNR X 1G RACKtangle and HalfRACK systems Backplane Power Rail Turn on Reset Turn off Voltages Voltage V Voltage V Voltage V Notes Logic power 3 3V 2 5V 7 5 7 2 7 0 Supplies power to all CPUs supply 1 5V 1 2V When Vin is and oe oe below 2V 8 municate wi eme when CPU is functional voltage reset puts all layers into reset mode Analog power 24V 8 5 7 8 Analog power supply is supply used as a regulated source for on layer DC DCs on most layers Fan power 12V 8 5 8 4 supply On layer DC VIn 7 8 8 8 7 5 8 5 Varies with layer type DCs that use input power 1 Turn on V The value of Vin at which the corresponding DC DCs are turned on 2 Turn off V The value of Vin at which the corresponding DC DCs are turned off NOTE A DNR 12 1GB CPU NIC core module consumes only 70mW when Vin is below 7V NX Copyright 2010 Tel 508 921 4600 www ueidag com Vers 1 5 bd United Electronic Industries Inc Date October 2010 File DNR 12 6 1G Chap2 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 3 21 The DNR 6 1G HalfRACK System Chapter3 The DNR 6 1G HalfRACK System 3 1 System The UEI PowerDNR DNR 6 1G HalfRACK product is identical to the DNR Overview 12 1G system except for the size of the enclosure an
76. ectronic Industries Inc Date October 2010 File DNR 12 6 1G_Chap6 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 7 79 Programming Module specific Functions Chapter 7 Programming Module specific Functions 7 1 Overview This chapter describes tools and facilities used for programming module specific functions memory maps for various CPUs register descriptions procedures for startup setting parameters loading updating firmware setting up triggers synchronization and clock lines The DNR CPU 1000 Core Module has the following memory map Table 7 1 Memory Map Start Device Address End Address Size Description SDRAM 0x0 0x8000000 128MB SDRAM_ADDRESS Exception table 0x0 0x3000 12k Processor address map IMM 0x10000000 Memory map register tum ADDRESS On board logic OxAO0E0000 OxAOOEFFFC 64kB EXT_SRAM_ADDRESS Watchdog timer 0xA00E8000 IOM WDTIMER within PLD access space Processor 0x80000000 RAMBAR Module CS2 0xA0000000 OxAOOFFFFC 1MB EXT_DEV_ADDRESS2 Module CS3 0xA0100000 OxAFFFFFFC 256M EXT DEV ADDRESS3 Flash OxFFC00000 OxFFCOFFFF 64kB Parameters 64 sectors parameters Flash firmware OxFFC10000 OxFFEFFFFF 3MB Firmare 3MB 64kB Flash U Boot OxFFF00000 OxFFFFFFFF 1MB U Boot Two address ranges are interesting for host software Module Address Space 0xA0000000 OxAOOFFFFC and 0xA0100000 OxAFFFFFFC
77. ed Output Shutdown Figure 5 16 Example of DIO 403 Outputs Input Output Configuration Initialization Shutdown tabs switch between settings for init and shutdown states as well as operation mode configuration and display of current data Input Output tabs get set the current input output values They contain the following columns FAS Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 yee Date October 2010 File DNR 12 6 1G_Chap5 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 5 69 PowerDNA Explorer The unnamed first column contains the channels e Name is a user defined string e 7 through 0 contain the values 0 or 1 For the output tab they are checkmarks for output channels allowing you to select 0 unchecked or 1 checked PowerDNA Explorer File Network View Help Hodod DIO 403 Te eeaeee c 9p e wp 9 e S open Info D In Out 48 channel 6 ports of 8 ele lj TT SK 0021391 i Mfg Date Nov 30 0002 un B Cal Date Nov 30 0002 Vi Enabled i 10M 20977 lt 0 DIO 403 Configuration Name Tin Toa DIO0 DIO1 DIO2 DIO3 DIO4 DIOS Figure 5 17 Example of DIO 403 Configuration PowerDNA Explorer File Network View Help EA 964 85 Host PC 9 oM 20977 2 DIO 403 IEJBEEEEEESEEEEEEREE
78. ed define DQ LNCL RSVDO 1UL 16 reserved define DQ LNCL DIFF 1UL 15 differential mode PAS Copyright 2010 United Electronic Industries Inc b d There are a few helper macros defined to simplify setting gain and subsystem flags as follows Tel 508 921 4600 www ueidaq com Vers 1 5 Date October 2010 File DNR 12 6 1G Chap7 fm define define define define define define DNR X 1G RACKtangle and HalfRACK Systems Chapter 7 87 Programming Module specific Functions DQ LNCL GAIN G G amp Oxf lt lt 8 set gain DQ LNCL GETGAIN E E amp Oxf00 gt gt 8 pull out gain DO LNCL GETCHAN E E amp Oxff pull out channel DQ EXTRACT SS flags flags amp LNCL SS1 LNCL SS0 gt gt 28 DO EXTRACT DIR flags flags amp LNCL INOUT 30 DO SS DIR ss dir ss 1 dir NX Copyright 2010 United Electronic Industries Inc b d The configuration flags serve different functions DQ LNCL NEXT specifies that there is a following channel list entry in the channel list A channel list entry without this flag set is considered the last one Advanced and ACB functions add this flag automatically DO LNCL INOUT specifies whether this is an input or output channel for multifunction modules DO LNCL SS1 specifies the subsystem to which the channel belongs Do not use for single subsystem modules
79. eeeseteeesenaeens 73 5 23 Example Bin Counter Controls ccecccceeccecceeeeeeeeeeeeeeeceaaeaaeaeeeseeeeeeeeeeeeeseeniaaeees 73 5 24 Example Pulse Width Modulation PWM Controls eeeeenne 73 5 25 Example Pulse Period Controls c ceccecceeeeeeeeeeeeeeeeeceeaaeeeeeeeeeeeeeteteeeeennensaeees 73 5 26 Example of Started Counter cccecceeccccecccceeeeeeeeeeeeeeeeeseaeaaeeaeceeeeseeeeeeseeeeeesenaeees 74 Chapter 6 The DNR CPU 1000 Core Module esee 75 6 1 PowerDNR Core Module CPU NIC DNR CPU 1000 sse 75 6 2 FreeScale PowerPC CPU NIC Controller Architecture ssssessssss 76 6 3 CPU NIC Pinout Diagrams ssssssssssseeeeeeme nnne nnn ns 78 Chapter 7 Programming Module specific Functions LLs 79 7 1 TCP IP Properties ssssssssssssssssesseenenee nennen emn nrnn enne n nennen ner nenten 85 7 2 Core Module Interconnection Diagram sssssssssss eem 91 Appendix B Location of Fuses eleeeeeeeeelee een 110 9 1 Location of Fuse for PL 61x PL 62x and PL 63x Boards cccccceeeeeeeteeeseees 109 9 2 Location of Fuses for DNR POWER DC Board ssssssssseeeee 110 9 3 Location of Fuses for DNR POWER 1GB Board ssssssssseee 110 s Copyright 2008 Tel 508 921 4600 www ueidaq com Vers 1 5 b d Dnited Electroni
80. eface generally represents text you should enter verbatim For instance it can represent a command as in the following example You can instruct users how to run setup using a command such as setup exe Before plugging any I O connector into the Cube or Board be sure to remove power from all field wiring Failure to do so may cause severe damage to the equipment Usage of Terms Throughout this manual the term Cube refers to either a PowerDNA Cube product or to a PowerDNA RACKtangle rack mounted system whichever is applicable Throughout this manual the term DNR X 1G refers to both DNR 12 1G and DNR 6 1G types of systems The DNR 12 can accept up to 12 IO modules and the DNR 6 1G can accept up to 6 IO modules The two models are identical in all other respects 2 Copyright 2010 United Electronic Industries Inc Tel 508 921 4600 www ueidaq com Vers 1 5 Date October 2010 File DNR 12 6 1G_Chap1 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 2 3 The DNR 12 1G RACKtangle System Chapter2 The DNR 12 1G RACKtangle System 2 1 PowerDNR The UEI PowerDNR DNR 12 1G RACKtangle product is a rack mounted DNR 12 1G version of the popular PowerDNA Cube Ethernet based Data Acquisition System System The DNR 12 1G houses a PowerDNA data acquisition system in a rack enclosure accessible from the front of the rack Multiple DNR 12 1G systems may be mounted in a single rack All standard PowerDNA I O bo
81. eindustriesalnes Date October 2010 File DNR12 6 1G_ManualLOF fm vi Chapter 1 Introduction 0 0 0 ee 1 None Chapter 2 The DNR 12 1G RACKtangle System leere 3 2 1 DC Power Thresholds for DNR X 1G RACKtangle and HalfRACK systems 20 Chapter 3 The DNR 6 1G HalfRACK System eeeeeee eee 21 3 1 DC Power Thresholds for DNR 6 1G HalfRACK Systems sees 30 Chapter 4 Installation and Configuration llelseleselllleess 31 4 1 POIL Sales estote tees uris tedio batenaacndecess E dL eed cce least se e ccce estre 52 4 2 List of Functions and Associated Layers sssssssseeeenene emere mener 56 Chapter 5 PowerDNA Explorer s seseeeeee een 58 None Chapter 6 The DNR CPU 1000 Core Module eee eee eens 75 None Chapter 7 Programming Module specific Functions Lss 79 7 1 Memor Map 79 Appendix A ccce edo piena piama Oe RUE Ree OEE ee ORO Oe ee Oe a Bad 128 None Appendix B Field Replacement of Fuses 2 000 cece eee eee eee 141 B 1 DNA DNR Replacement FUSES 2 scccccccecseseedeseeeedecendensedeedecee duei todan cidi ga ieaiaia ediad iaiia 109 Zs Copyright 2008 Tel 508 921 4600 www ueidaq com Vers 1 5 b d els Md Date October 2010 File DNR12 6 1G ManualLOT fm List of Tables vii DNR
82. erature sensors monitor temperatures within the enclosure above the DNR POWER DC module and the DNR CPU module The DNR CPU 1000 Module contains a PowerPC 8347 CPU and associated Network Interface Control NIC logic that controls all Ethernet communication functions The DNR CPU 1000 has a dual 1 GB Ethernet module Tel 508 921 4600 www ueidaq com Vers 1 5 Date October 2010 File DNR 12 6 1G_Chap2 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 2 20 The DNR 12 1G RACKtangle System 2 7 DNR Buffer The DNR BUFFER Module provides buffering between the CPU and I O module Module address control clock lines which functions as described in Figure 2 15 Although the module may not always be required it is included to provide an extra margin of safety against loss of data 2 8 DNR IO All standard PowerDNA I O modules are also available as PowerDNR modules Modules A typical PowerDNR module has functions that are functionally identical to its corresponding PowerDNA version The only difference between them is the physical mounting arrangement PowerDNR modules are designed for insertion into the DNR 12 ENCL enclosure PowerDNA modules can be inserted only into a PowerDNA Cube Therefore for detailed electrical specifications and user instructions for a specific DNR I O board refer to the datasheets and User Manuals for the equivalent PowerDNA I O module These documents are available for examination and
83. etmask configured for this system 4 2 1 IP Addresses The DNR X 1G ships with preconfigured factory default IP addresses for NIC1 on the IOM and NIC2 in nonvolatile memory usually 192 168 100 2 for NIC1 and 192 168 100 102 for NIC2 This is a static IP address the system never retrieves its IP address from a DHCP server This section describes why and how to change the default IP addresses Should you change the IP Address Yes if you plan to use the DNR X 1G on a LAN in which High sampling rate is not necessary e Some samples can be dropped due to network congestion and collisions The system should be accessible by multiple parties on the LAN Multiple Cubes systems operate and interact on the same network Alternatively if you plan to use the system for high speed measurements where high reliability is necessary a direct connection between the host PC and a NIC is recommended For a direct connection refer to Improving Network Performance on page 38 How to change the IP address of the primary Ethernet port Both PowerDNA Explorer and a terminal emulation program can be used to change IP addresses Consult your system or network administrator to obtain unused IP addresses Let s say for example that your system administrator assigns you the IP 192 168 0 65 for the primary port of your IOM 1 NIC Network Interface Controller a commercially available Ethernet i e IEEE 802 3 2005 adapter NX
84. etwork as required If you are in the office and you want to check your email Plug in the Ethernet cable for your company s network connection into your computer and either power up your computer and log onto the network as you normally do or if your computer is already powered on perform a Windows Log Off and then a Log On and log onto your company network as you normally do FAS Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Q DU Bectronic Industries Inc Date October 2010 File DNR 12 6 1G_Appx fm DNR X 1G RACKtangle and HalfRACK Systems If you are working in the field with a PowerDNA cube or DNR 12 6 Plug in the Ethernet cable from the data acquisition system into your computer and make sure that the data acquisition system is powered on Then either power up your computer and bypass your network log on screens or if your computer is already powered on perform a Log Off and then a Log On and bypass your network logon screens D Configuring a This section describes procedures for configuring a second Ethernet Card under Second Windows 2000 Ethernet Card The procedure is as follows Under Windows 2000 A Set Up Your Ethernet Card NIC Windows 2000 will normally detect and install your Ethernet card and TCP IP automatically To check that your card has been installed run through the following steps STEP 1 From the Start menu select Settings and then select Network and Dial up Co
85. go to Configure TCP IP Local Area Connection Properties axi General Connect using Big AMD PCNET Family PCI Ethernet Adapter Configure Components checked are used by this connection m Client for Microsoft Networks Y Intemet Protocol TCP IP K KI Instal Uninstall Properties STEP 5 If Internet Protocol TCP IP is not listed click on Install STEP 6 In the next window double click on Protocol Select Network Component Type Click the type of network component you want to install E Client a Service vi protocol is a language your computer uses to Description communicate with other computers STEP 7 Select Internet Protocol TCP IP and click OK E lick tthe Network Protocol that you want to metal then click OK W you have an natakasan dk for thes component click Have Dish Netwoc Protocol Apple T ak Protocol DUC Protocol Neff E UI Protoccl Netwerk Mondor Daves NWLink IP SPMetBi0S Compatible Transport Protocol STEP 8 Make sure the box beside nternet Protocol TCP IP contains a check mark and proceed to the next section Configure TCP IP NX Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Qy ee Industries Inc Date October 2010 File DNR 12 6 1G_Appx fm DNR X 1G RACKtangle and HalfRACK Systems C Configure TCP IP STEP 1 From the Start menu select Settings and then select Network and Dial up Connections STEP 2 In
86. he Network Connections window B Troubleshooting Ifyou encounter problems connecting to the network first check to make sure the Windows XP Internet Connection Firewall is turned off Follow the instructions below STEP 1 From the Start menu select Control Panel STEP 2 Under the heading Pick a Category click Network and Internet Connections STEP 3 Under pick a Control Panel icon click Network Connections STEP 4 Double click the icon under LAN or High Speed Internet In the next window click Properties STEP 5 Click the Advanced tab and uncheck the box Protect My Computer and Network by limiting or preventing access to this computer from the Internet see illustration below 4 Local Area Connection Properties General Authentication Advanced Internet Connection Firewall C Protect my computer and network by limiting or preventing access to this computer from the Internet Learn more about Internet Connection Firewall STEP 6 Click OK or Close until you return to the Network Connections window STEP 7 Close the Network Connections window C Using the If you re using a computer with only one Ethernet port such as a laptop you can Windows XP configure Windows XP to automatically switch settings depending on which Alternate network it s connected Configuration Windows XP users have the ability to configure a second IP address setting Setting under the Control Panel that will allow Windows to pi
87. ic and option numbers are stored inside E PROM E PROM is divided into certain access areas some of them can be missing in different module types typedef struct DOEECMNDEVS ee DOCALSET xxx calset DQOPMODEPRM xxx opmodeprm DOIN TPRM xxx initprm DOSDOWNPRM xxx sdownprm DOCNAMES xxx cname DEVEEPROM xxx pDEVEEPROM XXX Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Cpe ean LE Date October 2010 File DNR 12 6 1G_Chap7 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 7 90 Programming Module specific Functions The first part of the module E PROM is common device information defined as typedef struct header is standard for all devices uintl6 uintl16 uinti16 uint32 uint32 uint32 uint32 superuser access model device model to verify EEPROM identity option device option total total EEPROM size EEPROM read is expensive if this field 32 or gt 2048 read a112048 bytes sernum serial number pad to 07d when printing mfgdate manufacturing date Oxmmddyyyy user access caldate calibration date Oxmmddyyyy calexpd calibration expired Oxmmddyyyy DOEECMND EVS header is followed by device specific data structures pDOEECMNDEVS CALSET xxx conta
88. ich sequence each should be acquired output Every module has its own specific set of channel list flags The firmware takes care of this hardware dependency Please refer to the specific module description to find out what channel list flags are supported Users should use the following flags generalized for all modules entries definition lower 16 bits are reserved for channel number gain and special module specific settings define DQ LNCL NEXT 1UL 31 channel list has next entry define DQ LNCL INOUT 1UL 30 input or output subsystem define DQ LNCL SS1 1UL 29 subsystem high define DQ LNCL SSO 1UL 28 subsystem low define DQ LNCL IRQ 1UL 27 fire IRQ define DQ LNCL NOWAIT 1UL lt lt 26 execute this step but don t wait for the next CV define DQ LNCL SKIP 1UL 25 execute this step and discard data for the next CV define DQ LNCL CLK 1UL lt lt 24 wait for the next channel list clock define DQ LNCL CTR 1UL 23 clock counter once define DQ LNCL WRITE 1UL 22 write to the channel but do not update define DQ LNCL UPDALL 1UL 21 update all written channels define DQ LNCL TSRQ 1UL 20 copy TS along with data i 2 define DQ LNCL SLOW 1UL lt lt 19 slow down operation define DQ LNCL RSVD2 1UL 18 reserved define DQ LNCL RSVD 1UL 17 reserv
89. idaq com Vers 1 5 United Electronic Industries Inc File bd Date October 2010 DNR 12 6 1G App B fm DNR X 1G RACKtangle and HalfRACK Systems F1 5A L F4 5A e o O o c c O O a 3 a E ao eo N um c Zz a F3 5A4 F2 5A Figure 9 2 Location of Fuses for DNR POWER DC Board F1 54 DNA 120 pin Bus Connector F2 5A Figure 9 3 Location of Fuses for DNR POWER 1GB Board NX Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Qy ee Industries Inc Date October 2010 File DNR 12 6 1G_App B fm DNR X 1G RACKtangle and HalfRACK Systems Index Symbols Show Command 35 A Air Flow 11 B Boot up 34 C Channel List 86 Clock and Watchdog Access 85 Common Layer Interface 86 Configuration Flags 88 Configuring a Second Ethernet Card Under Win dows 2000 98 Configuring a Second Ethernet Card Under Win dows 95 98 SE ME 103 Configuring a Second Ethernet Card Under Win dows NT 101 Configuring a Second Ethernet Card Under XP 94 Conventions 2 D Default IP Address 36 DHCP 40 DNR Core Module Device Architecture 76 DNR 12 Enclosure 7 DNR 6 Enclosure 25 DNR 6 Overview 21 DNR CPU 1000 Core Module 75 DNR POWER DC 34 E EEPROM User Area Access 89 F Features 6 Field Connections 49 Fuse Replacement 109 G Gateway Mask 37 Improving Network Performance 38 Installing Software 32 L Layer Signaling 91 M Modifying
90. input Figure 2 9 DNR 12 1G System Front Panel Arrangement FAS Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 yee Date October 2010 File DNR 12 6 1G_Chap2 fm 12 DNR X 1G RACKtangle and HalfRACK Systems Chapter 2 13 The DNR 12 1G RACKtangle System Figure 2 10 Figure 2 11 and Figure 2 12 describe the conditions indicated by the LEDs on the front of each module in the rack LED ON Off means LED ON means Input Voltage OK Error Input Current OK High 1 5VDC OK Error 1 2VDC OK I O Circuit OK flashes 1 sec Fans On Off User Controlled Off default Temp High OK 24VDC OK Error Modules 1 6 3 3VDC OK Error Modules 1 6 24VDC OK Error Modules 7 12 3 3VDC OK Error Modules 7 12 Module Groups Figure 2 10 DC Power Module LEDs When Flashing Module Needs Attention Temp High OK User Controlled Off Read Write Activity Serial Comm Activity Serial Port 3 3VDC OK Error 24VDC OK Error Power Good Note On a UEIPAC CPU NIC module the LEDs are user programmable Ethernet Ports NIC1 Main NIC2 Secondary USB 2 0 Slave Port Type B Connector reserved for future use USB 2 0 Controller Port Type A Connector reserved for future use Figure 2 11 DNR CPU 1000 Module LEDs FAS Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 yee Date October 2010 File DNR 12 6 1G_Chap2 fm DNR
91. ins module calibration information Firmware writes this information automatically upon entering initialization mode OPMODEPRM xxx contains module parameters for operation mode For example Al 201 has the following parameters stored typedef struct uint32 uint32 uint32 uint32 uint32 chlst AI201 CHAN channel list full conf control word module API flags cvclk CV clock clclk CL clock trig trigger configuration DOOPMODEPRM 201 pDQOPMODEPRM 201 LEMS CB BMW This structure varies from one major firmware revision to another When the firmware switches the module into operation mode it processes stored configuration information as it would process configuration parameters received from host All working fields in the internal device information structure are filled and the unit is ready to switch into operation mode By programming the DOOPMODEPRM structure ahead of time and storing it into E PROM you can avoid programming the IOM every time before switching into operation mode INITPRM xxx contains initial I O directions and output levels The firmware sets up the direction and the level on every output line on entering initialization state SDOWNPRM xxx contains final I O directions and output levels The firmware sets up the direction and the level on every output line on entering shutdown state NX Copyright 2010 United Electronic Industries Inc
92. ion value show Show parameters show Store Store parameters flash store mw Write wr addr val hex mw mr Read rd addr hex mr time Show Set time time mm dd yyyy hh mm ss pswd Set password pswd user su ps Show process state ps value test Test something test test number simod System Init Module Cal simod routine reset Reset system reset all dqping Send DQ ECHO to mac addr gt dqping MAC IP mode Set current mode mode init config oper shutdown ID log Display log content log start end 1 clear ver Show firmware version ver devtbl Show all devices modules devtbl netstat Show network statistics netstat One of the most useful commands is show DO show name IOM 22811 model 0x1005 serial 0022811 mac 00 0C 94 00 59 1B fwct 1 2 0 0 srv 192 168 0 229 ip 192 168 0 67 gateway 192 168 0 1 netmask 255 255 255 0 udp 6334 This command displays current values of every major DNR X 1G parameter To change parameters use the set command type set for set command syntax DQ set Valid set options Tel 508 921 4600 Date October 2010 Vers 1 5 File DNR 12 6 1G Chap7 fm PAS Copyright 2010 www ueidaq com United Electronic Industries Inc b d DNR X 1G RACKtangle and HalfRACK Systems Chapter 7 82 Programming Module specific Functions name lt Device name gt model lt Model id gt serial lt Serial gt mac lt my ethernet address g
93. itch that performs both data acquisition and diagnostic functions NIC1 192 168 1 10 NIC2 192 168 100 3 Diagnostics Figure 4 4 Single Network for Both Operation and Diagnostics Using Two DNR Racks and LAN Switch Figure 4 5 shows a two rack dual network system with two LAN switches that performs both data acquisition and diagnostic functions NIC1 to Intranet NIC2 Diagnostic Ports Figure 4 5 Separate Networks for Operation and Diagnostics Using Two DNR Racks and Two LAN Switches FAS Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 b d Dnited Elecironic Industries Ino Date October 2010 File DNR 12 6 1G_Chap4 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 4 40 Installation and Configuration For example assume that your office uses a Class C network the class intended for small networks with fewer than 256 devices and your host is configured with a static IP or via DHCP Dynamic Host Configuration Protocol a protocol for assigning dynamic IP addresses to devices on a network STEP 1 Obtain your networking configuration by using the Command Prompt Start gt gt Programs gt gt Accessories Command Prompt C gt ipconfig Ethernet adapter NIC1 Local Area Connection Connection specific DNS Suffix IP Addresse wo c uo 6 a e 9o a oa f 192 168 1 10 Subnet Mask x m e x amp a s wo x 255 255 255 0 Default Gateway
94. iversal powerline brick that plugs into an AC outlet and provides 24V dc output The supply comes with a power cord for the mains and an adapter cable ending in a Molex connector for plugging into the DNR POWER DC Module e DB 9 serial cable for initial hardware configuration and firmware downloading CD ROM with support software NOTE Depending on your application you may also need to provide the following items not normally included with your order see Figures 4 3 to 4 6 on pages 38 to 42 e CAT5e cables between host and DNR system NIC1 primary port and or between host and an Ethernet switch and or between switch and DNR primary port e CAT5e cables between host and DNR system secondary diagnostic NIC2 port between host and an Ethernet switch and or between switch and DNR secondary diagnostic port 4 1 2 Install This section describes how to load the PowerDNA software suite onto a Software Windows or Linux based computer and run some initial tests The latest PowerDNA or DNR X 1G support software is online at www ueidag com download a known working copy is also on the PowerDNA Software Suite CD 1 A larger power supply is required for some configurations Refer to UEI NX Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Qy ee Industries Inc Date October 2010 File DNR 12 6 1G_Chap4 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 4 33 Installation and Configuration A Software Insta
95. king host IP define DOSETLOCK DIAG4 Switch into diagnostics mode To advance a port into diagnostics mode call this function with the Mode parameter set to DOSETLOCK DIAG To return a port to normal mode use the same function call with DOSETLOCK UNLOCK The following table describes the possible states of both ports Table 4 1 Port States Port LOCK State First Port NIC1 Second Port NIC2 First DOSETLOCK UNLOCK Full functionality Full functionality DOSETLOCK LOCK Full functionality locked to the All but state change functions host DOSETLOCK DIAG Diagnostic functionality only Full functionality Second DOSETLOCK UNLOCK Full functionality Full functionality DOSETLOCK LOCK All but state change functions Full functionality locked to the host DOSETLOCK DIAG Full functionality Diagnostics functionality only DQCMD ECHO This command returns information about the layer s installed Use of this command is described in the API manual DQCMD RDCFG This command returns the current configuration of the specified layer s int DAQLIB DqCmdReadCfg int Iom DQRDCFG pDORdCfg uint32 maxsize uint32 entries int Iom a pointer to the DQIOME structure DORDCFGpDOQRdCfg structure that contains layer configuration uint32 maxsize number of DQRDCFG structures passed uint32 entries number of D
96. l l O Module LEDS rib iret eite ctt cte ed er ead etie tcu 14 213 DNR POWER DC Module irr dt o o i da tds 17 2 14 Functional Block Diagram of DNR POWER DC Module eee 18 2 15 Functional Block Diagram of DNR 12 ENCL 0 0000 eee eee 19 Chapter 3 The DNR 6 1G HalfRACK System 00 cece cee eee 21 3 1 Typical DNR 6 1G HalfRACK System 00 0 cceeeeceeeeee eee eeeeeeeeeeeeeeeeeeeseeaaeeeeeeenaeees 21 3 2 DNR 6 1G HalfRACK Product Features sssssssseeene nennen 24 3 3 Typical HalfRACK DNR 6 ENCL Enclosure Exploded View 25 3 4 DNR 6 Air E E 26 3 5 DNR 6 1G System Front Panel Arrangement sse 27 3 6 DC Power Module BEDS uet ett n d a t PRSE QUU ees 28 3 7 DNR CPU 1000 Module LEDS ecrans anA aA ERENER EE RE 28 3 8 Typical VO Module LEDS ce a 29 Chapter 4 Installation and Configuration 0 000 cee eee 31 4 1 Typical MT TTY Screen ssssssssssseeeee nene nennen nmn nn en neri nn nemen nnne ns 35 4 2 Show System Configuration 2 eden a ce Aaland 36 4 3 Single DNR X 1G Direct Connected to Host without LAN Switch s 38 4 4 Single Network for Operation Diagnostics Using Two DNR Racks and LAN Switch 39 4 5 Separate Networks for Operation Diagnostics 2 DNR Racks and 2 LAN Switches 39 4 6 Typical Configuration for a Single DNR X 1G with a LAN Switch ssss 42 4 7 Addre
97. ll Windows 9x 2000 XP The PowerDNA CD provides one installer that combines the UEI low level driver and UEIDAQ Framework The installer automatically searches for third party IDE and testing suites and adds them as tools to the suites found Be sure to install third party applications such as LabVIEW MATLAB or MsVS2003 before installing the PowerDNA Software Suite To install the PowerDNA Software Suite do the following STEP 1 Log in as Administrator STEP 2 Run Setup a Insert the PowerDNA Software Suite CD into your CD ROM drive Windows should automatically start the PowerDNA Setup program An installer with the UEI logo and then PowerDNA Welcome screen should appear If none appears run setup exe from the CD drive Start gt gt Run gt gt d setup exe gt gt OK If you downloaded the most recent executable from www ueidaq com double click on the filename to run the executable b Choose the PowerDNA Software Suite option c Unless you are an expert user and have specific requirements select Typical Installation and accept the default configuration The Software Suite installer requires and automatically installs Sun s Java VM JRE for you in addition to the full complement of tools As an alternative use the Custom option to display and ensure that all of the necessary packages are installed Companion Documentation Quick Start Guide Configuration and Core Module I O Board Manuals Low Level Programmi
98. llation and Configuration STEP 1 Select Network Address Ranges from the menu View Help Ad dre tande Scan Network Ctrl N E Reload Config Ctri R Store Config Ctrl em Windows XP 40 469 n 32 Store All Configs Ctrl Shift w ye Ranges Read Input Data Ctrl D Start Data Logging Ctrl IP Addresses Update Firmware Ctrl 192 168 100 2 6334 Add Edit Delete one Figure 4 7 Address Ranges to be Scanned STEP 2 Add the IP address of the PowerDNR system e g 192 168 100 2 click Done STEP 3 Nowscan the LAN for PowerDNR systems or cubes using Network gt gt Scan Network One or more gray icons will display in the left hand side of the screen If no icons are displayed refer to the Troubleshooting note in the previous section Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 i Date October 2010 File DNR 12 6 1G_Chap4 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 4 45 Installation and Configuration STEP 4 Double click an icon to display its information and list the boards 2 PowerDNA Explorer File Network View Help Podad Q Host PC i IOM 19575 IOM 20877 lt 0 AI 201 i 1 AI 201 lt 2 AI 201 lt 3 AI 201 NX Copyright 2010 United Electronic Industries Inc b d Al 201 TOTO BE PEELE Info A In 24 channel ES RIA AE MW SIN 0022432 Mfg Date Aug 1 2004
99. mbered from left to right A typical module address is OxAO00nxxxx where A00 is the BASE address n is the module position number starting from O at the left XXXX is the address of the module With this addressing method the address of a given I O board module automatically changes if you move it from one position to another within the enclosure Tel 508 921 4600 www ueidaq com Vers 1 5 Date October 2010 File DNR 12 6 1G Chap3 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 3 30 The DNR 6 1G HalfRACK System The slots or module positions for the DNR 6 1G are numbered as follows Physical Position Position Module L R Number Description 1 OxC POWER DC 2 OxD POWER 1GB OxE CPU NIC 3 0x0 Module1 4 0x1 Module2 5 0x2 Module3 6 0x3 Module4 7 0x4 Module5 8 0x5 Module6 3 5 DNR POWER Refer to See DNR POWER DC Module on page 16 in Chapter 2 for a detailed DC Module description of the DNR POWER DC Module 3 6 DNR CPU NIC The DNR CPU 1000 Module contains a PowerPC 8347 CPU and associated Module Network Interface Control NIC logic that controls all Ethernet communication functions The DNR CPU 1000 has a dual 1 GB Ethernet module This unit is used in both the DNR 6 and the DNR 12 systems 3 7 DNR IO All standard PowerDNA I O modules are also available as PowerDNR modules Modules A typical PowerDNR module has functions that are functionally identical to its corresp
100. nd Data Logger Modes Upgradable to UElLogger 1200R Upgradable to UEIPAC 1200R Upgradable to UEIModbus 1200R Rugged and Industrial Solid Aluminum construction Operation tested from 40 C to 70 C Vibration tested to TBD g operating Shock tested to TBD g operating All 1 O isolated from rack and host PC Operation to TBD feet Outstanding Software Support e Windows Linux RT Linux Windows RT RTX and QNX operating systems VB VB NET C C C J MATLAB LabVIEW LabVIEW RT DASYLab OPC ActiveX Varies with layer types Refer to layer datasheets Figure 2 3 DNR 12 1G PowerDNR Product Features Tel 508 921 4600 www ueidaq com Vers 1 5 o Date October 2010 File DNR 12 6 1G_Chap2 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 2 7 The DNR 12 1G RACKtangle System 2 4 DNR 12 1G Because a major design goal of the DNR product line is to allow easy PowerDNR configuration and updates in the field each DNR 12 1G enclosure contains a System DNR POWER DC Power Module with status indicating LEDs and a local ON Enclosure OFF switch and each I O module is provided with a mechanical lever see Figure 2 6 on page 9 for quick ejection and insertion of the board In addition each DNR 12 1G system enclosure also contains its own GigE CPU and two Network Interface Control NIC modules one for controlling up to 12 I O modules mounted in the enclosure and another for diagnostics functions
101. ng Guide SDK includes lib for C Java examples and Sun s JRE The SDK is not the UeiDaq Framework PowerDNA Apps PowerDNA Explorer MTTTY PowerDNA Components incl DLL files PowerDNA Firmware d Click Next to continue through the dialogs e Click Finish to complete the installation restart the computer This Software Suite installed the bare minimum tools needed in later steps MTTTY PowerDNA Explorer and the low level driver UEIDAQ Framework provides the structure for developing applications under C C C VB NET ActiveX VB6 Delphi MATLAB LabVIEW DASYLab LabWindows CVI OPC and other programming languages NX Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Qy ee Industries Inc Date October 2010 File DNR 12 6 1G_Chap4 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 4 34 Installation and Configuration NOTE Because the installation process modifies your Windows registry you should always install or uninstall the software using the appropriate utilities Never remove PowerDNA software from your PC directly by deleting individual files always use the Windows Control Panel Add Remove Programs utility B Software Install Linux Linux The PowerDNA tgz file in the CD Linux folder contains the software package for Linux To extract the file to a local directory tar xjvf path to powerdna tgz Follow the instructions in the readme txt file contained therein
102. ng columns The unnamed first column contains the channel names Name is a user defined string Value contains a slider to set the voltage to output from the channel and the numerical voltage value which you can input directly The actual voltage depends on the selected output range 5 4 Analog Input We ll use the Al 201 as an example to start with The Al 202 and Al 205 are Module similar Settings mM NOTE Use Network 2Read Input Data to see immediate input values in Input tabs Use Network 2Store Config to save values to the module PowerDNA Explorer i Bl x File Network View Help vo 6 RES Q9 m Host PC ti s Model AIl 201 TELL Loo IOM 20877 Info A In 24 channel ze S RN E HA 4 0AF2001 s 0022432 D an M g Date Aug 1 2004 3 AI 201 E Cal Date Aug 17 2004 vi Enabled Input Range 15 15 Volts Name Value Aln 0 0007 Aln1 0 0011 Aln2 0 0016 Aln3 0 0021 Aln4 0 0025 Ans 0 003 Aln6 0 0034 Aln 0 0038 Aln8 0 0043 lAng 0 0048 Aln10 0 0053 Alnd1 0 0057 Aln12 0 0062 A3 0 0066 Ania 0 0071 Aln15 0 0076 Anie 0 008 Al1 0 0085 Figure 5 20 Example Al 201 Module FAS Copyright 2010 Tel 508 921 4600 www ueidag com Vers 1 5 United Electronic Industries Inc Date October 2010 File DNR 12 6 1G_Chap5 fm DNR X 1G RACKtangle and
103. nic Industries Inc Date October 2010 File DNR 12 6 1G_Chap5 fm Chapter 6 DNR X 1G RACKtangle and HalfRACK Systems Chapter 6 75 The DNR CPU 1000 Core Module The DNR CPU 1000 Core Module This chapter focuses on the device architecture of the Core Module not I O modules Two slots of a DNR X 1G RACKtangle Enclosure are occupied by the PowerDNR Core Module called the DNR CPU 1000 The Core Module consists of a Freescale formerly Motorola MPC8347 32 bit 400 MHz CPU and peripheral devices USB 2 0 RS 232 NIC SD etc for use with a Gigabit Ethernet communication network and an internal 66 MHz 32 bit common logic interface bus The NICs are copper 1000BaseT interfaces The module has an RS 232 port used for configuration and also two USB 2 0 ports controller and slave for general purpose use not implemented yet LEDs on the front panel of each module indicate the current operating status of the device Front Panel l iO Oa G DB 9 Connector a a for serial port sO Ox i Ne Diagnostic 4 Port NIC2 Ni SD Cord la Primary Ethernet Port NIC1 S USBB a USB A D omes USBB XR United H Isometric of Carrier holds two circuit boards CPU and NIC Figure 6 1 PowerDNR Core Module CPU NIC DNR CPU 1000 Zs Copyright 2010 Tel 508 921 4600 b d United Electronic Industries Inc Date October 2010 www ueidaq com Vers 1 5 File DNR 12 6 1G_
104. nnections STEP 2 f you see a Local Area Connection icon your Ethernet card has been detected and installed skip ahead to the section Configure TCP IP If you do not see this icon proceed to step 3 STEP 3 From the Start button select Settings then Control Panel Double click on the Add Remove Hardware icon and follow the on screen instructions We recommend that you allow Windows 2000 to search for and install your Ethernet card automatically If Windows 2000 does not find your Ethernet card you will need to install it manually by following the manufacturer s instructions STEP 4 Once your Ethernet card has been installed click OK and continue with the next section B Installing TCP IP STEP 1 From the Start menu select Settings and then select Network and Dial up Connections STEP 2 In the Network and Dial up Connections window double click on the Local Area Connection 2 icon NX Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Qy ee Industries Inc Date October 2010 File DNR 12 6 1G_Appx fm DNR X 1G RACKtangle and HalfRACK Systems STEP 3 Inthe Local Area Connection 2 Status window click Properties axi General r Connection Status Connected Duration 02 25 00 Speed 10 0 Mbps r Activity sent Ah Received Ca Packets 768 458 1 Properties Disable STEP 4 If Internet Protocol TCP IP is listed make sure the box next to it contains a check mark and
105. o the Internet Connect to the Internet so you can browse the Web and read email STEP 9 Select Set Up My Connection Manually and click Next STEP 10 Select Connect Using a Broadband Connection that is always on and click Next STEP 11 Click Finish STEP 12 In the Network Connections window double click the second icon under LAN or High Speed Internet STEP 13 In the next window see illustration below click Properties ES Local Area Connection Status General 5 upport Connection Status Connected Duration 02 08 34 Speed 10 0 Mbps Signal Strength Activity Sent 3 Received Cab Packets 5 689 4 664 _Properties_ Close STEP 14 Click the General tab click once on Internet Protocol TCP IP then click Properties STEP 15 Click the General tab click Use the Following IP Addresses and in the corresponding boxes enter 192 168 100 1 for the IP address 255 255 255 0 for the Subnet Mask and leave blank the router or default gateway information STEP 16 Click Use the Following DNS Server Addresses STEP 17 Make sure the Preferred DNS Server box and the Alternate DNS Server box are blank STEP 18 Click OK or Close until you return to the Network Connections window FAS Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 b d ited Electronic Industries Irc Date October 2010 File DNR 12 6 1G_Appx fm DNR X 1G RACKtangle and HalfRACK Systems STEP 19 Close t
106. oard into PEE backplane connector Qo 9 Ci Figure 2 6 DNR Ejection Insertion Lever Operation FAS Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Q DU Bectronic Industries Inc Date October 2010 File DNR 12 6 1G_Chap2 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 2 10 The DNR 12 1G RACKtangle System Turn bracket upside down to use as surface or flange Y mounted device Figure 2 7 DNR BRACKET Reversible Mounting Bracket PAS Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 e V Bectronic Industries Inc Date October 2010 File DNR 12 6 1G_Chap2 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 2 11 The DNR 12 1G RACKtangle System 2 4 4 Cooling Air As shown in Figure 2 8 cooling air is drawn into the rear of the enclosure Flow routed forward over the electronic circuit boards up to the top of the enclosure and then out the top rear of the enclosure The system is designed to maintain positive pressure cooling within the enclosure at all times Figure 2 8 DNR 12 Air Flow PAS Copyright 2010 Tel 508 921 4600 www ueidaq com b d United Electronic Industries Inc Vers 1 5 Date October 2010 File DNR 12 6 1G Chap2 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 2 The DNR 12 1G RACKtangle System 2 4 2 DNR Power This sec
107. ober 2010 File DNR 12 6 1G_Chap2 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 2 4 The DNR 12 1G RACKtangle System e DNR 429 566 DNR 429 512 DNR GPS e Any future additions to the PowerDNR I O module product line Note Refer to www ueidaq com for a description of each I O module All standard PowerDNA accessories are also available for use in a PowerDNR rack mount system NOTE UEIPAC UEISIM and UEIModbus deployments are now available for use with DNR 12 RACKtangle systems with the following model names e UEIPAC UEIPAC 1200R e UEISIM UEISIM 1200R e UEIModbus UElIModbus 1200R PAS Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 b d United Electronic Industries Ino Date October 2010 File DNR 12 6 1G_Chap2 fm 2 2 Specifi cations DNR X 1G RACKtangle and HalfRACK Systems Chapter 2 5 The DNR 12 1G RACKtangle System Figure 2 2 lists the technical specifications of the DNR 12 1G PowerDNR system Standard Interfaces To Host Computer Two independent 1000Base T Gigabit Ether net ports via RJ 45 connector Distance from host 100 meters max Other Interfaces One USB 2 0 controller port One USB 2 0 slave port Config General RS 232 9 pin D Sync 1 0 Slots Available DNR 12 1G Ethernet data transfer rate Data transfer and co Custom cable to sync multiple racks 12 slots mmunications rates 20 megabytes per second Analog da
108. ober 2010 File DNR12 6 1G_ManuallX fm een
109. ode located at Oxffc10000 Firmware self expands into the DDRAM initializes the exception table and starts execution There are two ways to set up Core Module CM parameters The first one is the use of serial interface and the second one is the use of DaqBIOS calls To connect to the serial interface you should connect a 9 wire serial extender cable to the DNR 12 6 CPU NIC module male plug connector and your PC COMI serial port female connector Some cables have female to female connectors so you may have to use a gender changer Set up your terminal to the proper serial port 57600 bit rate no parity eight data bits and one stop bit Alternately using Start 2Run on the Microsoft Windows desktop type Program Files UEl PowerDNA Firmware mttty exe Then click File Connect Tel 508 921 4600 www ueidaq com Vers 1 5 Date October 2010 File DNR 12 6 1G Chap7 fm 80 DNR X 1G RACKtangle and HalfRACK Systems Chapter 7 81 Programming Module specific Functions Once a connection to the PowerDNR DNR X 1G system is established tap Enter once The DNR X 1G should respond with either a bo prompt this is firmware prompt or a gt prompt monitor prompt Once you see the po prompt you can type help enter to receive the list of all available commands The following commands are available DQ help help Display this help message help set Set parameter set opt
110. on will also write your configuration to the module NX Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Qy ee Industries Inc Date October 2010 File DNR 12 6 1G_Chap5 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 5 74 PowerDNA Explorer Clicking the Start button for a counter will start that counter on the module The Start button will turn into a Stop button and the other controls for that counter will become disabled until you click Stop While the module is running you can choose Network Read Input Data to retrieve runtime values from the counter which will display in the read only text field s of the counter control panel PIU x PowerDNA Explorer File Network View Help 4e eius 9 lom_20030 i 0 CT 601 Model CT 601 cep Cepepeper e cere ep er er ere eye SIN 0021169 Mfg Date Jun 4 2004 Fig vi Enabled DUE POUL V JUU H L Wad BU JUU H Info Counter Timer 8 units 5 JF i Cal Date Jun 4 2004 Counter 1 mode Bin Counter Stop Min Gate Pulse Width psec Input Pre inversion Min Clock Pulse Width psec Gate Pre inversion Prescaler Value 3 3 C Output Post inversion C Use External Clock Counter Value l 1773034 Counter 2 mode v Start Present Value of Count Figure 5 26 Example of Started Counter PAN Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Qy V1 Bectro
111. onding PowerDNA version The only difference between them is the physical mounting arrangement PowerDNR modules are designed for insertion into the DNR 6 ENCL or DNR 12 ENCL enclosure PowerDNA modules can be inserted only into a PowerDNA Cube Therefore for detailed electrical specifications and user instructions for a specific DNR I O board refer to the datasheets and User Manuals for the equivalent PowerDNA I O module These documents are available for examination and download from the UEI website at www ueidaq com cs Copyright 2010 Tel 508 921 4600 b d United Electronic Industries Inc Date October 2010 www ueidaq com Vers 1 5 File DNR 12 6 1G Chap3 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 3 31 The DNR 6 1G HalfRACK System 3 8 DC Power Table 3 1 lists the DC power threshold specifications for DNR X 1G HalfRACK Thresholds systems Table 3 1 DC Power Thresholds for DNR 6 1G HalfRACK Systems Backplane Power Rail Turn on Reset Turn off Voltages Voltage v Voltage V Voltage v2 Notes Logic power 3 3V 2 5V 7 5 7 2 7 0 Supplies power to all CPUs supply 1 5V 1 2V When Vin is and D IE m below 7 2V a municate vi Bine when CPU is functional voltage reset puts all layers into reset mode Analog power 24V 8 5 7 8 Analog power supply is supply used as a regulated source for on layer DC DCs on most layers Fan power 12V 8 5 8 4 supply On layer DC
112. onic Industries ine Date October 2010 File DNR12 6 1G ManualTOC fm Appendix A Configuring Ethernet Cards 20 0c ee 94 Appendix B Sete aceasta dank eee ee RM RR AUN RR E RERBA RUE mee X dne RR Raine ace d 109 INDEX CCP O L 111 Zs Copyright 2008 Tel 508 921 4600 www ueidaq com Vers 1 5 We nenne Industries e Date October 2010 File DNR12 6 1G ManualTOC fm List of Figures Chapter 1 Introduction ser on eee eee Ae ee ee eS 1 None Chapter 2 The DNR 12 1G RACKtangle System 0c e eee eee eee eee 3 2 1 Typical PowerDNR DNR 12 1G RACKtangle System cccccceccccceeeeeeieeeeeeeenneeeeere 3 2 2 DNR 12 1G Technical Specifications sssssssssssssssseseeee nene 5 2 3 DNR 12 1G PowerDNR Product Features sssssesseee nennen 6 2 4 Typical PowerDNR DNR 12 ENCL Enclosure Exploded View ssss 7 2 5 Optional DNR IO Filler Panel for empty slots ssssssssssssse 9 2 6 DNR Ejection Insertion Lever Operation seeeene emn 9 2 7 DNR BRACKET Reversible Mounting Bracket 10 2 8 DNR 12 Ait FlOW 1c idee eec ette e e bene bl d a e EE ER bd E e n du 11 2 9 DNR 12 1G System Front Panel Arrangement sse 12 2 10 DO Power Module LEDS coreia Errh tta uev Lieu eed in tend lace i re ale 13 2 11 DNR CPU 1000 Module LEDS seen eene nennen nennen nns 13 2 12 Typica
113. operating mode it is cleared upon re entering configuration mode and STS FW OPER MODE which means that the layer switched into operating mode without any errors flags CLK OOl SYNC El R 1UL lt lt 0 Clock out of range error IOM define STS F define STS F packet define STS F samples packet also CHNL El IOM RR 1UL lt lt 1 Synchronization interface RR 1UL lt lt 2 Channel list is incorrect BUF SCANS PER INT 1UL 3 Buf setting error scans I BUF SAMPS PER PKT 1UL 4 Buf setting error define STS F V BUF RING SZ 1UL 5 buffer ring size define STS F buffering define STS F BUF PR size BAD CONF current config Buf setting error FW EBUF SZ 1UL 6 Buf setting error Pre G 1UL 7 Layer cannot operate in I R IUL 8 Firmware buffer overrun DER 1UL 9 Firmware buffer underrun LYR FIFO OVER 1UL 10 Layer FIFO overrun LYR FIFO UNDER 1UL 11 Layer FIFO underrun EEPROM FAIL 1UL 12 Layer EEPROM failed GENERAL FAIL 1UL lt lt 13 Layer general failure define STS FW BUF OVE define STS FW BUF UN define STS F define STS F define STS F define STS F define STS F ISO TIMEOUT 1UL lt lt 14 Isolated part reply time
114. our Ethernet connection STEP 5 Ifyou don t see TCP IP for your second Ethernet card then continue with step 4 If you do see TCP IP for your second Ethernet card skip ahead to Configure TCP IP Do these steps only if you do not see TCP IP listed in your Network control panel for your second Ethernet card STEP 6 In the Network control panel click the Add button STEP 7 In the Select Network Component Type window choose Protocol and click the Add button Select Network Component Type 21x Click the type of network component you want to install Protocol is language computer uses Computers must use the same protocol to communicate STEP 8 In the Select Network Protocol window select Microsoft under Manufacturer and TCP IP under Network Protocols FAS Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Q DU Bectronic Industries Inc Date October 2010 File DNR 12 6 1G_Appx fm DNR X 1G RACKtangle and HalfRACK Systems Select Network Protocol ex Click the Network Protocol that you want to install then click OK If you have E en installation disk for this device click Have Disk Manufacturers Network Protocols Banyan Fast Infrared Protocol IBM 4 IPX SPX compatible Protocol Microsoft 32 bit DLC Novell Have Disk STEP 9 Click the OK button to return to the Network control panel then click the OK button again to exit the control panel STEP 10 Re
115. out define STS F change or single channel ops define STS F current CL O FAIL 1UL 15 CLI or CLO counter does not OUT FA define STS F layers define STS F L 1UL 16 Output CB tripped or over IO FAIL 1UL 17 Messaging I O failed 5xx NO MEMORY 1UL 18 Error with memory allocation define STS F properly define STS F successful define STS FW CONFIG no error BAD OP LAYER ER IUL 19 Operation was not performed ERR 1UL 20 Layer entered operation ly DONE 1UL 30 Configuration is completed define STS FW OPER MODE 1UL 31 Layer entered operation mode succe ssfully status helper macros defines define STS FW STICKY PAS Copyright 2010 United Electronic Industries Inc b d STS FW EEPROM FAIL STS FW GE B ERAL FAIL Tel 508 921 4600 www ueidaq com Date October 2010 Vers 1 5 File DNR 12 6 1G Chap4 fm Copyright 2010 United Electronic Industries Inc DNR X 1G RACKtangle and HalfRACK Systems Chapter 4 56 Installation and Configuration Status bits are divided into conditional and sticky Conditional bits are set when a condition arises they are cleared when the error condition expires Sticky bits are persistent once set
116. owerDNA PowerDNA Explorer d Choose Network Scan Network e Select the DNR X 1G icon you wish to query by clicking the icon f The version is given in the FW Ver field 9 PowerDNA Explorer File Network View Help Name lOM 10238 Model 1008 DNA CM 100 Base T PW Ver 3 4 2 SN 10238 MAC 23 F8 90 7B 19 40 IP 192 168 100 2 Figure 4 9 Displaying the Version of Your Firmware FAS Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Q DU Bectronic Industries Inc Date October 2010 File DNR 12 6 1G_Chap4 fm 4 5 2 Firmware Update Instructions STEP STEP STEP STEP STEP STEP DNR X 1G RACKtangle and HalfRACK Systems Chapter 4 47 Installation and Configuration If the FW Ver field has is version 2 x x or 3 x x let x be any version number you should follow the applicable Firmware Update Instructions section below For other versions of firmware e g 1 x x refer to the user manual on the CD that accompanied your device when you purchased it Before using a new release ofthe libraries and applications to communicate with your system you must install the latest version of the firmware onto the DNR CPU 1000 The version of the firmware must correspond to the version of the PowerDNA Software Suite mismatched versions cause an error Instructions for updating the DNR CPU 1000 via PowerDNA Explorer over Ethernet LAN line and over MTTTY serial line follow
117. p1 Sensor jj 4 P of BH e H P ug 4g yp qp up yp ug oF E93 sg sls es SSS SB 3 82 2 Bz Olnz 9 60 0 9 6 Co EI IZ 2 N 4k N d A 4 old ak d s Ll o l RS 232 Status p10 O j g Stat wO Ouse Serial Port Ory olatus LEDs uO Oss Connector Oss LEDs LO O DB 9 5 Sy nc Sync Reset O FK 0N Conn PB H sa 2l NIC2 Port On off SD Card H DB 37 med Slot j NIC1 Port Connector Power d ad USBB USB 2 0 s l Slave Port J Dein T USB 2 0 O E Controller L a L Industries Port zz PowerDNR PowerDNR Typical DNR POWER DC DNR CPU 1000 PowerDNR DC DC Module LED CPU NIC Module I O Module ae Single Slot Model ATT Indicates error when red R W Flashes when bus is active COM Flashes when SD Card is read written PG Indicates presence of valid power input Figure 3 5 DNR 6 1G System Front Panel Arrangement FAS Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Q ee Industries Inc Date October 2010 File DNR 12 6 1G_Chap3 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 3 28 The DNR 6 1G HalfRACK System Figure 3 6 Figure 3 7 and Figure 3 8 describe the conditions indicated by the LEDs on the front of each module in the rack LED ON Off means LED ON means Input Voltage OK Error Input Current OK High 1 5VDC OK Error 1 2VDC OK I O Circuit OK flashes 1 sec Fans On Off User Controlled Off default Temp High OK 24VDC OK Error Modules 1 6 3 3VDC
118. r analog D for digital In for input Out for output and a number of channels available S N shows the device serial number Mfg Date shows the manufacturing date Cal Date shows the date of the last calibration done Enabled is a checkbox which when unchecked excludes the device from configuration The device is excluded from the Store All Configs command and the Reload Config command is disabled Also the device appears gray in the tree All devices are enabled by default Tel 508 921 4600 www ueidaq com Vers 1 5 Date October 2010 File DNR 12 6 1G Chap5 fm PowerDNA Explorer File Network View Help DNR X 1G RACKtangle and HalfRACK Systems Chapter 5 65 PowerDNA Explorer Select Network gt gt Read Input Data to update the Value column of any module as shown below Biel xj fo 6 6 UE IOM 19675 a lOM 20977 lt 0 Al 201 i 1 AI 201 i 2 AI 201 i 3 AI 201 5 2 8 Digital Input Output Module Settings PAS Copyright 2010 United Electronic Industries Inc b d Model AL201 E Senn Info A In 24 channel ee III i Raag SM 0022432 I Mfg Date Aug 1 2004 Cal Date Aug 17 2004 4 vi Enabled Input Range 15 15 Volts Nam vawe Aln0 0 0007 Aln1 0 0011 Aln2 0 0016 Aln3 0 0021 Aln4 0 0025 Aln5 0 003 Aln6 0 0034 Aln 0 0039 AIn8 0 0043 Ang po048 Aln10 0 0053
119. right 2010 l Tel 508 921 4600 www ueidaq com Vers 1 5 United Electronic Industries Inc Date October 2010 File DNR 12 6 1G Appx fm DNR X 1G RACKtangle and HalfRACK Systems Microsoft TCP IP Properties 121 xi IP Address DNS WINS Address Routing n IP address can be automatically assigned to this network card by a DHCP server If your network does not have a DHCP server ask your network administrator for an address and then type it in the space below Adapter 3Com Fast EtherLink XL NIC 3C305B T Obtain an IP address from a DHCP server Specify an IP address IP Address Subnet Mask Default Gateway Advanced Cancel Apply STEP 8 Click on the DNS tab Leave blank the Host Name and Domain fields STEP 9 Click OK to close the Microsoft TCP IP Properties window STEP 10 Click Close to close the Network control panel STEP 11 Restart your computer STEP 12 You should now be able to access network based services F Configuringa Set Up Your Ethernet Card NIC Second If you installed your Ethernet card before or at the same time as you installed Ethernet Card Windows 95 98 ME then the system should have automatically detected it and Under you should proceed to the next section Install TCP IP Optionally you may Windows 95 98 follow steps 1 3 below to confirm that your card is recognized SE ME If you obtained an Ethernet interface after Windows
120. rough 192 168 0 254 excluding 192 168 100 28 the host IP address For example type DQ set ip 192 168 0 2 Then DQ store This sequence of commands stores a new IP address in the flash parameter sector Then you have to reset the DNR 12 6 system DNR 12 6 systems come from the factory with IP addresses already preset for 192 168 x x network The factory IP address can be found on the label located on the back of the DNR 12 6 enclosure along with factory set MAC address After the IP address is set you can establish communication with the DNR 12 6 system using PowerDNA Explorer 7 3 2 Clock and To show and set up the date and time use the time command as follows Watchdog Access DQ time Current time 17 39 22 11 01 2004 PAS Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 b d Dnited Elecironic Industries Ino Date October 2010 File DNR 12 6 1G_Chap7 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 7 86 Programming Module specific Functions To set up time of the day enter DQ time 17 40 00 7 4 Common Module Layer Interface 7 4 4 Channel List Channel list To set up date enter DQ time 11 03 2004 Date and time are stored in the battery backed real time clock chip The Common Layer Interface is the protocol used in a PowerDNR system for communication between the IOM and its layers I O boards A channel list specifies what channels and in wh
121. rovided for on board data storage It can also store both data and Linux embedded programs using the soon to be released embedded toolkit Supports FAT12 FAT16 and FAT32 file systems 6 1 9 LEDs The operating conditions indicated by the front panel LEDs are described in the figures starting with Figure 1 9 on page 11 and ending with Figure 1 12 on page 13 6 1 10 Watchdog The DNR X 1G system includes a watchdog timer with battery backed up real Timer With time clock Real time Clock Battery Backed PAS Copyright 2010 Tel 508 921 4600 www ueidag com Vers 1 5 Qy ee Date October 2010 File DNR 12 6 1G_Chap6 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 6 78 The DNR CPU 1000 Core Module 6 2 11 CPU NIC Pinout diagrams for the various connectors on the DNR CPU 1000 and DNR Pinouts POWER DC Modules are shown in Figure 6 3 Power IN SYNC RS 232 Serial Port Connector Connector Connector on POWER Module on CPU NIC Module on CPU NIC Module VIN 4 Clock in NN FOND GND 3 i hO 9 4 8 GND 12 Clock out 3 j RAD VINH 1 8 7 3 TXD Trigger in H 11 e ag Trigger out gt 12 e SGND 3 2 5VFo 4 1 14 Mating connector available from DigiKey Molex PN 39 01 4040 Figure 6 3 CPU NIC Pinout Diagrams PAS Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 bd United El
122. s 1 stop bit Try COMI COM2 COM3 then click Connect and press Enter Reboot the DNR X 1G system The start up screen should display upon restart If all else fails contact UEI support at support ueidaq com Type show to verify the IP Subnet Mask and Gateway Ensure that the computers are on a valid subnet and have valid IPs KE EIER K Finally contact UEI for support at support ueidaq com 4 5 PowerDNA PowerDNA Explorer does just what its name implies it explores the LAN Explorer looking for connected PowerDNA Cubes and or DNR X 1G systems Chapter 3 Quick Start covers the PowerDNA Explorer in detail This section only provides a quick start guide The PowerDNA Explorer identifies DNR X 1G systems or Cubes on a selected network the discovered systems are listed on the left hand pane of the display Select a specific system to display pertinent hardware and firmware information Select a board of a specific system to manipulate its inputs or outputs In brief this useful tool lets you verify that the system is communicating with the host and that the I O Boards are functioning properly To scan the network for DNR X 1G systems or Cubes provide a set of addresses to scan Do the following NX Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Qy ee Industries Inc Date October 2010 File DNR 12 6 1G_Chap4 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 4 44 Insta
123. s and status of all layers note that each layer status is expressed as four 32 bit words Thus the maximum size of status packets is 4 14 4 sizeof uint32 240 bytes 0x7F returns IOM status only four bytes 0x0 OxE returns status of one of the layers The status for each layer consists of four 32 bit words as follows status offsets into devob status array defineSTS STATE 0 state of the layer define STS POST 1 post status define STS FW 2 firmware status define STS LOGIC 3 logic status The first word is the state of the layer what mode of operation it is in and the lower 8 bits of the timestamp If the 10us timestamp does not change after each call the logic is in the inoperative state as state flags define STS STATE TS SH8 define STS STATE TS SH INS S TS S amp OxffffOOff TS 8 amp Oxff00 PAS Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Qy ee Industries Inc Date October 2010 File DNR 12 6 1G_Chap4 fm define POST define define define define define define define define define define define define DNR X 1G RACKtangle and HalfRACK Systems Chapter 4 54 Installation and Configuration STS STATE STICKY 0 The second word describes the status of the layer It is written when the layer enters initialization mode and remains unchanged until the next reboot STS_POST_SDCARD_FA
124. shared interrupt first The firmware sets up device driver priorities when it registers device drivers simod is a command for system initialization and module calibration simod 0 is used to initialize initial module parameters serial number option etc We do not recommend use of this command in the field simod 1 allows module calibration Different modules have different calibration procedures explained in respective sections of this document simod 3 allows you to perform factory tests this is a non destructive command WARNING Once you use the simod 0 command the module AN warranty is void 7 3 1 Setting Using the serial interface you can set up the following parameters Parameters Via Serial Interface name lt Device name gt model lt Model id gt serial lt Serial gt mac lt my ethernet address gt fwct lt autorun runtype portnum umports gt srv lt Host IP address gt ip lt IOM IP address gt gateway lt gateway IP address gt netmask lt network mask gt PAN Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 hk diiit Industries Inc Date October 2010 File DNR 12 6 1G_Chap7 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 7 84 Programming Module specific Functions udp lt udp port gt Name sets the device name up to 32 characters Model sets the device model factory programmed do not change A valid value is
125. show any flags set status flags STS LOGIC DC OOR 1UL 0 DC DC out of range IOM STS LOGIC DC FAILED 1UL 1 DC DC failed IOM also STS LOGIC TRIG START 1UL 2 Trigger event started IOM STS LOGIC TI J G STOP 1UL 3 Trigger event stopped IOM STS LOGIC CLO NOT RUNNING 1UL 4 Output channel list not STS LOGIC CLI NOT RUNNING 1UL lt lt 5 Input channel list not STS LOGIC CVCLK CLO ERR 1UL lt lt 6 CV clock error for CLO STS LOGIC CVCLK CLI ERR 1UL 7 CV clock error for CLI STS LOGIC CLCLK CLO ERR 1UL lt lt 8 CL clock error for CLO STS LOGIC CVCLK CLI ERR 1UL 9 CL clock error for CLI STS LOGIC NO REPORTING 1UL lt lt 31 Installed logic does not STS LOGIC STICKY STS LOGIC NO REPORTING PAS Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 United Electronic Industries Inc b d Date October 2010 File DNR 12 6 1G Chap4 fm w status define STS F also define STS F DNR X 1G RACKtangle and HalfRACK Systems Chapter 4 55 Installation and Configuration The fourth word contains the status of the firmware A layer operating normally does not have any flags set except STS FW CONFIG DONE which means the layer was properly configured before entering
126. ss Ranges to be Scanned ssssssssssssseeeeee eene nnns 44 4 8 Typical Screen for Analog Input Board ssesse emm 45 4 9 Displaying the Version of Your Firmware ssssessen eee 46 4 10 Update Firmware Menu ltem ssssssssssssesseseeenen ener nnne 47 4 11 Password Dialog BoX cccccceeccneeeeeeeecteee eee eitie eee eetieeee eee eeee eee enne nennen 48 4 12 Firmware Update Progress Dialog Box sesssseee emen 48 4 13 Physical Dimensions of DNR 12 ENCL Enclosure sseeee 49 4 14 Physical Dimensions of DNR 6 ENCL Enclosure see 50 4 15 System Configuration with LAN Switch sse 50 Chapter 5 PowerDNA Explorer seseseeeeee Ren 58 5 1 PowerDNA Explorer Main Window cssssssssseseeeeeme nennen 58 5 2 Prefererices oodd b ru a d bor HR E a re i reda peres 58 5 3 Address Ranges Dialog Box 0 ceccccceesseeeeeeeeseneeeeeenseneeeceeenenceeeeeeseneaeseeesseaeeeeeeneaaes 59 5 4 Edit Address Ranges Dialog Box ssssssseeeeeeene nennen nnns 59 Z Copyright 2008 Tel 508 921 4600 www ueidaq com Vers 1 5 Q e Bectronic Industries ine Date October 2010 File DNR12 6 1G_ManualLOF fm 5 5 After a Network gt gt Scan Network ccccceecceccecceceeeeeeeeeeeeeeeeceaaeaaeaeeeeeeeeeenseeeeneeesaeeas 60 5
127. start your computer if Windows gives you the option to do so Then continue with Configure TCP IP Configure TCP IP STEP 1 From the Start menu select Settings and then Control Panel Double click on the Network icon Click the Configuration tab if it is not already selected STEP 2 Inthe box labeled The following network components are installed select TCP IP TCP IP is listed at least twice so choose the one followed by the name of your second Ethernet card do not choose TCP IP gt Dial up Adapter STEP 3 Click the Properties button STEP 4 In the TCP IP Properties window click on the IP Address tab STEP 5 Make sure that Specify an IP address is selected STEP 6 Enter 192 168 100 1 for IP Address and 255 255 255 0 for Subnet Mask PAN Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Qy V1 Bectronic Industries Inc Date October 2010 File DNR 12 6 1G_Appx fm DNR X 1G RACKtangle and HalfRACK Systems TCP IP Properties STEP 7 Click on the DNS Configuration tab STEP 8 Select Enable DNS Make sure the Host and Domain information is blank TCP IP Properties STEP 9 Click on the Gateway tab Make sure the box labeled New gateway is blank A Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 United Electronic Industries Inc Date October 2010 File DNR 12 6 1G Appx fm DNR X 1G RACKtangle and HalfRACK Systems TCP IP Properties STEP 10 Click the O
128. stem DNR Series Advantages Easy to Configure and Deploy Over 30 different I O boards available Over 5 quadrillion possible configurations Gigabit Ethernet based 100 10Base T compatible Bracket kit for mounting to wall or in 19 racks Industrial quality rubber feet for solid table top mounting Passive backplane ensures extremely low MTTR Standard Off the shelf products and delivery True Real time Performance 1 msec updates guaranteed with 1000 I O Up to 6 million samples per second Use QNX RTX RT Linux RTAI Linux LabVIEW RT Flexible Connectivity 1000Base T with Cat 5 cable Supports WIFI GSM Cell networks Built in USB 2 0 slave and controller ports Compact Size 5 2506 5x 10 51 300 analog inputs per rack 384 analog outputs per rack 576 digital I O bits per rack 96 counter quadrature channels per rack 144 ARINC 429 channels per rack 48 RS 232 422 485 ports per rack Low Power Less than 13 watts per typical rack not including 1 0 AC 9 36 VDC or battery powered Stand alone and Data Logger Modes Upgradable to UElLogger 600R Upgradable to UEIPAC 600R Upgradable to UEIModbus 600R Rugged and Industrial Solid Aluminum construction 130 000 hour MTBF Operation tested from 40 C to 70 C Vibration tested to 3 g operating Shock tested to 50 g operating All I O isolated from rack and host PC Outstanding Software Support Windows Linux RT Linux Windows RT RTX VXworks and QNX operating s
129. t fwct lt autorun runtype portnum umports gt srv lt Host IP address gt ip lt IOM IP address gt gateway lt gateway IP address gt netmask lt netmask IP address gt udp lt udp port dec gt For example to set a new IP address type DQ set ip 192 168 100 100 Other parameters can be changed the same way Once parameters are set however you have to store them into non volatile flash memory DQ gt store Flash 1212 bytes of 1212 stored CRC 0x8975E34A Old 20x8975E34A Configuration stored DO After parameters are stored you should reset firmware start firmware execution from the beginning without full hardware reset as follows DO reset Stopping DaqBIOS C UEI 2001 2004 Running PowerDNA Firmware Built on 16 39 15 Oct 1 2004 Initialize uC OS Real Time Kernel v 252 Configuration recalled 3 device detected Address Irq Model Option Phy Virt S N Pri DevN 0xA0000000 2 205 1 phys 0023115 10 0 0xA0010000 2 205 1 phys 0023117 20 1 0xA0020000 2 205 1 phys 0023119 30 2 Current time 18 53 45 11 01 2004 IOM TCP IP DQ stack MAC 00 0C 94 00 59 1B To perform a full hardware reset use DQ gt reset all The full reset performs a_physical reset of the CPU and initiates the whole startup sequence FAS Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Q DU Bectronic Industries Inc Date
130. t Etherne LAN on Molheiboard Name Network Tasks A LAN or High Speed Int This connection uses the iamen Tena z F IV NW Link IPX SPX NetBIOS Compatible Transport Prot Local Area Connection Status F Intemet Protocol TCP IP Qw BH sen res i Address e Network Connections General Support internet Protocol TCP IP Properties Connection Status Connected Duration 06 45 54 Speed 100 0 Mbps ey General temate Configuration M thigfcompute is used on more than one network enter the allemate IP setifis below Automalic private IP address Uter configured IP address Activity 192 168 100 TE AL ARUM 1 Sent Received Packets 68912 122 715 Subnet mask Default gateway Preferred DNS sptve flared WINS server Alteinate WINS server Select Alternate Configuration tab Enter IP address and Subnet mask as shown Once you have this configuration in place your computer will look for the attached device on your Ethernet port during Boot Up or during a Windows Log On operation If it sees a powered on PowerDNA cube connected to the Ethernet port it will automatically switch to using the secondary IP address If the computer sees a DHCP network connected to the Ethernet port it will use the primary IP configuration and negotiate an IP address with your company n
131. t can be executed on the diagnostics port as well The following standard DAQBIOS commands are accessible on the diagnostics port whenever one or more layers are in operating mode DOCMD_ DOCMD DOCMD DOCMD D D D a DW b RCHNL sel DCHNL sel ve DOCM DOCM DOCM CHO echo DCFG read configuration new DSTS read status lected write channel lected read channel IOCTL selected ioctl low priority command SETLOCK set release port lock Commands that are capable of changing the state of the running layers will not execute NX Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Qy ee Industries Inc Date October 2010 File DNR 12 6 1G_Chap4 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 4 52 Installation and Configuration To switch a port into diagnostics mode use the DQCMD_SETLOCK command as described below int DAQLIB DqCmdSetLock int Iom uint8 Mode char Password uint32 TIP Parameters int Iom Pointer to the DQIOME structure uint8 Mode Function mode lock unlock check diagnostics char Password password string ignored and can be NULL if Mode is DOSETLOCK CHECK uint32 IP returns the IP address of the locking host if Mode is DOSETLOCK CHECK Mode can be one of the following define DQSETLOCK LOCK0 Lock IOM to host define DOSETLOCK UNLOCK1 Unlock IOM define DOSETLOCK CHECK2 Get loc
132. t this chapter several screens include graphic representations of DNR 12 systems For a DNR 6 system each screen is the same except that it includes a photo of a DNR 6 instead of a DNR 12 5 1 The Main The Main Window of the PowerDNA Explorer is shown in Figure 5 1 Window amp PowerDNA Explorer x File Network View Help FADE INL i l m Host PC i System Windows XP 2 IP 10 102 226 7 Figure 5 1 PowerDNA Explorer Main Window The Main Window is the window you see when the PowerDNA Explorer is first launched and is where you do most of your work It has four main parts the Menu Bar the Toolbar the Device Tree and the Settings panel 5 2 Menu Bar The Menu Bar contains the following menus and menu items 5 2 1 File Menu Preferences brings up the preferences dialog The preferences dialog allows you to specify the network timeout interval This is the length of time PowerDNA Explorer will wait for response from a CPU NIC Core Module before giving up with an error It defaults to 100 milliseconds Network timeout h 0 msec Figure 5 2 Preferences FAS Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Q DU Bectronic Industries Inc Date October 2010 File DNR 12 6 1G_Chap5 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 5 59 PowerDNA Explorer Exit exits the application If there are unsaved device settings changes you are prompted for confirmation 5 2 2 Network
133. ta transfer rate up to 6 megasample per sec 16 bit samples DMAP O mode Processor CPU update 1000 I O channels analog and or digital in less than 1 millisecond guaranteed Freescale 8347 400 MHz 32 bit Memory Status LEDs Environmental Temp operating Temp storage 128 MB not including on board Flash Power supplies within spec One second system heart beat Attention Read Write Power Communications Active Tested to 40 C to 70 C 40 C to 100 C Humidity 0 to 95 non condensing Vibration IEC 60068 2 64 10 500 Hz 3 g rms Broad band random IEC 60068 2 6 10 500 Hz 3 g Sinusoidal Shock IEC 60068 2 27 Physical Dimensions DNR 12 series Voltage Power Requirements 50 g 3 ms half sine 18 shocks at 6 orientations 50 g 11 ms half sine 18 shocks at 6 orientations 5 25 x 6 2 x 17 5 3U in a 19 rack 9 36 VDC AC adaptor included Fuse Internal 10 A Power Dissipation Power Monitoring 1 O board power 13 W at 24 VDC not including I O boards All internal power supplies monitored to 1 accuracy All PS voltages may be read by host LED annunciators indicate out of range Input current Monitored by host LED indicates overcurrent Input voltage Monitored by host LED indicates out of range Figure 2 2 DNR 12 1G Technical Specifications Tel 508 921 4600 Date October 2010 Vers
134. te October 2010 File DNR 12 6 1G_Chap4 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 4 46 Installation and Configuration 4 5 4 Updating Firmware in a DNR CPU 1000 CPU module stores configuration data along Firmware with a user application user app is compiled on a host PC Updated firmware is periodically released to introduce new features and to improve the performance of existing features Updated releases of the firmware are bundled with the entire PowerDNA Software Suite available for download at any time from the UEI web site www ueidaq com CAUTION If you update the firmware in a DNR CPU 1000 be sure to use the PDNA Explorer from the same release as the new firmware After installing the PowerDNA Software Suite browse to the installation s Firmware directory e g C Program Files UEl PowerDNA Firmware The directory may contain MTTTY updated firmware installation instructions Firmwarelnstall html and two sub directories containing the firmware Choose the sub directory corresponding to the architecture of your system for the DNR X 1G this is the Firmware_PPC sub directory and the rom image file with extension MOT NOTE Before updating the firmware of a system check the version to determine which update method to use a Turn on power to the DNR POWER DC module b Connect the system to its network c Start PowerDNA Explorer on the Microsoft Windows desktop from Start Programs UEI P
135. ternal DIO line EXTO 1 lines are assigned to DIOO 1 lines when DIO lines are in the input state DgAdvAssignlsoSync This function selects signal assignment for INT lines This function allows selecting what signal from isolated side of the module logic will be assigned to INTx lines Signals can be selected from internal clock sources and SYNCXx lines DqAdvAssignSyncx This function selects a signal for each of the SYNCx lines When a SYNC line is selected it switches to the output state All other modules listen to this command on the system bus and release that SYNC line from use switch to the input mode This organization prevents two modules from driving the same line DgAdvWriteSignalRouting This function writes and activates selected signal routing This function transfers created configuration to the cube and activates it Cube sends current synchronization configuration as a reply Note that to take advantage of using external clocks for the module clock and or trigger the source should be selected as external This means that in clocking configurations the following bits should be set up RC1 external CL clock is selected DG external start trigger is selected external stop trigger is selected 92 PAS Copyright 2010 United Electronic Industries Inc b d Tel 508 921 4600 Date October 2010 www ueidaq com Vers 1 5 File DNR 12 6 1G_Chap7 fm DNR X 1G RACKtangle and HalfR
136. the Network and Dial up Connections window double click on the Local Area Connection 2 icon STEP 3 In the Local Area Connection 2 Status window click Properties ax General r Connection Status Connected Duration 02 25 00 Speed 10 0 Mbps p Activity Sent ap Received Ca Packets 768 458 1 Properties Disable Lote STEP 4 Click once on Internet Protocol TCP IP Then click Properties Local Area Connection Properties General Connect using Hj AMD PCNET Family PCI Ethermet Adapter Components checked are used by this connection ivi Bl Client for Microsoft Networks Vi Y7 Intemet Protocol TCP IP wa Uninstall Properties STEP 5 Select Use the following IP address and type 192 168 100 1 In the Subnet mask box type 255 255 255 0 Leave the Default Gateway box blank Internet Protocol TCP IP Properties Generi You can get IP vettings assigned automatically d your network upp thes copay CRPAT pou needs so poa nabad aar vetri Use the following IP address IP oddone d e Scheel nad ara ee the appropriate I Xx Obtain an IP address automaticaly NX Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 We DU Bectronic Industries Inc Date October 2010 File DNR 12 6 1G_Appx fm STEP 6 STEP 7 STEP 8 E Configuring a Second Ethernet Card Under Windows NT STEP 1 STEP 2 STEP 3
137. the following STEP 1 From the Start menu select Control Panel and click Printers and Other Hardware STEP 2 From the menu on the left click Add Hardware and follow the on screen instructions NOTE We recommend that you allow Windows XP to search for and install your Ethernet card automatically If Windows XP does not find your Ethernet card you will need to install it manually by following the manufacturer s instructions Once your Ethernet card has been installed continue to the next section B Configure TCP IP STEP 1 From the Start menu select Control Panel STEP 2 Under the heading Pick a Category click Network and Internet Connections STEP 3 Under pick a Control Panel icon click Network Connections STEP 4 If you see an icon under LAN or High Speed Internet heading for your second NIC skip ahead to step 10 STEP 5 Ifthere is no icon under LAN or High Speed Internet for your second NIC proceed to step 4 STEP 6 From the menu on the left click Create a new connection to launch the New Connection Wizard STEP 7 Click Next and proceed to the Network Connection Type window NX Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Qy ee Industries Inc Date October 2010 File DNR 12 6 1G_Appx fm DNR X 1G RACKtangle and HalfRACK Systems STEP 8 Select Connect to the Internet and click Next New Connection Wizard Network Connection Type What do you want to do Connect t
138. the front of the enclosure Then attach the flanges to the rack with bolts The DNR 6 1G can be mounted in the same ways as the DNR 12 1G except for the 19 inch rack mounting because the DNR 6 enclosure is not as wide as the DNR 12 Refer to UEI for other accessories needed for this type of installation 4 6 1 Physical The DNR 12 ENCL enclosure used in a DNR 12 1G system is compatible with Dimensions Specification EIA 310 C for 19 Rack Mounting Equipment and is designed to occupy 3U units of vertical space where 1U is 1 75 The physical dimensions of the DNR 12 ENCL enclosure are shown below in Figure 4 13 18 31 in lt lt A p CD gt Ww co e3 N e p 5 50 in 17 50 in Note For wall mounting align flanges flush with rear of enclosure For rack mounting align flanges with front of enclosure Figure 4 13 Physical Dimensions of DNR 12 ENCL Enclosure NX Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Qy ee Industries Inc Date October 2010 File DNR 12 6 1G_Chap4 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 4 50 Installation and Configuration Except for the width the DNR 6 ENCL enclosure used ina DNR 6 1G system is compatible with Specification EIA 310 C for 19 Rack Mounting Equipment and is designed to occupy 3U units of vertical space where 1U is 1 75 The physical dimensions of the DNR 6 ENCL enclosure are shown below
139. tion describes the basic modules included in every DNR 12 1G system CPU NIC and the CPU NIC module the DC DC power module buffer module and I O I O Modules modules IempO Sensor on backplane Temp1 Sensor on backplane o o o o o lel ge e lel o o p p ap p 31 FF p p ap p pF 4p q V V y eo Naa uillejiej ej e je 9 zal jejej ejeje e5 iizilsisisisjsusiss2pgqsilsbsisiisiss O o le ol lo fe o a 2 5 le o o fe OG az z miz 2 O m 2 2 23 1 31 TF 4 fl IF 4 SS Sa EP it 1 34 f 124 IE o L oFr o e Ex o a l RS 232 AE mS Status Excess Serial Port Ow Status ds LEDs EO O L Connector Oss LEDs Fan sO Oxz DB 9 O sid Syn C Sync Reset oO hes 7 12 Conn PB m Switch NIC2 Port On off SD Card Hh DB 37 m Slot j e NIC1 Port Connector rove USBB USB 2 0 onn ine NN USB o N Controller c Industries Port D PowerDNR PowerDNR Typical DNR POWER DC DNR CPU 1000 PowerDNR DC DC Module CPU NIC Module I O Module LEDs Single Slot Model ATT Indicates error when red R W Flashes when bus is active COM Flashes when SD Card is read written PG Indicates presence of valid power
140. urce as a time base Al 201 supports the CL clock only where the time between consecutive channel readings is calculated by the rule of maximizing setup time per channel If you d like to clock CL clock from an external clock source such as SYNCx line set the DO LN Tel 508 921 4600 Date October 2010 CLCKSRCI flag as well Vers 1 5 File DNR 12 6 1G Chap7 fm www ueidaq com DNR X 1G RACKtangle and HalfRACK Systems Chapter 7 89 Programming Module specific Functions DQ LN CVCKSRCO selects the internal conversion clock CV source as a time base Setting CV clock allows having an equal time period between conversions of different channels It is mostly used when you are interested in a phase shift between channels You can select either the CL or CV clock as a time base If both clocks are selected the CL clock is taken as a time base and the CV clock determines the delay between converting channels i e setting time DO LN STRIGEDGEO DQ LN STRIGEDGE1 define the start trigger edge and source The source can be either software command or external trigger edge DO LN PTRIGEDGEO DQ LN PTRIGEDGEI define the stop trigger edge and Source The source can be either software command or external trigger edge DO LN TSCOPY copy timestamp at the end of every channel list DQ LN MAPPED set this flag to declare DMap mode DO LN STREAMING set this flag to declare ACB
141. ustries Inc Date October 2010 18 Vers 1 5 File DNR 12 6 1G Chap2 fm 2 6 DNR CPU NIC PULLUPS CPU NIC 3 3V 24V DNR POWER DC Module Copyright 2010 United Electronic Industries Inc li O SLOTS poorer ADURICTRE DNR BUFFER E 6 B CLOCK DIST 1 2V AND 1 5V DNR X 1G RACKtangle and HalfRACK Systems Chapter 2 19 The DNR 12 1G RACKtangle System The input current and all output voltages including the 2 5 3 3 and 24VDC from the NIC module plus signals from the two temperature sensors mounted within the enclosure are input to a 24 bit delta sigma A D converter Except for Vin the voltage sources use 1 23 1 dividers on the front end Vin uses a 1 45 3 divider Figure 2 15 shows the interaction of modules within a DNR 12 ENCL Enclosure when the DNR BUFFER module is used DATE BOS PULLUPS IE Figure 2 15 Functional Block Diagram of DNR 12 ENCL As shown above the I O slots are divided into two groups 0 to 5 and 6 to OxB OxC for the DC Power Module is included with the 0 to 5 group The DNR BUFFER board is located at the center of the enclosure which is also at the center point of the ADDR CTRL bus The DNR CPU 1000 module is also located at the center of the enclosure and the center of the data bus to minimize bus delays The CPU addresses I O modules and transmits clock ticks through the Buffer Board which controls the Addr Ctrl and clock lines to the modules Temp
142. ut channels allowing you to select O or 1 The DI 401 module just has Reference and 0 and 1 Level controls and Input tab The DO 402 module just has Output Initialization and Shutdown tabs no Reference value or Level sliders The DIO 403 module is different because it groups 8 bits at a time into ports and three ports into two channels For the sake of abstraction in PowerDNA Explorer we ll call all the ports channels NX Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Qy ee Industries Inc Date October 2010 File DNR 12 6 1G_Chap5 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 5 68 PowerDNA Explorer lolx 2 PowerDNA Explorer File Network View Help PODANE Host PC 9 OM 20977 4 Mode DIO 403 Fem SSS SS ESL SLE SS SS SLM lt 0 DIO 403 fo D In Out 48 channel 6 ports of 8 BA ESA SW 0021391 i Mfg Date Nov 30 0002 Hl g Cal Date Nov 30 0002 Vi Enabled Figure 5 15 Example of DIO 403 Inputs amp PowerDNA Explorer ml x File Network View Help Xe e S Hast PC 2 x 9 lom_20977 Model DIO 403 RIESESESESESESESEE ES ESESES EIS IEES 0 DIO 403 Info D In Out 48 channel 6 ports of 8 AA E SIN 0021391 Mfg Date Nov 30 0002 HU a Cal Date Nov 30 0002 vi Enabl
143. y existing devices that are missing will be removed from the tree unless you have made unsaved changes to such a device s configuration in which case it will be marked in the tree as missing Reload Config re reads the configuration of the current device selected in the Device Tree If you have made changes to the settings in the settings panel for the current device Read will replace those settings with the current settings for the device after prompting for confirmation Store Config writes the changed settings for the currently selected device to the device The button is disabled for devices that haven t been modified Store All Configs writes all of the changed device settings to the devices The button is disabled if no devices have been modified Read Input Data is enabled when the currently selected device is an input device board It reads the current input values to the device and causes them to be displayed in the settings panel Update Firmware loads a firmware update file to all connected DNR X 1G systems if Host PC is selected It updates only one DNR X 1G system when a specific unit is specified More details about this can be found in the section Updating Firmware in a Version 2 0 PowerDNA system Note that writing certain configuration changes to a PowerDNR system running firmware 2 0 16 will bring up a password dialog box More information about passwords can be found in the Interfacing to the CM module using a Seri
144. ystems VB VB NET C C C J MATLAB LabVIEW DASYLab OPC ActiveX support Figure 3 2 DNR 6 1G HalfRACK Product Features FAS Copyright 2010 Tel 508 921 4600 www ueidaq com Vers 1 5 Q DU Bectronic Industries Inc Date October 2010 File DNR 12 6 1G_Chap3 fm DNR X 1G RACKtangle and HalfRACK Systems Chapter 3 25 The DNR 6 1G HalfRACK System 3 4 DNR 6 1G Each DNR 6 1G enclosure contains a DNR POWER DC Power Module with HalfRACK status indicating LEDs and a local ON OFF switch and each I O module is System provided with a mechanical lever see Figure 2 6 on page 9 for quick ejection Enclosure and insertion of the board In addition each DNR 6 1G system enclosure also contains its own GigE CPU and two Network Interface Control NIC modules one for controlling up to 6 I O modules mounted in the enclosure and another for diagnostic functions The module specific I O boards are functionally identical to the corresponding modules for the PowerDNA Cube The only differences between the two types relate to the mounting arrangements Carrying m un Handle Cooling Fans 9 Backplane if a with 2 temp sensors Guides for Power lt T CPU and I O modules 0 oal B f 9 f 0 f i i C3 COE keg Rubber feet 4 for tabletop mounting Figure 3 3 Typical HalfRACK DNR 6 ENCL Enclosure Exploded View As shown in Figure 3 3 and Figure 3

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