A/D Converter Analog Aspects AP2428.01
Contents
1. Varer and VAGNnD Application Note 25 V 1 0 2001 05 ss Infineon AP2428 01 Cofino C500 C166 Microcontroller Families Analog Input ANO ANy 5 4 2 Cycle Time The cycle time teycjen is the duration from the start of a conversion to the next conversion start of the same analog channel The figure below shows the relation between the conversion time of an analog channel and the cycle time tcYCLEn o ten Conversion time of analog channel n tcycLen Cycle time of analog channel n chn analog channel n Figure 15 Cycle Time For continuous conversion mode of a channel the conversion time te can be equal to the cycle time teycj En The cycle time of consecutive conversions is important for the calculation of the voltage on Cex7 at the start of next conversion The voltage difference between the analog source Vp and the analog input ANx at the start of a conversion should be 0 V or negligible The recommendation is tevcLE 7 6 T3 ts Note After 7 6 T3 the remaining deviation from Vp is 0 049 of the assumed Error Ayx for Vs ts Application Note 26 V 1 0 2001 05 ss Infineon AP2428 01 ofie C500 C166 Microcontroller Families Analog Input ANO ANy 5 4 3 Calculation Example with 0 pF lt Cexy lt 2 1 Cain The assumed values used in the example are CAIN 33 pF ts 1 28 HS VAREF Vo 5V Rain 250 Q tc 7 8 US r 10 10 bit resolution Cext 200 pF Erro2. 2 1 j Cain DAG Be ae a ee aa E 28 5 5 1 External Capacitance CgyxT 20 eee eee eee 28 5 5 2 Cycle Time tCYCLEn aaa cirai deen time UN nee kahaba Sah GN ae ied eather ok mak TR Db in 28 5 9 3 Cutoff Frequency fg a mat gow cont AG one EG nile wont dated 30 5 5 4 Calculation Example with Cgxr gt 2 1 CAN 2 eee eee 30 5 6 Rasac Calculation with Cpp 0pF 4 0 a a ka a a WD GG on 32 5 6 1 Resistance of the Analog Source Raspc eee 32 5 6 2 Calculation Example with Cex7 OpF 0 33 5 6 3 Calculation Example with the Formula in the Data Sheet 34 Application Note 3 V 1 0 2001 05 we Infineon AP2428 01 Cofino C500 C166 Microcontroller Families 6 Reference Voltage VAREF and VAGND AP AA PAA 35 6 1 Sources for the Voltage Reference 0A aa 36 6 1 1 Supply Voltage of the Microcontroller 20000000 36 6 1 2 External Voltage Reference 0 0 0 000 c cece eee eee 37 6 2 Rarer Calculation Including an External Capacitance 38 6 2 1 Calculation Example 2 004 42 dee ABAKA DA de KALMA AAG same ets eee 40 6 3 Rarer Calculation based on the Formula in the Data Sheet 41 6 3 1 Calculation Example 4a on ah ctdevadica bette AKNG GAGANA ALA Be 43 6 4 Ratiometric Configuration 2402c00esee de eee NA KABANG KANG awd aos 44 7 Overload and Leakage Current 0 00 eeeeuee 45 7 1 Leakage Current 0 0 cece teens 45 7 1
3. corresponds directly to the voltage level of the connected analog input channel The digital value is found successively starting from the most significant bit down to the least significant bit The comparator is used to decide whether the actual voltage of the capacitor C is below or above the voltage stored in the hold capacitance The charge redistribution phase is finished after 10 steps of successive approximation The conversion C net for a 12 bit A D converter consists of C44 to Co and 12 steps are required The conversion C net for a 8 bit A D converter consists of C7 to Cg and 12 steps are required 3 3 Calibration Phase The conversion accuracy depends on the precision of the conversion C net and the offset voltage of the comparator In order to correct the errors that are introduced through process variations and offset voltage an additional C net the calibration C net is used together with a calibration control logic A detailed description of the calibration phase is shown in the chapter 4 Calibration Mechanism 3 4 Write Back Phase During the write back phase the result of the successive approximation is copied to the result register ADDAT The duration of the write back phase is 4 TCL During the write back phase the conversion C net is precharged with approximately Varner 2 Note Because of parasitic capacitances caused by the pads and the analog multiplexer the precharge voltage at the pins can differ from VREF
4. respectively is the condition to determine the correct values for Rasrc Cext sample time and cycle time of a system The worst case voltage deviation for the system is the maximum voltage difference between the precharge voltage of Cam approximately Vapep 2 and Vo at the beginning of the sample phase This case is given for Vo Varer Of Vo Vacnp Figure 10 shows the absolute voltage difference between Vo and Car Vo Varer 21 at the beginning of the sample phase The formulas in this ApNote are all related to the possible absolute maximum Vo Varer The result can also be transformed to Vo Vagnp Voltages used in the calculations are all referred to Vagnp Vo Varer 2 Varer 2 V AREF VAGND Figure 10 Voltage Difference between Vo and Can Vo Varer 21 at the Start of the Sample Time Note The assumed error Erroran used in this chapter Analog Input ANO ANy for the calculation examples is referred to the allowed maximum input voltage at ANx Vainx Varer For input voltages at ANx smaller than Vapep the additional inaccuracy at Vamy is proportional less than the value of Erroran used in the example calculations The real additional inaccuracy at Va is Erroranx_real Vainx VaREF Erroranx with the condition VAGND lt VaINx VAREF Application Note 19 V 1 0 2001 05 ss Infineon AP2428 01 ofinn C500 C166 Microcontroller Families Analog Input ANO ANy 5 3
5. 8 bit resolution Cext gt 255 Cain 10 bit resolution Cext 5 1023 Cain 12 bit resolution Cext gt 4095 Cain The condition Cex gt 2 1 Cain allows a free choice of the sample time tg without consideration of the resistance of the analog source Raspc but Rasrc has a direct influence on the cycle time teycLen of the conversion 5 5 2 Cycle Time tcycLen The calculation of the cycle time takes into account that the external capacitor is not totally charged to the voltage of the analog source Vo worst case Vp Vapep Or Vo VaGnp but a small voltage rest Vp is missing See Figure 16 With the condition Cay lt lt Cexr the formula for V can be simplified Va Cain Varer Varer 2 Cain Cext Va Can Varner 2 Cext Application Note 28 V 1 0 2001 05 we a aga AP2428 01 technologies C500 C166 Microcontroller Families Analog Input ANO ANy The condition Va Vp lt Errorany with Vp Varer Ve tcycien is based on Figure 16 The charge curve V t of the capacitor Cex7 via the resistance of the analog source Raspc IS t T3 Velt Varer Erroranx Ee With an assumed maximum error of LSB 2 Errorany Varer 2 2 and with Ta Rasrc Cexr the formulas result in the relation Cext teycLe 2 Rasrc CexT n gt Cex1 2 Can This formula is only valid for Cexr gt 2 Cain VAIN loYvcLen gt t teyolen Vo VAREF l l Ma a aa i Error ANx Sam
6. Charge Flow during Sample Time The input impedance of the A D converter is mainly capacitive Can with a small resistive Ra part This capacitance however applies only to the selected analog input pin ANx during the sample time During the remaining time the inputs are extremely high impendance e g typical leakage currents are in the range of some 10 nA See specification in the Data Sheet Input leakage current of the ADC During the sample phase two different sequential processes are running First Cay is charged from Cex7 and the voltages at Cam and Cexr get the same value Secondly the common voltage at Ca and Ceyz is adjusted to Vp via the resistance of the analog source Raspc Depending on the performed phases of the A D converter different time constants T have to be considered e Ti Time constant at the beginning of the sample time It contains Cain Cext and Rain e To Time constant during sample time It contains Cap Cexr and Rasrc e Ts Time constant during and after charge redistribution phase It contains Cex7 and Rasrc 5 3 1 Charge Balance between Cam and Cex7 The electrical model for T4 is shown in Figure 11 The voltage at Cay before switch Sample is closed is approximately Vapep 2 because of precharging Ca at the end of conversion The voltage at Cexy is nearly V depending on the cycle time of the conversion Rain Sample VAINx Cext Voain VAREF 2 Cain Figure 11 Electrical Model
7. Error INLE anaana 11 3 Principle of Conversion aana 12 3 1 Sample Phase aunnna aunan 12 3 2 Charge Redistribution Phase anaana cc eee 13 3 3 Calibration Phase n PAA AP 13 3 4 Write Back Phase eee an ask oa KAR KPA RK he ROR re ae HO NG ae 13 4 Calibration Mechanism Error Correction 15 4 1 Calibration Principle st secur ceeuedation AT 15 4 2 Reset Calibration cacwt ances teens wee PP AA Sie eee ews 15 4 3 Normal Calibration paaa NA KAN DE KG Tae ee heat ABAYA sam TIGA HANYA 16 4 4 Disturbance Filtering pang Oma wa PAG KA pee eee KA DADING LARA RAGE 16 5 Analog Input ANO ANy 222 0 0 0 ee 17 5 1 Electrical Model of the A D Converter Input 04 17 5 2 Accuracy at Sample Time 00 0 cee eee ees 19 5 3 Charge Flow during Sample Time 4 00 e eee 20 5 3 1 Charge Balance between Cap and Ceyt aaa 20 5 3 2 Charge of CAIN and CExT via Rasrc haba ee alee NONA NG ee Gee 22 5 4 Rasrc Calculation with 0 pF lt Ceyt lt 27 1 CAN 23 5 4 1 Charge Redistribution Time 0 0 eee 25 5 4 2 Cycle Time seis cise eee ok ee hd eek na ae hak Oo Seed ee ee AA 26 5 4 3 Calculation Example with O pF lt Cex7 lt 21 1 Can 27 5 4 3 1 Resistance of the Analog Source Raspc 27 5 4 3 2 Cycle Time tCYCLEn fe ee ee ae Oe ee ae ae gee ee ae aa 27 5 5 Rasrc Calculation with Cext gt
8. O a l i l LSS SS tcycLen ts Sample time tc Conversion time tcycLen Cycle time of channel n Ti To T3 Time constants Vo Voltage of the analog source tcr Charge redistribution time conversion phase VA Voltage jump at the start of the sample phase Errorany Voltage deviation between sampled voltage and voltage of the analog source Figure 13 Voltage Waveform at ANx Application Note 24 V 1 0 2001 05 ss Infineon AP2428 01 ofinn C500 C166 Microcontroller Families Analog Input ANO ANy 5 4 1 Charge Redistribution Time During the charge redistribution time the Sample switch is open and the external capacitance Cre yz is charged via the resistor of the analog source Rasrc Rasrc Vo Cext Figure 14 Electrical Model of the A D Converter during T3 The time constant during and after charge redistribution time is T3 T3 Rasro CEXT While the external capacitance Cpexr7 is charged via Rasprc the A D converter performs the successive approximation charge redistribution This is the transformation of the analog voltage into a digital value The reference for the transformation is the reference voltage at pin Varer referred to Vagnp It is very important for an exact conversion result to hold the reference voltage and the reference ground on a constant level during the charge redistribution time More details can be found in the chapter Reference Voltage
9. Raper between voltage reference Vpp and input Varer Of the A D converter is Rarer lt VERRoR lAREF RAREF lt 1 22 mV 21 UA Note In case of an overload condition it is possible that Raper has to be increased to limit the overload current to the specified values If that value of Raper exceeds the demanded error of the system an external diode between Varer and Vpp can reduce the overload current See Figure 19 Application Note 40 V 1 0 2001 05 Infineon AP2428 01 Cofino C500 C166 Microcontroller Families Reference Voltage VAREF and VAGND 6 3 Rarer Calculation based on the Formula in the Data Sheet The calculation of Rarer in the Data Sheets of the C500 C166 Family is based on the assumption that there is no external capacitance between Vapep and Vacnp The electrical model for the calculation is shown in the figure below Voltage A D Converter Reference VERROR Comparator I AREF Vinet RAREF INT Var VAREF VusB nversion 3 Co NN Control al Central Analog Ground Figure 21 A D Converter during Conversion Phase without C AREF During charge redistribution time successive approximation all capacitors of the A D converter are charged with Vapgp 2 and compared with the sampled voltage from analog input ANx The successive approximation is started with the MSB and finished with the LSB The capacitor of the MSB needs most charge from the vo
10. cycle time the internal C net is disconnected from the analog source Therefore no capacitance has to be charged via Ragpc until the start of the next sample time Application Note 32 V 1 0 2001 05 Infineon AP2428 01 Cofino C500 C166 Microcontroller Families Analog Input ANO ANy 5 6 2 Calculation Example with Cex7 OpF The calculation example gives a rough estimation for the allowed maximum of Ragpc if Cexr7 is nearly zero pF The assumed values used in the example are Cain 33 pF ts 1 28 US VAREF Vo 5V Rain 250 Q tc 7 8 ps r 10 10 bit resolution Cexr 0pF Error ANx 0 5 LSB V AREF 2048 2 44 mV The calculation results in the value for Rasrc with V Vaper 2 Rasrc ts Cain In Vaq Erroranx Rain Rasrc 1 28 us 33 pF In 2 5 V 2 44 mV 250 Q Raspe 5345 Q The table below includes the maximum values for Raspc and different sample times with the assumed values of the example Table 6 Maximum Values for Rasrc and sample Times ts Cexr 0 pF ts Us 1 2 3 4 5 6 7 8 9 10 Rasrc KQ 4 1 8 5 12 9 17 2 21 6 26 0 30 4 34 7 39 1 43 5 Note The leakage current specified in the Data Sheet can have an influence to the accuracy of the analog input voltage when the values of Rasrc exceeds a certain limit This limit depends on the allowed inaccuracy referred to Vain which is given by the system demands S
11. explicitly in the Data Sheet but implicitly in the formula for the calculation of the internal resistance of the analog source Rasrc The sample switch represents an analog switch closed only during sample time The multiplexer connects the selected analog input ANx with the internal conversion C net The external capacitance Cexy can be a real external capacitor for noise reduction or only the parasitic capacitance caused by the signal line between analog source and A D converter input The analog voltage source is represented by an ideal voltage source Vp and a series resistance Raspc Application Note 17 V 1 0 2001 05 Infineon technologies AP2428 01 C500 C166 Microcontroller Families Analog Input ANO ANy Analog Source Central Analog Ground Figure 9 Block Diagram of A D Converter and Analog Source Application Note V 1 0 2001 05 ss Infineon AP2428 01 Cofino C500 C166 Microcontroller Families Analog Input ANO ANy 5 2 Accuracy at Sample Time As already described in chapter Principle of Conversion a total conversion is divided in two phases the sample phase and the charge redistribution phase The total accuracy of the A D converter result depends on the TUE the accuracy of V apep and the voltage level difference between analog source Vp and Vgajin Erroran at the end of the sample phase A detailed consideration of the voltage level at Cay or ANx
12. for the quantization uncertainty of 0 5 LSB which is a natural error and inherent to each A D converter The quantization step size is 1 LSB Vaper 2 According to the Ideal Transfer Curve 1 the first digital transition from 0 to 1 occurs at the analog value of 0 5 LSB That is why the first step width of the Ideal ADC Transfer Curve 2 is 0 5 LSB and the last step width is 1 5 LSB The inherent quantization error in relation to the analog input voltage is shown in Figure 2 The total unadjusted error includes all A D converter related inaccuracies like production process deviations and internal noise The TUE consists of offset error gain error DNLE and INLE but it is not simply the sum of individually measured errors Since some errors of the ADC like offset and gain error can compensate each other the TUE can be far less than the absolute sum of all individual errors Figure 1 shows the definition of the TUE in relation to the Ideal ADC Transfer Curve 1 The real result of the A D converter is in the range of Ideal ADC Transfer Curve 2 TUE This area is shaded in Figure 1 and is between both TUE related to ideal ADC Transfer Curves 3 and 4 Application Note 6 V 1 0 2001 05 we a aga AP2428 01 technologies C500 C166 Microcontroller Families Transfer Characteristic and Error Definition Digital Output Ideal Transfer Curve TUE related to ideal Transfer Curve TUE related to ideal i 2 ADC Tra
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14. input for the A D converter Reference ground for the A D converter Voltage at the analog input ANx Voltage at the internal C net Charge curve of Ceyz for a total cycle Voltage of Cexy at the end of a total cycle Supply voltage Voltage at RAREF Maximum voltage of an analog signal in case of a fatal system error Leakage voltage at Rasrc Voltage at the internal MSB of the C net Comparator voltage during conversion of MSB Comparator voltage after 2 ipc Missing rest voltage at the end of a conversion cycle Voltage reference Digital GND Voltage during sample time Voltage at the end of sample time Voltage of the analog source Voltage jump at the beginning of the sample time VAREF VAGND VANx VGAIN Vet VeltcycLE VDD VERROR VERR_max VLeak VMSB Vussit Vusp 2tgc VR VRF Vss Vs t Vs ts Vo VA Application Note AP2428 01 C500 C166 Microcontroller Families Used Short Cuts 53 V 1 0 2001 05 Infineon goes for Business Excellence Business excellence means intelligent approaches and clearly defined processes which are both constantly under review and ultimately lead to good operating results Better operating results and business excellence mean less idleness and wastefulness for all of us more professional success more accurate information a better overview and thereby less frustration and more satisfaction Dr Ulrich Schumacher http www
15. is degraded by the involved external elements which are connected to the analog input ANx and to the reference voltage Vaper It is the task of the system designer to keep the inaccuracies caused by the external circuits as low as possible This application note provides the necessary basic information to optimize the external circuits of the A D converter Application Note 5 V 1 0 2001 05 we Infineon AP2428 01 Cofino C500 C166 Microcontroller Families Transfer Characteristic and Error Definition 2 Transfer Characteristic and Error Definition The following diagrams show the ideal transfer characteristic of an A D converter and the error definition for the different kind of errors e Offset error e Gain error e Differential nonlinearity error DNLE e Integral nonlinearity error INLE The total unadjusted error TUE is specified in the Data Sheets of the C500 and C166 microcontrollers 2 1 Ideal Transfer Characteristic Figure 1 defines the ideal transfer characteristic for an A D converter The Ideal Transfer Curve 1 transfers each input to an output The Ideal ADC Transfer Curve 2 includes a quantization error since all analog input values are presumed to exist they must be quantized by partitioning the continuum into discrete digital values All analog values within a given range quantization step are represented by the same digital value which corresponds to the nominal mid range value That is the reason
16. of the A D Converter during T4 When switch Sample is closed then a charge balance between Cay and Cexz is done with the time constant T See Figure 11 Figure 13 presents the corresponding waveform at ANx Application Note 20 V 1 0 2001 05 Infineon AP2428 01 Cofino C500 C166 Microcontroller Families Analog Input ANO ANy _ Cain Cext Tr RAN CANT The possible maximum value is T 8 25 ns Can 33 pF and Ceyz infinite because Ra and Can are fixed values of the A D converter For the calculation of the sample time which is in the range of some us the duration of time constant T4 is in most cases negligible after 7 6 T the voltage error is less than 0 5 LSB For typical values of 7 6 T see Table 1 Table 1 Values for 7 6 T Can 33 pF and Ran 250 Q Cext 1 pF 10 pF 100 pF 1nF 10 nF 100 nF 1 WF 7 6 T 1 84ns 14 58 ns 47 14 ns 60 70 ns 62 49 ns 62 68 ns 62 70ns The charge balance between Ca and Cex7 causes a voltage jump V at the analog input ANx Depending on the voltage on ANx when the sample phase starts the voltage can be increased or decreased The example of Figure 13 uses the worst case Vo Varer At the end of 7 677 the voltage at ANx is reduced or increased by the value V with an accuracy of 0 5 LSB The charge balance between Cexy and Cain results in the formula for V y Cain Vo Voan a Cain Cext Table 2 Typical Values for th
17. steps The same calibration C net is used for both the offset and the linearity calibrations During offset calibration the corrective charge in order to zero adjust the comparator is determined During linearity calibration for each of the binary weighted capacitors of the conversion C net a correction value with respect to the sum of the remaining Capacitors is determined The results of the calibration are stored in the calibration RAM During normal conversion the stored values are used to correct the measurement For this purpose the calibration control unit is used to calculate the appropriate combination of the calibration capacitors 4 2 Reset Calibration After a reset the contents of the calibration RAM is cleared and the A D converter automatically starts an initial full calibration sequence power up calibration Both the offset and the linearity deviations are adjusted This calibration sequence has a duration of 3328 tgc 0 66 msec fepy 20 MHz with the reset values of register ADCON During the first quarter of this calibration sequence a coarse adjustment with steps from 0 5 LSB down to 0 1 LSB is performed which becomes more precise during the following three quarters of the sequence with calibration steps of 0 03 LSB This scheme guarantees a very fast reduction of the offset and linearity error Application Note 15 V 1 0 2001 05 Infineon AP2428 01 Cofino C500 C166 Microcontroller Families Calib
18. the A D converter the external capacitance Cexy7 and the resistance of the analog source Raspc form an RC lowpass filter which has the charging function Vg t In normal systems the sample time ts gt gt T4 therefore T is neglected in the formula for V t The waveform is shown in Figure 13 t T2 Vo t Varer Va e The voltage on ANx at the end of the sample time can also be described with the formula Vs ts The Erroran describes the maximum allowed deviation between the voltage on ANx and Vp when the sample time is finished An assumed Erroray of 0 5 LSB is equivalent to 9 76 mV 2 44 mV 0 61 mV Varer 5 V and 8 bit 10 bit 12 bit A D converter resolution Vo ts Varer Error anx Now it is possible to calculate the maximum value of the analog source resistance Rasrc The formula for Rasrc assumes that Ran 0 Q ts Cain Cexr In R ASRC Va Error any The formula is only valid for V Errorany gt 1 An assumed maximum Erroran LSB 2 leadsto Ceyz lt 2 1 Can Depending on the A D converter resolution the relations between Cex7 and Car for the calculation of Raspe are 8 bit resolution O pF lt Ceyt lt 255 CAN 10 bit resolution 0 pF lt Ceyz lt 1023 Cain 12 bit resolution 0 pF lt Cex7 lt 4095 Cain Application Note 23 V 1 0 2001 05 ss a aga AP2428 01 technologies C500 C166 Microcontroller Families Analog Input ANO ANy mt tg o tiep ee ex l D
19. the charge redistribution phase and also during the calibration phase each group of capacitors from the C net is individually switched to either Varer or VAGND Because of this switching and the according charge transfers in the C net the A D converter requires a dynamic current at pin Vapep Thus the resistance of the voltage reference source has to be low enough to supply the current for the charge redistribution and calibration phase The external circuit at Varer has a direct influence to the required resistance of the voltage reference If an external capacitance Carer between Varer and Vagnp is used then the voltage reference has to supply a small continuous current to charge the external capacitor The necessary peak current during the charge redistribution phase is supplied by the external capacitance Ceyz The continuous current and the charge duration teycLe have to be high enough to fill the external capacitance to a sufficient voltage level before the next charge redistribution phase starts If there is no external capacitance between Varer and Vagnp then the voltage reference has to supply the peak current directly The maximum allowed resistance Raper between the voltage reference Vpp and Varer using no external capacitance Caper is specified in the Data Sheets of the C500 C166 Family The specified value for Raper in the Data Sheet is the worst case for the calculation of the minimum sourcing peak current which has to be suppl
20. 1 Calculation Example 2 secs pa ma GA naaa 46 7 2 Overload Current jac AKBAR KKK KANAL esd CHeee sd eee BRA EAR KAMA 47 7 24 Overload Current and Absolute Maximum Ratings 47 7 2 1 1 Calculation Example sagad ue wus BOS 9S See KA ee Sys eee ee oe 47 7 2 2 Overload Current and Operating Conditions 48 7 2 2 1 Calculation Example o2 54650 0 ond cea Peewee ed deve eee we 48 8 PCB and Design Considerations 2 000000 eee 49 8 1 Component Placing 4 22 s an aana Gas as ow KAL ahere cea dates eae be 49 8 2 Power SUDDIY wa sama apan nigata taaa na aid paka ayaa whee ee p 49 8 3 Ground Planes APAPAP PAPA MAPA AA 49 8 4 Signal EINES se naaa anal whe oie pace wee nee bar Balak oes tole tne 50 8 5 Clock Generation sawa 26a kau panama ae abg eons BA man utes e be 50 9 Used Short C tS cenceeeadetiee kegs LENA BRAY ANAK NA oye 51 Application Note 4 V 1 0 2001 05 ss Infineon AP2428 01 finen C500 C166 Microcontroller Families Introduction 1 Introduction For analog signal measurement on most members of the C500 and C166 microcontroller families an A D Analog Digital converter with multiplexed input channels and a sample and hold circuit has been integrated on chip Depending on the device type of the C500 C166 Family an 8 bit or 10 bit A D converter with 4 8 10 12 15 16 or 24 multiplexed input channels is integrated The A D converter uses the method of successive approximation In pr
21. 2 Application Note 13 V 1 0 2001 05 we Infineon AP2428 01 Cofino C500 C166 Microcontroller Families Principle of Conversion Comparator Calibration eee ee ee Control El IL LE ee eee Conversion Control Figure 8 Block Diagram for the analog Part of a 10 bit A D Converter with Calibration and Conversion C Nets Application Note 14 V 1 0 2001 05 ss Infineon AP2428 01 ofinn C500 C166 Microcontroller Families Calibration Mechanism Error Correction 4 Calibration Mechanism Error Correction An automatic self calibration mechanism is implemented in the A D converter in order to compensate the offset error and to balance differences in the capacitive network This is due to production variations which can cause linearity deviations of the A D conversion The self calibration mechanism consists of the calibration capacitor net the calibration RAM and the calibration control unit See Figure 8 The self calibration includes two kinds of calibrations e Offset Calibration is the adjustment of the offset error e Linearity Calibration is the binary weight adjustment between the capacitors of the conversion capacitor net 4 1 Calibration Principle The additional correction capacitor net calibration C net is used to add subtract a capacitive charge to the comparator input of the A D converter This correction C net allows an adjustment in the range of 4 LSB with a resolution of 1 32 LSB within 128
22. Application Note V 1 0 May 2001 AP2428 01 A D Converter C500 and C166 Microcontroller Families Analog Aspects Microcontrollers Never stop thinking A D Converter Revision History 2001 05 V 1 0 Previous Version Page Subjects major changes since last revision Controller Area Network CAN License of Robert Bosch GmbH We Listen to Your Comments Any information within this document that you feel is wrong unclear or missing at all Your feedback will help us to continuously improve the quality of this document Please send your proposal including a reference to this document to mcdocu comments infineon com Ka Edition 2001 05 Published by Infineon Technologies AG 81726 Miinchen Germany Infineon Technologies AG 2006 All Rights Reserved LEGAL DISCLAIMER THE INFORMATION GIVEN IN THIS APPLICATION NOTE IS GIVEN AS A HINT FOR THE IMPLEMENTATION OF THE INFINEON TECHNOLOGIES COMPONENT ONLY AND SHALL NOT BE REGARDED AS ANY DESCRIPTION OR WARRANTY OF A CERTAIN FUNCTIONALITY CONDITION OR QUALITY OF THE INFINEON TECHNOLOGIES COMPONENT THE RECIPIENT OF THIS APPLICATION NOTE MUST VERIFY ANY FUNCTION DESCRIBED HEREIN IN THE REAL APPLICATION INFINEON TECHNOLOGIES HEREBY DISCLAIMS ANY AND ALL WARRANTIES AND LIABILITIES OF ANY KIND INCLUDING WITHOUT LIMITATION WARRANTIES OF NON INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS OF ANY THIRD PARTY WITH RESPECT TO ANY AND ALL INFO
23. F ErrormsB ESD fcpu fc fCYCLE Application Note AP2428 01 C500 C166 Microcontroller Families Used Short Cuts Used Short Cuts Analog Digital Converter Analog input X Additional unadjusted error caused by the leakage current A D converter input capacitance internal C net Maximum of the A D converter input capacitance External capacitance connected to the reference voltage input VAREF External capacitance connected to the analog input Hold capacitance of the A D converter LSB of the internal C net MSB of the internal C net Internal A D converter capacitor network C net for conversion 10 bit resolution C net for calibration Analog channel n Differential nonlinearity error Variable for allowed Error to calculate Carer Maximum deviation between the voltage on ANx and Vo when the sample time is finished Real deviation between the voltage on ANx and Vp referred to the actual voltage at ANx Maximum voltage error at Vapep caused by Carer Missing voltage to charge the MSB capacitance of the internal C net to VaAREF 2 during charge redistribution phase Electrostatic discharge CPU frequency Cutoff frequency Cycle frequency fcycue 1 toycLEn 51 V 1 0 2001 05 Infineon technologies INLE IAREF Ii lov lov_max loz1 LSB LSB MSB Q r Rain Rasrc RAREF RAREF INT Rp tBc tc ten tcr tcYCLE ICYCLEn ICHARGE 1
24. GOMPARE ts TCL Ty To T3 TUE Application Note AP2428 01 C500 C166 Microcontroller Families Used Short Cuts Integral nonlinearity error Current of the voltage reference Input leakage current C500 Family Overload current Specified maximum rating of the overload current or Specified maximum of the overload current during operating conditions Input leakage current C166 Family Least significant bit general Least significant bit referred to r bit resolution LSB Varer 2 Most significant bit Charge for a complete charge redistribution and a calibration phase Resolution of the A D converter Internal series resistance of the A D converter Internal resistance of the analog source Resistance between voltage reference and Vape_r input Internal resistance of the voltage reference External resistor Rp to protect an analog input in case of an overload condition A D converter basic clock Conversion time Conversion time of analog channel n Charge redistribution time Cycle time Cycle time of analog channel n Time to charge the MSB capacitance to Vaper 2 within 2 tpc Time to compare MSB voltage with sampled input voltage ANx within 2pc Sample time Internal clock 2 TCL 1 fcpu Time constants for the different phases of a conversion Total unadjusted error 52 V 1 0 2001 05 Infineon technologies Reference voltage
25. RMATION GIVEN IN THIS APPLICATION NOTE Information For further information on technology delivery terms and conditions and prices please contact your nearest Infineon Technologies Office www infineon com Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Infineon Technologies Office Infineon Technologies Components may only be used in life support devices or systems with the express written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system Life support devices or systems are intended to be implanted in the human body or to support and or maintain and sustain and or protect human life If they fail it is reasonable to assume that the health of the user or other persons may be endangered we Infineon AP2428 01 Cofino C500 C166 Microcontroller Families 1 Introduction 2 2 3 ncc5ecac8es ac eneeeneteeacn donee tude he eens sae 5 2 Transfer Characteristic and Error Definition 6 2 1 Ideal Transfer Characteristic aka aha Na iv ebb awn aden TERENA RA wes 6 2 2 ONSET ENOL aaa eean eee eenen arare ee aeaa ees 8 2 3 GaN ENOL cesare APAN NAN NO anaana e e ea eaea 9 2 4 Differential Nonlinearity Error DNLE aaan 10 2 5 Integral Nonlinearity
26. alculation results in the value of cycle time tcycLen and cutoff frequency fc The values of the external capacitance Cexy and resistance of the analog source Raspc are in a fixed relation with the cycle time teyc En teycLen 2 Rasrc Cext In Cext Cext 2 Cex1 toveLEn 2 20 KQ 100 nF In 100 nF 100 nF 210 100 nF tcYCLEn 2 0 82 ms The cutoff frequency is calculated via fo 1 2 T Rasrc Cext fo 1 2 m 20 kQ 100 nF fc 80 Hz Application Note 30 V 1 0 2001 05 Infineon AP2428 01 Cofino C500 C166 Microcontroller Families Analog Input ANO ANy Table 4 includes calculation results of the cycle time in ms for different values of Cex7 and Rasprc with the assumed values of the example Error anx 0 5 LSB Table 4 Cycle Time tcycy en for Different Values of Cey7 and Rasrc 0 17 0 07 0 06 0 04 0 04 0 03 0 03 0 03 0 87 0 37 0 28 0 22 0 21 0 17 0 17 0 17 1 73 0 75 0 56 0 45 0 41 0 35 0 34 0 34 2 60 1 12 0 84 0 67 0 62 0 52 0 52 0 52 3 47 1 49 1 13 0 90 0 82 0 70 0 69 0 68 4 33 1 86 1 41 1 12 1 03 0 87 0 86 0 85 5 20 2 24 1 69 1 35 1 24 1 05 1 03 1 02 6 93 2 98 2 25 1 80 1 65 1 40 1 38 1 35 8 66 3 73 2 82 2 25 2 06 1 75 1 72 1 69 17 33 7 45 5 63 4 49 4 12 3 50 3 44 3 38 tCYCLEn ms Table 5 includes calculation results of the cutoff frequency in Hz for different values of Cexr and Raspc with the assumed values of
27. ase and a calibration phase is Q Cain Varer The current for the voltage reference depends on the minimum cycle time for a total conversion Q teycLE AREF The external resistance Rarer between the voltage reference and the input Vapep of the A D converter has an enormous influence on the accuracy This resistor should be chosen as small as possible Because the continuous current lapgf Causes a voltage difference Veppop between the voltage reference Vpp and the reference voltage input Varer Of the A D converter See Figure 20 Verror Rarer JAREF Application Note 39 V 1 0 2001 05 Infineon AP2428 01 Cofino C500 C166 Microcontroller Families Reference Voltage VAREF and VAGND 6 2 1 Calculation Example The assumed values used in the example are Cain 33 pF Rain 250 Q VRF BV tsc 160 ns r 10 10 bit resolution tcycLte 7 8 us C166 Family minimum time fepy 20 MHz E 2 Error AREF 0 25 LSB VERROR VRF 4096 1 22 mV The value for the external capacitance between Varer and Vacnp IS Carer 2 2 E Cain 2 C AREF gt 21042 33pF 2 C AREF gt 68 nF Note A typical recommendation for the value of the external capacitance is CAREF 100 nF With the assumption Vaper Vpp the minimum continuous current which has to be supplied by the voltage reference is lAREF 2 Cain Varer CYCLE AREF gt 33 pF 5V 7 8 Us IAREF 2 21HA The allowed maximum value for the resistor
28. curacy Erroran to the TUE of the A D converter This chapter shows how to calculate the external circuits for the analog inputs The derivation of the necessary formulas is followed by calculation examples Because of the different phases of a total conversion sample and charge redistribution time the calculation examples are shared into different electrical models which fit best to the values of the used external circuits The basis for the way of proceeding is the voltage waveform of analog input ANx which can be observed during a conversion Note A detailed solution of the calculation without a simplified electrical model leads to a 2nd order differential equation and will not be discussed in the ApNote 5 1 Electrical Model of the A D Converter Input Figure 9 is a strongly simplified block diagram of the A D converter The block diagram includes only the relevant elements necessary for a calculation of the external circuits The A D converter input capacitance Ca contains the capacitors of the conversion C net and all parasitic capacitors which have to be considered for the calculation The A D converter input capacitance Cain is specified in the A D converter characteristics in the Data Sheet The value of the actual design steps is Can max 33 pF Please refer to the Data Sheet for the exact value of the used microcontroller Rain is the internal series resistance of the A D converter The value is Rain 250 Q This value is not
29. e Voltage Jump V Cain 33 pF Precharge Vo Vcain 2 5 V and Vo Varer Cext 1 pF 10 pF 100 pF 1nF 10 nF 100 nF 1 WF Va 2 4 V 1 9 V 0 6 V 80 mV 8 2MV 0 8mV 0 08 mV Application Note 21 V 1 0 2001 05 ss Infineon AP2428 01 Cofino C500 C166 Microcontroller Families Analog Input ANO ANy 5 3 2 Charge of Cain and Cext via Rasrc The electrical model during sample time with Ts is shown in Figure 12 In this electrical model Ray is neglected because in typical systems Rasrpc gt gt Rain The voltage at Cain and Ceyz is defined by Vg and V at the beginning of the second phase start voltage Vo Va Rasrc Vo Cext Cain Figure 12 Electrical Model of the A D Converter during T After V has reached the absolute maximum value Cey7 and Cay are charged via Rasrc from Vo with the time constant To To Rasrc Cain Cext Application Note 22 V 1 0 2001 05 Infineon AP2428 01 Cofino C500 C166 Microcontroller Families Analog Input ANO ANy 5 4 Rasrc Calculation with 0 pF lt Cext lt 2 z 1 Cain For reliable results it must be assured that during the sample time the input capacitance Cain is completely charged to the desired value which is then digitized by the converter Under worst case conditions this capacity must be charged or discharged by the half input voltage when Vo Varer Of Ng VAGND The input capacitance C ay of
30. e gap between the analog ground plane and the digital ground plane region Application Note 49 V 1 0 2001 05 we Infineon AP2428 01 Cofino C500 C166 Microcontroller Families PCB and Design Considerations 8 4 Signal Lines e Analog signal traces should be over the analog ground plane e Digital power and digital signal traces should be over the digital ground plane e Regions between analog signal traces should be filled with copper which should be electrically attached to the analog ground plane Regions between digital signal traces should be filled with copper which should be electrically attached to the digital ground plane These regions should not be left floating which only makes the interference worse Using ground plane fill has shown to reduce digital to analog coupling by up to 30 dB 8 5 Clock Generation e Locate quartz crystal ceramic resonator or external oscillator as close as possible to the microcontroller e Keep digital signal traces especially the clock signal as far away from analog input and voltage reference pins as possible e Avoid multiple oscillators or asynchronous clocks Best results are obtained when all circuits are synchronous to the A D converter sampling clock Application Note 50 V 1 0 2001 05 we Infineon technologies 9 ADC ANx AUE cak CAIN CAIN max CAREF CExT CHOLD Ci sB CusB C Net Ga Co TRN chn DNLE E Errorainx Errorainx real Error ARE
31. ee chapter Overload and Leakage Current Application Note 33 V 1 0 2001 05 we Infineon AP2428 01 Cofino C500 C166 Microcontroller Families Analog Input ANO ANy 5 6 3 Calculation Example with the Formula in the Data Sheet The A D converter Characteristics in the Data Sheet example for C166 Family include the formula for the calculation of the maximum Internal resistance of analog source With tg in ns and Ragpc in KQ the formula is Rasrc lt te 450 0 25 This formula in the C166 Family Data Sheets is based on the assumption that the analog input ANx is only loaded with a small external parasitic capacitance Cex lt 65 pF For systems with an external capacitance which exceeds this value the external components have to be calculated as shown in the previous chapters The table below includes the maximum values for Rasrc calculated with the formula in the Data Sheets of the C166 Family Table 7 Maximum Values for Raspc and sample Times ts Cex7 65 pF ts Us 1 2 3 4 5 6 7 8 9 10 Rasrc KQ 2 0 4 2 6 4 8 6 10 9 13 1 15 3 17 5 19 8 22 0 Note The leakage current specified in the Data Sheet can have an influence to the accuracy see note at Table 6 Application Note 34 V 1 0 2001 05 Infineon AP2428 01 Cofino C500 C166 Microcontroller Families Reference Voltage VAREF and VAGND 6 Reference Voltage Varep and V AGND During
32. ent damage to the microcontroller Exposing the microcontroller to absolute maximum rating conditions for extended periods may affect device reliability When the system is switched off or in periods where it is not necessary to guarantee correct operation the absolute maximum ratings are the fundamental information for the calculation of the input overload current which may occur in case of a system error In those cases the specified maximum overload current is loy 10 mA on any pin and the absolute sum of input overload currents on all port pins is 100 mA For the exact values please refer to the Data Sheet 7 2 1 1 Calculation Example Assumed system values Vpp 0V System supply voltage is off worst case VErr max 12 V Maximum voltage of the analog signal 7 in case of a fatal system error lov max 10 mA Specified absolute maximum rating of the overload current What is the minimum value for the external resistor Rp to protect an analog input pin for a short time overload condition Application Note 47 V 1 0 2001 05 we Infineon AP2428 01 Cofino C500 C166 Microcontroller Families Overload and Leakage Current Rp Ver max 7 VDD 0 5 V lov_max Rp 12V 0V 0 5V 10mA Rp 1150 Q 7 2 2 Overload Current and Operating Conditions The Operating Conditions must not be exceeded in order to ensure correct operation of the microcontroller The specified operating conditions allow a maximum overload current of l
33. erwise the voltage reference supplies the system with current via the ESD clamp diode In that case it is necessary to reduce the overload current to the specified absolute maximum ratings See chapter overload and leakage current The overload current can be reduced via a resistor or a diode If the additional external clamp resistor causes an unacceptable additional error at Application Note Varer then an external clamp diode should be used 37 V 1 0 2001 05 ss Infineon AP2428 01 ofinn C500 C166 Microcontroller Families Reference Voltage VAREF and VAGND 6 2 Rarer Calculation Including an External Capacitance The calculation is based on the assumption that there is an external capacitance Carer between Vapep and Vagnp The selected external capacitance has to be high enough that the total charge which is necessary to load the internal C net Caw for a total conversion phase is supplied by the external capacitor Carer Voltage Reference VERROR lAREF A D Converter Rain tbit conversion Cain Central Analog Ground Figure 20 A D Converter during Conversion Phase with Caper The following considerations include the value of the external capacitance Caper with respect to the assumed maximum voltage error at Varer Errorapep caused by Carer and the necessary time teycy g to reload the external capacitor The relation between the external capacitance Cape
34. es of the real ADC Transfer Curve and the Ideal ADC Transfer Curve at the maximum digital out value For the consideration in the figure below all other kinds of errors offset DNLE INLE are excluded Digital Output Gain Error Ideal Transfer Curve Ideal ADC Transfer Curve Real ADC Transfer Curve Cc 2 O W w oc a O 1022 1023 1024 Analog Input Voltage LSB Figure 4 Gain Error Application Note 9 V 1 0 2001 05 Infineon AP2428 01 Cofino C500 C166 Microcontroller Families Transfer Characteristic and Error Definition 2 4 Differential Nonlinearity Error DNLE The differential nonlinearity error describes variations in the analog value between adjacent pairs of digital numbers over the full range of the digital output If each transition step width is exactly 1 LSB the differential nonlinearity error is zero If the transitions are 1 LSB 1 LSB then there is the possibility of a missing codes If a missing code occurs then one value of the digital output is missing e g the digital output might jump from 0011 to 0101 and missing out 0100 See figure below If the differential nonlinearity error is less than 1 LSB then a missing code is automatically excluded For the consideration in the figure below all other kinds of errors offset gain INLE are excluded Ideal Transfer Curve Digital Output Ideal Transfer Curve ADG Transfer Curve Real ADC Transfer Curve Ideal ADC T
35. ied by the voltage reference VRE RAREF lAREF 2 Application Note 35 V 1 0 2001 05 ss Infineon AP2428 01 Cofino C500 C166 Microcontroller Families Reference Voltage VAREF and VAGND 6 1 Sources for the Voltage Reference Depending on the system demands several different kinds of voltage references can be used in a system The supply voltage of the microcontroller can be selected for the reference voltage but the accuracy is in percentage range The accuracy of an external high precision voltage reference is in the per mille range 6 1 1 Supply Voltage of the Microcontroller In most systems the voltage reference used for the A D converter is the supply voltage Vpp of the microcontroller The typical accuracy of voltage regulators is 2 Yo See power semiconductor family TLE42xx from Infineon Technologies When using the digital supply voltage of the microcontroller it is recommended to insert a low pass filter between Vpp and Vap_r for the voltage reference See figure below The low pass filter suppresses noise on pin Vapep to improve the accuracy of the A D converter results 5V 5 Power Supply 9 IV o Central AGND Oo Analog 2 Ground GND Vss Central Digital Ground Figure 18 Supply Voltage used for Voltage Reference The values of the capacitance Carrer and the resistor Raper depend on the characteristics of the system Typical values are Raper 47 Ohm and Cape
36. inciple the A D converter can be divided in two parts the analog interface including the converter with sample and hold circuit and the digital part which contains different registers and the digital control unit This Application Note provides basic information and recommendations concerning the analog part of the A D converter Please refer to the corresponding User s manual for the description concerning the digital part of the A D converter Based on the history and evolution of the microcontrollers there are different implementations of the A D converter available This Application Note is referred to the actual status of A D converters which are implemented in the C500 C166 Family The differences of the analog part concern mainly the values in the A D converter characteristics specified in the Data Sheet For details please use the corresponding Data Sheet The resolution r of the A D converter refers to the number of quantization levels an analog input voltage can be determined to This number of smallest levels is given in bits and one of them is an LSB Figure 1 shows an example of an A D converter with 1024 quantization levels This A D converter has a 10 bit resolution An input voltage of 5 V is quantized with a step size of 5 V 2 1 4 88 mV This theoretical accuracy of an A D converter is degraded by inaccuracies of the A D converter itself total unadjusted error Further the accuracy of the total A D conversion system
37. log source and the reference voltage at pin Varer Both the accuracy of the reference voltage and the accuracy of the analog source have an influence to the accuracy of the total A D conversion system because any changes in the supply voltage of the analog source results in a change at the analog input voltage ANx seen by the A D converter Since the voltage reference is independent from the analog source excitation the ADC conversion result will reflect the changed excitation Figure 23 shows the principle of a ratiometric configuration The same voltage reference source is used for the analog source excitation and the reference voltage input Vaperp Therefore a given change in the analog source excitation causes the same change at the reference voltage Vapep The A D converter conversion result is the ratio of the analog input ANx to the reference voltage Vapep Since both the analog input ANx and the reference voltage Vapep are derived from the same voltage reference source changes do not cause measurement errors Hence the A D converter conversion result is independent to variations in the analog source excitation or variations in the reference voltage input Vapep Because of that a stable voltage reference is not necessary to achieve an accurate measurement result Voltage y Reference DD Analog if Raper Source AJ Varer Tantalum Ceramic CAREF LJ Vacno 2 Central Analog Ground 2 ees TAN 9 Power o Supply 5V JVoo Cent
38. ltage reference due to the binary weighting The available time to charge the MSB to Vapeg 2 and to compare the MSB voltage with the sampled voltage is 4 tgc tpc Basic Clock frequency can be controlled via register ADCON Typically half the time can be used to charge MSB to Vapreg 2 value depends on device type and on technology The other half is necessary for the comparison of the values by the comparator of the A D converter The worst case for the maximum allowed resistance between voltage reference Var and input Vapep of the A D converter is the conversion of the MSB The capacitance Cysp is charged with Vapep 2 and the voltage wave form at the comparator input is Application Note 41 V 1 0 2001 05 ss Infineon AP2428 01 Cofino C500 C166 Microcontroller Families Reference Voltage VAREF and VAGND t Raper Rain Cmeg Vusp Vaner 2 1 AREPF RAIN USB The maximum allowed value for Raper With Visp tac VaReg 2 Errorysp is Rarer lt tge V AREF n ABEE MSB Errormsg 2 RAN The figure below shows the comparator voltage Vmsg t during the conversion of the MSB The conversion of the MSB lasts 4 tgc l CHaRGE __ tcompanE 000008 ny ana 4 tgo m teHARGE time to charge the MSB capacitance to Vapgep 2 within 2 tpc tcompare time to compare MSB voltage with sampled input voltage ANx within 2 tgc Figure 22 Comparator Vol
39. no C500 C166 Microcontroller Families Overload and Leakage Current Family it is l In this Application Note the symbol loz is used for the input leakage current The specified value of the A D converter input leakage current depends on the device type Please refer to the Data Sheet for the exact value The input leakage current has to be taken into account for the calculation of the maximum allowed error of the A D converter result referred to the analog source Because the resistance of the analog source Raspc and the input leakage current loz can cause an additional error via the external leakage voltage V fax VLeak loz1 Rasrc The leakage voltage Vi pag can cause an additional unadjusted error AUEL gak AUEj pak VLEAK 1LSB 7 1 1 Calculation Example Assumed system values AUE gak 0 25 LSB Assumed maximum additional unadjusted error caused by resistance of the analog source Rasrc Varep 25V 1 LSB 4 9 mV 10 bit A D converter loz1 200 nA Specified maximum input leakage current What is the allowed maximum resistance of the analog source Raspc Rasrac Vieak lozi Rasrc AUEj par 1LSB loz Rasrc 0 25 LSB 4 9 mV 200 nA Rasre 6125 Q Note The specified maximum Input Leakage Current of 200 nA can reduce the conversion accuracy when the external resistance has a high value 510 kOhm Application Note 46 V 1 0 2001 05 ss Infineon AP2428 01 ofinn C500 C166 Microc
40. nsfer Curve Ideal ADC Transfer Curve 10 Bit Resolution TUE related to ideal Transfer Curve TUE related to ideal ADC Transfer Curve l l 1 l I 1 l l l 1 1 l 0 0 0 5 1022 1023 1024 0 5 SB ie Analog Input Voltage LSB Quantization Error Figure 1 Ideal Transfer Characteristic Quantization Error LSB Figure 2 Quantization Error Application Note 7 V 1 0 2001 05 Infineon AP2428 01 Cofino C500 C166 Microcontroller Families Transfer Characteristic and Error Definition 2 2 Offset Error The offset error is the deviation from the Ideal ADC Transfer Curve at the lowest transition level on the Real ADC Transfer Curve It is the input voltage required to bring the digital output to zero and can be measured by determining the first digital transition from 0 to 1 of the A D converter The offset error affects all codes by the same amount For the consideration in the figure below all other kinds of errors gain DNLE INLE are excluded Digital Output Ideal Transfer Curve Ideal ADC Transfer Real ADC Transfer Curve including the Offset Error 10 Bit Resolution 1022 1023 1024 Offset Error Analog Input Voltage LSB Figure 3 Offset Error Application Note 8 V 1 0 2001 05 Infineon AP2428 01 Cofino C500 C166 Microcontroller Families Transfer Characteristic and Error Definition 2 3 Gain Error The gain error is the difference between the slop
41. ntroller should bridge the partitions with only analog pins in the analog area and only digital pins in the digital area Rotating the microcontroller can often make this task easier 8 2 Power Supply e Place the analog power and voltage reference regulators over the analog plane The same holds for the digital power regulators e Analog power traces should be over the analog ground plane The same holds for the digital power traces e Decoupling capacitors should be close to the microcontroller pins or positioned for the shortest connection to pins with wide traces to reduce impedance e If both large electrolytic and small ceramic capacitors are recommended make the small ceramic capacitor closest to the microcontroller pins 8 3 Ground Planes e Have separate analog and digital ground planes on the same layer separated by a gap with the digital components over the digital ground plane and the analog components over the analog ground plane e Analog and digital ground planes should only be connected at one point most cases The best place is below the microcontroller Have vias available in the board to allow alternative points e The analog to digital ground plane connection should be near to the power supply or near to the power supply connections to the board or near to the microcontroller e For boards with more than 2 layers do not overlap analog related and digital related planes Do not have a plane that crosses th
42. og channel is possible without inserting a waiting period to charge the external capacitance Cre yt Application Note 27 V 1 0 2001 05 we Infineon AP2428 01 Cofino C500 C166 Microcontroller Families Analog Input ANO ANy 5 5 Rasrc Calculation with Cex7 gt 2 1 Cain The selected external capacitance has to be high enough so the total charge which is necessary to load the internal C net Cam of the A D converter is supplied by the external capacitor Cey7 The considerations below include the value of the external capacitance Cry7 with respect to the assumed maximal Error anx caused by the Cex7 and the necessary time tcycLen to reload the external capacitor 5 5 1 External Capacitance Cex7 The calculation of the external capacitance Cexy is based on the assumption that Varer Va is the sampled voltage and V is the maximum allowed Errorany See Figure 16 After the charge balance voltage jump V the voltage change at the Capacitors during the sample phase is extremely small because of the high time constant Ts of the external capacitance and the resistance of the analog source The example is calculated with the assumption of a maximum allowed error Erroranx LSB 2 Error LSB 2 Error V AREF 2 J 2 Error gt Va Cain Varer Varee 2 Cain Cext Cext gt 2 1 Cain Depending on the A D converter resolution the relations between Cex7 and Car for the calculation of Raspe are
43. ontroller Families Overload and Leakage Current 7 2 Overload Current An overload condition is not a normal operating condition It occurs if the standard operating conditions are exceeded i e the voltage on an A D converter input pin Vain exceeds the specified range Vainx gt Vpp 0 5 V or Vainx lt Vss 0 5 V The supply voltage must remain within the specified limits In case of an overload condition on an A D converter input pin one of the clamp diodes becomes conductive If Vain gt Vpp 0 5 V then the clamp diode connected to Vpp begins to conduct If Vain lt Vss 0 5 V then the clamp diode connected to Vss begins to conduct See Figure 24 The overload current has to be taken into account for the calculation of external resistors which protect the microcontroller inputs These external resistors guarantee that in case of a system error the specified maximum value of the overload current will not be exceeded The calculation also has to consider the specified absolute sum of input overload currents on all port pins of the microcontroller and especially the specified absolute sum of the A D converter input 7 2 1 Overload Current and Absolute Maximum Ratings The parameters of the Absolute Maximum Ratings are stress ratings only and functional operation of the microcontroller is not guaranteed at these or other conditions above the operation conditions Stresses above the absolute maximum ratings may Cause perman
44. oy 5 mA on any pin and the absolute sum over input overload currents on all port pins is 50 mA The specified TUE of the A D converter is guaranteed only if the absolute sum of input overload currents on all analog input pins does not exceed 10 mA For the exact values please refer to the Data Sheet 7 2 2 1 Calculation Example Assumed system values Vpp 45V Minimum system supply voltage during operating conditions worst case VErr max 12 V Maximum voltage of the analog signal 7 in case of a fatal system error lov max 5 mA Specified maximum of the overload current during operating conditions What is the minimum value of the external resistor Rp to protect an analog input of the microcontroller and to ensure correct operation Rp z VErr_max 7 VDD 0 5 V lov_max Rp 12 V 4 5 V 0 5 V 5 mA Rp 1400 Q Application Note 48 V 1 0 2001 05 Infineon AP2428 01 ofinn C500 C166 Microcontroller Families PCB and Design Considerations 8 PCB and Design Considerations This chapter is a brief introduction in mixed signal board design with a list of guidelines for optimum printed circuit board layout for microcontrollers with on chip A D converter 8 1 Component Placing e Partition the board with all analog components grounded together in one area and all digital components in the other Common power supply related components should be centrally located e Mixed signal components including the microco
45. pled Voltage Jooo t tcycLen Cycle time of channel n Vo Voltage of the analog source Velt Charge curve for CExT Vp Voltage rest at the end of teycj pn VA Voltage jump at the start of the sample phase Erroranx Voltage deviation between sampled voltage and voltage of the analog source Figure 16 Voltage at Cey7 with High Capacitance for Periodical Conversions Application Note 29 V 1 0 2001 05 ss Infineon AP2428 01 ofinn C500 C166 Microcontroller Families Analog Input ANO ANy 5 5 3 Cutoff Frequency fc The resistance of the analog source and the external capacitance Creyz act as a low pass filter with the cutoff frequency fe A check is necessary whether the cutoff frequency fits to the frequency of the analog source If the relation between A D converter cycle frequency fcycLe 1 tcycLen and the cutoff frequency is fcycig fe 0 1 then the analog signal is damped with 5 1 LSB 1 fo a 27 Rasrc Cext Note If the external circuit reaches the cutoff frequency then the voltage of the analog source Vo is damped with the factor 3 AB Vain 0 7 Vo cutoff frequency f 5 5 4 Calculation Example with Cgexr gt 2 1 Cain The assumed values used in the example are Cain 33pF ts 1 28 us Varer Vo DV Ran 2509 te 7 8uS r 10 10 bit resolution Rasrc 20 ka Cext 100 nF Cext 3030 Cain Erroranx 0 5 LSBio V AREF 2048 2 44 mV The c
46. r 100 nF r 10 and Ca 33 pF The cutoff frequency of this low pass filter is fe 34 kHz If there is noise on the system supply voltage with a very low frequency then the cutoff frequency can be reduced via an appropriate tantalum capacitance in parallel to Caper which stabilizes the voltage reference Note The impedance and the noise caused by the connection between Central Analog Ground and Central Digital Ground should be as low as possible Application Note 36 V 1 0 2001 05 we Infineon technologies AP2428 01 C500 C166 Microcontroller Families Reference Voltage VAREF and VAGND 6 1 2 External Voltage Reference The source for an external voltage reference can be a standard supply voltage with increased accuracy or with less noise For systems where a high accuracy is demanded high precision voltage reference can be used with a typical accuracy in the range of 2 5 mV 20 mV 5 000 Voltage Reference VDD RAREF V C AREF Tantalum VAREF 5 GND S Ca Power Central 9 Supply Analog o Ground Oo 5V Vp GND Vss Central Digital Ground Figure 19 External Voltage Reference Note If the supply voltage of the microcontroller and the voltage reference of the A D converter are switched on and off at different times then it is very important that the voltage reference is switched on or off only when the supply voltage of the microcontroller is on oth
47. r the internal C net Cay and the assumed maximum error caused by Caper is E Carer 2 2 7 Cain 2 with r 8 8 bit resolution E 0 Errorapep 1LSB Errorapep 1 25 LSB r 10 10 bit resolution E 1 Errorppep LSB 2 LSB Varner 2 r 12 12 bit resolution E 2 Errorppep LSB 4 Application Note 38 V 1 0 2001 05 we Infineon AP2428 01 Cofino C500 C166 Microcontroller Families Reference Voltage VAREF and VAGND Note The maximum voltage error Error aper at Varer caused by Caper is referred to the allowed maximum input voltage at ANx Vain Varer For input voltages at ANx smaller than Varer the additional inaccuracy at Vjjny is proportional less than the value of Error pep used in the example calculations The real additional inaccuracy at Vany S Errorarer_real Vainx VaRer Errorarer with the condition VAGND lt VaINx VAREF The condition Caper 2 2 F Can 2 allows a free choice of the A D converter basic clock tpc but the cycle time teycje has a direct influence on the accuracy of the conversion The cycle time has to be long enough to recharge the external capacitance Carer before the next charge redistribution phase is started The external capacitance Chpep has to be charged from the voltage reference The minimum current which is drawn from the voltage reference is based on the charge that is necessary for a complete conversion The charge Q for a complete charge redistribution ph
48. ral Digital Ground Figure 23 Ratiometric Configuration Application Note 44 V 1 0 2001 05 ae Infineon AP2428 01 Cofino C500 C166 Microcontroller Families Overload and Leakage Current 7 Overload and Leakage Current Both overload and leakage currents are specified in the Data Sheet Consideration of overload and leakage currents can have an influence on the design of the external components of the analog source Figure 24 is a simplified electrical model with ESD structure clamp diodes and leakage current of an analog input Analog Vpp Source Microcontroller MUX ESD Structure Leakage Source Figure 24 A D Converter Input with ESD Structure and Leakage Source Note The ESD structure of the reference voltage Varer and the reference ground Vagnp s the same as shown in the Figure 24 7 1 Leakage Current The maximum input leakage current of the A D converter is specified in the Data Sheet in section DC Characteristics The input leakage current is the sum of all currents which can flow into or out of an input pin caused by parasitic effects of the input structure see Figure 24 The symbols in the Data Sheets of the C500 and C166 Family used for the input leakage current of the A D converter are different For the C166 Family it is loz and for the C500 Application Note 45 V 1 0 2001 05 Infineon AP2428 01 Cofi
49. ransfer Curve Missing Code Cc 2 2 O op w aa b a O 5 1022 1023 1024 a Analog Input Voltage LSB DNLE 1 LSB Figure 5 Differential Nonlinearity Error Application Note 10 V 1 0 2001 05 ss Infineon AP2428 01 finen C500 C166 Microcontroller Families Transfer Characteristic and Error Definition 2 5 Integral Nonlinearity Error INLE The integral nonlinearity error is the maximum difference between the Ideal ADC Transfer Curve and the adjusted Real ADC Transfer Curve without offset and gain error For the consideration in the figure below DNLE is also excluded Digital Output Ideal Transfer Curve 10 Bit Resolution 1022 1023 1024 aa Analog Input Voltage LSB INLE 1 LSB Figure 6 Integral Nonlinearity Error Application Note 11 V 1 0 2001 05 Infineon AP2428 01 Cofino C500 C166 Microcontroller Families Principle of Conversion 3 Principle of Conversion The A D converter is based on the principle of successive approximation It uses a Capacitor network in order to compare the analog input voltage with the actual digital approximation of this voltage The capacitor network is also used for the sample and hold function The conversion is performed in several steps A total conversion consists of e Sample phase e Charge redistribution phase conversion phase e Calibration phase e Write back phase The sequence of the different phases is shown in Fig
50. ranx 0 5 LSB VAREF 2048 2 44 mv The calculation results in the values for Rasrc and teycLen 5 4 3 1 Resistance of the Analog Source Rasrc First the voltage jump V during the sample phase is calculated Va Cain Varer Varer 2 Cain Cext Vas 33 pF 5 V 2 5 V 33 pF 200 pF Va 354 mV The allowed maximum resistance of analog source Raspe IS Rasrc ts Cain Cext In Vq Erroranx Rasrc 1 28 us 33 pF 200 pF In 354 mV 2 44 mV Rasrc 1103 Q The table below shows the different results of Raspc with the assumed values used in the example Table 3 Maximum Values for Rasprc and different Cex7 Cex7 pF 1 20 40 60 80 100 150 200 250 500 1000 10000 Rasrc KQ 5 4 3 7 2 9 2 3 2 0 1 7 1 3 1 1 0 9 0 6 0 35 0 1 Note The capacitive load at the analog inputs ANx should be as small as possible because it reduces the allowed resistance of the analog source Rasrc See Table 3 The only exception is the use of a very high external capacitance which supplies the A D converter with the necessary charge during the sample phase 5 4 3 2 Cycle Time tcycLen The recommended minimum value of the cycle time is toycLen 7 6 Rasrc Cext ts tCYCLEn 7 6 1103 Q 200 pF 1 28 Us teycLen 2 95 Us The calculated cycle time is smaller than the conversion time and in that case continuous conversion of this anal
51. ration Mechanism Error Correction Note After reset the positive and negative analog reference voltages Varner and Vaanp have to be stable and within the specified range in order to perform a correct reset calibration Note The reset calibration can be interrupted by any conversion In this case the reset calibration is lengthened by the conversion time The calibration sequence is performed with the actual values of register ADCON A change of bit field ADCTC A D Conversion Time Control also changes the duration of the calibration sequence During the reset calibration sequence the specified maximum TUE can be exceeded Note When entering IDLE or Slow Down Mode before reset calibration is finished the reset calibration continues until it is finished In this case the Power Down current increases It is recommended to wait until reset calibration is finished before entering IDLE or Slow Down Mode 4 3 Normal Calibration During A D converter operation a re calibration is performed after each conversion in order to perform an adaptation to changing operation conditions e g temperature This re calibration is performed in single steps where a maximum change of 1 32 LSB of the calibration value is possible 4 4 Disturbance Filtering Due to the way the calibration operation is implemented a filtering of disturbances during the calibration is achieved For example noise on Varer Or Vagnp can disturb calibration but ins
52. tage during Conversion of MSB The formula in the Data Sheet can be derived from the relation above The typical value Cusp of a 16 bit microcontroller used for the calculation is Cmsg 16 5 pF Cmsg Cain 2 The assumed maximum Errormsg caused by Rarer is LSB 2 Vaper 2 2 Application Note 42 V 1 0 2001 05 Infineon AP2428 01 Cofino C500 C166 Microcontroller Families Reference Voltage VAREF and VAGND BC RAN Rarer S 57 10 This relation rounded with Rarer in kQ and tp in ns results in the Data Sheet formula Rarer lt tec 60 0 25 6 3 1 Calculation Example For a system using an fepy 25 MHz and a tpc 160 ns the allowed maximum value for RAREF is Rarer 160 ns 60 0 25 with Raper in KQ and tg in ns The minimum current which has to be supplied by the voltage reference is lAREF 2 Varer Rarer AREF gt 5 V 2400 Q with VAREF 5 V lAREF gt 2 1 mA The calculated current is not a continuous one Itis a peak current which flows only at the beginning of MSB conversion and becomes smaller with each converted bit down to the LSB Note This value of Raper assumes that no external capacitance between Vaper and VAGND is used Application Note 43 V 1 0 2001 05 ss Infineon AP2428 01 ofinn C500 C166 Microcontroller Families Reference Voltage VAREF and VAGND 6 4 Ratiometric Configuration In a non ratiometric configuration there is no relation between the voltage of the ana
53. tead of performing a full correction of a detected deviation either offset or linearity in one cycle the calibration circuit performs a step by step reduction of the deviation Thus if during one calibration cycle a deviation caused by a disturbance is detected the last correction value will only be incremented or decremented by one 1 32 LSB As an example if the disturbance would cause an offset deviation of 1 LSB then 32 calibration steps would be necessary to correct for this error If however a deviation occurs during one calibration cycle but has vanished during the next calibration cycle the previous change of the correction value will be cancelled again In other words a wrong calibration caused by disturbances can only occur if the disturbance lasts for a long time Also disturbances occurring during the reset calibration will be eliminated due to the long calibration sequence and the re calibration after each conversion Application Note 16 V 1 0 2001 05 we Infineon AP2428 01 ofinn C500 C166 Microcontroller Families Analog Input ANO ANy 5 Analog Input ANO ANy Each application where an analog voltage has to be measured needs an accurate calculation of the involved external elements This is fundamental to ensure the sufficiently charging of the A D converter input capacitance Cay to the same potential of the analog source during the sample time An insufficient charging of Cay causes an additional inac
54. the example Errorany 0 5 LSB 0 Table 5 Cutoff Frequency fc for Different Values of Cey7 and Rasrc Application Note 31 V 1 0 2001 05 Infineon AP2428 01 finen C500 C166 Microcontroller Families Analog Input ANO ANy 5 6 Rasrc Calculation with Cex7 OpF In this case which is in real systems hard to realize the external capacitance is neglected The electrical model is shown in Figure 17 It can be used for a rough estimation of the external components if the value of Cexy is nearly zero pF The internal C net capacitance of the A D converter is directly charged via Rasrc and Ran Figure 17 Electrical Model of the A D Converter during T with Cey7 0 pF 5 6 1 Resistance of the Analog Source Rasrc When the external capacitance is Cex7 O pF then time constant T 0 s and the maximum voltage jump V at the beginning of the sample time is approximately Vapgp 2 equal to the precharge value of the internal C net Va Cain Varer Varer 2 Cain Va Varer 2 The resistance of the analog source Raspc is calculated via the formula for systems with a small external capacitance but without Cey7 and with Ray t Rasrc gt Rain V Cain AR ta Error ANx The calculation of the cycle time is not necessary because only during sample time is the internal C net connected to the analog source In the other phases of the
55. ure 7 The total ADC conversion time can be controlled via register ADCON C166 Family The block diagram in Figure 8 is related to an A D converter with 10 bit resolution and represents the principle connections between the analog input ANx conversion C net comparator and the result register ADDAT Start of End of Conversion pansala MSB LSB p o a ee Charge Redistribution Phase ea Write back Phase bq ADC Conversion Time gt Figure 7 A D Converter Timing 3 1 Sample Phase During the sample phase the conversion control unit connects the capacitors of the conversion C net to one of the analog input channels via a multiplexer The capacitor network is thus charged discharged to the voltage level of the connected analog input channel The hold capacitor Cyo p at the comparator holds the analog input voltage after sample phase Application Note 12 V 1 0 2001 05 we Infineon AP2428 01 Cofino C500 C166 Microcontroller Families Principle of Conversion 3 2 Charge Redistribution Phase At the end of the sample phase and with the start of the charge redistribution phase the conversion C net is disconnected from the analog input The goal now is to reconstruct the voltage level stored in the hold capacitor Cyo p by connecting the capacitors Cg to Cg individually to Varner Or Vagnp AS the capacitor network conversion C net is binary weighted i e Ch 2 C the charge of the capacitors Cg to Cp
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