`Mapping` in `ICE Emulator for PowerPC`
Contents
1. 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 53 Physical Dimensions Adapter Not necessary 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 54 Adapter2. Only MPC860 MPC821 The internal peripherals of the cpu can be mapped at different places Sys o base defines the base address of the peripheral window This option must be set before the peripheral window is activated If it is changed later you must reprogram the peripheral window with the command per rp SYStem Option RESETCONF Reset configuration Format SYStem Option RESETCONF lt Value gt Only MPC860 MPC821 After HRESET is released the reset configuration word is sampled from the data bus With this option you can define your reset configuration The DBGC value is always 0x3 and the DBPC value is always O SYStem Option IBUS IBUS control Format SYStem Option IBUS lt Value gt Only MPC860 MPC821 With this option you can set the instruction fetch show cycle and serialize control bits of the IBUS support control register SYStem Option ICFLUSH Internal instruction cache flush Format SYStem Option ICFLUSH ON OFF If you use the internal instruction cache it is necessary to flush the cache before every go or hll step Option CFLUSH enables the cache flush software before each jump in Warning Problems can occur when the LCD driver of the MPC821 is active 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC General SYStem Settings and Restrictions SYStem Option ICREAD Instruction cache read Format SYStem Option ICREAD ON OFF If this option
3. If this option is on the emulator tests if there is a clock output of the CPU 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC General SYStem Settings and Restrictions SYStem Option BreakMask Break mask Format SYStem Option BreakMask ON OFF Only MPC860 MPC821 MPC505 The cpu handles debug events similar to exceptions When a debug event normally a break OR a exception occurs the cpu copies the msr into srr1 and the ip into srr0 This means that after an exception occurred the old values of ip and msr are as backup in the srr0 and srr1 registers If now a break happens these values will be overwritten by the new msr and ip values So it is possible to return to the exception routine but not to the main program The status after the start of the exception routine is called non recoverable state If you want to break in a non recoverable state you must switch the option BreakMask to on SYStem Option FREEZE Timer freeze modes Format SYStem Option FREEZE ON OFF If this option is on the internal timer counter are frozen when being in debug mode 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 22 General SYStem Settings and Restrictions SYStem Option VSYNC Synch trace signals Format SYStem Option VSYNC ON OFF Only MPC860 MPC821 MPC505 The emulator has the possibility to trace the flowtrace signals of the cpu with each clock cycle With this trace it is pos
4. EmulInt Reguest EmulExt Denied The emulation head can stay in 6 modes The modes are selected by the SYStem Up or the SYStem Mode command Format SYStem Mode lt mode gt lt mode gt ResetDown ResetUp Alonelnt AloneExt Emullnt EmulExt Reset Down Target is down all drivers are in tristate mode Reset Up Target has power drivers are logically in inactive state but not tristate Alone Internal Probe is running with internal clock driver inactive Only with active module and buffer module Alone External Probe is running with external clock driver inactive Only with active module and buffer module Emulation Internal Probe is running with internal clock strobes to target are generated Only with active module buffer module optional Emulation External Probe is running with external clock strobes to target are activated Active module and buffer module optional In active mode the power of the target is sensed and by switching down the target the emulator changes to RESET mode The probe is not supplied by the target When running without target the target voltage is simulated by an internal pull up resistor 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 10 Basics SYStem Clock Clock generation Format SYStem Clock lt option gt lt option gt VCO High Mid Low VCO Variable frequency 1 35 MHz Low Mid 2 5 5 0 or 10 0 MHz High Dualport Modes Format SYStem Access
5. P DMA3 P J1 P J7 P DMARO P DMAR3 P KO P K5 PDSR P L2 P L7 P DTR P M3 P M7 P EOTO P EOT3 P Q0 P Q6 PERROR PZ0 P Z3 PHALT PDS PHOLDACK PTCK PHOLDREG PTMS P INTO P INT4 P TRST POE P TDI P READY P TDO P SCLK P TCLK P TSO P TS6 P XMITD P Z0 P Z9 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 39 Port Analyzer MPC860 MPC821 Ports are Multiplexed on the Module Switch with PMUX A PMUX B The port analyzer must be switched before tracing the ports MPC860 A MPC860 B P IRQO P IRQ7 P PAOO P PA15 P CS0 P CS7 P PB14 P PB31 PWE0 PWE3 PPC04 PPC15 P GPLAO P GPLA5 P PDO3 P PD15 P GPLB4 P IPAO P IPA7 P IPBO P IPB7 P ALEB P BSAO P BSA3 P OP0 P OP1 PMODCK1 PMODCK2 P DPO P DP3 PHRESET P SRESET PPORESET P Z0 P Z4 P Z0 P Z4 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 40 PortAnalyzer Additional Trace Channels Not used trace channels on Port Analyzer are connected to pins placed on the emulation module Module PPC403GA Port Z0 Port Z1 Port Z2 Port Z3 Port Z4 Port Z5 Port Z6 Port Z7 Port Z8 Port Z9 O0G MON ADU PWD AR p Module MPC505 Gnd Gnd Port Z0 Port Z1 Gnd Gnd Port Z2 Port Z3 GND GND OG ON AU PWD RH p 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 41 PortAnalyzer Module MPC860 MPC821 Port Z0 Port Z1 Port Z2 Port Z3 Port Z4 Gnd Gnd Gnd Gnd Gnd O0 ON AU PWD AR p 1989 2015 Lauterbach GmbH ICE Emulator fo
6. lt mode gt lt mode gt Request Denied Dualport access modes Request The CPU bus access is stopped by the bus request signals for dualport access Denied No dualport access is allowed while the realtime emulation is running 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 11 Basics Mapping and CS Setting of the MPC505 PPC403 The PowerPC controllers have bus interfaces which allows the CPU to communicate with the external memory and peripherals without external logic In the emulator we use an epld to rebuild an address and data strobe out of the different chipselect lines of the CPU For programming this epld it is necessary for us to know how the user has programmed the bus interface So it is necessary for us to know these settings before delivering to adapt this reconstruction epld to your target If the CS settings change during the project it is possible to reprogram this epld It is possible to reprogram it by sending a programming batch file to the customer Mapping and CS setting of the MPC860 821 Normally it is possible to map the user ram of an MPC860 emulator without any application specific epld The following rules should enable you to make your own mapping 1 Set the SYS OPTION PreMapModule off 2 Set your CS registers in the way you want the mapping If you use the UPMA or UPMB DRAM access the start address multiplex bit CSNT SAM in the option register of the CS must be 0 The emu
7. Format MMU TLBSCAN MMU TLBSCAN lt tlb gt lt tlb gt IMMU DMMU Loads the TLB table entries from the CPU to the debugger internal MMU table 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 36 CPU specific MMU commands Memory Classes Memory Class Description P Program D Data SPR Special Purpose Register DCR Device Control Register 400 P and D This storage classes operate on the same physical memory They are only used to be compatible with other emulation probes CPU internal registers and memory may not be accessed dualported 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 37 Memory Classes State Analyzer Keywords for the Trigger Unit Input Event Meaning Analyzer Hardware ECC8 HAC HA120 SA120 BURST X X BUS8 8 bit bus access X X BUS16 16 bit bus access X X BUS32 32 bit bus access X X DATA Data access X X X DMA DMA cycle X X X FETCH Opcode fetch X X X IO IO cycle X X X Read Read cycle X X X Write Write Cycle X X X For not CPU specific keywords see non declarable input variables in ICE FIRE Analyzer Trigger Unit Programming Guide analyzer prog pdf Keywords for the Display WAIT Wait for interrupt normally not sampled PAO PA7 Port A 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 38 State Analyzer Port Analyzer Keywords for the Port Analyzer PPC403GA MPC505 PBUSERR P AO P A7 PBUSREG P B0 P B7 P CINT P 10 P 17 P DMAO
8. Option BRKNOMSK tbd 24 SYStem Option FlowTrace tbd 25 SYStem Option ResetExt tbd 25 SYStem Option ResetMode tbd 25 SYStem Option SCRATCH tbd 26 SYStem Option TURBO tbd 26 SYStem Option Wait System wait states 26 Exception Coal paa AA aaa 27 Schematics 27 RESET 28 eXception Activate Force exception 29 eXception Enable Enable exception 31 eXception Pulse Stimulate exception 32 MAPA Ai 34 MAP BUS Bus width mapping 34 CPU specific MMU commands cmmncccncconnnnnnnnnnnnnnn rr 35 MMU TLB Display MMU TLB entries 35 MMU TLBSCAN Load MMU TLB entries 35 Memory ClASSOS saa a AA AA AA AA iai 36 A A AA AA a i i nic eaananee 37 Keywords for the Trigger Unit 37 Keywords for the Display 37 a KO AA AA AA a 38 Keywords for the Port Analyzer 38 Additional Trace Channels 40 Module PPC403GA 40 Module MPC505 40 Module MPC860 MPC821 41 nn Gn AA a a L a esa cueeteteree nates 42 3rd Party Tool integrations 0 i 43 Realtime operation Systems umaasam an 44 Emaon MOuI S pida 45 Module Overview 45 Order Information 46 CORE AMO a 47 PRESIONES siais siais ii iii iii iii i 48 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 2 Adapter sass Maa ANA nosis ii iii i ik ii i dea ki i ii i i 53 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 3 ICE Emulator for PowerPC Version 06 Nov 2015 P FFFOOFC4 DIABC1 main DA T MIX I E w per E w d 1 addr line code label mne 535 Processor Versio
9. is switched on data dump considers the valid cache lines of the instruction cache This can be different to the external memory SYStem Option DCREAD Date cache read Format SYStem Option DCREAD ON OFF If this option is switched on data dump considers the valid cache lines of the data cache This can be different to the external memory SYStem Option WATCHDOG Disable watchdog Format SYStem Option WATCHDOG ON OFF If this option is switched off the watchdog timer of the CPU is disabled after the sys up SYStem Option BRKNOMSK tbd Format SYStem Option BRKNOMSK ON OFF ON tbd OFF tbd tbd 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC General SYStem Settings and Restrictions SYStem Option FlowTrace tbd Format SYStem Option FlowTrace ON OFF ON tbd OFF tbd tbd SYStem Option ResetExt tbd Format SYStem Option ResetExt ON OFF ON tbd OFF tbd tbd SYStem Option ResetMode tbd Format SYStem Option ResetMode ON OFF ON tbd OFF tbd tbd 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC General SYStem Settings and Restrictions SYStem Option SCRATCH tbd Format SYStem Option SCRATCH ON OFF ON tbd OFF tbd tbd SYStem Option TURBO tbd Format SYStem Option TURBO ON OFF ON tbd OFF tbd tbd SYStem Option Wait System wait states Format SYStem Option Wait lt w
10. 3 5V LA 7201 MPC821 LAMPC860 J3 0 3 5V LA 7202 MPC860 LAMPC860 J3 0 3 5V 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 46 Emulation Modules Order Information Order No Code Text AF7206 BGA272 EXTENSION BGA272 Adapter Extension Ak7207 BGA357 AHMALE Advanced Interconnect male male block for MPC AF7208 BGA357 AI SOCKET Advanced Interconnect socket for MPC860 880 AF7209 BGA357 EXTENSION BGA357 Adapter Extension AF9546 BGA256 AI SOCKET Advanced Interconnect socket for MPC850 AH 9549 BGA272 AHSOCKET Advanced Interconnect socket for MPC555 AL9664 BGA388 A SOCKET Advanced Interconnect socket for MPC561 563 A A9667 BGA388 ADAPTER Advanced Interconnect BGA388 Adapter for CPU AF9672 BGA388 MALE MALE 28 BGA388 Male Male Connector 0 28mm Pin AF9673 BGA388 MALE MALE 22 BGA388 Male Male Connector 0 20mm Pin LA 7210 BGA357 ETEC MPC860 Emulation adapter for E TEC socket for MPC860 LA 7211 CONNECTOR ADS MPC860 Emulation adapter for ADS board LA 7213 BGA357 A MPC860 Emulation adapter for Al socket for MPC860 LA 7214 BGA357 ETEC SOCKET E TEC socket for MPC860 SMD LA 7215 A4MIPC860 BOTTOM Bottom Side Target Adapter for MPC860 LA 7217 CON FADS MPC860 Emulation adapter for FADS board LA 7218 BGA357 ETEC SOCKEFT E TEC socket for MPC860 through hole LA 7907 TCON320 BGA357 PPC Emulation adap f TCON320 to BGA357 MPC880 LA 9545 BGA256 AHVIPC850 PPC Emulation adapter for Al socket for MPC850 LA 9548 BGA272 AI MPC555 Emulation adapter for Al s
11. ESETC Stimulate RESETC line RESETO Stimulate RESETO line RESETT Stimulate RESETT line INTO Stimulate INTO line INT1 Stimulate INT1 line INT2 Stimulate INT2 line INT3 Stimulate INT3 line INT4 Stimulate INT4 line IRQO Stimulate IRQO line IRQ1 Stimulate IRQ1 line IRQ2 Stimulate IRQ2 line IRQ3 Stimulate IRQ3 line IRQ4 Stimulate IRQ4 line IRG5 Stimulate IRQ4 line IRQ6 Stimulate IRQ4 line IRQ7 Stimulate IRQ4 line OFF No stimulation on any exception line 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 34 Exception Control Mapping MAP BUS Bus width mapping Format MAP BUS8 lt range gt MAP BUS16 lt range gt MAP BUS32 lt range gt MAP BUSEXT ranges Every block in the address space of the CPU has either an 8 16 or 32 bit bus width The emulator breakpoint and trace system need this information in realtime in order to work correctly The mapper must be set for all ranges where internal bus width setting is used map bus8 0x0 0x0fffff maps first 1 MB block for 8 bit map busext remaps all to external definition The MAP RESet command sets the bus width definition to external 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 35 Mapping CPU specific MMU commands MMU TLB Display MMU TLB entries Format MMU TLB lt t b gt lt tlb gt IMMU DMMU Displays a table of all MMU TLB entries of the selected TLB table MMU TLBSCAN Load MMU TLB entries
12. Format eXception Activate RESETC ON OFF Format eXception Activate RESETH ON OFF Format eXception Activate RESETC ON OFF Format eXception Activate INTO INT4 ON OFF Format eXception Activate IRGO IRQ7 ON OFF Format eXception Activate OFF CINT Activates the CINT line HRESET Activates the HRESET line SRESET Activates the SRESET line RESET Activates the RESET line RESETC Activates the RESET line RESETO Activates the RESET line RESETT Activates the RESET line INTO Activates the INTO line INT1 Activates the INT1 line INT2 Activates the INT2 line INT3 Activates the INT3 line 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 30 Exception Control INT4 IRQO IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 OFF Activates the INT4 line Activates the IRQO line Activates the IRQ1 line Activates the IRQ2 line Activates the IRQO line Activates the IRQ1 line Activates the IRQ2 line Activates the IRQO line Activates the IRQ1 line No activation of any exception line 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 31 Exception Control eXception Enable Enable exception Format eXception Enable CINT ON OFF Format eXception Enable HRESET ON OFF Format eXception Enable SRESET ON OFF Format eXception Enable RESET ON OFF Format eXception Enable RESETO ON OFF Format eXception Enable INT ON OFF Format eXception Enable INTO INT4 ON
13. IBM PPC403GA MPC505 MPC821 MPC860 The adaption to different probes is done by changing the module Modules support BGA or QFP versions where applicable The emulation frequency is up to 20MHz with O wait states and up to 28 MHz with 1 or more wait states There is no significant speed difference to realtime because target systems in most cases use wait states and fast program loops are running from the cache This leads to an average performance reduction of only about 1096 using three wait states The probe uses a special emulation concept active passive emulation to provide either emulation in realtime in the target or the advanced emulation features of Trace32 with reduced speed Therefore the probe contains three parts The top level is the passive emulation module It contains the drivers for addresses data and ports the control for the bus interface the dualport and the BDM The second level is the active CPU module it contains the CPU the interrupt reset enable and the clock switches the pull up resistors for the CPU and the control of the switches and the buffers on the buffer module The third level is the buffer module It contains the address and data buffers between the CPU and the target The modules are connected with the target connector for the CPU signals e g ET160 and additional an intermodul connector for the control signals You can put these three modules one on the other If you want to use all emulati
14. ICE Emulator for PowerPC TRACE32 Online Help TRACE32 Directory TRACE32 Index TRAGES2 Doc is ICE Circul MUSSO ii Ao ICE Target A AA ICE Emulator Tor PowerPC UA PANG Aia k i CARNICOS QUESTA A A a a A Troubleshooting ri a as Hang Up Dualport Errors BO A a a a SYStem Mode SY Stem Clock Clock generation Dualport Modes Mapping and CS Setting of the MPC505 PPC403 Mapping and CS setting of the MPC860 821 Jumper Settings of the MPC860 821 Probe Adaption to different Clock Sources of the MPC860 821 Probe Layout of the MPC860 821 Probe General SYStem Settings and Restrictions cccsssccsseeeesesseesseeeeeeseeesseeeeeeeeeessneeeneneeeess General Restrictions SYStem Option PreMap Address lines SYStem Option PreMapMod Premapper mode SYStem Option TestClock Clock test SYStem Option BreakMask Break mask SYStem Option FREEZE Timer freeze modes SYStem Option VSYNC Synch trace signals SYStem Option CFLUSH Instruction cache flush SYStem Option ONCE On circuit emulation SYStem Option BASE Peripheral base address SYStem Option RESETCONF Reset configuration SYStem Option IBUS IBUS control SYStem Option ICFLUSH Internal instruction cache flush 1989 2015 Lauterbach GmbH o N 000 a E 10 10 11 11 13 14 15 18 18 19 19 20 21 21 22 22 22 23 23 23 23 ICE Emulator for PowerPC 1 SYStem Option ICREAD Instruction cache read 24 SYStem Option DCREAD Date cache read 24 SYStem Option WATCHDOG Disable watchdog 24 SYStem
15. OFF Format eXception Enable IRQ ON OFF Format eXception Enable IRQO IRQ7 ON OFF Format eXception Enable OFF Format eXception Enable ON CINT Enables the CINT line HRESET Enables the HRESET line SRESET Enables the SRESET line RESET Enables the RESET line RESETO Enables the RESETO line INT Enables the INT line INTO Enables the INTO line INT1 Enables the INT1 line INT2 Enables the INT2 line INT3 Enables the INTS line 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC KY Exception Control INT4 Enables the INT4 line IRQ Enables the IRQ line IRQO Enables the IRQO line IRQ1 Enables the IRQ1 line IRQ2 Enables the IRQ2 line IRQ3 Enables the IRQ1 line IRQ4 Enables the IRQ2 line IRQ5 Enables the IRQ1 line IRQ6 Enables the IRQ2 line IRQ7 Enables the IRQ2 line ON Enables all exception line OFF Disables all exception lines eXception Pulse Stimulate exception Format eXception Pulse CINT Format eXception Pulse HRESET Format eXception Pulse SRESET Format eXception Pulse RESET Format eXception Pulse RESETO Format eXception Pulse RESETC Format eXception Pulse RESETT 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 33 Exception Control Format eXception Pulse INTO INT7 Format eXception Pulse IRQO IRQ7 Format eXception Pulse OFF CINT Stimulate CINT line HRESET Stimulate HRESET line SRESET Stimulate SRESET line RESET Stimulate RESET line R
16. X Systems Inc DEOS DDC I Inc implemented by DDC I ECOS eCosCentric Limited 1 3 2 0 and 3 0 Elektrobit tresos Elektrobit Automotive GmbH via ORTI ERCOSEK ETAS GmbH via ORTI Erika Evidence via ORTI FreeRTOS Freeware V7 Linux Kernel Version 2 4 and 2 6 3 x 4 x Linux MontaVista Software LLC 3 0 3 1 4 0 5 0 LynxOS LynuxWorks Inc 3 1 0 3 1 0a 4 0 MQX Freescale Semiconductor Inc 3 x and 4 x MQX Synopsys Inc 2 40 and 2 50 NetBSD NORTi MISPO Co Ltd Nucleus PLUS Mentor Graphics Corporation OS 9 Radisys Inc OSE Delta Enea OSE Systems 4 x and 5 x OSEK via ORTI OSEKturbo Freescale Semiconductor Inc via ORTI former MetrowerksOSEK PikeOS Sysgo AG ProOSEK Elektrobit Automotive GmbH via ORTI pSOS Wind River Systems 2 1 to 2 5 3 0 with TRACE32 QNX QNX Software Systems 6 0 to 6 5 0 RTEMS RTEMS 4 10 RTXC 3 2 Quadros Systems Inc RTXC Quadros Quadros Systems Inc Sciopta Sciopta SMX Micro Digital Inc 3 4 to 4 0 ThreadX Express Logic Inc 3 0 4 0 5 0 uC OS I Micrium Inc 2 0 to 2 92 UITRON HI7000 RX4000 NORTi PrKernel VRTXsa Mentor Graphics Corporation VxWorks Wind River Systems 5 x to 7 X 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 45 Realtime operation Systems Emulation Modules Module Overview ET160 QF07 3 0 3 5V LA 7220 LA 7221 PPC403GC ET160 QF07 J 3 0 3 5V PPC403GCX ET160 QF07 3 0 3 5V LA 7222 PPC403GB ET128 GF51 3 0 3 5V MPC505 ET160 QF07 3 0 3 5V LA 7203 MPC509 ET160 QF07 3 0
17. ait_states gt Number of additional system wait states 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC General SYStem Settings and Restrictions Exception Control This menu chart is from the PPC403 It may be different for other CPUs Schematics Activate OFF CpuReset PerReset HALT BR IRQO IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 ICE Emulator for PowerPC HALT BR BERR IRQ IRQO IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 lt lt eee AQ a VPerReset CpuReset PerReset HALT BR BERR IRQ4 IRQ5 IRQ6 Puls 1989 2015 Lauterbach GmbH 28 CpuReset PerReset HALT BR BERR IRQO IRQ1 IRQ2 IRQ3 IRQ4 IRO5 IRQ6 Exception Control RESET The reset line input and output of the active module is controlled by a bridge with analog switches and S1 GND diodes PPC400 RESET input Passive Module Active Module TARGET Reset Target R1 1K S1 Reset Passive s2 s3 s4 Reset Out Reset In Reset CPU ICE Emulator for PowerPC tu 53 X Activate ResetP X Puls ResetP X Enable Resetout X Enable Reset X Activate ResetC X Puls ResetC 1989 2015 Lauterbach GmbH 29 Exception Control eXception Activate Force exception Format eXception Activate CINT ON OFF Format eXception Activate HRESET ON OFF Format eXception Activate SRESET ON OFF Format eXception Activate RESET ON OFF
18. al Dimensions Dimension LA 7210 BGA357 ETEC MPC860 UL Te SIDE VIEW 31 TOP VIEW all dimensions in mm 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC Physical Dimensions Dimension LA 9539 BGA272 CPU ADAPTER TY TOP VIEW 2400 Y AK 50 t LL 4 SIDE VIEW 425 SAMTEC TFM 130 32 S D LC 4 180 SAMTEC SFM 130 L1 S D LC ALL DIMENSIONS IN 1 1000 INCH LA 9548 BGA272 AI MPC555 mA TAREN wA ANAN 2400 y maam L so CCC tib SIDE VIEW 425 SAMTEC TFM 130 32 S D LC 500 ALL DIMENSIONS IN 1 1000 INCH 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 52 PhysicalDimensions Dimension LA 7907 TCON320 BGA357 PPC TOP VIEW 2850 1425 gt PIN1 AR 1425 2850 SIDE VIEW SAMTEC TFM 140 32 S D LC BGA ADAPTER Telo SYSTEM 18 ADVANCED 200000000000000 SOLDER IN ALL DIMENSIONS IN 1 1000 INCH
19. he target PORESET has a 4 7K pull up and will be asserted with every system up RSTCONF has a 1K pull down MODCK has pull up pull down as configured Ref Adaption to different clock sources PORESET CPU Look in Layout of the MPC860 821 probe for the physical location of the jumpers 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 14 Basics Adaption to different Clock Sources of the MPC860 821 Probe MPC860 Clock source selection is made by sampling the MODCK1 and MODCK2 pins during Power On Reset POR The POR is asserted during every sys up command The emulation pod has 4 7K pull up at MODCK1 and 4 7K pull down at MODCK2 as default This is the 1 1 mode setting of the CPU clock For adapting to different clock sources you may change the pull up down resistors as needed MODCK1 MODCK2 Default SPLL Options MF 1 0 0 513 Normal Operation PLL Enabled Timing reference is freq OSCM 32 kHz 0 1 5 Normal Operation PLL Enabled Timing reference is freq OSCM 4 MHz 1 0 1 Normal Operation PLL Enabled 1 1 Mode F clkout F extclk 1 1 5 Normal Operation PLL Enabled Timing reference is freq OSCM 4 MHz Target Look in Layout of the MPC860 821 probe for the physical location of the jumpers 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 15 Basics Layout of the MPC860 821 Probe Bar eer 989I rage 1989 2015 Lauterbach GmbH ICE Emulator f
20. indows ALL CODEWRIGHT Borland Software Windows Corporation ALL CODE CONFIDENCE Code Confidence Ltd Windows TOOLS ALL CODE CONFIDENCE Code Confidence Ltd Linux TOOLS ALL EASYCODE EASYCODE GmbH Windows ALL ECLIPSE Eclipse Foundation Inc Windows ALL RHAPSODY IN MICROC IBM Corp Windows ALL RHAPSODY IN C IBM Corp Windows ALL CHRONVIEW Inchron GmbH Windows ALL LDRA TOOL SUITE LDRA Technology Inc Windows ALL UML DEBUGGER LieberLieber Software Windows GmbH ALL ATTOL TOOLS MicroMax Inc Windows ALL VISUAL BASIC Microsoft Corporation Windows INTERFACE ALL LABVIEW NATIONAL Windows INSTRUMENTS Corporation ALL CODE BLOCKS Open Source ALL C TEST Parasoft Windows ALL RAPITIME Rapita Systems Ltd Windows ALL DA C RistanCASE Windows ALL TRACEANALYZER Symtavision GmbH Windows ALL SIMULINK The MathWorks Inc Windows ALL TA INSPECTOR Timing Architects GmbH Windows ALL UNDODB Undo Software Linux ALL VECTORCAST Vector Software Windows ALL WINDOWS CE PLATF Windows Windows BUILDER POWERPC GR228X IC Battefeld GmbH Windows TESTSYSTEME POWERPC OSE ILLUMINATOR Enea OSE Systems Windows POWERPC DIAB RTA SUITE Wind River Systems Windows 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 44 3rd Party Tool Integrations Realtime operation Systems Name Company Comment AMX KadakProducts Ltd ChorusOS Oracle Corporation CMX RTX CM
21. lator uses the first cycle of the memory access to latch the internal addresses With this bit at O the first cycle of the DRAM access is not multiplexed but shows the internal addresses on the address pins For accessing your target memory it is necessary to change the programming of the UPM RAM It is recommended to use internal emulation memory instead of the external target DRAM Then you don t have to care for the UPM settings Find more Information about this matter in the chapters External Bus Interface and Memory Controller of the user manual CLKOUT Typical DRAM Access TS v 0 Waitstates TA TA SAM 1 mk XrowX corrum LL DATA X RAS CS CAS UU fF 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 12 Basics CLKOUT me Typical DRAM Access v_ 0 Waitstates TA X SAM 0 gt RAS CS N CAS O 3 Map workbenches wherever you need ram 4 Map RAM wherever you need it Map the bus size to the RAM location Example SYS DOWN MAP RESET SYS O PMM OFF SYS M AT d s 0x2200110 31 0x000800081 See BR C82 d s 0x2200114 31 0x0FC00800 Seit OR CS2 MAP PRE 0x0 0x0FFFFF MAP RAM 0x0 0x0FFFF MAP 64 K MAP BUS32 0x0 0x0FFFF 32 BiLe MAP I internal 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 13 Basics Jumper Settings of the MPC860 821 Probe Some lines of the MPC860 CPU are connected with the target and can be disconnected by removing a jumper if they cause problems to t
22. n P FFFOOFC4 9421FFD8 main stw PVR 00200001 FAM 00000002 ME P FFFOOFCS8 7C0802A6 mf1 MAJ 00000000 MI P FFFOOFCC 93E10024 stw P FFFOOFDO 9001002C stw Timer int j TSR 44000000 WIS pending WR char p TCR 00000000 WP 2417 WPC of PIE disable FP 539 vtripplearray 0 0 0 PIT 00000000 E w a l record run address cycle d 1 s ol 000003 f P FFFOOFC4 fetch 7FE00008 DIABC1 main 1 532 533 534 main 535 f trap 000002 mflr r0 000001 BRE For general informations about the In Circuit Debugger refer to the ICE User s Guide ice user pdf All general commands are described in IDE Reference Guide ide ref pdf and General Commands and Functions 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 4 WARNING NOTE Do not connect or remove probe from target while target power is ON Power up Switch on emulator first then target Power down Switch off target first then emulator 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 5 WARNING Quick Start tbd 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 6 QuickStart Troubleshooting Hang Up tbd Dualport Errors tbd 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 7 Troubleshooting FAQ 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 8 FAQ Basics The ICE PPC emulation head supports MPC500 and MPC800 series derivatives from Freescale Semiconductor and PPC400 series derivatives from
23. ocket for MPC555 LA 9660 TCON200 MPC823 AMC Converter TCON 200 to AMC Footprint 823 LA 9661 TCON240 AHMPC555 Emulation adap from TCON240 to BGA272 MPC555 LA 9666 TCON320 AHMPC56X Emulation adap from TCON320 to BGA388 MPC56x Additional Options LA 7216 BGA357 CPU ADAPTER CPU Test Adapter for BGA357 MPC860 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 47 Emulation Modules Operating Voltage tbd 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 48 Operating Voltage Physical Dimensions Dimension LA 7222 M PPC403GB QFP cable 400 El E a 136 gt Ba 143 gt SIDE VIEW A CAT 7 4 Bante Sieve ZR Et d l l Y LARA EA al ra ra LI A LI LI LI LI 74 ll LI LI A LI Lu Lu LA Na EN EE KAN KA a Tl A 4 7 T y 3 fe TOP VIEW all dimensions in mm 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC Physical Dimensions Dimension LA 7203 M MPC505 QFP cable 400 a 133 gt 141 gt SIDE VIEW a r 4 APRA 4 ra ra i 1 J i KI i 82 fi ie j ii magi Nr 2 MAREA 4 9 et dl Y ke TOP VIEW all dimensions in mm LA 7213 BGA357 AI MPC860 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC Physic
24. on features Internal mode internal mapping internal clock you need all three of the modules If you want more speed in your target memory you can leave out the buffer module the buffers have a few ns delay The restriction now is that you can map internal memory only if no buffer on your target is decoded at the same address and that the synchronous breakpoints does not work with external memory If your target memory is a ram you can use software breakpoints instead If you have already soldered a CPU on your target you can work in passive emulation You need only the passive module The CPU on your target is operated via the BDM port Advantage is that there is no time delay Restrictions Same as above and also no internal clock mode and no enable disable of the interrupts and the reset lines An additional slot in the base modul offers upgrading with the port analyzer to get timing and state of the CPU ports We use a different system for numbering the address and data lines as it is used in the PowerPC descriptions Our least significant bit is called DO or AO the MSB D31 or A31 Don t be confused if you find some differences between your databook and perhaps our peripheral window 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 9 Basics SYStem Mode EC E w sys syste ode Down RESet y Up Analyzer Monitor ResetDown ResetUp cpu type NoProbe PPC403 VAloneInt y Nodelay 25 MHz AloneExt Wait
25. or PowerPC 16 Basics 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 17 Basics Pode P598 6594 gega 6591 96954 Roa OOo 0599 Sor 1599 Basics 1989 2015 Lauterbach GmbH 8 ICE Emulator for PowerPC General SYStem Settings and Restrictions General Restrictions Turbo Control 400 fam ily Trace Information 400 family Exception Routines 500 800 family Clock Output 500 800 family Dualport ICE Emulator for PowerPC Make sure that you don t increase the debug clock without decreasing the internal wait states when the TURBO option is enabled If external wait states are used it is recommended to switch TURBO mode off The emulator needs the trace information on the TS pins You must switch the realtime debug mode in the input output configuration register to bus The CPU handles the debug mode similar to an exception Therefore stepping through an interrupt service routine is not possible because the execution of the RFI instruction forces the CPU to exit from debug mode Also modifications of SRRO and SRR1 are ignored when exiting debug mode If it is necessary to debug an exception routine you are allowed to do the following things If the CPU is not in a recoverable state after jump into the exception routine no breakpoints are allowed When the software of the exception has saved the MSR and IP and set the RI bit of the MSR the CPU is in recoverable state and one is allowed to b
26. r PowerPC 42 PortAnalyzer Compilers Language Compiler Company Option Comment ADA GNAT Free Software ELF DWARF Foundation Inc C CXPPC Cosmic Software ELF DWARF C CC Freescale XCOFF Semiconductor Inc C XCC V GAIO Technology Co SAUF Ltd C GREEN HILLS C Greenhills Software Inc ELF DWARF C GCC HighTec EDV Systeme ELF DWARF GmbH C MCCPPC Mentor Graphics ELF DWARF Corporation C ULTRA C Radisys Inc ROF C HIGH C Synopsys Inc ELF DWARF C DCPPC TASKING ELF DWARF C D CC Wind River Systems IEEE C D CC Wind River Systems COFF C D CC Wind River Systems ELF DWARF C GCC Free Software ELF DWARF Foundation Inc C GREEN HILLS Greenhills Software Inc ELF DWARF C C CCCPPC Mentor Graphics ELF DWARF Corporation C MSVC Microsoft Corporation 8 EXE CV5 WindowsCE C HIGH C Synopsys Inc ELF DWARF C D C Wind River Systems ELF DWARF C GCCPPC Wind River Systems ELF STABS C C CODEWARRIOR Freescale ELF DWARF Semiconductor Inc GCC GCC Free Software ELF DWARF Foundation Inc JAVA FASTJ Wind River Systems ELF DWARF ICE Emulator for PowerPC 1989 2015 Lauterbach GmbH 43 Compilers 3rd Party Tool Integrations CPU Tool Company Host ALL ADENEO Adeneo Embedded ALL X TOOLS X32 blue river software GmbH W
27. reak the routine After this break the old srr0 and srr1 registers which contain the information about the state of the CPU before the exception are overwritten and lost You can now step through the exception routine till the srrO and srr1 registers are recalled from the stack After this program line till the RFI instruction is reached stepping neither HLL nor ASM steps or breaks are not allowed anymore but it is possible to leave the exception routine with a go command While being in a non recoverable state you can t execute a go command The emulator needs the clockout frequency of the CPU you must not switch off the clockout pin for power saving purposes For the dualport access it is necessary for the emulator to have the control of the bus between the cycles of the CPU The emulator uses the normal bus arbitration signals to stop the CPU cycles If you want to use dualport access no device on your target may drive an active high signal on the bus because then the emulator would produce an bus collision Use pull up resistors instead 1989 2015 Lauterbach GmbH General SYStem Settings and Restrictions SYStem Option PreMap Address lines Format SYStem Option PreMap ON OFF The emulator can run in 24 and 32 Bit mode If the upper address lines are not used by the target system the pre mapper should be switched off We call the most significant address A31 in difference to the PPC description Bu
28. s width SYStem Option PreMap A0 A24 OFF A0 A32 ON SYStem Option PreMapMod Premapper mode Format SYStem Option PreMapMod ON OFF The emulator has two premapper The first is the regular premapper which uses the address lines 20 to 31 The second is the module premapper which has defined the 16 workbenches to the CS signals and the address A20 A11 of the PowerPC of the CPU It is not as flexible a the regular premapper but it is faster Here you can define your memory region for each workbench The sys o pmm switches between the pre mapper ram on the base and the project specific premap epld on the module Switch Mapper 0 15 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 20 General SYStem Settings and Restrictions For example A20 0 A20 1 CSO WBO WB1 CS1 WB2 WB3 CS2 WB4 WB5 CS3 WB6 WB7 CS4 WB8 WB9 CS5 WB10 WB11 CS6 WB12 WB13 CS7 WB14 WB15 You want to use CS2 at the address Off00000 If you want to use the module premapper type sys o pmm on map pre Ox0ff00000 0x0fffff 4 map Now your map pre window shows following logical Workbench Address physical Workbench 1 OFF00000 0FFFFFFF 4 If you want to use the regular premapper type sys o pmm off map pre Ox0ff00000440x0fffff map Now your map pre window shows following logical Workbench Address physical Workbench 1 OFF00000 0FFFFFFF 0 SYStem Option TestClock Clock test Format SYStem Option TestClock ON OFF
29. sible to reconstruct the instruction flow of the cpu even if the cpu runs in the internal cache To reconstruct this flow it is necessary that the cpu makes a show cycle after each indirect branch See register setting of the ICTRL register in your cpu manual and that the cpu makes one show cycle after the half of the clock trace The option VSYNC generates a VSYNC command to the cpu every 32000 clock cycles to force the cpu to make a show cycle SYStem Option CFLUSH Instruction cache flush Format SYStem Option CFLUSH ON OFF Only MPC860 MPC821 MPC505 If you use the internal instruction cache it is necessary to flush the cache before every go or hll step Option CFLUSH enables the cache flush software before each jump in Warning Problems can occur when the LCD driver of the MPC821 is active SYStem Option ONCE On circuit emulation Format SYStem Option ONCE ON OFF Only MPC860 MPC821 If you use the target connection via samtec connectors and leave the CPU on the target you can switch the CPU on the target to HI Z state For this option it is necessary that the BDM JTAG pins of the target CPU are in BDM mode after reset default and that the TRST pin is pulled to high with a resistor 1K 10K 1989 2015 Lauterbach GmbH ICE Emulator for PowerPC 23 General SYStem Settings and Restrictions SYStem Option BASE Peripheral base address Format SYStem Option BASE lt Value gt
Download Pdf Manuals
Related Search