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uPD780852 Subseries (8-Bit Single-Chip) PUM

1. HL C HL C Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM area is accessed 3 Except r A Remark One instruction clock cycle is one cycle of the CPU clock fceu selected by the processor clock control register PCC 284 Preliminary User s Manual U14581EJ3V0UM00 CHAPTER 23 INSTRUCTION SET Instruction Group Mnemonic Operands rp word Operation rp word saddrp word saddrp lt word sfrp word sfrp word AX saddrp AX lt saddrp saddrp AX saddrp AX AX sfrp c sfrp sfrp sfrp AX AX rp AX c rp rp AX AIR rp AX laddr16 lt addr16 laddr16 addr16 rp 8 bit A byte A CY byte saddr byte saddr CY lt saddr byte A r CY A r r lt saddr A CY amp A laddr16 A A addr16 A HL A HL byte A CY A HL byte A HL B A CY A HL A CY HL B A HL C A CY A HL C operation A byte A CY A byte CY saddr byte saddr
2. 60 4 1 FUNCHONS 76 4 2 ERR 77 5 1 Glock Generator Configuration seision dave sua 91 5 2 Relation between CPU Clock and Minimum Instruction Execution Time 92 5 3 Maximum Time Required for Switching CPU 98 6 1 Timer Event Counter Operalloris enit ertet ee Eee e shasqa as 102 6 2 seem MH eerie REDDE 104 7 1 9 Bit Timer 1 TMI GonflgufaliOn carro 114 8 1 8 Bit Timer Event Counters 2 TM2 and 3 Configurations 2 123 9 1 Interval Timer Interval TIME ioi ua retire nee ter ter Ai care iav EE re eee 138 9 2 Watch Timer Configuration 2 u uu u UD 138 9 3 Interval Timer Interval Time 4 140 10 1 Watchdog Timer Runaway Detection Time 144 10 2 Interval TIME sonurin Hec eom etc cani eiue ERE LE ELE IRE E CH PEEL LEES CERE E Lec 144 10 3 Watchdog Timer Gonfig Ur allODy coitu potet I Res 145 10 4 Watchdog Timer Runaway Detection 147 10 5 Interval Timer Interval Time ILU ss tit retine tegere Leanne eene ERRE aa 148 11 1 Clock O
3. 148 CHAPTER 11 CLOCK OUTPUT 149 11 1 Clock Output Controller Functions u u u 149 11 2 Clock Output Controller Configuration ll u u u u u 149 11 3 Clock Output Control Controller Registers u u u 150 Preliminary User s Manual U14581EJ3V0UM00 15 11 4 Clock Output Controller Operation u u u u u u T 152 CHAPTER 12 A D CONVERTER iiie tried einen tasas aaia EES aHa 153 12 1 A D Converter Functions u u u uu u u u u T 153 12 2 A D Converter Configuration U U 155 12 3 A D Converter Control Registers eese u u u uu u J 157 12 4 A D Converter Operations U u u uu u u u uu u J 160 12 4 1 Basic operations of A D converter 2 160 12 4 2 Input voltage and conversion results 162 12 4 3 A D converter operation 163 12 5 A D Converter Cautions 165 12 6 Cautions o
4. 39 2 2 5 P4010 PAA POM iota uy sib slice tcx sassa E RUE 39 22 6 P50 t0 P54 POM uu Sis N II 40 2 2 7 PCO Port ud He EE iH Ree a 40 22 9 Ol LOL Or MONO uice reete dei ILI LI 41 2 2 9 P90 to P97 POLT ce edt aie exp rea edad 41 22 O COMO cec 41 naa EE 41 ZED M2 ANREP 41 22 d 3A SS pe rcs dL Le tcd 41 TA RESET M P 41 o 2 5 AAN Be eM EID I E LI LS 41 2 2 46 9M VDDESG eie tested anii s M M 42 2 2 47 IM MI IM MANI 42 2 2 MOP DIDO Sasa e oe ee LLL 42 2 219 WROUT PE 42 212 20 A E E 42 2221 VepTuPD78F0852 u MU LO EE 42 2 2 22 IG Mask ROM versiort only 2 dens tare danny oad eundo re anas 42 2 3 Input Output Circuits and Recommended Connection of Unused Pins 43 CHAPTER CPU ARCHITECTURE eer LLnic cereo 47 3 1 Memory 5 uu
5. CLPO 0 1 y 049 LE LE LLL LLL CLPO 1 Write SIO2 55H 1 0 1 1 Start trigger operation timing dete timing X SSH XABHX 56H XADH SAH BSH GAH DSH XAAH SIRB2 INTCSI2 interrupt request generated at rising edge 512 502 6 Hardware detection in error status Serial interface SIO2 has a function for checking whether an overflow error has occurred While serial data being transferred to the serial receive data buffer register SIRB2 has not yet been read the overflow flag SDOF is set to 1 if the capture strobe of the LSB of the serial data to be transferred next has occurred If an overflow has occurred the received serial data is not transferred to SIRB2 Therefore data that has already been received and transferred to SIRB2 can be read In this way the loss of receive data is prevented even if an overflow error occurs SDOF is cleared by reading the serial receive data buffer status register SRBS2 If SIRB2 is read to monitor the status of serial interface 5102 always monitor SRBS2 to check whether an interrupt request overflow error has occurred 198 Preliminary User s Manual U14581EJ3VOUMOO CHAPTER 14 SERIAL INTERFACE SIO2 Q WS 2 s Figure 14 8 shows the status of each register 5102 SIRB2 SRBS2 during receive operation Figure 14 8 Receive Operation 1 S 6 8 11 DATA1 DA
6. ire ras 194 CHAPTER 15 SERIAL INTERFACE SIOS 201 15 1 Serial Interface Functions U u enne u u u u u nns 201 15 2 Serial Interface sassa asss 202 15 3 Serial Interface Control Register l l u u u u u 203 15 4 Serial Interface Operations IU III ee cenae 204 15 4 1 Operation Stop S u s es vei ener erra cade deb yen de E 204 15 4 2 3 wire serial Imop86_ 7 usss assasyasassasatykhoasasquqasauqhuamaakasssqupsspayasqasssqaassqadasaas 205 CHAPTER 16 LCD CONTROLLER DRIVER l u u u u u uu u 207 16 1 LCD Controller Driver 207 16 2 LCD Controller Driver Configuration l u u u u 208 16 3 LCD Controller Driver Control Registers l l l l u u u 210 16 4 LCD Controller Driver Settings U l l u u u u u uu 2
7. 4 80 98 5 6 2 aee ike 99 14 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 6 16 TIMER 0 U 101 6 1 Outline of Internal Timer of PD780852 Subseries 101 6 2 16 Bit Timer 0 Functions U u nnn nnne 103 6 3 16 Bit Timer 0 Configuration 104 6 4 16 Bit Timer 0 Control Registers u u 105 6 5 16 Bit Timer 0 Operations U U u u u u u u u 108 6 5 1 Pulse width measurement 108 6 6 16 Bit Timer 0 TMO Cautions Ju neuter tiroir anten ena aaa Exe 111 CHAPTER 7 8 BIT TIMER T TMI 2 ii ertet nre ex sapu 113 7 1 8 Bit Timer 1 TM1 Fu ctions u lU UU 113 7 2 8 Bit Timer 1 TM1 Configuration U uuu u u u 114 7 3 8 Bit Timer 1 TM1 Control Registers u uu u u u 115 7 4 8 Bit Timer 1 TM1 Operations 117 7 4 1 8 bit interval timer operation 4
8. 47 3 1 Internal program Memory eA oer bapa 50 3 1 2 Internal data memory space 51 3 1 3 Special function register SFR area u LU l nennen 51 3 1 4 Data memory addressing u Q u uu Sa a daie 52 3 2 1 gt 55 a eiecit Im 55 Preliminary User s Manual 1714581 00 00 13 3 2 2 General registers uci eed hua Ee aS cvv dua te 58 3 2 3 Special function registers SFRS 444022 2 1 1010 59 3 3 Instruction Address Addressing 11 ener 63 3 9 1 Relative addressing iie 63 3 39 2 Immediate addressing dde sut Eun 64 3 9 9 EE coe LE EE 65 3 34 Hegister addressing u u en fes
9. 159 12 7 Basic Operation of 8 Bit A D Converter 161 12 8 Relation between Analog Input Voltage and A D Conversion 162 12 9 AJD GonVersiol uiae D utu a DS DS hu en tei tb es HII 164 12 10 Example of Method of Reducing Current Consumption in Standby Mode 165 12 11 Analog Input Pin LLL nnn 166 12 12 A D Conversion End Interrupt Request Generation 167 12 13 D A Converter Mode Register DAM1 Format u 168 13 1 Serial Interface UART Block 169 13 2 Asynchronous Serial Interface Mode Register ASIM 172 13 3 Asynchronous Serial Interface Status Register ASIS Format 173 13 4 Baud Rate Generator Control Register BRGC Format 174 13 5 Error Tolerance When k 0 Including Sampling 180 13 6 Format of Transmit Receive Data in Asynchronous Serial Interface 181 13 7 Asynchronous Serial Interface Transmit Completion Interrupt 183 13 8 Asyn
10. 115 7 3 8 Bit Timer Mode Control Register 1 1 Format 116 7 4 Interval Timer Operation Timings 117 7 5 8 Bit Timer 1 TM1 Start Timing 120 7 6 Timing after Compare Register Change during Timer Count Operation 120 8 1 8 Bit Timer Event Counter 2 TM2 Block 2 44000 00 121 8 2 8 Bit Timer Event Counter Block Diagram eesseeeeeneneeneenen enne 122 8 3 Timer Clock Select Register 2 TCL2 Formatl u 124 8 4 Timer Clock Select Register Formatl u 125 8 5 8 Bit Timer Mode Control Registers 2 3 TMC2 TMC3 Format 126 8 6 Port Mode Register 4 PM4 4 40 00000 127 8 7 Interval Timer Operation Timings sseessessesseeeenenenenenneeneenneee nennen rennen rennen nnne 128 8 8 External Event Counter Operation Timings with Rising Edge Specified 131 8 9 PWM Output Operation TIMING u L L a a rbi re DOR ua duis 133 8 10 Operation Timing by Change of CRn nnne nnne trennt innen nnne 134 8 11 8 Bit Counters 2 and 3 TM2 and Start 135 8 12 Timing after Compare Register Change during Timer Count O
11. TlOm pin input 4 ES J c 1 Value loaded to CROm po ICI LIMEN D2 DEEE I l INTTMOm _ V mF nT T Tionpininput i i C ES 1 1 J un Value loaded to CROn D1 INTTMOn MEM 1 1 es INTOVE MEM 5 1 dd s 01 00 10000H D2 xt D3 D2 xt 10000H D1 02 1 x t Remark 0 2 1 2 110 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 6 16 BIT TIMER 0 TMO 6 6 16 Bit Timer 0 TMO Cautions 1 Timer start errors An error with a maximum of one clock may occur until counting is started after timer start This is because the 16 bit timer register TMO is started asynchronously with the count pulse Figure 6 10 16 Bit Timer Register Start Timing TMO count value 0000H Timer start 2 Capture register data retention timings If the valid edge of the TlOn P4n pin is input during 16 bit capture register On CROn read CROn performs capture operation but the capture value is not guaranteed However the interrupt request flag INTTMOn is set upon detection of the valid edge Figure 6 11 Capture Register Data Retention Timing contouse TLE LE LE LEU count value N 3 2 1 N XN 1 o
12. amma TOL reor roc Timer clock select register 1 TCL1 Timer mode control register TMC1 Internal bus Preliminary User s Manual U14581EJ3V0UMOO 113 CHAPTER 7 8 BIT TIMER 1 TM1 7 2 8 Bit Timer 1 TM1 Configuration 8 bit timer 1 TM1 consists of the following hardware Table 7 1 8 Bit Timer 1 TM1 Configuration Item Configuration Timer register 8 bit counter 1 TM1 Register 8 bit compare register 1 CR1 Control register Timer clock select register 1 TCL1 8 bit timer mode control register 1 TMC1 1 8 bit counter 1 TM1 2 1 is an 8 bit read only register which counts the count pulses The counter is incremented in synchronization with the rising edge of the count clock When count value is read during operation count clock input is temporary stopped and then the count value is read In the following situations the count value is set to 00H lt gt RESET input 2 TCE1 3 Match between TM1 and CR1 8 bit compare register 1 CR1 The value set in the CR1 is constantly compared with the 8 bit counter 1 TM1 count value and an interrupt request INTTM1 is generated if they match It is possible to rewrite the value of CR1 within to during count operation 114 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 7 8 BIT TIMER 1 TM1 7 3 8 Bit Timer 1 TM1 Control Registers The following two types of registers are used to con
13. ee decies pee FASAH S18 P82 es A See FA59H S19 P81 ecc ca e S RA CERE T PIPER E NEN MEME COM3 COM2 COM COMO Caution higher 4 bits of the LCD display data memory do not incorporate memory Be sure to set them to 0 Preliminary User s Manual U14581EJ3VOUMOO 213 CHAPTER 16 LCD CONTROLLER DRIVER 16 6 Common Signals and Segment Signals An individual pixel on an LCD panel lights when the potential difference of the corresponding common signal and segment signal reaches or exceeds a given voltage the LCD drive voltage Vico The light goes off when the pote ntial difference becomes Vico or lower As an LCD panel deteriorates if a DC voltage is applied in the common signals and segment signals it is driven by AC voltage 1 Common signals For common signals the selection timing order is as shown in Table 16 3 and operations are repeated with these as the cycle Table 16 3 COM Signals COMO 1 2 COM3 Time division 4 time division r LLL 2 Segment signals 3 214 Segment signals correspond to a 20 byte LCD display data memory FA59H to FA6CH Each display data memory bit 0 bit 1 bit 2 and bit 3 is read in synchronization with the COMO COM1 2 and COMS timings respectively and if the value of the bit is 1 it is converted to the selection voltage If the value of the bit is
14. 5 78 0 Host Machine OS Supply Medium PC 9800 Series Windows Japanese version Note 3 5 inch 2HD FD IBM PC AT and compatibles Windows Japanese version Note 3 5 inch 2HC FD Windows English version Note Note WindowsNT is not supported 302 Preliminary User s Manual U14581EJ3VOUMOO APPENDIX A DEVELOPMENT TOOLS A 3 2 Software 2 2 ID78K0 NS Integrated Debugger Supports in circuit emulator IE 78K0 NS ID78KO Integrated Debugger Supports in circuit emulator IE 78001 R A This is a control program used to debug the 78K 0 Series The graphical user interfaces employed are Windows for personal computers and OSF Motif for EWSs offering the standard appearance and operability typical of these interfaces Further debugging functions supporting C language are reinforced and the trace result can be displayed in C language level by using a window integrating function that associates the source program disassemble display and memory display with the trace result In addition it can enhance the debugging efficiency of a program using a real time OS by incorporating function expansion modules such as a task debugger and System performance analyzer This debugger is used in combination with an optional device file DF780852 Part Number SxxxxID78KO NS uS xxxxlID78K0 Remark in the part number differs depending on the host machine and OS used uSxxxxID78K0 NS
15. 94 5 5 Incorrect Examples of Resonator Connection cc ccccesccecesceeeeeeeeeeeeeeeeeeeeeeceeeeceeeeeseeeeeseeeseneeess 95 5 6 Switching CRU 99 6 1 TMO Block pep 103 6 2 16 Bit Timer Mode Control Register TMCO 105 6 3 Capture Pulse Control Register 106 6 4 Prescaler Mode Register Format 2 107 6 5 Port Mode Register 4 PM4 107 6 6 Configuration Diagram for Pulse Width Measurement by Free Running Counter 108 6 7 Pulse Width Measurement Operation Timing by Free Running Counter and One Capture Register with Both Edges 108 Preliminary User s Manual U14581EJ3V0UMOO 19 LIST OF FIGURES 2 5 Figure No Title Page 6 8 CROm Capture Operation with Rising Edge Specified 2 109 6 9 Pulse Width Measurement Operation Timing by Free Running Counter with Both Edges Specified eeessssesssssssesseeseeenene eene nennen nnne nnn eene nennen 110 6 10 16 Bit Timer Register Start TIMING 111 6 11 Capture Register Data Retention Timing 2 u 111 721 8 Brt Timer t TM1 Block Diagram a iter teet ee o eres 113 7 2 Timer Clock Select Register 1 TCL1 Forimat_
16. Preliminary User s Manual U14581EJ3V0UMOO 293 CHAPTER 23 INSTRUCTION SET 2 16 bit instructions MOVW XCHW ADDW SUBW CMPW PUSH POP INCW DECW Second Operand 1st Operand laddr16 MOVW Note Note Only when rp DE HL 3 Bit manipulation instructions MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 BF BTCLR Second Operand First Operand sfr bit saddr bit PSW bit HL bit addr16 saddr bit 294 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 23 INSTRUCTION SET 4 Call branch instructions CALL CALLF CALLT BR BC BNC BZ BNZ BT BF BTCLR DBNZ Second Operand laddr16 laddr11 addr5 addr16 First Operand Basic instruction Compound instruction 5 Other instructions ADJBA ADJBS BRK RET RETI RETB SEL NOP El DI HALT STOP Preliminary User s Manual U14581EJ3VOUMOO 295 MEMO 296 Preliminary User s Manual U14581EJ3VOUMOO APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the wPD780852 Subseries Figure A 1 shows the development tool configuration Preliminary User s Manual U14581EJ3V0UM00 297 APPENDIX A DEVELOPMENT TOOLS Figure A 1 Development Tool Configuration Language Processing Software Assembler package C compiler package C library source
17. gt Used when normal instruction is executed ISP Priority of Interrupt Currently Being Serviced High priority interrupt servicing low priority interrupt disabled Interrupt request not acknowledged or low priority interrupt servicing all maskable interrupts enabled E Interrupt Request Acknowledge Enable Disable Disabled Enabled Preliminary User s Manual U14581EJ3V0UM00 251 CHAPTER 19 INTERRUPT FUNCTIONS 19 4 Interrupt Servicing Operations 19 4 1 Non maskable interrupt request acknowledge operation A non maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledge disable state It does not undergo interrupt priority control and has highest priority over all other interrupts If a non maskable interrupt request is acknowledged the contents are saved into the stacks in the order of PSW then PC the IE flag and ISP flag are reset to 0 and the contents of the vector table are loaded into PC and branched A new non maskable interrupt request generated during execution of a non maskable interrupt servicing program is acknowledged after the current execution of the non maskable interrupt servicing program is terminated following RETI instruction execution and one main routine instruction is executed However if a new non maskable interrupt request is generated twice or more during non maskable interrupt servicing program execution only one non maskable interru
18. 16 8 Display Mode 16 8 1 4 time division display example Figure 16 10 shows the connection of a 4 time division type 10 digit LCD panel with the display pattern shown in Figure 16 9 with the uPD780852 Subseries segment signals SO to 519 and common signals COMO to COM3 The display example is 1234567890 and the display data memory contents addresses FA59H to FA6CH correspond to this An explanation is given here taking the example of the 5th digit 6 In accordance with the display pattern in Figure 16 9 selection and non selection voltages must be output to pins S8 and S9 as shown in Table 16 6 at the COMO to COM3 common signal timings Table 16 6 Selection and Non Selection Voltages COMO to COM3 Segment S Selection NS Non selection From this it can be seen that 0101 must be prepared in the display data memory address FA64H corresponding to S8 Examples of the LCD drive waveforms between S8 and the COMO and COM signals are shown in Figure 16 11 for the sake of simplicity waveforms for COM2 and COMG have been omitted When S8 is at the selection voltage at the COMO selection timing it can be seen that the AC square wave which is the LCD illumination ON level is generated Figure 16 9 4 Time Division LCD Display Pattern and Electrode Connections COMO 1 2 O cows Sen 1 0109 218 Preliminary User s Manual U14581E
19. 218 17 1 Sound Generator Configuratioli 5 224 17 2 Maximum Value and Minimum Value of Buzzer Output Frequency 2 226 18 1 Meter Controller Driver Configuration sess nennen 232 19 1 6 ae 242 19 2 Flags Corresponding to Interrupt Request Sources a 245 19 3 Times from Generation of Maskable Interrupt Request until Servicing 255 19 4 Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing 258 20 1 HALT Mode Operating Status eL 265 20 2 Operation after HALT Mode Glear E HERE EDEN cet 267 20 3 STOP Mode Operating 268 20 4 Operation after STOP Clear iconic icio dient Ain ae ada Day Ee EO 270 21 1 Hardware Status after Reset sse innen nnne enne nenne nnne 273 22 1 Differences between wPD78F0852 and Mask ROM 275 22 2 Memory Size Switching Register Settings u L uuu au 276 22 3 Transmission Method LISt sione aaae Ernte ee te ue ek enc
20. 4 Current consumption in standby mode A D converter stops operating in the standby mode Atthis time current consumption can be reduced by setting bit 7 ADCS1 of the A D converter mode register ADM1 to 0 to stop conversion Figure 12 10 shows how to reduce the current consumption in the standby mode Figure 12 10 Example of Method of Reducing Current Consumption in Standby Mode AVner P ch lt ADCS1 Series resistor string AVss Input range of ANI0 to ANIA Keep the input voltage of ANIO to ANI4 within the rated range If a voltage outside the rated range is input the conversion value of that channel is undefined and the values of the other channels may also be affected Contending operations 1 Contention between A D conversion result register ADCR1 write and ADCR1 read by instruction upon the end of conversion ADCR 1 read is given priority After the read operation the new conversion result is written to ADCR1 2 Contention between ADCR1 write and A D converter mode register ADM1 write or analog input channel specification register ADS1 write upon the end of conversion ADM or ADS1 write is given priority ADCR1 write is not performed nor is the conversion end interrupt signal INTAD generated 3 If the A D converter mode register ADM1 or analog input channel specification register ADS1 is written as soon as the A D conversion end interrupt INTAD has occurred the contents of
21. Rising edge Setting prohibited Both falling and rising edges Count Clock Selection Caution Timer operation must be stopped before setting PRMO Remarks 1 fx Main system clock oscillation frequency 2 n 0to2 4 Port mode register 4 4 This register sets port 4 to the input or output mode in 1 bit units To use the 40 00 to P42 TIO2 pins as timer input pins set PM40 to 42 to 1 PM4 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets 4 to FFH Figure 6 5 Port Mode Register 4 PM4 Format Address FF24H After Reset FFH R W Symbol 7 6 5 4 3 2 1 0 P4n Pin I O Mode Selection n 0 to 4 Output mode output buffer on Input mode output buffer off Preliminary User s Manual U14581EJ3VOUMOO 107 CHAPTER 6 16 BIT TIMER 0 TMO 6 5 16 Bit Timer 0 TMO Operations 6 5 1 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the 00 40 to TIO2 P42 pins using the 16 bit timer register TMO TMO is used in free running mode 1 Pulse width measurement with free running counter and one capture register TIOO When the edge specified by prescaler mode register PRMO is input to the 00 40 pin the value of is taken into 16 bit capture register 00 CROO and an external interrupt request signal INTTMOO is set Any of three edge specifications can be selected rising falling
22. Setting lt gt lt 2 gt lt 3 gt lt 4 gt 5 Set port latch P43 P44 and port mode register 4 PM43 44 to 0 Set active level width with 8 bit compare register CRn Select count clock with timer clock select register n TCLn Set active level with bit 1 TMCn1 of TMCn Count operation starts when bit 7 TCEn of TMCn is set 1 Set TCEn to 0 to stop count operation PWM output operation 1 2 lt 3 gt lt 4 gt lt 5 gt PWM output output from TlOn outputs inactive level after count operation starts until overflow is generated When overflow is generated the active level set in lt 1 gt of setting is output The active level is output until CRn matches the count value of 8 bit counter n TMn After the CRn matches the count value PWM output outputs the inactive level again until overflow is generated PWM output operation 2 and 3 are repeated until the count operation stops When the count operation is stopped with TCEn 0 PWM output changes to inactive level Remark 2 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 8 8 TIMER EVENT COUNTERS 2 TM2 AND 3 a PWM output basic operation Figure 8 9 PWM Output Operation Timing i Basic operation active level H MUUL ULL oe 8 Ta CRN N Cam sss cem IEEE UE i __ _
23. The operating status in the STOP mode is described below Table 20 3 STOP Mode Operating Status STOP Mode Setting During STOP Instruction Execution Using Main System Clock Clock generator Only main system clock oscillation is stopped CPU Operation stops Port Output latch Status before STOP mode setting is held 16 bit timer Operation stops 8 bit timer Operable only when 2 and are selected as count clock Watch timer Operation stops Watchdog timer Operation stops A D converter Operation stops Serial interface Other than UART Operable only when externally supplied input clock is specified as the serial clock UART Operation stops LCD controller driver Operation stops External interrupt Operable Sound generator Operation stops Meter controller driver Operation stops 268 Preliminary User s Manual U14581EJ3VOUMOO CHAPTER 20 STANDBY FUNCTION 2 STOP mode clear The STOP mode can be cleared with the following two types of sources a Clear upon unmasked interrupt request An unmasked interrupt request is used to clear the STOP mode If interrupt acknowledge is enabled after the lapse of oscillation stabilization time vectored interrupt service is carried out If interrupt acknowledge is disabled the next address instruction is executed Figure 20 4 STOP Mode Clear upon Interrupt Generation Wait Time set by OSTS S
24. 15 4 Serial Interface Operations This section explains the two modes of the serial interface SIO3 15 4 1 Operation stop mode This mode is used when serial transfers are not performed to reduce power consumption In the operation stop mode the P50 SCK3 P51 SO3 and P52 SI3 pins can be used as normal I O port pins 1 Register settings Operation stop mode is set with the serial operation mode register 3 CSIM3 CSIMG is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears CSIM3 to 00H Address FF84H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 5103 Operation Enable Disable Specification CSIE3 Shift Register Operation 0 Operation disabled 1 Operation enabled Caution Bits 3 to 6 must be set to 0 204 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 15 SERIAL INTERFACE SIO3 15 4 2 3 wire serial I O mode The 3 wire serial I O mode is useful when connecting a peripheral I O device that includes a clocked serial interface a display controller etc This mode executes data transfers via three lines a serial clock line SCK3 serial output line SO3 and serial input line SI3 1 Register settings 3 wire serial mode is set with the serial operation mode register 3 CSIM3 CSIMG is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears CSIMS to 00H Caution the 3 wire serial I O mode set the port mode register PM5X as foll
25. CHAPTER 21 RESET FUNCTION Figure 21 2 Timing of Reset by RESET Input FAZ VF N NL Oscillation Misit Normal operation 2 XS Reset processing RESET Internal Y reset signal i Port pin gt m CS Figure 21 3 Timing of Reset due to Watchdog Timer Overflow JAVANA mwmw w Oscillation Reset period stabilization Normal operation Oscillation stop time wait Reset processing Watchdog timer overflow i Normal operation Normal operation Internal reset signal Port pin Figure 21 4 Timing of Reset in STOP Mode by RESET Input X1 STOP instruction execution Oscillati Stop status Reset period __ scil ation Normal operation i Oscillation stop Stabilization Reset processing Normal operation Oscillation stop time wait RESET hd Internal reset signal Delay Delay 272 Preliminary User s Manual U14581EJ3VOUMOO CHAPTER 21 RESET FUNCTION Table 21 1 Hardware Status after Reset 1 2 Hardware Status after Reset Program counter PC Note 1 Contents of reset vector table 0000H 0001H are set Stack pointer SP Undefined Program status word PSW 02H RAM Data memory Undefined Note 2 General register Undefined Note 2 Port Output latch 00H Port mode registers PMO to PM6 PM8
26. d SCK2 Serial interface serial clock input output pin 2 2 2 P10 to P14 Port 1 These pins constitute a 5 bit input only port In addition they also function as A D converter analog input pins The following operation modes can be specified in 1 bit units 1 Port mode In this mode P10 to P14 function as a 5 bit input only port 2 Control mode In this mode P10 to P14 function as A D converter analog input pins ANIO to 14 38 Preliminary User s Manual U14581EJ3VOUMOO CHAPTER 2 PIN FUNCTION 2 2 3 P20 to P27 Port 2 These pins constitute an 8 bit output only port In addition they also function as PWM output pins for meter control The following operation modes can be specified in 1 bit units 1 Port mode In this mode P20 to P27 function as an 8 bit output only port They go into a high impedance state when 1 is set to port mode register 2 PM2 2 Control mode In this mode P20 to P27 function as PWM output pins SM11 to SM14 and SM21 to 5 24 for meter control 2 2 4 P30 to P37 Port 3 These pins constitute an 8 bit output only port In addition they also function as PWM output pins for meter control The following operation modes can be specified in 1 bit units 1 Port mode In this mode P30 to P37 function as an 8 bit output only port They go into a high impedance state when 1 is set to port mode register 3 PM3 2 Control mode In this mode P30 to P37 function as PWM output pins SM31 to
27. fsa2 fx 8 00 MHz fx 8 38 MHz Max kHz Min KHz Max kHz Min KHz Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 17 SOUND GENERATOR 2 Sound generator buzzer control register SGBR SGBR is a register that sets the basic frequency of the sound generator output signal SGBR is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears SGBR to 00H Figure 17 4 shows the SGBR format Figure 17 4 Sound Generator Buzzer Control Register SGBR Format Address FF95H After Reset OOH R W Symbol 7 6 5 4 3 2 1 0 Buzzer Output Frequency kHz Nete fx 8 MHz fx 8 38 MHz 0 0 0 0 0 0 0 0 Note Output frequency where SGCLO SGCL1 and SGCL2 are all 0s Cautions 1 When rewriting SGBR to other data stop the timer operation TCE z 0 beforehand 2 Bits 4 to 7 must be set to 0 3 Sound generator amplitude register SGAM SGAM is a register that sets the amplitude of the sound generator output signal SGAM is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears SGAM to 00H Figure 17 5 shows the SGAM format Preliminary User s Manual U14581EJ3VOUMOO 227 CHAPTER 17 SOUND GENERATOR Figure 17 5 Sound Generator Amplitude Register SGAM Format Address FFC1H After Reset OOH R W Symbol 7 6 5 4 3 2 1 0 SGAM SGAM4 SGAM3 SGAM2 SGAM1 SGAMO o
28. 1 can be used for an interval timer see CHAPTER 7 8 BIT TIMER 1 1 8 bit timer event counters 2 TM2 and 3 TM3 2 and TM3 can be used to serve as an interval timer and an external event counter and to output square waves with any selected frequency and PWM see CHAPTER 8 8 BIT TIMER EVENT COUNTERS 2 TM2 AND 3 TM3 Watch timer This timer can set a flag every 0 5 sec and simultaneously generates interrupt request at the preset time intervals see CHAPTER 9 WATCH TIMER Watchdog timer This timer can perform the watchdog timer function or generate non maskable interrupt request maskable interrupt request and RESET at the preset time intervals see CHAPTER 10 WATCHDOG TIMER Clock output controller Clock output supplies other devices with the divided main system clock see CHAPTER 11 CLOCK OUTPUT CONTROLLER Preliminary User s Manual U14581EJ3V0UM00 101 CHAPTER 6 16 BIT TIMER 0 TMO Operating mode Table 6 1 Timer Event Counter Operations Interval timer 2 channels 8 Bit Timer TM1 1 channel 8 Bit Timer Event Counter TM2 2 channels Watch Timer 1 channel Note 1 Watchdog Timer 1 channel Note 2 External event counter O Function Timer output PWM output O Pulse width measurement Square wave output Divided output Interrupt request Notes 1 Watch timer can perform both watch timer and interval timer functions at the same tim
29. A Setting prohibited Cautions 1 Writing to BRGC during a communication operation may cause abnormal output fromthe baudrate generator and disable further communication operations Therefore do not write to BRGC during a communication operation 2 Bit 7 must be set to 0 Remarks 1 fx Main system clock oscillation frequency 2 fsck Source clock for 5 bit counter 3 n Value set via TPSO to TPS2 1 lt n lt 8 4 Value set via MDLO to MDL3 0 k x 14 178 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 13 SERIAL INTERFACE UART The transmit receive clock that is used to generate the baud rate is obtained by dividing the main system clock Use of main system clock to generate a transmit receive clock for baud rate The main system clock is divided to generate the transmit receive clock The baud rate generated by the main system clock is determined according to the following formula Baud rate X Hz 2 k 16 fx Main system clock oscillation frequency n Value set via TPSO to 52 1 lt lt 8 For details see Table 13 2 k Value set via MDLO to MDL3 0 k lt 14 Table 13 2 shows the relation between the 5 bit counter s source clock assigned to bits 4 to 6 TPSOto TPS2 of BRGC and the n value in the above formula Table 13 2 Relation between 5 Bit Counter s Source Clock and Value Remark fx Main system clock oscillatio
30. CY lt saddr byte CY A CY A r4 CY r A CY A CY lt A saddr CY A laddr 6 NM W M M M P A CY A addr16 CY HL A CY A HL CY HL byte A CY amp A HL B CY A A A HL B A HL C hw j OO j O CO OoOo CO OO O A CY lt HL byte CY A CY HL CY Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM area is accessed 3 Only when rp BC DE or HL 4 Except r A Remark One instruction clock cycle is one cycle of the CPU clock fceu selected by the processor clock control register PCC Preliminary User s Manual U14581EJ3VOUMOO 285 CHAPTER 23 INSTRUCTION SET Instruction Group Mnemonic Operands A byte A Operation A CY A byte saddr byte saddr CY lt saddr byte A r A CY A r r A A saddr A CY A saddr A laddr16 A CY addr16 A HL A HL byte A CY lt A HL byte A HL B A CY A HL A CY A HL B A HL C A CY A HL C A byte A CY A
31. HP9000 Series 700 HP UX Rel 9 05 DAT DDS SPARCstation SunOS Rel 4 1 4 Solaris Rel 2 5 1 3 5 inch 2HC FD 1 4 inch CGMT NEWS RISC Note WindowsNT is not supported A 2 Flash Memory Writing Tools Flashpro 111 NEWS OS Rel 6 1 3 5 inch 2HC FD Dedicated flash writer for microcontrollers with on chip flash memory part number FL PR3 PG FP3 Flash Writer Remark FL PR3 is a product of Naito Densei Machida Mfg Co Ltd For details contact Naito Densei Machida Mfg Co Ltd TEL 81 44 822 3813 300 Preliminary User s Manual U14581EJ3V0UMOO APPENDIX A DEVELOPMENT TOOLS A 3 Debugging Tools A 3 1 Hardware IE 78K0 NS This in circuit emulator is used to debug hardware and software when developing application In circuit Emulator systems using the 78K 0 Series It is compatible with the integrated debugger ID78K0 This emulator is used in combination with an emulation probe and an interface adapter for connection to a host machine IE 70000 MC PS B This is an adapter for power supply from a receptacle of 100 to 240 VAC Power Unit IE 70000 98 IF C This adapter is required when using the PC 9800 Series computer except notebook type as Interface Adapter the IE 78KO NS host machine It is compatible with the C bus IE 70000 CD IF A These PC card and interface cable are required when using a notebook as the IE 78K0 NS PC Card
32. PC AT is a trademark of International Business Machines Corporation HP9000 series 700 and HP UX are trademarks of Hewlett Packard Company SPARCstation is a trademark of SPARC International Inc SunOS and Solaris are trademarks of Sun Microsystems Inc Ethernet is a trademark of Xerox Corporation NEWS and NEWS OS are trademarks of Sony Corporation OSF Motif is a trademark of OpenSoftware Foundation Inc TRON is an abbreviation of The Realtime Operating system Nucleus ITRON is an abbreviation of Industrial TRON Preliminary User s Manual U14581EJ3V0UMOO 5 The export of these products from Japan is regulated by the Japanese government The export of some or all of these products may be prohibited without governmental license To export or re export some or all of these products from a country other than Japan may also be prohibited without a license from that country Please call an NEC sales representative License not needed uPD78F0852GC 8BT The customer must judge the need for license uPD780851GC A xxx 8BT 7808520 8 The information in this document is current as of October 2000 The information is subject to change without notice For actual design in refer to the latest publications of NEC s data sheets or data books etc for the most up to date specifications of NEC semiconductor products Not all products and or types are available in every country Please check with an NEC sales representative fo
33. Serial receive data buffer register SIRB2 Control registers Serial operation mode register 2 CSIM2 Serial receive data buffer status register SRBS2 Port mode register 0 PMO Serial I O shift register 2 5102 This is an 8 bit register that performs parallel serial conversion and serial transmit receive shift operations in synchronization with the serial clock SIO2 is set with an 8 bit memory manipulation instruction A transmit receive operation is started by writing or reading data to or from SIO2 when bit 7 CSIE2 of the serial operation mode register 2 CSIM2 is 1 When the received data is completely stored in SIO2 if SDVA bit 1 of the receive data buffer status register SRBS2 is 0 the contents of SIO2 are immediately transferred to the receive data buffer register SIRB2 If SDVA is 1 the received data is held in SIO2 RESET input clears SIO2 to 00H Cautions 1 Do not access read write SIO2 during a transmit receive operation shift operation 2 When a transmit receive operation starts writing to SIO2 do not access read write SIO2 before a transmit completion interrupt INTCSI2 occurs in the transmit receive mode MODE2 1 3 If the external clock mode CLPH 1 is selected in the slave mode SCL20 0 5 21 z 0 do not read the data of SIO2 directly The value of SIO2 may not coincide with the value transferred to SIRB2 To obtain the accurate value read the data of SIRB2 Serial rece
34. byte CY saddr byte saddr CY lt saddr byte CY A r A CY A r CY r CYer A CY A saddr A CY A saddr A addr16 o m NI N N N N A CYA CY A HL A CY lt A HL A CY A HL byte CY A HL byte A HL B A CY HL CY A HL C A CY A HL CY A byte A A byte saddr byte saddr lt saddr byte lt A r lt r A saddr A laddr16 I N N N N N lt A addr16 lt AA HL lt A HL byte lt A HL B N S O 2T c j Oo OO RI RI OD lt AA HL C Notes 1 2 When an area except the internal high speed RAM area is accessed 3 Except r A When the internal high speed RAM area is accessed or instruction with no data access Remark One instruction clock cycle is one cycle of the CPU clock fceu selected by the processor clock control register PCC 286 Preliminary User s Manual U14581EJ3VOUMOO CHAPTER 23 INSTRUCTION SET Instruction Group 8 bit operation Mnemonic Operands A byte Operation lt A
35. overscore over pin or signal name Note Footnote for item marked with Note in the text Caution Information requiring particular attention Remark Supplementary information Numerical representation Binary Or Decimal XXX Hexadecimal xxxxH Preliminary User s Manual U14581EJ3VOUM00 9 Related Documents The related documents indicated in this publication may include preliminary versions However preliminary versions are not marked as such Related documents for 0780852 Subseries Document No Document Name Japanese English uPD780851 A 780852 A Preliminary Product Information U14577J U14577E uPD78F0852 Preliminary Product Information U14576J U14576E uPD780852 Subseries User s Manual U14581J This manual 78K 0 Series User s Manual Instructions U12326J U12326E 78K 0 Series Instruction Table U10903J 78K 0 Series Instruction Set U10904J Related documents for development tool User s Manual Document No Document Name Japanese English RA78KO0 Assembler Package Operation U11802J U11802E Language U11801J U11801E Structured Assembly Language U11789J U11789E CC78K0 C Compiler Operation U11517J U11517E Language U11518J U11518E CC78K0 C Compiler Application Note Programming Know how U13034J U13034E IE 78K0 NS U13731J U13731E IE 780852 NS EM4 To be prepared To be prepared 5 78 0 System Simulator Windows Ba
36. read during operation choose a select clock which has longer high low level wave because the select clock is stopped temporarily Preliminary User s Manual U14581EJ3VOUMOO 135 MEMO 136 Preliminary User s Manual U14581EJ3VOUMOO CHAPTER 9 WATCH TIMER 9 1 Watch Timer Functions The watch timer has the following functions Watch timer nterval timer The watch timer and the interval timer can be used simultaneously Figure 9 1 shows watch timer block diagram Figure 9 1 Watch Timer Block Diagram 5 bit counter Clear Selector fx 27 9 bit prescaler Selector fx 2 INTWTI Selector L l Watch timer mode control register WTM Internal bus Preliminary User s Manual U14581EJ3V0UM00 137 CHAPTER 9 WATCH TIMER 1 Watch timer When the main system clock is used interrupt requests INTWT are generated at 0 25 second at fx 8 38 MHz operation intervals 2 Interval timer Interrupt requests INTWT are generated at the preset time interval Table 9 1 Interval Timer Interval Time When Operated at fx 8 38 MHz Interval Time 489 us 978 us 1 96 ms 3 91 ms 7 82 ms 15 65 ms Remark fx Main system clock oscillation frequency 9 2 Watch Timer Configuration The watch timer consists of the following hardware Table 9 2 Watch Timer Configuration Item Configuration Counter
37. 1 04 MHz fx 24 524 kHz fx 25 262 kHz fx 2 131 kHz fx 27 65 5 kHz Cautions 1 When rewriting CKS to other data stop the timer operation beforehand 2 Bits 3 and 5 to 7 must be set to 0 Remarks 1 fx Main system clock oscillation frequency 2 Figures in parentheses apply to operation with fx 2 8 38 MHz 150 Preliminary User s Manual U14581EJ3VOUMOO CHAPTER 11 CLOCK OUTPUT CONTROLLER 2 Port mode register 6 PM6 This register sets port 6 input output in 1 bit units When using the P60 PCL TPO pin for clock output set PM60 and the output latch of P60 to 0 PM6 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM6 to FFH Figure 11 3 Port Mode Register 6 PM6 Format Address FF26H After Reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM6 P6n Pin Input Output Mode Selection n 0 1 Output mode output buffer on Input mode output buffer off Preliminary User s Manual U14581EJ3V0UM00 151 CHAPTER 11 CLOCK OUTPUT CONTROLLER 11 4 Clock Output Controller Operation To output the clock pulse follow the procedure described below 1 lt 2 gt lt 3 gt lt 4 gt 5 152 Select the clock pulse output frequency with bits 0 to 2 CCSO to CCS2 of the clock output selection register CKS clock pulse output in disabled status Set bit 0 TPOE of the 16 bit timer mode control register TMCO to 0 prescaler signal output in d
38. 1221 3 LCD clock selector ATE Timing controller Display data memory LCD display control register LCDC LCDC7 10006 10005 L144 Segment selector LCD driver voltage controller P97 output P81 output buffer buffer 0 S4 S5P97 ue S19 PB81 COMO COM1 COM2 COM3 Vico Note Segment driver 208 Preliminary Users Manual U14581EJ3VOUMOO CHAPTER 16 LCD CONTROLLER DRIVER Remarks 1 2 fLcp fx 2 4 Figure 16 2 LCD Clock Selector Block Diagram Prescaler fico 2 fico 2 2 LCDCL Selector fico LCDM6 LCDMS LCDM4 LCD display mode register Internal bus LCDCL LCD clock LCD clock frequency Preliminary User s Manual U14581EJ3V0UMOO 209 CHAPTER 16 LCD CONTROLLER DRIVER 16 3 LCD Controller Driver Control Registers The following two types of registers are used to control the LCD controller driver LCD display mode register LCDM LCD display control register LCDC 1 LCD display mode register LCDM This register sets display operation enabling disabling the LCD clock and frame frequency LCDM is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears LCDM to 00H Figure 16 3 LCD Display Mode Register LCDM Format Address FFBOH After Reset OOH R W Symbol 7 6 5 4 3
39. 2 and 3 consist of the following hardware Table 8 1 8 Bit Timer Event Counters 2 TM2 and 3 Configurations Item Configuration Timer register 8 bit counter x 2 TM2 TM3 Register 8 bit compare register x 2 CR2 CR3 Timer output 2 TIO2 TIO3 Control register Timer clock select registers 2 3 TCL2 TCL3 8 bit timer mode control registers 2 3 2 TMC3 Port mode register 4 PM4 1 8 bit counters 2 3 TM2 TM3 TMn is an 8 bit read only register which counts the count pulses The counter is incremented in synchronization with the rising edge of the count clock When count value is read during operation count clock input is temporary stopped and then the count value is read In the following situations the count value is set to 00H 1 RESET input 2 Clear TCE2 and 3 Match between TM2 and and CR2 and in clear and start mode with match between TM2 and and CR2 2 8 bit compare registers 2 3 CR2 CR3 The value set in the CR2 is constantly compared with the 8 bit counter 2 TM2 count value and the value set in the CR3 is constantly compared with the 8 bit counter 3 TM3 count value and interrupt requests INTTM2 and are generated if they match except PWM mode CR2 and CR3 are set with an 8 bit memory manipulation instruction They are not set with a 16 bit memory manipulation instruction It is possible to rewrite the
40. 40 O gt lt o n O gt lt a SGAMO Amplitude 0 128 2 128 3 128 4 128 5 128 6 128 7 128 8 128 9 128 10 128 11 128 12 128 13 128 14 128 15 128 16 128 17 128 18 128 19 128 20 128 21 128 22 128 23 128 24 128 25 128 26 128 27 128 28 128 29 128 30 128 31 128 HE gt E O ojoojoojio j o o o o o o o ojo oj o oj o o o o o o o jo oj oi o 128 128 Cautions 1 When rewriting SGAM to other data stop the timer operation beforehand However note that a high level may be output for one period due to rewrite timing 2 Bit 7 must be set to 0 228 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 17 SOUND GENERATOR 17 4 Sound Generator Operations 17 4 1 To output basic cycle signal SGO The basic cycle signal is output from the SGO pin if the bit 7 TCE of the sound generator control register SGCR is set to 1 The basic cycle signal of the frequency set by SGCLO to SGCL2 and SGBRO to SGBR3 is output The amplitude of the basic cycle signal can be changed by changing the set value of the sound generator amplitude register SGAM Figure 17 6 Sound Generat
41. 9 FFH Pull up resistor option register PUO 00H Processor clock control register PCC 04H Memory size switching register IMS CFH Internal expansion RAM size switching register IXS 0CH Oscillation stabilization time select register OSTS 04H Oscillator mode register OSCM Note 3 00H 16 bit timer 0 TMO Timer register TMO 00H Capture registers CROO to CRO2 00H Prescaler mode register PRMO 00H Mode control register TMCO 00H Capture pulse control register 0 CRCO 00H Notes 1 During reset input or oscillation stabilization time wait only the PC contents among the hardware status become undefined All other hardware statuses remain unchanged after reset 2 The post reset status is held in the standby mode 3 For uPD780851 A 780852 A only Preliminary User s Manual U14581EJ3V0UM00 273 CHAPTER 21 RESET FUNCTION Hardware Status after Reset 8 bit timer TM1 to TM3 Table 21 1 Hardware Status after Reset 2 2 Timer counters TM1 to Compare registers CR1 to CR3 Clock select registers TCL1 to TCL3 Mode control registers TMC1 to TMC3 Watch timer Mode control register WTM Watchdog timer Clock select register WDCS Mode register WDTM Clock output controller Clock output selection register CKS A D converter Mode register ADM1 Conversion result register ADCR1 Analog input
42. BRK 50 Preliminary Users Manual U14581EJ3VOUMOO CHAPTER 3 CPU ARCHITECTURE 2 CALLT instruction table area The 64 byte area 0040H to 007FH can store the subroutine entry address of a 1 byte call instruction CALLT 3 CALLF instruction entry area The area 0800H to OFFFH can perform a direct subroutine call with a 2 byte call instruction CALLF 3 1 2 Internal data memory space The uPD780852 Subseries have the following RAM 1 Internal high speed RAM The configuration of the internal high speed RAM is 1 024 x 8 bits at addresses FBOOH to FEFFH The 32 byte area FEEOH to FEFFH is allocated with four general purpose register banks composed of eight 8 bit registers The internal high speed RAM can be used as stack memory 2 LCD display RAM An LCD display RAM is allocated to an area of 20 x 4 bits at addresses FA59H to FA6CH The LCD display RAM can also be used as a normal RAM 3 Internal expansion RAM An internal expansion RAM is allocated to an area of 512 x 8 bits at addresses F600H to F7FFH 3 1 3 Special function register SFR area on chip peripheral hardware special function register SFR is allocated in the area FFOOH to FFFFH see Table 3 3 Special Function Register List in 3 2 3 Special function registers SFRs Caution Do not access addresses where the SFR is not assigned Preliminary User s Manual U14581EJ3VOUM00 51 CHAPTER 3 CPU
43. Figure 11 1 Clock Output Controller Block Diagram fx fx 2 fx 2 fx 28 fx 2 fx 25 26 fx 27 1 1 P60 Clock output selection register CKS Port mode register 6 PM6 T PO Note Selector Clock PCL TPO P60 controller Internal bus Note TPO Prescaler output signal of 16 bit timer 0 TMO 11 2 Clock Output Controller Configuration The clock output controller consists of the following hardware Table 11 1 Clock Output Controller Configuration Control register Clock output selection register CKS Port mode register 6 PM6 Preliminary User s Manual U14581EJ3V0UMOO 149 CHAPTER 11 CLOCK OUTPUT CONTROLLER 11 3 Clock Output Control Controller Registers The following two types of registers are used to control the clock output controller Clock output selection register CKS Port mode register 6 PM6 1 Clock output selection register CKS This register sets output clock CKS is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears CKS to 00H Caution To enable PCL output set CCSO to CCS2 and then set CLOE to 1 by using a 1 bit memory manipulation instruction Figure 11 2 Clock Output Selection Register CKS Format Address FF40H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 Operation disabled Operation enabled CCS1 CCSO PCL Output Clock Selection fx 8 38 MHz fx 2 4 19 MHz fx 22 2 09 MHz fx 23
44. Hi Z Serial function Hi Z Note Master slave can be selected by setting bits 0 and 1 CSK1 and SCL20 of the serial operation mode register 2 CSIM2 196 Preliminary User s Manual U14581EJ3VOUMOO CHAPTER 14 SERIAL INTERFACE SIO2 5 Transfer format A simultaneous transmit receive operation can be performed when the receive data is transferred from the serial I O shift register 2 SIO2 to the receive data buffer register SIRB2 a Clock phase and polarity The phase and polarity of the serial clock can be selected from four combinations by setting bits 3 and 4 CLPO and CLPH of the serial operation mode register 2 CSIM2 Select a clock polarity by using CLPO An active high or active low clock can be selected The clock phase is set by CLPH The output timing of SO2 can be selected For the setting of CLPO and CLPH serial transfer clock data output and the capture timing of input data see Figure 14 3 b Transfer format when CLPH 0 Figure 14 6 shows the operation timing when CLPH 0 Two waves of SCK2 when CLPO 0 and when CLPO 1 are shown in the figure Data is transmitted or received in 8 bit units Each bit of data is transmitted or received in synchronization with the serial clock 5102 is shifted at the falling edge of SCK2 if CLPH 0 and CLPO 0 If CLPH 0 and CLPO 1 SIO2 is shifted at the rising edge of SCK2 The transmit data is held by the SO2 latch and output from the SO2 The
45. Interrupt request flag Capture read signal a uu _ CROn interrupt value X X N ra Capture operation Remark 0102 3 Valid edge setting Set the valid edge of the TlOn P4n pin after setting bit 2 02 of the 16 bit timer mode control register TMCO to 0 and then stopping timer operation Valid edge setting is carried out with bits 2 to 7 ESnO and ESn1 of the prescaler mode register PRMO Remark n 0to2 Preliminary User s Manual U14581EJ3VOUMOO 111 CHAPTER 6 16 BIT TIMER 0 TMO 4 112 Occurrence of INTTMOn INTTMOn occurs even if no capture pulse exists immediately after the timer operation has been started 02 of TMCO has been set to 1 with a high level applied to input pins TIOO to TIO2 of 16 bit timer 0 and with the rising edge with ESn1 and ESn0 of PRMO set to 0 1 or both the rising and falling edges with ESn1 and ESnO of PRMO set to 1 1 selected However INTTMOn does not occur if a low level is applied to TIOO to TIO2 Remark nz0to2 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 7 8 BIT TIMER 1 TM1 7 1 8 Bit Timer 1 TM1 Functions The 8 bit timer 1 TM1 operates as an 8 bit interval timer Figure 7 1 shows timer 1 TM1 block diagram Figure 7 1 8 Bit Timer 1 TM1 Block Diagram Internal bus 8 bit compare register 1 CR1 Coincidence fx 23 INTTM1 24 1x 25 2 fx 27 8 bit counter TM1 fx 2 fx 2 Clear
46. Output buffer off Note Note When 0 is set to ENn of port mode control register PMC Preliminary User s Manual U14581EJ3V0UMOO 87 CHAPTER 4 PORT FUNCTIONS 2 Pull up resistor option register PUO This register is used to set whether to use an on chip pull up resistor at port O or not By setting the PUO the on chip pull up resistor of the corresponding port pin can be used PUO is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears this register to 00H Caution When the on chip pull up resistor is used the pull up resistor is not cut off even when the port is set to the output mode To use the port in the output mode clear the corresponding pull up resistor option register to 0 Figure 4 13 Pull Up Resistor Option Register PUO Format Address FF30H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 POn Pin On Chip Pull Up Resistor Selection n 0 to 7 On chip pull up resistor not used On chip pull up resistor used 88 Preliminary User s Manual U14581EJ3VOUMOO CHAPTER 4 PORT FUNCTIONS 4 4 Port Function Operations Port operations differ depending on whether the input or output mode is set as shown below 4 4 1 Writing to input output port 1 Output mode A value is written to the output latch by a transfer instruction and the output latch contents are output from the pin Once data is written to the output latch it is retained until data is written to the output latch aga
47. PC 9800 Series Host Machine Supply Medium Windows Japanese version N 3 5 inch 2HD FD IBM PC AT and compatibles Windows Japanese version 89 3 5 inch 2HC FD Note Windows English version Note WindowsNT is not supported uSxxxxlD78K0 PC 9800 Series Host Machine Supply Medium Windows Japanese version V 3 5 inch 2HD FD IBM PC AT and compatibles Windows Japanese version N 3 5 inch 2HC FD Note Windows English version HP9000 Series 700 HP UX Rel 9 05 DAT DDS SPARCstation SunOS Rel 4 1 4 Solaris Rel 2 5 1 3 5 inch 2HC FD 1 4 inch CGMT Note WindowsNT is not supported NEWS RISC NEWS OS Rel 6 1 Preliminary User s Manual U14581EJ3V0UMOO 3 5 inch 2HC FD 303 MEMO 304 Preliminary User s Manual U14581EJ3VOUMOO APPENDIX EMBEDDED SOFTWARE For efficient development and maintenance of the uPD780852 Subseries the following embedded software products are available Real Time OS 1 2 RX78K 0 RX78K 0 is a real time OS conforming with the specifications Real time OS Tool configurator for generating nucleus of RX78K 0 and plural information tables is supplied Used in combination with an optional assembler package RA78K 0 and device file DF780852 Caution when using in PC environment Real time OS is a DOS based application Use DOS prompt in Windows Part number 78
48. PO3 SCK2 PO2 INTP2 P0O1 INTP1 POO INTPO AVREF Cautions 1 Connect IC Internally Connected pin to Vsso or Vssi directly AN O Q P86 S14 P87 S13 P90 S12 P91 S11 P92 S10 P93 S9 P94 S8 P95 S7 P96 S6 P97 S5 S4 S3 S2 1 50 COM3 COM2 COM1 COMO Vreo 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 Po O 4 3 2 P14 AN P13 AN P12 AN 22 23 24 25 26 27 28 29 30 31 o o ge g OQ D SO Q z Z gt X OQ e 2 x x 9 SO S O xlooq ctrrEtctr lt lt p 9 9 G ANS OT tT n n 2 Connect pin to Vsso 3 Connect AVnrr pin to P44 TIO3 P60 TPO PCL P61 SGO 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 32 33 34 35 36 37 38 39 40 SMVss SMVpp P20 SM11 P21 SM12 P22 SM13 P23 SM14 P24 SM21 P25 SM22 P26 SM23 P27 SM24 P30 SM31 P31 SM32 P32 SM33 P33 SM34 P34 SM41 P35 SM42 P36 SM43 P37 SM44 SMVpp SMVss Remarks 1 When these devices are used in applications that require reduction of the noise generated from inside the microcontroller the implementation of noise reduction measures such as connecting the Vsso and Vssi to different ground lines is recommended 2 Pin connection in parentheses is intended for the uPD78F0852 Preliminary User s Manual U14581EJ3VOUM00 29 CHAPTER 1 OUTLINE 30 ANIO to ANIA AVREF AVs
49. Watchdog Timer Runaway Detection Time Runaway Detection Time 212 x 1 fx 489 ps 213 x 1 fx 978 us 214 x 1 fx 1 96 ms 215 x 1 fx 3 91 ms 216 x 1 fx 7 82 ms 217 x 1 fx 15 6 ms 218 x 1 fx 31 3 ms 220 x 1 fx 125 ms Remarks 1 fx Main system clock oscillation frequency 2 Figures in parentheses apply to operation with fx 8 38 MHz 2 Interval timer mode Interrupt requests are generated at preset time intervals Table 10 2 Interval Time Interval Time 21 x 1 fx 489 us 213 x 1 fx 978 us 214 x 1 fx 1 96 ms 215 x 1 fx 3 91 ms 216 x 1 fx 7 82 ms 217 x 1 fx 15 6 ms 218 x 1 fx 31 3 ms 220 x 1 fx 125 ms Remarks 1 fx Main system clock oscillation frequency 2 Figures in parentheses apply to operation with fx 8 38 MHz 144 Preliminary User s Manual U14581EJ3VOUMO0 CHAPTER 10 WATCHDOG TIMER 10 2 Watchdog Timer Configuration The watchdog timer consists of the following hardware Table 10 3 Watchdog Timer Configuration Control register Watchdog timer clock select register WDCS Watchdog timer mode register WDTM 10 3 Watchdog Timer Control Registers The following two types of registers are used to control the watchdog timer Watchdog timer clock select register WDCS Watchdog timer mode register WDTM 1 Watchdog timer clock select register WDCS This register sets overflow time of the watc
50. compared If the condition for comparison is satisfied INTAD is generated Preliminary User s Manual U14581EJ3VOUMOO 153 CHAPTER 12 A D CONVERTER Figure 12 1 A D Converter Block Diagram Series resistor string Successive approximation register SAR 1 ANIO P10 Sample amp hold circuit ANH P11 5 T oltage comparator ANI2 P12 8 E 1 1 1 o 1 1 10 ANI3 P13 i L0 1 1 1 5 ANI4 P14 T 1 1 1 Lu Controller NTAD 3 A D conversion result register ADCR1 ADS12 ADS11 ADS10 ADCS1 FR12 FR11 FR10 Analog input channel A D converter mode specification register ADS1 register ADM1 Internal bus Figure 12 2 Power Fail Detection Function Block Diagram PFCM PFEN ANIO P10 G B 11 9 5 2 INTAD 2 12 A D converter o ANI3 P13 2 ANI4 P14 Power fail compare threshold value register PFT PFEN PFCM H FI Power fail compare mode register PFM Internal bus 154 Preliminary User s Manual U14581EJ3V0UM00 CHAPTER 12 A D CONVERTER 12 2 A D Converter Configuration 1 2 3 4 5 6 A D converter consists of the following hardware Table 12 1 A D Converter Configuration Item Configuration Analog input 5 channels ANIO to ANI4 Register Successive approximation register SAR A D convers
51. customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features NEC semiconductor products are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to semiconductor products developed based on a customer designated quality assurance program for a specific application recommended applications of a semiconductor product depend on its quality grade as indicated below Customers must check the quality grade of each semiconductor product before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems life support systems and medical equipment for life support etc The quality grade of NEC semiconductor products is Standard unless otherwise expressly specified in NEC s data sheets or data books etc customers wish to use NEC semiconductor products in applications not
52. 2 1 0 Display off all segment outputs are non select signal outputs Display on LCD Clock Selection fx 8 38 MHz fx 217 64 Hz fx 216 128 Hz fx 215 256 Hz 1 fx 214 512 Hz Other than above Setting prohibited Remark fx Main system clock oscillation frequency 210 Preliminary User s Manual U14581EJ3V0UM00 CHAPTER 16 LCD CONTROLLER DRIVER 2 LCD display control register LCDC This register sets cutoff of the current flowing to split resistors for LCD drive voltage generation and switchover between segment output and input output port functions LCDC is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears LCDC to 00H Figure 16 4 LCD Display Control Register LCDC Format Address FFB2H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 P81 819 to 97 55 Pin Functions Port Pins Segment Pins P81 None P81 S5 S6 P81 S5 to S8 P81 S5 to S10 P81 S5 to 512 P81 S5 to 514 P81 S5 to S16 P81 S5 to S18 None S5 to 519 0 0 0 0 0 0 0 0 Other than above Setting prohibited LIPS LCD Driving Power Supply Selection 0 Does not supply power to LCD 1 Supplies power to LCD from pin Cautions 1 Pins which perform segment output cannot be used as output port pins even if 0 is set in the port mode register 2 If a pin which performs segment output is read as a port its value will be 0 3 If a pin s
53. 21 fsck 22 fsck 23 fsck 24 O 25 26 A 27 a 28 EN 29 EN fscx 30 AB Setting prohibited Caution Writing to BRGC during a communication operation may cause abnormal output from the baud rate generator and disable further communication operations Therefore do not write to BRGC during a communication operation Remarks 1 fx Main system clock oscillation frequency 2 fsck Source clock for 5 bit counter 3 n Value set via TPSO to TPS2 1 lt n lt 8 4 k Value set via MDLO to MDL3 O x k x 14 174 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 13 SERIAL INTERFACE UART 13 4 Serial Interface Operations This section explains the two modes of the serial interface UART 13 4 1 Operation stop mode This mode is used when serial transfers are not performed to reduce power consumption In the operation stop mode P53 RxD and P54 TxD pins can be used as ordinary ports 1 Register settings Operation stop mode is set with the asynchronous serial interface mode register ASIM ASIM is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears ASIM to 00H Address FF85H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 ASIM TXE RXE PS1 PSO CL SL RxD P53 Pin Function TxD P54 Pin Function Operation st
54. 512 256 512 256 512 256 512 256 512 Input voltage AVner 162 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 12 A D CONVERTER 12 4 3 A D converter operation mode The operation mode of the A D converter is the select mode One analog input channel is selected from among ANIO to ANI4 with the analog input channel specification register ADS1 and A D conversion is performed 1 2 The following two types of functions can be selected by setting the PFEN flag of the PFM register 1 Normal 8 bit A D converter PFEN 0 2 Power fail detection function PFEN 1 A D conversion when PFEN 0 When bit 7 ADCS1 of the A D converter mode register ADM1 is set to 1 and bit 7 of the power fail compare mode register PFM is set to 0 A D conversion of the voltage applied to the analog input pin specified with the analog input channel specification register ADS1 starts Upon the end of the A D conversion the conversion result is stored in the A D conversion result register ADCR1 and the interrupt request signal INTAD is generated After one A D conversion operation is started and ended the next conversion operation is immediately started A D conversion operations are repeated until new data is written to ADS1 If ADS1 is rewritten during A D conversion operation the A D conversion operation under execution is stopped and A D conversion of a newly selected analog input channel is started If data with ADCS1
55. 7 6 5 4 3 2 1 0 E O No parity error Parity error Transmit data parity does not match EE Framing Error Flag No framing error Framing error Note 1 Stop bit not detected E Overrun Error Flag No overrun error Overrun error Note 2 Next receive operation was completed before data was read from receive buffer register Notes 1 Even ifa stop bit length of two bits has been setto bit 2 SL in the asynchronous serial interface mode register ASIM stop bit detection during a receive operation only applies to a stop bit length of 1 bit 2 Be sure to read the contents of the receive buffer register RXB when an overrun error has occurred Until the contents of RXB are read further overrun errors will occur when receiving data Preliminary User s Manual U14581EJ3V0UM00 177 CHAPTER 13 SERIAL INTERFACE UART c Baud rate generator control register BRGC BRGC is set with an 8 bit memory manipulation instruction RESET input clears BRGC to 00H Address FF87H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 fx 8 38 MHz TPSO Source Clock Selection for 5 bit Counter n 16 17 18 19 20 fscK 21 22 23 24 NI aJJ AJOJN 25 26 E 27 28 EN 29 A fscx 30
56. IFOL IFAL IMS IXS L LCDC LCDM LCDTM M MCMP10 MCMP11 20 MCMP21 310 A D conversion result register 155 A D converter mode register 157 Analog input channel specification register 158 Asynchronous serial interface mode register 170 Asynchronous serial interface status register 173 Baud rate generator control register 173 Clock output selection register 150 Capture register 00 104 Capture register 01 104 Capture register 02 104 8 bit compare register 1 114 8 bit compare register 2 123 8 bit compare register 3 123 Capture pulse control register 106 Serial operation mode register 2 189 Serial operation mode register 3 203 D A converter mode register 168 External interrupt falling edge enable register 249 External interrupt rising edge enable register 249 Interrupt request flag register OH 246 Interrupt request flag register OL 246 Interrupt request flag register 1L 246 Memory size switching register 276 Internal expansion RAM size switching register 277 LCD display control register 211 LCD display mode register 210 LCD timer control register 221 Compare register sin side 233 Compare register cos side 233 Compare register sin side 233 Compare register cos side 233 Preliminary User s Manual U14581EJ3V0UMOO APPENDIX C REGISTER INDEX MCMP3
57. Interrupt request hold ete rtr ttti tide nile repe eb 261 CHAPTER 20 STANDBY FUNCTION 263 20 1 Standby Function and Configuration u u uu u u 263 20 SLAM YUM CUOM mus us ettet 263 20 1 2 Standby function control register ssssssssssseeeeeee nennen nennen 264 20 2 Standby Function Operations u u uuu uu uu u 265 20 2 1 HALT MOUS ves e cr PEE Ete au hasan Suk E PE EUH 265 20 2 2 SIFOP IW0de citer eue ve be reve dnt dee eee epe ususiy 268 CHAPTER 21 RESET FUNGTION roro terea tune Cn 271 21 1 R set PUNCO S a eea a aaa a eaaa aaar aeae aaae aaaea 271 CHAPTER 22 78 0852 2 5 275 22 1 Memory Size Switching Register IMS l l l u u J 276 22 2 Internal Expansion RAM Size Switching Register IXS 277 22 3 Flash Memory Programming U U u u u u u u u 278 22 3 1 Selection of transmission method 278 22 3 2 Flash memory pr
58. MSB of SAR remains set If the analog input is smaller than 1 2 AVrer the MSB is reset Next bit 6 of SAR is automatically set and the operation proceeds to the next comparison The series resistor string voltage tap is selected according to the preset value of bit 7 as described below Bit 7 1 3 4 AVREF Bit 7 0 1 4 AVneF The voltage tap and analog input voltage are compared and bit 6 of SAR is manipulated as follows Analog input voltage gt Voltage tap Bit 6 1 Analog input voltage lt Voltage tap Bit 6 0 Comparison is continued in this way up to bit 0 of SAR Upon completion of the comparison of 8 bits an effective digital result value remains in SAR and the result value is transferred to and latched in the A D conversion result register ADCR1 At the same time the A D conversion end interrupt request INTAD can also be generated The occurrence of INTAD can be controlled by setting bit 6 PFCM of the power fail compare mode register PFM Caution The first A D conversion value is undefined immediately after an A D conversion operation has been started Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 12 A D CONVERTER Figure 12 7 Basic Operation of 8 Bit A D Converter mi Conversion time Sampling time a A D converter operation Sampling A D conversion Conversion SAR Undefined result Conversion result INTAD A D conversion operations ar
59. NS ID78K0 and 5 78 0 are used R W Indicates whether the corresponding special function register can be read or written R W Read write enable R Read only W Write only Manipulatable bit units Indicates the manipulatable bit unit 1 8 or 16 indicates a bit unit for which manipulation is not possible After reset Indicates each register status upon RESET input Preliminary Users Manual U14581EJ3VOUMOO 59 CHAPTER 3 CPU ARCHITECTURE Table 3 3 Special Function Register List 1 3 Manipulatable Bit Unit Address Special Function Register SFR Name After Reset 1 Bit 8 Bits 16 Bits O O Port 0 Port 1 R Port 2 R W Note Port 3 Port 4 Port 5 Port 6 Port 8 O O O O Port 9 8 bit compare register 1 8 bit compare register 2 8 bit compare register 3 8 bit counter 1 8 bit counter 2 O O O O JOJ O O 8 bit counter 3 Capture register 00 Capture register 01 Capture register 02 16 bit timer register 0 Serial I O shift register Transmit shift register Receive buffer register A D conversion result register Serial shift register 2 Note When 2 and set to read operation is enabled Moreover when 2 and set to FFH these ports go into a high impedanc
60. P43 TIO2 P44 TIOS Internal bus PM40 to PM44 Alternate functions PM Port mode register RD Port 4 read signal WR Port 4 write signal Preliminary User s Manual U14581EJ3V0UMOO 81 CHAPTER 4 PORT FUNCTIONS 4 2 6 Port 5 Port 5 is a 5 bit input output port with output latch P50 to P54 pins can specify the input mode output mode in 1 bit units with the port mode register 5 PM5 Alternate functions include serial interface data input output and clock input output RESET input sets port 5 to input mode Figure 4 7 shows a block diagram of port 5 Caution When port 0 is used as the serial interface pins an I O and output latches must be set according to the functions to be used For an explanation of how to set these latches refer to the description of the format of the serial operation mode register Figure 4 7 P50 to P54 Block Diagram P50 SCK3 Output latch P51 SO3 P50 to P54 gt P52 SI3 P53 RxD P54 TxD Internal bus 50 to PM54 Alternate functions PM Port mode register RD Port 5 read signal WR Port 5 write signal 82 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 4 PORT FUNCTIONS 4 2 7 Port 6 Port 6 is a 2 bit input output port with output latch P60 and P61 pins can specify the input mode output mode in 1 bit units with the port mode register 6 PM6 Alternate functions include clock output and sound generator o
61. Sound generator amplitude register Serial operation mode register 2 Serial receive data buffer register Undefined Serial receive data buffer status register 00H Oscillator mode register Note 2 LCD display mode register LCD display control register Interrupt request flag register OL Interrupt request flag register OH Interrupt request flag register 1L Interrupt mask flag register OL Interrupt mask flag register OH Interrupt mask flag register 1L Priority specify flag register OL Priority specify flag register OH O O O O O O O OO Priority specify flag register 1L Memory size switching register CFH Note 3 Internal expansion RAM size switching register OCH Note 4 Watchdog timer mode register 00H Oscillation stabilization time select register 04H O OJO O O O OJO IO OJO IO OI IOIOI OO OJO O IOIOIOIO OC O Processor clock control register Notes 1 DAMO is a register that must be set when debugging the uPD780852 with an in circuit emulator IE 78K0 62 NS Set this register when emulating a power fail detection function LP D780851 A 780852 A only The initial value of this register is CFH Set the following value to this register of each model LPD780851 A C8H 780852 LPD78F0852 to set the same memory map a
62. TIO2 P42 16 bit TIMERO ded TPO PCL P60 o 2 8 bit TIMER1 8 bit TIMER TIO2 P43 EVENT COUNTER2 8 bit TIMER 44 COUNTER3 WATCHDOG TIMER WATCH TIMER SCK2 P03 SERIAL SO2 P04 INTERFACE K gt SI2 P05 5102 SCK3 P50 SERIAL 503 51 SI3 P52 RxD P53 TxD P54 ANIO P10 to ANI4 P14 AVss AVREF POWER FAIL DETECTOR INTPO POO to INTP2 P02 INTERRUPT CONTROL STANDBY CONTROL KY KY roca INTERNAL EXPANSION RA P00 to P07 Qj rem P10 to P14 P20 to P27 ports P30 to P37 P40 to P44 Qj roms P50 to P54 Qj rome K gt P60 P61 D rome P81 to P87 P90 to P97 gt 501054 CLOCK OUTPUT PCL TPO P60 CONTROL SOUND GENERATOR OUTPUT SGO P61 SYSTEM CONTROL VOLTAGE REGULATOR Vsso IC i VPP L Remarks 1 The internal ROM capacities depend on the product 2 Memory type in parentheses is for the uPD78F0852 Preliminary User s Manual U14581EJ3VOUM00 SMVop SMVss X1 2 RESET VRour Vss 33 CHAPTER 1 OUTLINE 1 8 Outline of Function Part Number Internal memory 32 Kbytes Mask ROM 40 Kbytes Mask ROM 40 Kbytes Flash memory High speed RAM 1 024 bytes Expanded RAM 512 bytes LCD display RAM 20 x 4 bits General register 8 bits x 32 registers 8 bits x 8 registers x 4 banks Minimum instruction execution time On chip m
63. Users Manual U14581EJ3VOUMOO FEFFH FEF8H FEFOH FEE8H FEEOH CHAPTER 3 CPU ARCHITECTURE 3 2 3 Special function registers SFRs Unlike the general registers these registers have special functions They are allocated in the to FFFFH area The special function registers can be manipulated like the general registers with the operation transfer and bit manipulation instructions The bit units 1 8 or 16 bits for the manipulation vary for each register Each manipulation bit unit can be specified as follows 1 bit manipulation Describe the symbol reserved with assembler for the 1 bit manipulation instruction operand sfr bit This manipulation can also be specified with an address 8 bit manipulation Describe the symbol reserved with assembler for the 8 bit manipulation instruction operand sfr This manipulation can also be specified with an address 16 bit manipulation Describe the symbol reserved with assembler for the 16 bit manipulation instruction operand sfrp When addressing an address describe an even address Table 3 3 gives a list of special function registers The meaning of items in the table is as follows Symbol Symbol indicating the address of a special function register Itis a reserved word in the RA78K 0 and is defined via the header file sfrbit h in the 78 0 It can be described as an instruction operand when the RA78K 0 ID78K0
64. WTIIF WTIF CSIMK2 WTIMK WTMK CSIPR2 WTIPR WTPR Remark The WDTIF WDTMK and WDTPR flags are interrupt control flags when the watchdog timer is used as an interval timer Preliminary User s Manual U14581EJ3VOUMOO 245 CHAPTER 19 INTERRUPT FUNCTIONS 1 Interrupt request flag registers IFOL IFOH IF1L The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of RESET input IFOL IFOH and IF1L are set with a 1 bit or 8 bit memory manipulation instruction When IFOL and IFOH are combined to form 16 bit register IFO they set with a 16 bit memory manipulation instruction RESET input clears these registers to 00H Figure 19 2 Interrupt Request Flag Register IFOL IFOH IF1L Format Address FFEOH After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 Address FFE1H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 Address FFE2H After Reset 00H R W Symbol y 6 5 4 3 2 1 0 0 No interrupt request signal is generated 1 Interrupt request signal is generated interrupt request status Cauti
65. acknowledge enable state is selected IE 1 except non maskable interrupts Also when an interrupt request is received interrupt requests acknowledge becomes disabled IE 0 Therefore to enable multiple interrupts itis necessary to set the IE flag to 1 with the El instruction during interrupt servicing to enable interrupt acknowledge Moreover even if interrupts are enabled multiple interrupts may not be enabled this being subject to interrupt priority control Two types of priority control are available default priority control and programmable priority control Programmable priority control is used for multiple interrupts In the interrupt enable state if an interrupt request with a priority equal to or higher than that of the interrupt currently being serviced is generated it is acknowledged for multiple interrupt servicing If an interrupt with a priority lower than that of the interrupt currently being serviced is generated during interrupt servicing it is not acknowledged for multiple interrupt servicing Interrupt requests that are not enabled because of the interrupt disable state or they have a lower priority are held pending When servicing of the current interrupt ends the pending interrupt request is acknowledged following execution of one main processing instruction execution Multiple interrupt servicing is not possible during non maskable interrupt servicing Table 19 4 shows interrupt requests enabled for multiple inte
66. channel specification register ADS1 Power fail compare mode register PFM Power fail compare threshold value register PFT Serial interface UART Asynchronous serial interface mode register ASIM Asynchronous serial interface status register ASIS Baud rate generator control register BRGC Transmit shift register TXS Receive buffer register RXB Serial interface SIO2 Operation mode register 2 CSIM2 00H Shift register 2 SIO2 00H Receive data buffer register SIRB2 Undefined Receive data buffer status register SRBS2 00H Serial interface SIO3 Operation mode register 3 CSIM3 00H Shift register 3 SIO3 00H LCD controller driver Display mode register 00H Display control register LCDC 00H Sound generator Control register SGCR 00H Amplitude register SGAM 00H Buzzer control register SGBR 00H Meter controller driver Compare registers MCMP10 MCMP11 MCMP20 MCMP21 MCMP30 MCMP31 MCMP40 MCMP41 00H Timer mode control register MCNTC 00H Port mode control register PMC 00H Compare control registers MCMPC1 to MCMPC3 00H Interrupt 274 Request flag registers IFOL IFOH IF1L 00H Mask flag registers MKOL MKOH MK1L FFH Priority specify flag registers PROL PROH PR1L FFH External interrupt rising edge enable
67. designed to help users understand the following functions using the organization below The uPD780852 Subseries manual is separated into two parts this manual and the instruction edition common to the 78K 0 Series uPD780852 Subseries 78K 0 Series User s Manual User s Manual This Manual Instructions Pin functions CPU functions Internal block functions Instruction set Interrupt Explanation of each instruction Other on chip peripheral functions This manual assumes general knowledge of electric engineering logic circuits and microcontrollers To understand the functions of the wPD780851 A 780852 A and 78F0852 in general Read this manual in the order of the CONTENTS How to read register formats The name of a bit whose number is enclosed in square is reserved for the RA78K 0 and is defined for the CC78K 0 by the header file sfrbit h To learn the detailed functions of a register whose register name is known See APPENDIX C REGISTER INDEX The application examples in this manual are for the standard model for general purpose electronic systems If the examples in this manual are to be used for applications where a quality higher than that of the special model is required study the quality grade of the respective components and circuits actually used Data significance Higher digits on the left and lower digits on the right Active low representation
68. file Device file Debugging Tools System simulator Integrated debugger Device file Embedded Software Real time OS OS Host machine PC Interface adapter PC card interface etc Flash memory writing environment In circuit emulator Flash programmer Emulation board On chip flash memory version Emulation probe Conversion socket or conversion adapter Target system 298 Preliminary User s Manual U14581EJ3VOUMOO Power unit APPENDIX A DEVELOPMENT TOOLS A 1 Language Processing Software RA78K 0 Assembler Package This assembler converts programs written in mnemonics into an object code executable with a microcontroller Further this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization This assembler is used in combination with an optional device file DF780852 Caution when using in PC environment This assembler package is a DOS based application however using Project Manager which is included in the assembler package enables use of this assembler in a Windows environment Part Number uS xxxRA78KO0 CC78K 0 C Compiler Package This compiler converts programs written in C language into an object code executable with a microcontroller This compiler is used in combination with an optional assembler package 78 0 and device fil
69. fw 4 09 kHz Preliminary User s Manual U14581EJ3VOUMOO 139 CHAPTER 9 WATCH TIMER 9 4 Watch Timer Operations 9 4 14 Watch timer operation When the 8 38 MHz main system clock is used the timer operates as a watch timer with a 0 25 second interval The watch timer generates interrupt requests at a constant time interval When bit 0 WTMO and bit 1 WTM1 of the watch timer mode control register WTM are set to 1 the count operation starts When set to 0 the 5 bit counter is cleared and the count operation stops For simultaneous operation of the interval timer zero second start can be set only for the watch timer by setting WTM to 0 However since the 9 bit prescaler is not cleared the first overflow of the watch timer INTWT after zero second start may include an error of up to 29 x 1 fw 9 4 2 Interval timer operation The watch timer operates as interval timer which generates interrupt request repeatedly at an interval of the preset count value The interval time can be selected with bits 4 to 6 WTM4 to WTM6 of the watch timer mode control register WTM Table 9 3 Interval Timer Interval Time WTM6 WTMS WTM4 interval Time When Operated at When Operated at fw 2 65 4 kHz fw 4 09 kHz 2 x 1 fw 25 x 1 fw 28 x 1 fw 27 x 1 fw 28 x 1 fw 29 x 1 fw Other than above Setting prohibited Remark fw Watch timer clock frequency 140 Preliminary User s Manual U14581EJ3V0UMOO
70. is required to secure an oscillation stabilization time after the STOP mode is cleared select the HALT mode if it is necessary to start processing immediately upon interrupt request In either of these two modes all the contents of registers flags and data memory just before the standby mode is set are held The input output port output latch and output buffer status are also held Cautions 1 When operation is transferred to the STOP mode be sure to stop the peripheral hardware operation and execute the STOP instruction 2 The following sequence is recommended for power consumption reduction of the A D converter First clear bit 7 ADCS1 of the A D converter mode register ADM1 to 0 to stop the A D conversion operation and then execute the HALT or STOP instruction Preliminary User s Manual U14581EJ3VOUMOO 263 CHAPTER 20 STANDBY FUNCTION 20 1 2 Standby function control register The wait time after the STOP mode is cleared upon interrupt request is controlled with the oscillation stabilization time select register OSTS OSTS is set with an 8 bit memory manipulation instruction RESET input sets OSTS to 04H Figure 20 1 Oscillation Stabilization Time Select Register OSTS Format Address FFFAH After Reset 04H R W Symbol Z 6 5 4 3 2 1 0 oss o o o o o osrs oss ostso OSTS0 Oscillation Stabilization Time Selection When STOP Mode Is Cleared 212 fx 488 us 214 fx 1 95 ms 215 fx 3 91
71. m ji in nterrupt received in nterrupt received 1 1 1 1 TlOn Ta nn 1 1 nia Interval time Interval time Interval time Remarks 1 Interval time N 1 xt N 00H to FFH 2 n 2 3 128 Preliminary User s Manual U14581EJ3V0UM00 CHAPTER 8 8 TIMER EVENT COUNTERS 2 TM2 AND 3 Figure 8 7 Interval Timer Operation Timings 2 3 b When CRn 00H Count clock Ar ET EIE E ETE TMn OOH OOH 1 R CRn OOH i OOH 1 TER 10121 o3 Interval time c When CRn FFH i t 177 27 e TrET s RN INTTMn Es Interrupt received Interrupt received TlOn 72 l Interval time Remark 2 3 Preliminary User s Manual U14581EJ3V0UMOO 129 CHAPTER 8 8 TIMER EVENT COUNTERS 2 TM2 AND 3 Figure 8 7 Interval Timer Operation Timings 3 3 d Operated by CRn transition M N Count clock TM N I CHn N M i TCEn INTTMn 4 U CRn transition TMn overflows since M lt N e Operated by CRn transition M gt N cutdock LE L
72. mode Oscillation Oscillation Oscillation Clock stop Remarks 1 fx Main system clock oscillation frequency 2 Figures in parentheses apply to operation with fx 8 38 MHZ Table 20 2 Operation after HALT Mode Clear Clear Source Operation Maskable interrupt request Next address instruction execution Interrupt service execution Next address instruction execution Interrupt service execution HALT mode hold Non maskable interrupt request Interrupt service execution RESET input Reset processing x don t care Preliminary User s Manual U14581EJ3V0UMOO 267 CHAPTER 20 STANDBY FUNCTION 20 2 2 STOP mode 1 STOP mode setting and operating status The STOP mode is set by executing the STOP instruction Cautions 1 When the STOP mode is set the X2 pin is internally connected to Von viaa pull up resistor to minimize the leakage current at the crystal oscillator Thus do notuse the STOP mode in a system where an external clock is used for the main system clock 2 Because the interrupt request signal is used to clear the standby mode if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset the standby mode is immediately cleared if set Thus the STOP mode is reset to the HALT mode immediately after execution of the STOP instruction After the wait set using the oscillation stabilization time select register OSTS the operation mode is set
73. ms 216 fx 7 81 ms 217 fx 15 6 ms Other than above Setting prohibited Caution The waittime after the STOP mode is cleared does not include the time see a in the illustration below from STOP mode clear to clock oscillation start regardless of clearance by RESET input or by interrupt request generation STOP mode clear X1 pin voltage waveform Vss Remarks 1 fx Main system clock oscillation frequency 2 Figures in parentheses apply to operation with fx 8 38 MHz 264 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 20 STANDBY FUNCTION 20 2 Standby Function Operations 20 2 1 HALT mode 1 HALT mode setting and operating status The HALT mode is set by executing the HALT instruction The operating status in the HALT mode is described below Table 20 1 HALT Mode Operating Status HALT Mode Setting During HALT Instruction Execution Using Main System Clock Clock generator Main system clock can be oscillated Clock supply to CPU stops CPU Operation stops Port Output latch Status before HALT mode setting is held 16 bit timer Operable 8 bit timer Watch timer Watchdog timer A D converter Operation stops Serial interface Operable LCD controller driver External interrupt Sound generator Meter controller driver Preliminary User s Manual U14581EJ3VOUMOO 265 CHAPTER 20 STANDBY FUNCTION 2 HALT mode clear Th
74. operation Status Checks the current operation mode and operation end Oscillation frequency setting Inputs the resonator oscillation frequency information Delete time setting Inputs the memory delete time Baud rate setting Sets the transmission rate when the UART method is used Silicon signature read Outputs the device name memory capacity and device block information Preliminary User s Manual U14581EJ3V0UM00 279 CHAPTER 22 4PD78F0852 22 3 3 Flashpro Ill connection Connection of Flashpro IIl and the uPD78F0852 differs depending on the transmission method 3 wire serial I O and UART Each case of connection shows in Figures 22 4 22 5 and 22 6 Figure 22 4 Flashpro 11 Connection Using 3 Wire Serial I O Method 5103 Flashpro III 78 0852 Figure 22 5 Flashpro Connection Using 3 Wire Serial I O Method 5102 Flashpro III uPD78F0852 Figure 22 6 Flashpro 11 Connection Using UART Method Flashpro Ill Lu PD78F0852 280 Preliminary Users Manual U14581EJ3VOUMOO CHAPTER 23 INSTRUCTION SET This chapter lists the instruction set of the uPD780852 Subseries For details of the operation and machine language instruction code refer to the separate document 78K 0 SERIES USER S MANUAL Instructions 012326 Preliminary User s Manual U14581EJ3V0UMOO 281 CHAPTER 23 INSTRUCTION SET 23 1 Legend for Opera
75. register EGP 00H External interrupt falling edge enable register EGN Preliminary User s Manual U14581EJ3V0UMOO 00H CHAPTER 22 uPD78F0852 The uPD78F0852 is a version with a flash memory in uPD780852 Subseries The uPD78F0852 replaces the internal ROM of the uPD780852 A with flash memory to which a program can be written deleted and overwritten while mounted on a board Table 22 1 lists the differences between the uPD78F0852 and the mask ROM version Table 22 1 Differences between 078 0852 Mask ROM Version Internal ROM type uPD78F0852 Flash memory uPD780851 A Mask ROM uPD780852 A Internal ROM capacity 40 Kbytes 32 Kbytes 40 Kbytes IC pin None Available VPP pin Available None Electrical specifications See data sheet of each product Quality grade Standard for general electronic devices Special for highly reliable electronic devices Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions When pre producing an application set with the flash memory version and then mass producing it with the mask ROM version be sure to conduct sufficient evaluations for the commercial samples not engineering samples of the mask ROM version Preliminary User s Manual U14581EJ3V0UMOO 275 CHAPTER 22 4PD78F0852 22 1 Memory Size Switching Register IMS The uPD78F0852 a
76. registers are specified by implied addressing 66 Preliminary Users Manual U14581EJ3VOUMOO CHAPTER 3 CPU ARCHITECTURE 3 4 2 Register addressing Function The general register to be specified is accessed as an operand with the register specify code Rn and RPn in an operation code and with the register bank select flags RBSO and RBS1 Register addressing is carried out when an instruction with the following operand format is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the operation code Operand format X A B ED L H r rp AX BC DE HL and rp can be described with function names X A C B E D L H AX BC DE and HL as well as absolute names RO to R7 and RPO to RP3 Description example MOV A C when selecting C register as r Operation code 01100010 L Register specify code INCW DE when selecting DE register pair as rp Operation code 10000100 Register specify code Preliminary User s Manual U14581EJ3VOUM00 67 CHAPTER 3 CPU ARCHITECTURE 3 4 3 Direct addressing Function The memory to be manipulated is addressed with immediate data in an instruction word becoming an operand address Operand format addr16 Label or 16 bit immediate data Description example MOV A OFEOOH when setting l addr16 to FE00H Operation code 10001110 OP code 00000000 OOH 1 1 11111 0 FEH Operati
77. request acknowledge Example 2 Multiple interrupt servicing does not occur due to priority control Main processing INTxx servicing INTyy servicing 1 instruction execution IE 0 RETI Y Interrupt request INTyy issued during servicing of interrupt INTxx is not acknowledged because its priority is lower than that of INTxx and multiple interrupt servicing does not take place The INTyy interrupt request is held pending and is acknowledged following execution of one main processing instruction 0 Higher priority level 1 Lower priority level IE 0 Interrupt request acknowledge disable Preliminary User s Manual U14581EJ3VOUMOO 259 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19 14 Multiple Interrupt Examples 2 2 Example 3 Multiple interrupt servicing does not occur because interrupt is not enabled Main processing INTxx servicing servicing 0 PR 0 ia 1 instruction execution IE 0 RETI Interrupt is not enabled during servicing of interrupt INTxx El instruction is not issued therefore interrupt request INTyy is not acknowledged and multiple interrupt servicing does not take place The INTyy interrupt request is held pending and is acknowledged following execution of one main processing instruction PR 0 Higher priority level IE 0 Interrupt request acknowledge disable 260 Preliminary Users Manual U14581EJ3VOUMOO CHAPTE
78. s Manual U14581EJ3VOUMOO 157 CHAPTER 12 A D CONVERTER 2 Analog input channel specification register ADS1 This register specifies the analog voltage input port for A D conversion ADS is set with an 8 bit memory manipulation instruction RESET input clears ADS1 to 00H Figure 12 4 Analog Input Channel Specification Register ADS1 Format Address FF81H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 asi o o o o o aos ADS ADSIO ADS12 ADS11 ADS10 Analog Input Channel Specification ANIO ANI1 ANI2 4 Other than above Setting prohibited Caution 3 to 7 must be set to 0 158 Preliminary User s Manual U14581EJ3VOUMOO CHAPTER 12 A D CONVERTER 3 Power fail compare mode register PFM The power fail compare mode register PFM controls a comparison operation RESET input clears PFM to 00H Figure 12 5 Power Fail Compare Mode Register PFM Format Address FF82H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 PM PEN prom o o o o o 0 Power fail comparison disabled used as normal A D converter Power fail comparison enabled used to detect power failure Power Fail Compare Mode Selection ADCR1 gt Generates interrupt request signal INTAD ADCR1 PFT Does not generate interrupt request signal INTAD ADCR1 2 PFT Does not generate interrupt request signal INTAD ADCR1 lt PFT Generates int
79. set LCDTM is a register used to set a probe board IE 780852 NS EM4 LCDTM is a write only register that controls supply of the LCD clock Unless LCDTM is set the LCD controller driver does not operate Therefore set bit 1 TMC21 of LCDTM to 1 when using the LCD controller driver Figure 16 12 LCD Timer Control Register LCDTM Format Address FF4AH After Reset 00H W Symbol 7 6 5 4 3 2 1 0 0 LCD controller driver stop mode supply of LCD clock is stopped 1 LCD controller driver operation mode supply of LCD clock is enabled Cautions 1 LCDTM is a special register that must be set when debugging is performed with an in circuit emulator Even if this register is used the operation of the 0780852 Subseries is not affected However delete the instruction that manipulates this register from the program at the final stage of debugging 2 Bits 7 to 2 and 0 must be set to 0 Preliminary User s Manual U14581EJ3V0UM00 221 MEMO 222 Preliminary User s Manual U14581EJ3VOUMOO CHAPTER 17 SOUND GENERATOR 17 1 Sound Generator Function The sound generator has the function to sound the buzzer from an external speaker and the following signal are output Basic cycle output signal The signal is a buzzer signal with a variable frequency By setting bits 0 to 2 SGCLO to SGCL2 of the sound generator control register SGCR the signal in a range of 0 12 to 4 0 kHz can be output when fx 8 38 MHz The amplitude of the
80. to INTP2 SCK2 502 SI2 P10 to P14 Input Port 1 5 bit input only port ANIO to ANI4 P20 to P23 P24 to P27 Output Port 2 8 bit output only port SM11 to SM14 SM21 to SM24 P30 to P33 P34 to P37 Output Port 3 8 bit output only port SM31 to SM34 SM41 to SM44 P40 to P42 P43 P44 Input Output Port 4 5 bit input output port Input output mode can be specified in 1 bit units TIOO to TIO2 TIO2 P50 P51 P52 P53 P54 Input Output Port 5 5 bit input output port Input output mode can be specified in 1 bit units SCK3 503 513 RxD TxD P60 P61 Input Output Port 6 2 bit input output port Input output mode can be specified in 1 bit units PCL TPO SGO P81 to P87 Input Output Port 8 7 bit input output port Input output mode can be specified in 1 bit units Can be set in input output port or segment output mode in 2 bit units with the LCD display control register LCDC 19 to S13 P90 to P97 76 Input Output Port 9 8 bit input output port Input output mode can be specified in 1 bit units Can be set in input output port or segment output mode in 2 bit units with the LCD display control register LCDC Preliminary User s Manual U14581EJ3V0UMOO 51210 S5 CHAPTER 4 PORT FUNCTIONS 4 2 Port Configuration A port consists of the following hardware Table 4 2 Port Configuration Item Configurati
81. to other data stop the timer operation PCE 0 beforehand 2 Bits 0 to 3 6 and 7 must be set to 0 234 Preliminary User s Manual U14581EJ3VOUMOO CHAPTER 18 METER CONTROLLER DRIVER 2 Compare control register n MCMPCn MCMPOn is an 8 bit register that controls the operation of the compare register and output direction of the PWM pin MCMPOn is set with an 8 bit memory manipulation instruction RESET input clears MCMPCn to OOH Figure 18 4 shows the MCMPOn format Figure 18 4 Compare Control Register n MCMPCn Format Address FF6BH to FF6EH After Reset 00H R W Symbol Transfer Enable Control Bit by Register from Master to Slave Disables data transfer from master to slave New data can be written Transfers data from master to slave when MCNT overflows New data cannot be written ADBn1 1 Bit Addition Circuit Control cos side of meter n No 1 bit addition to PWM output 1 bit addition to PWM output 1 Bit Addition Circuit Control sin side of meter n No 1 bit addition to PWM output 1 bit addition to PWM output Note TENn functions as a control bit and status flag As soon as the timer overflows and PWM data is output TENn is cleared to 0 by hardware Caution Bits 5 to 7 must be set to 0 Remark 1 4 Preliminary User s Manual U14581EJ3VOUMOO 235 CHAPTER 18 METER CONTROLLER DRIVER 3 Port mode control register PMC PMC is a
82. to the output mode PM54 0 When transceiving Set P53 to the input mode and P54 to the output mode Address FF85H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 Operation Mode Operation stop RxD P53 Pin Function Port function P53 TxD P54 Pin Function Port function P54 UART mode receive only Serial function RxD Port function P54 UART mode Port function P53 Serial function TxD transmit only UART mode Serial function RxD Serial function TxD transmit and receive Parit Bit Specification 0 0 No parity 0 1 Zero parity always added during transmission No parity detection during reception parity errors do not occur 1 0 Odd parity 1 1 Even parity Character Length Specification 7 bits 8 bits Stop Bit Length Specification for Transmit Data 1 bit 2 bits Receive Completion Interrupt Control When Error Occurs Receive completion interrupt is issued when an error occurs Receive completion interrupt is not issued when an error occurs Cautions 1 Do not switch the operation mode until after the current serial transmit receive operation has stopped 2 Bit 0 must be set to 0 176 Preliminary Users Manual U14581EJ3V0UMOO CHAPTER 13 SERIAL INTERFACE UART b Asynchronous serial interface status register ASIS ASIS is read with an 8 bit memory manipulation instruction RESET input clears ASIS to 00H Address FF86H After Reset 00H R Symbol
83. u u u u 232 18 3 Meter Controller Driver Control Registers 1 u u u u 234 18 4 Meter Controller Driver Operations U 237 18 4 1 Basic operation of free running up counter 2 2 0 22 4 00 0 eene 237 18 4 2 To update PWM data eren retener eek 237 18 4 3 1 bit addition circuit operation nennen nennen nennen nnne 238 18 4 4 PWM output operation output with 1 clock 239 CHAPTER 19 INTERRUPT 241 19 1 Interrupt Function Types 241 19 2 Interrupt Sources and Configuration 241 19 3 Interrupt Function Control Registers eese seen u u 245 19 4 Interrupt Servicing Operations u U enn nnne u nn nnn 252 19 4 1 Non maskable interrupt request acknowledge operation 252 19 4 2 Maskable interrupt request acknowledge operation 2 255 19 4 3 Software interrupt request acknowledge operation 0 257 19 4 4 Multiple interrupt servicing 2 einer iater tei ind 258 19 4 5
84. values of CR2 and within to during count operation RESET input clears these regiters to 00H Preliminary User s Manual U14581EJ3V0UMOO 123 CHAPTER 8 8 BIT COUNTERS 2 TM2 AND 3 8 3 8 Bit Timer Event Counters 2 2 and 3 Control Registers The following three types of registers are used to control 8 bit timer event counters 2 TM2 and 3 TM3 Timer clock select registers 2 3 TCL2 8 bit timer mode control registers 2 3 TMC2 TMC3 Port mode register 4 4 1 Timer clock select registers 2 3 TCL2 TCL3 These registers set count clocks of 8 bit counters 2 and TM2 and TCL2 and TCL3 are set with an 8 bit memory manipulation instruction RESET input clears these registers to 00H Figure 8 3 Timer Clock Select Register 2 TCL2 Format Address FF74H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 TCL2 TCL22 TCL21 TCL20 L3 T I II Tre TIO2 falling edge TIO2 rising edge fx 23 1 04 MHz fx 25 261 kHz fx 27 65 4 kHz fx 28 32 7 kHz fx 29 16 3 kHz 211 4 09 kHz Cautions 1 When rewriting TCL2 to other data stop the timer operation beforehand 2 Bits 3 to 7 must be set to 0 Remarks 1 fx Main system clock oscillation frequency 2 Figures in parentheses apply to operation with fx 8 38 MHz 124 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 8 8 BIT TIMER EV
85. 0 MCMP31 MCMPA0 MCMP41 MCMPC1 2 MCMPCA MKOH MKOL MK1L O OSCM OSTS P P1 P2 P3 P4 P5 P6 P8 P9 PCC PFM PFT PMO 2 PM3 PM4 5 6 8 PM9 PMC PROH PROL PRIL PRMO PSW PUO R RXB Compare register sin side 233 Compare register cos side 233 Compare register sin side 233 Compare register cos side 233 Compare control register 1 235 Compare control register 2 235 Compare control register 3 235 Compare control register 4 235 Timer mode control register 234 Interrupt mask flag register OH 247 Interrupt mask flag register OL 247 Interrupt mask flag register 1L 247 Oscillator mode register 93 Oscillation stabilization time select register 264 Port 0 38 77 Port 1 38 78 Port 2 39 79 Port 3 39 80 Port 4 39 81 Port 5 40 82 Port 6 40 83 Port 8 41 84 Port 9 41 85 Processor clock control register 92 Power fail compare mode register 159 Power fail compare threshold value register 159 Port mode register O 86 192 Port mode register 2 86 Port mode register 3 86 Port mode register 4 86 107 127 Port mode register 5 86 Port mode register 6 86 151 Port mode register 8 86 Port mode register 9 86 Port mode control register 236 Priority specify flag register OH 248 Priority spe
86. 0 itis converted to the non selection voltage and output to a segment SO to 519 818 to S5 have an alternate function as input output port pins Consequently it is necessary to check what combination of front surface electrodes corresponding to the segment signals and rear surface electrodes corresponding to the common signals of the LCD panel to be used form the display pattern and then write bit data corresponding on a one to one basis with the pattern to be displayed Bits 4 to 7 are fixed at O Common signal and segment signal output waveforms The voltages shown in Table 16 4 are output in the common signals and segment signals The Vicp ON voltage is only produced when the common signal and segment signal are both at the selection voltage other combinations produce the OFF voltage Table 16 4 LCD Drive Voltage Segment Signal Selection Signal Level Non Selection Signal Level Common Signal Vss1 Vico Vici Vice Selection signal level Vico Vss Vicp 1 3Vucp 1 3Vicp Non selection signal level Vice Vic 1 3Vucp 1 3Vucp 1 3Vucp 1 3Vicp Preliminary User s Manual U14581EJ3V0UM00 CHAPTER 16 LCD CONTROLLER DRIVER Figure 16 6 shows the common signal waveform and Figure 16 7 shows the common signal and segment signal voltages and phases Figure 16 6 Common Signal Waveform COMn Divided by 4 T One LCDCL cycle Tr Frame frequency Figure 16 7 Common Si
87. 013 Caution When purchasing the RX78K O fill in the purchase application form in advance and sign the User Agreement Remark AAAA in the part number differ depending on the host machine and OS used Lu SxxxxRX78013 AAAA Product Outline Upper Limit of Mass Production Quantity Evaluation object Do not use for mass produced products Object for mass produced product 0 1 million units 1 million units 10 million units Source program Source program for mass produced object Host Machine Supply Medium PC 9800 Series Windows Japanese version Notes 2 3 5 inch 2HD FD PC AT and compatibles Windows Japanese version Notes 1 2 3 5 inch 2HC FD Windows English version Notes 1 2 HP9000 Series 700 HP UX Rel 9 05 DAT DDS SPARCstation SunOS Rel 4 1 4 3 5 inch 2HC FD Solaris Rel 2 5 1 1 4 inch CGMT NEWS RISC NEWS OS Rel 6 1 3 5 inch 2HC FD Notes 1 DOS is also supported 2 WindowsNT is not supported Preliminary User s Manual U14581EJ3VOUMOO 305 APPENDIX B EMBEDDED SOFTWARE Real Time OS 2 2 78 0 LITRON specification subset OS Nucleus of MX78KO0 is supplied OS This OS performs task management event management and time management It controls the task execution sequence for task management and selects the task to be executed next Caution when using in PC environment MX78K0 is a DOS based applic
88. 1 read operation is disabled Remark 1 2 79 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 4 PORT FUNCTIONS 4 2 4 Port 3 Port 3 is an 8 bit output only port with output latch P30 to P37 pins go into a high impedance state when the ENn of port mode control register PMC is set to 0 and the port mode register 3 PM3 is set to 1 Alternate functions include meter control PWM output RESET input sets port 3 to high impedance state Figure 4 5 shows a block diagram of port 3 Figure 4 5 P30 to P37 Block Diagram Internal bus Output latch P30 to P37 P30 SM31 to P33 SM34 p34 SM41 to P37 SM44 Selector PM30 to PM37 D gt Alternate functions Decoder PM Port mode register RD Port 3 read signal WR Port 3 write signal Caution When PM3is setto 0 read operation is enabled When is setto 1 read operation is disabled Remark 3 4 80 Preliminary User s Manual U14581EJ3VOUMOO CHAPTER 4 PORT FUNCTIONS 4 2 5 Port 4 Port 4 is 5 bit input output port with output latch 40 to 44 pins can specify the input mode output mode 1 bit units with the port mode register 4 4 Alternate functions also include timer input output RESET input sets port 4 to input mode Figure 4 6 shows a block diagram of port 4 Figure 4 6 P40 to P44 Block Diagram D P40 T100 to P42 T102 Output latch P40 to P44
89. 1 valid edge is performed with the prescaler mode register PRMO When the valid edge of the TIO1 is detected an interrupt request INTTMO1 is generated CR01 is set with a 16 bit memory manipulation instruction RESET input makes 01 to undefined Capture register 02 02 The valid edge of the TIO2 can be selected as the capture trigger Setting of the 02 valid edge is performed with the prescaler mode register PRMO When the valid edge of the TIO2 is detected an interrupt request INTTMO2 is generated 02 is set with a 16 bit memory manipulation instruction RESET input makes 02 to undefined Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 6 16 BIT TIMER 0 TMO 6 4 16 Bit Timer 0 TMO Control Registers The following four types of registers are used to control 16 bit timer 0 TMO 16 bit timer mode control register TMCO Capture pulse control register CRCO Prescaler mode register PRMO Port mode register 4 4 1 16 bit timer mode control register TMCO This register sets the 16 bit timer operation mode and controls the prescaler output signals TMCO is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears TMCO to Figure 6 2 16 Bit Timer Mode Control Register TMCO Format Address FF72H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 0 Operation stop TMO cleared to 0 1 Operation enabled TPOE Prescaler O
90. 12 16 5 LCD Display Data Memory J U U u u 213 16 6 Common Signals and Segment Signals uu 214 16 7 Supplying LCD Drive Voltage Vico Vici and VLC2 216 16 8 Display Djs 218 16 8 1 4 time division display example 4 4 3 218 16 9 Cautions on Emulation eicere peruana omen nina aan 221 16 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 17 SOUND GENERATOR 4 1 1 4 1 223 17 1 Sound Generator Function 223 17 2 Sound Generator Configuration U UU asina nnn 224 17 3 Sound Generator Control Registers J l u 225 17 4 Sound Generator Operations l l u 229 17 41 To output basic cycle signal SQQ e Re ts 229 CHAPTER 18 METER CONTROLLER DRIVER J l u u u u 231 18 1 Meter Controller Driver Functions U 231 18 2 Meter Controller Driver Configuration l l l
91. 15 0 4 When S 0 all bits of are 0 When S 1 all bits of o are 1 Preliminary User s Manual U14581EJ3VOUMOO 63 CHAPTER 3 CPU ARCHITECTURE 3 3 2 Immediate addressing Function Immediate data in the instruction word is transferred to the program counter PC and branched This function is carried out when the CALL laddr16 BR addr16 or CALLF addr11 instruction is executed CALL addr16 and BR laddr16 instructions can be branched to the entire memory space The CALLF addr11 instruction is branched to the 0800H to OFFFH area Operation In the case of CALL addr16 and BR addr16 instructions 7 0 CALL or BR Low Addr High Adar 15 87 0 In the case of CALLF addr11 instruction 64 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 3 CPU ARCHITECTURE 3 3 3 Table indirect addressing Function Table contents branch destination address of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter PC and branched This function is carried out when the CALLT addr5 instruction is executed This instruction references the address stored in the memory table from 40H to 7FH and allows branching to the entire memory space Operation 7 6 5 1 0 15 8 7 65 10 Effective address 000000000 T Memory table 0 Low Addr Effective address 1 High Addr
92. 15 8 7 0 PC 3 3 4 Register addressing Function Register pair AX contents to be specified with an instruction word are transferred to the program counter PC and branched This function is carried out when the BR AX instruction is executed Operation Preliminary Users Manual U14581EJ3VOUMOO 65 CHAPTER 3 CPU ARCHITECTURE 3 4 Operand Address Addressing The following methods are available to specify the register and memory addressing which undergo manipulation during instruction execution 3 4 1 Implied addressing Function The register which functions as an accumulator A and AX in the general register is automatically implicitly addressed Of the wPD780852 Subseries instruction words the following instructions employ implied addressing Instruction Register to be Specified by Implied Addressing MULU Register A for multiplicand and register AX for product storage DIVUW Register AX for dividend and quotient storage ADJBA ADJBS Register A for storage of numeric values subject to decimal adjustment ROR4 ROL4 Register A for storage of digit data subject to digit rotation Operand format Because implied addressing can be automatically employed with an instruction no particular operand format is necessary Description example In the case of MULU X With an 8 bit x 8 bit multiply instruction the product of A register and X register is stored in AX In this example the A and AX
93. 1L must be set to 1 Preliminary User s Manual U14581EJ3VOUM00 CHAPTER 19 INTERRUPT FUNCTIONS 4 External interrupt rising edge enable register EGP and external interrupt falling edge enable register EGN These registers specify the valid edge for INTPO to INTP2 EGP and EGN are set with a 1 bit or 8 bit memory manipulation instruction RESET input clears these registers to 00H Figure 19 5 External Interrupt Rising Edge Enable Register EGP and External Interrupt Falling Edge Enable Register EGN Format Address FF48H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 ep o o o o o E2 EGPO Address FF49H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 cen o o o o o INTPn Pin Valid Edge n 0 to 2 Interrupt disabled Falling edge Rising edge Both rising and falling edges Preliminary User s Manual U14581EJ3V0UM00 249 CHAPTER 19 INTERRUPT FUNCTIONS 5 Prescaler mode register PRMO This register specifies the valid edge for 00 40 to TIO2 P42 pins input PRMO is set with an 8 bit memory manipulation instruction RESET input clears PRMO to 00H Figure 19 6 Prescaler Mode Register PRMO Format Address FF70H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 Falling edge Rising edge Interrupt disabled Both rising and falling edges TIO1 Valid Edge Selection Falling edge Rising edge Interrupt disable
94. 2 input output also used for 8 bit PWM output 8 bit timer TM3 input output also used for 8 bit PWM output Input P43 P44 TPO Output Prescaler signal output of 16 bit timer TMO Input PCL P60 PCL Output Clock output for main system clock trimming Input TPO P60 SGO Output Sound generator signal output Input P61 50 to S4 S5 to 512 51310 519 Output Segment signal output of LCD controller driver Output Input P97 to P90 P87 to P81 COMO to COM3 Output Common signal output of LCD controller driver Output Vreo LCD driving power supply SM11 to SM14 SM21 to SM24 SM31 to SM34 SM41 to SM44 Output Meter control signal output P20 to P23 P24 to P27 P30 to P33 P34 to P37 ANIO to ANI4 A D converter analog input P10 to P14 AVREF A D converter reference voltage input shared with analog power supply AVss A D converter ground potential Connect to Vsso RESET System reset input X1 X2 Crystal connection for main system clock oscillation Power supply for meter controller driver Ground potential for meter controller driver Port block positive power supply 36 Port block ground potential Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 2 PIN FUNCTION Function Regulator output pin for power supply of pins other tha
95. 25 POT A ioi Ed Lai EA Lu e re E 81 4 26 POMO drop e 82 LEN 83 e228 2 Io pe ER 84 429 POM EE 85 4 3 Port Function Control Registers U 86 4 4 Port F nction Operations ide ea oae ce iuueni ore aude nu uda 89 4 4 1 Writing to input output Ea EaR 89 4 4 2 Reading from input output 89 4 4 3 Operations on lt ege de guia 89 CHAPTERS CLOCK 222 2 denuo DU coran 91 5 1 Clock Generator Functions 91 5 2 Clock Generator Configuration 91 5 3 Clock Generator Control Registers 1 92 5 4 System Clock Oscillatoria assasi nana norme p nada ren 94 5 4 1 Mairisystem clock Oscillator 5 2 ayau Sasi 94 54 2 DIVIGSR CIRCUIT t 96 5 5 Clock Generator Operations i 97 5 6 Changing Setting of CPU Clock 98 5 6 1 Time required for switching CPU
96. 3 jdisp8 if A bit 1 then reset A bit PSW bit addr16 PC PC 4 jdisp8 if PSW bit 1 then reset PSW bit HL bit addr16 PC lt PC 3 jdisp8 if HL bit 1 then reset HL bit B addr16 B lt B 1 then PC PC 2 jdisp8 if Bz 0 C addr16 C C 1 then PC PC 2 jdisp8 if C 0 saddr addr16 saddr saddr 1 then PC lt PC 3 jdisp8 if saddr 0 RBn RBS1 0 lt n No Operation IE 1 Enable Interrupt IE 0 Disable Interrupt Set HALT Mode Notes 1 When the internal high speed RAM area is accessed or instruction with no data access Set STOP Mode 2 When an area except the internal high speed RAM area is accessed Remark One instruction clock cycle is one cycle of the CPU clock fceu selected by the processor clock control register PCC Preliminary User s Manual U14581EJ3V0UMOO 291 CHAPTER 23 INSTRUCTION SET 23 3 Instructions Listed by Addressing Type 1 8 bit instructions MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MULU DIVUW INC DEC ROR ROL RORC ROLC ROR4 ROL4 PUSH POP DBNZ 292 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 23 INSTRUCTION SET Second Operand First Operand laddr16 HL byte HL B HL C addr16 HL byte HL B HL C X C Note Exceptr
97. 33 Fax 01908 670 290 NEC Electronics Italiana s r l Milano Italy Tel 02 66 75 41 Fax 02 66 75 42 99 NEC Electronics Germany GmbH Benelux Office Eindhoven The Netherlands Tel 040 2445845 Fax 040 2444580 NEC Electronics France S A Velizy Villacoublay France Tel 01 30 67 58 00 Fax 01 30 67 58 99 NEC Electronics France S A Madrid Office Madrid Spain Tel 91 504 2787 Fax 91 504 2860 NEC Electronics Germany GmbH Scandinavia Office Taeby Sweden Tel 08 63 80 820 Fax 08 63 80 388 Preliminary User s Manual U14581EJ3V0UMOO NEC Electronics Hong Kong Ltd Hong Kong Tel 2886 9318 Fax 2886 9022 9044 NEC Electronics Hong Kong Ltd Seoul Branch Seoul Korea Tel 02 528 0303 Fax 02 528 4411 NEC Electronics Singapore Pte Ltd United Square Singapore Tel 65 253 8311 Fax 65 250 3583 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 2719 2377 Fax 02 2719 5951 NEC do Brasil S A Electron Devices Division Guarulhos SP Brasil Tel 55 11 6462 6810 Fax 55 11 6462 6829 J00 7 MEMO 8 Preliminary User s Manual U14581EJ3VOUM00 Readers Purpose Organization How to Read This Manual Conventions INTRODUCTION This manual has been prepared for user engineers who want to understand the functions of the uPD780852 Subseries and design and develop its application systems and programs LuPD780852 Subseries uPD780851 A 780852 A 78F0852 This manual is
98. 3583 Fax 1 800 729 9288 1 408 588 6130 Europe Korea Japan NEC Electronics Europe GmbH NEC Electronics Hong Kong Ltd NEC Semiconductor Technical Hotline Seoul Branch Fax 044 435 9608 Technical Documentation Dept Fax 02 528 4411 Fax 49 211 6503 274 South America Taiwan NEC do Brasil S A NEC Electronics Taiwan Ltd Fax 55 11 6462 6829 Fax 02 2719 5951 would like to report the following error make the following suggestion Document title Document number Page number If possible please fax the referenced page or drawing Document Rating Excellent Acceptable Clarity Technical Accuracy Organization
99. 4 0 117 7 5 8 Bit Timer 1 1 Cautions 120 8 8 BIT TIMER EVENT COUNTERS 2 2 AND 121 8 1 8 Bit Timer Event Counters 2 TM2 and 3 Functions 121 8 2 8 Bit Timer Event Counters 2 TM2 and 3 Configurations 123 8 3 8 Bit Timer Event Counters 2 TM2 and 3 Control Registers 124 8 4 8 Bit Timer Event Counters 2 2 and 3 Operations 128 8 4 1 8 bit interval timer Operation ics ssc u i A dene Ld q reU Pe ee ERE Euh 128 8 4 2 External event counter operation nennen nennen 130 8 4 3 Square wave output operation 8 bit 131 8 4 4 8 bit PWM outp t Operation u iia Da DDR nS CR Lane RUE 132 8 5 8 Bit Timer Event Counters 2 TM2 and 3 Cautions 135 9 WATCH eroe ano et uacua x xen saa 137 91 Watch Timer FUnCtion UU ce eric erue rne renis con aser quas uana crux n inre Ou pn 137 9 2
100. 47 Interrupt mask flag register OL MKOL 247 Interrupt mask flag register 1L MK1L 247 Interrupt request flag register OH IFOH 246 Interrupt request flag register OL IFOL 246 Interrupt request flag register 1L IF1L 246 L LCD display control register LCDC 211 LCD display mode register LCDM 210 LCD timer control register LCDTM 221 M Memory size switching register IMS 276 O Oscillation stabilization time select register OSTS 264 Oscillator mode register OSCM 93 P Port 0 PO 38 77 Port 1 P1 38 78 Port 2 P2 39 79 Port 3 P3 39 80 Port 4 P4 39 81 Port 5 P5 40 82 Port 6 P6 40 83 Port 8 P8 41 84 Port 9 P9 41 85 Port mode control register PMC 236 Port mode register 0 PMO 86 192 Port mode register 2 PM2 86 Port mode register 3 PM3 86 Port mode register 4 4 86 107 127 PMS 86 86 151 Port mode register 8 8 86 Port mode register 9 PM9 86 Power fail compare mode register PFM 159 Port mode register 5 PM5 Port mode register 6 PM6 Power fail compare threshold value register PFT 159 Prescaler mode register PRMO 107 250 Priority specify flag register OH PROH 248 Priority specify flag register OL PROL 248 Priority specify flag register 1L PR1L 248 308 Preliminary User s Manual
101. 5 bits x 1 Prescaler 9 bits x 1 Control register Watch timer mode control register WTM 138 Preliminary User s Manual U14581EJ3VOUMOO CHAPTER 9 WATCH TIMER 9 3 Watch Timer Control Register The watch timer mode control register WTM is used to control the watch timer Watch timer mode control register WTM This register sets the watch timer count clock watch timer operation mode prescaler interval time and prescaler and 5 bit counter operation enable disable WTM is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears WTM to 00H Figure 9 2 Watch Timer Mode Control Register WTM Format Address FF41H After Reset 00H R W Symbol 7 6 5 4 3 2 1 WTM WTM7 WTM6 5 WTM4 WTM3 0 WTM1 WTMO WTM7 Watch Timer Count Clock Selection 0 fx 27 65 4 kHz 211 4 09 kHz WTM4 Prescaler Interval Time Selection 24 fw 3 91 ms 25 tw 7 82 ms 26 fw 15 6 ms 27 fw 31 2 ms 28 fw 62 5 ms 29 tw 125 ms Setting prohibited Normal operating mode flag set at fw 2 4 Fast feed operating mode flag set at fw 25 Clear after operation stop Start Operation stop clear both prescaler and timer Operation enabled Remarks 1 fw Watch timer clock frequency fx 2 fx 2 2 fx Main system clock oscillation frequency 3 Figures in parentheses apply to operation with fx 8 38 MHz
102. 7 bit resolution PWM signal can be varied to enable control of the buzzer sound volume Figure 17 1 shows the sound generator block diagram and Figure 17 2 shows the concept of basic cycle output signal SGO Figure 17 1 Sound Generator Block Diagram Internal bus D Sound generator control register SGCR TCE SGCL 2 5 bit counter 1 SGCL0 Selector Selector Prescaler Clear OSGO P61 PWM amplitude Comparator a e mes SGBRO SGAM6 SGAM5 SGAM4 SGAM SGAM SGAM1 SGAMO Pen output PM61 ound generator buzzer ound generator amplitude Port mode register SGBR reoisier SGAM 1 y register 6 PM6 Internal bus b Figure 17 2 Concept of Basic Cycle Output Signal SGO sae te cunt sco Preliminary User s Manual U14581EJ3V0UMOO 223 CHAPTER 17 SOUND GENERATOR 17 2 Sound Generator Configuration The sound generator consists of the following hardware Table 17 1 Sound Generator Configuration Configuration Counter 8 bits x 1 5 bits x 1 SG output SGO Control register Sound generator control register SGCR Sound generator buzzer control register SGBR Sound generator amplitude register SGAM 224 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 17 SOUND GENERATOR 17 3 Sound Generator Control Registers The following three types of registers are used to control the soun
103. 81EJ3V0UMOO CHAPTER 12 A D CONVERTER 12 3 A D Converter Control Registers The following four types of registers are used to control A D converter A D converter mode register ADM1 Analog input channel specification register ADS1 Power fail compare mode register PFM Power fail compare threshold value register PFT 1 A D converter mode register ADM1 This register sets the conversion time for analog input to be A D converted conversion start stop and external trigger ADM1 is set with an 8 bit memory manipulation instruction RESET input clears ADM1 to OOH Figure 12 3 A D Converter Mode Register ADM1 Format Address FF80H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 ADCS1 A D Conversion Operation Control 0 Conversion operation stop 1 Conversion operation enabled Conversion Time Selection Note 1 144 fx 17 2 us 120 fx 14 3 us 96 fx Note 2 288 fx 34 4 us 240 fx 28 6 us 192 fx 22 9 us Other than above Setting prohibited Notes 1 Set so that the A D conversion time is 14 us or more 2 Setting prohibited because the A D conversion time will be less than 14 us Cautions 1 Bits 0 to 2 and 6 must be set to 0 2 Whenrewriting FR10to FR12to other data stop the A D conversion operation beforehand Remarks 1 fx Main system clock oscillation frequency 2 Figures in parentheses apply to operation with fx 8 38 MHz Preliminary User
104. ARCHITECTURE 3 1 4 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions The address of an instruction to be executed next is addressed by the program counter PC for details see 3 3 Instruction Address Addressing Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the uPD780852 Subseries based on operability and other considerations For areas containing data memory in particular special addressing methods designed for the functions of special function registers SFRs and general purpose registers are available for use Data memory addressing is illustrated in Figures 3 4 to 3 6 For the details of each addressing mode see 3 4 Operand Address Addressing Figure 3 4 Data Memory Addressing uPD780851 A Special function registers SFRs SFR addressing 256 x 8 bits General registers Register addressing 32 x 8 bits Short direct addressing Internal high speed RAM 1 024 x 8 bits LLL Y FE1FH FBOOH FAFFH Reserved FA6DH Direct addressing LCD display RAM 20 x 4 bits Register indirect FA59H addressing FA58H Reserved Based addressing F800H F7FFH Based indexed addressing Internal expansion RAM 512 x 8 bits F600H F5FFH Reserved 8000H 7FFFH Internal R
105. B2 and if the next reception operation has been completed before that data is read if data is transferred to SIO2 Cautions 1 When an overflow error occurs receive data in SIO2 will not be transferred to SIRB2 even if the next receive operation for SIO2 is complete 2 When an overflow error occurs be sure to read SRBS2 clear SDOF and read SIRB2 clear SDVA If the receive operation is resumed without reading SIRB2 clearing SDVA after SDOF clear SDOF is set even if the next receive operation ends normally 3 Even if an overflow error has occurred new receive data can be received by SIO2 At this time a transmit completion interrupt INTCSI2 occurs a Serial data valid flag SDVA This flag indicates that the serial receive data buffer register SIRB2 has not been completely read It is set to 1 when the receive data has been completely transferred from the serial I O shift register 2 SIO2 to SIRB2 SDVA is cleared to 0 when SIRB2 has been read If SIRB2 is accessed for read SDVA remains cleared to 0 until the next receive data is transferred from SIO2 to SIRB2 b Overflow flag SDOF This flag indicates whether an overflow error occurs on the serial receive data buffer register SIRB2 It is automatically set to 1 to prevent a loss of receive data if data that has not yet been read remains in SIRB2 SDVA 1 if the next data has been transferred to 5102 Preliminary User s Manual U14581EJ3V0UMOO 191 CHAPT
106. C Package 34 80 pin plastic QFP 14 x 14 mm Preliminary User s Manual U14581EJ3VOUM00 2 1 Pin Function List 1 Port Pins to P02 P04 Input Output Input Output CHAPTER 2 PIN FUNCTION Function Port 0 8 bit input output port Input output mode can be specified in 1 bit units On chip pull up resistor can be used by software After Reset Alternate Function INTPO to INTP2 P10 to P14 Input Port 1 5 bit input only port ANIO to ANI4 P20 to P23 Output P24 to P27 Port 2 8 bit output only port SM11 to SM14 SM21 to SM24 P30 to P33 Output P34 to P37 Port 3 8 bit output only port SM31 to SM34 SM41 to SM44 P40 to P42 Input Output Port 4 5 bit input output port Input output mode can be specified in 1 bit units TIOO to TIO2 TIO2 Input Output P43 P44 P50 P51 Port 5 5 bit input output port Input output mode can be specified in 1 bit units SCK3 TxD Input Output Port 6 2 bit input output port Input output mode can be specified in 1 bit units PCL TPO SGO P81 to P87 Input Output Port 8 7 bit input output port Input output mode can be specified in 1 bit units Can be set in I O port mode or segment output mode 2 bit units with the LCD display control register LCDC 19 to S13 P90 to P97 Input Output Port 9 8 bit input output port Input output mode can be specified in 1 bi
107. CHAPTER 5 CLOCK GENERATOR 5 6 2 Switching CPU clock The following figure illustrates how the CPU clock switches Figure 5 6 Switching CPU Clock Voo RESET CPU clock Fastest au operation M 15 6 ms at 8 38 MHz operation Internal reset operation 1 The CPU is reset when the RESET pin is made low on power application The effect of resetting is released when the RESET pin is later made high and the main system clock starts oscillating At this time the time during which oscillation stabilizes 2 7 fx is automatically secured After that the CPU starts instruction execution at the slowest speed of the main system clock 3 81 us at 8 38 MHz operation 2 After a lapse of time long enough for the voltage to rise to the level at which the CPU can operate at its maximum speed rewrite the contents of the processor clock control register PCC to execute the maximum speed operation Preliminary User s Manual U14581EJ3V0UMOO 99 MEMO 100 Preliminary Users Manual U14581EJ3VOUMOO CHAPTER 6 16 BIT TIMER 0 TMO 6 1 Outline of Internal Timer of u PD780852 Subseries This chapter explains the 16 bit timer 0 Before that the internal timers of the w PD780852 Subseries and the related functions are briefly explained below 1 2 3 4 5 6 16 bit timer 0 TMO The TMO can be used for pulse widths measurement divided output of input pulse 8 bit timer 1 TM1 The
108. CHAPTER 9 WATCH TIMER Figure 9 3 Watch Timer Interval Timer Operation Timing 5 bit counter Overflow Overflow Start 1 fw or fw 29 Watch timer 1 1 interrupt INTWT 22 22 2 Interval timer interrupt INTWTI T L Z i 1 L duc L 1 Interval timer Remark fw Watch timer clock frequency fw 4 09 kHz 8 38 MHz Preliminary User s Manual U14581EJ3V0UM00 141 MEMO 142 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 10 WATCHDOG TIMER 10 1 Watchdog Timer Functions The watchdog timer has the following functions Watchdog timer nterval timer Caution Select the watchdog timer mode or the interval timer mode with the watchdog timer mode register WDTM Figure 10 1 shows the watchdog timer block diagram Figure 10 1 Watchdog Timer Block Diagram RUN Internal bus INTWDT _ Maskable 5 5 interrupt request o 5 E RESET 8 INTWDT Ll Non maskable interrupt request RUN WDTMAWDTMS Watchdog timer mode register WDTM select register WDCS 052 0051 1 0050 Watchdog timer clock m Internal bus Preliminary User s Manual U14581EJ3V0UMOO 143 CHAPTER 10 WATCHDOG TIMER 1 Watchdog timer mode A runaway is detected Upon detection of the runaway a non maskable interrupt request or RESET can be generated Table 10 1
109. CO 106 Capture register 00 CROO 104 Capture register 01 CRO1 104 Capture register 02 CR02 104 Clock output selection register CKS 150 Compare control register 1 MCMPC1 235 Compare control register 2 MCMPC2 235 Compare control register 3 MCMPC3 235 Compare control register 4 MCMPCA 235 Compare register cos side MCMP11 233 Compare register cos side MCMP21 233 Compare register cos side MCMP31 233 Compare register cos side MCMP41 233 Compare register sin side MCMP10 233 Compare register sin side MCMP20 233 Compare register sin side MCMP30 233 Compare register sin side MCMP40 233 D D A converter mode register DAM1 168 E 8 bit compare register 1 CR1 114 8 bit compare register 2 CR2 123 8 bit compare register 3 CR3 123 8 bit counter 1 TM1 114 8 bit counter 2 TM2 123 8 bit counter 3 TM3 123 8 bit timer mode control register 1 TMC1 116 8 bit timer mode control register 2 TMC2 125 8 bit timer mode control register 3 TMC3 125 External interrupt falling edge enable register EGN 249 Preliminary User s Manual U14581EJ3VOUMOO 307 APPENDIX C REGISTER INDEX External interrupt rising edge enable register EGP 249 l Internal expansion RAM size switching register IXS 277 Interrupt mask flag register OH MKOH 2
110. Capacity Selection 512 bytes Other than above Setting prohibited Caution The initial value of IXS is OCH Always set OBH in this register Preliminary User s Manual U14581EJ3V0UM00 277 CHAPTER 22 4PD78F0852 22 3 Flash Memory Programming On board writing of flash memory with the device mounted on the target system is supported On board writing is done after connecting a dedicated flash writer Flashpro III part number FL PR3 PG FP3 to the host machine and target system Moreover writing to flash memory can also be performed using a flash memory writing adapter connected to Flashpro Ill Remark Flashpro Ill is a product of Naito Densei Machida Mfg Co Ltd 22 3 1 Selection of transmission method Writing to flash memory is performed using Flashpro Ill and serial communication Select the transmission method for writing from Table 22 3 For the selection of the transmission method a format like the one shown in Figure 22 3 is used The transmission methods are selected with the Ver pulse numbers shown in Table 22 3 Table 22 3 Transmission Method List Transmission Method Number of Channels Pin Used Note Number of VPP Pulses 3 wire serial I O SIS P52 SO3 P51 SCK3 P50 SI2 P05 SO2 P04 SCK2 P03 RxD P53 TxD P54 Note When the device enters the flash memory programming mode the pins not used for flash memory programming are in the same status as immediately after reset If th
111. Control Register The serial operation mode register 3 CSIM3 is used to control the serial interface SIOS This register is used to set the SIO3 s serial clock operation mode and operation enable disable CSIMG is set with 1 bit or 8 bit memory manipulation instruction RESET input clears CSIM3 to Caution In the 3 wire serial mode set the port mode register PM5X as follows Besides that set all output latches to 0 When serial clock output Master transmit or master receive Set 50 SCK3 to the output mode 50 0 When serial clock input Slave transmit or slave receive Set P50 to the input mode 50 1 When transmit or transmit receive mode Set P51 SO3 to the output mode PM51 0 When receive mode Set P52 SI3 to the input mode 52 1 Figure 15 2 Serial Operation Mode Register 3 CSIM3 Format Address FF84H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 SIOS Operation Enable Disable Specification CSIE3 Shift Register Operation 0 Operation disabled 1 Operation enabled Transfer Operation Mode Flag MODE3 Operation Mode 0 Transmit or transmit receive mode 1 Receive only mode SCL31 SCL30 Clock Selection 0 0 External clock input 0 1 fx 22 1 0 fx 28 1 1 fx 24 Caution Bits to 6 must be set to 0 Remark fx Main system clock oscillation frequency Preliminary User s Manual U14581EJ3VOUMOO 203 CHAPTER 15 SERIAL INTERFACE SIO3
112. Counter Operation disabled Clear Port function Operation enabled Counter operation enabled Serial function port function SIO2 Operation Mode Setting Operation Mode Transfer Start Trigger SO2 P04 Pin Transmit receive mode Writing to SIO2 SO output Receive only mode Reading from SIO2 Port function Serial Transfer Operation Clock Selection Operation Clock Transfer Frequency Master Slave External clock input to SCK2 Slave mode fx 29 Master mode fx 210 Master mode fx 211 Master mode 194 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 14 SERIAL INTERFACE SIO2 Cautions 1 Bits 5 and 6 must be set to 0 2 Whilea serial transfer operation is enabled CSIE2 1 be sure to stop the serial transfer operation once before changing the values of bits other than CSIE2 to different data 3 Whenoperation is disabled CSIE2 0 during a serial transfer operation the operation will be sopped immediately Atthis time even if operation is enabled again CSIE2 1 after it was once stopped the operation will not start To resume operation set operation enable CSIE2 1 and then execute an access that will be the start trigger of each transfer operation mode 4 Changing CSIE2 and other bits at the same time is prohibited After clearing CSIE2 to 0 change the other bits Remark fx Main system clock oscillation frequency 2 Communication operations Data is transmitt
113. ENT COUNTERS 2 2 AND 3 Figure 8 4 Timer Clock Select Register 3 TCL3 Format Address FF75H After Reset OOH R W Symbol 7 6 5 4 3 2 1 0 TIO3 falling edge TIO3 rising edge fx 24 523 kHz fx 28 130 kHz fx 27 65 4 kHz fx 28 32 7 kHz fx 210 8 18 kHz fx 212 2 04 kHz Cautions 1 When rewriting TCL3 to other data stop the timer operation beforehand 2 Bits 3 to 7 must be set to 0 Remarks 1 fx Main system clock oscillation frequency 2 Figures in parentheses apply to operation with fx 8 38 MHz 2 8 bit timer mode control registers 2 3 TMC2 TMC3 TMC2 and TMC3 are registers which sets up the following five types 1 8 bit counters 2 and 3 TM2 and TM3 count operation control 2 8 0 counters 2 and 3 TM2 and operation mode selection 3 Timer output F F flip flop status setting 4 Active level selection in timer F F control or PWM free running mode 5 Timer output control TMC2 and TMC3 are set with a 1 bit or 8 bit memory manipulation instruction RESET input clears these registers to Preliminary User s Manual U14581EJ3VOUMOO 125 CHAPTER 8 8 BIT COUNTERS 2 2 AND 3 Figure 8 5 8 Bit Timer Mode Control Registers 2 and 3 TMC2 and TMC3 Format Address FF77H TMC2 FF78H TMC3 After Reset 00H R W Symbol Z 6 5 4 3 2 1 0 After clearing count
114. ER 14 SERIAL INTERFACE SIO2 3 192 Port mode register 0 PMO This register is used to specify the input output of port 0 in 1 bit units When using the PO3 SCK2 P04 SO2 and P05 SI2 pins in the 3 wire serial I O mode set to 05 as shown in Table 14 2 below Set the output latches of to 05 to 0 PMO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PMO to FFH Figure 14 5 Port Mode Register 0 PMO Format Address FF20H After Reset R W Symbol 7 6 5 4 3 2 1 0 Output mode output buffer on Input mode output buffer off Remark nz0to7 Table 14 2 Relation between Operation Modes and Settings of PM03 to PM05 Operation Mode PMO Settings Note 2 SIO2 Operation Serial Operation Mode Master Slave Note PM04 PM05 Disabled CSIE2 0 Enabled CSIE2 1 Receive only mode Master MODE2 0 Slave Transmit receive Master mode MODE2 1 Slave Notes 1 Master slave can be selected by setting bits 0 and 1 SCL20 and SCL21 of the serial operation mode register 2 CSIM2 2 0 Output mode 1 Input mode x don t care can be used as an ordinary port pin Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 14 SERIAL INTERFACE SIO2 14 4 Serial Interface Operations This section explains the two modes of the serial interface SIO2 14 4 1 Operation stop mode This mode is used when seri
115. Figure 13 2 Asynchronous Serial Interface Mode Register ASIM Format Address FF85H After Reset OOH R W Symbol 7 6 5 4 3 2 1 0 Operation Mode RxD P53 Pin Function TxD P54 Pin Function Operation stop Port function P53 Port function P54 UART mode receive only Serial function RxD Port function P54 UART mode transmit only Port function P53 Serial function TxD UART mode Serial function RxD Serial function TxD transmit and receive Parit Bit Specification 0 0 No parity 0 1 Zero parity always added during transmission No parity detection during reception parity errors do not occur 1 0 Odd parity 1 1 Even parity Character Length Specification 7 bits 8 bits Stop Bit Length Specification for Transmit Data Receive Completion Interrupt Control When Error Occurs Receive completion interrupt is issued when an error occurs Receive completion interrupt is not issued when an error occurs Cautions 1 Do switch the operation mode until after the current serial transmit receive operation has stopped 2 Bit 0 must be set to 0 172 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 13 SERIAL INTERFACE UART 2 Asynchronous serial interface status register ASIS When a receive error occurs during UART mode this register indicates the type of error ASIS is read with an 8 bit memory manipulation instruction RESET input clears ASIS to 00H Figure 13 3 Asynchronou
116. Instruction N Interrupt request hold instruction 2 Instruction M Instruction other than interrupt request hold instruction 3 The xxPR priority level values do not affect the operation of xxIF interrupt request Preliminary User s Manual U14581EJ3VOUMOO 261 MEMO 262 Preliminary User s Manual U14581EJ3V0UMOO 20 CHAPTER 20 STANDBY FUNCTION 1 Standby Function and Configuration 20 1 1 Standby function The standby function is designed to decrease power consumption of the system The following two modes are available 1 2 HALT mode HALT instruction execution sets the HALT mode The HALT mode is intended to stop the CPU operation clock The system clock oscillator continues oscillating In this mode current consumption is not decreased as much as in the STOP mode However the HALT mode is effective to restart operation immediately upon interrupt request and to carry out intermittent operations such as watch operation STOP mode STOP instruction execution sets the STOP mode In the STOP mode the main system clock oscillator stops stopping the whole system thereby considerably reducing the CPU current consumption Data memory low voltage hold down Voo 2 0 V is possible Thus the STOP mode is effective to hold data memory contents with ultra low current consumption Because this mode can be cleared upon interrupt request it enables intermittent operations to be carried out However because a wait time
117. Interface host machine It is compatible with the PCMCIA socket IE 70000 PC IF C This adapter is required when using PC AT or compatible as the IE 78K0 NS host Interface Adapter machine IE 70000 PCI IF This adapter is required when using on chip PCI bus as the IE 78K0 NS host machine Interface Adapter IE 780852 NS EM4 Probe board and I O board for emulating the uPD780852 Subseries IE 78K0 NS P04 Probe Board NP 80GC TQ Emulation probe for 80 pin plastic QFP GC 8BT type Remark NP 80GC TQ is a product of Naito Densei Machida Mfg Co Ltd For details contact Naito Densei Machida Mfg Co Ltd TEL 81 44 822 3813 Preliminary User s Manual U14581EJ3VOUMOO 301 APPENDIX A DEVELOPMENT TOOLS A 3 2 Software 1 2 5 78 0 This system simulator is used to perform debugging at C source level or assembler System Simulator level while simulating the operation of the target system on a host machine The 5 78 0 operates on Windows Use of the SM78KO0 allows the execution of application logical testing and performance testing on an independent basis from hardware development without having to use an in circuit emulator thereby providing higher development efficiency and software quality The 5 78 0 is used in combination with the optional device file DF780852 Part Number 5 78 0 Remark in the part number differs depending the host machine and OS used
118. Interrupt Request Generation Timing ADS1 rewrite ADS 1 rewrite ADIF is set but ANIm conversion start of ANIn conversion start of ANIm conversion has not ended A D conversion ADCR1 INTAD Remarks 1 n 0 1 4 2 0 1 4 9 Read of A D conversion result register ADCR1 When write operation is executed to A D converter mode register ADM1 and analog input channel specification register ADS1 the contents of ADCR1 are undefined Read the conversion result before write operation is executed to ADM1 ADS1 If a timing other than the above is used the correct conversion result may not be read Preliminary User s Manual U14581EJ3VOUMOO 167 CHAPTER 12 A D CONVERTER 12 6 Cautions on Emulation 1 2 168 D A converter mode register DAM1 To perform debugging with an in circuit emulator IE 78K0 NS the D A converter mode register DAM1 must be set DAM is a register used to set a probe board IE 780852 NS EM4 DAM is used when the power fail detection function is used Unless DAM1 is set the power fail detection function cannot be used DAM is a write only register Because the IE 780852 NS EM4 uses an external analog comparator and a D A converter to implement part of the power fail detection function the reference voltage must be controlled Therefore set bit 0 DACE of DAM1 to 1 when using the power fail detection function Figure 12 13 D A Converter Mode Register DAM1 Forma
119. J U LILI LIL LU LW UU 1 N N JM 1j m 00H 01H INTTMn TIOn 4 CRn transition Remark 2 3 8 4 2 External event counter operation The external event counter counts the number of external clock pulses to be input to the TlOn TMn is incremented each time the valid edge specified with the timer clock select register n TCLn is input Either the rising or falling edge can be selected When the TMn counted values match the values of 8 bit compare register n CRn TMn is cleared to 0 and the interrupt request signal INTTMn is generated Whenever the TMn value matches the value of CRn INTTMn is generated Remark 2 3 130 Preliminary User s Manual U14581EJ3VOUMOO CHAPTER 8 8 BIT TIMER EVENT COUNTERS 2 TM2 AND 3 Figure 8 8 External Event Counter Operation Timings with Rising Edge Specified c JF EE EFUFE LA B L a TMn count value XooooXooorXooozXooosXooo4XooosX 1 X0000X0001X0002X0003X CRn N Remark 2 3 8 4 3 Square wave output operation 8 bit resolution A square wave with any selected frequency is output at intervals of the value preset to 8 bit compare register n CRn pin output status is inverted at intervals of the count value preset to CRn by setting bit 0 TOEn of 8 bit timer mode control register n TMCn to 1 This enables a square wave with a
120. J3V0UMOO 103 CHAPTER 6 16 BIT TIMER 0 TMO 6 3 16 Bit Timer 0 TMO Configuration 16 bit timer 0 TMO consists of the following hardware 1 2 3 4 104 Table 6 2 16 Bit Timer 0 TMO Configuration Item Configuration Timer register 16 bits x 1 TMO Register Capture register 16 bits x 3 CROO to CRO2 Control register 16 bit timer mode control register TMCO Capture pulse control register Prescaler mode register PRMO Port mode register 4 4 16 bit timer register 0 TMO TMO is a 16 bit read only register that counts count pulses The counter is incremented in synchronization with the rising edge of an input clock If the count value is read during operation the count value at that point is read The value of the counter continues to be incremented even while the count value is being read The count value is reset to 0000H in the following cases 1 RESET input 2 Clear 02 Capture register 00 CROO The valid edge of the TIOO pin can be selected as the capture trigger Setting of the TIOO valid edge is performed with the prescaler mode register PRMO When the valid edge of the TIOO is detected an interrupt request INTTMOO is generated CR00 is set with a 16 bit memory manipulation instruction RESET input makes CROO to undefined Capture register 01 CRO1 The valid edge of the TIO1 can be selected as the capture trigger Setting of the 0
121. J3VOUMOO CHAPTER 16 LCD CONTROLLER DRIVER Timing strobes Data memory address Figure 16 10 4 Time Division LCD Panel Connection Example COM3 2 COM COMO t r Ww 0 m I I e 2 pu B Tp S2 1 A Mus Lc ru 8 S5 56 di 6 sie 5 ae f 2 59 x S10 LUC S11 Z 2 T FA5FH Em E l S15 C AL B S17 VA lt S18 T A 2 519 L uL LA Preliminary User s Manual U14581EJ3V0UMOO LCD panel 219 CHAPTER 16 LCD CONTROLLER DRIVER Figure 16 11 4 Time Division LCD Drive Waveform Examples 1 3 Bias Method TF Vico Vici COMO Vice Vico Vici 1 Vice Vico Vici COM2 Vice Vico Vict COM3 Vice Vico Vici Vice S8 1 3Vicp COMO to S8 0 1 3Vicp Vicp Vicb 1 3Vicp COM1 to S8 0 1 3Vicp Vic 220 Preliminary User s Manual U14581EJ3VOUMOO CHAPTER 16 LCD CONTROLLER DRIVER 16 9 Cautions on Emulation 1 LCD timer control register LCDTM To perform debugging with an in circuit emulator IE 78K0 NS the LCD timer control register LCDTM must be
122. MER L S Sa eni sus aa 137 WATCHDOG IIMER III ua nth sinister intr nna 143 OUTPUT CONTROLLER 1 1 4 149 A D CONVERTER fT 153 SERIAL INTERFACE UART u 169 SERIAL INTERFACE SIOJ2 187 SERIAL INTERFACE SIO3 201 LCD u uu uuu u u 207 SOUND 223 METER CONTROLLER DRIVER u u uu u uu u 231 INTERRUPT FUNCTIONS U 241 STANDBY FUNCTION U U u uuu u uu u 263 RESET FUNCTION 271 HPD 8F0852 u a E 275 INSTRUCTION SET cen innui wass neun nur daa aae pr Yam inan ades 281 DEVELOPMENT TOOLS IIIa asua nerui inan 297 EMBEDDED SOFTWARE renes ennemis 305 REGISTER INDEX u asua 307 REVISION 2 22 nena tnnc inam
123. Max 120 pin 2295780328 H Display capability and timer of the uPD780308 were enhanced Segment signal output 32 Max 120 pin 7 780318 23 Display capability and timer of the u PD780308 were enhanced Segment signal output 24 Max SIO of the uPD78064 was enhanced and ROM and RAM were expanded 100 pin LPD78064B EMI noise reduced version of the uPD78064 100 pin 078064 LPD78064Y Basic subseries for driving LCDs on chip UART Bus interface 1 00 LPD780948 On chip DCAN controller 80 uPD78008B 459 IEBus controller was added to the uPD78054 reduced version 80 pin uPD780701Y Z On chip DCAN IEBus controller 80pn HPD780833Y On chip J1850 CLASS2 controller 64 pin 780814 d puce Special in DCAN controller function Meter control 100 pin uPD780958 Industrial meter control 80 pin uPD780852 On chip automobile meter driving controller driver 80 pin E uPD780828B For automotive meter drive On chip DCAN controller 4 Remark 5 documents use the name fluorescent indicator panel FIP instead of vacuum fluorescent display VFD The functions of FIP and VFD are the same Preliminary User s Manual U14581EJ3VOUMOO 31 CHAPTER 1 OUTLINE The major functional differences among the subseries are shown below Subseries Name Control Inverter control Bus interface Meter control Dash board control ROM Capa
124. Mode Register Format nemen rennen 250 19 7 Program Status Word Format aru ttr metere teca sancti SURE 251 19 8 Non Maskable Interrupt Request Generation to Acknowledge Flowchart 253 19 9 Non Maskable Interrupt Request Acknowledge 253 19 10 Non Maskable Interrupt Request Acknowledge Operation ss 254 19 11 Interrupt Request Acknowledge Processing 256 19 12 Interrupt Request Acknowledge Timing Minimum m 257 19 13 Interrupt Request Acknowledge Timing Maximum 257 19 514 Multiple Interrupt Examples crore trente eoe ntc ere eaa e ees 259 19 15 Interrupt REQUEST OIG E 261 20 1 Oscillation Stabilization Time Select Register OSTS Format 264 20 2 HALT Mode Clear upon Interrupt Generation 2 266 20 3 HALT Mode Clear upon RESET Input ccsssssessessessssssessessessssessesseesssussessesssesssessesetsissesseeseeseeess 267 20 4 STOP Mode Clear upon Interrupt Generation U 269 20 5 STOP Mode Clear upon RESET Input occisi brutto terunt tete trek getto tti cues 270 21 1 Reset Function Block Diagram 148 4 nnne retener innen 271 21 2 Timing of
125. O2 Operation Enable Disable Specification Shift Register Operation Serial Counter Operation disabled Clear Port function Operation enabled Counter operation enabled Serial function port function 5 2 is high while serial transfer is stopped 5 2 is low while serial transfer is stopped SIO2 Operation Mode Setting Operation Mode Transfer Start Trigger SO2 P04 Pin Transmit receive mode Writing to SIO2 SO output Receive only mode Reading from SIO2 Port function Serial Transfer Operation Clock Selection Operation Clock Transfer Frequency Master Slave External clock input to SCK2 Slave mode fx 29 Master mode fx 210 Master mode fx 211 Master mode Preliminary User s Manual U14581EJ3VOUMOO 189 CHAPTER 14 SERIAL INTERFACE SIO2 Cautions 1 Bits 5 and 6 must be set to 0 2 Whilea serial transfer operation is enabled CSIE2 1 be sure to stop the serial transfer operation once before changing the values of bits other than CSIE2 to different data 3 When operation is disabled CSIE2 0 during a serial transfer operation the operation will be stopped immediately At this time even if operation is enabled again CSIE2 1 after it was once stopped the operation will not start To resume operation set operation enable CSIE2 1 and then execute an access that will be the start trigger of each transfer operation mode 4 Changing CSIE2 and other
126. OM 32 768 x 8 bits 0000H Y 52 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 3 CPU ARCHITECTURE FE20H FE1FH FBOOH FAFFH FA6DH FA6CH FA59H FA58H F800H F7FFH F600H F5FFH A000H 9FFFH 0000H Figure 3 5 Data Memory Addressing uPD780852 A Special function registers SFRs SFR addressing 256 x 8 bits General registers 32 x 8 bits Register addressing Internal high speed RAM 1 024 x 8 bits Short direct addressing Reserved LCD display RAM 20 x 4 bits Reserved Direct addressing Register indirect addressing Based addressing Based indexed addressing Internal expansion RAM 512 x 8 bits Reserved Internal ROM 40 960 x 8 bits Y Preliminary User s Manual U14581EJ3VOUM00 53 CHAPTER 3 CPU ARCHITECTURE 54 FE20H FE1FH FBOOH FAFFH FA6DH FA6CH FAS9H 58 F800H F7FFH F600H F5FFH A000H 9FFFH 0000H Figure 3 6 Data Memory Addressing uPD78F0852 Special function registers SFRs SFR addressing 256 x 8 bits n General registers 32 x 8 bits Register addressing Y Internal high speed RAM 1 024 x 8 bits Short direct addressing Reserved LCD display RAM 20 x 4 bits Reserved Direct addressing Register indirect addressing Based addressing Based indexed addressing Internal expansion RAM 512 x 8 bits Reser
127. Operands Operation AX CY AX word AX CY AX word AX word AX Ax X AX Quotient C Remainder AX C rer i saddr saddr 1 rer 1 saddr saddr 1 Increment decrement rp lt rp 1 rp lt 1 A lt Am 1 lt Am x 1 time CY Ao lt Az Am 1 lt Am x 1 time CY lt Ao CY Am 1 lt Am x 1 time CY lt Az Ao CY Am 1 Am x 1 time lt HL s o HL 7 4 lt HL s o lt HL z 4 As o lt HL z 4 HL s o lt HL z 4 lt HL s o NI SN I INI NN I Y RR mM RI DM A Decimal Adjust Accumulator after Addition Decimal Adjust Accumulator after Subtract CY lt saddr bit CY lt sfr bit CY c A bit CY lt PSW bit CY c HL bit saddr bit CY sfr bit CY A bit CY PSW bit CY HL bit CY CY saddr bit CY sfr bit CY A bit CY PSW bit CY HL bit saddr bit CY sfr bit CY A bit CY PSW bit CY HL bit CY N O N OO wm wo ow Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM area is accessed Remark One instruction clock cycle is one cycle of the CPU clock fceu selected by the pro
128. PEU 512 x 8 bits F600H Program area F5FFH Reserved 0080H A000H 007FH SERER CALLT table area Program memory Flash memory 40 960 x 8 bits Vector table area 0000H 0000H Preliminary User s Manual U14581EJ3VOUM00 49 CHAPTER 3 CPU ARCHITECTURE 3 1 1 Internal program memory space The internal program memory space contains the program and table data Normally it is addressed with the program counter PC The uPD780852 Subseries incorporate internal ROM or flash memory as listed below Table 3 1 Internal Memory Capacity Part Number uPD780851 A Internal ROM uPD780852 A Mask ROM Capacity 32 768 x 8 bits 0000H to 7FFFH 40 960 x 8 bits 0000H to 9FFFH uPD78F0852 Flash Memory 40 960 x 8 bits 0000H to 9FFFH The following three areas are allocated to the program memory space 1 Vector table area The 64 byte area 0000H to 003FH is reserved as a vector table area This area stores program start addresses to which execution branches when the RESET signal is input or when an interrupt request is generated Of a 16 bit address the lower 8 bits are stored at an even address and the higher 8 bits are stored at an odd address Table 3 2 Vector Table Vector Table Address Interrupt Source RESET input INTWDT INTAD INTOVF INTTMOO INTTMO1 INTTMO2 INTPO INTP1 INTP2 INTCSI3 INTSER INTSR INTST INTTM1 INTTM2 INTTM3 INTCSI2 INTWTI INTWT
129. R 19 INTERRUPT FUNCTIONS 19 4 5 Interrupt request hold There are instructions where even if an interrupt request is issued for them while another instruction is executed request acknowledge is held pending until the end of execution of the next instruction These instructions interrupt request hold instructions are listed below MOV PSW byte MOV A PSW MOV PSW A MOV1 PSW bit CY MOV1 CY PSW bit AND1 CY PSW bit OR1 CY PSW bit e XOR1 CY PSW bit SET1 PSW bit CLR1 PSW bit RETB RETI PUSH PSW POP PSW BT PSW bit addr16 BF PSW bit addr16 BTCLR PSW bit addr16 El DI e Manipulate instructions for the IFOL IFOH IF1L 1F1H MKOL MKOH MK1L PROL PROH PR1L PR1H EGP and EGN registers Caution The BRK instruction is not one of the above listed interrupt request hold instruction However the software interrupt activated by executing the BRK instruction causes the IE flag to be cleared to 0 Therefore even if a maskable interrupt request is generated during execution of the BRK instruction the interrupt request is not acknowledged However a non maskable interrupt request is acknowledged The timing with which interrupt requests are held pending is shown in Figure 19 15 Figure 19 15 Interrupt Request Hold 2 Save PSW and PC jump Interrupt servicing CPU processing Instruction N Instruction M to interrupt servicing brogram xxlF Remarks 1
130. RD WR 4 2 2 Port 1 Output latch to P07 PM00 to 07 to P02 INTP2 P03 SCK2 functions Pull up resistor option register Port mode register Port 0 read signal Port 0 write signal Port 1 is a 5 bit input only port Alternate fu nctions include an A D converter analog input Figure 4 3 shows a block diagram of port 1 RD 78 Figure 4 3 P10 to P14 Block Diagram RD 1 Internal bus Port 1 read signal Preliminary User s Manual U14581EJ3V0UMOO P04 SO2 5 512 6 7 O ANIO to 4 ANIA CHAPTER 4 PORT FUNCTIONS 4 2 3 Port 2 Port 2 is an 8 bit output only port with output latch P20 to P27 pins go into a high impedance state when the ENn of port mode control register PMC is set to 0 and the port mode register 2 PM2 is set to 1 Alternate functions include meter control PWM output RESET input sets port 2 to high impedance state Figure 4 4 shows a block diagram of port 2 Figure 4 4 P20 to P27 Block Diagram RD HF L5 4 WRPonr Output latch P20 to P27 Internal bus P20 SM11 to P23 SM14 P24 SM21 to P27 SM24 Selector PM20 to PM27 D gt Alternate functions PM Port mode register RD Port 2 read signal WR Port 2 write signal Caution When PM2issetto 0 read operation is enabled When PM2is setto
131. Register LCDM Format 210 16 4 LCD Display Control Register LCDC 211 16 5 Relation between LCD Display Data Memory Contents and Segment Common Outputs 213 16 6 Gommon Signal uu bee ii em E EE E euet ee Te iva Eo Ua ERE ee ee teg 215 16 7 Common Signal and Segment Signal Voltages and Phases 215 16 8 Example of Connection of LCD Drive Power Supply seen 217 16 9 4 Time Division LCD Display Pattern and Electrode Connections 218 16 10 4 Time Division LCD Panel Connection Example u 219 16 11 4 Time Division LCD Drive Waveform Examples 1 3 Bias Method 220 16 12 LCD Timer Control Register LCDTM Format 221 Preliminary User s Manual U14581EJ3VOUMOO 21 LIST OF FIGURES 4 5 Figure No Title Page 17 1 Sound Generator Block Diagram sse nennen nennen nnne 223 17 2 Concept of Basic Cycle Output Signal 55 223 17 3 Sound Generator Control Register SGCR Format sse 226 17 4 Sound Generator Buzzer Control Register SGBR Format 227 17 5 Sound Generator Amplitude Register SGAM Format sse 228 17 6 Sound Generator Ou
132. Reset by RESET Input c ccccccscsscssscssesescscesesesesessesesssescasesessscasasesessscsesesssescaneuessseacasenees 272 21 3 Timing of Reset due to Watchdog Timer Overflow ssssssseeeeneeenenem eene 272 21 4 Timing of Reset in STOP Mode by RESET Input tees 272 22 Preliminary User s Manual U14581EJ3V0UMO0 LIST OF FIGURES 5 5 Figure No Title Page 22 1 Memory Size Switching Register IMS 276 22 2 Internal Expansion RAM Size Switching Register IXS 277 22 3 Transmission Method Selection Format u 278 22 4 Flashpro Connection Using 3 Wire Serial I O Method SIO3 280 22 5 Flashpro Ill Connection Using 3 Wire Serial I O Method SIO2 280 22 6 Flashpro Connection Using UART Method rennen 280 A 1 Development Tool Configuration srein ndana nes ipanaa ee 298 Preliminary User s Manual U14581EJ3V0UM00 23 LIST OF TABLES 1 2 Table No Title Page 2 1 Pin Input Output Circuit eene nennen nennen nnne tnter 43 3 1 Internal Memory Capaclly cheese cuite ten o tren te to tuner 50 3 2 Meer ce A POR 50 3 3 Special Function Register Listu L U eiie
133. SM34 and SM41 to 5 44 for meter control 2 2 5 P40 to P44 Port 4 These pins constitute a 5 bit input output port In addition they also function as timer input output pins The following operation modes can be specified in 1 bit units 1 Port mode In this mode P40 to P44 function as a 5 bit input output port They can be set in the input or output port in 1 bit units with the port mode register 4 4 2 Control mode In this mode P40 to P44 function as timer input output pins a TIO2 8 bit timer input output pins b TIOO to TIO2 These pins input a capture trigger signal to the 16 bit timer capture registers CROO to 02 Preliminary User s Manual U14581EJ3V0UMOO 39 CHAPTER 2 PIN FUNCTION 2 2 6 P50 to P54 Port 5 These pins constitute a 5 bit input output port In addition they also function as serial interface data input output and clock input output pins The following operation modes can be specified in 1 bit units 1 Port mode In this mode P50 to P54 function as a 5 bit input output port They can be set in the input or output port in 1 bit units with the port mode register 5 PM5 2 Control mode In this mode P50 to P54 function as serial interface data input output and clock input output pins 513 Serial interface serial data input pin b SO3 Serial interface serial data output pin c SCK3 Serial interface serial clock input output pin d RxD TxD Asynch
134. SMVss This is the ground pin of the meter controller driver 2 2 18 Positive power supply port pin 2 2 19 VRour This is a regulator output pin for the power supply to pins other than port pins Connect this pin to Vsso 1 via a 0 1 uF capacitorNete Do not use this pin to supply power to other ICs Note The size of the capacitor to be connected will be finalized after evaluation 2 2 20 Vsso Vssi The Vsso pin is the ground potential port pin The Vssi pin is the ground potential pin except for port block 2 2 24 VPP uPD78F0852 only A high voltage should be applied to this pin when the flash memory programming mode is set and when the program is written or verified Directly connect this pin to Vsso or Vss in the normal operation mode 2 2 22 Mask ROM version only The IC Internally Connected pin is provided to set the test mode to check the uPD780852 Subseries before shipment In the normal operation mode directly connect this pin to the Vsso or Vss pin with as short a wiring length as possible When a potential difference is generated between the pin and Vssoor Vssi pin because the wiring between those two pins is too long or external noise is input to the IC pin the user s program may not run normally e Directly connect the IC pin to the Vsso or Vssi pin Vsso or Vss1 e Keep short 42 Preliminary User s Manual U14581EJ3VOUMOO CHAPTER 2 PIN FUNCTION 2 3 Input Output Circu
135. Signals are fetched 5 4 2 Divider circuit The divider circuit divides the output of the main system clock oscillator fx to generate various clocks 96 Preliminary User s Manual U14581EJ3VOUMOO CHAPTER 5 CLOCK GENERATOR 5 5 Clock Generator Operations The clock generator generates the following clocks and controls the operation modes of the CPU such as the stand by mode Main system clock CPU clock fcPu Clock to peripheral hardware The operation of the clock generator is determined by the processor clock control register PCC and oscillator mode register OSCM as follows a The slowest mode 3 81 us at 8 38 MHz operation of the main system clock is selected when the RESET signal is generated PCC 04H While a low level is input to the RESET pin oscillation of the main system clock is stopped Five types of CPU clocks 0 24 us 0 48 us 0 95 us 1 91 us and 3 81 us at 8 38 MHz operation can be selected by the PCC setting Two standby modes STOP and HALT can be used The clock to the peripheral hardware is supplied by dividing the main system clock The other peripheral hardware is stopped when the main system clock is stopped except however the external clock input operation The uPD780851 A and uPD780852 A can be setto the reduced current consumption mode by setting OSCM only when operated at fx 4 to 4 19 MHz Setting 1 to bit 7 HALFOSC of OSCM will reduce th
136. TA2 DATA3 DATA4 DATAS DATA6 Data reception end l I SIRB2 SDVA SDOF SIRB2 read SRBS2 read INTCSI2 After DATA1 receive data is received completely it is transferred to SIRB2 SDVA is set since the receive data is transferred to SIRB2 SDVA is automatically cleared to 0 by SIRB2 read SRBS2 is read and the status is checked overflow error check Like 1 above DATA2 receive data is transferred to SIRB2 after it is received completely Even though DATAG receive data reception is complete it is held in SIO2 without being transferred to SIRB2 since the previous receive data DATA2 has not been read from SIRB2 SDOF is set to 1 since SDVA has been set to 1 and reception for SIO2 is complete DATAS receive data is discarded and DATA4 receive data reception ends Like 6 above DATA4 is not transferred to SIRB2 and is held S102 Like 3 above SDVA is automatically cleared to 0 by SIRB2 read SDOF is automatically cleared to 0 by SRBS2 read Like 1 above after DATAS receive data is received completely DATAS is transferred to SIRB2 Preliminary User s Manual U14581EJ3VOUMOO 199 200 CHAPTER 14 SERIAL INTERFACE SIO2 7 Operation in standby mode a Operation in HALT mode Even after a HALT instruction has been executed serial interface SIO2 continues to operate In the HALT mode the CPU cannot access the registers of serial interfac
137. TOP instruction s y gh Standby release 1 signal ee ares ans Oscillation stabilization Operation mode STOP mode wait status em mode Oscillation Oscillation stop Oscillation Clock gt Remark The broken line indicates the case when the interrupt request which has cleared the standby mode is acknowledged Preliminary User s Manual U14581EJ3VOUMOO 269 CHAPTER 20 STANDBY FUNCTION b Clear upon RESET input The STOP mode is cleared and after the lapse of oscillation stabilization time reset operation is carried out Figure 20 5 STOP Mode Clear upon RESET Input Wait STOP instruction 2 fx 15 6 ms X n OV RESET signal Reset Oscillation stabilization Operation mode STOP mode period wait status mode Oscillation Oscillation stop Oscillation Clock Remarks 1 fx Main system clock oscillation frequency 2 Figures in parentheses apply to operation with fx 8 38 MHz Table 20 4 Operation after STOP Mode Clear Clear Source Operation Maskable interrupt request Next address instruction execution Interrupt service execution Next address instruction execution Interrupt service execution STOP mode hold RESET input Reset processing x don t care 270 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 21 RESET FUNCTION 21 1 Reset Functions The following two operations are available to ge
138. To our customers Old Company Name in Catalogs and Other Documents On April 1 2010 NEC Electronics Corporation merged with Renesas Technology Corporation and Renesas Electronics Corporation took over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 1 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http www renesas com inquiry 24 NC S AS 10 11 12 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is g
139. U14581EJ3VOUMOO APPENDIX C REGISTER INDEX Processor clock control register PCC 92 Program status word PSW 55 251 Pull up resistor option register PUO 88 R Receive buffer register RXB 170 S Serial receive data buffer register SIRB2 188 Serial receive data buffer status register SRBS2 191 Serial I O shift register 2 SIO2 188 Serial I O shift register SIO3 202 Serial operation mode register 2 CSIM2 189 Serial operation mode register CSIM3 203 16 bit timer mode control register TMCO 105 16 bit timer register TMO 104 Sound generator amplitude register SGAM 227 Sound generator buzzer control register SGBR 227 Sound generator control register SGCR 225 T Timer clock select register 1 TCL1 115 Timer clock select register 2 TCL2 124 Timer clock select register 3 TCL3 124 Timer mode control register MCNTO 234 Transmit shift register TXS 170 W Watch timer mode control register WTM 139 Watchdog timer clock select register WDCS 145 Watchdog timer mode register WDTM 146 Preliminary User s Manual U14581EJ3VOUMOO 309 APPENDIX C REGISTER INDEX C 2 Register Index in Alphabetical Order with Respect to Register Symbol A ADCR1 ADM1 ADS1 ASIM ASIS B BRGC C CKS CROO CRO2 CR1 CR2 CRCO CSIM2 CSIM3 D DAM1 E EGN EGP IFOH
140. VOUMOO 255 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19 11 Interrupt Request Acknowledge Processing Algorithm Yes Interrupt request generation N Interrupt request held pending Yes High priority Yes Any high priority interrupt request among those simultaneously generated with xxPR 0 Yes Interrupt request held pending No Interrupt request held pending Vectored interrupt servicing xxlF Interrupt request flag xxMK Interrupt mask flag xxPR Priority specify flag No Low priority Any interrupt request among those simultaneously generated with xxPR 0 Yes Interrupt request held pending Any high priority interrup request among those simultaneously generated No Interrupt request held pending No lt gt Y Interrupt request held pending No Yes Interrupt request held pending Vectored interrupt servicing IE Flag that controls acknowledge of maskable interrupt request 1 Enable 0 Disable ISP Flag that indicates the priority level of the interrupt currently being serviced 0 High priority interrupt servicing 1 No interrupt request acknowledged or low priority interrupt servicing 256 Preliminary Users Manual U14581EJ3VOUMOO CHAPTER 19 INTERRUPT FUNCTIONS Figure 19 12 Interrupt Request Acknowledge Timing Minimum Time 6 clocks PSW and PC sa
141. Vbyte saddr byte saddr lt saddr Vbyte lt AVr lt A saddr lt AV saddr A laddr16 A lt AV addr16 HL lt AV HL byte A HL byte A HL B A AV HL A lt AV HL B A HL C A lt AV HL C A byte lt AN byte saddr byte lt saddr v byte A r lt lt saddr A saddr A laddr 6 Co m NIM GOO N N N N lt Av addr16 HL lt A HL Av HL byte A A HL byte A HL B lt AN HL B A HL C A AN HL C A byte A byte saddr byte saddr byte G SS NIN GCI N I NM NM N N hw O 2T c AJIAJ RLS O oo j O RI RI OD Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM area is accessed 3 Except r A Remark One instruction clock cycle is one cycle of the CPU clock fceu selected by the processor clock control register PCC Preliminary User s Manual U14581EJ3VOUMOO 287 CHAPTER 23 INSTRUCTION SET Instruction Group Mnemonic
142. W boards with semiconductor devices on it HANDLING OF UNUSED INPUT PINS FOR CMOS Note No connection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins itis possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to Voo or GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins must be judged device by device and related specifications governing the devices STATUS BEFORE INITIALIZATION OF MOS DEVICES Note Power on does not necessarily define initial status of MOS device Production process of MOS does not define the initial operation status of the device Immediately after the power source is turned ON the devices with reset function have not yet been initialized Hence power on does not guarantee out pin levels I O settings or contents of registers Device is not initialized until the reset signal is received Reset operation must be executed immediately after power on for devices having reset function IEBus is a trademark of NEC Corporation Windows and WindowsNT are either registered trademarks or trademarks of Microsoft Corporation in the United States and or other countries
143. Watch Timer Configuration J U u u u T 138 9 3 Watch Timer Control Register nana 139 9 4 Watch Timer Operations J u u u uuu u uu u 140 gaT Watch timer OPShatlon rtr teni 140 9 4 2 Interval ede Eee Ain 140 CHAPTER 10 WATCHDOG ennai 143 10 1 Watchdog Timer Functions U u uu uuu u u J T 143 10 2 Watchdog Timer Configuration l l u u J J J J 145 10 3 Watchdog Timer Control Registers 1 u u u u u u 145 10 4 Watchdog Timer eise eene u u u u u u 147 10 4 1 eee 147 109 4 2 Interval timer ODOFallOEi
144. _ O s 4 i i Active level Inactive level Active level ii CRn 0 Countclock FLT U L J U UU UL SUUL IUUU TTE JUUL Mn CENTRES OO unm CRn 00H LII RI UU TlOn 25 I 4 P 4 4 Inactive level Inactive level iii CRn FFH a lan Sg see ae a tl Mn IEFSTOOR UTR 2H TNI CRn L a ea s 1 1 1 1 1 1 TCEn A 27 1 1 1 Pas MEE 1 1 1 1 1 INTTMn __ 1 LU 1 1 1 1 1 1 TIOn E i L l EN m Inactive level Active level Active level Inactive level Inactive level Remark 2 3 Preliminary User s Manual U14581EJ3V0UMOO 133 CHAPTER 8 8 TIMER EVENT COUNTERS 2 2 AND 3 b Operation by change of CRn Figure 8 10 Operation Timing by Change of CRn i Change of CRn value to to M before overflow of TMn ai ainle 100100 Me INEST ET H 1 1 I INTTMn U i I I 1 1 4 CRn transition N M ii Change of CRn value to N to M after overflow of TMn cu TEE I l l l rEdu l TCEn H 1 I 1 I I I INTTMn i I CRn transition N iii Change of CRn value between two clocks 00H and 01H after over
145. able interrupt request until interrupt servicing is performed are listed in Table 19 3 below For the interrupt request acknowledge timing see the Figures 19 12 and 19 13 Table 19 3 Times from Generation of Maskable Interrupt Request until Servicing Meere einn When xxPRx 0 7 clocks 32 clocks When xxPRx 1 8 clocks 33 clocks Note lf an interrupt request is generated just before a divide instruction the wait time is maximized Remark 1 clock 1 fceu fcpu CPU clock If two or more maskable interrupt requests are generated simultaneously the request with a higher priority level specified in the priority specify flag is acknowledged first If two or more interrupts requests have the same priority level the request with the highest default priority is acknowledged first An interrupt request that is held pending is acknowledged when it becomes acknowledgeable Figure 19 11 shows the interrupt request acknowledge algorithm If a maskable interrupt request is acknowledged the contents are saved into the stacks in the order of program status word PSW then program counter PC the IE flag is reset to 0 and the contents of the priority specify flag corresponding to the acknowledged interrupt are transferred to the ISP flag Further the vector table data determined for each interrupt request is loaded into PC and branched Return from an interrupt is possible with the RETI instruction Preliminary User s Manual U14581EJ3
146. ag registers PROL PROH PR1L are disabled for acknowledgement Actual acknowledgement is controlled with the interrupt enable flag IE Carry flag CY This flag stores overflow and underflow upon add subtract instruction execution It stores the shift out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution Preliminary User s Manual U14581EJ3VOUM00 CHAPTER 3 CPU ARCHITECTURE 3 Stack pointer SP This is a 16 bit register to hold the start address of the memory stack area Only the internal high speed RAM area can be set as the stack area Figure 3 9 Stack Pointer Configuration SP 15 0 se sen Se sede ea sr The SP is decremented prior to write save to the stack memory and is incremented after read restore from the stack memory Each stack operation saves restores data as shown in Figures 3 10 and 3 11 Caution Since RESET input makes SP contents undefined be sure to initialize the SP before instruction execution Figure 3 10 Data to Be Saved to Stack Memory Interrupt and PUSH rp instruction CALL CALLF and BRK instruction CALLT instructions SP lt SP 3 SP SP 2 SP SP 2 SP 3 PC7 to PCO SP 2 Register pair low SP 2 PC7 to PCO SP 2 PC15 to PC8 SP 1 Register pair high SP 1 PC15 to PC8 SP 1 PSW SP gt SP gt SP gt F
147. al U14581EJ3VOUMOO CHAPTER 3 CPU ARCHITECTURE 3 4 9 Stack addressing Function The stack area is indirectly addressed with the stack pointer SP contents This addressing method is automatically employed when the PUSH POP subroutine call and RETURN instructions are executed or the register is saved reset upon generation of an interrupt request Stack addressing enables to address the internal high speed RAM area only Description example In the case of PUSH DE Operation code 10110101 Preliminary User s Manual U14581EJ3VOUM00 73 MEMO 74 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 4 PORT FUNCTIONS 4 1 Port Functions The uPD780852 Subseries are provided with five input port pins sixteen output port pins and thirty five input output port pins Figure 4 1 shows the port configuration Every port can be manipulated in 1 bit or 8 bit units controlled in various ways Moreover the port pins can also serve as pins of the internal hardware Figure 4 1 Port Types Port 4 Port 0 Port 5 Port 1 Port 6 Pong Port 2 Port 9 Port 3 Preliminary User s Manual U14581EJ3V0UMOO 75 CHAPTER 4 PORT FUNCTIONS Pin Name POO to P02 P03 P04 P05 P06 P07 Input Output Input Output Table 4 1 Port Functions Function Port 0 8 bit input output port Input output mode can be specified in 1 bit units On chip pull up resistor can be used by software Alternate Function INTPO
148. al bus Remark 1 4 0 1 18 2 Meter Controller Driver Configuration The meter controller driver consists of the following hardware Table 18 1 Meter Controller Driver Configuration Item Configuration Timer Free running up counter MCNT 1 channel Register Compare register MCMPn1 MCMPn0 8 channels Control registers Timer mode control register MCNTC Compare control register n Port mode control register PMC Pulse controller 1 bit addition circuit output controller Remark 1 4 1 Free running counter MCNT MONT is an 8 bit free running up counter and is a register that executes increment at the rising edge of input clock PWM pulse with a resolution of 8 bits can be output The duty factor can be set in a range of 0 to 100 The count value is cleared in the following cases RESET input Stop cou Cautions 1 nter PCE 0 MCNT executes counting operation from 01H to FFH repeatedly However it counts from 00H upon operation start 2 The PWM output is not output until the first overflow of MCNT 232 Preliminary User s Manual U14581EJ3VOUM00 CHAPTER 18 METER CONTROLLER DRIVER 2 3 4 5 Compare register n0 0 MCMPnoO is an 8 bit register that can rewrite compare values through specification of bit 4 TENn of the compare control register n MCMPCn RESET input clears this registe
149. al time N 1 xt N 00H to FFH Preliminary User s Manual U14581EJ3VOUMOO 117 CHAPTER 7 8 BIT TIMER 1 TM1 118 Figure 7 4 Interval Timer Operation Timings 2 3 b When CR1 00H Count clock M TM1 00H OOH 00H 1 I I I CR1 00H OOH i interval time I l Interval time c When CR1 FFH ERE 5 espe pe re ee Ct F FF I EE SS Interrupt received Interrupt received TM1 interval time 22 1 I Interval time Preliminary User s Manual U14581EJ3V0UM00 CHAPTER 7 8 BIT TIMER 1 TM1 Figure 7 4 Interval Timer Operation Timings 3 3 d Operated by CR1 transition M N counteock LT LJ U LI LIL LU LU uu CR1 N TCE1 INTTM1 1 TM1 interval time i 4 i CR1 transition 1 overflows since M e Operated by CR1 transition M N counteock LE LJ U LILI LU LU WU LU uu 1 1 N 1 CR1 N M TCE1 TM1 interval time i CR1 transition Preliminary User s Manual U14581EJ3V0UMOO 119 CHAPTER 7 8 BIT TIMER 1 TM1 7 5 8 Bit Timer 1 TM1 Cautions 1 Timer start errors An error with a maximum of one clock may occur concerning the time required for a ma
150. al transfers are not performed to reduce power consumption In addition in this mode the PO3 SCK2 04 502 and P05 SI2 pins be used as normal I O port pins 1 Register setting The operation stop mode is set with the serial operation mode register 2 CSIM2 CSIM2 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears 51 2 to 00H Address FF98H After Reset 00H R W Symbol T 6 5 4 3 2 1 0 s SIO2 Operation Enable Disable Specification IE2 Shift Register Operation Serial Counter 0 Operation disabled Clear Port function 1 Operation enabled Counter operation enabled Serial function port function Preliminary User s Manual U14581EJ3V0UMOO 193 CHAPTER 14 SERIAL INTERFACE SIO2 14 4 2 3 wire serial I O mode The 3 wire serial mode is useful when connecting to devices such as peripheral I Os and display controllers which incorporate a clocked serial interface This mode executes data transfer via three lines a serial clock line SCK2 a serial output line SO2 and a serial input line SI2 1 Register settings The 3 wire serial mode is set with the serial operation mode register 2 CSIM2 CSIM2 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears CSIM2 to 00H Address FF98H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 SIO2 Operation Enable Disable Specification Shift Register Operation Serial
151. and output pins the output latch contents for pins specified as input are undefined even for bits other than the manipulated bit Preliminary User s Manual U14581EJ3V0UMOO 89 MEMO 90 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 5 CLOCK GENERATOR 5 1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware Main system clock oscillator This circuit oscillates at frequencies of 4 00 to 8 38 MHz Oscillation can be stopped by executing the STOP instruction Figure 5 1 shows clock generator block diagram Figure 5 1 Clock Generator Block Diagram Prescaler Clock to gt peripheral X10 Main system hardware clock Prescaler X2 oscillator fx Standby CPU clock controller Selector STOP NENNEN Processor clock control register PCC Oscillator mode register OSCM Internal bus 5 2 Clock Generator Configuration The clock generator consists of the following hardware Table 5 1 Clock Generator Configuration Control register Processor clock control register PCC Oscillator mode register OSCM Note Oscillator Main system clock oscillator Note PD780851 A 780852 A only Preliminary User s Manual U14581EJ3VOUMOO 91 CHAPTER 5 CLOCK GENERATOR 5 3 Clock Generator Control Registers The following two types of registers are used to control the clock gen
152. and priority specify flag WDTPR are validated and the maskable interrupt request INTWDT can be generated Among maskable interrupts the INTWDT default has the highest priority The interval timer continues operating in the HALT mode but it stops in STOP mode Thus set bit 7 RUN of WDTM to 1 before the STOP mode is set clear the interval timer and then execute the STOP instruction Cautions 1 Once bit 4 WDTM4 of WDTM is set to 1 with the watchdog timer mode selected the interval timer mode is not set unless RESET input is applied 2 The interval time just after setting with WDTM may be shorter than the set time by a maximum of 28 fx sec Table 10 5 Interval Timer Interval Time WDCSO Interval Time fx 212 489 us fx 213 978 us 214 1 96 ms 215 3 91 ms fx 216 7 82 ms fx 217 15 6 ms fx 218 31 3 ms fx 220 125 ms Remarks 1 fx Main system clock oscillation frequency 2 Figures in parentheses apply to operation with fx 8 38 MHz 148 Preliminary User s Manual U14581EJ3V0UM00 CHAPTER 11 CLOCK OUTPUT CONTROLLER 11 1 Clock Output Controller Functions The clock output controller is intended for carrier output during remote controlled transmission and clock output for supply to peripheral 1515 The clock selected with the clock output selection register CKS is output from the PCL TPO P60 pin Figure 11 1 shows the clock output controller block diagram
153. ate data is to 1FH 1 Preliminary Users Manual U14581EJ3VOUMOO 69 CHAPTER 3 CPU ARCHITECTURE 3 4 5 Special function register SFR addressing Function The memory mapped special function register SFR is addressed with 8 bit immediate data in an instruction word This addressing is applied to the 240 byte spaces FFOOH to FFCFH and FFEOH to FFFFH However the SFR mapped at to FF1FH can be accessed with short direct addressing Operand format Identifier Description sfr Special function register name sfrp 16 bit manipulatable special function register name even address only Description example MOV A when selecting PMO FF20H as sfr Operation code 1111011 0 OP code 00100000 20H sfr offset Operation OP code sfr offset Effective address 70 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 3 CPU ARCHITECTURE 3 4 6 Register indirect addressing Function This addressing is to address a memory area to be manipulated by using as an operand address the contents of a register pair specified by the register bank select flags RBSO and RBS1 and the register pair specification code in the operation code This addressing can be carried out for all the memory spaces Operand format e pen Description example MOV A DE when selecting DE as register pair Operation code 10000101 Operation The memory address specified with the
154. ation Use DOS prompt in Windows Part number 78 0 Remark and AAA in the part number differ depending on the host machine and OS used uSxxxxMX78K0 AAA Product Outline Evaluation object Use for trial product Object for mass produced product Use for mass produced product Source program Can be purchased only when object for mass produced product is purchased Host Machine Supply Medium Notes 1 2 5 5 inch 2HD FD PC AT and compatibles Windows Japanese version Notes 1 2 3 5 2HC FD PC 9800 Series Windows Japanese version Windows English version Notes 1 2 HP9000 Series 700 HP UX Rel 9 05 DAT DDS SPARCstation SunOS Rel 4 1 4 3 5 inch 2HC FD Solaris Rel 2 5 1 1 4 inch CGMT NEWS RISC NEWS OS Rel 6 1 3 5 inch 2HC FD Notes 1 DOS is also supported 2 WindowsNT is not supported 306 Preliminary User s Manual U14581EJ3VOUMOO APPENDIX C REGISTER INDEX C 1 Register Index in Alphabetical Order with Respect to Register Name A A D conversion result register ADCR1 155 A D converter mode register ADM1 157 Analog input channel specification register ADS1 158 Asynchronous serial interface mode register ASIM 170 Asynchronous serial interface status register ASIS 173 B Baud rate generator control register BRGC 173 C Capture pulse control register CR
155. bits at the same time is prohibited After clearing CSIE2 to 0 change the other bits Remark fx Main system clock oscillation frequency The following shows the relationships between the CLPO and CLPH settings and the serial transfer clock data output and input data capture timing Figure 14 3 Serial Transfer Operation Timing According to CLPO and CLPH Settings Serial Transfer Operation Clock Selection Remarks 1 SCK2 Serial transfer clock 2 502 Data output timing 3 SI2 Input data capture timing 190 Preliminary User s Manual U14581EJ3VOUMOO CHAPTER 14 SERIAL INTERFACE SIO2 2 Serial receive data buffer status register SRBS2 This register is used to indicate the status of serial receive data buffer register SIRB2 SRBS2 is set with an 8 bit memory manipulation instruction RESET input clears SRBS2 to OOH Figure 14 4 Serial Receive Data Buffer Status Register SRBS2 Format Address FF9AH After Reset OOH R Symbol 7 6 5 4 3 2 1 0 All data SIRB2 has been read This bit is cleared to 0 when SIRB2 has been read Data in SIRB2 has not been read This bit is set to 1 when all receive data has been transferred from SIO2 to SIRB2 SDOF Overflow Check When Serial Data Is Transferred No overflow error data SIRB2 has been read This bit is cleared to 0 when SIRB2 has been read Overflow error occurs This bit is set to 1 if receive data is set in SIR
156. but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers offic
157. cessor clock control register PCC 288 Preliminary User s Manual U14581EJ3VOUMOO CHAPTER 23 INSTRUCTION SET Instruction Group Mnemonic Operands CY saddr bit Operation CY lt CY saddr bit CY sfr bit CY lt CY stfr bit CY A bit CY CY A bit CY PSW bit CY CYAPSW bit CY HL bit CY CY HL bit CY saddr bit CY lt CY V saddr bit CY sfr bit CY lt CY V sfr bit CY A bit CY CYVA bit CY PSW bit CY CYVPSW bit CY HL bit CY V HL bit CY saddr bit CY lt CY Y sadadr bit CY sfr bit CY lt CY str bit CY A bit CY CY Y A bit CY PSW bit CY CY v PSW bit CY HL bit CY lt CY v HL bit saddr bit saddr bit 1 sfr bit sfr bit 1 A bit A bit 1 PSW bit PSW bit 1 HL bit HL bit lt 1 saddr bit saddr bit 0 sfr bit sfr bit 0 A bit A bit 0 PSW bit PSW bit 0 HL bit NI N N I ASI NI SITIO NN N CGO I NN N GD G HL bit 0 CY 1 CY 0 CY CY Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM area is accessed Remark One instructio
158. chronous Serial Interface Receive Completion Interrupt 184 13 9 Receive Error Timing EIER 185 14 1 Serial Interface SIO2 Block Diagram 187 14 2 Serial Operation Mode Register 2 CSIM2 Formatl rennen 189 14 3 Serial Transfer Operation Timing According to CLPO and CLPH Settings 190 14 4 Serial Receive Data Buffer Status Register SRBS2 Format 191 14 5 Port Mode Register 0 PMO 08040 nnne nnne 192 14 6 Operation Timing When CLPH Is Set to 0 Serial output data 55H serial input data 197 14 7 Operation Timing When CLPH Is Set to 1 Serial output data 55H serial input data 198 14 8 um ua ut 199 15 1 Serial Interface 5103 Block Diagram a a aassasssssssssss 201 15 2 Serial Operation Mode Register 3 CSIM3 Format 203 15 3 3 Wire Serial Mode Timing y su na e ies ied Fe tata et ci nid 206 16 1 LCD Controller Driver Block Diagram 208 16 2 Clock Selector Block Diagratm coiere cnr ure raura tiene ee i 209 16 3 LCD Display Mode
159. cify flag register OL 248 Priority specify flag register 1L 248 Prescaler mode register 107 250 Program status word 55 251 Pull up resistor option register 88 Receive buffer register 170 Preliminary User s Manual U14581EJ3V0UMOO 311 APPENDIX C REGISTER INDEX S SGAM Sound generator amplitude register 227 SGBR Sound generator buzzer control register 227 SGCR Sound generator control register 225 SIO2 Serial I O shift register 2 188 5103 Serial shift register 202 SIRB2 Serial receive data buffer register 188 SRBS2 Serial receive data buffer status register 191 T TCL1 Timer clock select register 1 115 TCL2 Timer clock select register 2 124 TCL3 Timer clock select register 3 124 TMO 16 bit timer register 104 TM1 8 bit counter 1 114 TM2 8 bit counter 2 123 8 bit counter 123 TMCO 16 bit timer mode control register 105 TMC1 8 bit timer mode control register 1 116 TMC2 8 bit timer mode control register 2 125 TMC3 8 bit timer mode control register 3 125 TXS Transmit shift register 170 W WDCS Watchdog timer clock select register 145 WDTM Watchdog timer mode register 146 WTM Watch timer mode control register 139 312 Preliminary User s Manual U14581EJ3VOUMOO APPENDIX D REVISION HISTORY The following table shows the revision history of this man
160. city uPD78075B 32 K to 40 K uPD78078 48 K to 60 K uPD78070A 0780058 24 K to 60 K uPD78058F 48 K to 60 K uPD78054 16 K to 60 K uPD780065 40 K to 48K uPD780078 48 K to 60 K 10 Bit A D Serial Interface 3 ch UART 1 ch 3 ch time division UART 1ch 3 ch UART 1 ch 4 ch UART 1 ch uPD780034A 8 K to 32 K uPD78014H 3 ch UART 2 ch uPD78018F 8K to 60 K uPD78083 uPD780988 16 K to 60 K uPD780208 32 K to 60 K uPD780232 16 K to 24 K uPD78044H 32 K to 48 K uPD78044F 16 K to 40 K uPD780338 48 K to 60 K uPD780328 uPD780318 3 ch UART 1 ch External Expansion Available 1 ch UART 1 ch 3 ch UART 2 ch 2 ch UART 1 ch uPD780308 48 K to 60 K uPD78064B 32 K uPD78064 16 K to 32K uPD780948 60 K uPD78098B 40 K to 60 K uPD780814 32 K to 60 K 3 ch time division UART 1 ch 2 ch UART 1 ch 3 ch UART 1 ch Available Available 2 ch UART 1 ch uPD780958 48 Kto60 K 4ch 2 ch _ 1ch 2ch UART 1ch 69 22V uPD780852 32 K to 40 K uPD780828B 32 K to 60 K 3 ch UART 1 ch Note 16 bit timer 2 channels 10 bit timer 1 channel 32 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 1 OUTLINE 1 7 Block Diagram 00 40 to
161. ct the operating clock for serial transfer by using SCL21 and SCL20 Transfer is completed and a transmit completion interrupt INTCSI2 occurs when all the 8 bits of the serial data have been completely transferred b Slave mode with external clock Serial interface SIO2 operates in the slave mode with an external clock if bits 1 and 0 SCL21 and SCL20 of the serial operation mode register 2 CSIM2 are set to 0 0 In the slave mode the SCK2 pin operates as an external serial clock input pin Serial data is transferred to SIO2 in synchronization with the externally input serial clock After the serial data has been received by 5102 it is transferred to the serial receive data buffer register SIRB2 At the same time the SDVA flag is set to 1 and a transmit completion interrupt INTCSI2 occurs Caution To prevent the occurrence of an overflow error read the value of SIRB2 before the next serial data is transferred to SIO2 Table 14 3 below shows the status of the PO3 SCK2 04 502 and P05 SI2 pins in each operation mode Table 14 3 Operation Mode and Pin Status Operation Mode Pin SIO2 Operation Serial Operation Mode Master Slave Note P03 SCK2 P04 SO2 P05 SI2 Disabled CSIE2 0 Port function Port function Port function Enabled CSIE2 1 Receive only mode Serial function Port function Hi Z MODE2 1 Hi Z Port function Hi Z Transmit receive Serial function Serial function Hi Z mode MODE2 0
162. d Both rising and falling edges TIOO Valid Edge Selection Falling edge Rising edge Interrupt disabled Both rising and falling edges Caution Set the valid edge of the TIOO P40 to TIO2 P42 pins after setting bit 2 02 of 16 bit timer mode control register 0 TMCO to 0 to stop the timer operation 250 Preliminary Users Manual U14581EJ3VOUMOO CHAPTER 19 INTERRUPT FUNCTIONS 6 Program status word PSW The program status word is a register to hold the instruction execution result and the current status for an interrupt request The IE flag to set maskable interrupt enable disable and the ISP flag to control multiple interrupt processing are mapped Besides 8 bit read write this register can carry out operations with a bit manipulation instruction and dedicated instructions El and DI When a vectored interrupt request is acknowledged if the BRK instruction is executed the contents of PSW are automatically saved into a stack and the IE flag is reset to O If a maskable interrupt request is acknowledged the contents of the priority specify flag of the acknowledged interrupt are transferred to the ISP flag The PSW contents are also saved into the stack with the PUSH PSW instruction They are reset from the stack with the RETI RETB and POP PSW instructions RESET input sets PSW to 02H Figure 19 7 Program Status Word Format After Reset 7 6 5 4 3 2 1 0 psu ie esi ac reso o ee ov 02H
163. d Cleared to 0 Set to 1 Set cleared according to the result Previously saved value is restored Preliminary User s Manual U14581EJ3V0UMOO 283 CHAPTER 23 INSTRUCTION SET 23 2 Operation List Instruction Group Mnemonic Operands byte Operation r lt byte saddr byte saddr lt byte sfr byte G O Pp sfr byte A r _ Aer lt saddr lt saddr saddr saddr A A sfr A lt sfr sfr A sfr lt A A laddr16 lt addr16 laddr16 A addr16 A PSW byte PSW lt byte A PSW A PSW PSW A N N GO CGO N N N N PSW lt A A DE A DE 8 bit data DE A DE A transfer A HL A lt HL HL A HL A A HL byte A lt HL byte HL byte A HL byte A A HL B A HL B HL B A HL B A A HL C A HL C HL A O aI In m C A Aor BLM O oj AJAJAJA A A c sfr laddr16 addr16 DE DE HL HL HL byte HL byte HL B HL B
164. d generator Sound generator control register SGCR Sound generator buzzer control register SGBR Sound generator amplitude register SGAM 1 Sound generator control register SGCR SGCR is a register which sets up the following three types Controls sound generator output Selects sound generator input frequency fsc Selects 5 bit counter input frequency fse2 SGCR is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears SGCR to 00H Figure 17 3 shows the SGCR format Preliminary User s Manual U14581EJ3V0UM00 225 CHAPTER 17 SOUND GENERATOR 226 Figure 17 3 Sound Generator Control Register SGCR Format Address FF94H After Reset OOH R W Symbol 7 6 5 4 3 2 1 0 NN Timer operation stopped SGO for low level output Sound generator operation SGO for output 5 Bit Counter Input Frequency fse2 Selection fsc2 fsa1 25 fsa2 fsa1 26 fsa1 27 fsa1 28 Sound Generator Input Frequency fse Selection fse1 fx 2 fse1 fx Cautions 1 Before setting the TCE bit set all the other bits 2 When rewriting SGCR to other data stop the timer operation TCE 0 beforehand 3 Bits 4 to 6 must be set to 0 4 Bit 3 must be set to 1 The maximum and minimum values of the buzzer output frequency are as follows Table 17 2 Maximum Value and Minimum Value of Buzzer Output Frequency Maximum and Minimum Values of Buzzer Output
165. d version of the uPD78078 100 pin Timer was added to the wPD78054 and the external interface function was enhanced 100 pin ROM less versions of the uPD78078 100 pin Serial I O of the 78078 was enhanced and only selected functions are provided 80 pin Serial I O of the uPD78054 was enhanced 80 pin EMI noise reduced version of the uPD78054 80 pin uPD78054 UART and D A converter were added to the 78018 and I O was enhanced 80 pin RAM was expanded the 0780024 64 pin 780078 E 780078 Timer was added to the 780034 and serial I O was enhanced 64 pin LPD780034A uPD780034AY A D converter of the LPD780024A was enhanced 64 pin Serial I O of the uPD78018F was enhanced 64 pin EMI noise reduced version of the uPD78018F 64 pin Basic subseries for control 42 44 pin On chip UART capable of operating at a low voltage 1 8 V Inverter control 64 pin UPD780988 On chip inverter control circuit and UART EMI noise reduced version VFD drive 100 pin and VFD C D of the uPD78044F were enhanced Display output total 53 80 pin For panel control On chip VFD C D Display output total 53 80 pin N ch open drain input output was added to the uPD78044F Display output total 34 80 pin Basic subseries for driving VFD Display output total 34 z LGB Brive ius 120 pin 780338 i Display capability and timer of the uPD780308 were enhanced Segment signal output 40
166. dex in Alphabetical Order with Respect to Register Name 307 C 2 Register Index in Alphabetical Order with Respect to Register Symbol 310 APPENDIX D REVISION HISTORY J LIU cere cac nna vana Co 313 18 Preliminary User s Manual U14581EJ3V0UMOO LIST OF FIGURES 1 5 Figure No Title Page 2 1 rr 44 3 1 Memory Map 2 0780851 2 a sanu Rick en Eu u Sus 47 3 2 Memory 780852 48 3 3 Memory Map uPD78F0852 J I enit dee nde ban 49 3 4 Data Memory Addressing 0 780851 52 3 5 Data Memory Addressing 780852 eene menn 53 3 6 Data Memory Addressing 78 0852 nnne nnn 54 3 7 Program Counter Configuration 2 cric Du S 55 3 8 Program Status Word Configuration senses 55 3 9 Stack Pointer Gornfig ration oerte au IS tante gratie stipe 57 3 10 Data to Be Saved to Stack entere 57 3 11 Data to Be Reset from Stack Memory 57 3 12 Genera
167. e 2 Watchdog timer can perform either the watchdog timer function or the interval timer function as 102 selected Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 6 16 BIT TIMER 0 TMO 6 2 16 Bit Timer 0 TMO Functions The 16 bit timer O TMO has the following functions Pulse width measurement Divided output of input pulse Figure 6 1 shows 16 bit timer 0 TMO block diagram Figure 6 1 Timer 0 TMO Block Diagram Internal bus Prescaler mode register PRMO 521 520 ES11 ES10 501 500 fx 8 Capture pulse control register CRCO 16 bit timer mode control register TMCO fx 16 B og ge fx 32 m 16 bit timer register TMO INTOVF 1 64 ES21 ES20 y Noise rejection Prescaler Edge hi 02 42 circuit 1 1 2 1 4 1 8 16 bit capture register CRO2 ES11 ES10 02 TIO1 P41 Noise rejection Edge 16 bit capture register CRO1 circuit detector 501 500 gt 01 Y Noise rejection Edge hi 00 40 16 bit capture re INTTMOO L TPOE M Internal bus 1 Pulse width measurement TMO can measure the pulse width of an externally input signal 2 Divided output of input pulse The frequency of an input signal can be divided and the divided signal can be output Preliminary User s Manual U14581E
168. e DF780852 Caution when using in PC environment This C compiler package is a DOS based application however using Project Manager which is included in the assembler package enables use of this compiler in a Windows environment Part Number uSxxxxCC78K0 DF780852 Device File This file contains information peculiar to the device This file is used in combination with each optional tools RA78K 0 CC78K 0 SM78KO and ID78KO0 Supported OS and host machine depend on each tool Part Number uSxxxxDF780852 CC78K 0 L C Library Source File This is a source of functions configuring the object library included in the C compiler package CC78K 0 It is required to make the object library included in the CC78K 0 conform to the customer s specifications Operation environment does not depend on OS because the source file is used Part Number uS xxxxCC78K0 L Note The DF780852 is used in common with the RA78K 0 CC78K 0 SM78KO0 and ID78KO Remark in the part number differs depending on the host machine and OS used Preliminary User s Manual U14581EJ3VOUMOO 299 APPENDIX A DEVELOPMENT TOOLS Lu SxxxxRA78K0 USxxxxCC78K0O uSxxxxDF780852 USxxxxCC78KO0 L Host Machine PC 9800 Series Windows Japanese version Supply Medium 3 5 inch 2HD FD IBM PC AT and compatibles Windows Japanese version Windows English version 3 5 inch 2HC FD
169. e 278 22 4 Main Functions of Flash Memory mene 279 23 1 Operand Identifiers and Description Formats a 282 Preliminary User s Manual U14581EJ3VO0UMOO 25 MEMO 26 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 1 OUTLINE 1 1 Features Internal memory Item Program Memory Data Memory Part Number ROM Flash Memory Internal High Speed RAM Internal Expansion RAM LCD Display RAM uPD780851 A 32 Kbytes 1 024 bytes 512 bytes 20 x 4 bits uPD780852 A 40 Kbytes uPD78F0852 40 Kbytes Instruction execution time can be changed from high speed 0 24 us to low speed 3 81 us Instruction set suited to system control Bit manipulation possible in all address spaces Multiply and divide instructions Fifty six I O ports including pins that have an alternate function as segment signal output 8 bit resolution A D converter 5 channels Sound generator 1 channel Meter controller driver PWM output 8 bit resolution 16 Can set pulse width with a precision of 8 1 bits with 1 bit addition function LCD controller driver Segment signal output 20 max Common signal output 4 max Bias 1 3 bias e Power supply voltage Vico 3 0 V to Serial interface 3 channels 3 wire serial mode 2 channels UART mode 1 channel Timer Six channels 16 bit timer 1 channel 8 bit timer 1 channel 8 bit timer
170. e HALT mode can be cleared with the following three types of sources a Clear upon unmasked interrupt request An unmasked interrupt request is used to clear the HALT mode If interrupt acknowledge is enabled vectored interrupt service is carried out If interrupt acknowledge is disabled the next address instruction is executed Figure 20 2 HALT Mode Clear upon Interrupt Generation HALT instruction Wait Standby release J MN RR Operation mode HALT mode Wait 4 Operation mode Oscillation Clock Remarks 1 broken line indicates the case when the interrupt request which has cleared the standby mode is acknowledged 2 Wait times are as follows When vectored interrupt service is carried out 8 to 9 clocks When vectored interrupt service is not carried out 2 to 3 clocks b Clear upon non maskable interrupt request The HALT mode is cleared and vectored interrupt service is carried out whether interrupt acknowledge is enabled or disabled 266 Preliminary User s Manual U14581EJ3VOUMOO CHAPTER 20 STANDBY FUNCTION c Clear upon RESET input As in the case with normal reset operation a program is executed after branch to the reset vector address Figure 20 3 HALT Mode Clear upon RESET Input Wait HALT instruction 27 fx 15 6 ms s o n p RESET signal Reset Oscillation stabilization Operation me HALT mode period wait status
171. e N Ff LE LP Ly Ly Ly 1 bit addition PWM output of expected value N 1 _ T LJ LI LE LE LJ 1 bit non addition The 1 bit addition mode repeats 1 bit addition non addition to PWM output alternately upon MONT overflow output and enables the state of PWM output between current compare value and the next compare value N 1 In this mode 1 bit addition to the PWM output is set by setting ADBn of the MCMPOn register to 1 and 1 bit non addition normal output is set by setting ADBn to 0 Remark 1 4 238 Preliminary Users Manual U14581EJ3VOUMOO CHAPTER 18 METER CONTROLLER DRIVER 18 4 4 PWM output operation output with 1 clock shifted Figure 18 8 Timing of Output with 1 Clock Shifted Count clock UULU UUU ULUL Meter 1 sin SM11 SM12 Meter 1 cos SM13 SM14 Meter 2 sin SM21 SM22 Meter 2 cos SM23 SM24 Meter 3 sin SM31 SM32 Meter 3 cos SM33 SM34 Meter 4 sin SM41 SM42 Meter 4 cos SM43 SM44 If the wave of sin and cos of meters 1 to 4 rises and falls internally as indicated by the broken line the SM11 to SM44 pins always shift the count clock by 1 clock and output signals in order to prevent Vpp GND from fluctuating Preliminary User s Manual U14581EJ3VOUMOO 239 MEMO 240 Preliminary User s Manual U14581EJ3VOUMOO 19 1 2 3 19 CHAPTER 19 INTERRUPT FUNCTIONS 1 Interrupt Function Types The following three types of interrupt functi
172. e SIO2 If itis not necessary to use serial interface SIO2 in the HALT mode the power consumption can be reduced by stopping the operation of the serial interface SIO2 before the HALT instruction is executed b Operation in STOP mode Serial interface SIO2 can operate in the STOP mode if the slave mode in which an external clock is used is selected Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 15 SERIAL INTERFACE SIO3 15 1 Serial Interface Functions The serial interface SIO3 has the following two modes 1 Operation stop mode This mode is used when serial transfers are not performed For details see 15 4 1 Operation stop mode 2 3 wire serial I O mode fixed as MSB first This is an 8 bit data transfer mode using three lines a serial clock line SCK3 serial output line SO3 and serial input line SI3 Since simultaneous transmit and receive operations are enabled in 3 wire serial 1 mode the processing time for data transfers is reduced The first bit in the 8 bit data in serial transfers is fixed as the MSB 3 wire serial I O mode is useful for connection to a peripheral I O device that includes a clocked serial interface a display controller etc For details see 15 4 2 3 wire serial mode Figure 15 1 shows the serial interface SIO3 block diagram Figure 15 1 Serial Interface SIO3 Block Diagram Internal bus Serial I O shift register 3 SIO3 SI3 P52 gt SO3 P51 lt en
173. e during A D conversion Voltage comparator The voltage comparator compares the analog input to the series resistor string output voltage Series resistor string The series resistor string is in AVRer to AVss and generates a voltage to be compared to the analog input ANIO to ANI4 pins These are five analog input pins to input analog signals to undergo A D conversion to the A D converter ANIO to ANI4 are alternate function pins that can also be used for digital input Caution Keep the input voltage of ANIO to 4 within the rated range If a voltage outside the rated range is input the conversion value of that channel is undefined and the values of the other channels may be also affected Preliminary Users Manual U14581EJ3VOUMOO 155 CHAPTER 12 A D CONVERTER 7 AVreF pin Shared with AVpp This pin inputs the A D converter reference voltage This pin also functions as an analog power supply pin Supply power to this pin when the A D converter is used It converts signals input to ANIO to ANI4 into digital signals according to the voltage applied between AVrer and AVss The current flowing in the series resistor string can be reduced by setting the voltage to be input to the AVrer pin to AVss level in the standby mode 8 AVss pin 156 This is the GND potential pin of the A D converter Always keep it at the same potential as the Vss pin even when not using the A D converter Preliminary User s Manual U145
174. e equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under c
175. e external device connected to each port does not recognize the port status immediately after reset therefore the pin must be connected to or Vss via a resistor Cautions 1 select the number of VPP pulses shown in Table 22 3 for the transmission method 2 If performing write operations to flash memory with the UART transmission method set the main system clock oscillation frequency to 4 19 MHz or higher Figure 22 3 Transmission Method Selection Format Vss i Voo J RESET Flash write mode Vss VPP pulses A 10V VPP Voo 278 Preliminary User s Manual U14581EJ3V0UM00 CHAPTER 22 4PD78F0852 22 3 2 Flash memory programming function Flash memory programming functions such as flash memory writing are performed through command and data transmit receive operations using the selected transmission method The main functions are listed in Table 22 4 Table 22 4 Main Functions of Flash Memory Programming Reset Detects write stop and transmission synchronization Batch verify Compares entire memory contents and input data Batch delete Deletes the entire memory contents Batch blank check Checks the deletion status of the entire memory High speed write Performs writing to flash memory according to write start address and number of write data bytes Continuous write Performs successive write operations using the data input with high speed write
176. e performed continuously until bit 7 ADCS1 of the A D converter mode register ADM1 is reset to 0 by software If a write operation to the ADM1 and analog input channel specification register ADS1 is performed during an A D conversion operation the conversion operation is initialized and if the ADCS1 bit is set to 1 conversion starts ADCR1 again from the beginning RESET input clears the A D conversion result register ADCR1 to 00H Preliminary User s Manual U14581EJ3V0UM00 161 CHAPTER 12 A D CONVERTER 12 4 2 Input voltage and conversion results The relation between the analog input voltage input to the analog input pins ANIO to 4 and the A D conversion result stored in the A D conversion result register ADCR1 is shown by the following expression VIN AVREF ADCR1 INT x 256 0 5 or ABORI 0 5 ween cds xo 256 256 where INT Function which returns integer part of value in parentheses VIN Analog input voltage AVrer AVreF pin voltage ADCR 1 A D conversion result register ADCR1 value Figure 12 8 shows the relation between the analog input voltage and the A D conversion result Figure 12 8 Relation between Analog Input Voltage and A D Conversion Result 255 ee 254 A D conversion result ADCR1 1 1 3 2 5 3 507 254 509 255 511 1 512 256
177. e power consumption Cautions 1 This function is available only when the device is operated at fx 4 to 4 19 MHz In other cases be sure not to set 1 to HALFOSC 2 When using in normal operation mode setting OSCM is not necessary 3 Only the first setting of OSCM is effective Preliminary User s Manual U14581EJ3V0UMOO 97 98 CHAPTER 5 CLOCK GENERATOR 5 6 Changing Setting of CPU Clock 5 6 1 Time required for switching CPU clock The CPU clock can be selected by using bits 0 to 2 PCCO to PCC2 of the processor clock control register PCC Actually the specified clock is not selected immediately after the setting of has been changed and the old clock is used for the duration of several instructions after that see Table 5 3 Table 5 3 Maximum Time Required for Switching CPU Clock Set Value mm before Switching Set Value after Switching PCC1 PCCO PCC2 PCC1 2 PCCI PCCO ofo 1 o 1 olo NE 16 instructions 16 instructions 16 instructions 16 instructions 8 instructions 8 instructions 8 instructions 8 instructions 4 instructions 4 instructions 4 instructions 4 instructions 2 instructions 2 instructions 2 instructions 2 instructions 1 instruction 1 instruction 1 instruction 1 instruction Remark instruction is the minimum instruction execution time of the CPU clock before switching Preliminary User s Manual U14581EJ3V0UMOO
178. e state 60 Preliminary Users Manual U14581EJ3VOUMOO CHAPTER 3 CPU ARCHITECTURE Table 3 3 Special Function Register List 2 3 Manipulatable Bit Unit Address Special Function Register SFR Name After Reset 1 Bit 8 Bits 16 Bits Port mode register 0 PMO Port mode register 2 PM2 Port mode register 3 PM3 Port mode register 4 PM4 Port mode register 5 PM5 Port mode register 6 PM6 Port mode register 8 PM8 Port mode register 9 PM9 Pull up resistor option register PUO Clock output selection register CKS Watch timer mode control register WTM Watchdog timer clock select register WDCS External interrupt rising edge enable register EGP External interrupt falling edge enable register EGN LCD timer control registerNote LCDTM Compare register sin side MCMP10 Compare register cos side MCMP 1 1 Compare register sin side MCMP20 Compare register cos side 21 Compare register sin side MCMP30 Compare register cos side MCMP31 Compare register sin side MCMP40 Compare register cos side MCMP41 Timer mode control register MCNTC Port mode control register PMC Compare control register 1 MCMPC1 Compare control register 2 MCMPC2 Compare control register 3 MCMPC3 Compare co
179. ed received in 8 bit units 8 bit data is transmitted received bit by bit in synchronization with the serial clock Two transfer modes are provided for the 3 wire serial I O mode transmit receive mode and receive only mode After setting each operation mode using the serial operation mode register CSIM2 transmit receive operation is started by performing an operation that will be the start trigger 3 Transfer start A serial transfer starts when the following conditions have been satisfied Receive only mode When CSIE2 1 and MODE 1 transfer starts when writing to 5102 Transmit receive mode When CSIE2 1 and MODE 0 transfer starts when reading from SIO2 Caution After data has been written to 5102 transfer will not start even if the CSIE2 bit value is set to 1 Completion of an 8 bit transfer automatically stops the serial transfer operation and sets a serial transfer completion flag Preliminary User s Manual U14581EJ3VOUMOO 195 CHAPTER 14 SERIAL INTERFACE SIO2 4 Operation mode a Master mode with internal clock SCK2 Serial interface SIO2 operates in the master mode with internal clock SCK2 if bits 1 and 0 SCL21 and SCL20 of the serial operation mode register 2 CSIM2 are set to 0 1 1 0 or 1 1 Transfer is started when data has been read from or written to the serial shift register 2 5102 The serial data is output from the SO2 pin in synchronization with the serial clock Sele
180. eive operation is enabled when 1 is set to bit 6 RXE of the asynchronous serial interface mode register ASIM and input via the RxD pin is sampled The serial clock specified by ASIM is used when sampling the RxD pin When the RxD pin goes low the 5 bit counter of the baud rate generator begins counting and the start timing signal for data sampling is output when half of the specified baud rate time has elapsed If sampling the RxD pin input with this start timing signal yields a low level result a start bit is recognized after which the 5 bit counter is initialized and starts counting and data sampling begins After the start bit is recognized the character data parity bit and one bit stop bit are detected at which point reception of one data frame is completed Once reception of one data frame is completed the receive data in the shift register is transferred to the receive buffer register RXB and a receive completion interrupt INTSR occurs Even if an error has occurred the receive data in which the error occurred is still transferred to RXB INTSR occurs if bit 1 ISRM of ASIM is cleared to 0 on occurrence of an error If the ISRM bit is set to 1 INTSR does not occur see Figure 13 9 If the RXE bit is reset to 0 during a receive operation the receive operation is stopped immediately At this time the contents of RXB and ASIS do not change nor does INTSR or INTSER occur Figure 13 8 shows the timing of the asynchronou
181. er 3 block diagram Figure 8 1 8 Bit Timer Event Counter 2 TM2 Block Diagram Internal bus INTTM2 8 bit compare register 2 CR2 TIO2 P43 fx 2 Mask circuit 8 Selector TIO2 P43 Selector P43 output latch PM43 Note Invert level 4 Timer mode control register 2 TMC2 1 3 Timer clock select register 2 TCL2 Internal bus Note Bit 3 of port mode register 4 PM4 Preliminary User s Manual U14581EJ3VOUMOO 121 CHAPTER 8 8 TIMER EVENT COUNTERS 2 TM2 AND 3 Figure 8 2 8 Bit Timer Event Counter 3 Block Diagram Internal bus E 8 bit compare register 3 CR3 44 24 Mask circuit 4 25 5 5 2 6 fx 28 D 8 bit counter 3 OVF 8 fx 210 e TM3 44 212 Clear P44 output latch PM44 Note Timer mode control register 3 TMC3 Et Timer clock select register 3 TCL3 Internal bus Note Bit 4 of port mode register 4 PM4 122 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 8 8 BIT COUNTERS 2 TM2 AND 3 8 2 8 Bit Timer Event Counters 2 TM2 and 3 Configurations The 8 bit timer event counters 2
182. er to 0 count operation disabled prescaler disabled Count operation start 6 TMn Operation Mode Selection Clear and start mode by matching between TMn and CRn PWM Free running mode Timer Output F F Status Setting No change Timer output F F reset to 0 Timer output F F set to 1 Setting prohibited In Other Modes TMCn6 0 In PWM Mode 6 1 Timer F F Control Active Level Selection Inversion operation disabled Active high Inversion operation enabled Active low Timer Output Control Output disabled Port mode Output enabled Cautions 1 Bits 4 and 5 must be set to 0 2 Bits 2 and 3 are write only Remarks 1 PWM mode PWM output will be inactive because of TCEn 0 2 If LVSn and LVRn are read after data is set they will be 0 3 2 3 126 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 8 8 BIT TIMER EVENT COUNTERS 2 TM2 AND 3 3 Port mode register 4 4 This register sets port 4 to the input or output mode in 1 bit units To use the 43 2 44 pins as timer output pins clear the output latches of PM43 and PM44 and P43 and P44 to 0 PM4 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM4 to FFH Figure 8 6 Port Mode Register 4 PM4 Format Address FF24H After Reset FFH R W Symbol 7 6 5 4 3 2 1 0 P4n Pin I O Mode Selection Output mode out
183. erator Processor clock control register PCC Oscillator mode register OSCM 1 Processor clock control register PCC PCC sets the division ratio of the CPU clock PCC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PCC to 04H Figure 5 2 Processor Clock Control Register PCC Format Address FFFBH After Reset 04H R W Symbol 7 6 5 4 3 2 1 0 ec o o o o o ec oco PCC1 PCCO CPU Clock fceu Selection fx fx 2 fx 22 fx 28 fx 24 Other than above Setting prohibited Caution Bits 3 to 7 must be set to 0 Remark fx Main system clock oscillation frequency The fastest instructions of the uPD780852 Subseries are executed in two CPU clocks Therefore the relation between the CPU clock fceu and the minimum instruction execution time is as shown in Table 5 2 Table 5 2 Relation between CPU Clock and Minimum Instruction Execution Time Minimum Instruction Execution Time 2 f CPU Clock fcu rn fceu 8 MHz fceu 8 38 MHz Remark fx Main system clock oscillation frequency 92 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 5 CLOCK GENERATOR 2 Oscillator mode register OSCM The uPD780851 A and uPD780852 A can be set to the reduced current consumption mode by setting OSCM only when operated at fx 4 to 4 19 MHz OSOM is set with a 1 bit or 8 bit memory manipulation instruction RESET inpu
184. eristics Type 8 A pullup enable e m D data Lr p 1 O OUT output disable output disable Push pull output whose output can go into a high impedance state both P ch and N ch are off Type 5 Vpp data P ch Comparator T F D IN OUT output N ch VREF disable Threshold voltage 77 input enable input enable Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 2 PIN FUNCTION Figure 2 1 Circuits of Pins 2 2 Type 17 G Voo get gt l output disable input enable L Vico P ch Vici Preliminary User s Manual U14581EJ3VOUMOO 45 MEMO 46 Preliminary User s Manual U14581EJ3VO0UMOO CHAPTER 3 CPU ARCHITECTURE 3 4 Memory Spaces The uPD780852 Subseries can access 64 Kbyte memory space Figures 3 1 to 3 3 show memory maps of the respective devices Figure 3 1 Memory Map uPD780851 A Special function registers SFRs 256 x 8 bits General registers 32 x 8 bits Internal high speed RAM 1 024 x 8 bits FBOOH FAFFH Reserved FA6DH FA6CH LCD display RAM 20 x 4 bits Program area Data memory E 1000H R
185. errupt request signal INTAD Caution Bits 0 to 5 must be set to 0 4 Power fail compare threshold value register PFT The power fail compare threshold value register PFT sets a threshold value against which the result of A D conversion is to be compared PFT is set with an 8 bit memory manipulation instruction RESET input clears PFT to 00H Figure 12 6 Power Fail Compare Threshold Value Register PFT Format Address FF83H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 Preliminary Users Manual U14581EJ3VOUMOO 159 CHAPTER 12 A D CONVERTER 12 4 A D Converter Operations 12 4 1 Basic operations of A D converter 1 lt 2 gt lt 3 gt lt 4 gt lt 5 gt lt 6 gt lt 7 gt lt 8 gt 160 Select one channel for A D conversion with the analog input channel specification register ADS1 The voltage input to the selected analog input channel is sampled by the sample amp hold circuit When sampling has been done for a certain time the sample amp hold circuit is placed in the hold state and the input analog voltage is held until the A D conversion operation is ended Set bit 7 of the successive approximation register SAR so that the tap selector sets the series resistor string voltage tap to 1 2 The voltage difference between the series resistor string voltage tap and analog input is compared with the voltage comparator If the analog input is greater than 1 2 AVrer the
186. errupt requests are generated simultaneously 0 is the highest priority and 18 is the lowest 2 Basic configuration types A to E correspond to A to E in Figure 19 1 242 Preliminary User s Manual U14581EJ3VOUMOO CHAPTER 19 INTERRUPT FUNCTIONS Figure 19 1 Basic Configuration of Interrupt Function 1 2 A Internal non maskable interrupt Internal bus Interrupt request Priority controller Vector table address generator Standby release signal B Internal maskable interrupt Internal bus Vector table Interrupt address generator request gt Standby release signal C External maskable interrupt 16 bit timer capture input Internal bus TEF Vector table address generator Standby release signal Interrupt request Preliminary User s Manual U14581EJ3VOUMOO 243 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19 1 Basic Configuration of Interrupt Function 2 2 D External maskable interrupt except 16 bit timer capture input Internal bus q T Vector table E Priority controller address generator Standby release signal External interrupt edge enable register EGP EGN Edge detector Interrupt IF request E Software interrupt Internal bus Interrupt request Priority controller Vector table address generator IF Interrupt request flag IE Interrupt enable flag ISP In service
187. ertain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electro
188. eserved OFFFH F800H F7FFH CALLF entry area Internal expansion RAM 2 512 x 8 bits 0 F600H Program area F5FFH Reserved 0080H 8000H 007FH CALLT table area Program memory Internal ROM 2 space 32 768 x 8 bits Vector table area Y 0000H 0000H Preliminary User s Manual U14581EJ3VOUMOO 47 CHAPTER 3 CPU ARCHITECTURE 48 Figure 3 2 Memory Map uPD780852 A Data memory space Special function registers SFRs 256 x 8 bits General registers 32 x 8 bits Internal high speed RAM 1 024 x 8 bits FBOOH FAFFH Reserved FA6DH FA6CH 9FFFH LCD display RAM FA59H FAS8H 1000H Reserved OFFFH F800H F7FFH CALLF entry area Internal expansion RAM PEE 512 x 8 bits F600H Program area F5FFH Reserved 0080H A000H 007FH CALLT table area Program memory Internal ROM 2 40 960 x 8 bits Vector table area 0000 0000H Preliminary User s Manual U14581EJ3VOUM00 CHAPTER 3 CPU ARCHITECTURE Figure 3 3 Memory Map uPD78F0852 Data memory space Special function registers SFRs 256 x 8 bits General registers 32 x 8 bits Internal high speed RAM 1 024 x 8 bits FBOOH FAFFH Reserved FA6DH FA6CH 9FFFH LCD display RAM 20 x 4 bits Program area FA59H FA58H 1000H Reserved OFFFH F800H F7FFH CALLF entry area Internal expansion RAM
189. et as a segment output pin is not used leave that pin open Preliminary User s Manual U14581EJ3VOUMOO 211 CHAPTER 16 LCD CONTROLLER DRIVER 16 4 LCD Controller Driver Settings LCD controller driver settings should be performed as shown below 1 Setthe initial value in the display data memory FA59H to FA6CH 2 Set the pins to be used as segment outputs in the LCD display control register 3 Set the LCD clock in the LCD display mode register LCDM Next set data in the display data memory according to the display contents 212 Preliminary User s Manual U14581EJ3VOUMOO CHAPTER 16 LCD CONTROLLER DRIVER 16 5 LCD Display Data Memory The LCD display data memory is mapped onto addresses FA59H to FA6CH The data stored in the LCD display data memory can be displayed on an LCD panel by the LCD controller driver Figure 16 5 shows the relation between the LCD display data memory contents and the segment outputs common outputs Any area not used for display can be used as normal RAM Figure 16 5 Relation between LCD Display Data Memory Contents and Segment Common Outputs Address b7 be bs ba bs be bi bo qe peer mee Hem 6 i 50 eme cere M FA6BH 81 ENS Meet d FA6AH S2 FA69H S3 F i aese Z ees b aet esc l eel Se Toe FA5BH S17 P83
190. event counter 2 channels Watch timer 1 channel Watchdog timer 1 channel Vectored interrupt sources 21 Power supply voltage 4 0 to 5 5 V 1 2 Applications Automobile meter dash board control Preliminary User s Manual U14581EJ3VOUMOO 27 CHAPTER 1 OUTLINE 1 3 Ordering Information Part Number Package Internal ROM 780851 8 80 plastic QFP 14 x 14 mm Mask ROM 780852 8 80 pin plastic QFP 14 x 14 mm Mask ROM uPD78F0852GC 8BT 80 pin plastic QFP 14 x 14 mm Flash memory Remark indicates ROM code suffix 1 4 Quality Grade Part Number Package Quality Grade uPD78F0852GC 8BT 80 pin plastic QFP 14 x 14 mm Standard 780851 8 80 plastic QFP 14 x 14 mm Special 780852 8 80 pin plastic QFP 14 x 14 mm Special Remark indicates ROM code suffix Please refer to Quality Grades on NEC Semiconductor Device Document No C11531E published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications 28 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 1 OUTLINE 1 5 Pin Configuration Top View 80 pin plastic QFP 14 x 14 mm 780851 8 7808520 8 78F0852GC 8BT P85 815 P84 816 P83 S17 P82 S18 P81 S19 VPP x1 X2 Vssi Vnour RESET P07 P06 PO5 SI2 P04 SO2
191. f Z 0 addr16 Conditional addr16 Branch addr16 addr16 N Ml NI NI mM MH oO N N Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM area is accessed Remark One instruction clock cycle is one cycle of the CPU clock fceu selected by the processor clock control register PCC 290 Preliminary User s Manual U14581EJ3VOUMOO CHAPTER 23 INSTRUCTION SET Instruction Group Mnemonic Operands saddr bit addr16 Operation PC lt PC 3 jdisp8 if saddr bit 1 sfr bit addr16 PC lt PC 4 jdisp8 if sfr bit 1 A bit addr16 PC lt PC 3 jdisp8 if A bit 1 PSW bit addr16 PC lt PC 3 jdisp8 if PSW bit 1 HL bit addr16 PC lt PC 3 jdisp8 if HL bit 1 saddr bit addr16 PC PC 4 jdisp8 if saddr bit 0 sfr bit addr16 PC PC 4 jdisp8 if sfr bit 0 A bit addr16 PC lt PC 3 jdisp8 if A bit 0 PSW bit addr16 PC PC 4 jdisp8 if PSW bit 0 HL bit addr16 PC lt PC 3 jdisp8 if HL bit 0 saddr bit addr16 RI OLR HR wl wo wo AJo PC amp PC 4 jdisp8 if saddr bit 1 then reset saddr bit sfr bit addr16 PC PC 4 jdisp8 if sfr bit 1 then reset sfr bit A bit addr16 PC amp PC
192. flow of TMn ns eal lods diii fu Mn IT EEE oa E EST EE 1 1 CRn N pop a 1 TCEn I I INTTMn i I i i Loool l CRn transition N M Remark 2 3 134 Preliminary User s Manual U14581EJ3V0UM00 CHAPTER 8 8 BIT TIMER EVENT COUNTERS 2 TM2 AND 3 8 5 8 Bit Timer Event Counters 2 TM2 and 3 TM3 Cautions 1 Timer start errors An error with a maximum of one clock may occur concerning the time required for a match signal to be generated after timer start This is because 8 bit counters 2 and 3 TM2 and TM3 is started asynchronously with the count pulse Figure 8 11 8 Bit Counters 2 and 3 TM2 and Start Timing cwtpie LT LT LI L Timer start Remark 2 3 2 Operation after compare register change during timer count operation If the values after the 8 bit compare registers 2 and 3 CR2 and CR3 are changed are smaller than the value of 8 bit counters 2 and 3 2 and TM2 and continue counting overflow and then restart counting from 0 Thus if the value M after CR2 and CR3 change is smaller than value before the change it is necessary to restart the timer after changing CR2 and CR3 Figure 8 12 Timing after Compare Register Change during Timer Count Operation X Remarks 1 gt gt 2 2 3 3 2 reading during timer operation When 2
193. gment signal output of the LCD controller driver Segment output and input output port can be switched by setting the LCD display control register LCDC RESET input sets port 9 to input mode Figure 4 10 shows a block diagram of port 9 Figure 4 10 P90 to P97 Block Diagram 7 4 RD 5 WRpeort oe 2 Output latch P90 to P97 P90 S12 to P97 S5 WRem 90 97 4 NJ Segment output latch PM Port mode register RD Port 9 read signal WR Port 9 write signal Preliminary User s Manual U14581EJ3V0UMOO 85 CHAPTER 4 PORT FUNCTIONS 4 3 Port Function Control Registers The following two types of registers control the ports 1 86 Port mode registers PMO PM2 to PM6 PM8 9 Pull up resistor option register PUO Port mode registers PM2 to PM6 PM8 PM9 These registers are used to set port input output in 1 bit units PM2 to PM6 PM8 and are independently set with a 1 bit or 8 bit memory manipulation instruction RESET input sets these registers to FFH When a port pin is used as an alternate function pin set the port mode register and output latch corresponding to the port in accordance with the function to be used Cautions 1 Pins P10 to P17 are input only pins and pins P20 to P27 and P30 to P37 are output only pins 2 PortOhasanalternate function as external interrupt request input when the port functi
194. gnal and Segment Signal Voltages and Phases Selected Not selected Common signal Vico Segment signal Vico T One LCDCL cycle Preliminary User s Manual U14581EJ3V0UM00 215 CHAPTER 16 LCD CONTROLLER DRIVER 16 7 Supplying LCD Drive Voltage Vico Vici and Vic2 The uPD780852 Subseries have a split resistor to create an LCD drive voltage and the drive voltage is fixed to 1 3 bias To supply various LCD drive voltages internal Voo or external Vicp supply voltage can be selected Table 16 5 LCD Drive Voltage Bias Method LCD Drive Voltage 1 3 Bias Method Vreo 2 3Vicp 1 Figure 16 8 shows example of supplying an LCD drive voltage from internal source according to Table 16 5 By using variable resistors r and re a non stepwise LCD drive voltage can be supplied 216 Preliminary User s Manual U14581EJ3V0UM00 CHAPTER 16 LCD CONTROLLER DRIVER Figure 16 8 Example of Connection of LCD Drive Power Supply To supply LCD drive voltage from Vicp vss ae Vss Vicp b To supply LCD drive voltage from external source Voo Voo ues PDH E P ch Zn 0 4 Vico gn Vico R 777 Vss Vic 3 Vicp R Vico R vss 1 Vss R Vicp x r ere Preliminary User s Manual U14581EJ3V0UMOO 217 CHAPTER 16 LCD CONTROLLER DRIVER
195. hdog timer and the interval timer WDCS is set with an 8 bit memory manipulation instruction RESET input clears WDCS to 00H Figure 10 2 Watchdog Timer Clock Select Register WDCS Format Address FF42H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 fx 2 2 489 us Overflow Time of Watchdog Timer Interval Timer 213 978 us 214 1 96 ms 215 3 91 ms fx 216 7 82 ms fx 217 15 6 ms 218 31 3 ms fx 220 125 ms Cautions 1 When rewriting WDCS to other data stop the timer operation beforehand 2 Bits 3 to 7 must be set to 0 Remarks 1 fx Main system clock oscillation frequency 2 Figures in parentheses apply to operation with fx 8 38 MHz Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 10 WATCHDOG TIMER 2 146 Watchdog timer mode register WDTM This register sets the watchdog timer operating mode and enables disables counting WDTM is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears WDTM to 00H Figure 10 3 Watchdog Timer Mode Register WDTM Format Address FFF9H After Reset OOH R W Symbol 7 6 5 4 3 2 1 0 wom o o worm wm 9 9 Watchdog Timer Operation Mode Selection Note 1 0 Count stop 1 Counter is cleared and counting starts WDTM4 WDTM3 Watchdog Timer Operation Mode Selection Note 2 and Reset by the Watchdog Timer and Timer Interrupt Control 0 x Interva
196. herefore no parity errors will occur regardless of whether the parity bit is a O or a 1 iv No parity No parity bit is added to the transmit data During reception receive data is regarded as having no parity bit Since there is no parity bit no parity errors will occur Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 13 SERIAL INTERFACE UART c Transmission The transmit operation is started when transmit data is written to the transmit shift register TXS A start bit parity bit and stop bit s are automatically added to the data Starting the transmit operation shifts out the data in TXS thereby emptying TXS after which a transmit completion interrupt INTST is issued The timing of the transmit completion interrupt is shown in Figure 13 7 Figure 13 7 Asynchronous Serial Interface Transmit Completion Interrupt Timing i Stop bit length 1 bit Caution Donotrewrite the asynchronous serial interface mode register ASIM during a transmit operation Rewriting to the ASIM register during a transmit operation may disable further transmit operations in such case enter a RESET to restore normal operation Whether or nota transmit operation is in progress can be determined by software using the transmit completion interrupt INTST or the interrupt request flag STIF that is set by INTST Preliminary User s Manual U14581EJ3VOUMOO 183 CHAPTER 13 SERIAL INTERFACE UART 184 d Reception The rec
197. ial interface UART mode Figure 13 1 shows the serial interface UART block diagram Figure 13 1 Serial Interface UART Block Diagram Internal bus Asynchronous serial interface status register ASIS M RE XB Direction controller l T 3 Transmit shift Direction controller register TXS RxD P53 register RXS TXE Transmit controller INTST i TxD P54 lt INTSER fx 2 Receive controller INTSR 22 Baud rate generator fx 25 6 2 fx2 3 4 fx 2 xe Re 51 Pso ct st srm TPS2 TPS1 TPSO MDL3 MDL2 MDL1 MDLO Asynchronous serial interface mode register ASIM Baud rate generator control register BRGC Internal bus Preliminary User s Manual U14581EJ3VOUMOO 169 CHAPTER 13 SERIAL INTERFACE UART 13 2 Serial Interface Configuration The serial interface UART consists of the following hardware 1 2 3 4 170 Table 13 1 Serial Interface UART Configuration Item Configuration Registers Transmit shift register TXS Receive shift register RXS Receive buffer register RXB Control registers Asynchronous serial interface mode register ASIM Asynchronous serial interface status register ASIS Baud rate generator control register BRGC Transmit shift register TXS This is the register for setting transmit data Data written to TXS is transmitted as serial data When the data length is set as 7 bits bits 0
198. igure 3 11 Data to Be Reset from Stack Memory RETI and RETB POP rp instruction RET instruction instructions SP Register pair low SP gt PC7 to PCO SP PC7 to PCO SP 1 Register pair high SP 1 PC15 to PC8 SP 1 PC15 to PC8 SP SP 2 SP SP 2 SP 2 PSW SP SP 3 Preliminary User s Manual U14581EJ3VOUM00 57 CHAPTER 3 CPU ARCHITECTURE 3 2 2 General registers General registers are mapped at particular addresses FEEOH to FEFFH of the data memory Four banks of general registers each consisting of eight 8 bit registers X A C B E D L and H are available Each register can also be used as an 8 bit register Two 8 bit registers can be used in pairs as a 16 bit register AX BC DE and HL They can be described in terms of function names X A C B E D L H AX BC DE and HL and absolute names RO to R7 and RPO to RP3 Register banks to be used for instruction execution are set with the CPU control instruction SEL RBn Because of the 4 register bank configuration an efficient program can be created by switching between a register for normal processing and a register for interrupt processing for each bank Figure 3 12 General Register Configuration a Absolute Name 16 bit processing 8 bit processing FEFFH RP3 FEF8H RP2 FEFOH RP1 FEE8H RPO FEEOH 15 0 b Function Name 16 bit processing 8 bit processing HL DE BC AX 15 0 58 Preliminary
199. in 2 Input mode A value is written to the output latch by a transfer instruction but since the output buffer is OFF the pin status does not change Once data is written to the output latch it is retained until data is written to the output latch again Caution In the case of 1 bit memory manipulation instruction although a single bit is manipulated the port is accessed as an 8 bit unit Therefore on a port with a mixture of input and output pins the output latch contents for pins specified as input are undefined even for bits other than the manipulated bit 4 4 2 Reading from input output port 1 Output mode The output latch contents are read by a transfer instruction The output latch contents do not change 2 Input mode The pin status is read by a transfer instruction The output latch contents do not change 4 4 3 Operations on input output port 1 Output mode An operation is performed on the output latch contents and the result is written to the output latch The output latch contents are output from the pins Once data is written to the output latch it is retained until data is written to the output latch again 2 Input mode The output latch contents are undefined but since the output buffer is OFF the pin status does not change Caution In the case of 1 bit memory manipulation instruction although a single bit is manipulated the port is accessed as an 8 bit unit Therefore on a port with a mixture of input
200. inary User s Manual U14581EJ3VOUMOO 55 CHAPTER 3 CPU ARCHITECTURE 56 a b c d e f Interrupt enable flag IE This flag controls the interrupt request acknowledge operations of the CPU When 0 the IE is set to DI and only non maskable interrupt request becomes acknowledgeable Other interrupt requests are all disabled When 1 the IE is set to El and interrupt request acknowledge enable is controlled with an in service priority flag ISP an interrupt mask flag for various interrupt sources and a priority specify flag The IE is reset to 0 upon DI instruction execution or interrupt acknowledgement and is set to 1 upon EI instruction execution Zero flag Z When the operation result is zero this flag is set to 1 It is reset to 0 in all other cases Register bank select flags RBSO and RBS1 These are 2 bit flags to select one of the four register banks In these flags the 2 bit information which indicates the register bank selected by SEL RBn instruction execution is stored Auxiliary carry flag AC If the operation result has a carry from bit 3 or a borrow at bit 3 this flag is set to 1 It is reset to 0 in all other cases In service priority flag ISP This flag manages the priority of acknowledgeable maskable vectored interrupts When this flag is 0 low level vectored interrupts specified with a priority specify flag register PROL PROH PR1L see 19 3 3 Priority specify fl
201. inimum instruction execution timer variable function 0 24 us 0 48 us 0 95 us 1 91 us 3 81 us in operation at 8 38 MHz Instruction set 16 bit operation Multiply divide 8 bits x 8 bits 16 bits 8 bits Bit manipulation set reset test and Boolean operation BCD adjust etc port including pins shared with segment signal output Total 56 CMOS input 5 CMOS output 16 CMOS input output 35 A D converter 8 bit resolution x 5 channels Power fail detection function LCD controller driver Segment signal outputs 20 max Common signal outputs 4 max Bias 1 3 bias only Serial interface 3 wire serial mode 2 channels UART mode 1 channel Timer 16 bit timer 1 channel 8 bit timer 1 channel 8 bit timer event counter 2 channels Watch timer 1 channel Watchdog timer 1 channel Timer outputs 2 8 bit PWM output 2 Meter controller driver PWM output 8 bit resolution 16 Can set pulse width with a precision of 8 1 bits with 1 bit addition function Sound generator 1 channel Clock output 65 5 kHz 131 kHz 262 kHz 524 kHz 1 04 MHz 2 09 MHz 4 19 MHz 8 38 MHz 8 38 MHz operation with main system clock Vectored interrupt Maskable Internal 16 External 3 source Non maskable Internal 1 Software 1 Power supply voltage Voo SMVop 4 0 to 5 5 V Operating ambient temperature Ta 40 C to 85
202. intended by NEC they must contact an NEC sales representative in advance to determine NEC s willingness to support a given application Note 1 NEC as used in this statement means NEC Corporation and also includes its majority owned subsidiaries 2 NEC semiconductor products means any semiconductor product developed or manufactured by or for NEC as defined above M8E 00 4 6 Preliminary User s Manual U14581EJ3VO0UMOO Regional Information Some information contained in this document may vary from country to country Before using any NEC product in your application please contact the NEC office in your country to obtain a list of authorized representatives and distributors They will verify Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications for example specifications for third party tools and components host computers power plugs AC supply voltages and so forth Network requirements In addition trademarks registered trademarks export restrictions and other legal issues may also vary from country to country NEC Electronics Inc U S Santa Clara California Tel 408 588 6000 800 366 9782 Fax 408 588 6130 800 729 9288 NEC Electronics Germany GmbH Duesseldorf Germany Tel 0211 65 03 02 Fax 0211 65 03 490 NEC Electronics UK Ltd Milton Keynes UK Tel 01908 691 1
203. ion result register ADCR1 Control register A D converter mode register ADM1 Analog input channel specification register ADS1 Power fail compare mode register PFM Power fail compare threshold value register PFT Successive approximation register SAR This register compares the analog input voltage value to the voltage tap compare voltage value applied from the series resistor string and holds the result from the most significant bit MSB When up to the least significant bit LSB is set end of A D conversion the SAR contents are transferred to the A D conversion result register A D conversion result register ADCR1 This register holds the A D conversion result Each time A D conversion ends the conversion result is loaded from the successive approximation register is read with an 8 bit memory manipulation instruction RESET input clears ADCR1 to 00H Caution When write operation is executed to A D converter mode register ADM1 and analog input channel specification register ADS1 the contents of ADCR1 are undefined Read the conversion result before write operation is executed to ADM1 ADS1 If a timing other than the above is used the correct conversion result may not be read Sample amp hold circuit The sample amp hold circuit samples each analog input sequentially applied from the input circuit and sends it to the voltage comparator This circuit holds the sampled analog input voltage valu
204. isabled status Set the P60 output latch to 0 Set bit 0 PM60 of port mode register 6 to 0 set to output mode Set bit 4 CLOE of CKS to 1 and enable clock output Caution The clock output cannot be used if the output latch of P60 is set to 1 Remark The clock output controller is designed not to output pulses with a small width during output enable disable switching of the clock output As shown in Figure 11 4 be sure to start output from the low period of the clock marked with in the figure below When stopping output do so after securing high level of the clock Figure 11 4 Remote Control Output Application Example Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 12 A D CONVERTER 12 1 A D Converter Functions The A D converter is an 8 bit resolution converter that converts analog inputs into digital values It can control up to 5 analog input channels ANIO to ANIA This A D converter has the following functions 1 A D conversion with 8 bit resolution One channel of analog input is selected from ANIO to ANI4 and A D conversion is repeatedly executed with a resolution of 8 bits Each time the conversion has been completed interrupt request INTAD is generated 2 Power fail detection function This function is to detect a voltage drop in the battery of an automobile The result of A D conversion value of the ADCR1 register and the value of PFT register PFT power fail compare threshold value register are
205. its and Recommended Connection of Unused Pins Table 2 1 shows the input output circuit types of pins and the recommended connection for unused pins See Figure 2 1 for the configuration of the input output circuit of each type Table 2 1 Pin Input Output Circuit Types Pin Name Input Output Circuit Type Input Output Recommended Connection of Unused Pins to PO2 INTP2 Input output Independently connect to Vsso via a resistor P03 SCK2 P04 SO2 P05 SI2 P06 P07 P10 ANIO to P14 ANI4 Input Independently connect to Vppo or Vsso via a resistor P20 SM11 to 23 5 14 Output Leave open P24 SM21 to 27 5 24 P30 SM31 to P33 SM34 P34 SM41 to P37 SM44 P40 TIOO to P42 TIO2 Input output Independently connect to or Vsso via a resistor P43 TIO2 44 50 5 51 5 P52 SI3 P53 RxD P54 TxD P60 PCL TPO P61 SGO P81 S19 to P87 S13 P90 S12 to P97 S5 SO to S4 Output Leave open COMO to COM3 Vicp RESET SMVopp Connect to SMVss Connect to Vsso AVREF Connect to AVss Connect to Vsso Connect directly to Vsso or 1 Preliminary User s Manual U14581EJ3V0UMOO 43 CHAPTER 2 PIN FUNCTION 44 Figure 2 1 Circuits of Pins 1 2 Vpp data OPER output disable IN OUT Schmitt triggered input with hysteresis charact
206. ive data buffer register SIRB2 This is an 8 bit register that stores the data transferred from the serial I O shift register 2 5102 The contents of SIO2 are immediately transferred to SIRB2 when SDVA bit 1 of the receive data buffer status register SRBS2 0 When SDVA 1 the contents of SIO2 are not transferred to SIRB2 and the receive data is held by SIC2 The status of SIRB2 can be checked by using the serial receive data buffer status register SRBS2 If an overflow occurs the value of SIRB2 does not change after SRBS2 has been read until transfer of the new data has been completed SIRB2 can be read with an 8 bit memory manipulation instruction It cannot be written to RESET input makes SIRB2 to undefined Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 14 SERIAL INTERFACE SIO2 14 3 Serial Interface Control Registers The following three types of registers are used to control the serial interface SIO2 Serial operation mode register 2 CSIM2 Serial receive data buffer status register SRBS2 Port mode register 0 PMO 1 Serial operation mode register 2 CSIM2 This register is used to set the SIO2 interface s serial clock operation mode and operation enable disable CSIM2 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears CSIM2 to 00H Figure 14 2 Serial Operation Mode Register 2 CSIM2 Format Address FF98H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 SI
207. ka Serial clock SCK3 P50 gt INTCSI3 2 Serial clock Met controller Selector 24 Serial operation mode register 3 CSIM3 EE mene Internal bus Preliminary User s Manual U14581EJ3V0UM00 201 CHAPTER 15 SERIAL INTERFACE SIO3 15 2 Serial Interface Configuration The serial interface SIO3 consists of the following hardware Table 15 1 Serial Interface SIO3 Configuration Register Serial shift register 3 SIO3 Control register Serial operation mode register 3 CSIM3 1 Serial shift register 3 SIO3 This is an 8 bit register that performs parallel serial conversion and serial transmit receive shift operations synchronized with the serial clock SIO3 is set with an 8 bit memory manipulation instruction When 1 is set to bit 7 CSIES3 of the serial operation mode register CSIM3 a serial operation can be started by writing data to or reading data from SIO3 When transmitting data written to 5103 is output via the serial output 503 When receiving data is read from the serial input SI3 and written to SIO3 RESET input clears SIO3 to 00H Caution not access SIO3 during a transfer operation unless the access is triggered by a transfer start Read is disabled when MODE3 0 and write is disabled when 1 202 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 15 SERIAL INTERFACE SIO3 15 3 Serial Interface
208. l Register Configuration ciuitate D ERR ERE ER a 58 4 1 dO TYPOS IPRC RIS 75 4 2 POO to PO7 Block Diagralm u ie ene pcr tenen Ee dc Spe kx iub a ann aka gn Dep id 78 4 3 P10 to P T4 Block Diagram cei ite tiri rtr t E ER 78 4 4 P20 to P27 Block cr et Suma E sasa ss asses 79 4 5 P3010 acrlsi oe qBIC le I men 80 4 6 P40 to P44 Block Diagrarri ii cr Ret ete eret Eder eese rete Ye et erue t ge une ad 81 4 7 P50 to P54 Block Diagram 82 4 8 60 61 Block Diagram u os u u l u terere rn cu Pene dea uae 83 4 9 P81 to P87 Block Diagrama eee de 84 4 10 P90 to P97 Block DIagEtaltis 85 4 11 Port Mode Register PM4 to PM6 PM8 9 87 4 12 Port Mode Register PM2 87 4 13 Pull Up Resistor Option Register PUO 88 5 1 Clock Generator Block Diagram nennen nnne 91 5 2 Processor Clock Control Register PCC Format 92 5 3 Oscillator Mode Register OSCM Formal u nnn 93 5 4 External Circuit of Main System Clock
209. l timer mode Maskable interrupt request occurs upon generation of an overflow 1 0 Watchdog timer mode 1 Non maskable interrupt request occurs upon generation of an overflow 1 1 Watchdog timer mode 2 Reset operation is activated upon generation of an overflow Notes 1 Once set to 1 RUN cannot be cleared to 0 by software Thus once counting starts it can only be stopped by RESET input 2 Once set to 1 WOTM3 and WDTM4 cannot be cleared to 0 by software Cautions 1 If the watchdog timer is cleared by setting 1 for RUN the actual overflow time will be up to 28 fx seconds shorter than the time set by the watchdog timer clock select register WDCS 2 use watchdog timer modes 1 and 2 make sure that the interrupt request flag WDTIF is 0 and then set WDTMA to 1 If WDTM4 is set to 1 when WDTIF is 1 the non maskable interrupt request occurs regardless of the contents of WDTM3 Remark x don t care Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 10 WATCHDOG TIMER 10 4 Watchdog Timer Operations 10 4 1 Watchdog timer operation When bit 4 WDTMA of the watchdog timer mode register WDTM is set to 1 the watchdog timer is operated to detect any runaways A watchdog timer count clock runaway detection time interval can be selected by using bits 0 to 2 WDCSO to WDCS2 of the watchdog timer clock select register WDCS Watchdog timer starts by setting bit 7 RUN of WDTM to 1 After the watchdog timer is star
210. level is changed by specifying the output mode of the port function an interrupt request flag is set Therefore 1 should be set in the interrupt mask flag before using the output mode 3 Bits 3 to 7 of MK1L must be set to 1 Preliminary User s Manual U14581EJ3V0UMOO 247 CHAPTER 19 INTERRUPT FUNCTIONS 3 248 Priority specify flag registers PROL PROH PR1L The priority specify flag registers are used to set the corresponding maskable interrupt priority orders PROL PROH and are set with a 1 bit or 8 bit memory manipulation instruction If PROL and PROH combined to form 16 bit register PRO they are set with a 16 bit memory manipulation instruction RESET input sets these registers to FFH Figure 19 4 Priority Specify Flag Register PROL PROH PR1L Format Address FFE8H After Reset FFH R W Symbol T 6 5 4 3 2 1 0 Address FFE9H After Reset FFH R W Symbol 7 6 5 4 3 2 1 0 PROH Address FFEAH After Reset FFH R W 7 6 5 4 3 2 1 0 wren wrer CSIPR2 XXPRX Priority Level Selection Symbol PR1L 0 High priority level 1 Low priority level Cautions 1 Whenthe watchdog timer is used in the watchdog timer mode 1 set 1 in the WDTPR flag 2 Bits 3 to 7 of PR
211. llows users to select the internal memory capacity using the memory size switching register IMS so that the same memory map as that of the mask ROM version with a different size of internal memory capacity can be achieved IMS is set with an 8 bit memory manipulation instruction RESET input sets IMS to CFH Figure 22 1 Memory Size Switching Register IMS Format Address FFFOH After Reset R W Symbol 7 6 5 4 3 2 1 0 IMS RAM2 oo ROM3 ROM2 ROMO RAM2 RAM1 RAMO Internal High Speed RAM Capacity Selection 1 024 bytes Setting prohibited ROMO Internal ROM Capacity Selection 32 Kbytes 40 Kbytes Other than above Setting prohibited The IMS settings to obtain the same memory map as the mask ROM version are shown in Table 22 2 Table 22 2 Memory Size Switching Register Settings Mask ROM Version IMS Setting uPD780851 A uPD780852 A 276 Preliminary User s Manual U14581EJ3VOUMOO CHAPTER 22 uPD78F0852 22 2 Internal Expansion RAM Size Switching Register IXS The internal expansion RAM size switching register IXS is used to select the capacity of the internal expansion RAM IXS is set with an 8 bit memory manipulation instruction RESET input sets IXS to OCH Figure 22 2 Internal Expansion RAM Size Switching Register IXS Format Address FFF4H After Reset OCH R W Symbol 7 6 4 3 2 1 0 IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAMO Internal Expansion RAM
212. n port pins Connect this pin to Vsso or Vss via a 0 1 uF capacitor After Reset Alternate Function Ground potential except for port block High voltage application for program write verify Connect directly to Vsso or Vss in normal operation mode uPD78F0852 only Internally connected Connect directly to Vsso or Vss Preliminary User s Manual U14581EJ3VOUMOO 37 CHAPTER 2 PIN FUNCTION 2 2 Description of Pin Functions 2 2 1 P00 to P07 Port 0 These pins constitute an 8 bit input output port In addition they also function as external interrupt request input serial interface data input output and clock input output pins The following operation modes can be specified in 1 bit units 1 Port mode In this mode POO to P07 function as 8 bit input output port POO to P07 can be specified as an input or output port 1 bit units with port mode register 0 On chip pull up resistor can be used in 1 bit units with the pull up resistor option register O PUO 2 Control mode In this mode P00 to PO7 function as external interrupt request input serial interface data input output and clock input output pins a INTPO to INTP2 These are external interrupt input pins for which the valid edge rising edge falling edge and both the rising and falling edges can be specified b 512 Serial interface serial data input pin c SO2 Serial interface serial data output pin
213. n 8 bit register that specifies PWM port output PMC is set with an 8 bit memory manipulation instruction RESET input clears PMC to 00H Figure 18 5 shows the PMC format Figure 18 5 Port Mode Control Register PMC Format Address FF6AH After Reset OOH R W Symbol T 6 5 4 3 2 1 0 Meter n Full Half Bridge Selection 0 Meter n output is full bridge 1 Meter n output is half bridge Meter n Port PWM Mode MeternPor PWMModeSeletion Meter n output is in port mode Meter n output is in PWM mode Remark 1 4 The relation among the ENn MODn of the PMC register DIRn1 and DIRnO of the MCMPOn register and output pins is shown below Port mode PWM mode full bridge PWM mode half bridge DIRn1 and DIRnO mean the quadrant of sin and cos DIRn1 and DIRnO 00 through 11 correspond to quadrants 1 through 4 respectively The PWM signal is output to the specific pin of the and polarities of sin and cos of each quadrant When ENn 0 all the output pins are used as port pins regardless of MODn DIRn1 and DIRnO When ENn 1 and MODn 0 the full bridge mode is set and 0 is output to a pin that does not output a PWM signal When ENn 1 and MODn 1 the half bridge mode is set and the pin that does not output a PWM signal is used as a port pin Caution output polarity of the PWM output changes when MCNT overflows 236 Preliminary User
214. n Emulation ier rr Lagen ncn 168 CHAPTER 13 SERIAL INTERFACE UART T 169 13 1 Serial Interface FUNCTIONS eire ridi Ferre iot nno rn enu eer eo tud ds nex ieu 169 13 2 Serial Interface Configuration U U u u u u u u u u u 170 13 3 Serial Interface Control Registers u u u 171 13 4 Serial Interface Operations 175 1341 Operation Stop MOOS 175 13 4 2 Asynchronous serial interface UART mode sse 175 CHAPTER 14 SERIAL INTERFACE SIO2 ete II notae nnt in annm naar kan penu une 187 14 1 Serial Interface Functions U 187 14 2 Serial Interface Configuration l l 188 14 3 Serial Interface Control Registers l l u u enne nnne nnn nnn nnn 189 14 4 Serial Interface Operations U u u u nennen nannten anna nant nnn nnns 193 14 4 1 Operation STOP MOMS seis eere NL tte nte nrbe deus talea 193 14 4 2 3 wire serial l O u
215. n clock cycle is one cycle of the CPU clock fceu selected by the processor clock control register PCC Preliminary User s Manual U14581EJ3VOUMOO 289 CHAPTER 23 INSTRUCTION SET Instruction Group Mnemonic Operands Operation SP 1 lt PC 3 SP 2 lt PC 3 PC addr16 SP SP 2 SP 1 lt PC 2 4 SP 2 lt PC 2 laddr1 1 PCis 00001 PC10 0 lt addr11 SP SP 2 SP 1 lt PC 1 SP 2 lt PC 1 lt 00000000 addr5 1 lt 00000000 addr5 SP SP 2 SP 1 lt PSW SP 2 lt PC 1 SP 3 lt PC 1 PCH lt 003FH PC 003EH SP SP 3 IE 0 PCH lt SP 1 PC lt SP SP SP 2 PCH lt SP 1 PCL SP PSW lt SP 2 SP lt SP 3 NMIS 0 PCH lt SP 1 SP PSW lt SP 2 SP lt SP 3 SP 1 lt PSW SP lt SP 1 SP 1 lt SP 2 SP e SP 2 PSW lt SP SP lt SP 1 lt SP 1 rp lt SP SP lt 2 laddr16 addr5 Call return rp SP word SP AX AX SP Uncondi laddr16 tional addr16 branch AX SP lt word SP AX AX SP PC lt addr16 PC lt PC 2 jdisp8 PCH A PC X PC lt PC 2 jdisp8 if CY 1 PC lt PC 2 jdisp8 if CY 0 PC c PC 2 jdisp8 if Z 1 PC lt PC 2 jdisp8 i
216. n external clock is input This is because if the STOP instruction is executed the main system clock operation is stopped and the X2 pin is connected to via a pull up resistor 2 Whenusing a main system clock oscillator carry out wiring in the broken line area in Figure 5 4 as follows to avoid influence of wiring capacity Keep the wiring length as short as possible Donotcross the wiring with any other signal lines Do not route the wiring in the vicinity of a line through which a high alternating current flows Always keep the ground of the capacitor of the oscillator at the same potential as Vss Do not ground the capacitor to a ground pattern through which a high current flows Do not fetch signals from the oscillator Figure 5 5 shows examples of resonator having bad connection 94 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 5 CLOCK GENERATOR Figure 5 5 Incorrect Examples of Resonator Connection 1 2 a Too long wiring La c Wiring near high alternating current High current d Current flowing through ground line of oscillator potential at points A B and C b Crossed signal line n 0 to 6 8 and 9 7T fluctuates IC X2 gt ir Pmn X1 Te Preliminary User s Manual U14581EJ3V0UMOO High current 95 CHAPTER 5 CLOCK GENERATOR Figure 5 5 Incorrect Examples of Resonator Connection 2 2 e
217. n frequency fx 8 38 MHz Preliminary User s Manual U14581EJ3V0UMOO 179 CHAPTER 13 SERIAL INTERFACE UART Error tolerance range for baud rates The tolerance range for baud rates depends on the number of bits per frame and the counter s division rate 1 16 k Table 13 3 describes the relation between the main system clock and the baud rate and Figure 13 5 shows an example of a baud rate error tolerance range Table 13 3 Relation between Main System Clock and Baud Rate Baud Rate fx 8 386 MHz bps BRGC Set Value Error 95 600 1 200 2 400 4 800 9 600 19 200 31 250 38 400 76 800 115 200 Remark fx Main system clock oscillation frequency Figure 13 5 Error Tolerance When k z 0 Including Sampling Errors Ideal sampling point 32T 64T 256 288T 320T 352T 304T 336T Basic timing clock cycle T START DO U7 Jj P jso High speed clock 15 5 clock cycle i START D7 P jsroP enabling normal 00 Sampling error 30 45 60 9 304 5 0 5 Low speed clock 15 5 enabling normal START Do A o A P jso recepuon 33 55T 67 1T 301 95T 335 5T Remark T 5 bit counter s source clock cycle 15 5 320 Baud rate error tolerance when 0 x 100 4 8438 96 180 Preliminary User s Manual U14581EJ3VOUMOO CHAPTER 13 SERIAL INTERFACE UART 2 Communication
218. nals is possible by automatic reading of the display data memory 2 Display mode 1 4 duty 1 3 bias 3 Any of four frame frequencies can be selected in each display mode 4 Maximum of 20 segment signal outputs 50 to S19 4 common signal outputs COMO to Fifteen of the segment signal outputs can be switched to input output ports in units of 2 P81 S19 to P87 S13 90 512 to P97 S5 The maximum number of displayable pixels is shown in Table 16 1 Table 16 1 Maximum Number of Display Pixels Bias Method Common Signals Used Maximum Number of Display Pixels COME 80 20 segments x 4 commons Nl Note 10 digits on amp type LCD panel with 2 segments digit Preliminary User s Manual U14581EJ3V0UM00 207 CHAPTER 16 LCD CONTROLLER DRIVER 16 2 LCD Controller Driver Configuration The LCD controller driver consists of the following hardware Table 16 2 LCD Controller Driver Configuration Item Configuration Display outputs Segment signals 20 Dedicated segment signals 5 Segment signal input or output port alternate function 14 Segment signal input or output port 16 bit timer prescaler output alternate function 1 Common signals 4 COMO to COM3 Control registers LCD display mode register LCDM LCD display control register LCDC Figure 16 1 LCD Controller Driver Block Diagram Internal bus LCD display mode register FA59H 76543210 LCDON LCDM6 LCDM5
219. nerate the reset signal 1 External reset input with RESET pin 2 Internal reset by watchdog timer overrun time detection External reset and internal reset have no functional differences In both cases program execution starts at the address at 0000H and 0001H by RESET input When a low level is input to the RESET pin or the watchdog timer overflows a reset is applied and each hardware is set to the status shown in Table 21 1 Each pin has high impedance during reset input or during oscillation stabilization time just after reset clear When high level is input to the RESET pin the reset is cleared and program execution starts after the lapse of oscillation stabilization time 2 7 fx The reset applied by watchdog timer overflow is automatically cleared after reset and program execution starts after the lapse of oscillation stabilization time 217 fx see Figures 21 2 to 21 4 Cautions 1 For an external reset input a low level for 10 us or more to the RESET pin 2 During reset input main system clock oscillation stops but subsystem clock oscillation continues 3 When the STOP mode is cleared by reset the STOP mode contents are held during reset input However the port pin becomes high impedance Figure 21 1 Reset Function Block Diagram Reset controller Reset signal Overflow Count clock Watchdog timer Interrupt function Stop Preliminary User s Manual U14581EJ3VOUMOO 271
220. nics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics RENESAS Preliminary User s Manual uPD780852 Subseries 8 Bit Single Chip Microcontrollers uPD780851 A uPD780852 A uPD78F0852 Document U14581EJ3VOUMO0 3rd edition Date Published October 2000 J CP K NEC Corporation 2000 Printed in Japan MEMO 2 Preliminary User s Manual U14581EJ3VOUM00 CHAPTER 1 CHAPTER 2 CHAPTER 3 CHAPTER 4 CHAPTER 5 CHAPTER 6 CHAPTER 7 CHAPTER 8 CHAPTER 9 CHAPTER 10 CHAPTER 11 CHAPTER 12 CHAPTER 13 CHAPTER 14 CHAPTER 15 CHAPTER 16 CHAPTER 17 CHAPTER 18 CHAPTER 19 CHAPTER 20 CHAPTER 21 CHAPTER 22 CHAPTER 23 APPENDIX A APPENDIX B APPENDIX C APPENDIX D SUMMARY OF CONTENTS OUTLINE ioter 27 FUNCTION 35 CPU ARCHITECTURE eere enne u nnn intr uu u u uuu 47 PORT FUNCTIONS po 75 CLOCK GENERATOR u u a a aaa 91 16 BIT TIMER 0 J I I s sa san nada 101 8 BIT 1 TMI 113 8 TIMER EVENT COUNTERS 2 2 AND 121 WATCH TI
221. nterrupt Source internat Vector Basic Interrupt Type Default External Table Configuration Priority Trigger Address Type Note 2 Non maskable INTWDT Watchdog timer overflow Internal with non maskable interrupt selected Maskable INTWDT Watchdog timer overflow with interval timer selected INTAD End of A D conversion INTOVF 16 bit timer overflow INTTMOO TIOO valid edge detection INTTMO1 TIO1 valid edge detection INTTMO2 TIO2 valid edge detection INTPO Pin input edge detection External INTP1 INTP2 OO O AJ AJOJN INTCSI3 End of serial interface SIO3 transfer Internal INTSER Generation of serial interface UART receive error at INTSR End of serial interface UART reception 5 End of serial interface UART transmission Generation of 8 bit timer register and capture register CR1 match signal INTTM2 Generation of 8 bit timer register and capture register CR2 match signal INTTM3 Generation of 8 bit timer register and capture register CR3 match signal INTCSI2 End of serial interface SIO2 transfer INTWTI Watch timer overflow INTWT Reference time interval signal from watch timer Software BRK BRK instruction execution Notes 1 The default priority is the priority applicable when two or more maskable int
222. ntrol register 4 MCMPC4 Prescaler mode register PRMO Capture compare control register CRCO O O O O O O O O O O O O O O O O O O O O O O O O O O O O 16 bit timer mode control register TMCO Timer clock select register 1 TCL1 Timer clock select register 2 TCL2 Timer clock select register 3 TCL3 8 bit timer mode control register 1 TMC1 8 bit timer mode control register 2 TMC2 O OJO OJOJ OJOJO O OJO O O O O O OI O O O O OP O OI OO O O O O O OP OI O O O O 8 bit timer mode control register 3 TMC3 Note LCDTM is register that must be set when debugging the wPD780852 with an in circuit emulator IE 78K0 NS Preliminary User s Manual U14581EJ3VOUMOO 61 CHAPTER 3 CPU ARCHITECTURE Address Table 3 3 Special Function Register List 3 3 Manipulatable Bit Unit Special Function Register SFR Name After Reset 1 Bit 8 Bits 16 Bits A D converter mode register Analog input channel specification register Power fail compare mode register Power fail compare threshold value register Serial operation mode register 3 Asynchronous serial interface mode register Asynchronous serial interface status register Baud rate generator control register D A converter mode register Note 1 Sound generator control register Sound generator buzzer control register
223. nu scc anna ie e sawa rau pr y daran 313 Preliminary User s Manual U14581EJ3V0UMOO 3 Major Revisions in This Edition Changing 1 5 Pin Configuration Top View Changing description of supply voltage in 1 8 Outline of Function Changing 6 4 4 Port mode register 4 4 Changing Figure 6 11 Capture Register Data Retention Timing Adding Caution 3 to Figure 16 4 LCD Display Control Register LCDC Format Adding Note to Table 22 3 Transmission Method List The mark shows major revised points 4 Preliminary User s Manual U14581EJ3VOUM00 NOTES FOR CMOS DEVICES D PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note Strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it once when it has occurred Environmental control must be adequate When it is dry humidifier should be used It is recommended to avoid using insulators that easily build static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for P
224. ny selected frequency to be output duty 50 Setting 1 Set each register Set port latch and port mode register to 0 e TCLn Select count clock CRn Compare value TMOn Clear and start mode by match of TMn and CRn Timer Output F F Status Setting 1 0 High level output 0 1 Low level output Timer output F F inversion enabled Timer output enabled 1 2 After TCEn 1 is set count operation starts 9 Timer output F F is inverted by match of TMn and CRn After INTTMn is generated TMn is cleared to 4 Timer output F F is inverted at the same interval and square wave is output from TlOn Remark n 2 3 Preliminary User s Manual U14581EJ3VOUMOO 131 CHAPTER 8 8 BIT COUNTERS 2 TM2 AND 3 8 4 4 8 bit PWM output operation 8 bit timer event counters operate as PWM output when bit 6 TMCn6 of 8 bit timer mode control register n TMCn is set to 1 The duty rate pulse determined by the value set to 8 bit compare register n CRn is output from Set the active level width of PWM pulse to CRn and the active level can be selected with bit 1 TMCn1 of TMCn Count clock can be selected with bit O to bit 2 TCLnO to TCLn2 of timer clock select register n TCLn PWM output enable disable can be selected with bit 0 TOEn of TMOn Caution Rewrite of CRn in PWM mode is allowed only once in a cycle Remark 2 3 1 PWM output basic operation 132
225. o when the edge specified by bits 4 and 5 ES10 and ES11 of PRMO is input to the TIO1 P41 pin the value of TMO is taken into 16 bit capture register 01 01 and an external interrupt request signal 01 is set When the edge specified by bits 6 and 7 ES20 and ES21 of PRMO is input to the TIO2 P42 pin the value of is taken into 16 bit capture register 02 CRO2 and external interrupt request signal INTTMO2 is set Any of three edge specifications can be selected rising falling or both edges as the valid edges for the TIOO 40 to 02 42 pins by means of bits 2 and 3 500 and 501 bits 4 and 5 ES10 and 511 and bits 6 and 7 ES20 ES21 of PRMO respectively For 00 40 to TIO2 P42 pins valid edge detection sampling is performed at the interval selected by means of PRMO and a capture operation is only performed when a valid level is detected twice thus eliminating noise with a short pulse width Capture operation free running mode Capture register operation in capture trigger input is shown Figure 6 8 CROm Capture Operation with Rising Edge Specified Count clock Remark 0 2 Preliminary User s Manual U14581EJ3VOUMOO 109 CHAPTER 6 16 BIT TIMER 0 TMO Figure 6 9 Pulse Width Measurement Operation Timing by Free Running Counter with Both Edges Specified TMO count value Y
226. o the asynchronous serial interface mode register ASIM Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 13 SERIAL INTERFACE UART 5 Receive controller The receive controller controls receive operations based on the values set to the asynchronous serial interface mode register ASIM During a receive operation it performs error checking such as for parity errors and sets various values to the asynchronous serial interface status register ASIS according to the type of error that is detected 13 3 Serial Interface Control Registers The following three types of registers are used to control the serial interface UART Asynchronous serial interface mode register ASIM Asynchronous serial interface status register ASIS Baud rate generator control register BRGC 1 Asynchronous serial interface mode register ASIM This is an 8 bit register that controls UART s serial transfer operations ASIM is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears ASIM to 00H Figure 13 2 shows the format of ASIM Caution UART mode set the port mode register PM5X as follows Besides that set all output latches to 0 When receiving Set P53 RxD to the input mode PM53 1 When transmitting Set P54 TxD to the output mode PM54 0 When transceiving Set P53 to the input mode and P54 to the output mode Preliminary User s Manual U14581EJ3V0UM00 171 CHAPTER 13 SERIAL INTERFACE UART
227. ock is latched to 5103 Completion of an 8 bit transfer automatically stops operation of SIO3 and sets an interrupt request flag CSIIF3 Figure 15 3 3 Wire Serial I O Mode Timing SCK3 1 2 3 4 5 6 7 8 ss Yr De p ow ps p or oo I 503 007 X DOs DO5 DO4 DO2 pO DOO CSIIF3 Transfer completion Transfer starts in synchronized with the falling edge of SCK3 Transfer start A serial transfer starts when the following two conditions have been satisfied and transfer data has been set to or read from serial shift register 3 SIO3 SIO3 operation control bit CSIE3 1 After an 8 bit serial transfer the internal serial clock is either stopped or SCK3 is set to high level Transmit or transmit receive mode When CSIE3 1 and MODES 0 transfer starts when writing to SIO3 Receive only mode When CSIE3 1 and MODES 1 transfer starts when reading from SIO3 Caution After data has been written to SIO3 transfer will not start even if the CSIE3 bit value is set to 1 Completion of an 8 bit transfer automatically stops the serial transfer operation and sets an interrupt request flag CSIIF3 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 16 LCD CONTROLLER DRIVER 16 1 LCD Controller Driver Functions The functions of the LCD controller driver incorporated in the uPD780852 Subseries are shown below 1 Automatic output of segment signals and common sig
228. of MCMPnm x cycle of MCNT count clock PWM duty x 10096 255 x cycle of MCNT count clock _ Set value of MCMPnm x 100 255 Cautions 1 0 and MCMPn1 cannot be read or written by a 16 bit access instruction 2 0 and MCMPni are in master slave configuration and MCNT is compared with a slave register The PWM pulse is not output until the first overflow occurs after the counting operation has been started because the compare data is not transferred to the slave Preliminary User s Manual U14581EJ3VOUMOO 233 CHAPTER 18 METER CONTROLLER DRIVER 18 3 Meter Controller Driver Control Registers The following three types of registers are used to control the meter controller driver Timer mode control register MCNTC e Compare control register n MCMPCn Port mode control register PMC Remark 1 4 1 Timer mode control register MCNTC MONTO is 8 bit register that controls the operation of the free running up counter MONT MONTO is set with an 8 bit memory manipulation instruction RESET input clears MCNTC to 00H Figure 18 3 shows the MCNTC format Figure 18 3 Timer Mode Control Register MCNTC Format Address FF69H After Reset 00H R W Symbol 7 MCNTC PO Po rois ioi Timer Timer Counter Clock Selection Clock fuc Selection a Timer Operation Control 0 Operation stopped timer value is cleared 1 Operation enabled Cautions 1 When rewriting MCNTC
229. ogramming function sessesseeeenennem mene 279 22 3 3 NH Em 280 CHAPTER 23 INSTRUCTION Rn can 281 Preliminary User s Manual U14581EJ3VOUMOO 17 23 1 Legend for Operation List u 282 23 1 1 Operand identifiers and description 282 23 1 2 Description of Operation LLL Ra a u Wu enne nnne nennen nente rns 283 23 1 3 Description of flag operation 283 23 2 Operation List ee eee 284 23 3 Instructions Listed by Addressing 1 u 292 APPENDIX A DEVELOPMENT TOOLS III 297 A 1 Language Processing Software U u u u u u 299 A 2 Flash Memory Writing 15 nennen u u u u J J T 300 DEBUGGING TOONS c 301 Hardware ee cree ced 301 3 2 SOfIWare u uuu 302 APPENDIX B EMBEDDED SOFTWARE III IIIa aac cred awas 305 APPENDIX C REGISTER INDEX a 307 C 1 Register In
230. on OP code addr16 lower addr16 upper Memory 68 Preliminary Users Manual U14581EJ3VOUMOO CHAPTER 3 CPU ARCHITECTURE 3 4 4 Short direct addressing Function The memory to be manipulated in the fixed space is directly addressed with 8 bit data in an instruction word This addressing is applied to the 256 byte space FE20H to FF1FH An internal high speed RAM and a special function register SFR are mapped at FE20H to FEFFH and to FF1FH respectively If the SFR area FFOOH to FF1FH where short direct addressing is applied ports which are frequently accessed in a program and a compare register of the timer event counter and a capture register of the timer event counter are mapped and these SFRs can be manipulated with a small number of bytes and clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is set to 0 When it is at OOH to 1FH bit 8 is set to 1 Operand format saddr Label or FE20H to FF1FH immediate data saddrp Label or FE20H to FF1FH immediate data even address only Description example MOV 50H when setting saddr to and immediate data to 50H Operation code 000100041 OP code 00110000 30H saddr offset 01010000 50H immediate data Operation OP code saddr offset Short direct memory Effective address When 8 bit immediate data is 20H to FFH a 0 When 8 bit immedi
231. on Control register Port mode register PMm m 0 2 to 6 8 9 Pull up resistor option register PUO Port Total 56 5 inputs 16 outputs 35 inputs outputs Pull up resistor Total 8 software specifiable 8 4 2 1 Port 0 Port 0 is an 8 bit input output port with output latch POO to P07 pins can specify the input mode output mode in 1 bit units with the port mode register 0 PMO On chip pull up resistor can be usedin 1 bit units with a pull up resistor option register 0 PUO Alternate functions include external interrupt request input serial interface data input output and clock input output RESET input sets port 0 to input mode Figure 4 2 shows a block diagram of port 0 Cautions 1 Because port 0 also serves for external interrupt request input when the port function output mode is specified and the output level is changed the interrupt request flag is set Thus when the output mode is used set the interrupt mask flag to 1 2 When port 0 is used as the serial interface pins an and output latches must be set according to the functions to be used For an explanation of how to set these latches refer to the description of the format of the serial operation mode register Preliminary User s Manual U14581EJ3V0UMOO 77 CHAPTER 4 PORT FUNCTIONS WReuo PUOO to PUO7 D gt RD Figure 4 2 P00 to P07 Block Diagram WRP gt Ponr Internal bus WRem PU PM
232. on output mode is specified and the output level is changed the interrupt request flag is set When the output mode is used therefore the interrupt mask flag should be set to 1 beforehand 3 Ports 2 and 3 that can be also used as meter driving PWM signal output pins go into a high impedance state when 1 is set to PM2x and PM3x respectively Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 4 PORT FUNCTIONS Figure 4 11 Port Mode Register PMO PM4 to PM6 PM8 PM9 Format Address FF20H After Reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM0 Address FF24H After Reset FFH R W Symbol 7 6 5 4 3 2 1 0 Address FF25H After Reset FFH R W Symbol T 6 5 4 3 2 1 0 1 1 1 PM5 PM54 5 52 51 50 or i 1 Me Puss PMs2 51 Pmso Address FF26H After Reset FFH R W 7 6 5 4 3 2 1 0 Address FF28H After Reset FFH R W Symbol PM6 Symbol 7 6 5 4 3 2 1 0 PM8 Address FF29H After Reset FFH R W Symbol 7 6 5 4 3 2 1 0 Pmn Pin Input Output Mode Selection m 0 4 to 6 8 9 n 0 to 7 0 Output Mode Output buffer 1 Input Mode Output buffer off Figure 4 12 Port Mode Register PM2 PM3 Format Address FF22H After Reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM2 Address FF23H After Reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM Pmn Pin Input Output Mode Selection m 2 3 n 0 to 7 0 Output Mode Output buffer on 1 High impedance state
233. ons 1 The WDTIF flag is R W enabled only when the watchdog timer is used as the interval timer If watchdog timer mode 1 is used set the WDTIF flag to O 2 Bits 3 to 7 of IF1L must be set to 0 246 Preliminary User s Manual U14581EJ3V0UM00 CHAPTER 19 INTERRUPT FUNCTIONS 2 Interrupt mask flag registers MKOL MKOH MK1L The interrupt mask flags are used to enable disable the corresponding maskable interrupt service MKOL and MK1L are set with a 1 bit or 8 bit memory manipulation instruction When MKOL and MKOH are combined to form a 16 bit register MKO they are set with a 16 bit memory manipulation instruction RESET input sets these registers to FFH Figure 19 3 Interrupt Mask Flag Register MKOL MKOH MK1L Format Address FFE4H After Reset FFH R W Symbol 7 6 5 4 3 2 1 0 Address FFE5H After Reset FFH R W Symbol 7 6 5 4 3 2 1 0 Address FFE6H After Reset FFH R W 7 6 5 4 3 2 1 0 Symbol MK1L 0 Interrupt servicing enabled 1 Interrupt servicing disabled Cautions 1 Ifthe watchdog timer is used in watchdog timer mode 1 the contents of the WDTMK flag become undefined when read 2 Because port 0 pins have an alternate function as external interrupt request input when the output
234. ons are used Non maskable interrupt This interrupt is acknowledged unconditionally even in the interrupt disabled state It does not undergo priority control and is given top priority over all other interrupt requests A standby release signal is generated One interrupt request from the watchdog timer is incorporated as a non maskable interrupt Maskable interrupts These interrupts undergo mask control Maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specify flag registers PROL PROH PR1L High priority interrupts can be issued even if there are low priority interrupts If two or more interrupts with the same priority are simultaneously generated each interrupt has a predetermined priority see Table 19 1 A standby release signal is generated Three external interrupt requests and sixteen internal interrupt requests are incorporated as maskable interrupts Software interrupt This is a vectored interrupt to be generated by executing the BRK instruction It is acknowledged even in the interrupt disabled state The software interrupt does not undergo interrupt priority control 2 Interrupt Sources and Configuration A total of 21 interrupt sources exist among non maskable maskable and software interrupts see Table 19 1 Preliminary User s Manual U14581EJ3VOUMOO 241 CHAPTER 19 INTERRUPT FUNCTIONS Table 19 1 Interrupt Source List Note 1 I
235. op Port function P53 Port function P54 UART mode Serial function RxD Port function P54 receive only UART mode Port function P53 Serial function TxD transmit only UART mode Serial function RxD Serial function TxD transmit and receive Cautions 1 Do not switch the operation mode until after the current serial transmit receive operation has stopped 2 Bit 0 must be set to 0 13 4 2 Asynchronous serial interface UART mode This mode enables full duplex operation wherein one byte of data is transmitted or received after the start bit The on chip dedicated UART baud rate generator enables communications using a wide range of selectable baud rates The dedicated UART baud rate generator can also be used to generate a MIDI standard baud rate 31 25 kbps 1 Register settings UART mode is set with the asynchronous serial interface mode register ASIM asynchronous serial interface status register ASIS and the baud rate generator control register BRGC Preliminary User s Manual U14581EJ3VOUMOO 175 CHAPTER 13 SERIAL INTERFACE UART a Asynchronous serial interface mode register ASIM ASIM is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears ASIM to 00H Caution In UART mode setthe port mode register PM5X as follows Besides that set all output latches to 0 When receiving Set P53 RxD to the input mode PM53 1 When transmitting Set P54 TxD
236. operations a Data format Figure 13 6 shows the transmit receive data format Figure 13 6 Format of Transmit Receive Data in Asynchronous Serial Interface 1 data frame Start D1 D2 ps D7 Parity Stop bit bit bit Character bits One data frame consists of the following each bit Start bit 1 bit e Character bits 7 bits or 8 bits Parity bit Even parity odd parity zero parity or no parity Stop bit s 1 bit or 2 bits The asynchronous serial interface mode register ASIM is used to set the character bit length parity selection and stop bit length within each data frame When 7 bits is selected as the number of character bits only the lower 7 bits bits 0 to 6 are valid so that during a transmission the highest bit bit 7 is ignored and during reception the highest bit bit 7 must be set to 0 The asynchronous serial interface mode register ASIM and the baud rate generator control register BRGC are used to set the serial transfer rate If a receive error occurs information about the receive error can be recognized by reading the asynchronous serial interface status register ASIS Preliminary User s Manual U14581EJ3V0UM00 181 CHAPTER 13 SERIAL INTERFACE UART b Parity types and operations 182 The parity bit is used to detect bit errors in transfer data Usually the same type of parity bit is used by the transmitting and
237. or Output Operation Timing Timer Comparator 1 coincidence SGO Preliminary User s Manual U14581EJ3V0UM00 229 MEMO 230 Preliminary User s Manual U14581EJ3VOUMOO CHAPTER 18 METER CONTROLLER DRIVER 18 1 Meter Controller Driver Functions The meter controller driver is a function to drive a stepping motor for external meter control or cross coil Can set pulse width with a precision of 8 bits Can set pulse width with a precision of 8 1 bits with 1 bit addition function Can drive up to four 360 type meters Figure 18 1 shows the block diagram of the meter controller driver and Figure 18 2 shows 1 bit addition circuit block diagram Figure 18 1 Meter Controller Driver Block Diagram Internal bus Timer mode control register MCNTC Port mode control register PMC 8 bit timer register fx 2 MODn ENn 5 5 1 sin Q Output controller SMn2 si 1 bit addition circuitt n2 sin MODn ENn Q Output controller 1 bit addition circuit R ADBnO DIRn1 DIRnO Compare control register n MCMPCn Internal bus Remark 1 to 4 Preliminary User s Manual U14581EJ3V0UMOO 231 CHAPTER 18 METER CONTROLLER DRIVER Figure 18 2 1 Bit Addition Circuit Block Diagram Compare register MCMPnm Selector Compare control register MCMPCn Intern
238. or both edges by means of bits 2 and 3 500 and ES01 of prescaler mode register PRMO For TIOO pin valid edge detection sampling is performed at the count clock selected by PRMO and a capture operation is only performed when a valid level is detected twice thus eliminating noise with a short pulse width Figure 6 6 Configuration Diagram for Pulse Width Measurement by Free Running Counter 16 bit timer register TMO INTOVF 26 TIOO E 16 bit capture register 00 CROO NTTMOO Internal bus Figure 6 7 Pulse Width Measurement Operation Timing by Free Running Counter and One Capture Register with Both Edges Specified 23 fx 24 25 i TUL TUL Two count qegesp pos Yes 100 pin deo input mvo INTOVF 108 Preliminary User s Manual U14581EJ3VOUMOO CHAPTER 6 16 BIT TIMER 0 TMO 2 Measurement of three pulse widths with free running counter The 16 bit timer register TMO allows simultaneous measurement of the pulse widths of the three signals input to the 00 40 to 02 42 pins When the edge specified by bits 2 and 3 500 and 501 of prescaler mode register PRMO is input to the 00 40 pin the value of is taken into 16 bit capture register 00 CROO and an external interrupt request signal INTTMOO is set Als
239. output line 502 and a serial input line SI2 Since simultaneous transmit and receive operations are enabled in the 3 wire serial I O mode the processing time for data transfers is reduced The first bit in the 8 bit data in serial transfer is fixed as the MSB This data contains a 1 byte receive buffer and can be received successively The serial clock and the data phase polarity can be selected The 3 wire serial I O mode is useful for connection to a peripheral I O device that includes a clocked serial interface a display controller etc Figure 14 1 shows the serial interface SIO2 block diagram Figure 14 1 Serial Interface SIO2 Block Diagram Internal bus Serial receive buffer status register SRBS2 SDOF Receive buffer register SIRB2 SI2 P05 Serial I O shift register 2 S102 Serial clock counter SCK2 P03 502 04 lt Interrupt request INTCSI2 signal generator Serial fx 29 clock Selector fx 2 controller fx 2 21 SCL2 Serial operation mode register 2 CSIM2 Internal bus 0 Preliminary User s Manual U14581EJ3VOUMOO 187 CHAPTER 14 SERIAL INTERFACE SIO2 14 2 Serial Interface Configuration The serial interface SIO2 consists of the following hardware 1 2 188 Table 14 1 Serial Interface SIO2 Configuration Configuration Registers Serial shift register 2 5102
240. ove documents are subject to change without prior notice Be sure to use the latest version of a document when starting design Preliminary User s Manual U14581EJ3VO0UMOO 11 MEMO 12 Preliminary Users Manual U14581EJ3VOUMO0O CONTENTS ea ialz uU E 27 1 1 F eat rp8sS uuu s 27 DAESJUMDIIM 27 1 3 Ordering Information ccc cc II nr ann ener eta Las En vein usc 28 TA Q a lity Grade Me 28 1 5 Pin Configuration Top View U U u u u u uu u u u 29 1 6 78K 0 Series Product Development l l l 31 1 7 Block DI8Qram E 33 1 8 Oulline of FuncllOnh u u yx no De So yx 34 CHAPTER 2 PIN FUNCTION 2 2 aE 35 743 src 35 2 2 Description of Pin Functions U 38 22 1 0 eR 38 2 2 2 JP TO TO P T4 POTE T inicios siete eorr iere teen Cerere 38 2 2 3 IPo0 16 P2o7 POM 39 2 2 4 S uu u u uuu
241. ows Besides that set all output latches to 0 When serial clock output Master transmit or master receive Set P50 SCK3 to the output mode PM50 0 When serial clock input Slave transmit or slave receive Set P50 to the input mode 50 1 When transmit or transmit receive mode Set P51 SO3 to the output mode PM51 0 When receive mode Set P52 SI3 to the input mode PM52 1 Address FF84H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 SIOS Operation Enable Disable Specification Shift Register Operation Operation disabled Operation enabled Transfer Operation Mode Flag Operation Mode Transmit or transmit receive mode Receive only mode Clock Selection External clock input fx 22 fx 28 fx 24 Caution Bits 3 to 6 must be set to 0 Remark fx Main system clock oscillation frequency Preliminary User s Manual U14581EJ3VOUMOO 205 CHAPTER 15 SERIAL INTERFACE SIO3 2 3 206 Communication operations In the 3 wire serial I O mode data is transmitted and received in 8 bit units Each bit of data is transmitted or received in synchronization with the serial clock The serial I O shift register 3 5103 is shifted in synchronization with the falling edge of the serial clock Transmission data is held in the 503 latch and is output from the 503 Data that is received via the SI3 pin in synchronization with the rising edge of the serial cl
242. peration 135 9 1 Watch Timer Block Dia Grain torii quiere t etc ike Abts 137 9 2 Watch Timer Mode Control Register WTM Format a 139 9 3 Watch Timer Interval Timer Operation Timing a 141 10 1 Watchdog Timer Block Diagrami 143 10 2 Watchdog Timer Clock Select Register WDCS Format seen 145 10 3 Watchdog Timer Mode Register WDTM Format 146 11 1 Clock Output Controller Block Diagram eene 149 11 2 Clock Output Selection Register CKS Format sse 150 11 3 Port Mode Register 6 PM6 4 4 ennemi eterni nnne 151 11 4 Remote Control Output Application Example sesenta 152 12 1 A D Converter Block DIagFamm u u L U L 154 12 2 Power Fail Detection Function Block 154 12 3 A D Converter Mode Register ADM1 Format sessi 157 12 4 Analog Input Channel Specification Register ADS1 Format 158 12 5 Power Fail Compare Mode Register 159 20 Preliminary User s Manual U14581EJ3V0UMOO LIST OF FIGURES 3 5 Figure No Title Page 12 6 Power Fail Compare Threshold Value Register PFT
243. priority flag MK Interrupt mask flag PR Priority specify flag 244 Preliminary User s Manual U14581EJ3V0UM00 CHAPTER 19 INTERRUPT FUNCTIONS 19 3 Interrupt Function Control Registers The following six types of registers are used to control the interrupt functions Interrupt request flag register IFOL IFOH IF1L Interrupt mask flag register MKOL MK1L Priority specify flag register PROL PROH PR1L External interrupt rising edge enable register EGP External interrupt falling edge enable register EGN Prescaler mode register PRMO Program status word PSW Table 19 2 gives a list of interrupt request flags interrupt mask flags and priority specify flags corresponding to interrupt request sources Interrupt Source INTWDT INTAD INTOVF INTTMOO INTTMO1 INTTMO2 INTPO INTP1 Table 19 2 Flags Corresponding to Interrupt Request Sources Interrupt Request Flag WDTIF ADIF OVFIF TMIFOO TMIFO1 TMIFO2 PIFO PIF1 Register Interrupt Mask Flag Register WDTMK ADMK OVFMK TMMKOO TMMKO1 TMMK02 PMKO PMK1 Priority Specify Flag Register WDTPR ADPR OVFPR 00 TMPRO1 TMPR02 PPRO PPR1 INTP2 INTCSI3 INTSER INTSR INTST INTTM1 INTTM2 INTTMS PIF2 CSIIF3 SERIF SRIF STIF TMIF1 TMIF2 PMK2 CSIMK3 SERMK SRMK STMK TMMK1 TMMK2 TMMK3 PPR2 CSIPR3 SERPR SRPR STPR TMPR1 TMPR2 TMPR3 INTCSI2 INTWTI INTWT CSIIF2
244. progress as this may reduce the conversion resolution Also if digital pulses are applied to a pin adjacent to the pin in the process of A D conversion the expected A D conversion value may not be obtainable due to coupling noise Therefore avoid applying pulses to pins adjacent to the pin undergoing A D conversion AVner pin input impedance A series resistor string of approximately 21 is connected between the AVner and the AVss pin Therefore if the output impedance of the reference voltage is high this will result in parallel connection to the series resistor string between the AVner pin and the AVss pin and there will be a large reference voltage error Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 12 A D CONVERTER 8 Interrupt request flag ADIF The interrupt request flag ADIF is not cleared even if the analog input channel specification register ADS1 is changed Caution is therefore required since if a change of analog input pin is performed during A D conversion the A D conversion result and conversion end interrupt request flag for the pre change analog input may be set just before the ADS1 rewrite and when ADIF is read immediately after the ADS1 rewrite ADIF may be set despite the fact that the A D conversion for the post change analog input has not ended When the A D conversion is stopped and then resumed clear ADIF before the A D conversion operation is resumed Figure 12 12 A D Conversion End
245. pt request is acknowledged after termination of the non maskable interrupt servicing program execution Figures 19 8 19 9 and 19 10 show the flowchart of the non maskable interrupt request generation through acknowledge acknowledge timing of non maskable interrupt request and acknowledge operation at multiple non maskable interrupt request generation respectively 252 Preliminary User s Manual U14581EJ3V0UM00 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19 8 Non Maskable Interrupt Request Generation to Acknowledge Flowchart WDTM4 1 with watchdog timer mode selected Interval timer Overflow in WDT WDTM3 0 with non maskable interrupt selected Reset processing Interrupt request generation WDT interrupt Yes servicing Interrupt request held pending Interrupt control register accessed Yes Start of interrupt servicing WDTM Watchdog timer mode register WDT Watchdog timer Figure 19 9 Non Maskable Interrupt Request Acknowledge Timing PSW and P l ici uw Si mu WDTIF h Interrupt request generated during this interval is acknowledged at WDTIF Watchdog timer interrupt request flag Preliminary User s Manual U14581EJ3VOUMOO 253 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19 10 Non Maskable Interrupt Request Acknowledge Operation a If a non maskable interrupt request is generated execution Main ro
246. put buffer on Input mode output buffer off Remark nz0to4 Preliminary User s Manual U14581EJ3V0UM00 127 CHAPTER 8 8 BIT TIMER EVENT COUNTERS 2 TM2 AND 3 8 4 8 Bit Timer Event Counters 2 TM2 and 3 Operations 8 4 1 8 bit interval timer operation The 8 bit timer event counters operate as interval timers which generate interrupt requests repeatedly at intervals of the count value preset to 8 bit compare register n CRn When the count values of the 8 bit counter n TMn match the values set to CRn counting continues with the TMn values cleared to 0 and the interrupt request signal INTTMn is generated Count clock of the 8 bit timer register n TMn be selected with the timer clock select register n TCLn Setting 1 Setthe registers TCLn Select count clock CRn Compare value TMOn Select clear and start mode by match of TMn and CRn TMCn 0000xxx0B x don t care 2 After TCEn 1 is set count operation starts 3 If the values of TMn and CRn match the INTTMn is generated and is cleared to OOH 4 generates repeatedly at the same interval Set TCEn to 0 to stop count operation Remark n 2 3 Figure 8 7 Interval Timer Operation Timings 1 3 a Basic operation e rn goed tee CELE n TMn count value eB CD TEE Start count Clear Clear CRn N N N N TCEn INTTMn 00000000 LR LR
247. r availability and additional information No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC NEC assumes no responsibility for any errors that may appear in this document NEC does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC or others Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these circuits software and information in the design of customer s equipment shall be done under the full responsibility of customer NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information While NEC endeavours to enhance the quality reliability and safety of NEC semiconductor products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC semiconductor products
248. r to 00H and clears hardware to 0 MCMPnoOis a register that supports read write only for 8 bit access instructions MCMPn0 continuously compares its value with the MCNT value When the above two values match a match signal of the sin side of meter n is generated Compare register n1 MCMPn1 MCMPn1 is an 8 bit register that can rewrite compare values through specification of bit 4 TENn of the compare control register n MCMPCn RESET input clears this register to 00H and clears hardware to 0 MCMPn1 is a register that supports read write only for 8 bit access instructions MCMPn1 continuously compares its value with the MCNT value When the above two values match a match signal of the cos side of meter n is generated 1 bit addition circuit The 1 bit addition circuit repeats 1 bit addition non addition to PWM output alternately upon MCNT overflow output and enables the state of PWM output between current compare value and the next compare value This circuit is controlled by bits 2 and ADBnO and ADBn1 of the MCMPCn register Output controller The output controller consists of a P ch and N ch drivers and can drive a meter in H bridge configuration by connecting a coil When a meter is driven in half bridge configuration the unused pins can be used as normal output port pins The relation of the duty factor of the PWM signal output from the SMnm pin is indicated by the following expression n 1 to 4 m 0 1 Set value
249. ranted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document
250. receive data Framing error Stop bit was not detected Overrun error RxD input Reception of the next data was completed before data was read from the receive buffer register Figure 13 9 Receive Error Timing INTSR Nete INTSER when framing overrun error occurs INTSER when parity error occurs Note f reception error occurs when ISRM bit is set to 1 INTSR does not occur Cautions 1 The contents of asynchronous serial interface status register ASIS are reset to 0 when the receive buffer register is read or when the next data is received To obtain information about the error be sure to read the contents of ASIS before reading RXB Be sure to read the contents of the receive buffer register RXB even when a receive error has occurred Overrunerrors will occur during the next data receive operations and the receive error status will remain until the contents of RXB are read Preliminary User s Manual U14581EJ3VOUMOO 185 MEMO 186 Preliminary User s Manual U14581EJ3VOUMOO CHAPTER 14 SERIAL INTERFACE SIO2 14 1 Serial Interface Functions The serial interface SIO2 has the following two modes 1 Operation stop mode This mode is used when serial transfers are not performed For details see 14 4 1 Operation stop mode 2 3 wire serial I O mode fixed as MSB first This is an 8 bit data transfer mode using three lines a serial clock line 5 2 a serial
251. receive data input to the SI2 pin is latched to 5102 at the rising edge of SCK2 if CLPH 0 and CLPO 0 Completion of an 8 bit transfer automatically stops operation of SIO2 and sets a serial transfer completion flag Figure 14 6 Operation Timing When CLPH Is Set to 0 Serial output data 55H serial input data AAH CLPO 0 CLPO 1 Start trigger Write SIO2 55H operation timing i Serial output data timing SIRB2 INTCSI2 interrupt request generated at rising edge 512 Preliminary User s Manual U14581EJ3V0UMOO 197 CHAPTER 14 SERIAL INTERFACE SIO2 c Transfer format when CLPH 1 Figure 14 7 shows the operation timing when CLPH 1 Two waves of SCK2 when CLPO 1 and when CLPO 0 are shown in the figure Data is transmitted or received in 8 bit units Each bit of data is transmitted or received in synchronization with the serial clock 5102 is shifted at the falling edge of SCK2 if CLPH 1 and CLPO 0 If CLPH 1 and CLPO 1 SIO2 is shifted at the rising edge of SCK2 The transmit data is held by the SO2 latch and output from the SO2 pin The receive data input to the SI2 pin is latched to SIO2 at the falling edge of SCK2 if CLPH 1 and CLOP 0 Completion of an 8 bit transfer automatically stops operation of SIO2 and sets a serial transfer completion flag Figure 14 7 Operation Timing When CLPH Is Set to 1 Serial output data 55H serial input data AAH 029
252. receiving sides When odd parity or even parity is set errors in the parity bit the odd number bit can be detected When zero parity or no parity is set errors are not detected i Even parity During transmission The number of bits in transmit data that includes a parity bit is controlled so that there are an even number of 1 bits The value of the parity bit is as follows If the transmit data contains an odd number of 1 bits the parity bit value is 1 If the transmit data contains an even number of 1 bits the parity bit value is 0 During reception The number of 1 bits is counted among the receive data that include a parity bit and a parity error occurs when the result is an odd number ii Odd parity During transmission The number of bits in transmit data that includes a parity bit is controlled so that there is an odd number of 1 bits The value of the parity bit is as follows If the transmit data contains an odd number of 1 bits the parity bit value is 0 If the transmit data contains an even number of 1 bits the parity bit value is 1 During reception The number of 1 bits is counted among the receive data that include a parity bit and a parity error occurs when the result is an even number iii Zero parity During transmission the parity bit is set to O regardless of the transmit data During reception the parity bit is not checked T
253. register pair DE The contents of the memory addressed are transferred Preliminary User s Manual U14581EJ3VOUMOO 71 CHAPTER 3 CPU ARCHITECTURE 3 4 7 Based addressing Function 8 bit immediate data is added as offset data to the contents of the base register that is the HL register pair in an instruction word of the register bank specified with the register bank select flags RBSO and RBS1 and the sum is used to address the memory Addition is performed by expanding the offset data as a positive number to 16 bits A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format mw Description example MOV A HL 10H when setting byte to 10H Operation code 10101110 00010000 3 4 8 Based indexed addressing Function The B or C register contents specified in an instruction word are added to the contents of the base register that is the HL register pair in an instruction word of the register bank specified with the register bank select flags RBSO and RBS1 and the sum is used to address the memory Addition is performed by expanding the B or C register contents as a positive number to 16 bits A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format NEM HL B HL C Description example In the case of MOV A HL B Operation code 10101011 72 Preliminary User s Manu
254. ronous serial interface serial data input output pins 2 2 7 P60 P61 Port 6 These pins constitute a 2 bit input output port In addition they also function as clock output sound generator signal output and prescaler signal output pins The following operation modes can be specified in 1 bit units 1 Port mode In this mode P60 and P61 function as a 2 bit input output port They can be set in the input or output port in 1 bit units with the port mode register 6 PM6 2 Control mode In this mode P60 and P61 function as clock output sound generator signal output and prescaler signal output pins a PCL Clock output pin b SGO Sound generator with amplitude signal output pin c TPO Prescaler signal output pin of the 16 bit timer 40 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 2 PIN FUNCTION 2 2 8 P81 to P87 Port 8 These pins constitute a 7 bit input output port In addition they also function as segment signal output pins of the LCD controller driver The following operation modes can be specified in 1 bit units 1 Port mode In this mode P81 to P87 function as a 7 bit input output port They can be set in the input or output port in 1 bit units with the port mode register 8 8 2 Control mode In this mode P81 to P87 function as segment signal output pins S13 to S19 of the LCD controller driver 2 2 9 P90 to P97 Port 9 These pins constitute an 8 bit input output port In addi
255. rrupt servicing and Figure 19 14 shows multiple interrupt examples Table 19 4 Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing Multiple Interrupt Request Maskable Interrupt Request Non Maskable Interrupt Request xxPR 0 xxPR 1 Interrupt Being Serviced IE 1 IE 1 Non maskable interrupt Maskable interrupt Software interrupt Remarks 1 O Multiple interrupt enable 2 x Multiple interrupt disable 3 ISP and IE are flags contained in PSW ISP 20 Aninterrupt with higher priority is being serviced ISP 1 Nointerrupt request has been acknowledged or an interrupt with a lower priority is being serviced IE 2 0 Interrupt request acknowledge is disabled IE 1 Interrupt request acknowledge is enabled 4 xxPR is a flag contained in PROL PROH PR1L and PR1H xxPR 0 Higher priority level xxPR 1 Lower priority level 258 Preliminary Users Manual U14581EJ3VOUMOO CHAPTER 19 INTERRUPT FUNCTIONS Figure 19 14 Multiple Interrupt Examples 1 2 Example 1 Multiple interrupts occur twice Main processing INTxx servicing INTyy servicing INTzz servicing 1 RETI RETI During servicing of interrupt INTxx two interrupt requests INTyy and INTzz are acknowledged and multiple interrupt servicing takes place Before each interrupt request is acknowledged the El instruction must always be issued to enable interrupt
256. s 0780851 LPD78F0852 to set the same memory map as uPD780852 A Although the initial value of this register is OCH set this register to OBH Preliminary User s Manual U14581EJ3VOUM00 CHAPTER 3 CPU ARCHITECTURE 3 3 Instruction Address Addressing An instruction address is determined by program counter PC contents and is normally incremented 1 for each byte automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed When a branch instruction is executed the branch destination information is set to the PC and branched by the following addressing For details of instructions refer to 78K 0 SERIES USER S MANUAL Instructions U12326E 3 3 1 Relative addressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the program counter PC and branched The displacement value is treated as signed two s complement data 128 to 127 and bit 7 becomes a sign bit In other words relative addressing consists in relative branching from the start address of the following instruction to the 128 to 127 range This function is carried out when the BR addr16 instruction or a conditional branch instruction is executed Operation u PC indicates the start address after the BR instruction 15 8 7 6 0 x jdisp8
257. s COMO to COM3 IC INTPO to INTP2 POO to 07 P10 to P14 P20 to P27 P30 to P37 P40 to P44 P50 to P54 P60 P61 P81 to P87 P90 to P97 PCL RESET RxD SO to S19 Analog Input Analog Reference Voltage Analog Ground Common Output SCK2 SCK3 SGO 512 513 Serial Clock Sound Generator Output Serial Input SM11 to SM14 SM21 to SM24 SM31 to 5 34 SM41 to SM44 Internally Connected External Interrupt Input Porto Port Port2 Port3 Port4 Port5 Port6 Port8 Port9 Programmable Clock Output Reset Receive Data Segment Output SMV pp SMVss SO2 SO3 TIOO to TIO2 TIO2 TIO3 TPO TxD Vppo VPP VROUT Vsso Vssi X1 X2 Preliminary User s Manual U14581EJ3VO0UMOO Meter Output Meter Controller Power Supply Meter Controller Ground Serial Output Timer Input Timer Output Event Counter Input Prescaler Output Transmit Data Power Supply LCD Power Supply Programming Power Supply Power Supply Regulator Output Ground Crystal Main System Clock CHAPTER 1 OUTLINE 1 6 78K 0 Series Product Development These products are a further development in the 78K 0 Series The designations appearing inside the boxes are subseries names 78K 0 Series 100 pin uPD780308 uPD780308Y LO J Products in mass production Y subseries products are compatible with I C bus Control 100 pin 78075 EMI noise reduce
258. s addr1 1 0800H to OFFFH Immediate data or labels addr5 0040H to 007FH Immediate data or labels even addresses only word 16 bit immediate data or label byte 8 bit immediate data or label bit 3 bit immediate data or label RBn RBO to RB3 Note Addresses from FFDOH to FFDFH cannot be accessed with these operands Remark For special function register symbols see Table 3 3 Special Function Register List 282 Preliminary User s Manual U14581EJ3VOUMO0 CHAPTER 23 INSTRUCTION SET 23 1 2 Description of Operation column A oo EM BC DE HL PC SP PSW CY AC RBS IE NMIS XH XL A Y addr16 jdisp8 A register 8 bit accumulator X register B register C register D register E register H register L register AX register pair 16 bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer Program status word Carry flag Auxiliary carry flag Zero flag Register bank select flag Interrupt request enable flag Non maskable interrupt servicing flag Memory contents indicated by address or register contents in parentheses Higher 8 bits and lower 8 bits of 16 bit register Logical product AND Logical sum OR Exclusive logical sum exclusive OR Inverted data 16 bit immediate data or label Signed 8 bit data displacement value 23 1 3 Description of flag operation column Blank x Not affecte
259. s Manual U14581EJ3VOUMOO CHAPTER 18 METER CONTROLLER DRIVER 18 4 Meter Controller Driver Operations 18 4 1 Basic operation of free running up counter MCNT The free running up counter MCNT is counted up by the count clock selected by the PCS bit of the timer mode control register MCNTC RESET input clears the value of MCNT The counting operation is enabled or disabled by the PCE bit of MCNTC Figure 18 6 shows the timing from count start to restart Figure 18 6 Restart Timing after Count Stop Count Start Count Stop Count Start j CLK e L e e Ke Y mmm _ Count start Count stop Count start Remark N 00H to FFH 18 4 2 To update PWM data Confirm that bit 4 TENn of MCMPOn is 0 and then set 8 bit PWM data to MCMPn1 and MCMPn0O and bits 2 and 3 ADBn1 and ADBnO of MCMPOn and at the same time set TENn to 1 The data will be automatically transferred to the slave latch when the timer overflows and the PWM data becomes valid At the same time TENn is automatically cleared to 0 Remark 1 4 Preliminary User s Manual U14581EJ3V0UMOO 237 CHAPTER 18 METER CONTROLLER DRIVER 18 4 3 1 bit addition circuit operation Figure 18 7 Timing in 1 Bit Addition Circuit Operation FFH MONT value OVF overflow Match signal of expected value N i PWM output of i expected value N _ J Ef LF LJ 1 bit non addition PWM output of i expected valu
260. s Serial Interface Status Register ASIS Format Address FF86H After Reset 00H R Symbol 7 6 5 4 3 2 1 0 7 RENE No parity error Parity error Transmit data parity does not match fe Framing Error Flag No framing error Framing error Note 1 Stop bit not detected Overrun Error Flag No overrun error Overrun error Note 2 Next receive operation was completed before data was read from receive buffer register Notes 1 Even if a stop bit length of two bits has been set to bit 2 SL in the asynchronous serial interface mode register ASIM stop bit detection during a receive operation only applies to a stop bit length of 1 bit 2 Be sure to read the contents of the receive buffer register RXB when an overrun error has occurred Until the contents of RXB are read further overrun errors will occur when receiving data 3 Baud rate generator control register BRGC This register sets the serial clock for UART BRGC is set with an 8 bit memory manipulation instruction RESET input clears BRGC to 00H Figure 13 4 shows the format of BRGC Preliminary User s Manual U14581EJ3VOUMOO 173 CHAPTER 13 SERIAL INTERFACE UART Figure 13 4 Baud Rate Generator Control Register BRGC Format Address FF87H After Reset 00H R W Symbol 6 5 4 3 2 1 0 BRGC 0 TPs2 TPst fx 8 38 MHz 16 17 18 19 20 fsck
261. s serial interface receive completion interrupt Figure 13 8 Asynchronous Serial Interface Receive Completion Interrupt Timing RxD input INTSR Caution sure to read the contents of the receive buffer register even when a receive error has occurred Overrun errors will occur during the next data receive operations and the receive error status will remain until the contents of RXB are read Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 13 SERIAL INTERFACE UART e Receive errors Three types of errors can occur during a receive operation parity error framing error or overrun error If as the result of data reception an error flag is set to the asynchronous serial interface status register ASIS areceive error interrupt INTSER will occur Receive error interrupts are generated before receive interrupt requests INTSR Table 13 4 lists the causes behind receive errors As part of receive error interrupt servicing INTSER the contents of ASIS can be read to determine which type of error occurred during the receive operation see Table 13 4 and Figure 13 9 The contents of ASIS are reset to 0 when the receive buffer register RXB is read or when the next data is received if the next data contains an error another error flag will be set Parity error Table 13 4 Causes of Receive Errors Receive Error ASIS Value Parity specified during transmission does not match parity of
262. se Reference U10181J U10181E SM78K Series System Simulator External Part User Open U10092J U10092E Interface Specifications ID78KO Integrated Debugger EWS Base Reference U11151J ID78KO Integrated Debugger Windows Base Guide U11649J U11649E ID78K0 Integrated Debugger PC Base Reference U11539J U11539E Related documents for embedded software User s Manual Document No Document Name Japanese English 78K 0 Series Real Time OS Basics U11537J U11537E Installation U11536J U11536E 78K 0 Series OS 78 0 Basics U12257J U12257E Caution The above documents are subject to change without prior notice Be sure to use the latest version of a document when starting design 10 Preliminary User s Manual 1 14581 3 00 00 Other related documents Document Name SEMICONDUCTOR SELECTION GUIDE Products amp Packages CD ROM Document No Japanese X13769X English Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Device C11531J C11531E NEC Semiconductor Device Reliability Quality Control System C10983J C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge ESD C11892J C11892bE Semiconductor Device Quality Control Reliability Handbook U12769J Guide for Products Related to Micro Computer Other Companies U11416J Caution The ab
263. set to 0 is written to ADM1 during A D conversion operation the A D conversion operation stops immediately Power fail detection function when PFEN 1 When bit 7 ADCS1 of the A D converter mode register ADM1 and bit 7 PFEN of the power fail compare mode register PFM are setto 1 A D conversion of the voltage applied to the analog input pin specified with the analog input channel specification register ADS1 starts Upon the end ofthe A D conversion the conversion result is stored in the A D conversion result register ADCR1 compared with the value of the power fail compare threshold value register PFT and INTAD is generated under the condition specified by the PFCM flag of the PFM register Caution Whenexecuting power fail comparison the interrupt request signal INTAD is not generated on completion of the first conversion after ADCS1 has been set to 1 INTAD is valid from completion of the second conversion Preliminary Users Manual U14581EJ3VOUMOO 163 CHAPTER 12 A D CONVERTER Figure 12 9 A D Conversion ADM rewrite ADCS1 1 ADS1 rewrite ADCS1 0 A D conversion Conversion suspended Stop Conversion results are not stored INTAD PFEN 0 INTAD PFEN 1 t First conversion Condition satisfied Remarks 1 0 1 4 2 m O 1 4 164 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 12 A D CONVERTER 12 5 A D Converter Cautions 1 2 3
264. t Address FF89H After Reset 00H W Symbol 7 6 5 4 3 2 1 0 o o o o o o o 0 Disabled 1 Enabled when power fail detection function is used Cautions 1 DAM1 is a special register that must be set when debugging is performed with an in circuit emulator Even if this register is used the operation of the PD780852 Subseries is not affected However delete the instruction that manipulates this register from the program at the final stage of debugging 2 Bits 7 to 1 must be set to 0 A D converter of IE 780852 NS EM4 A D converter of the IE 780852 NS EM4 may not satisfy the rating of the first A D conversion value right after A D conversion has been started The above applies only to the IE 780852 NS EM4 and does not affect the operation of the 0780852 Subseries Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 13 SERIAL INTERFACE UART 13 1 Serial Interface Functions The serial interface UART has the following two modes 1 Operation stop mode This mode is used when serial transfers are not performed to reduce power consumption For details see 13 4 1 Operation stop mode 2 Asynchronous serial interface UART mode This mode enables full duplex operation wherein one byte of data is transmitted and received after the start bit The on chip dedicated UART baud rate generator enables communications using a wide range of selectable baud rates For details see 13 4 2 Asynchronous ser
265. t clears OSCM to 00H Figure 5 3 Oscillator Mode Register OSCM Format Address FFAOH After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 o o o o o o o HALFOSC Oscillator Mode Selection 0 Normal operation mode 1 Reduced current consumption mode only when operated at fx 4 to 4 19 MHz Cautions 1 This function is available only when the device is operated at fx 4 to 4 19 MHz In other cases be sure not to set 1 to HALFOSC 2 When using in normal operation mode setting OSCM is not necessary 3 Only the first setting of OSCM is effective Remark fx Main system clock oscillation frequency Preliminary User s Manual U14581EJ3V0UMOO 93 CHAPTER 5 CLOCK GENERATOR 5 4 System Clock Oscillator 5 4 1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator standard 8 38 MHz connected to the X1 and X2 pins External clocks can be input to the main system clock oscillator In this case input a clock signal to the X1 pin and an inverted clock signal to the X2 pin Figure 5 4 shows an external circuit of the main system clock oscillator Figure 5 4 External Circuit of Main System Clock Oscillator a Crystal and ceramic oscillation b External clock 2 clock i uPD74HCU04 Crystal resonator or ceramic resonator Cautions 1 Do execute the STOP instruction while a
266. t units Can be set in I O port mode or segment output mode 2 bit units with the LCD display control register LCDC Preliminary User s Manual U14581EJ3VOUMOO 51210 S5 35 CHAPTER 2 PIN FUNCTION 2 Non port pins Pin Name INTPO to INTP2 Input Output Input Function External interrupt request input with specifiable valid edges rising edge falling edge and both rising and falling edges After Reset Input Alternate Function to P02 512 Input Serial interface SIO2 serial data input Input POS 502 Output Serial interface SIO2 serial data output Input P04 SCK2 Input Output Serial interface SIO2 serial clock input output Input P03 Input Serial interface SIOS serial data input Input P52 503 Output Serial interface SIO3 serial data output Input P51 SCK3 Input Output Serial interface SIO3 serial clock input output Input P50 RxD Input Asynchronous serial interface serial data input Input P53 TxD Output Asynchronous serial interface serial data output Input P54 TIOO TIO1 T102 Input Capture trigger signal input to capture register CR00 Capture trigger signal input to capture register CR01 Capture trigger signal input to capture register CR02 Input P40 P41 P42 TIO2 Input Output 8 bit timer TM
267. tch signal to be generated after timer start This is because 8 bit counter 1 TM1 is started asynchronously with the count pulse Figure 7 5 8 Bit Timer 1 TM1 Start Timing Count pulse TMicountvalue 00H 04H Timer start 2 Operation after compare register change during timer count operation If the values after the 8 bit compare register 1 CR1 is changed are smaller than the value of 8 bit timer register 1 TM1 TM1 continues counting overflows and then restarts counting from 0 Thus if the value M after CR1 change is smaller than value N before the change it is necessary to restart the timer after changing CR1 Figure 7 6 Timing after Compare Register Change during Timer Count Operation Caution Always set 1 0 before setting the STOP state Remark gt gt 3 TM1 reading during timer operation When TM1 is read during operation choose a count clock which has a longer high low level wave because 8 bit counter TM1 is stopped temporary 120 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 8 8 BIT TIMER EVENT COUNTERS 2 2 AND 3 8 1 8 Bit Timer Event Counters 2 TM2 and 3 Functions The 8 bit timer event counters 2 TM2 and 3 can have the following functions Interval timer External event counter Square wave output PWM output Figure 8 1 shows 8 bit timer event counter 2 TM2 block diagram and Figure 8 2 shows 8 bit timer event count
268. te t eter eee Ei tb eh ETE e asus aska 65 3 4 Operand Address Addressing U u U U U U UI uQ 66 3 41 Implied addressing asciende Ea uuu 66 3 4 2 Register addressing 222242 10 67 3 4 3 Direct addressing uiri oed ecce i haapa aa ger epe 68 2 4 4 Shor direct addressilig succes ctore ri te atte Gea toa cre Reda Ee Pao cus 69 3 4 5 Special function register SFR addressing 70 3 4 6 Register iridirect addressing_ eorr tnde RE kx iara ne dp br p nid aedi 71 93 4 7 Based addressing u u u UU TL EL ipe ctr dra 72 3 4 8 Based indexed addressing sessssssssesssssseseeeeeeenee E Era N nnne nnne nennen ns 72 9 4 9 Stack agddresSsiigu ioter 73 CHAPTER 4 PORT FUNCTIONS cerco cerato dive diene eet 75 Porn Funcions 75 4 2 Configuration RS sss ususqa usss 77 42 15 TATEN LIE UII IE ML 77 MB um 78 42 3 POIL2 HEN EDI LN EIE IEEE ET 79 4 2 4 e a acts ed ed eee ices hayama eain 80 4 2
269. ted set RUN to 1 within the set runaway time interval The watchdog timer can be cleared and counting is started If RUN is not set to 1 and the runaway detection time is past system reset or a non maskable interrupt request is generated according to the WDTM bit 3 WDTM3 value The watchdog timer is cleared if RUN is set to 1 The watchdog timer continues operating in the HALT mode but it stops in the STOP mode Thus set RUN to 1 before the STOP mode is set clear the watchdog timer and then execute the STOP instruction Caution actual runaway detection time may be shorter than the set time by a maximum of 2 fx sec Table 10 4 Watchdog Timer Runaway Detection Time Runaway Detection Time fx 212 489 us 213 978 us 214 1 96 ms 215 3 91 ms fx 216 7 82 ms fx 2 7 15 6 ms 218 31 3 ms fx 220 125 ms Remarks 1 fx Main system clock oscillation frequency 2 Figures in parentheses apply to operation with fx 8 38 MHz Preliminary User s Manual U14581EJ3VOUMOO 147 CHAPTER 10 WATCHDOG TIMER 10 4 2 Interval timer operation The watchdog timer operates as an interval timer which generates interrupt request repeatedly at an interval of the preset count value when bit 3 WDTM3 and bit 4 WDTM4 of the watchdog timer mode register WDTM set to 1 and 0 respectively When the watchdog timer operates as interval timer the interrupt mask flag WDTMK
270. the A D conversion result register ADCR1 will be undefined After A D conversion operation has been completed therefore read ADCR1 before writing data to ADM or ADS1 Starting conversion The first A D conversion result after A D conversion has been started by setting bit 7 ADCS1 of the A D conversion mode register ADM1 to 1 may differ from the expected value Therefore do not use the first conversion result immediately after A D conversion has been started Preliminary Users Manual U14581EJ3VOUMOO 165 CHAPTER 12 A D CONVERTER 5 6 7 166 Noise countermeasures To maintain 8 bit resolution attention must be paid to noise input to pin AVner and pins ANIO to ANI4 Because the effect increases in proportion to the output impedance of the analog input source it is recommended that a capacitor be connected externally as shown in Figure 12 11 to reduce noise Figure 12 11 Analog Input Pin Connection If there is a possibility that noise equal to or higher than AVner or equal to or lower than AVss may enter clamp with a diode with a small Vr value 0 3 V or lower Reference voltage O AVREF input 7 ANIO to 4 C 100 to 1000 pF A 77 AVss Vss ANIO to ANIA The analog input pins ANIO to ANI4 also function as input port pins P10 to P14 When A D conversion is performed with any of pins ANIO to ANI4 selected do not execute a port input instruction while conversion is in
271. tion they also function as segment signal output pins of the LCD controller driver The following operation modes can be specified in 1 bit units 1 Port mode In this mode P90 to P97 function as an 8 bit input output port They can be set in the input or output port in 1 bit units with the port mode register 9 PM9 2 Control mode In this mode P90 to P97 function as segment signal output pins S5 to S12 of the LCD controller driver 2 2 10 COMO to COM3 These pins output common signals from the LCD controller driver during 4 time division drive in 1 3 bias mode COMO to COMG outputs 2 2 11 Vicp This pin supplies a voltage to drive an LCD 2 2 12 AVREF This is A D converter reference voltage input pin This pin also functions as an analog power supply pin AVpp Supply power to this pin when the A D converter is used When A D converter is not used connect this pin to Vooo 2 2 13 AVss This is a ground voltage pin of A D converter Always use the same voltage as that of the Vsso pin even when an A D converter is not used 2 2 14 RESET This is a low level active system reset input pin 2 2 15 X1 and X2 Crystal resonator connect pins for main system clock oscillation When using an external clock supply input it to X1 and its inverted signal to X2 Preliminary User s Manual U14581EJ3V0UMOO 41 CHAPTER 2 PIN FUNCTION 2 2 16 SMVpp This pin supplies a positive power to the meter controller driver 2 2 17
272. tion List 23 1 1 Operand identifiers and description formats Operands are described in Operand column of each instruction in accordance with the description format of the instruction operand identifier refer to the assembler specifications for detail When there are two or more description formats select one of them Alphabetic letters in capitals and symbols and are key words and must be described as they are The meaning of the symbols are as follows Immediate data e Absolute address Relative address Indirect address In the case of immediate data describe an appropriate numeric value or a label When using a label be sure to describe the and symbols For operand register identifiers r and rp either function names X A C etc or absolute names names in parentheses in the table below RO R1 R2 etc can be used for description Table 23 1 Operand Identifiers and Description Formats Identifier Description Format r X RO A R1 C R2 B R3 E R4 D R5 L R6 H R7 rp AX RPO BC RP1 DE RP2 HL RP3 sfr Special function register symbol Note sfrp Special function register symbol 16 bit manipulatable register even addresses only Note saddr FE20H to FF1FH Immediate data or labels saddrp FE20H to FF1FH Immediate data or labels even addresses only addr16 0000H to FFFFH Immediate data or labels Only even addresses for 16 bit data transfer instruction
273. to 0 and bit 2 must be set to 1 116 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 7 8 BIT TIMER 1 TM1 7 4 8 Bit Timer 1 TM1 Operations 7 4 1 8 bit interval timer operation The 8 bit timer 1 operates as an interval timer which generates interrupt requests repeatedly at intervals of the count value preset to 8 bit compare register 1 CR1 When the count values of the 8 bit counter 1 TM1 match the values set to CR1 counting continues with the TM1 values cleared to 0 and the interrupt request signal INTTM1 is generated Count clock of the TM1 can be selected with bits 0 to 2 TCL10 to TCL12 of the timer clock select register 1 1 Setting 1 Setthe registers TCL1 Select count clock CR1 Compare value 2 After TCE1 1 is set count operation starts 3 If the values of TM1 and CR1 match the is generated and TM1 is cleared to OOH 4 generates repeatedly at the same interval Set TCE1 to 0 to stop count operation Figure 7 4 Interval Timer Operation Timings 1 3 a Basic operation 3 amam LIT Ta LE E 1 count value otHY TETH XXE Start count clear clear CR1 N N N N INTTM1 EC 1 1 m I received 1 1 1 TM1 interval time ee 2 ae i Interval time Interval time Interval time Remark Interv
274. to 6 of the data written to TXS are transmitted as transmit data Writing data to TXS starts the transmit operation TXS is written with an 8 bit memory manipulation instruction It cannot be read RESET input sets TXS to FFH Caution Do not write to TXS during a transmit operation The same address is assigned to TXS and the receive buffer register RXB A read operation reads values from RXB Receive shift register RXS This register converts serial data input via the RxD pin to parallel data When one byte of data is received at this register the receive data is transferred to the receive buffer register RXB RXS cannot be manipulated directly by a program Receive buffer register RXB This register is used to hold receive data When one byte of data is received one byte of new receive data is transferred from the receive shift register RXS When the data length is set as 7 bits receive data is transferred to bits 0 to 6 of RXB In RXB the MSB must be set to O RXB is read with an 8 bit memory manipulation instruction It cannot be written to RESET input sets RXB to FFH Caution same address is assigned to RXB and the transmit shift register TXS During a write operation values are written to TXS Transmit controller The transmit controller controls transmit operations such as adding a start bit parity bit and stop bit to data that is written to the transmit shift register TXS based on the values set t
275. tput Operation Timing a 229 18 1 Meter Controller Driver Block 231 18 2 1 Circuit Block u n u Dn 232 18 3 Timer Mode Control Register MCNTO 234 18 4 Compare Control Register n MCMPOn Formal nennen nnne 235 18 5 Port Mode Control Register PMC Format een ennemis 236 18 6 Restart Timing after Count Stop Count Start2 Count Stop Count Start 237 18 7 Timing in 1 Bit Addition Circuit Operation rectori te teneri rn rte ngu aerae Ra a 238 18 8 Timing of Output with 1 Clock 239 19 1 Basic Configuration of Interrupt Function ssssssseeeeeeeeneeeneneen nennen nennen 243 19 2 Interrupt Request Flag Register IFOL IF1L 246 19 3 Interrupt Mask Flag Register MKOL MK1L 247 19 4 Priority Specify Flag Register PROL PROH PR1L 2 2 248 19 5 External Interrupt Rising Edge Enable Register EGP and External Interrupt Falling Edge Enable Register EGN 249 19 6 Prescaler
276. trol 8 bit timer 1 TM1 e Timer clock select register 1 TCL1 8 bit timer mode control register 1 TMC1 1 Timer clock select register 1 TCL1 This register sets count clocks of 8 bit timer 1 TCL1 is set with an 8 bit memory manipulation instruction RESET input clears TCL1 to 00H Figure 7 2 Timer Clock Select Register 1 TCL1 Format Address FF73H After Reset OOH R W Symbol 7 6 5 4 3 2 1 0 fx 23 1 04 MHz fx 24 523 kHz fx 25 261 kHz fx 27 65 4 kHz 1x 29 16 3 kHz fx 211 4 09 kHz Other than above Setting prohibited Cautions 1 When rewriting TCL1 to other data stop the timer operation beforehand 2 Bits 3 to 7 must be set to 0 Remarks 1 fx Main system clock oscillation frequency 2 Figures in parentheses apply to operation with fx 8 38 MHz Preliminary User s Manual U14581EJ3V0UMOO 115 CHAPTER 7 8 BIT TIMER 1 TM1 2 8 bit timer mode control register 1 TMC1 is a register that controls the counting operation of the 8 bit counter 1 TM1 TMC1 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears TMC1 to 00H Figure 7 3 8 Bit Timer Mode Control Register 1 TMC1 Format Address FF76H After Reset OOH R W Symbol 7 6 5 4 3 2 1 0 mot o o o o o 0 After clearing counter to 0 count operation disabled 1 Count operation start Caution Bits 0 1 and 3 to 6 must be set
277. ual Chapter indicates the chapter of the newest edition where revision was made Edition Major Revision from Previous Edition Chapter 2nd edition Changing 1 5 Pin Configuration Top View CHAPTER 1 OUTLINE Changing description of supply voltage in 1 8 Outline of Function Changing 6 4 4 Port mode register 4 PM4 CHAPTER 6 16 BIT TIMER 0 TMO Changing Figure 6 11 Capture Register Data Retention Timing Adding Caution 3 to Figure 16 4 LCD Display Control Register CHAPTER 16 LCD CONTROLLER LCDC Format DRIVER Adding Note to Table 22 3 Transmission Method List CHAPTER 22 4PD78F0852 Preliminary User s Manual U14581EJ3VOUMOO 313 MEMO 314 Preliminary User s Manual U14581EJ3V0UMOO Although NEC has taken all possible steps essage to ensure that the documentation supplied to our customers is complete bug free and up to date we readily accept that From errors may occur Despite all the care and precautions we ve taken you may Name encounter problems in the documentation Please complete this form whenever Company you d like to report errors or suggest improvements to us Tel FAX Address Thank you for your kind support North America Hong Kong Philippines Oceania Nations except Philippines NEC Electronics Inc NEC Electronics Hong Kong Ltd NEC Electronics Singapore Pte Ltd Corporate Communications Dept Fax 852 2886 9022 9044 Fax 465 250
278. utine NMI request 1 NMI request lt 2 gt Execution of 1 instruction Zl during non maskable interrupt servicing program Execution of NMI request lt 1 gt NMI request lt 2 gt held pending Servicing of NMI request 2 that was pended b If two non maskable interrupt requests are generated during non maskable interrupt servicing program execution NMI request lt gt Lose m NMI request 2 NMI request lt 3 gt Execution of 1 instruction 254 Preliminary User s Manual Execution of NMI request 1 NMI request 2 held pending NMI request 3 held pending Servicing of NMI request 2 that was pended NMI request 3 not acknowledged Although two or more NMI requests have been generated only one request is acknowledged U14581EJ3VOUM00 CHAPTER 19 INTERRUPT FUNCTIONS 19 4 2 Maskable interrupt request acknowledge operation A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the mask MK flag corresponding to that interrupt is cleared to 0 A vectored interrupt request is acknowledged if in the interrupt enable state when IE flag is setto 1 However a low priority interrupt request is not acknowledged during servicing of a higher priority interrupt request when the ISP flag is reset to 0 The times from generation of a mask
279. utput RESET input sets port 6 to input mode Figure 4 8 shows a block diagram of port 6 Figure 4 8 P60 and P61 Block Diagram C Output latch i P60 PCL TPO P60 P61 gt p61 SGO Internal bus 60 PM61 Alternate functions PM Port mode register RD Port 6 read signal WR Port 6 write signal Preliminary User s Manual U14581EJ3V0UMOO 83 CHAPTER 4 PORT FUNCTIONS 4 2 8 Port 8 Port 8 is a 7 bit input output port with output latch P81 to P87 pins can specify the input mode output mode in 1 bit units with the port mode register 8 8 Alternate functions also include segment signal output of the LCD controller driver Segment output and input output port can be switched by setting the LCD display control register LCDC RESET input sets port 8 to input mode Figure 4 9 shows block diagram of port 8 Figure 4 9 P81 to P87 Block Diagram RD Internal bus Output latch P81 to P87 P81 S19 to P87 S13 WRem E PM81 to PM87 Segment output function PM Port mode register RD Port 8 read signal WR Port 8 write signal 84 Preliminary User s Manual U14581EJ3V0UMOO CHAPTER 4 PORT FUNCTIONS 4 2 9 Port 9 Port 9 is an 8 bit input output port with output latch P90 to P97 pins can specify the input mode output mode in 1 bit units with the port mode register 9 PM9 Alternate functions also include se
280. utput Control Prescaler signal output disabled Prescaler signal output enabled Cautions 1 Before changing the operation mode stop the timer operation by setting 0 to 02 2 Bits 1 and 3 to 7 must be set to 0 Preliminary User s Manual U14581EJ3VOUMOO 105 CHAPTER 6 16 BIT TIMER 0 TMO 2 106 Capture pulse control register CRCO This register specifies the division ratio of the capture pulse input to the 16 bit capture register 02 from an external source CRCO is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears CRCO to 00H Figure 6 3 Capture Pulse Control Register CRCO Format Address FF71H After Reset 00H R W Symbol Z 6 5 4 3 2 1 0 Does not divide capture pulse Divides capture pulse by 2 Divides capture pulse by 4 Divides capture pulse by 8 Cautions 1 Timer operation must be stopped before setting CRC0 2 Bits 2 to 7 must be set to 0 Preliminary User s Manual U14581EJ3V0UM00 CHAPTER 6 16 BIT TIMER 0 TMO 3 Prescaler mode register PRMO This register is used to set TMO count clock and valid edge of TIOO to TIO2 input PRMO is set with an 8 bit memory manipulation instruction RESET input clears PRMO to 00H Figure 6 4 Prescaler Mode Register PRMO Format Address FF70H After Reset OOH R W Symbol 7 6 5 4 3 2 1 0 PRMO ES21 ES20 ES11 ES10 501 500 PRM01 PRM00 ESn1 5 0 TIOn Valid Edge Selection Falling edge
281. utput Controller Configuratio 2 149 12 1 A D Gonverter GonfiguratiOhi iei teret SEE EXER ERR ev ERN REEF E APER Ge 155 13 1 Serial Interface UART Configuration u 170 13 2 Relation between 5 Bit Counter s Source Clock and n 179 13 3 Relation between Main System Clock and Baud Rate 180 13 4 Gauses of Receive cii cce dr sid e men Eee e ka Pru aqhapa kas 185 14 1 Serial Interface 5102 Configuration u 188 14 2 Relation between Operation Modes and Settings of PMOS to 192 14 3 Operation Mode and Pin enne nnnm 196 15 1 Serial Interface SIO3 Configuration 202 24 Preliminary User s Manual U14581EJ3V0UM00 LIST OF TABLES 2 2 Table No Title Page 16 1 Maximum Number of Display nnne nere 207 16 2 LCD Controller Driver Configuration u S u QS S Enna aaa ee eR Rn ER Rad as 208 16 3 COIS IGS iio 214 16 4 LCD Drive hl EST 214 16 5 LOD Drive ble IRR 216 16 6 Selection and Non Selection Voltages COMO to
282. ve CPU processing Instruction Instruction jump to interrupt Interrupt servicing servicing program xxlF xxPR 1 8 clocks xxlF 20 T mr 00 7 clocks Remark 1 clock 1 fceu fceu CPU clock Figure 19 13 Interrupt Request Acknowledge Timing Maximum Time 25 clocks 6 clocks PSW and PC save CPU processing Instruction Divide instruction jump to interrupt Interrupt servicing servicing program xxIF xxPR 1 _ 33 clocks xxlF xxPR 0 32 clocks Remark 1 clock 1 fceu fceu CPU clock 19 4 3 Software interrupt request acknowledge operation A software interrupt request is acknowledged by BRK instruction execution Software interrupts cannot be disabled If a software interrupt request is acknowledged the contents are saved into the stacks in the order of the program status word PSW then program counter PC the IE flag is reset to 0 and the contents of the vector table OO3EH 003FH are loaded into PC and branched Return from a software interrupt is possible with the RETB instruction Caution Do not use the RETI instruction for returning from the software interrupt Preliminary User s Manual U14581EJ3VOUMOO 257 CHAPTER 19 INTERRUPT FUNCTIONS 19 4 4 Multiple interrupt servicing Multiple interrupts occur when another interrupt request is acknowledged during execution of an interrupt Multiple interrupts do not occur unless the interrupt request
283. ved Flash memory 40 960 x 8 bits Y Preliminary User s Manual U14581EJ3VOUM00 CHAPTER 3 CPU ARCHITECTURE 3 2 Processor Registers The uPD780852 Subseries incorporate the following processor registers 3 2 1 Control registers The control registers control the program sequence status and stack memory The control registers consist of a program counter PC a program status word PSW and a stack pointer SP 1 2 Program counter PC The program counter is a 16 bit register which holds the address information of the next program to be executed In normal operation the PC is automatically incremented according to the number of bytes of the instruction to be fetched When a branch instruction is executed immediate data and register contents are set RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter Figure 3 7 Program Counter Configuration PC 15 0 dope eres Pos eros oer pow Program status word PSW The program status word is an 8 bit register consisting of various flags to be set reset by instruction execution Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are automatically reset upon execution of the RETB RETI and POP PSW instructions RESET input sets PSW to 02H Figure 3 8 Program Status Word Configuration 7 0 ie z ss mes s Prelim

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