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XLM72 User`s Manual Revision B - JTEC

1. July 14 2003 Page 42 Manual XLM 72 NET LEDOPD lt 2 gt LOC P83 high NET NMIDXOPD LOC P177 directly to pad C13 of the ET INT6DXOPD LOC P176 directly to pad D2 of the z Unmasked and masked interrupt of DSP strobes require at least a 2 cyclelow followed by at least a 2 cycle nonmaskable interr DSP masked interrupt DSP mdo X LM 72 M AN 001 0 Low to high leading edge upt NMI connected EXT INT6 connected 5 2 USING UTILITY CONFIGURATION OF FPGA As discussed in Section 4 5 1 XLM 72 is released with a Utility Configuration of FPGA loaded into sector 0 of Flash M emory which is loaded into FPGA upon power up This configuration can be used to perform operations on Flash M emory but it offers also other functions useful for diagnostic purposes As discussed in Section 4 5 1 the various actions of the utility program are triggered by writing into the write only Interface location 820004h see also Section 4 3 1 2 and that the utility program identifies the nature of the request by inspecting the content of its data register at VM EBus address 40000Ch Thus to induce the general utility program to perform any of its operations the user must v acquire control of Bus X by writing 10000h into location 800000h Interface vi write the code of the desired operation into location 40000Ch FPGA vii release control of buses by
2. 35 4 6 6 INSPECTING THE IRQPENDING FLAGS 36 Arly QOPERATIONS ON THE FLASH MEMORY 36 4 LL FERGA UTIDIEY CONTIGURA TI QN ripetere rerit em eei pee ere ter 36 July 14 2003 Page 1 Manual XLM 72 mdo X LM 72 M AN 001 0 5 APPENDICES weiss erri mieten te edt ere oe a tere 38 51 USER CONSTRAINTS FIEE 38 5 2 USING UTILITY CONFIGURATION OF FPGA sssseeennennnnn nnns 43 5 2 1 WRITING TO THE IRQ MAILBOX OF INTERFACE eene 44 5 22 TEST DATA PATTERNS insit tie eee iei 44 July 14 2003 Page 2 Manual XLM 72 mdo X LM 72 M AN 001 0 J TEC Model XLM 72 Universal L ogic M odule 1 OVERVIEW JTEC Model XLM72 is a highly versatile general purpose programmable universal logic module for use in VM E based systems The desired logic operations are performed by a Xilinx XCS40XL Field Programmable Gate Array FPGA while more elaborate numeric operations are performed by a Texas Instruments 900 M flops s floating point Digital Signal Processor DSP TM S320C 6711 It communicates with external devices via 72 programmable front panel ECL ports which can be configured in quartets either as input or output ports The ECL ports are mapped onto the ports of the user FPGA On the other end 72 communicates with computers via the VM EBus utilizing 32 bit addressing and 32 bit and 16 bit data transfer including 32 bit block transf
3. ECL FPGA Pad UCF Name of ECL FPGA Pad UCF Name of Port FPGA Pad Port FPGA Pad 1 107 ECLAPD 1 1 150 ECLCPD 1 2 101 ECLAPD 2 C2 149 ECLCPD lt 2 gt 100 ECLAPD 3 148 ECLCPD 3 4 99 ECLAPD 4 C4 147 ECLCPD 4 A598 ECLAPD 5 C5 146 ECLCPD lt 5 gt A6 97 ECLAPD 6 C6 145 ECLCPD 6 7 96 ECLAPD 7 C7 144 ECLCPD 7 A8 95 ECLAPD 8 C8 142 ECLCPD lt 8 gt 9 94 ECLAPD 9 C9 141 ECLCPD lt 9 gt 10 93 ECLAPD 10 C10 139 ECLCPD 10 11 92 ECLAPD lt 11 gt C11 138 ECLCPD lt 11 gt A12 90 ECLAPD 12 C12 137 ECLCPD 12 A13 89 ECLAPD 13 C13 136 ECLCPD 13 14 88 ECLAPD 14 C14 135 ECLCPD 14 15 87 ECLAPD 15 C15 134 ECLCPD 15 A16 85 ECLAPD 16 C16 133 ECLCPD lt 16 gt A17 127 ECL17PD lt 1 gt C17 129 ECL17PD 3 1 126 ECLBPD 1 D1 175 ECLDPD 1 2 125 ECLBPD 2 D2 174 ECLDPD lt 2 gt B3 124 ECLBPD 3 D3 172 ECLDPD lt 3 gt B4 123 ECLBPD 4 D4 171 ECLDPD 4 B5 122 ECLBPD 5 D5 169 ECLDPD lt 5 gt 6 120 ECLBPD 6 D6 168 ECLDPD 6 B7 119 ECLBPD 7 D7 167 ECLDPD 7 B8 117 ECLBPD 8 D8 166 ECLDPD lt 8 gt 9 116 ECLBPD 9 D9 165 ECLDPD lt 9 gt B10 115 ECLBPD 10 D10 164 ECLDPD 10 B11 114 ECLBPD 11 D11 163 ECLDPD 11 B12 113 ECLBPD 12 12 162 ECLDPD 12 B13 122 ECLBPD 13
4. Ex Interrupts from VME and DSP functionality is user defined Active low 3 cycle strobes Clocked by LE of the system clock Recommended way of use latch the leading edge NET NIRQXVIPD LOC P49 NET NIRQXDIPD LOC P80 Select FPGA from Interface Active low clocked by LE of the system clock NET NSELXVIPD LOC P48 for an explanation look after the description of NWRI Signal used by the Interface to define Write Read operation to from the FPGA Clocked by LE of the system clock NET NWRXIPD LOC P34 In write to FPGA operations by the Interface NWRI is low and NSELX is a 2 cycle write strobe In read from FPGA operations by the Interface NWRI is high and NSELX is a 4 cycle data output enable signal Active low strobe of two different of the system clock Interrupt VME on VMEbus IRQ3 durations To be clocked by LI NET NIRQVXOPD LOC P67 A 2 cycle strobe generates in the Interface an XLM72 IRQ ID with bit 0 0 while a 3 cycle strobe generates an ID with bit 0 1 a mechanism to inform the IRQ service routine of the nature of the request e g data ready in ASRAM A or data ready in ASRAM B E Control of three front panel LEDs Active high Minimum duration 2 clock cycles to produce a robust blink Continuous on keeps LED on LEDOPD 1 LOC P84 NET LEDOPD lt 3 gt LOC P82
5. Digital Delay and Gate Generators Detector R eadout Processor Histogramming M emory Due to the ultimate parallelism of an FPGA XLM 72 can be programmed to perform multiple functions simultaneously whether related or completely unrelated For example part of XLM72 may be programmed to function as an Intelligent FERA Controller B uffer while other parts execute trigger logic yet another parts serving as a block of gated and non gated scalers and yet another part serving as digital delay and gate generators 2 SPECIFICATIONS Formfactor 6U VME PC Board 8 layer double sided mixed surface mount and through hole VME Connectors 96 pin 1 2 and 30 pinJAUX implementing CERN extensions ECL Ports 72 mapped onto the user FPGA LEDs one to indicate VM EBus operations three user programmable via the FPGA configuration Clocks one 80 M Hz shared by the VM EBus interface and FPGA one 37 5 MHz for DSP External Clock Inputs up to four rated at 110 M Hz FPGA 540 1 5 0208 by Xilinx DSP TM 5320 6711 by Texas Instruments ASRAM s 16 CY 7C1024B 15CV organized in two banks of 2 M byte 32 bit memory FPGA Configuration Memory 2 M byte AT 29C020 by Atmel July 14 2003 Page 4 Manual XLM 72 mdo X LM 72 M AN 001 0 VMEBusAddressing 32 bit geographic VMEBus Data Transfer 32 bit and 16 bit 32 bit block transfer at rates of up to 40 M bytes s Front Panel Black anodized with white silk screen lab
6. Successful operation of X LM 72 requires its proper hardware setup the programming of its user FPGA and or DSP and the computer access of its five addressable devices via VMEBus 4 1 HARDWARE SETUP The hardware setup of XLM 72 includes i configuring its front panel ECL ports for operation in conjunction with the intended FPGA configuration and ii making sure that the three blocks of jumpers JP34 JP36 are configured properly Furthermore one is expected to connect respective ECL ports to external devices with twisted pair or flat ribbon cables The ECL ports are configurable in quartets either as inputs or outputs The four ports identified by silk screen labels on the front panel and on the X LM 72 board as E1 E4 play a special role as they connect via ECL to TTL translators M C10125 to primary PGCK clock inputs E1 E3 and secondary SGCK inputs E4 of FPGA These FPGA inputs can be used to drive intrinsic clock nets of FPGA Accordingly ports E1 E4 can and should be used to supply external clock signals up to 110 MHz to XLM 72 4 1 1 IMPORTANT WARNINGS Improper configuring of ECL ports may lead to the damage of translator ICs or a costly damage of the XLM 72 board or of the user FPGA A special care should be taken to correctly identify and populate the sockets with translator ICs When not sure please consult J TEC Support service Warning 1 Only one translator IC either input or output is allowed for any singl
7. 3 1 3 DIGITAL SIGNAL PROCESSOR To allow one to perform more complex numerical operations on data that are beyond the capabilities of the user FPGA XLM72 is equipped with a Texas Instruments TM S 320C 6711 floating point digital signal processor The processor is clocked at 150 MHz and given its 6 parallel processors is rated at 900 Mflop s The DSP can access July 14 2003 Page 7 Manual XLM 72 mdo X LM 72 M AN 001 0 select registers of the Interface and both banks of ASRAM in either 32 bit data words or in 16 bit words VM EBus can access the DSP via the Host Port Interface HPI of the latter 3 1 4 VMEBUS INTERFACE AND BUS ROUTER ARBITER The communication between V M EBus and various devices of XLM 72 is mediated by an interface and bus router arbiter array implemented in four X ilinx Complex Programmable Logic Devices Interface The Interface is comprised of one XC95216 10PQ160C and three X C95288X L 7TQ144C chips Individual CPLDs can be reprogrammed in system via the on board TAG port allowing one to alter the functionality of the Interface should a need arise The Interface serves also as a multiple master bus router and arbiter such that it may route in parallel bus needs by more than one master Since XLM 72 features three masters V M EBus FPGA and DSP there is a need not only for bus routing but also for bus arbitration The needed arbitration scheme is also implemented in the Interface array Furthermore some
8. The correspondence between these signals and FPGA pins is shown in Table 9 Table 9 Data Byte Enable pins Byte FPGA pin Byte FPGA pin Byte FPGA pin Byte FPGA pin 0 72 1 44 2 63 3 81 4 4 4 5 WRITE OPERATION PORTS The FPGA signals to the Interface a write operation by asserting one or both of its NWRA and NWRB lines active low NWRA low indicates that the operation upon ASRAM A the Interface or the Flash Memory is a write operation The target of the operation is in this case determined by the Interface based on the state of the NSEL lines discussed below NWRA low indicates that the operation upon ASRAM B is a write operation Note that the two NWR signals are not strobes They are to be asserted at the time of the placement of the address and data on their respective local buses and de July 14 2003 Page 25 M anual XLM 72 mdo X LM 72 M AN 001 0 asserted upon completion of operation They should be kept constant for the duration of a block transfer In the UCF the NWRA and NWRB pins are labeled NWRAOPD and NWRBOPD respectively Their association with physical pins of the FPGA is shown in Table 10 below Table 10 Write enable output pins of the FPGA NWR signal FPGA pin NWR signal FPGA pin NWRA 69 NWRB 59 4 4 4 6 DEVICE SELECTION PORTS The FPGA signals to the Interface the intended target of its operation over three lines NSELA NSELB and NSELV
9. named in UCF as NSELAOPD NSELBOPD and NSELVOPD All these lines are active low and have dual functionality depending on whether the operation is write or read In write operations NSEL signals serve as write strobes and hence must be asserted so as to allow the address to propagate to the target device prior to their own reaching of the target via the Interface It was found that a safe way to write to ASRAM s is to assert the relevant NSEL signal for one system clock cycle two system clock cycles after the FPGA has placed the address and data on their respective local buses In a block transfer this results then in a 3 cycle transfer and in an overall throughput of 107M byte s 80M Hz clock The Interface makes here use of the data byte enable signals NDBEO lt 0 gt lt 3 gt to strobe only the desired memory chips storing individual bytes In read operations NSEL signals serve as chip enable signals which in conjunction with the ASRAM output enable signals cause the target device to output the addressed data on the data bus In this case NSEL is to be asserted at the time of the placement of address on the local address bus and can be constantly low for the entire duration of a block transfer The ASRAM output enable signals are generated by the Interface when the latter detects the presence of an NSEL signal in the absence of the associated NWR signal NWR high There are following valid combinations of t
10. ADDRESS SPACE The TM S320C6711 DSP has a single 32 bit address space covering internal memory and registers as well as external memories The DSP accesses external memories through its Extended M emory Interface EM IF capable of handling a variety of memory types In the XLM 72 these external memories are the two banks of ASRAM s and the Interface all of which present themselves to the D SP as asynchronous random access memories The address space of the DSP is allocated as follows 0000 0000h Internal memory of the DSP 8000 0000h ASRAM A 2M bytes 9000 0000h ASRAM B 2M bytes A 000 0000h Interface few selected addresses By default the Extended M emory Interface is set for asynchronous RAM and hence will work with ASRAM s and the Interface of XLM 72 The default timing of the EMIF is however slow and it is advisable to set it to a much faster one The EMIF for any particular internal device of X LM 72 can be configured by writing to the respective EM IF register The EMIF registers have the following addresses within the DSP internal address space 180 0008h EMIF forASRAM A 180 0004h EMIF for ASRAM B 180 0010h EMIF for Interface 180 0000h Global EM IF register 4 5 2 USER S GUIDE TO HOST PROCESSOR INTERFACE General remarks i The present guide applies to X LM 72s equipped with DSPs with silicon ID C21 and not C13 used in prototype series ii XLM 72 powers up with DSP kept in reset state To use HPI and the DS
11. D13 161 ECLDPD 13 B14 111 ECLBPD 14 D14 159 ECLDPD 14 B15 110 ECLBPD 15 D15 152 ECLDPD 15 16 109 ECLBPD 16 D16 151 ECLDPD 16 B17 128 ECL17PD lt 2 gt D17 132 ECL17PD lt 4 gt 1 102 SGCK3 ECLEPD 1 2 PGCK1 lt 3 gt July 14 2003 Page 21 Manual XLM 72 mdo X LM 72 M AN 001 0 E2 108 PGCK3 ECLEPD lt 2 gt E4 160 4 ECLEPD lt 4 gt 4 4 2 LED PORTS X LM 723 is equipped with three front panel user programmable LEDs red green and yellow controlled by FPGA configuration through expanding drivers These drivers extend the duration of short pulses of at least 2 clock cycle duration to approx 25 ms to provide for a robust flash of the associated LED while not affecting the action of longer pulses All LED ports are active high A non configured FPGA will cause all three LEDs to turn on a state that can be taken as indicative of a failure of FPGA to boot Conversely user LEDs will signal a successful configuration of the FPGA by displaying a pattern foreseen by the user code In the UCF file See Appendix 5 1 LED pads are named LEDOPD lt 1 gt LEDOPD 3 respectively Their association with physical pads of the FPGA is shown in Table 4 Table 4 Front panel LED control pads of the FPGA LED FPGA Name of LED FPGA UCF FPGA Name of Pad Pad Pad FPGA Pad Pad FP
12. DSP at 00 0824h Table 16 Direct Interrupt M echanism IRQSource IRQTarget Direct Interrupt Mechanism VMEBus FPGA Write to 82 0004h VMEBus_ DSP Write to 82 1048h generates INT 4 for DSP FPGA DSP Toggle INT6DXOPD NMIDXOPD for INT6 NMI DSP FPGA Write to A003 1048h July 14 2003 Page 34 Manual XLM 72 mdo X LM 72 M AN 001 0 4 63 SETTING OF THE IRQOPENDING FLAGS The IRQPending flags are set automatically upon writing to the respective IRQM ail register by an IRQSource In the case of the V M EBus interrupting the FPGA the flag is set automatically at writing to 82 0004h 4 64 READING THE CONTENT OF THE IROMAIL REGISTERS Every master device can access the IRQID data written by the two remaining masters by reading the content of the Interface register at address 824h A ccordingly V M EB us must read from address 82 0824h DSP must read from address A 000 0824h and FPGA must read from address 00 0824 of the Interface The correspondence between the bits of the read register and the IR QSource is shown in Table 17 Table 17 Bit assignment in the 32 bit IRQM ail register words read by IRQT argets IRQTarget IRQSource for Bits 2 15 IRQ Source for Bits 18 31 VMEBus FPGA DSP FPGA DSP N A DSP VME FPGA UIRQID is to be placed to a User defined register within the FPGA 4 65 CLEARING THE CONTENT OF THE IROMAIL REGISTERS For a sound operation of
13. M AN 001 0 LED is driven via a pulse length extender such that even short 20ns long pulses produce robust flashes while long pulses or DC levels are transmitted to the LED unaltered 3 2 BUSES Devices of XLM 72 and the V M EBus communicate with each other via the V M EBus and five internal buses All communications are mediated by the Interface which routes addresses and data generated by the three masters VM EBus FPGA and DSP to the respective target devices The Interface allows for a concurrent access of several buses by Several masters and performs at the same time the function of the bus arbitrator 3 2 1 INTERFACE TO ASRAM BUSES Thetwo ASRAMs ASRAM A and ASRAM B communicate with the Interface via their respective buses named Bus A and Bus B respectively Each of these buses has 19 address 32 data and 3 control lines Bus A is shared with the Flash M emory with the exception of one control line for which the Flash M emory has its individual counterpart Buses A and B can be controlled by any of the three masters VM EBus FPGA and DSP Which in practical terms means that any one of these three masters can write to or read from either of the two banks of ASRAM s 3 22 INTERFACE TO FPGA BUS The FPGA communicates with the Interface via a bus named Bus X featuring 19 address 32 data and 26 control lines Bus X can be controlled by either the V M EBus or the FPGA 3 23 INTERFACE TO DSP BUS The DSP commu
14. Note that bit 10 set appears as 0400h and bit 26 set appears as 0400 0000h Note also that in the case of the VM EBus and the DSP bits 0 1 and 8 for VM EBus only of the status register at Oh contain acknowledgment of bus grants 4 7 OPERATIONS ON THE FLASH MEMORY 4 7 1 FPGA UTILITY CONFIGURATION XLM 72 is released with a general FPGA utility program loaded into the default boot sector 0 of the flash memory This program guarantees that there is no bus contention on the ECL ports of the FPGA upon power up as it has all respective pads defined as bi directional with outputs being disabled A mong other things this Utility Configuration allows one to program the flash memory set and reset its software protection and read back the FPGA configuration files stored in the flash memory The various actions of the utility program are triggered by the interrupt signal by the VM Ebus which is generated by writing into read only Interface location 820004h see also Section 4 3 1 2 The utility program identifies the nature of the request by inspecting the content of its data register at V M EBus address 40000Ch Thus to induce the general utility program to perform any of its operations the user must i acquire control of Bus X by writing 10000h into location 800000h Interface ii write the code of the desired operation into location 40000Ch FPGA ili release control of Bus X by writing 0 into location 800000 Interfa
15. Page 19 Manual XLM 72 mdo X LM 72 M AN 001 0 interest A s discussed in Section 3 3 the V M EBus address space for ASRAM A extends from Oh to IFFFFCh and that of ASRAM B from 200000h to 3FFFFCh The use of the address spaces of the two banks of ASRAMs is straightforward and involves writing of desired data into or reading data from the desired memory address For example writing data to the address 000008h causes this data to be stored in the memory location 8h of ASRAM A Asa second example reading from memory location 200010h will retrieve the content of the memory location 10h of ASRAM B 4 3 5 ACCESSING FPGA The use of the address space of the FPGA remains at discretion of the user and is to be determined at the design time of the user FPGA code One would expect here only a few low memory locations to be utilized with perhaps a suggestion to dedicate always the same location 0 for storing a read only 32 bit ID of the particular user firmware 4 5 4 ACCESSING DSP The DSP can be accessed via its Host Port Interface HPI over the dedicated BUS The use of this bus is described in detail in subsection 4 5 1 4 4 PROGRAMMING OF THE USER FPGA With Interface being an integral and tested part of XLM 72 any further successful use of XLM 72 hinges critically on the quality of the user code loaded into the FPGA of XLM 72 To write such a code the user must know the role of all pins of the FPGA used in the design of XL M 72
16. of the registers of the Interface serve the role of mailboxes for sending messages between the VM EBus DSP and the FPGA In particular such registers are used to implement interrupt and polling schemes required by various data acquisition systems 3 1 5 FLASH MEMORY To provide for the storage of the FPGA configuration data XL M 72 is equipped with one 2 MBit Programmable Erasable Read Only Memory Flash Memory an ATMEL 29 020 90 The size of this memory is sufficient to accommodate up to four configuration files one of which is a default boot configuration The Flash M emory is socketed but can be reprogrammed in system The chip is rated for 10 000 programming cycles and 20 year data retention 3 1 6 ECL PORTS XLM 72 is equipped with 72 ECL ports organized in four 34 pin and one 8 pin header The ports are controlled exclusively by the FPGA and can be configured in quartets as either inputs or outputs but always unidirectional Four ECL ports serve special role as they are associated with clock inputs of the FPGA As such they can serve as inputs for external clock signals to the FPGA 3 1 7 DIAGNOSTIC LEDs XLM 72 is equipped with four front panel light emitting diodes LED one of which yellow signals V M EBus operations by the Interface and the remaining three red green and yellow being controlled by the FPGA and hence by the user configuration Every July 14 2003 Page 8 M anual XLM 72 mdo X LM 72
17. their first common pins marked by dots The correspondence between the ECL ports and the 10 position rows of the Zig Zag sockets is indicated by silk screen labels printed on both sides of these sockets Figure 2 illustrates placement of translator chips and resistor arrays for ECL ports D1 D4 configured as output ports and ports E1 E4 as input ports Dots indicate pins 1 July 14 2003 Page 12 Manual XLM 72 mdo X LM 72 M AN 001 0 Fig 2 Placement of ECL port components for inputs yellow and outputs blue 4 1 2 1 CONFIGURING IMPEDANCE MATCHING RESISTOR ARRAYS FOR ECL INPUT PORTS As noted in subsection 4 1 2 further above to avoid reflections of incoming signals from the ECL input ports 8 x 50Qresistor arrays are to be inserted into proper rows of the Zig Zag sockets Note that each differential ECL input is associated with two signal lines and that both these lines need to be terminated Which is why for one quartet of inputs eight terminating resistors are needed The 8 x 50Q arrays are to be inserted with their common pins entering sockets marked as 11 top most sockets in the case of the 7 vertical Zig Zag sockets and left most sockets in the case of the 2 horizontal Zig Zag sockets Warning Even though each row of a 20 pin Zig Zag socket is capable of accommodating a typical commercial 9 x 500 resistor array with ten pins one should use only 8 x 500 arrays This is so because the pins on the opposite end
18. with respect to 11 of the Zig Zag sockets labeled as O1 are connected to 5 2V to supply pull down voltage for output port resistor arrays 8 x 4700 see also sub section 4 1 2 3 Note that general rules for bussing of ECL input ports require that only the last port on the bus has its terminating resistor installed 4 1 2 2 CONFIGURING INPUT POLARIZING RESISTORS To guarantee a default logical zero at ECL input ports that are not externally driven XLM 72 provides sockets for respective polarizing pull down of complementary ECL input line resistor arrays These sockets are located next to the input translator sockets and are associated directly with the adjacent socket This association is also reflected in the silk screen label printed next to the socket Position of the pin 1 common is in this case indicated by the cut corner of the silk screen socket outline bottom The input July 14 2003 Page 13 Manual XLM 72 mdo X LM 72 M AN 001 0 polarizing resistors should be removed when the particular ports are configured as output ports Note that the use of polarizing resistors is not mandatory unless the user configuration of FPGA relies on a definite polarization It may be however a sound practice to use these resistors with every input translator Note that general rules for bussing of ECL input ports require that only the last port on the bus has its polarizing resistor installed 4 1 2 3 CONFIGURING OUTPUT PULL
19. 3 3 SETTINGS OF JP36 DSP ENDIANNESS JP36 selects endianness of DSP as indicated by the silk screen labels to its right With a jumper in the lower position LE DSP operates in little endian while with a jumper in the upper position BE DSP operates in big endian 4 2 ADDRESSING AND DATA FORMATTING CONVENTIONS Further below the role of individual bits in various address and data words will be discussed as well as the significance of various addresses and values of data words stored at these address locations The rules adopted to identify individual bits and to interpret address and data words are presented in sub sections 4 2 1 4 2 3 below 4 2 1 NUMBERING IN ADDRESS AND DATA WORDS Whenever the role of individual bits either in address or data words is discussed it will be assumed further below that the least significant bit has index zero Accordingly the most significant bit in a 32 bit word is bit 31 4 2 2 ADDRESS REPRESENTATION XLM 72 allows only 32 bit addressing with the five most significant bits of this address representing the slot number occupied by XLM 72 or in other words its geographic July 14 2003 Page 15 Manual XLM 72 mdo X LM 72 M AN 001 0 address To address the total of five addressable internal devices XLM 72 implements a 24 bit scheme where the 3 most significant bits identify the device of interest and the remaining 21 bits identify the internal register or memory location of
20. 320 6711 and the 3 pin J P36 right below JP35 4 1 3 1 JP34 SETTINGS FPGA DEFAULT BOOT SOURCE JP34 has two positions identified by silk screen labels SPROM and JTAG respectively For normal operation the jumper should be placed in the SPROM position i e connecting the two left most pins of JP34 This allows FPGA to boot upon power up from the default boot sector of the flash memory socketed A T 29C 020 to the left of JP34 The JTAG position of JP34 is intended primarily for in system programming reprogramming in conjunction with the 6 pin JP33 JTAG header of the four complex programmable logical devices CPL Ds constituting the Interface Since the July 14 2003 Page 14 Manual XLM 72 mdo X LM 72 M AN 001 0 user FPGA is a JTAG chain with the Interface CPLDs it can be programmed via the port too when JP34 is set to TAG 4 1 3 2 JP35 SETTINGS DSP BOOT SOURCE AND DATA SIZE JP35 is used to select the boot source and the size of the boot data for DSP It has three pairs of pins with one pair serving only as a storage bin The significance of various jumper settings is described by the silk screen label located right to J P35 It is shown in Table 1 below Table 1 Settings of DSP boot mode jumpers 1 2 3 4 Boot Source DataW ord Size OFF OFF ASRAM A 8 bits ON OFF ASRAM A 32 bits OFF ON HPI 16 bit Default ON ON ASRAM A 16 bits 4 1
21. C DRIVEN BY FORCE OF LOGIC User s M anual M odel XL M 72 Universal L ogic M odule For VME Systems Revision B JTEC Instruments 32 Thompson Rd Rochester NY USA T el 585 334 1960 FAX 585 334 1960 http www jtec instruments com Information furnished by JTEC Instruments J TEC is believed to be accurate and reliable However no responsibility is assumed by JTEC for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patents rights of JTEC reserves the right to change specifications at any time without notice Copyright 2002 by JTEC M anual mdo X LM 72 MAN 001 1 D ecember 2002 Manual XLM 72 mdo X LM 72 M AN 001 0 TABLE OF CONTENTS 1 POV ERM IEW eninin rni ner p rne Oe OP e Fe pea a Li SUMMARY OF EEATURES iei dete beet mera rp eed p 1 2 POSSIBLE APPLEICA TIONS iret htt ere reete aa 2 SPECIFICATIONS eto o n a re pe are e deu ED E epe d tage 3 ARCHITECTURE tiro e etre rr eer Pene isn ERE Ee dtp eq dd Jil DEVICES eae ea i i e prete divae 3 11 ASYNCHRONOUS STATIC RANDOM ACCESS MEMORY 3 1 2 FIELD PROGRAMMABLE 3 1 3 DIGITALE SIG
22. C P20 ET LOCDAPD 8 LOC P200 ET LOCDAPD 9 LOC P19 ET LOCDAPD 10 LOC P30 July 14 2003 Page 39 Manual XLM 72 NET LOCDAPD 11 LOC NET LOCDAPD 12 LOC NET LOCDAPD 13 LOC NET LOCDAPD 14 LOC NET LOCDAPD 15 LOC NET LOCDAPD 16 LOC NET LOCDAPD 17 LOC NET LOCDAPD lt 18 gt LOC NET LOCDAPD lt 19 gt LOC LOCDAPD lt 20 gt LOC LOCDAPD lt 21 gt LOC NET LOCDAPD lt 22 gt LOC LOCDAPD 23 LOC NET LOCDAPD 24 LOC NET LOCDAPD 25 LOC NET LOCDAPD 26 LOC NET LOCDAPD 27 LOC NET LOCDAPD 28 LOC NET LOCDAPD 29 LOC NET LOCDAPD 30 LOC NE LOCDAPD 31 LOC Bidirectional add LOC LOC LOC LOGS LOC LOC LOC LOC LOC LOC LOC t pins and AS interf LOC P data LOC P router NE LOCADPD lt 2 gt NE LOCADPD lt 3 gt NE LOCADPD lt 4 gt NE LOCADPD lt 5 gt NE LOCADPD lt 6 gt NE LOCADPD lt 7 gt NE LOCADPD lt 8 gt NE LOCADPD lt 9 gt NE LOCADPD lt 10 gt NE LOCADPD lt 11 gt NE LOCADPD lt 12 gt NE LOCADPD lt 13 gt NE LOCADPD lt 14 gt NE LOCADPD lt 15 gt NE LOCADPD lt 16 gt NE LOCADPD lt 17 gt NE LOCADPD
23. DOWN RESISTORS For a proper operation of ECL output ports 8 x 470Q pull down resistor arrays are to be inserted into proper rows of the Zig Zag sockets Note that each differential ECL output is associated with two signal lines and that both these lines need to be pulled down via resistors to Veg 5 2V Which is why for one quartet of outputs eight pull down resistors are needed The 8 x 4700 arrays are to be inserted with their common pins entering sockets marked as O1 bottom sockets in the case of the 7 vertical Zig Zag Sockets and right most sockets in the case of the 2 horizontal Zig Zag sockets Warning Even though each row of a 20 pin Zig Zag socket is capable of accommodating a typical commercial 9 x 4700 resistor array with ten pins should use only 8 x 4700 arrays This is so because the pins the opposite end with respect to O 1 of the Zig Zag sockets labeled as11 are connected to ECL bias voltage to supply terminating voltage for input port resistor arrays 8 x 50Q see also sub section 4 1 2 1 N ote that general rules for bussing of ECL output ports require that only the last port on the bus has its pull down resistor installed 4 1 3 JUMPER SETTINGS There are three jumper blocks on the X LM 72 board that must be properly configured for a normal operation of the module These are the 3 pin J P34 on the top of the board front panel facing left the 6 pin JP35 close to the upper left corner of DSP TM 5
24. DSP the control over Bus B by writing 2 0000h into the VM EB us address 800000h iv releasing DSP from reset by writing 0 or 1 to VM EBus address 80 0004h v releasing the boot mode grant of bus B by writing 0 to VM EBus address 800000h see the warning below Warning Step v of the boot sequence via ASRAM B is of great importance as because of a hardware bug with Bus B allocated to DSP by the VME Bus XLM 72 has control of the VM E Bus data bus In fact in this state XL M 72 outputs the boot mode jumper setting on the VM EBus data bus bits 3 and 4 By the same token July 14 2003 Page 32 Manual XLM 72 mdo X LM 72 M AN 001 0 bug one should not attempt step iii and more generally the booting of the DSP when there is any activity on the VM E Bus data bus 4 6 TheINTERRUPT SYSTEM OF XLM72 XLM 72 features an interrupt system by which any single of its three masters V M EB us FPGA and DSP can request a specific action by any one of the two remaining masters The system includes a positive hand shaking mechanism by which the target device of the request may inform the requestor device of the status of the requested action The general strategy of the interrupt handling is as follows i The interrupt requestor device IRQSource places a 14 bit interrupt code argument IRQID in the dedicated interrupt request mailbox IRQM ail register for the desired interrupt target device IR QT arget IRQSource sets an in
25. ENTATION zoe tert e e Pa e at dnd 15 42 3 ENDIANNESS oie eee pee e RO E C dte d do ed rn T anne 16 4 3 SOFTWARE ACCESS OF INTERNAL DEVICES eene 16 431 ACCESSING INTERFACE REGISTERS me eret ee mo i ea 16 4 3 2 ACCESSING A SRAM Ss cis ct seront renti nnm ire ri rn 19 4 3 3 ACCESSING FPGK icio sinistrae inar deer 20 423 4 ACCESSING 20 44 PROGRAMMING OF THE USER 20 4 41 8 mter eerta rie 20 4 4 0 PED PORTS rennen iier nia 22 443 5 irritating irit i 22 4 44 entere rts 23 4 4 5 CONFIGURING FPGA ennt rientrare tenti arias 28 4 5 USING THE DSD inei cnni interni oo rie rernm irre niei raa 30 45 1 DSPADDRESS SPACE cemere rtt eren interner tari nena de 30 45 2 USER S GUIDE TO HOST PROCESSOR INTERFACE 30 45 3 DHEDSP BOOT PROCESS eren proie 32 46 ThelNTERRUPT SY STEM OF XLM 72 sse eene 33 46 1 WRITING TO IRQM ail REGISTERS eene 34 4 6 2 7 ISSUING OF SERVICE REQUESTS 34 46 3 SETTING OF THE IRQPENDING FLAGS enne 35 4 66 4 READING THE CONTENT OF THE IRQMAIL REGISTERS eee 35 4 6 5 CLEARING THE CONTENT OF THE IRQMAIL
26. ET ECLC lt 9 gt LOC P141 D 10 LOC P139 lt 11 gt LOC P138 D 12 LOC P137 UM TU UU ET ECLC ET ECLC ET ECLC ET ECLC D lt 13 gt LOC P136 lt 14 gt LOC P135 D 15 LOC P134 D 16 LOC P133 UM TU UU D 1 175 D 2 174 D 3 172 D 4 171 2 X3 XU ET ECL ET ECL ET ECL ET ECL lt 5 gt LOC P169 lt 6 gt LOC P168 D 7 LOC P167 D 8 LOC P166 QOQUUUUU ET ECL ET ECL ET ECL ET ECL lt 9 gt LOC P165 D 10 LOC P164 lt 11 gt LOC P163 D 12 LOC P162 CJ A X C7 PD lt 13 gt LOC P161 PD 14 LOC P159 PD 15 LOC P152 PD 16 LOC P151 X AU A 52 UU UU ri Bidirectional data bus connecting FPGA to the VME interface bus router 222222 ZZ CZ CZ ded eS eS Se VOZ Z CZ dc ZZ 2 ee ee 2 2 2 Z Z2 Zoe ZZ 2 eee ee eee 22 222 ET LOCDAPD 0 LOC P58 ET LOCDAPD 1 LOC P64 ET LOCDAPD 2 LOC P41 ET LOCDAPD 3 LOC P36 ET LOCDAPD 4 LOC P29 ET LOCDAPD 5 LOC P21 ET LOCDAPD 6 LOC P198 ET LOCDAPD 7 LO
27. Flash M emory with the content of ASRAM To program Flash M emory using Utility Configuration one must i Reset software protection of Flash memory see Section 4 5 1 1 ii acquire control of Buses B and X by writing 10002h into 800000h iii select sector to be programmed by writing its ID 1 3 into location 800008h iv load configuration data into ASRAM v write 0 into 40000Ch vi release control of Buses B and X by writing 0 into 800000h vii FPGA interrupt by writing into 820004h viii set software protection recommended July 14 2003 Page 37 Manual XLM 72 5 APPENDICES 5 1 USER CONSTRAINTS FILE UCF mdo X LM 72 M AN 001 0 The usage of FPGA pads is defined in the user constraints file UCF Part of such a file used by Utility Configuration is reproduced below AA I A pU UU ou rst sni bo Ce succ E cm t I HELL ES t July 14 2003 ET ECLEPD 1 LOC P102 ET ECLEPD 2 LOC P108 ET ECLEPD 3 LOC P2 ET ECLEPD 4 LOC P160 ET ECL17PD 1 127 ET ECL17PD 2 LOC2 P128 ET ECL17PD 3 LOC P129 ET ECL17PD 4 LOC P132 ET ECLAPD 1 LOC
28. GA Pad Red 84 LEDOPD 1 Green 82 LEDOPD 2 Y ellow 83 LEDOPD lt 3 gt 4 4 3 DSP INTERRUPT PORTS There are two lines connecting two pins of the FPGA to two interrupt pins of the DSP One of them NMIDX is used by the FPGA to drive the non maskable interrupt NM I of the DSP pad C13 of the DSP while the other one INT6DX drives the EXT INT6 pad D2 of the DSP Both DSP interrupts are edge driven by a low to high transition with a requirement for the level to be low for at least two system clock cycles and then high for at least two cycles In the UCF file see Appendix 5 1 the above two pins of the FPGA are labeled NMIDXOPD and INT6DXOPD respectively Their association with physical pins of the FPGA is shown in Table 5 below Table 5 DSP Interrupt pads of the FPGA Interrupt FPGA pin Interrupt FPGA pin NMIDX 171 INT6DX 176 July 14 2003 Page 22 Manual XLM 72 mdo X LM 72 M AN 001 0 4 44 INTERFACE PORTS With the exception of the two DSP interrupt signals discussed above the FPGA communicates with all internal devices as well as with the V M Ebus via the Interface i e has direct connections only with pins of the constituent CPLDs of the Interface These are 19 local address lines labeled in the UCF as LOCA DPD lt 2 gt LOCA DPD 20 32 local data lines labeled in the as LOCDAPD lt 0 gt LOCDAPD lt 31 gt and 20 control lines supplying s
29. GA is shown in Table 11 Table 11 Device selection pins of the FPGA Signal FPGA pin Signal FPGA pin Signal FPGA pin NSELA 76 NSELB 68 NSELV 47 4 4 4 7 INTERRUPT PORTS There are three interrupt lines interconnecting the FPGA and the Interface one dedicated for transmitting interrupt signals sent from the VMEbus to the FPGA NIRQXV one for transmitting interrupt signals sent from the FPGA to the VM Ebus NIRQV X and one for transmitting interrupt signals sent by the DSP to the FPGA NIRQXD The NIRQVX interrupt is not used in the present implementation of the Interface In the UCF the NIRQXV NIRQVX and NIRQXD pins are labeled NIRQXVIPD NIRQVXOPD and NIRQXDIPD respectively The association between the NIRQ signals and the physical pins of the FPGA is shown in Table 12 Table 12 Interrupt pins of the FPGA IRQ FPGA pin IRQ FPGA pin IRQ FPGA pin NIRQXV 49 NIRQVX 67 NIRQXD 80 July 14 2003 Page 27 Manual XLM 72 mdo X LM 72 M AN 001 0 4 4 4 8 WRITE READ CONTROL PORTS The Interface controls writing and reading of data into from the FPGA registers by means of two signals NSELXV and NWRX The mechanism is here very much the same as the one used by the FPGA to execute read and write operations In a write operation NWRX is low for the duration of the operation e g for the duration of block transfer while the NSELXV active low plays a role of the w
30. LA Reasonable combinations are NSELA NSELB NSELV NSELA and NSELB used for simultaneous writes to both ASRAM banks and transfers of data between these banks and NSELA and NSELB and NSELV used to program Flash Memory from ASRAM B and to read back the Flash Memory data into ASRAM B The combination NSELB and NSELV does not seem to have a reasonable application Define Read Write operation for ASRAMA Interface Flash Memory and ASRAMB Active low NET NWRAOPD LOC P69 When NWRA is low operations on ASRAM A Interface and Flash Memory are write operations and the data byte select signals NDBE0 3 must 1 cycle write strobes Else NDBE are 3 cycle chip enable ASRAM output enable signals are generated by the Interface NET NWRBOPD LOC P59 When NWRB is low operations on ASRAM B are write operations and the NDBE signals are 1 1 write strobes Else NDBE are 3 cycle 1 ASRAM output enable signals are generated by the Interface Timing of the write operations Place address and data on address and data buses X and pull the relevant NWRA and or NWRB low After one clock cycle pull the relevant NSEL low for one clock cycle write strobe For the write access to Flash Memory NSELV is to be asserted together with NWRA Address and data change i e c
31. NAL PROCESSOR inerti tree Ped dti tret naria 314 VMEBUSINTERFACE AND BUS ROUTER ARBITER eee 3 5 FLASH MEMORY iiidiicie eerie tiene 3 L6 ECL PORTS iiec teer eedem Hd bend Mini eai 31 7 6 ee nete nec orti en dte 9 2 BUSES deer oid ud de eri dde 3 21 INTERFACE TO ASRAM 5 4 tinent nte 32 2 INTERFACE TO FPGA teneo Henn o ter ir dde 3 2 3 INTERFACE TO DSP Heo tii eniin 3 24 INTERFAGE TO HPI BUS uenerit trementem tis 3 2 5 BUS ARBITRATION SCHEME reete eee nno die Pas 3 2 6 INHIBIT OF BUS ACCESS BY FPGA AND DSP icteric 10 3 32 VMEBUSADDRESS SPA CE erre ini T Dena 10 4 2 PR ette A d ennai 11 4 1 HARDWARE SETU Piocann na i trema ui ea d nnda 11 ALl IMPORTANT WARNINGS ehe b ini indies manta 11 412 5 5 e Feet fe tr te 12 413 tta rre he e e redet e rt ie e e A 14 4 2 ADDRESSING AND DATA FORMATTING CONVENTIONS 15 42 1 BIT NUMBERING IN ADDRESS AND DATA 15 42 2 ADDRESS REPRES
32. P in general the reset must be removed by writing 0 to V M EBus address 800004h Note that writing 2 to 800004h sets the DSP reset iii default X LM 72 powers up with DSP boot mode set to HPI regardless of the setting of DSP boot mode jumpers July 14 2003 Page 30 Manual XLM 72 mdo X LM 72 M AN 001 0 XLM72 is designed to take advantage of the Host Port Interface HPI of the TM S320C6711 Digital Signal Processor Via the HPI the XLM 72 user has access to internal registers of the DSP as well as to the whole address space The latter includes internal devices of XLM72 such as Interface ASRAM and ASRAM B Communication with HPI occurs through writing and reading to control HPC address HPA and data HPD registers of the DSP using part of the HPI address space set up in the Interface The target register and the direction of transfer read write are selected using 4 VM EBus address lines A2 A4 and A10 0 being the least significant bit These address lines connect via Interface to the HHWIL Half word Identification Select HCTL 1 0 Access Control Select and HRW Read W rite Select pins of the DSP as follows DSP Pin VME HHWIL A2 HHWIL 0 selects the first 16 bit halfword HCTL 0 A3 HCTL 0 selects HCTL 1 selects HPA HCTL 1 A4 2 3 select HPD with without address auto increment HRW 10 HRW 20 1 correspond to W rite R ead According to the above assignment HP maps ont
33. P107 ET ECLAPD 2 LOC P101 ET ECLAPD 3 LOC P100 ET ECLAPD 4 LOC P99 ET ECLAPD 5 LOC P98 ET ECLAPD 6 LOC P97 ET ECLAPD 7 LOC P96 ET ECLAPD 8 LOC P95 ET ECLAPD 9 LOC P94 ET ECLAPD 10 LOC P93 ET ECLAPD 11 LOC P92 ET ECLAPD 12 LOC P90 ET ECLAPD 13 LOC P89 ET ECLAPD 14 LOC P88 ET ECLAPD 15 LOC P87 ET ECLAPD 16 LOC P85 ET ECLBPD 1 LOC P126 ET ECLBPD 2 LOC2 P125 ET ECLBPD 3 LOC P124 ET ECLBPD 4 LOC P123 ET ECLBPD 5 LOC P122 ET ECLBPD 6 LOC P120 ET ECLBPD 7 LOC P119 ET ECLBPD 8 LOC P117 ET ECLBPD 9 LOC P116 ET ECLBPD 10 LOC P115 ET ECLBPD 11 LOC P114 ET ECLBPD 12 LOC2 P113 j it SGCK3 PGCK3 PGCK1 PGCK4 Page 38 Manual XLM 72 mdo X LM 72 M AN 001 0 ET ECLB ET ECLB ET ECLB ET ECLB D lt 13 gt LOC P112 D lt 14 gt LOC P111 D 15 LOC P110 D 16 LOC P109 ET ECLC ET ECLC ET ECLC ET ECLC D lt 1 gt LOC P150 D 2 LOC P149 D lt 3 gt LOC P148 D 4 LOC P147 UM TU UU D 5 146 lt 6 gt 145 D 7 LOC P144 D 8 LOC P142 UM 09 09 U0 ET ECLC ET ECLC ET ECLC
34. and must know or establish safe timing patterns for interacting with other internal devices via write read operations The interaction mechanism of the FPGA with other Devices is described in detail below 4 4 1 ECL PORTS As described in Section 4 1 XLM 72 features a total of 72 ECL ports organized in four 34 pin and one 8 pin header named A E respectively The ECL ports communicate exclusively with FPGA Ports E1 E4 are connected via the ECL TTL level translator to secondary global clock pin SGCK3 and primary global clock pins PGCK 3 PGCK 1 and PGCK 4 of the FPGA respectively They can be used to send dedicated clock signals to the FPGA but be used also as ordinary 1 0 5 For the actual numbers of the FPGA pins associated with individual ECL ports see Table 3 below and also Appendix A This appendix lists with abundant comments the relevant section of a user constraint file ucf that can be used at the implementation time of the July 14 2003 Page 20 M anual XLM 72 mdo X LM 72 M AN 001 0 FPGA code Note that the user has no particular interest in knowing the pin associations as the UCF file takes care of this task automatically provided the design uses the proposed naming scheme Table 3 Association between ECL ports physical FPGA pad numbers and their respective U CF names
35. ce July 14 2003 Page 36 Manual XLM 72 mdo X LM 72 M AN 001 0 iv write into location 820004h Interface Valid codes for operations relevant to the programming of Flash M emory are shown in Table 20 below Table 20 Operation codes relevant for Flash M emory operations Code Action by theFPGA 0 Program Flash M emory with the content of ASRAM B 5 Read data from Flash M emory into ASRAM B 6 Transfer content of ASRAM A into ASRAM B 8 9 R eset software protection of Flash emory Set software protection of Flash M emory 4 7 1 1 SOFTWARE PROTECTION OF FLASH MEMORY The data stored in Flash M emory may be protected from an inadvertent corruption by setting of software data protection The protection is achieved by writing a sequence of proper bytes into proper memory locations of Flash memory To induce Utility Configuration to execute such a sequence one must i acquire control of Bus X by writing 10000h into 800000h ii write 9 to location 40000Ch and ill issuethe FPGA interrupt by writing into location 820004h Reset of the software protection is achieved in a similar manner except in ii one would write 8 rather than 9 into location 40000C h 4 7 1 2 PROGRAMMING OF FLASH MEMORY FPGA has exclusive control of Flash M emory and thus in system programming of this memory is possible only via FPGA Utility Configuration can be induced to program any sector of
36. ction 4 3 1 2 and ili release reset for FPGA by writing 0 into location 800004h Section 4 3 1 2 Upon release of reset FPGA will attempt to boot from the selected sector of Flash Memory 4 4 5 3 CONFIGURING FPGA FROM ASRAM A To reconfigure FPGA from ASRAM one must i select ASRAM A as the FPGA boot source by writing 10000h into location 800008h Section 4 3 1 3 acquire control of Bus A by writing 1 into 800000h Section 4 3 1 1 i load the desired configuration file into ASRAM A v release control of Bus A by writing 0 into 800000h Section 4 3 1 1 v set reset for FPGA by writing 1 into location 800004h Section 4 3 1 2 and vi release reset for FPGA by writing 0 into location 800004h Section 4 3 1 2 Upon release of reset FPGA will attempt to boot from ASRAM A The above procedure has to be somewhat altered when FPGA is not yet configured In such a case in order to be able to acquire Bus A one must first inhibit the bus access by FPGA and DSP by writing 1 into location 80000Ch see Section 4 3 1 4 and then set July 14 2003 Page 29 Manual XLM 72 mdo X LM 72 M AN 001 0 reset for FPGA as in v above Subsequently one would have to perform i ii iii vi and cancel inhibition of bus access by FPGA by writing 0 into 80000Ch 4 5 USING THE DSP To use the DSP the user must prepare an executable suitable for downloading into the DSP and boot the DSP with this executable 4 5 1 DSP
37. device The association between the local data lines and the FPGA pins is shown in Table 8 below July 14 2003 Page 24 Manual XLM 72 mdo X LM 72 M AN 001 0 Table 8 Local Data pads of the FPGA Dataline FPGA Data line FPGA Data line FPGA Data line FPGA Pad Pad Pad Pad 0 58 8 200 16 61 24 9 1 64 9 19 17 65 25 24 2 41 10 30 18 28 26 27 3 36 11 194 19 37 27 196 4 29 12 179 20 23 28 178 5 21 13 193 21 22 29 181 6 198 14 191 22 197 30 180 7 20 15 187 23 199 31 188 In the UCF see A ppendix 5 1 local data pins are labeled LOC DA PD lt 0 gt lt 31 gt 4 4 4 4 BYTE ENABLE PORTS While the data are addressed in XLM 72 in 32 bit words there is a mechanism in place that allows one to access any arbitrary combination of bytes without affecting the remaining bytes One simply asserts a proper combination of data byte enable signals active low NDBEO lt 0 gt NDBEO lt 3 gt Note that since the index 0 refers to low data lines it refers in fact to high data byte numbers Big Endian For the most common and fastest 32 bit data transfer all four NDBEO lt 0 gt NDBEO lt 3 gt signals may be set permanently to 0 as they will be ultimately qualified within the Interface additionally by an appropriate device select signal to be generated by the FPGA In the UCF see Appendix 5 1 the data byte enable pins are labeled NDBEOPD lt 0 gt NDBEOPD lt 3 gt
38. e port Which in practical terms means that in any horizontal pair of sockets at most one should be filled Warning 2 When configuring input ports 10125 it must be ascertained that the corresponding ports of the FPGA are configured indeed as input ports and not as output ports In particular this applies to the default boot configuration of the FPGA active upon power up To avoid ports conflict right upon power up it is recommended to keep as the default boot configuration the general Utility Configuration supplied originally with XLM 72 or its possible update This Utility Configuration has no FPGA ports configured as outputs and hence guarantees that there is no conflict with any translator IC July 14 2003 Page 11 Manual XLM 72 mdo X LM 72 M AN 001 0 Warning 3 XL M 72 requires differential ECL inputs and will not function properly no damage will occur though with single ended ECL signals Which means among other things that these inputs cannot be driven by an ECL bus connected to ECL outputs of multiple external devices Warning 4 When configuring output ports make sure that the input polarizing resistor arrays for the particular quartets of ECL ports are removed from their respective sockets 4 1 2 CONFIGURING ECL PORTS ECL to TTL conversion input and TTL to ECL conversion output is accomplished by 16 pin MC10125 and MC10124 ICs respectively Each converter IC is capable of interfacing
39. e second read yielding the correct data In the case of reading in address autoincrement mode only first read needs to be preceded by the fetch command 4 5 3 THE DSP BOOT PROCESS On power up XLM 72 keeps the DSP in the state of reset To make use of the DSP the user must select the DSP boot mode by setting the DSP boot source jumper s J P35 for the desired mode and then performing the boot sequence proper for the selected mode There are four DSP boot modes available as labeled in silk screen on the XLM 72 board and as shown in Table 1 in Subsection 4 1 3 2 For XLM72 modules with DSPs of the C21 issue and not C13 the most convenient and hence advisable procedure of booting the DSP is to boot via the Host Processor Interface HPI To boot via HPI one must i release the DSP from reset by writing 0 or 1 to VM EB us address 80 0004h ii load the executable into the DSP memory space via HPI and iii release the DSP from the HPI boot mode Note that due to a hardware bug the HPI boot is insensitive to the jumper settings the setting being overridden by V M EBus data bits 3 and 4 that are expected to be 0 See also the warning below The remaining three boot modes involve ASRAM B as the boot medium and differ only in lengths of the boot data words These modes and require i loading of up to 1 kbyte of the executable into ASRAM B ii setting the boot mode jumpers to the desired mode ili granting the
40. e three buses at the same time one simply writes 0 to the same address 4 3 1 2 FPGA AND DSP RESET REGISTER AT 800004h The FPGA and DSP reset register at 800004h is a 2 bit write only register mapping onto bits 0 and 1 of the 32 bit VM EBus word Depending on what data are written into these two bits the Interface will set or release the reset signal of the FPGA or DSP The action is always simultaneous on both register bits involved 00000001h 00000002h Set Reset for the FPGA RESFPGA Set Reset for the DSP RESDSP Reset signals are released by setting the associated bits to 0 Example To only set the Reset for the FPGA one must write RESFPGA OR RESDSP OR IRQFPGA OR IRQDSP 1 to the memory location 800004 To release this reset one writes 0 to this memory location Note that the latter causes then the FPGA to boot from the selected boot source 4 3 1 3 FPGA BOOT SOURCE SELECTOR REGISTER AT 800008 The FPGA boot source selector register is a write read 4 bit register mapping onto bits 0 1 16 and 17 of the 32 bit VM EBus word July 14 2003 Page 18 Manual XLM 72 mdo X LM 72 M AN 001 0 Select sector 0 of flash memory BOOTO 00000000h Select sector 1 of flash memory BOOTI 00000001h Select sector 2 of flash memory BOOT2 00000002h Select sector 3 of flash memory BOOT3 00000003h Select ASRAM A BOOTA 00010000h The BOOTA bit overrides the other BOOT bits that might be set Example To select ASRAM A as a boot
41. eling two ejector handles with anodized blue ID plates Power Requirements 5V at approximately 1 5 A 5 2V at approximately 600 mA 2V at approximately 100 mA Depends ECL port usage July 14 2003 Page 5 Manual XLM 72 mdo X LM 72 M AN 001 0 3 ARCHITECTURE XLM 72 features a number of distinct devices interconnected by address data and control buses in star like topology Two devices the FPGA and the DSP may serve along with the VM EBus as bus masters assuming and releasing control of the buses according to user programmable routines A block diagram of XLM 72 is illustrated in Fig 1 Fig 1 Block diagram of XLM 72 Interaction of devices and routing of buses is discussed in Sections 3 1 and 3 2 further below 3 1 DEVICES XLM 72 features eight distinct devices five of which are addressable via VM EBus The addressable devices include i ii two banks of fast asynchronous static random access memories ASRAM iii one Field Programmable Gate Array FPGA iv one floating point digital signal processor DSP more accurately the host processor interface H PI of this processor and July 14 2003 Page 6 Manual XLM 72 mdo X LM 72 M AN 001 0 v a V M Ebus Interface and Bus A rbiter R outer A rray Interface The non addressable by V M EB us devices are accessible to the user FPGA and include vi one flash memory to store configuration data for the FPGA vii an array of 72 ECL port
42. er at rates of up to 40 M bytes s Further XLM 72 features two banks of fast asynchronous static random access memory ASRAM 2 M bytes each accessible to VM EBus FPGA and DSP and it features an on board 2 M byte EEPROM or flash memory allowing one to store up four FPGA configuration files Few digital applications are out of XLM 72 range 1 1 SUMMARY OF FEATURES e 72 programmable front panel ECL ports configurable in quartets as either inputs or outputs organized in four 34 pi and one 8 pin headers Four ports can be configured as external clock ports supporting rates of up to 110 M Hz Oneuser programmable FPGA 540 1 5 0208 by X ilinx Inc e One user programmable floating point DSP TM S320C6711 by Texas instruments rated at 900 M flops s e 2 banks of fast asynchronous SRAM 2 M bytes each addressable in 32 bit 16 bit and 8 bit words e A custom programmable in system reconfigurable V M EB us interface and bus router arbitrator e One2 M byte programmable erasable read only memory holding up to four FPGA configuration files e Four front panel LEDs one indicating VMEBus operation and the remaining three being user programmable mapped onto ports of the user FPGA July 14 2003 Page 3 Manual XLM 72 mdo X LM 72 M AN 001 0 1 2 POSSIBLE APPLICATIONS FERA Controller D ata B uffer Intelligent D ata B uffer Scalers Prescalers Coincidence R egisters Time Stampers M ultilevel Trigger Logics
43. ffer the capability of a fast hardware conversion between the big and little endian formats With this in mind the present manual uses little endian format i e all data discussed further below are represented in little endian format 4 3 SOFTWARE ACCESS OF INTERNAL DEVICES 4 3 1 ACCESSING INTERFACE REGISTERS The use of the memory space of the Interface is fixed by the Interface firmware at the design or upgrade time The VM Ebus must write to proper locations of this space to accomplish the following tasks i Request control of any of the three shared internal buses that are subject to bus arbitration Bus A Bus B and Bus X see also Section 3 2 ii Issue interrupt signals to the DSP and FPGA and toggle reset lines for these devices iii Write the interrupt request ID to the proper IRQ mailbox July 14 200 Manual XLM 72 mdo X LM 72 M AN 001 0 iv Select the warm boot source for the FPGA which is either one of the 4 banks of the Flash Memory or ASRAM A See also Section X v Snatch the bus control from the FPGA and the DSP vi Resetthe FPGA and DSP Interrupt Service Registers and Flags The VM Ebus must read from proper locations of the address space to accomplish the following tasks Check if the requested control of any of the buses has been indeed granted i Check what the actual FPGA boot source is ii Check the actual ownership of the three arbitrated buses v Poll the Interrupt Se
44. he asserted NSEL signals NSELA alone i NSELB alone ii NSELV alone v NSELA and NSELV v NSELA and NSELB and vi NSELA and NSELB and NSELV i and ii are used to achieve transfer of data between the FPGA and the individual ASRAM s iii is used to access the FPGA interrupt service register and the associated July 14 2003 Page 26 Manual XLM 72 mdo X LM 72 M AN 001 0 flag in Interface The combination iv is used e g by Utility Configuration to write data into the Flash M emory The combination v allows simultaneous write by the FPGA into both ASRAMS or a transfer of data between the two ASRAMs while the combination vi is intended for data transfer operations between ASRAM B and the Flash M emory programming of the Flash M emory with a configuration file stored in ASRAM B or read back of the content of the Flash M emory into ASRAM B Note that an access of the Flash Memory involves asserting both NSELA and NSELV For operations on the Flash M emory the user is encouraged to use the default cold boot Utility Configuration residing in bank 0 of the Flash M emory Note that ASRAM A shares NWRA line and the Output Enable line with the Flash Memory which precludes transfer of data between ASRAM A and the Flash M emory These two devices have however separate chip enable signals which allows one to access any one of them individually The correspondence between the NSEL lines and the physical pins of the FP
45. ignals necessary for executing various operations The address and data signals when accompanied by proper combination of control signals propagate via Interface to address and data pins of a desired ASRAM or Flash M emory while the Interface provides the output enable OE chip enable CE and write WR signals necessary for accessing any device It is important to appreciate that the local address and data lines are bi directional and therefore bi directional pads and tri state buffers must be used by the FPGA to connect to these lines It is then up to the user to provide for proper enable signals for these buffers to achieve the desired result and more importantly not to cause a prolonged bus contention 4 4 4 1 BUS ARBITRATION PORTS Since internal devices of XLM 72 can be accessed by up to three different masters VMEbus FPGA and DSP the presence of a reliable arbitration scheme is absolutely necessary The user FPGA code must comply with the simple rules of bus arbitration not to cause prolonged bus contention that can lead to a destruction of components of XLM 72 The arbitration scheme of XL M 72 is based on the first come first serve release when done principle Therefore every access of any internal device of XLM 72 by the FPGA in fact by any master must be preceded by a request issued to the Interface for exclusive control over the needed bus es followed by a verification that such an access has been indeed granted Natu
46. lock address counter at the trailing edge of NSEL strobe For block transfers most common use NWR can be kept continuously low Also NSELV is continuously low in block transfers to from the Flash Memory Note that one transfer takes 3 clock cycles resulting in a transfer rates of up to 107 MBytes s Timing for read operations Place address on address buse X and assert the relevant NSEL Keep NWR continuously high The data is ready at the data bus after 2 cycles In block transfers keep control signals continuously asserted while clocking for one cycle the address every third cycle July 14 2003 Page 41 Manual XLM 72 mdo X LM 72 M AN 001 0 Request bus mastership of ASRAMA ASRAMB or Interface only Active OW ET NREQAOPD LOC P46 ET NREQBOPD LOC P45 ET NREQXOPD LOC P62 Interface Note that to acces ASRAM A or ASRAM B the FPGA must control bus X also as it supplies both data and address to ASRAM banks via bus X requests bus A and bus X requests bus B and bus X requests bus X alone for the access to Zu UL uu HE ob od Bus mastership granted for operations on ASRAMA ASRAMB or Interface only Clocked by LE of the system clock NET ACKAIPD LOC P75 NET ACKBIPD LOC P70 NET ACKXIPD LOC P57 The FPGA must check if bus es are granted before proceeding with ASRAM and Interafce access operations
47. lt 18 gt NE LOCADPD lt 19 gt NE LOCADPD lt 20 gt Data byte selec Signals ASRAMA Connect to the NET NDBEOPD 0 Endian formatted NET NDBEOPD 1 NET NDBEOPD 2 NET NDBEOPD 3 LOC P por LOC P35 LOC P32 LOC P31 LOC P10 LOC P12 TOCS PLA LOC P14 LOC P15 P42 P7A PIB P40 P43 P39 to RAMB ace 72 44 63 81 24 P27 P196 P178 P181 P180 P188 mdo X LM 72 M AN 001 0 P194 P179 PIO3 1 901 187 61 POS P28 P37 P23 P22 P197 P199 ress bus connecting FPGA to the VME interface bus 184 186 185 190 189 be used in conjunction with device select Active low most significant byte in 32 bit Big Select internal device of XLM72 more than one may be selected at time ASRAMA ASRAMB Interface Regis July 14 2003 ters or Flash Memory Active low NET NSELAOPD LOC P76 Page 40 Manual XLM 72 mdo X LM 72 M AN 001 0 NSELA selects ASRAM A when alone or when in conjunction with NSELB selects Flash Memory when in conjunction with NSELV NET NSELBOPD LOC P68 NSELB selects ASRAM B when alone or when in conjunction with NSELA or NSELV NET NSELVXOPD LOC P47 NSELV selects Interface when alone or when in conjunction with NSELB selects Flash Memory when in conjunction with NSE
48. nicates with the Interface via a bus named Bus D featuring 19 address 32 data and 11 control lines Bus D is controlled exclusively by the DSP 3 24 INTERFACE TO HPI BUS The Host Processor Interface HP of the DSP communicates with the Interface via a bus named B us H featuring 16 data and 7 control lines Bus H is controlled exclusively by the VM EBus 3 25 BUS ARBITRATION SCHEME Buses A B and X can be controlled by more than one master and consequently an arbitration scheme is provided by the Interface to guarantee each of the three masters the July 14 2003 Page 9 Manual XLM 72 mdo X LM 72 M AN 001 0 VM EBus FPGA and DSP access to these buses while avoiding bus contention The arbitration scheme is based on the first come first serve release when done principle whereby the masters are granted control of buses on first come first serve principle and are required to release the control upon completion of their task M asters post their bus requests in the respective bus request registers of the Interface The requests are placed on the queues associated with individual buses and are granted as soon as the bus involved becomes available The grant of the bus control is signaled to the requesting master by the content of the respective bus grant register The requesting master upon detection of the bus grant signal takes control of the bus performs the intended task and removes its request from the request registe
49. o V M EBus address space as follows VMEBus Address HPI Function 600000h Write first half word into HPC 600004h Write second half word into HPC 600400h Read first half word from HPC 600404h R ead second half word from HPC 600008h Write first half word into HPA 60000Ch Write second half word into HPA 600408h Read first half word from HPA 60040Ch Read second half word from HPA 600010h Write first half word into HPD with addr autoincr 600014h Write second half word into HPD with addr A utoincr 600410h Read first half word from HPD with addr autoincr 600414h Read second half word from HPD with addr A utoincr 600018h Write first half word into HPD fixed address 60001Ch W rite second half word into HPD fixed address 600418h Read first half word from HPD fixed address 60041Ch Read second half word from HPD fixed address Note that in order to write read to from any address location of the DSP address space one must first load the desired address into HPA and for the write operation load the data into HPD July 14 2003 Page 31 Manual XLM 72 mdo X LM 72 M AN 001 0 Reading from the HPI is somewhat tricky due to bugs in the DSP silicon It works however reliably for the silicon version C21 provided after loading the address register and before reading from HPD one writes the fetch bit into the control register i e writing 10h into VM EBus address 60 0000h Alternatively one could read from HPD twice th
50. o be loaded into ASRAM A or ASRAM B in the case of Flash M emory programming see Section 4 5 The mapping is shown in Table 14 below July 14 2003 Page 28 Manual XLM 72 mdo X LM 72 M AN 001 0 Table 14 M apping of 8 bit raw configuration data bytes onto 32 bit words Bit zin Raw 8 bit Word 0111231415617 Bit zin 32 bit Word 2134 10 18 19 20 26 Note that raw byte FFh converts to a 32 bit 41C041Ch configuration word Furthermore the header part of the raw data file has to be skipped and only the configuration data proper converted and loaded into target ASRAM To perform this stripping one has to rely on the fact that the first data word to be converted is FFh decimal 255 which means that a conversion program must skip all bytes read from a raw configuration file until it encounters FFh 255 Note also that second valid byte is always 0 4 4 5 2 CONFIGURING FPGA FROM FLASH MEMORY Upon power up FPGA attempts to boot configure itself from the default boot sector of Flash Memory Whether such a boot is successful or unsuccessful one may force FPGA to boot from a desired different sector of Flash To this end one must i select the desired boot sector by writing its ID 0 3 for the four sectors available into location 800008h see Section 4 3 1 3 ii set reset for FPGA by writing 1 into location 800004h Se
51. peration ID 10h Upon interrupt FPGA waits until the IR QPending flag of the Interface is cleared indicating that previous request is completed and then writes bits 2 7 of the utility register at 400004h into the Interface IRQ Mailbox register bits 2 7 of this register are allocated to the FPGA Writing of these bits sets also the IRQPending flag 5 2 2 TEST DATA PATTERNS Utility Configuration allows one to write various test data patterns into ASRAM s using operation IDs as indicated in Table 21 above Pattern A consists of bits 2 17 of the address placed in both lower and upper 16 bits of data words Pattern B is equal to the content of the Utility Configuration register at 400004h The desired pattern must be entered into this register prior to executing the FPGA interrupt Pattern C is similar to B except alternating with 00000000h for consecutive addresses Pattern D is similar pattern A except upper 16 bits being 0000h Pattern E is similar to pattern A except lower 16 bits being 0000h July 14 2003 Page 44
52. r making the bus available to the master that is first in the queue 3 2 6 INHIBIT OF BUS ACCESS BY FPGA AND DSP The Interface provides the EBus with the capability to inhibit the control of buses by the remaining two masters the FPGA and the DSP In other words the VM EBus can at will snatch the bus control already in progress from the FPGA and or DSP so as to allow it to perform urgent or emergency tasks of its own The response of the FPGA and the DSP to the bus snatching is at the discretion of the user and is to be programmed into the FPGA and the DSP respectively A reasonable programming is assumed to detect the occurrence of snatching and provide for its smooth handling e g the abortion of the current operation and release of the request or when feasible suspension of the current operation and its resumption upon removal of the bus grant inhibit 3 3 VMEBus ADDRESS SPACE The address spaces of the five addressable devices of XLM 72 are defined by 24 bits A0 A23 of the complete V M Ebus address bits A 24 A 26 being disregarded and bits A 27 31 carrying the geographical address of X LM 72 ASRAM A 000000h 1FFFFCh ASRAM B 200000h 3FFFFCh FPGA 400000h 5FFFFCh used freely at user s discretion DSP HPI 600000h 7FFFFCh most of which is unused INTERFACE 800000h 9FFFFCh most of which is unused July 14 2003 Page 10 Manual XLM 72 mdo X LM 72 M AN 001 0 4 OPERATING INSTRUCTIONS
53. rally grant of control over a bus to one master automatically denies control over this bus to any competing masters At the conclusion of the access the FPGA must remove the request which releases the bus for subsequent arbitration There are three bus request lines associated with the three internal buses Subject to arbitration These three buses are i Bus A interconnecting Interface and ASRAM A ii Bus B interconnecting Interface and Bus B and ii Bus X interconnecting Interface and the FPGA The bus interconnecting Interface and the DSP is owned exclusively by the DSP and is hence not subject to arbitration The bus request signals are active low so a non configured FPGA does not generate a false request With each of the three bus request lines associated is a respective bus grant signal active high The bus grant signals are synchronized to the leading edge of the system clock It is absolutely essential that the user configuration of the FPGA conditions enabling of local address lines of the FPGA by the presence of high on the Bus X grant line as the Interface cannot here provide protection from a contention on bus X Also the user configuration must make sure that the local data buffers are not enabled when Interface is writing into the FPGA registers Since the control of the FPGA over bus A or over bus B always involves its control also over bus X a request for bus X for the FPGA is generated automatically by the Interface i
54. rite strobe User configuration may then utilize the leading edge of the NSELXV to register the local data LOCDAO 31 into registers identified by the local address LOCA D 2 20 In read operations NWRX is high and NSELX is low for the duration of the operation User configuration must then respond by placing the content of the addressed register on the local data bus and enabling the associated tri state drivers In this case it is the Interface that is in control of the timing In UCF the NWRX and NSELX pads are named NWRXIPD and NSELXIPD respectively Their association with physical pins of the FPGA is shown in Table 13 below Table 13 Write read to from FPGA control pads Control line FPGA Pad Control line FPGA Pad NWRX 34 NSELX 48 4 4 5 CONFIGURING FPGA XLM 72 offers three ways of configuring FPGA i via port see Section 4 1 3 1 ii from Flash Memory and iii from ASRAM Programming via the JTAG port is intended primarily for debugging purposes and requires dedicated equipment software and download cable and therefore is not discussed in this manual 4 4 5 1 CONFIGURATION DATA FILE When configuring FPGA from ASRAM A or programming Flash M emory a properly formatted configuration data file is needed FPGA programming software allows one to generate binary configuration data as an array of 8 bit words These 8 bit data words have to be properly mapped onto 32 bit words t
55. rol by FPGA and DSP 810000h Bus A ownership register read only 810004h Bus B ownership register read only 810008h Bus X ownership register read only 820000h Clear IRQ M ailboxes and the associated flags write only 820004h Interrupt FPGA write only 820048h Serial number read only 820824h M ailbox register read only 821048h DSP mailbox and interrupt write only July 14 2003 Page 17 Manual XLM 72 mdo X LM 72 M AN 001 0 The significance of data written to or read from the valid locations of the Interface address space is discussed in detail in sub sections 4 3 1 1 4 3 1 9 below 4 3 1 1 BUS CONTROL REQUEST REGISTER AT 800000h The bus control register located at 800000h is a 3 bit register mapped onto bits 0 1 and 16 of the 32 bit VM EB us word When set by Write operation they indicate to the bus arbitrator the request by the V M EBus of the control of an arbitrated bus Request Bus A REQA 00000001h Request B us B REQB 00000002h Request Bus X REQX 00010000h Request Bus B for DSP REQD 00020000h To release a bus its respective request bit must be set to 0 Note that the Interface will always simultaneously set and or release requests of all three buses depending on which of the four bits 0 1 16 and 17 are set and which are reset Example a combined request of all three buses of 72 is achieved by writing REQA OR REQB OR REQX 00010003 to the address 800000 To release all thes
56. rvice Registers of the FPGA and DSP for the presence of service requests iie Addressing of the Interface registers may appear somewhat peculiar due to the fact that the Interface is implemented in four Complex Programmable Logical Devices CPLDs each of which has access only to a portion non contiguous of the VM EBbus address bus For example the M aster CPLD controlling the Interface logics has access only to the V M Ebus data lines DO D1 D16 and D17 as well as to the address lines A 1 A2 A3 A16 and A17 Which is why with few exceptions accessing of the Interface is accomplished over the data lines 00 01 016 and 017 and address lines A2 A16 and 17 accounting for the apparent peculiarity of the Interface addressing and data scheme A ddresses of the Interface registers are shown in Table 2 below Note that bit 23 is always set to 1 to select the Interface as the target device Note also that to form a complete V M Ebus address the 24 bit addresses shown in Table 2 must be pre pended by a 5 bit geographical address followed by three don t care bits Table 2 Use of the Interface address space Address bits Registers accessed or action induced A0 A 23 800000h Bus control register and IRQ flags write read 800004h FPGA and DSP reset register write only 800008h FPGA boot source register write read 80000Ch Inhibit flag for the bus cont
57. s and viii an array of four front panel diagnostic light emitting diodes 3 1 1 ASYNCHRONOUS STATIC RANDOM ACCESS MEMORY XLM 72 features two banks of fast asynchronous static random access memory referred to as ASRAM A and ASRAM B Both banks are identical and consist of four CY 7C1024B 15VC ICs manufactured by Cypress Semiconductor Inc providing for 2 M bytes of storage capacity each They are configured as 32 bit wide memory but can be also accessed in half words by both VM EBus and by the DSP and by half words and byte wise by the FPGA 3 1 2 FIELD PROGRAMMABLE GATE ARRAY The desired logical operations of XL M 72 are to be programmed by the user into a X ilinx X CS40X L 5PQ208C field programmable gate array chip FPGA Any logic that can be implemented as synchronous state machine or combinatorial equation may be programmed subject only to the availability of resources of the XCS40XL chip which are quite vast These resources include among other things 1862 logic cells i 40 000 system gates ii 1784 complex logic blocks v 2 016 flip flops and v Fast Carry Logic pP The FPGA is clocked at 80 MHz from an on board clock but can be also clocked externally via one of four special ECL ports at rates of up to 110 M Hz The FPGA can access Interface registers and both banks of ASRAM Further it has exclusive control of Flash M emory of all ECL ports and of three out of four front panel diagnostic LEDs
58. s relevant IRQM ail registers by writing to the Interface addresses shown in Table 15 Table 15 IRQM ail registers for various IR Q Sources IRQSource IRQTarget IRQMail Address for IRQSource VMEBus FPGA IRQM ail to be set up in FPGA by User VMEBus DSP 82 1048h FPGA DSP 00 0824h FPGA VME 00 1048h DSP VME A000 0824h DSP FPGA A003 1048h The desired IRQID data are to be placed on bits 2 15 of the data word written into the IR QM ail register 4 62 ISSUING OF SERVICE REQUESTS For polling based interrupting it is sufficient for an IRQSource to write the desired IRQID data to the respective IRQM ail register For a direct interrupting available for the DSP and the FPGA as target devices the interrupt signal is generated automatically in some cases VM EBus gt DSP DSP gt FPGA upon writing into the respective IRQM ail registers see Table 16 In the case of VM EBus requesting service by the FPGA where no dedicated mail box is set up within the Interface V M EB us must write dummy write into Interface address 62 0004h In the case of the FPGA interrupting DSP User must configure the FPGA to toggle one of the two interrupt pins INT6DXOPD 177 or NMIDXOPD connected directly to the INT6 and NMI non masked interrupt pins of the DSP Obviously toggling of the desired interrupt pin can occur concurrently with writing the FPGA to the respective IR QM ail register associated with the
59. source of the FPGA one must write BOOTA 00010000h to the memory location 800008 4 3 1 4 BUS CONTROL INHIBIT FLAG FOR FPGA AND DSP AT 80000Ch Writing 1 to 80000Ch inhibits bus control by the FPGA and DSP and makes all buses A B and X unconditionally available to the VM EBus To actually gain the control of the desired bus VM EBus must still request control of the bus Writing 0 to 80000Ch removes inhibit and allows the FPGA and DSP to compete for the bus control 4 3 1 5 BUS OWNERSHIP REGISTERS AT 810000h 810004h AND 810008h Bus ownership registers at 810000h 810004h and 810008h are 2 bit read only registers storing data identifying the actual owner of Bus A B and X respectively The returned values of 0 1 2 and 3 indicate free status and control by the V M EBus FPGA and DSP respectively 4 3 1 6 72 SERIAL NUMBER REGISTER AT 820048h The serial number register at 820048h is an 11 bit read only register storing the XLM 72 serial number This number is returned in bits 0 10 of the 32 bit data word 4 3 1 7 INTERRUPT SYSTEM REGISTERS AT 820000h 820004h 820824h AND 821048h The significance and use of Interface addresses 820000h 820004h 820824h and 821048h is discussed in detail in subsection 4 6 4 3 2 ACCESSING ASRAMs One accesses either of the two ASRAMs by writing to or by reading from a desired memory location mapped onto the respective V M EBus address space of the ASRAM of July 14 2003
60. terrupt pending flag IRQPending i IRQSourceissues the service request to IRQT arget v IRQTarget executes the requested operation v IRQTarget clears the relevant IRQM ail register and the IR QPending flag vi IRQSource monitors IRQPending flag for the status of the requested service The minimum action needed comprises of ii and iii performed always simultaneously by the XLM72 firmware The remaining steps are optional with step vi being recommended and perhaps dictated by common sense There are two ways of issuing a service request First is based on the polling of the IRQMail register by IRQTarget and is available in any IRQSource IRQTarget combination The second mechanism is based on the use of interrupt signals on dedicated interrupt lines and is not available in the present XLM72 firmware for requests involving VM EBus as IRQTarget The second mechanism appears advisable for requests involving DSP and FPGA as IRQTargets As IRQSource each of the three masters of XLM72 has available two write only IRQM ail registers and two write only IRQPending flags one for each of the remaining two masters As IRQTarget each of the three masters of XLM 72 sees one read write IRQM ail register and two clear only IRQPending flags physically the same registers and flags accessed by the IRQSource July 14 2003 Page 33 Manual XLM 72 4 6 1 mdo X LM 72 M AN 001 0 WRITING TO IROMail REGISTERS IRQSources acces
61. the device Note that 21 bits are needed to make use of the full capacity of individual ASRAM banks Therefore further below for the sake of simplicity all addresses are expressed in the form of 5 digit hexadecimal numbers with a tacit understanding that a full VM EBus address has always bits 24 through 26 set to zero and that bits 27 through 31 encode geographic address 4 23 ENDIANNESS Endian is a term commonly used to describe the way multi byte data words are stored in memory VM EBus is inherently big endian such that bytes of increasing hierarchy are stored at memory locations of decreasing addresses Which means that the most significant byte of a multi byte word is stored at lowest memory location and the least significant byte at highest memory location Accordingly data bytes of highest significance are transferred over V M EBus data lines of lower indices And so in 32 bit transfers the most significant byte is transferred over data lines 0 07 the second most significant byte over data lines D8 D 15 the second least significant byte over data line D 16 D 24 and the least significant byte over data lines D25 D31 Similarly in 16 bit transfers the most significant byte is transferred over data lines 00 07 and the least significant byte over data lines 0 8 0 15 On the other hand modern PC s are mostly little endian such that higher hierarchy bytes occupy higher memory locations Also modern VME crate controllers often o
62. the interrupt system it is necessary that upon completion of the request the IR QTarget clears the relevant bits of the IRQM ail register and the associated IRQPending flag The clearing of the register and the associated flag is achieved by writing proper data into a designated location within the Interface address space as shown in table 18 Table 18 Addresses and Data for clearing IR QM ail registers and IR QPending flags IRQTarget IRQSource Address Data VMEBus FPGA 82 0000h 824h VMEBus DSP 82 0000h 1048h FPGA DSP Oh 824h July 14 2003 Page 35 Manual XLM 72 mdo X LM 72 M AN 001 0 FPGA VME Oh 1048h DSP VME A000 0000h 824h DSP FPGA A000 0000h 1048h 4 6 6 INSPECTING THE IRQPENDING FLAGS For a sound operation of the interrupt system it is advisable for the IR QSource to inspect the status of the IRQPending flag before undertaking further operations that might depend upon completion of the requested service by the IRQTarget The IRQFlags occupy bits 10 and 26 of the status register at address 0 of the Interface address space The correspondence between these two bits and the IRQTargets is shown in Table 19 Table 19 Correspondence between bits of the status register and the IRQ Targets IRQSource Addr of Status Reg IRQTargetfor Bit 10 IRQTarget for Bit 26 VMEBus 80 0000 DSP FPGA Oh DSP VMEBus DSP A000 0000h VMEBus FPGA
63. tself whenever the FPGA requests either bus A or bus B July 14 2003 Page 23 Manual XLM 72 mdo X LM 72 MAN 001 0 In UCF see Appendix 5 1 the bus A B and X request pads are labeled NREQAOPD NREQBOPD and NREQXOPD respectively while the associated grant pins are labeled ACKAIPD ACKBIPD and ACKXIPD The association between the above arbitration signals and the FPGA pad numbers is shown in Table 6 below Table 6 Bus arbitration pins of the FPGA Bus Request FPGA pin Bus Grant FPGA pin A 46 A 75 B 45 B 70 X 62 X 57 4 4 4 2 LOCAL ADDRESS PORTS Local address lines are used to transmit address bits between the FPGA and the Interface under assumption that these address bits will propagate via the Interface to the target device The association between the local address bits and the FPGA pins is shown in Table 7 below Table 7 Local Address pads of the FPGA Address FPGA Address FPGA Address FPGA Address FPGA bit Pad bit Pad bit Pad bit Pad 2 35 7 11 12 186 17 73 3 32 8 14 13 185 18 40 4 31 9 15 14 190 19 43 5 10 10 42 15 189 20 39 6 12 11 184 16 74 In UCF see Appendix 5 1 local address pins are labeled LOCA DPD lt 2 gt lt 20 gt 4 4 4 3 LOCAL DATA PORTS Local data lines are used to transmit data bits between the FPGA and the Interface under assumption that these data bits will propagate via the Interface to the target
64. up to four differential ECL ports to respective four TTL ports of the user FPGA Differential inputs of these ICs are directly connected to respective pairs of pins of front panel headers T he headers are identified going from top to bottom by labels A B C D and E respectively while individual ports within a header are identified by numbers 1 through 17 ports A D or 1 through 4 port E It is important to note that as indicated on the front panel of XLM 72 port 1 of each of the five headers is represented by the bottom pair of pins of the header and thus for example ports A 1 A4 are the four bottom pairs of pins of the top most 34 pin header As indicated by silk screen labels printed right below each of the two columns of 18 16 pin sockets the input translators are to be placed into sockets in the right most column while the output translators are to be inserted into sockets of in the left most column The correspondence between the sockets and the ECL ports is indicated by silk screen labels printed between the two columns of 16 pin sockets Note that 17 th ports top most of headers A D are associated with the pair of sockets labeled A 17 D17 9 th pair from top In addition to translator ICs proper functioning of ECL ports requires either impedance matching resistor arrays of 8 x 50Q input ports or pull down resistor arrays of 8 x 4700 output ports These two types of arrays share Zig Zag sockets with the exception of
65. writing 0 into location 800000h Interface viii generate FPGA interrupt by writing into 820004h In Table 21 below are listed all IDs of all operations that are performed by the utility program Table 21 V alid operation codes of Utility Configuration Action by theFPGA Program Flash M emory with the content of ASRAM B Transfer content of ASRAM B into ASRAM A Fill ASRAM A with data pattern A Transfer content of ASRAM A into ASRAM B 0 3 4 5 Read data from Flash M emory into ASRAM B 6 7 Fill ASRAM B with data pattern A 8 Manual XLM 72 mdo X LM 72 MAN 001 0 Table 21 Continuation Code Action by theFPGA 64h Fill ASRAM A with data pattern D 84h Fill ASRAM A with data pattern E 24h Fill ASRAM B with data pattern B 44h Fill ASRAM B with data pattern C 64h Fill ASRAM B with data pattern D 84h Fill ASRAM B with data pattern E 5 2 1 WRITING TO THE IR MAILBOX OF INTERFACE Utility Configuration allows also one to test the functioning of the interrupt service request system in which the FPGA communicates its request by writing a code into the IRQ Mailbox register within Interface VMEBus detects this request by periodically polling this register executes the desired operation and clears the register and its dirty flag see Section 4 3 1 7 To write into the FPGA IRQ Mailbox register one must issue an FPGA interrupt with o

XLM72 User`s Manual Revision B - JTEC

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