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USER`S MANUAL - 13thmonkey.org

1. g S 2 lt 3 x a 2 Tre 4 Figure 24 24 SDRAM Auto Refresh Timing Trp ELECTRONICS 24 22 ELECTRICAL DATA 53 2410 2 Tcl 2 2 Tred Figure 24 25 SDRAM Page Hit Miss READ Timing Trp 24 23 ELECTRONICS 3 2410 ELECTRICAL DATA ADDR BA 5 D i o 9 5 o 5 o o o o o 2 5 5 5 2 o 2 Tre 4 Figure 24 26 SDRAM Self Refresh Timing Trp ELECTRONICS 24 24 ELECTRICAL DATA S3C2410A lt m Q lt 2 Trcd 2 Figure 24 27 SDRAM Single Write Timing Trp 24 25 ELECTRONICS 3 2410 ELECTRICAL DATA dV 0OLV I I I 1 I l I l I l I l I I I l I I I l I I I I I l l lt vg daav 2 Tcl 2 2 Tred Miss Write Timing Trp 28 SDRAM Page Hit Figure 24 ELECTRONICS 24 26 53 2410 ELECTRICAL DATA xx CADH I XnXDACK 1 b Read X Write P Rest rte NES Wite Figure 24 29 External DMA Timing Handshake Single transfer Tf2hsetup i Tf2hhold I 1 Tl2cs
2. 3 59 Pseudo Random Binary Sequence Generator ara 3 61 Multiplication by Constant Using the Barrel Shifter a 3 61 Loading Word from an Unknown 3 63 Chapter 4 Thumb Instruction Set vi Thumbiinstr cti n Set ee SERERE Se RARE 4 1 Format Summary rc ere 4 2 4 3 Format 1 Move Shifted Register n 4 5 allori a lE 4 5 Instr ction Gy Cle TIMES xeu RE ce edes bae reda Dae Rie 4 6 EXxampleS o ntpote eum tta eit E 4 6 nan ta ka noa epe ese taa de s 4 7 Operation ess 4 7 INStrUCtION CYCle TIMES Sse oe TEE 4 8 aber S hua aa kutana 4 8 Format 3 Move Compare Add Subtract Immediate sss eee 4 9 PEE S tun 4 9 Instruction Cycle xe 4 10 DISS ites vaste Gav caves un ua fen em scent icis 4 10 Format 4 ALU Operations
3. 2 11 2 11 GIOCKING MOOS bur 2 11 2 12 Register 2 Translation Table Base u 2 12 2 13 Register 3 Domain Access 2 13 2 14 Fault Status 2 14 2 15 Function Descriptions Register 7 2 15 2 16 Cache Operations Register 7 2 16 2 17 TLB Operations Register 8 U enne 2 18 2 18 Accessing the Cache Lock Down Register 9 2 20 2 19 Accessing the TLB Lock Down Register 10 2 21 3 1 CP 15 Register ce a eee e aie 3 3 3 2 Interpreting Level One Descriptor Bits 0 3 8 3 3 Interpreting Page Table Entry Bits 0 3 11 3 4 Priority Encoding of Fault 3 18 3 5 Interpreting Access Control Bits in Domain Access Control Register 3 19 3 6 Interpreting Access Permission AP 3 20 4 1 Data Cache and Write Buffer Configuration sse 4 7 5 1 ARMO20T CIOCKlrig i crines dtr uud ep a a re Se 5 1 5 2 Synchronous Clocking Mode nennen nnns 5 2
4. T olo 1i t16 O SCLK SCLKO SCLKO 5 1 15 PRODUCT OVERVIEW 3 2410 Table 1 2 272 Pin FBGA Pin Assignments Continued Default State State State Type Function BE REQ nRESET H nBE2 nWBE2 DQM2 O H O H nawa naa e 5 688 nSRAS om om ot c sos Me om om o wowe owo mr INNBONADENC INA UN GEN 228 Lew mom wu of a ws e a jam aoa nz eo ________ ow won _ ou won som He ou o0 w we wswe P P P wowe P P P 4 ow womo Jao Ou oO e Em wm P P P s 99 el o ou woms ou oO w cr me T ou Ls omes Ws ote 1 16 ELECTRONICS 3 2410 PRODUCT OVERVIEW Table 1 2 272 Pin FBGA Pin Assignments Continued Default State State State Type Function BUS REQ MB ce we P C ON
5. 20 12 Multi Master Address IICADD Register a 20 13 Multi Master Transmit Receive Data Shift ICDS 20 13 S3C2410A MICROPROCESSOR XV Table of Contents Continued Chapter 21 IIS BUS Interface a sje Bc tee EE Functional Descrnpltlons bero ti bade Oe na cay etu ede e IER er Transmit or Receive Only 1 Audio Serial Interface Formatl IESU e PL TED SIUE Sampling Frequency and Master 15 Interface Special IIS Control IIGCON Register enne nnne en nennen sinn entente res nnns sn nnne ens IIS Mode Register IISMOD IIS Prescaler IISPSR Register enne nennen entente ns IIS FIFO Control IIGFCON nnne nennt 115 EIEO IISEIEGO Register eck i Saka Silas SER ee E ERU ER eater gah eee a Side ees Cha
6. m D rm 19 16 Base Register 20 Load Store Bit 0 Store to memory 1 Load from memory 21 Write back Bit 0 No write back 1 Write address into base 22 PSR amp Force User Bit 0 Do not load PSR or user mode 1 Load PSR or force user mode 23 Up Down Bit 0 Down subtract offset from base 1 Up add offset to base 24 Pre Post Indexing Bit 0 Post add offset after transfer 1 Pre add offset bofore transfer 31 28 Condition Field Figure 3 18 Block Data Transfer Instructions 3 40 ELECTRONICS 53 2410 ARM INSTRUCTION SET ADDRESSING MODES The transfer addresses are determined by the contents of the base register Rn the pre post bit P and the up down bit U The registers are transferred in the order lowest to highest so R15 if in the list will always be transferred last The lowest register also gets transferred to from the lowest memory address By way of illustration consider the transfer of R1 R5 and R7 in the case where Rn 0x1000 and write back of the modified base is required W 1 Figure 3 19 22 show the sequence of register transfers the addresses used and the value of Rn after the instruction has completed In all cases had write back of the modified base not been required W 0 Rn would have retained its initial value of 0x1000 unless it was also in the transfer list of a load multiple register instruction when it would have been overwr
7. 00000 3 53 3 27 Coprocessor Register Transfer 3 56 3 28 Undefined 3 58 53 2410 MICROPROCESSOR List of Figures continued Figure Title Page Number Number 4 1 THUMB Instruction Set Formats nnne 4 2 4 2 gelu 4 5 4 3 eub EE 4 7 4 4 eur EE 4 9 4 5 Format E EE 4 11 4 6 EE E 4 13 4 7 FOMAI O EE 4 16 4 8 EHE 4 18 4 9 FOE iet t fina 4 20 4 10 aeuum 4 22 4 11 Format p EE 4 24 4 12 euam p ap m y needy 4 26 4 13 eua PE 4 28 4 14 Format 32 iie 4 30 4 15 Format e E 4 31 4 16 4 33 4 17 Format 16 2 5 r t sic 4 34 4 18 Format Treron er ae ee eaa akay RD Ra LU nde det er ere 4 36 4 19 E 8 25 meti uet a fi A eui dett desc beca dade bat 4 37 4 20 Format 19 5 o 4 38 5 1 S3C2410A Memory Map after T 5 2 5 2 S3C2410A External nWAIT Timing Diagram 4 5 5 5 3 S3C2410A nXBREQ nXBACK Timing 5 6 5 4 Memory Interface with 8 bit a 5 7 5 5 Memory Interface with 8 bit ROM 2 2 4 1 1 00 nennen 5 7 5 6 Memory Interface with 8 bit ROM 5 8 5 7 Memory
8. Appendix 4 Caches Write Buffer About the Caches and Write Instruction Cache Instruction Cache Operation iesin th e E Re nest ide Instruction Cache Replacement Instruction Cache Lockdown 20201 R ia a la sasata Data Cache and Write ene eee Data Cache and Write Buffer Enable Disable L Data Cache and Write Buffer n na Data Cache Replacement Swap Instructions uice ete tedio da Cete qoe attese Data Gache Organization etie eti Pe tie ter eta ea e esee Data Cache Eo6kdOWn erre a eene dee nen ee aqa akay ea ge ue a Cache COnerence ETE Cache Cleaning when Lockdown is in 5 1 ener nennen nnns Impl mentatiorilNOtes eee EH prete et eed e qul ed ca tel fay a uqa qa dde feted Physical Address TAG RAM ete ete edd edite tat e a Quan erdt e ids Appendix 5 Clock Modes Eastbus Mode tui t od dtes deo a cot Syn
9. erate GPA O GPAIS Outputony Gm Ouputony aboes O o ADRM S agi appre Output only ADDR21 ago ame O am 9 2 ELECTRONICS 3 2410 PORTS Table 9 1 S3C2410A Port Configuration Continued Port B Selectable Pin Functions cmo oao GPB Ge GP o GP inputioutpat Gee GP mut GP www ww www ve a mu ae mut an mu ve Geo www wwe arco mut ace mut am iw Gs mut iw omen o ama mut www mw j aco mut
10. 7 21 Clock Slow Control CLKSLOW 7 22 Clock Divider Control CLKDIVN Register na enne 7 22 3C2410A MICROPROCESSOR Table of Contents Continued Chapter 8 DMA COVE IVICW Sete III 8 1 DMA REGUCSt 8 2 DMA Operations ta 8 2 External DREQ DACK 8 3 EXAM PISS 8 6 Special 8 7 Initial Source DISRC 8 7 DMA Initial Source Control DISRCC 8 7 DMA Initial Destination DIDST Register n aasan 8 8 DMA Initial Destination Control DIDSTC Register a 8 8 DMA Control DCON 8 9 DMA Status DSTAT 8 11 DMA Current Source DCSRC 8 11 Current Destination DCDST 8 12 DMA M
11. ELECTRONICS 9 3 PORTS 53 2410 Table 9 1 53 2410 Port Configuration Continued Port D Selectable Pin Functions Pon mot mw am mw seam amu mue seo Gen mua mw cms muet eres mut som soar ams mut soom ams muet Sk Gres esso ami mut muon since 9 4 ELECTRONICS 3 2410 PORTS Table 9 1 S3C2410A Port Configuration Continued Port F Selectable Pin Functions EINTO Rua 0 enne mua Gm mapu enne o pom GPG1 Input output EINT9 Loe input output EN ELECTRONICS 9 5 PORTS 53 2410 Table 9 1 S3C2410A Port Configuration Continued Port H Selectable Pin Functions Geo co 7 couo GP mu ama mut
12. 3 12 Immediate Operand 6 3 16 ate 3 16 Using R15 as 3 16 TST CMP and Opcoodes n nsn 3 16 Instr ction Cycle 3 16 Assembler Syntax 3 2 5 belit tut Detroit ta ti 3 17 es ha C Ve E ata anay 3 17 PSR Transfer MRS MSR Suyu usss pasu iaia CURIE FER 3 18 Operand Bestrictlons sec ere E ERE atunta asa ee 3 18 HOSGIVOGIBILS cei euet Uu nU nes parece amieta 3 20 TIME M 3 20 sawanakuna Qa rE nnns 3 20 Assembly SyntaX 3 21 EE 3 21 Multiply and Multiply Accumulate MUL 3 22 Wl mil san nacuy 3 24 InStr cton EM 3 24 D e I 3 24 ERU MERE DE E 3 24 Multiply Long and Multiply Accumulate Long MULL 3 25 Operand Restrictions omn 3 2
13. nns 7 9 7 8 Power Management State 7 10 7 9 Issuing Exit from Slow mode Command in PLL on 7 12 7 10 Issuing Exit from Slow mode Command After Lock 7 12 7 11 Issuing Exit from Slow mode Command and the Instant PLL on Command 7 13 7 12 Power OFF 7 16 8 1 Basic DMA Timing 8 3 8 2 Demand Handshake Mode 8 4 8 3 Burst 4 Transfer 5126 nega ae i o inea en ERR HER eg eee 8 5 8 4 Single service in Demand Mode with Unit Transfer 5126 8 6 8 5 Single service in Handshake Mode with Unit Transfer Size 8 6 8 6 Whole service in Handshake Mode with Unit Transfer Size 8 6 10 1 16 bit PWM Timer Block Diagram nennen 10 2 10 2 Timer Operations sere ete I Decet Mee c e ee hari M Dec 10 3 10 3 Example of Double Buffering Function T 10 4 10 4 Example of a Timer 10 6 10 5 Example ot PM S x ita entend test t smod aereis ox M 10 7 10 6 Inverter eio pM 10 8 10
14. aonr Ame OU ou _ aooo o0 ou ot Lm ot ADDR22 GPA7 ADDR22 Hi z O L L moms ot aoras avona o0 OU cs woomesGeAm o0 ou ot Es avoras avoras oo ou c P P e ws ws P P P s o vow P P P vso P P P s e P P s re vsswp P P P s 8s D onm nz os We m We m wowe P P P e ELECTRONICS 1 17 PRODUCT OVERVIEW S3C2410A Table 1 2 272 Pin FBGA Pin Assignments Continued MED omo zm umm Sam Function QBUS REQ PWR off nRESET 6 vssmop vssmop P P P sos p _____ vm F F F ws Js DATA18 DATA18 owes Hs Ws ss Wo Hz Me He We NOTES The BUS shows the pin states at the external bus which is used by the other bus master mark indicates the unchanged pin state at Bus Request mode Hi z or Pre means Hi z or Previous state and it is determined by the setting of MISCCR register means analog input analog output P and mean power in
15. 18 4 Chapter 19 MMC SD SDIO Host controller OVOLVIOWE akana A OA A E E E 19 1 REC EEA ed O 19 1 Block DE 19 2 SDI Operation EA ER Ce d e bi a rect beads 19 3 SDIG Operatlon Saha pete nete dp eredi E Pot M eS a 19 4 SDI Special ReglSters red etate eee tat tee pene de eee tid Dee darian 19 5 Chapter 20 IIC BUS Interface OVOIVIQW E ete ee cd Pe de 6 20 1 IIC Bus Interface 2 incerti e agde de Pre de Lee e dte a rude dde 20 3 Start and Stop Condltlons 2 pct ede e ER d a ee Pru dp 20 3 Data Transfer Eormat a ys eU Ca d E ep I eet 20 4 Signal Transmission dee A ee EL Ua ot a 20 5 Read Wirite odii iq tape pd tp dd e ERE e aR nde 20 6 Bus Arbitration Procedure Ssi eo nana a i apaa AAVA aE Aa A EAA ANNANN 20 6 Abort eed a eee A A Ea es 20 6 Gonfiguring lIO Bus ho doi HER Sd a uu ay ss 20 6 Flowcharts of Operations in Each 20 7 IIC Bus Interface Special Registers U 20 11 Multi Master IIC Bus Control IICCON Register a 20 11 Multi Master Control Status IICSTAT
16. 5 1 0 40000400 is Palette start address 2 VD18 VD10 VD2 have the same output value I 3 DATA 31 16 is invalid Palette Read Write When the user performs Read Write operation on the palette HSTATUS and VSTATUS of LCDCONS register must be checked for Read Write operation is prohibited during the ACTIVE status of HSTATUS and VSTATUS Temporary Palette Configuration The S3C2410A allows the user to fill a frame with one color without complex modification to fill the one color to the frame buffer or palette The one colored frame can be displayed by the writing a value of the color which is displayed on LCD panel to TPALVAL of TPAL register and enable TPALEN 15 20 ELECTRONICS 53 2410 LCD CONTROLLER 31 A 30 A 29 A 28 A 27 A 26 A 25 A 24 A 23 A 22 21 A 20 A 19 A 18 17 A 16 EXEJESERESESCIESESEJESEJESERE TEN LJEJESLSESESEOEJEJEJEJCSEAETE IER A 15 A 14 13 A 12 A 11 10 9 8 A 7 A 6 A 5 A 4 A S A 2 LCD Panel 16BPP 5 5 5 1 Format Non Palette A 31 A 30 A 29 A 28 A 27 A 26 A 25 A 24 A 23 A 22 A 21 A 20 A 19 A 18 A 17 A 16 15 A 14 A13 A 12 A 11 A 10 9 8 A 7 A 6 A 5 4 A S A 2 0 LCD Panel 16BPP 5 6 5 Format Non Palette Figure 15 5 16BPP Display Types TFT ELECTRONICS 15 21 LCD CONTROLLER S3C2410A
17. 6 5 Special Function 6 6 Nand Flash Configuration NFCONF Register u nennen 6 6 Nand Flash Command Set NFCMD Register U n nasa 6 7 Nand Flash Address Set NFADDR Register n aaa 6 7 Nand Flash Data NFDATA 6 7 Nand Flash Operation Status NFSTAT 6 8 Nand Flash ECC NFECO 6 8 Chapter 7 Clock amp Power Management TNI PEE 7 1 Functional Description k ice ten ede po ege gees red Ue pt 7 2 Glock Architect re sinet ett aee aee ed o te De qe ceti pot d ite tos 7 2 Glock Source Selection y etr ee E een petat a 7 2 Phase Locked PEL irte ctt ele e eet en ete 7 4 Glock Control Login 7 6 Power Management dette reti eet qe eee de t k eak det eee gue Ud e fees 7 9 Clock Generator amp Power Management Special 7 19 Lock Time Count Register LOCKTIME 7 19 PLL Value Selection Table n ed ed n etis pem degere aet een 7 20 Clock Control Register
18. NOTES 1 Although the MPLL starts just after a reset the MPLL output Mpll is not used as the system clock until the software writes valid settings to the MPLLCON register Before this valid setting the clock from external crystal or EXTCLK source will be used as the system clock directly Even if the user does not want to change the default value of MPLLCON register the user should write the same value into MPLLCON register 2 ON 32 is used to determine test mode when OM 1 0 is 11 7 2 ELECTRONICS 3 2410 EXTCLK ELECTRONICS CLOCK amp POWER MANAGEMENT ___ UPLL CLK FCLK Power Management Block ARM920T PCLK Memory Interrupt Controller Controller LCD Bus LCD Controller Controller Arbitration DMA 4ch Device Figure 7 1 Clock Generator Block Diagram 7 3 CLOCK amp POWER MANAGEMENT S3C2410A PHASE LOCKED LOOP PLL The MPLL within the clock generator as a circuit synchronizes an output signal with a reference input signal in frequency and phase In this application it includes the following basic blocks as shown in Figure 7 2 the Voltage Controlled Oscillator VCO to generate the output frequency proportional to input DC voltage the divider P to divide the input frequency Fin by p the divider M to divide the VCO output frequency by m which is input to Phase Frequency Detector PFD the divider S to divide the
19. TTC L 0x5200024C L DMA total transfer counter lower byte 0x00 0x5200024F B byte EP3 DMA TTC M 0x52000250 L DMA total transfer counter middle byte 0x00 0x52000253 B byte TTC H 0x52000254 L R W DMA total transfer counter higher byte 0x00 0x52000257 B byte L B EP4 DMA TTC M 0x52000268 L R W DMA total transfer counter middle byte 0x00 0x5200026B B byte 4_ _ _ 0x5200026C L R W DMA total transfer counter higher byte 0x00 0x5200026F B byte en ucu Description imitar State Em R DMAtoalransfr count vale rom RW 8 DMA anster count value miade yt O0 aw DMA total anster count value higher bye 600 EP4 DMA TTC_L 0x52000264 L R W EP4 total transfer counter lower byte 0x00 0x52000267 B byte 13 24 ELECTRONICS 3C2410A INTERRUPT CONTROLLER INTERRUPT CONTROLLER OVERVIEW The interrupt controller in the S8C2410A receives the request from 56 interrupt sources These interrupt sources are provided by internal peripherals such as the DMA controller the UART IIC and others In these interrupt sources the UARTn and EINTn interrupts are OR ed to the interrupt controller When receiving multiple interrupt requests from internal peripherals and external interr
20. owe 1 wop wo P P P _______ P P P 5 Ks onwoGges ____ oes ou 1 is ucovevercs ____ eme 1 i ____ 3 9 _ q pores ______ ow 1 wscecn ______ en I e M ______ P P P wee eme em ow w _ 1 w amp fvorercis es ow I Go ou w Gb 1 9 m fe ps vones GPs GP Co hae m _______ P P P a ws vssam gt F s m ems 1 9 m voae _____ 3 9 w cw 3 9 LAB lt lt lt lt LIII lt lt lt lt L T ELECTRONICS 1 11 PRODUCT OVERVIEW S3C2410A Table 1 2 272 Pin FBGA Pin Assignments Continued Function voer ome voze T2 R3 R4 U2 T
21. 16KB and D Cache 16KB e 8words length per line with one valid bit and two dirty bits per line Pseudo random or round robin replacement algorithm e Write through or write back cache operation to update the main memory The write buffer can hold 16 words of data and four addresses Clock amp Power Manager e On chip MPLL and UPLL UPLL generates the clock to operate USB Host Device MPLL generates the clock to operate MCU at maximum 266MHz 2 0V Clock can be fed selectively to each function block by software Power mode Normal Slow Idle and Power off mode Normal mode Normal operating mode Slow mode Low frequency clock without PLL Idle mode The clock for only CPU is stopped Power off mode The Core power including all peripherals is shut down Woken up by EINT 15 0 or RTC alarm interrupt from Power Off mode ELECTRONICS 3 2410 FEATURES Continued Interrupt Controller 55 Interrupt sources One Watch dog timer 5 timers 9 UARTs 24 external interrupts 4 DMA 2 RTC 2 ADC 1 IIC 2 SPI 1 SDI 2 USB 1 LCD and 1 Battery Fault Level Edge mode on external interrupt source e Programmable polarity of edge and level e Supports Fast Interrupt request FIQ for very urgent interrupt request Timer with Pulse Width Modulation PWM e 4 ch 16 bit Timer with PWM 1 ch 16 bit internal timer with DMA based or interrupt based operation Programmable d
22. Figure 20 1 IIC Bus Block Diagram NOTE IIC DATA HOLD TIME The IIC data hold time tSDAH is minimum Ons IIC data hold time is minimum Ons for standard fast bus mode in specification v2 1 Please check the data hold time of your IIC device if it s 0 nS or not The IIC controller supports only IIC bus device standard fast bus mode not C bus device ELECTRONICS 53 2410 IIC BUS INTERFACE IIC BUS INTERFACE The 53 2410 IIC bus interface has four operation modes Master transmitter mode Master receive mode Slave transmitter mode Slave receive mode Functional relationships among these operating modes are described below START AND STOP CONDITIONS When the IIC bus interface is inactive it is usually in Slave mode In other words the interface should be in Slave mode before detecting a Start condition on the SDA line a Start condition can be initiated with a High to Low transition of the SDA line while the clock signal of SCL is High When the interface state is changed to Master mode a data transfer on the SDA line can be initiated and SCL signal generated A Start condition can transfer a one byte serial data over the SDA line and a Stop condition can terminate the data transfer A Stop condition is a Low to High transition of the SDA line while SCL is High Start and Stop conditions are always generated by the master The IIC bus gets busy when a Start condition is generated A Stop condit
23. VCO is adapted to new clock frequency gt tRST2RUN MCU operates by XTIpll or EXTCLK clcok L is new frequency Figure 24 6 Power On Oscillation Setting Timing 24 6 ELECTRONICS S3C2410A ELECTRICAL DATA EXTCLK Clock Disable do Power OFF mode is initiated Figure 24 7 Power OFF Mode Return Oscillation Setting Timing ELECTRONICS 24 7 3 2410 ELECTRICAL DATA CACO Ao Qqvul 4 1 gt lt Sau gt rie 509 gt 4 4 Sau 0 DW 16 bit Figure 24 8 ROM SRAM Burst READ Timing l 0 Tcos 0 Tacc 2 Tcoh 0 Tcah 0 PMC 0 ST Tacs ELECTRONICS 24 8 ELECTRICAL DATA 53 2410 gt lt CHIHI S viva gt lt gt 4 gt pit lt I 1 I 4 1 i dvd 24 9 DW 16 bit 0 ST 1 Figure 24 9 ROM SRAM Burst READ Timing Il 0 Tacc 2 Tcoh 0 Tcah 0 PMC 0 Tcos Tacs
24. 13 16 End Point FIFO Register Epn Fifo 13 18 Max Packet Register Maxp_BReg 13 19 End Point Out Write Count Register Out Fifo Cnt1 Reg Out Fifo_Cnt2_Reg 13 20 DMA Interface Control Register Epn__Dma_Con esent 13 21 DMA Unit Counter Register Epn__Dma_Unit 13 22 DMA FIFO Counter Register Epn_Dma_FIFO aaa 13 23 DMA Total Transfer Counter Register Dma Ttc L 13 24 3C2410A MICROPROCESSOR Table of Contents Continued Chapter 14 Interrupt Controller Su E 14 1 Interrupt Controll r OpetratiOFi 14 2 Interrupt SOUICOS ooi ee eei Tur 14 3 Interrupt Priority Generating 14 4 NtSMUPE 14 5 Interrupt Controller Special Registers 22 00 14 6 Source Pending SRCPND 14 6 Interrupt Mode INTMOD Register U U 14 8 Interrupt Mask INTMSK
25. ctm o eroe oe t tete sexes x nete Ov ea tates ert etie erdt edi baa tune Format 9 Load Store With Immediate Offset ener entente ennt enne doce ED dece A Mt cii DM MIA M MT asua kunay ma ated uu da Format 10 Load Store 9 a M ND Atun ass Instruction Cycle aee d ive S aa ua saya ak Format 11 Sp Relative 4 Operation cssc c err Instruction Cycle Examples ete Eee itia ie a eue en ET er edt Format 12 Load Addiess auue im i Ee o nete ea Hae enu bah a E E XE ARE As aa E Instruction Cycle Examples
26. 16Mb 1Mx 8x2banks 4 ea 64Mb 4M x 8 x 2banks x 1 ea x16 1M x 16 x mee x1ea 22 21 ms v _ Camerae 1Mx16x4banks 2 1M x 16 x E x2ea 22 4M x 8 x 4banks x 1 ea 2Mx 16x 4banks xtea _ x 16 x 2Mx 16x 4banks xtea _ 1 wasa S TIL CRI 2423 128Mb 4M x 8 x 4banks x 2 ea 2M x 16 x 2 256 AM x 16x 4banks 1 x 16 x Pole x1ea 4M x 8 x 4banks x 4 ea A 25 24 8M x 8 x 4banks x 2 ea 4M 16 x 4banks 2 8Mx 8x4banks x4ea _ 128Mb 256Mb EE CNN 512 16Mx 8x4banks x 1 ea 8M x 8 x 4banks x 4 ea 26 25 5 4 ELECTRONICS 53 2410 MEMORY CONTROLLER nWAIT PIN OPERATION If the WAIT corresponding to each memory bank is enabled the nOE duration should be prolonged by the external nWAIT pin while the memory bank is active nWAIT is checked from tacc 1 will be deasserted at the next clock after sampling nWAIT is high The nWE signal have the same relation with nOE 1 1 1 1 Tacs 1 1 1 1 1 1 x Delayed i 34 Tcos 1 7 ma oe Figure 5 2 53C2410A External nWAIT Timing Diagram Tacc 4 ELECTRONICS 5 5 53 2410 MEMORY CONTROLLER nXBREQ nXBACK Pin Operation L the address data bu
27. 2 2 Operating the e t ee HA MN 2 3 E 2 3 The Program Status Registers ua cop eti paid tete tene d ed dla faai i eda eth 2 7 EXCOPllONS c 2 10 Interrupt Eatencles tau 2 15 ROSO cette co dme heave s ukata fexta ukya a 2 15 3C2410A MICROPROCESSOR Table of Contents Continued Chapter 3 ARM Instruction set Instr ction SCE SUMMA feces huan nam sayta maa 3 1 Format SUMMARY ct yay u ces I NANI LI ista a 3 1 lnStr ction AY 3 2 The Condition Field Sumu 3 4 Branch and Exchange BX 1 one eee douse at Dd 3 5 Instruction Cycle 3 5 3 5 Using R15 as am eni rer ase ERES 3 5 Branch and Branch with Link B 3 7 rere 3 7 INSTUCTION CY Cle EMIT 3 7 toI TM SEE 3 8 Data 3 9 EE 3 11
28. SP R13 212 but don t set the condition codes Note that the THUMB opcode will contain 53 as the Word 8 value ELECTRONICS 4 29 THUMB INSTRUCTION SET S3C2410A FORMAT 13 ADD OFFSET TO STACK POINTER 15 14 13 11 10 6 1 12 9 8 7 _____ 6 0 7 bit Immediate Value 7 Sign Flag 0 Offset is positive 1 Offset is negative Figure 4 14 Format 13 OPERATION This instruction adds a 9 bit signed constant to the stack pointer The following table shows the THUMB assembler syntax Table 4 14 The ADD SP Instruction 0 ADD SP ADD R13 R13 Add stlmm to the stack pointer SP ADD SP Imm SUB R13 R13 Add Imm to the stack pointer SP NOTE The offset specified by Imm can be up to 508 but must be word aligned ie with bits 1 0 set to 0 since the assembler converts lmm to 8 bit sign magnitude number before placing it in field SWord7 The condition codes are not set by this instruction INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 14 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES ADD SP 268 SP R13 SP 268 but don t set the condition codes Note that the THUMB opcode will contain 67 as the Word7 value and S 0 ADD SP 104 SP R13 SP 104 but don t set
29. 1 I AAXAXAXK AX AX I I I I 1 HSPW 1 HOZVAL 1 HFPD 1 Figure 15 6 TFT LCD Timing Example 15 22 ELECTRONICS 53 2410 LCD CONTROLLER SAMSUNG TFT LCD PANEL 3 5 PORTRAIT 256K COLOR REFLECTIVE A SI LCD The S3C2410A supports SEC TFT LCD panel SAMSUNG 3 5 Portrait 256K Color Reflective a Si TFT LCD LTS350Q1 PD1 TFT LCD panel with touch panel and front light unit LTS350Q1 PD2 TFT LCD panel only The 3 2410 provides timing signals as follows to use LTS350Q1 PD1 and PD2 STH Horizontal Start Pulse TP Source Driver Data Load Pulse INV Digital Data Inversion LCD_HCLK Horizontal Sampling Clock CPV Vertical Shift Clock STV Vertical Start Pulse OE Gate On Enable REV Inversion Signal REVB Inversion Signal So LTS350Q1 PD1 and PD2 can be connected with the S3C2410A without using the additional timing control logic But the user should additionally apply Vcom generator circuit various voltages INV signal and Gray scale voltage generator circuit which is recommended by PRODUCT INFORMATION SPEC of LTS350Q1 PD1 and PD2 Detailed timing diagram is also described in PRODUCT INFORMATION SPEC of LTS350Q1 PD1 and PD2 Refer to the documentation PRODUCT INFORMATION of LTS350Q1 PD1 and PD2 which is prepared by AMLCD Technical Customer Center of Samsung Electronics Co LTD Caution The S3C2410A has HCLK working as the clock of AHB bus Accidentally SEC TFT LCD panel LT
30. SPI Pin Control SPI Baud Rate Prescaler R SPD ELECTRONICS 1 3 PRODUCT OVERVIEW 3 2410 Table 1 4 S3C2410A Special Registers Continued pews emm es B Endian L Endian Write SD interface RW SDIRSP2 0x5A00001C SDI Response 501 Data Remain Counter R SDDAT oxeA000086 RW Cautions on S3C2410A Special Registers 1 Inthe little endian mode L endian address must be used In the big endian mode B endian address must used The special registers have to be accessed for each recommended access unit All registers except ADC registers RTC registers and UART registers must be read written in word unit 32 bit at little big endian 4 Make sure that the ADC registers RTC registers and UART registers be read written by the specified access unit and the specified address Moreover one must carefully consider which endian mode is used 5 W 32 bit register which must be accessed by LDR STR or int type pointer int HW 16 bit register which must be accessed by LDRH STRH or short int type pointer short int B 8 bit register which must be accessed by LDRB STRB or char type pointer char int 1 36 ELECTRONICS 53 2410 PROGRAMMER S MODEL PROGRAMMER S MODEL OVERVIEW S3C2410A has been developed using the advanced ARM920T core which has been designed by Advanced RISC Machines Ltd PR
31. current Source Register 0x00000000 5 1 0 48000058 R 1 current Source Register 0x00000000 DCSRC2 ox4B000098 R 2 current Source Register 0x00000000 DCSRC3 0x4B0000D8 R 3 current Source Register 0x00000000 CURR_SRC 30 0 Current source address for DMAn 0x00000000 ELECTRONICS 8 11 DMA 53 2410 CURRENT DESTINATION DCDST REGISTER DCDSTO R current destination register 0x00000000 DCDST1 0x4B00005C R DMA 1 current destination register 0x00000000 DCDST2 0 4 00009 R DMA 2 current destination register 0x00000000 DCDST3 0x4B0000DC R DMA3 current destination register 0x00000000 CURR_DST 30 0 Current destination address for DMAn 0x00000000 8 12 ELECTRONICS 3C2410A DMA DMA MASK TRIGGER DMASKTRIG REGISTER o eno mw OWA Omasktiggerreaster 99 mw mask ioger reger 90 DMASTRIG2 0 480000 0 mw mask tioger regse 99 oweskrmGs ox4B000060 mw DMA mask tioger regse 99 STOP 2 Stop the DMA operation 1 DMA stops as soon as the current atomic transfer ends If there is no current running atomic transfer DMA stops immediately The CURR TC will be 0 NOTE Due to possible current atomic transfer stop operation may take several cycles The finish of the operation i e actua
32. emrusewoseros Pe CN e z C C C ELECTRONICS 1 9 PRODUCT OVERVIEW S3C2410A Table 1 2 272 Pin FBGA Pin Assignments Function QBUS REQ QPWR off nRESET P P P voo P P P DATA24 DATA24 oms Me ome Me be Me DA bes Me omea Me z Ep E C3 B1 C2 D3 E5 s3o d3o t12 t12 t12 t12 wssuop owe 1 _ 5 5 VDDalive VDDalive dic O P NN 6288 mr i 1 41214 D D D E E E E G G G G G G G H H H H H H 2 4 1 3 2 4 1 F3 F5 F2 F1 F4 3 4 1 5 2 6 7 1 4 2 3 5 6 J1 J3 3o 3o t8 t8 t8 t8 t8 t8 t8 t8 3i t8 t8 t8 is is is 1 10 ELECTRONICS 3 2410 PRODUCT OVERVIEW Table 1 2 272 Pin FBGA Pin Assignments Continued omo mms e nmn e Function BUS REQ p off ROM 5 To TO owe 1 9 77 6 owe 1 9 om e e P or VSSiarm VSSiarm Le mvn cea
33. Figure 8 4 Single service in Demand Mode with Unit Transfer Size Single service in Handshake Mode with Unit Transfer Size XnXDREQ XnXDACK Double synch 1 Figure 8 5 Single service Handshake Mode with Unit Transfer Size Whole service in Handshake Mode with Unit Transfer Size XnXDREQ XnXDACK 3 cycles Read Write 2 cycles Read Write 2 cycles Read Write 1 I 1 Figure 8 6 Whole service Handshake Mode with Unit Transfer Size 8 6 ELECTRONICS 53 2410 DMA DMA SPECIAL REGISTERS Each DMA channel has nine control registers 36 in total since there are four channels for DMA controller Six of the control registers control the DMA transfer and other three ones monitor the status of DMA controller The details of those registers are as follows DMA INITIAL SOURCE DISRC REGISTER S_ADDR 30 0 Base address start address of source data to transfer This bit 0x00000000 value will be loaded into CURR_SRC only if the CURR_SRC is 0 and the DMA ACK is 1 DMA INITIAL SOURCE CONTROL DISRCC REGISTER 1 Bit 1 is used to select the location of source 0 the source is in the system bus AHB 1 the source is in the peripheral bus APB INC Bit 0 is used to select the address increment 0 Increment 1 Fixed If it is 0 the address is increased by its data size after each transfer in burst and single transfer mode If it is 1 the address is not changed after the transfer In th
34. 3C2410A ARM INSTRUCTION SET OFFSETS AND AUTO INDEXING The offset from the base may be either a 12 bit unsigned binary immediate value in the instruction or a second register possibly shifted in some way The offset may be added to U 1 or subtracted from U 0 the base register Rn The offset modification may be performed either before pre indexed P 1 or after post indexed P 0 the base is used as the transfer address The W bit gives optional auto increment and decrement addressing modes The modified base value may be written back into the base W 1 or the old base value may be kept W 0 In the case of post indexed addressing the write back bit is redundant and is always set to zero since the old base value can be retained by setting the offset to zero Therefore post indexed data transfers always write back the modified base The only use of the W bit in a post indexed data transfer is in privileged mode code where setting the W bit forces non privileged mode for the transfer allowing the operating system to generate a user address in a system where the memory management hardware makes suitable use of this hardware SHIFTED REGISTER OFFSET The 8 shift control bits are described in the data processing instructions section However the register specified shift amounts are not available in this instruction class See Figure 3 5 BYTES AND WORDS This instruction class may be used to transfer byte B 1 or
35. Confirm the end of SDI data operation when the flag of data transfer finish SDIDSTA 4 is set Clear the corresponding flag of SDIDSTA register by writing one to the flag bit NOTE In case of long response command CRC error can be wrong by H W but a user can ignore this It should be detected by software if it is need to check ELECTRONICS 19 3 MMC SD SDIO HOST CONTROLLER S3C2410A SDIO OPERATION There are two functions of the SDIO operation SDIO Interrupt receiving and Read Wait Request generation These two functions can operate when RcvlOInt bit and RwaitEn bit of SDICON register is activated respectively Detailed steps and conditions for the two functions are described below SDIO Interrupt In SD 1 bit mode the interrupt is received through all ranges from SDDAT1 pin In SD 4 bit mode SDDAT1 pin is shared between to receive data and interrupts When interrupt detection ranges Interrupt Period are 1 Single Block the time between A and B 2clocks after the completion of a data packet B The completion of sending the end bit of the next with data command 2 Multi Block SDIDCON 21 0 the time between A and B restart interrupt detection range at C 2clocks after the completion of a data packet 2 after 2clocks after the end bit of the abort command response 3 Multi Block SDIDCON 21 1 the time between A and B restart at A 2clocks after the completion
36. ama mut ame mut ami mut j amo mua c 9 6 ELECTRONICS S3C2410A PORTS PORT CONTROL DESCRIPTIONS PORT CONFIGURATION REGISTER GPACON GPHCON In the S3C2410A most pins are multiplexed So It is require to determine which function is selected for each pin port control register determines the function of each pin If GPFO GPF7 and GPGO GPG7 are used for wakeup signals in Power OFF mode these ports must be configured in Interrupt mode PORT DATA REGISTER GPADAT GPHDAT If ports are configured as output ports data can be written to the corresponding bit of the PnDAT If ports are configured as input ports the data can be read from the corresponding bit of the PnDAT PORT PULL UP REGISTER GPBUP GPHUP The port pull up register controls the pull up resister enable disable of each port group When the corresponding bit is 0 the pull up resister of the pin is enabled When 1 the pull up resister is disabled If the port pull up register is enabled the pull up resisters work without pin s functional setting input output DATAn EINTn etc MISCELLANEOUS CONTROL REGISTER This register controls DATA port pull up resister hi z state USB pad and CLKOUT selection EXTERNAL INTERRUPT CONTROL REGISTER EXTINTN The 24 external interrupts are requested by various signaling methods The EXTINTn register c
37. the address formed by adding 7 to RO ELECTRONICS 4 19 THUMB INSTRUCTION SET S3C2410A FORMAT 8 LOAD STORE SIGN EXTENDED BYTE HALFWORD 15 14 13 12 11 10 9 8 6 5 3 2 0 2 0 Destination Register 5 3 Base Register 8 6 Offset Register 10 Sign Extended Flag 0 Operand not sing extended 1 Operand sing extended 11 H Flag Figure 4 9 Format 8 OPERATION These instructions load optionally sign extended bytes or halfwords and store halfwords The THUMB assembler syntax is shown below Table 4 9 Summary of format 8 instructions STRH Rd Rb Ro STRH Rd Rb Ro Store halfword Add Ro to base address in Rb Store bits 0 15 of Rd at the resulting address LDRH Rb LDRH Rb Ro Load halfword Add Ro to base address in Rb Load bits 0 15 of Rd from the resulting address and set bits 16 31 of Rd to 0 LDSB Rd Rb Ro LDRSB Rb Ro Load sign extended byte Add Ro to base address in Rb Load bits 0 7 of Rd from the resulting address and set bits 8 31 of Rd to bit 7 LDSH Rad Rb Ro LDRSH Rb Ro Load sign extended halfword Add Ro to base address in Rb Load bits 0 15 of Rd from the resulting address and set bits 16 31 of Rd to bit 15 4 20 ELECTRONICS 3C2410A THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 9 The instruc
38. Determine data bus width for bank 6 00 8 bit 01 16 bit 10 32 bit 11 reserved 515 23 Determine SRAM for using UB LB for bank 5 0 Not using UB LB The pins are dedicated nWBE 3 0 1 Using UB LB The pins are dedicated nBE 3 0 WS5 22 Determine WAIT status for bank 5 0 WAIT disable 1 WAIT enable DW5 21 20 Determine data bus width for bank 5 00 8 bit 01 16 bit 10 32 bit 11 reserved ST4 19 Determine SRAM for using UB LB for bank 4 0 Not using UB LB The pins are dedicated nWBE 3 0 1 Using UB LB The pins are dedicated nBE 3 0 WS4 18 Determine WAIT status for bank 4 0 WAIT disable 1 WAIT enable DW4 17 16 Determine data bus width for bank 4 00 8 bit 01 16 bit 10 32 bit 11 reserved ST3 15 Determine SRAM for using UB LB for bank 3 0 Not using UB LB The pins are dedicated nWBE 3 0 1 Using UB LB pins are dedicated nBE 3 0 WS3 14 Determine WAIT status for bank 3 0 WAIT disable 1 WAIT enable DW3 13 12 Determine data bus width for bank 3 00 8 bit 01 16 bit 10 32 bit 11 reserved ST2 11 Determine SRAM for using UB LB for bank 2 0 Not using UB LB The pins are dedicated nWBE 3 0 1 Using UB LB The pins are dedicated nBE 3 0 ELECTRONICS 5 13 MEMORY CONTROLLER 53 2410 BUS WIDTH amp WAIT CONTROL REGISTER BWSCON Continued ewscon et 10 Determine WAIT status for bank 2 0 WAIT disable 1 WAIT
39. ELECTRONICS 11 15 UART S3C2410A UART ERROR STATUS REGISTER There are three UART Rx error status registers including UERSTAT0 UERSTAT1 and UERSTAT2 in the UART block __ UART hamelO eror oo ues oo R UART chanel 1 Ri status OO C UERSTAT2 UART channel Ri eror stats register 0 Reserved 3 0 frame error during receive 1 Frame error Interrupt is requested Frame Error 2 Set to 1 automatically whenever a frame error occurs during receive operation 0 No frame error during receive 1 Frame error Interrupt is requested Reserved 1 0 frame error during receive 1 Frame error Interrupt is requested Overrun Error Set to 1 automatically whenever an overrun error occurs during receive operation 0 No overrun error during receive 1 Overrun error Interrupt is requested NOTE These bits UERSATn 3 0 are automatically cleared to 0 when the UART error status register is read 11 16 ELECTRONICS 53 2410 UART UART FIFO STATUS REGISTER There are three UART FIFO status registers including UFSTAT0 UFSTAT1 and UFSTAT2 in the UART block urs ooo UART cramer O FIFO siatus regse 946 ooo UART chanel 1 FIFO satus deer 040 7 6 UART channel 2 FIFO satus register 946 Rx FIFO Full 0 0 byte lt Rx
40. L 24 9 24 10 External Bus Request in ROM SRAM Cycle Tacs 0 Tcos 0 Tacc 8 Tcoh 0 0 0 87 0 24 10 24 11 ROM SRAM READ Timing Tacs 2 Tcos 2 Tacc 4 2 2 0 6 0 ciun scenes e fee eee ch 24 11 24 12 ROM SRAM READ Timing 11 Tacs 2 Tcos 2 Tacc 4 Tcoh 2 2 usa 24 12 24 13 ROM SRAM WRITE Timing 1 Tacs 2 Tcos 2 4 Tcoh 2 Tcah 2 les 0E AE IEEE 24 13 24 14 ROM SRAM WRITE Timing 1 Tacs 2 Tcos 2 4 Tcoh 2 Tcah 2 20 ST AaS esata 24 14 24 15 External nWAIT READ Timing Tacs 1 Tcos 1 Tacc 4 Tcoh 0 Tcah 1 PMG ST 0 ech z m tcc uku ueq 24 15 24 16 External WRITE Timing Tacs 0 Tcos 0 Tacc 4 Tcoh 0 0 PMG 0 sa ed PUR 24 15 24 17 Masked ROM Single READ Timing Tacs 2 2 Tacc 8 01 10 11 24 16 24 18 Masked ROM Consecutive READ Timing Tacs 0 Tcos 0 Tacc 3 Tpac 2 PMG 09 1 0 14 PU 24 16 24 19 SDRAM Single Burst READ Timing Trp 2 Trcd 2 Tcl 2 DW 16 bit 24 17 24 20 External Bus Request SDRAM
41. Le o 24 15 ELECTRONICS ELECTRICAL DATA S3C2410A HCLK UVUWUWUUWUUUVUUUVUU U lt Hi 291 tRDS gt Figure 24 17 Masked ROM Single READ Timing Tacs 2 Tcos 2 8 PMC 01 10 11 HCLK 2 bids ALL Figure 24 18 Masked ROM Consecutive READ Timing Tacs 0 Tcos 0 Tacc 3 Tacp 2 PMC 01 10 11 24 16 ELECTRONICS 53 2410 ELECTRICAL DATA ADDR BA Figure 24 19 SDRAM Single Burst READ Timing Trp 2 Tred 2 Tcl 2 DW 16 bit ELECTRONICS 24 17 S3C2410A ELECTRICAL DATA ADDR BA tXnBRQS m x 1 tXnBACKD 1 1 i I 1 1 2 Tcl 2 2 Tred Figure 24 20 External Bus Request in SDRAM Timing Trp ELECTRONICS 24 18 ELECTRICAL DATA S3C2410A lt m c lt Figure 24 21 SDRAM MRS Timing 24 19 ELECTRONICS 3 2410 ELECTRICAL DATA lt a c lt 2 Tcl 2 2 Tred Figure 24 22 SDRAM Single READ Timing l Trp ELECTRONICS 24 20 ELECTRICAL DATA S3C2410A lt m lt 2 Tcl 3 2 Tred Figure 24 23 SDRAM Single READ Timing Il Trp 24 21 ELECTRONICS S3C2410A ELECTRICAL DATA ADDR BA g 5 5 o x c
42. Register Address R Description Reset Value AN SDICSTA 0x5A000010 R W SDI command status register 0x0 Response CRC CRC check failed when command response received This flag Fail RspCrc is cleared by setting one to this bit 0 not detect 1 crc fail Command Sent Command sent not concerned with response This flag is CmdSent cleared by setting one to this bit 0 not detect 1 command end Command Time Command response timeout 64clk This flag is cleared by Out CmdTout setting one to this bit 0 not detect 1 timeout Response Receive Command response received This flag is cleared by setting one End RspFin to this bit 0 not detect 1 response end CMD line progress Command transfer in progress On CmdOn not detect 1 in progress Rsplndex 7 0 Response index 6bit including start 2 bit 8 bit R ELECTRONICS 19 7 MMC SD SDIO HOST CONTROLLER S3C2410A SDI Response Register 0 SDIRSPO Register Address R W Description Reset Value SDIRSPO 0x5A000014 R SDI response register 0 0 0 31 0 status 31 0 short card status 127 96 long 000000000 SDI Response Register 1 SDIRSP1 Reset Value SDIRSP1 0 5 000018 R SDIresponse register 1 0 0 Bit Description Initial Value 31 24 CRC7 with end bit short card status 95 88 long 0x00 Response 23 0 Unused short card status 87 64 long 0x000000 SDI Response Register 2 SDIRSP2 SDIRSP2 0x5A00001C
43. sss 3 52 LEE 3 52 53 2410 MICROPROCESSOR Table of Contents Continued Chapter 3 ARM Instruction set Continued Coprocessor Data Transfers LDC a n nan 3 53 The Coprocessor Flelds x art iai ee iR eR RR DIE unease 3 54 Addressing MOSS 3 54 Address Aligrimert eco RT ee 3 54 ADOr Scz MUN LIEU 3 54 Assembler Syntax maa PEINE 3 55 TE ATA 3 55 Coprocessor Register Transfers MRC L u 3 56 The GoprocessoriFieldg uy rire acta 3 56 Transters eres sare ever tae E 3 57 Transters TOME UL u antin 3 57 TIMES 3 57 Assemblet Syhtax Qu 3 57 Examples t tuer chanel 3 57 Undefined eae ataa ae a aE A a Eea E R ELS 3 58 INSTFUCTION Cycle TIMES s s ans Seca vie 3 58 E A E A EE 3 58 InStruction Set Examples u u a rit eae cep masala asa NER ERES S DOR 3 59 Using the Conditional
44. 0x227 B B B Function address register Power management register EP INT REG EPO EP4 Endpoint interrupt register 0x148 USB INT REG EP INT EN REG EPO EP4 UJ UJ Endpoint interrupt enable register USB INT EN REG FRAME NUM1 REG FRAME NUM2 REG INDEX REG EPO FIFO REG USB Interrupt enable register Frame number 1 register 0x170 Index register B B lt lt Je KS 4 IH lt lt gt DMA transfer counter low byte register UJ Endpoint1 DMA transfer counter middle byte register w a Endpoint1 DMA transfer counter high byte register Endpoint2 DMA control register Endpoint2 DMA unit counter register 0 21 Endpoint2 DMA FIFO counter register 0x220 Endpoint2 DMA transfer counter low byte register 0x224 5 ELECTRONICS 13 3 USB DEVICE 53 2410 USB Device Controller Special Registers Continued Register Name Description Offset Address 2_ _ _ Endpoint2 DMA transfer counter middle byte register 0x228 L Ox22B B EP2 DMA TTC H Endpoint2 DMA transfer counter high byte register 0x22C L 0 22 CON 0x240 L 0 243 UNIT 0x244 L 0x24 EP3_D
45. 2 0 4 0 0 nennen 20 5 20 8 Operations for Slave Transmitter 20 9 20 9 Operations for Slave Receiver 20 10 21 1 15 D p A us uda u duka teaa NEE ias nnns 21 2 21 2 IIS Bus and MSB Left justified Data Interface Formats 21 4 22 1 SPI Bl cikecDIagralflu 22 2 22 2 Transfer Formatiu 22 4 24 1 24 4 24 2 EXTCLK Clock Input Timing ennemis 24 4 24 3 EXTCLK HCLK in case that EXTCLK is used without the 24 4 24 4 HCLK CLKOUT SCLK in case that EXTCLK is 24 5 24 5 Manual Reset Input Timing U nennen nnne 24 5 24 6 Power On Oscillation Setting Timing 24 6 24 7 Power OFF Mode Return Oscillation Setting Timing 24 7 xxiv 3C2410A MICROPROCESSOR List of Figures Continued Figure Title Page Number Number 24 8 ROM SRAM Burst READ Timing l Tacs 0 Tcos 0 2 Tcoh 0 Tcah 0 0 ST 0 DW 16 00 24 8 24 9 ROM SRAM Burst READ Timing Il Tacs 0 0 Tacc 2 0 Tcah 0 0 ST 1 DW 16 bit
46. 512 Tx Rx Interrupt IIC Bus Tx Rx interrupt enable disable bit note 5 0 Disable 1 Enable Interrupt pending IIC bus Tx Rx interrupt pending flag This bit cannot be written flag note 2 note 3 to 1 When this bit is read as 1 the IICSCL is tied to L and the IIC is stopped To resume the operation clear this bit as 0 0 1 No interrupt pending when read 2 Clear pending condition amp Resume the operation when write 1 1 Interrupt is pending when read 2 N A when write Transmit clock IIC Bus transmit clock prescaler Undefined value note 4 IIC Bus transmit clock frequency is determined by this 4 bit prescaler value according to the following formula Tx clock IICCLK IICCON 3 0 1 NOTES 1 Interfacing with EEPROM the ack generation may be disabled before reading the last data in order to generate the STOP condition in Rx mode 2 interrupt occurs 1 when a 1 byte transmit or receive operation is completed 2 when a general call or a slave address match occurs or 3 if bus arbitration fails 3 To adjust the setup time of IICSDA before IISSCL rising edge IICDS has to be written before clearing the IIC interrupt pending bit 4 ICCLK is determined by IICCON 6 Tx clock can vary by SCL transition time When IICCON 6 0 IICCON 3 0 0x0 or 0x1 is not available 5 Ifthe IICON 5 0 IICON 4 does not operate correctly So It is recommended that you should set IICCON 5 1 a
47. ELECTRONICS 16 3 ADC AND TOUCH SCREEN INTERFACE 53 2410 FUNCTION DESCRIPTIONS A D Conversion Time When the PCLK frequency is 50 MHz and the prescaler value is 49 total 10 bit conversion time is given A D converter freq 50 MHz 49 1 1 MHz Conversion time 1 1 MHz 5cycles 1 200 kHz 5 us NOTE This A D converter is designed to operate at maximum 2 5 MHz clock so the conversion rate can go up to 500 KSPS Touch Screen Interface Mode 1 Normal Conversion Mode Normal Conversion Mode AUTO_PST 0 XY_PST 0 is generally used for General Purpose ADC Conversion This mode can be initialized by setting the ADCCON and ADCTSC and completed with a read the XPDATA Normal ADC value of ADCDATO ADC Data Register 0 2 Separate X Y Position Conversion Mode Separate X Y Position Conversion Mode is consist of two Conversion Modes X Position Mode and Y Position Mode The first mode is operated in the following way X Position Mode AUTO_PST 0 and XY_PST 1 writes X position conversion data to XPDATA of ADCDATO register After conversion The Touch Screen Interface generates the Interrupt source INT_ADC to Interrupt Controller Y Position Mode AUTO PST 0 and XY PST 2 writes Y position conversion data to YPDATA of ADCDAT1 After the conversion the Touch Screen Interface also generates the Interrupt source INT_ADC to Interrupt Controller Table 16 1 Condition of Touch Screen Panel Pads in Separate X Y Po
48. Here if ARB_MODE bit is set to 0 ARB_SEL bits are not automatically changed making the arbiter to operate in the fixed priority mode note that even in this mode we can reconfigure the priority by manually changing the ARB_SEL bits On the other hand if ARB_MODE bit is 1 ARB_SEL bits are changed in rotation fashion e g if REQ1 is serviced ARB_SEL bits are changed to 01b automatically so as to put REQM into the lowest priority The detailed rules of ARB_SEL change are as follows If REQO or is serviced ARB SEL bits are not changed at all If REQ1 is serviced SEL bits are changed to 016 If REQ2 is serviced SEL bits are changed to 10b If REQ is serviced ARB SEL bits are changed to 11b f REQ4 is serviced SEL bits are changed to 006 ELECTRONICS 14 5 INTERRUPT CONTROLLER 53 2410 INTERRUPT CONTROLLER SPECIAL REGISTERS There are five control registers in the interrupt controller source pending register interrupt mode register mask register priority register and interrupt pending register All the interrupt requests from the interrupt sources are first registered in the source pending register They are divided into two groups including Fast Interrupt Request FIQ and Interrupt Request IRQ based on the interrupt mode register The arbitration procedure for multiple IRQs is based on the priority register SOURCE PENDING SRCPND REGISTER The SRCPND register is co
49. 0 560000 8 0 560000 3 2410 Table 1 4 S3C2410A Special Registers Continued Address 0x560000B0 Acc Unit Read Write R W R W Function Port A Control Port A Data Port B Control Port B Data Pull up Control B Port C Control Port C Data Pull up Control C Port D Control Port D Data Pull up Control D Port E Control Port E Data Pull up Control E Port F Control Port F Data Pull up Control F Port G Control Port G Data Pull up Control G Port H Control Port H Data Pull up Control H Miscellaneous Control DCLKO 1 Control External Interrupt Control Register 0 External Interrupt Control Register 1 External Interrupt Control Register 2 Reserved Reserved External Interrupt Filter Control Register 2 External Interrupt Filter Control Register 3 External Interrupt Mask External Interrupt Pending External Pin Status External Pin Status ELECTRONICS 3 2410 PRODUCT OVERVIEW Table 1 4 S3C2410A Special Registers Continued Register Address Address Read Function Name B Endian L Endian Write ALMMON 0x57000067 0x57000064 Alarm Month A D converter ADCCON 0x58000000 ADC Control ________ Control ADCTSC 0x58000004 LI M Touch Screen Control ADCDLY 0x58000008 ADC Start or Interval Delay Start or Interval ADC Start or Interval Delay ADCDATO 0x5800000C Conversion Data ADCDAT1 0x58000010 BEP TEE Conversion Data ______ lt w R sPisiaus o
50. 1 Division factor WTDAT amp WTCNT Once the watchdog timer is enabled the value of watchdog timer data WTDAT register cannot be automatically reloaded into the timer counter WTCNT In this reason an initial value must be written to the watchdog timer count WTCNT register before the watchdog timer starts CONSIDERATION OF DEBUGGING ENVIRONMENT When the 53 2410 is in debug mode using Embedded ICE the watchdog timer is disabled will be disabled automatically The watchdog timer can determine whether or not it is currently in the debug mode from the CPU core signal DBGACK signal Once the DBGACK signal is asserted the reset output of the watchdog timer is not activated as the watchdog timer is expired 18 2 ELECTRONICS 3C2410A WATCHDOG TIMER WATCHDOG TIMER SPECIAL REGISTERS WATCHDOG TIMER CONTROL WTCON REGISTER The WTCON register allows the user to enable disable the watchdog timer select the clock signal from 4 different sources enable disable interrupts and enable disable the watchdog timer output The Watchdog timer is used to resume the S3C2410A restart on mal function after its power on if controller restart is not desired the Watchdog timer should be disabled If the user wants to use the normal timer provided by the Watchdog timer enable the interrupt and disable the Watchdog timer WTCON 0x53000000 Watchdog timer control register 0x8021 Prescaler Value 15 8 Prescaler value The valid
51. 1 SDRAM SCKE enable SCLK_EN 4 SCLK is enabled only during SDRAM access cycle for reducing power consumption When SDRAM is not accessed SCLK becomes L level 0 SCLK is always active 1 SCLK is active only during the access recommended BK76MAP 2 0 BANK6 7 memory map 010 010 128MB 128MB 001 64MB 64MB 000 32M 32M 111 16M 16M 110 8M 8M 101 4M 4M 100 2M 2M 5 18 ELECTRONICS 53 2410 MEMORY CONTROLLER SDRAM MODE REGISTER SET REGISTER MRSR MRSRB6 0x4800002C Mode register set register MRSRB7 0x48000030 Mode register set register bank7 WBL Write burst length 0 Burst Fixed 1 Reserved 8 7 Test mode XX 00 Mode register set Fixed 01 10 and 11 Reserved CL 6 4 CAS latency XXX 000 1 clock 010 2 clocks 01123 clocks Others reserved BT 3 Burst type x 0 Sequential Fixed 1 Reserved BL 2 0 Burst length XXX 000 1 Fixed Others Reserved NOTE MRSR register must not be reconfigured while the code is running on SDRAM IMPORTANT NOTES In Power_OFF mode SDRAM has to enter SDRAM self refresh mode ELECTRONICS 5 19 MEMORY CONTROLLER 53 2410 5 20 ELECTRONICS 53 2410 FLASH CONTROLLER NAND FLASH CONTROLLER OVERVIEW Recently a NOR flash memory gets high in price while an SDRAM and a NAND flash memory get moderate motivating some users to execute the boot code on a NAND flash and execute the main
52. 14 10 Priority Register PRIORIDY o e 14 12 Interrupt Pending INTPND A u Sp LS b aa aS tua a atasi nnn nnns 14 14 Interrupt Offset INTOFFSET 14 16 Sub Source Pending SUBSRCPND 14 17 Interrupt Sub Mask INTSUBMSK Register sse eee 14 18 Chapter 15 LCD Controller OVeIVIOWE nU Ue e M 15 1 ILU spp Mc LEE 15 1 Gommon Eeatules nensis eap XL EL asas fs 15 2 External Interface Signal 2 nastro io ita ae hasa Suae 15 2 Block Diagram 5 em DAI iHi hut 15 3 STN LCD Controller Operation suasana aa enn nnns nnns 15 4 Timing Generator U ihres rds nnns innen 15 4 15 5 Dithering and Frame Rate 15 7 Memory Data Format STN BSWP 0 15 9 TE ECD Controller 15 15 kanqa eric sa IEEE 15 15 Memory Data Formar TET ssa rane ca iet ote weer eee 15 16 256 Palette Usage 5
53. 22 4 11 4 11 Instr ction Cycle TImes taa ihah BR ERR Red RED HERO E 4 12 ated hri suem NU 4 12 3C2410A MICROPROCESSOR Table of Contents Continued Chapter 4 Thumb Instruction Set Continued Format 5 Hi Register Operations Branch Exchange OJo Ye W 0 rc cere epee e Instruction Cycle The Bx Instructions rocas ditte a A aito matu eate w tee iae aaah Using R15 asan Operand iiie ee d a eise edt n e o Format oz Pc Relatve Load Biene etie ee ae AEAEE REL EDI HM EH Instruction Cycle cm Format 7 Load Store with Register Offset eese nere nennt nennen eb rr Ep EHE Instruction Cycle pr Format 8 Load Store Sign Extended Byte Halfword ar tef LLLA mc E cM ec do d ELLE Instruction
54. 3 16 level from a total of 16 levels the 3 times pixel should be on and 13 times pixel off In other words 3 frames should be selected among the 16 frames of which 3 frames should have a pixel on on a specific pixel while the remaining 13 frames should have a pixel off on a specific pixel These 16 frames should be displayed periodically This is basic principle on how to display the gray level on the screen so called gray level display by FRC The actual example is shown in Table 15 2 To represent the 141 gray level in the table we should have a 6 7 duty cycle which mean that there are 6 times pixel on and one time pixel off The other cases for all gray levels are also shown in Table 15 2 In the STN LCD display we should be reminded of one item i e Flicker Noise due to the simultaneous pixel on and off on adjacent frames For example if all pixels on first frame are turned on and all pixels on next frame are turned off the Flicker Noise will be maximized To reduce the Flicker Noise on the screen the average probability of pixel on and off between frames should be the same In order to realize this the Time based Dithering Algorithm which varies the pattern of adjacent pixels on every frame should be used This is explained in detail For the 16 gray level FRC should have the following relationship between gray level and FRC 15th gray level should always have pixel on and the 141 gray level should have 6 times pixel on and o
55. 3 9 3 14 3 10 Rotate Right 3 14 3 11 PSR Transtfer u dicere o afar dint veces 3 19 3 12 Multiply 3 22 3 13 Multiply Long 3 25 3 14 Single Data Transfer Instructions a 3 28 3 15 Little Endian Offset Addressing a 3 30 3 16 Halfword and Signed Data Transfer with Register Offset 3 34 3 17 Halfword and Signed Data Transfer with Immediate Offset and Auto Indexing 3 35 3 18 Block Data Transfer Instructions 00000 3 40 3 19 Post Increment 5 3 41 3 20 Pre Increment 3 42 3 21 Post Decrement 3 42 3 22 Pre Decrement 0 3 43 3 23 3 47 3 24 Software Interrupt 3 49 3 25 Coprocessor Data Operation Instruction 3 51 3 26 Coprocessor Data Transfer Instructions
56. 4 18 ELECTRONICS 3C2410A THUMB INSTRUCTION SET OPERATION These instructions transfer byte or word values between registers and memory Memory addresses are pre indexed using an offset register in the range 0 7 The THUMB assembler syntax is shown in Table 4 8 Table 4 8 Summary of Format 7 Instructions STR Rb Ro STR Rb Ro Pre indexed word store Calculate the target address by adding together the value in Rb and the value in Ro Store the contents of Rd at the address STRB Rb Ro STRB Rb Ro Pre indexed byte store Calculate the target address by adding together the value in Rb and the value in Ro Store the byte value in Rd at the resulting address LDR Rb Ro LDR Rb Ro Pre indexed word load Calculate the source address by adding together the value in Rb and the value in Ro Load the contents of the address into LDRB Rad Rb Ro LDRB Rad Rb Ro Pre indexed byte load Calculate the source address by adding together the value in Rb and the value in Ro Load the byte value at the resulting address INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 8 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES STR R3 R2 R6 Store word in R3 at the address formed by adding R6 to R2 LDRB R2 RO R7 Load into R2 the byte found at
57. 5 3 Switching from to BCLK in Synchronous Mode 5 2 5 4 Asynchronous Clocking 1 U n n 5 3 5 5 Switching from to BCLK in Asynchronous 5 3 S3C2410A MICROPROCESSOR xxix 53 2410 PRODUCT OVERVIEW PRODUCT OVERVIEW INTRODUCTION This manual describes SAMSUNG s S3C2410A 16 32 bit RISC microprocessor This product is designed to provide hand held devices and general applications with cost effective low power and high performance micro controller solution in small die size To reduce total system cost the S3C2410A includes the following components separate 16KB Instruction and 16KB Data Cache MMU to handle virtual memory management LCD Controller STN amp TFT NAND Flash Boot Loader System Manager chip select logic and SDRAM Controller 3 ch UART 4 ch DMA 4 ch Timers with PWM I O Ports RTC 8 ch 10 bit ADC and Touch Screen Interface IIC BUS Interface IIS BUS Interface USB Host USB Device SD Host amp Multi Media Card Interface 2 ch SPI and PLL for clock generation 53 2410 was developed using an 920 core 0 18um CMOS standard cells and a memory complier Its low power simple elegant and fully static design is particularly suitable for cost and power sensitive applications It adopts a new bus architecture called Advanced Microcontroller Bus Architecture
58. AIN 7 and AIN 5 see Figure 16 2 Touch Screen Interface controls and selects control signals nXPON and XMON and analog pads AIN 7 AIN 5 which are connected with pads of touch screen panel and the external transistor for X position conversion and Y position conversion Touch Screen Interface contains an external transistor control logic and an ADC interface logic with an interrupt generation logic FEATURES Resolution 10 bit Differential Linearity Error 1 0 LSB Integral Linearity Error 2 0 LSB Maximum Conversion Rate 500 KSPS Low Power Consumption Power Supply Voltage 3 3V Analog Input Range 0 3 3V On chip Sample and hold Function Normal Conversion Mode Separate X Y position conversion Mode Auto Sequential X Y Position Conversion Mode Waiting for Interrupt Mode ELECTRONICS 16 1 ADC AND TOUCH SCREEN INTERFACE 53 2410 ADC amp TOUCH SCREEN INTERFACE OPERATION BLOCK DIAGRAM Figure 16 1 shows the functional block diagram of the 53 2410 A D converter and Touch Screen Interface Note that the A D converter is a recycling type A pull up resister is attached to AIN 7 on VDDA_ADC So XP pad of the touch screen panel should be connected with AIN 7 of the S3C2410A YP pad of the touch screen panel should be connected with AIN 5 External Transistor Control VDDA ADC AIN 7 AIN 6 AIN 5 ADC AIN 4 ND Inter
59. AMBA The S3C2410A offers outstanding features with its CPU core a 16 32 bit ARM920T RISC processor designed by Advanced RISC Machines Ltd The ARM920T implements MMU AMBA BUS and Harvard cache architecture with separate 16KB instruction and 16KB data caches each with an 8 word line length By providing a complete set of common system peripherals the S3C2410A minimizes overall system costs and eliminates the need to configure additional components The integrated on chip functions that are described in this document include e 1 8V 2 0V int 3 3V memory 3 3V external I O microprocessor with 16KB 16 D Cache MMU External memory controller SDRAM Control and Chip Select logic LCD controller up to 4K color STN and 256K color TFT with 1 ch LCD dedicated DMA e 4 ch DMAs with external request pins 3 ch UART IrDA1 0 16 Byte Tx FIFO and 16 Byte Rx FIFO 2 ch SPI e 1 ch multi master IIC BUS 1 ch IIS BUS controller SD Host interface version 1 0 amp Multi Media Card Protocol version 2 11 compatible e 2 port USB Host 1 port USB Device ver 1 1 4 ch PWM timers amp 1 ch internal timer e Watch Dog Timer 117 bit general purpose I O ports 24 ch external interrupt source Power control Normal Slow Idle and Power off mode e 8 ch 10 bit ADC and Touch screen interface RTC with calendar function e On chip clock generator with PLL ELECTRONICS 1 1 PRODUCT OVERVIEW FEATURES
60. Addressing y u 3 41 Address mE 3 41 S 3 43 Rb 3s the Base occae EP D Quay sya e e aspa ess 3 43 Inclusion of the Base in the Register List L nnne nnns 3 44 BB cfe EET 3 44 Instruction Cycle 444 3 44 SVM ton ee 3 45 EET 3 46 Single Data Swap 3 47 3 47 3 48 Data AD OM cM TEE 3 48 Instruction Cycle limes ici 3 48 Assembler u tuh 3 48 Software Interrupt SWI aa aa a aai aaa 3 49 Return from the 3 49 Gomiment Eleld 3 49 Instruction Cycle 2 3 49 BS 3 50 Coprocessor Data Operations 3 51 Coprocessor INStrUuctions Eki tua 3 51
61. Architecture e Integrated system for hand held devices and general embedded applications e 16 32 Bit RISC architecture and powerful instruction set with ARM920T CPU core Enhanced ARM architecture MMU to support WinCE EPOC 32 and Linux e Instruction cache data cache write buffer and Physical address TAG RAM to reduce the effect of main memory bandwidth and latency on performance e ARM920T CPU core supports the ARM debug architecture e Internal Advanced Microcontroller Bus Architecture AMBA AMBA2 0 AHB APB System Manager Little Big Endian support e Address space 128M bytes for each bank total 1G bytes e Supports programmable 8 16 32 bit data bus width for each bank e Fixed bank start address from bank 0 to bank 6 Programmable bank start address and bank size for bank 7 Eight memory banks Six memory banks for ROM SRAM and others Two memory banks for ROM SRAM Synchronous DRAM e Fully Programmable access cycles for all memory banks e Supports external wait signals to expend the bus cycle e Supports self refresh mode in SDRAM for power down e Supports various types of ROM for booting NOR NAND Flash EEPROM and others 1 2 S3C2410A NAND Flash Boot Loader Supports booting from NAND flash memory internal buffer for booting e Supports storage memory for NAND flash memory after booting Cache Memory e 64 way set associative cache with
62. BSWP 0 Mono 4 bit Dual Scan Display Video Buffer Memory Address Data 0000 A 31 0 0004H B 31 0 LCD Panel A 31 A 30 L 31 L 30 1000H L 31 0 1004H M 31 0 Mono 4 bit Single Scan Display amp 8 bit Single Scan Display Video Buffer Memory LCD Panel Address Data 0000H 31 0 0004H B 31 0 0008H C 31 0 A 31 A 30 A 29 ELECTRONICS 15 9 LCD CONTROLLER S3C2410A MEMORY DATA FORMAT STN BSWP 0 Continued In 4 level gray mode 2 bits of video data correspond to 1 pixel In 16 level gray mode 4 bits of video data correspond to 1 pixel In 256 level color mode 8 bits 3 bits of red 3 bits of green and 2 bits of blue of video data correspond to 1 pixel The color data format in a byte is as follows musa Gem me In 4096 level color mode 12 bits 4 bits of red 4 bits of green 4 bits of blue of video data correspond to 1 pixel The following table shows color data format in words Video data must reside at 3 word boundaries 8 pixel as follows RGB Order para mesa pra 8 15 10 ELECTRONICS 3C2410A LCD CONTROLLER 4 bit Dual Scan Display 4 bit Single Scan Display 8 bit Single Scan Display Figure 15 2 Monochrome Display Types STN ELECTRONICS 15 11 LCD CONTROLLER S3C2410A VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 R1 G1 B1 R2 G2 B2 R3 G3 1 Pixel VD7
63. ELECTRONICS 3 2410 ELECTRICAL DATA gt XnBREQ XnBACK Figure 24 10 External Bus Request in ROM SRAM Cycle 0 Tcos 0 Tacc 8 0 Tcah 0 PMC 0 ST 0 Tacs ELECTRONICS 24 10 S3C2410A ELECTRICAL DATA l gt Figure 24 11 ROM SRAM READ Timing 1 Tacs 2 Tcos 2 Tacc 4 Tcoh 2 Tcah 2 PMC 0 ST 0 ELECTRONICS 24 11 ELECTRICAL DATA S3C2410A gt I Figure 24 12 ROWSRAM READ Timing 1 Tacs 2 Tcos 2 Tacc 4 Tcoh 2 Tcah 2 PMC 0 ST 1 24 12 ELECTRONICS ELECTRICAL DATA S3C2410A Figure 24 13 ROWSRAM WRITE Timing 1 2 Tcos 0 2 Tacc 4 Tcoh 2 Tcah 2 PMC 0 ST Tacs 24 13 ELECTRONICS S3C2410A ELECTRICAL DATA Figure 24 14 ROM SRAM WRITE Timing Il 2 Tcos 2 Tacc 4 Tcoh 2 Tcah 2 PMC 0 ST 1 Tacs ELECTRONICS 24 14 ELECTRICAL DATA 53 2410 it a The status of nWait is checked at 1 cycle NOTE 0 ST 0 0 Tcah 1 PMC 4 Tcoh Figure 24 15 External nWAIT READ Timing Tacs 1 Tcos 1 Tacc 4 cycles A o o G 5 o o ER Ee E 45 c be Ll di 28 a T 9
64. Figure 2 6 Program Status Register Formats ELECTRONICS 2 7 PROGRAMMER S MODEL 53 2410 The Condition Code Flags The N Z C and V bits are the condition code flags These may be changed as a result of arithmetic and logical operations and may be tested to determine whether an instruction should be executed In ARM state all instructions may be executed conditionally see Table 3 2 for details In THUMB state only the Branch instruction is capable of conditional execution see Figure 3 46 for details The Control Bits The bottom 8 bits of a PSR incorporating F T and M 4 0 are known collectively as the control bits These will be changed when an exception arises If the processor is operating in a privileged mode they can also be manipulated by software The T bit This reflects the operating state When this bit is set the processor is executing in THUMB state otherwise it is executing in ARM state This is reflected on the TBIT external signal Note that the software must never change the state of the TBIT in the CPSR If this happens the processor will enter an unpredictable state Interrupt disable The and F bits are the interrupt disable bits When set these disable the IRQ and FIQ bits interrupts respectively The mode bits The M4 M3 M2 M1 and MO bits M 4 0 are the mode bits These determine the processor s operating mode as shown in Table 2 1 Not all combinations of the mode bits define a valid proces
65. GPE7 15 14 Input 01 Output 10 SDDATO 11 Reserved GPE6 13 12 Input 01 Output 52 SDCMD 11 Reserved GPE5 11 10 Input 01 Output Ta SDCLK 11 Reserved GPE4 Input 01 Output m 125500 11 12550 GPE3 7 6 Input 01 Output 12550 11 nSS0 GPE2 5 4 Input 01 Output K CDCLK 11 Reserved GPE1 3 2 Input 01 Output l2SSCLK 11 Reserved GPEO 1 0 00 Input 01 Output 10 l2SLRCK 11 Reserved 9 14 ELECTRONICS 3 2410 PORTS GPEDAT GPE 15 0 15 0 When the port is configured as input port data from external sources can be read to the corresponding pin When the port is configured as output port data written in this register can be sent to the corresponding pin When the port is configured as a functional pin undefined value will be read B BesHlm GPE 13 0 13 0 0 The pull up function attached to to the corresponding port pin is enabled 1 The pull up function is disabled ELECTRONICS 9 15 PORTS 53 2410 PORT CONTROL REGISTERS GPFCON GPFDAT and GPFPU If GPF7 are used for wakeup signals Power OFF mode the ports must be configured as external interrupt set in Interrupt mode Reserved 7 15 14 Input 01 Output 15 EINT7 11 Reserved GPF6 13 12 Input 01 Output EINT6 11 Reserved GPF5 11 10
66. Input 01 Output EINT5 11 Reserved GPF4 Input 01 Output 112 EINT4 11 Reserved 7 6 01 Output 152 11 Reserved GPF2 5 4 Input 01 Output ic EINT2 11 Reserved GPF1 3 2 Input 01 Output 12 EINT1 11 Reserved GPFO 1 0 Input 01 Output Us EINTO 11 Reserved 5 1 Geor Sk 711 GPF 7 0 7 0 When the port is configured as input port data from external sources can be read to the corresponding pin When the port is configured as output port data written in this register can be sent to the corresponding pin When the port is configured as functional pin undefined value will be read 2 GPFUP Bescpon O GPFT 7 0 7 0 0 The pull up function attached to to the corresponding port pin is enabled 1 The pull up function is disabled 9 16 ELECTRONICS 53 2410 PORTS PORT CONTROL REGISTERS GPGCON GPGDAT AND GPGUP If GPG 7 0 are used for wakeup signals in Power_OFF mode the ports must be configured as external interrupt set in Interrupt mode RW C Reseved oxS600006c Rene GPGCON Bit Description GPG15 31 30 00 Input 01 Output 10 EINT23 11 GPG14 29 28 00 Input 01 Output 10 EINT22 11 GPG13 27 26 00 Input 01 Output 10 EINT21 11 GPG12 25 24 00 Input 01 Output 10 EINT20 11 GPG11 23 22 00 Input 01 Output 10
67. Lookup Table The S3C2410A can support the lookup table for various selection of color or gray level mapping ensuring flexible operation for users The lookup table is the palette which allows the selection on the level of color or gray Selection on 4 gray levels among 16 gray levels in case of 4 gray mode selection on 8 red levels among 16 levels 8 green levels among 16 levels and 4 blue levels among 16 levels in case of 256 color mode In other words users can select 4 gray levels among 16 gray levels by using the lookup table in the 4 gray level mode The gray levels cannot be selected in the 16 gray level mode all 16 gray levels must be chosen among the possible 16 gray levels In case of 256 color mode 3 bits are allocated for red 3 bits for green and 2 bits for blue The 256 colors mean that the colors are formed from the combination of 8 red 8 green and 4 blue levels 8x8x4 256 In the color mode the lookup table can be used for suitable selections Eight red levels can be selected among 16 possible red levels 8 green levels among 16 green levels and 4 blue levels among 16 blue levels In case of 4096 color mode there is no selection as in the 256 color mode Gray Mode Operation The S3C2410A LCD controller supports two gray modes 2 bit per pixel gray 4 level gray scale and 4 bit per pixel gray 16 level gray scale The 2 bit per pixel gray mode uses a lookup table BLUELUT which allows selection on 4 gray levels among 16 pos
68. REGISTER TICNT 0x57000044 L R W Tick time count register 0x0 0x57000047 B by byte TICK INT ENABLE 7 Tick time interrupt enable 0 Disable 1 Enable TICK TIME COUNT Tick time count value 17127 000000 This counter value decreases internally and users cannot read this counter value in working ELECTRONICS 17 5 REAL TIME CLOCK RTC 53 2410 RTC ALARM CONTROL RTCALM REGISTER The RTCALM register determines the alarm enable and the alarm time Note that the RTCALM register generates the alarm signal through both ALMINT and PMWKUP in power down mode but only through ALMINT in the normal operation mode RTCALM 0x57000050 L R W RTC alarm control register 0x0 0x57000053 B by byte eU ALMEN Alarm global enable 0 Disable 1 Enable YEAREN 5 Year alarm enable 0 Disable 1 Enable MONREN 4 Month alarm enable 0 Disable 1 Enable DATEEN 3 Date alarm enable 0 Disable 1 Enable HOUREN 2 Hour alarm enable 0 Disable 1 Enable MINEN 1 Minute alarm enable 0 Disable 1 Enable SECEN Second alarm enable 0 Disable 1 Enable 17 6 ELECTRONICS 3C2410A REAL TIME CLOCK RTC ALARM SECOND DATA ALMSEC REGISTER ALMSEC 0x57000054 L R W Alarm second data register 0x0 0x57000057 B by byte mew a SECDATA 6 4 BCD value for alarm second 0 5 13 0 0 0000 ALARM MIN DATA ALMMIN REGISTER ALMMIN 0x57000058 L R W
69. Requested 22 0 Not requested 1 Requested EINTPEND EINT23 EINT22 EINT21 EINT20 EINT19 EINT18 EINT17 EINT16 EINT15 EINT14 EINT13 EINT12 EINT11 EINT10 21 0 Not requested 12 Requested 20 0 Not requested 1 Requested 19 0 Not requested 1 Requested 18 0 Not requested 1 Requested 17 0 Not requested 1 Requested 16 0 Not requested 1 Requested 15 0 Not requested 1 Requested 14 0 Not requested 1 Requested 13 0 Not requested 1 Requested 12 0 Not requested 1 Requested 11 0 Not requested 1 Requested 10 0 Not requested 1 Requested EINT9 0 Not requested 1 Requested EINT8 0 Not requested 1 Requested EINT7 7 0 Not requested 1 Requested ERE 5 EN 2 po jo ELECTRONICS 9 27 PORTS 53 2410 GENERAL STATUS REGISTER GSTATUSn GSTATUS1 0x560000B0 R 0x32410002 0 1 GSTATUS3 0x560000B8 R W Infrom register 0x0 nWAIT Status of nWAIT pin NCON Status of NCON pin nBATT FLT J Status of nBATT pin CHIP ID 31 0 ID register 0x32410002 B PWRST Power on reset if this bit is set to 1 wer The setting is cleared by writing 1 to this bit OFFRST 1 Power OFF reset The reset after the wakeup from Power OFF mode The setting is cleared by writing 1 to this bit Watchdog reset The reset derived from Watchdog timer The setting is cleared by writing 1 to this bit INF
70. Vpp 1 8V 0 15 2 0 V 0 1 V T4 40 to 85 C 3 3V 0 3V Sym Typ Max nts back porch delay vertical ont porch dealy _______ veron vokmkewanmg o5 Pe wokmkewanow o5 Pw Hayne setup to VOLK taling 95 Pe setup to VOLK fling sde Wexwup os Pick hold from VOLK taling edge os Pe 0 setupto VOLK aling edge os Pick VD hod fom VCLK fling edge __ 5 Pe Tem 1 Pw LEND hoia fom VOLK Tema 3 setup to HSYNC fling edge Temeup VSYNC hold from HSYNC falling edge Tf2hhold HBPD HFPD Pvclk HOZVAL 4 3 NOTES 1 HSYNC period 2 VCLK period Table 24 12 15 Controller Module Signal Timing Constants 1 8V 0 15 2 0 V 0 1 V TA 40 to 85 3 3V 0 3V Symbo Min Typ Unit humane _ ne _ SS ILS CODEC clock frequency copEc 1 16 BLOCK 24 34 ELECTRONICS 53 2410 ELECTRICAL DATA Table 24 13 BUS Controller Module Signal Timing 1 8 0 15 2 0 V 0 1 V T4 40 to 85 C 3 3V 0 3V SCL clock frequency std 100 kH
71. executed otherwise it is ignored There are sixteen possible conditions each represented by a two character suffix that can be appended to the instruction s mnemonic For example a Branch B in assembly language becomes BEQ for Branch if Equal which means the Branch will only be taken if the Z flag is set In practice fifteen different conditions may be used these are listed in Table 3 2 The sixteenth 1111 is reserved and must not be used In the absence of a suffix the condition field of most instructions is set to Always suffix AL This means the instruction will always be executed regardless of the CPSR condition codes Table 3 2 Condition Code Summary wm js 3 4 ELECTRONICS 3C2410A ARM INSTRUCTION SET BRANCH AND EXCHANGE BX This instruction is only executed if the condition is true The various conditions are defined in Table 3 2 This instruction performs a branch by copying the contents of a general register Rn into the program counter PC The branch causes a pipeline flush and refill from the address specified by Rn This instruction also permits the instruction set to be exchanged When the instruction is executed the value of Rn 0 determines whether the instruction stream will be decoded as ARM or THUMB instructions 28 27 24 23 20 19 16 15 12 11 MONEE EER KEE 3 0 Operand Register If bitO of Rn 1 subsequ
72. nXDACK 1 0 O External DMA acknowledge ELECTRONICS 1 21 PRODUCT OVERVIEW 3 2410 Table 1 3 S3C2410A Signal Descriptions Continued ogg moo O UART transmits data output nots fro 1 ART ear to o SSS O UARTrequestto send 1 19 ius clock Open isswadsanpu ___ iO O CODEC O Minus convoi o Pius Y axis o Minus Y axis on off DATA from USB host 15Kohm pull down DATA from USB host 15Kohm pull down DATA for USB peripheral 470Kohm pull down DATA for USB peripheral 1 5Kohm pull up SPIMISO 1 0 SPIMISO is the master data input line when SPI is configured as a master When SPI is configured as a slave these pins reverse its role SPIMOSI 1 0 SPIMOSI is the master data output line when SPI is configured as a master When SPI is configured as a slave these pins reverse its role SPICLK 1 0 SPI clock nSS 1 0 SPI chip select only for slave mode 1 22 ELECTRONICS 3 2410 PRODUCT OVERVIEW Table 1 3 S3C2410A Signal Descriptions Continued SDDAT 3 0 SD receive transmit data SDCMD SD receive response transmit command SDCLK SD cloc
73. o s KENN 7 10 ELECTRONICS 53 2410 CLOCK 8 POWER MANAGEMENT NORMAL Mode In normal mode all peripherals and the basic blocks including power management block the CPU core the bus controller the memory controller the interrupt controller DMA and the external master may operate fully But the clock to each peripheral except the basic blocks can be stopped selectively by software to reduce the power consumption IDLE Mode In IDLE mode the clock to the CPU core is stopped except the bus controller the memory controller the interrupt controller and the power management block To exit the IDLE mode EINT 23 0 or RTC alarm interrupt or the other interrupts should be activated EINT is not available until GPIO block is turned on SLOW Mode Non PLL Mode Power consumption can be reduced in the SLOW mode by applying a slow clock and excluding the power consumption from the PLL The is the frequency of divide by n of the input clock XTlpll or EXTCLK without PLL The divider ratio is determined by SLOW VAL in the CLKSLOW control register and CLKDIVN control register Table 7 3 CLKSLOW and CLKDIVN Register Settings for SLOW Clock SLOW VAL FCLK HCLK PCLK UCLK 1 1 Option 1 2 Option 1 1 Option 1 2 Option 0 HDIVN 1 PDIVN 0 PDIVN 1 EXTCLK or EXTCLK or EXTCLK or HCLK HCLK 2 48 MHz XTIpll 1 XTIpll 1 2 0 0 1 EXTCLK or EXTCLK or EXTCLK or HCLK HCLK 2 48 MHz
74. tentent hase etudes eth meses dde Format 13 Add Offset To Stack 2 2242440 0 s sa arbe ch ACA ec M cea MIA Instruction Cycle Examples renr re eee M aU cece T Format 14 Push Pop a aS Sam Su s na TI TAEAE E EERE ODOration usc E E E E TTE A T Instruction Cycle Times u apun Saa E AEA A tete ite ta esate Format 15 Multiple nenas nnns Md Instruction Cycle Examples suan uH Dem INA IS NALE 53 2410 MICROPROCESSOR vii Table of Contents Continued Chapter 4 Thumb Instruction Set Continued Format 16 Conditional 4 34 s C emu i ce asas Gs sit apasi 4 34 Instruction Cycle T imaes saqmasaq asta eR Dine 4 35 onto etu ei IEEE LI vH UI ie 4 35 Format 17 So
75. which can be seen on the CPCLK output as shown in Figure 5 1 GCLK can be sourced from either BCLK or FCLK depending on the clocking mode selected using nF bit and iA bit in CP15 register 1 see Register 1 Control register on page 2 10 The three clocking modes are FastBus synchronous and asynchronous The ARM920T is a static design and both clocks can be stopped indefinitely without loss of state From Figure 5 1 it can be seen that some of the ARM920T macrocell signals will have timing specified with relation to GCLK which can be either FCLK or BCLK depending on the clocking mode CPCLK ARM920T I O AMBA bus Rest of ARM920T interface Figure 5 1 ARM920T Clocking ELECTRONICS 5 1 CLOCK MODES ARM920T PROCESSOR FASTBUS MODE In this mode of operation the BCLK input is the source for GCLK The FCLK input is ignored This mode is typically used in systems with high speed memory SYNCHRONOUS MODE This mode is typically used in systems with low speed memory In this mode GCLK can be sourced from BCLK and BCLK is used to control the AMBA memory interface FCLK is used to control the internal ARM9TDMI processor core and any cache operations FCLK must have a higher frequency and must also be an integer multiple of BCLK with a BCLK transition only when FCLK is HIGH An example is shown in Figure 5 2 Figure 5 2 Synchronous Clocking Mode If the ARM920T performs an external access for example a cache linefill the A
76. which is driven by the timer clock When the down counter reaches zero the timer interrupt request is generated to inform the CPU that the timer operation has been completed When the timer counter reaches zero the value of corresponding TCNTBn is automatically loaded into the down counter to continue the next operation However if the timer stops for example by clearing the timer enable bit of TCONn during the timer running mode the value of TCNTBn will not be reloaded into the counter The value of TCMPBn is used for pulse width modulation PWM The timer control logic changes the output level when the down counter value matches the value of the compare register in the timer control logic Therefore the compare register determines the turn on time or turn off time of an PWM output FEATURE Five 16 bit timers Two 8 bit prescalers amp Two 4 bit divider Programmable duty control of output waveform PWM Auto reload mode or one shot pulse mode Dead zone generator ELECTRONICS 10 1 PWM TIMER 3 2410 TCMPBO TCNTBO i Dead Zone Generator Control LogicO TCMPB1 TCNTB1 Control Divider Logic TCMPB2 TCNTB2 8 Bit Prescaler Control p Logic2 8 Bit TCMPB3 TCNTB3 Prescaler Clock Control gt Divider Logic3 TCNTB4 Control Logic4 Figure 10 1 16 bit PWM Timer Block Diagram 10 2 ELECTRONICS 53 2410 P
77. 0 0 15 8 D 23 16 gt D 31 24 0 31 24 D 23 16 2 D 15 8 D 7 0 SDI Baud Rate Prescaler SDIPRE Register SDIPRE 0x5A000004 SDI baud rate prescaler register Prescaler Value 7 0 Determine SDI clock SDCLK rate as above equation 0x00 Baud rate PCLK 2 Prescaler value 1 ELECTRONICS 19 5 MMC SD SDIO HOST CONTROLLER S3C2410A SDI Command Argument Register SDICARG Register Address R W Description Reset Value SDICARG 0x5A000008 SDI command argument register 0 0 CmdArg 31 0 Command Argument 0x00000000 SDI Command Control SDICCON Register Reset Value SDICCON 0x5A00000C SDI command control register 0x0 SDICCON Bit Description Initial Value Abort Command 12 Determine whether command type is for abort for SDIO AbortC md 0 normal command 1 abort command CMD12 CMD52 Command with 11 Determine whether command type is with data for SDIO Data WithData 0 without data 1 with data LongRsp 10 Determine whether host receives a 136 bit long response or not 0 short response 1 long response WaitRsp Determine whether host waits for a response or not 0 no response 1 wait response Command Determine whether command operation starts or not Start CMST 0 command ready 1 command start Cmdindex 7 0 Command index with start 2 bit 8 bit 19 6 ELECTRONICS 53 2410 MMC SD SDIO HOST CONTROLLER SDI Command Status SDICSTA Register
78. 0 __ v _______ 24 Link bit 0 Branch 1 Branch with link 31 28 Condition Field Figure 3 3 Branch Instructions Branch instructions contain a signed 2 s complement 24 bit offset This is shifted left two bits sign extended to 32 bits and added to the PC The instruction can therefore specify a branch of 32Mbytes The branch offset must take account of the prefetch operation which causes the PC to be 2 words 8 bytes ahead of the current instruction Branches beyond 32Mbytes must use an offset or absolute destination which has been previously loaded into a register In this case the PC should be manually saved in R14 if a Branch with Link type operation is required THE LINK BIT Branch with Link BL writes the old PC into the link register R14 of the current bank The PC value written into R14 is adjusted to allow for the prefetch and contains the address of the instruction following the branch and link instruction Note that the CPSR is not saved with the PC and R14 1 0 are always cleared To return from a routine called by Branch with Link use MOV PC R14 if the link register is still valid or LDM Rn P C if the link register has been saved onto a stack pointed by Rn INSTRUCTION CYCLE TIMES Branch and Branch with Link instructions take 2S 1N incremental cycles where S and N are defined as sequential S cycle and internal ELECTRONICS 3 7 ARM INSTRUCTION S
79. 0 32 Read only Receive FIFO data count 5 0 Data count value 0 32 000000 Read only NOTES 1 IISFCON register is accessible for each halfword and word unit using STRH STR and LDRH LDR instructions or short int int type pointer in Little Big endian mode 2 Li HW W Little HalfWord Word Bi HW W Big HalfWord Word IIS FIFO IISFIFO REGISTER 15 bus interface contains two 64 byte FIFO for the transmit and receive mode Each FIFO has 16 width and 32 depth form which allows the FIFO to handles data for each halfword unit regardless of valid data size Transmit and receive FIFO access is performed through FIFO entry the address of FENTRY is 0x55000010 0x5500001 0 Li HW IIS FIFO register 0x55000012 Bi HW FENTRY 15 0 Transmit Receive data for IIS 0x0 NOTES 1 IISFIFO register is accessible for each halfword and word unit using and LDRH instructions or short int type pointer in Little Big endian mode 2 Li HW Little HalfWord Bi HW Big HalfWord 21 8 ELECTRONICS 53 2410 SPI INTERFACE SPI INTERFACE OVERVIEW 53 2410 Serial Peripheral Interface SPI can interface the serial data transfer The S3C2410A includes two SPI each of which has two 8 bit shift registers for transmission and receiving respectively During an SPI transfer data is simultaneously transmitted shifted out serially and received shifted in serially 8 bit serial da
80. 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered ELECTRONICS 9 23 PORTS 53 2410 ExTINT2 Bi O FLTEN23 31 Filter Enable for EINT23 0 Disable 1 Enable EINT23 30 28 Set the signaling method of the EINT23 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered FLTEN22 27 Filter Enable for EINT22 0 Disable 1 Enable EINT22 26 24 Set the signaling method of the EINT22 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered FLTEN21 23 Filter Enable for EINT21 0 Disable 1 Enable EINT21 22 20 Set the signaling method of the EINT21 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered FLTEN20 19 Filter Enable for EINT20 0 Disable 1 Enable EINT20 18 16 Set the signaling method of the EINT20 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered FLTEN19 15 Filter Enable for EINT19 0 Disable 1 Enable EINT19 14 12 Set the signaling method of the EINT19 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered FLTEN18 11 Filter Enable for EINT18 Disable 12 Enable EINT18 10 8 Set the signaling me
81. 1 interrupt enable 1 interrupt enable 19 15 MMC SD SDIO HOST CONTROLLER S3C2410A SDI Data Timer Register SDI data busy timer register has 16 bit counter In case of 25MHz operation the countable maximum time is 2 6ms 40ns 0x10000 But some cards have very long access time TAAC their TAAC are up to 100ms In this case the SDI generates data timeout error state To solve this problem follow the below flow chart Start Read multil or single block Is timeout occurs 25MHz or 600KHz Send stop command Change SDI clock to 600KHz Send stop command if multi block Retry Y Change SDI clock to 25MHz if 600KHz ZG 600KHz Real timeout error 19 16 ELECTRONICS 53 2410 INTERFACE IIC BUS INTERFACE OVERVIEW The S3C2410A RISC microprocessor can support a multi master serial interface A dedicated serial data line SDA and a serial clock line SCL carry information between bus masters and peripheral devices which are connected to the The SDA and SCL lines are bi directional In multi master IIC bus mode multiple S3C2410A RISC microprocessors can receive or transmit serial data to or from slave devices The master S3C2410A can initiate and terminate a data transfer over the IIC bus The IIC bus in the S3C2410A uses Standard bus arbi
82. 1 272 FBGA 1414 Package Dimension 1 25 1 25 2 272 FBGA 1414 Package Dimension 2 Bottom View 25 2 3C2410A MICROPROCESSOR XXV List of Figures Concluded Figure Title Page Number Number 1 1 ARM920T Functional Block 1 2 2 1 CP15 MRC and MCR Bit Pattern enne enne nns 2 5 2 2 Register 7 MVA Format cer da coe tci ee cane oi d etia Ra Rn qa eran 2 17 2 3 Register 7 Index 2 17 2 4 Register 8 MVA Formatl na 2 18 2 5 Register eet an iit aene A dr e e dee 2 20 2 6 Register 10 25 ii e uni de iturum eet eta 2 21 2 7 CETO EE mL 2 22 2 8 Address Mapping Using CP15 Register 13 2 23 3 1 Translating Page 2 088 3 5 3 2 Translation Table Base 3 6 3 3 Accessing the Translation Table Level One Descriptors 3 7 3 4 Level One 3 8 3 5 SECTION THANSIALIOM seca 2 EIE 3 10 3 6 Page Table Entry Level One Descriptor 3 11 3 7 Large Page Translation from a Coarse Page 3 13 3 8 Small Page Translation from a Coarse Page
83. 13 14 ELECTRONICS 53 2410 USB DEVICE END POINT IN CONTROL STATUS REGISTER IN_CSR1_REG IN_CSR2_REG Continued IN PKT RDY 0 R SET CLEAR Set by the MCU after writing a packet of data into the FIFO The USB clears this bit once the packet has been successfully sent to the host An interrupt is generated when the USB clears this bit so the MCU can load the next packet While this bit is set the MCU will not be able to write to the FIFO If the MCU sets SEND STALL bit this bit cannot be set IN CSR2 REG 0x52000188 L IN END POINT control status register2 0x20 0x5200018B B byte AUTO SET 7 RAN If set whenever the MCU writes MAXP data IN PKT RDY will automatically be set by the core without any intervention from MCU If the MCU writes less than MAXP data IN PKT bit has to be set by MCU ISO Used only for endpoints whose transfer type is programmable 1 Reserved 0 Configures endpoint to Bulk mode MODE 5 Used only for endpoints whose direction is 1 programmable 1 Configures Endpoint Direction as IN 0 Configures Endpoint Direction as OUT IN DMA INT EN 4 Determine whether the interrupt should be issued or not when the IN PKT RDY condition happens This is only useful for DMA mode 0 Interrupt enable 1 Interrupt Disable ELECTRONICS 13 15 USB DEVICE 53 2410 END POINT OUT CONTROL STATUS REGISTER OUT CSR1 REG OUT CSR2 REG OUT CSR1 REG 0x52000190 L R W E
84. 256K Color Reflective a Si TFT LCD LTS350Q1 PD1 TFT LCD panel with touch panel and front light unit LTS350Q1 PD2 TFT LCD panel only NOTE WinCE doesn t support the 12 bit packed data format Please check if WinCE can support the 12 bit color mode EXTERNAL INTERFACE SIGNAL VFRAME VSYNC STV Frame synchronous signal STN vertical synchronous signal TFT SEC TFT signal VLINE HSYNC CPV Line synchronous pulse signal STN horizontal sync signal TFT SEC TFT signal VCLK LCD HCLK Pixel clock signal STN TFT SEC TFT signal VD 23 0 LCD pixel data output ports STN TFT SEC TFT VM VDEN TP AC bias signal for the LCD driver STN data enable signal TFT SEC TFT signal LEND STH Line end signal TFT SEC TFT signal LCD PWREN LCD panel power enable control signal LCDVFO SEC TFT Signal OE LCDVF1 SEC TFT Signal REV LCDVF2 SEC TFT Signal REVB The 33 output ports in total includes 24 data bits and 9 control bits 15 2 ELECTRONICS 3C2410A LCD CONTROLLER BLOCK DIAGRAM System Bus VCLK LCD_HCLK VLINE HSYNC CPV VFRAME VSYNC STV VIDEO MUX LPC3600 LCDVFO LCDVF1 LCDVF2 LCDCDMA VIDPRCS VD 23 0 LPC3600 is a timing control logic unit for LTS350Q1 PD1 or LTS350Q1 PD2 Figure 15 1 LCD Controller Block Diagram The S3C2410A LCD controller is used to transfer the video data and to generate the necessary control signals such VFRAME VLINE VM and so on In
85. 28 27 26 25 24 23 22 21 12 11 0 oon _ 22 Destination PSR 0 1 SPSR_ lt current mode gt 25 Immediate Operand 0 Source operand is a register 1 SPSHR current mode gt 11 0 Source Operand 0 m 8 0 Source Register 11 4 Source operand is an immediate value 11 8 7 0 Rowe mm 7 0 Unsigned 8 bit immediate value 11 8 Shift applied to Imm 31 28 Condition Field Figure 3 11 PSR Transfer ELECTRONICS 3 19 ARM INSTRUCTION SET 53 2410 RESERVED BITS Only twelve bits of the PSR are defined in ARM920T N Z C V I F T amp M 4 0 the remaining bits are reserved for use in future versions of the processor Refer to Figure 2 6 for a full description of the PSR bits To ensure the maximum compatibility between ARM920T programs and future processors the following rules should be observed e The reserved bits should be preserved when changing the value a PSR e Programs should not rely on specific values from the reserved bits when checking the PSR status since they may read as one or zero in future processors A read modify write strategy should therefore be used when altering the control bits of any PSR register this involves transferring the appropriate PSR register to a general register using the MRS instruction changing only the relevant bits and then transferring the modified value back to the PSR register using the MSR instru
86. 4 Count Buffer Register 10 19 Timer 4 Count Observation Register TCNTO4 nnns 10 19 Chapter 11 UART OVEINIEW 11 1 oatules sitame cutem unt ten ce ve M 11 1 BlockDiagram tetto taut eio tentat aite auem uas 11 2 Dart a desit metto a ue en turis dites Aet D e e 11 3 Special Begisters a e eei au smt med tbt a aaa sua s am A LA LI Maree heey 11 10 Uart Line Control Register nennen nnn trennen 11 10 Jar Control Register avesse atu Stm dto 11 11 FIFO Control 11 13 Uart Modem Control Register n ann 11 14 Wart o bb oae Ndi cg eet sata Rb tae 11 15 Error Status 11 16 WartiFIFO Status Register ento eene te ea eom er o e d 11 17 Uart Modem Status Register 11 18 Uart Transmit Buffer Register Holding Register amp FIFO Register 11 19 Receive Buffer Register Holdin
87. 46 Save RO to R3 to use as workspace and R14 for returning This nested call will overwrite R14 Restore workspace and return ELECTRONICS 53 2410 ARM INSTRUCTION SET SINGLE DATA SWAP SWP 28 27 23 22 21 20 19 16 15 12 11 z Ple pow e L 3 0 Source Register 15 12 Destination Register 19 16 Base Register 22 Byte Word Bit 0 Swap word quantity 1 Swap word quantity 31 28 Condition Field Figure 3 23 Swap Instruction The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 23 The data swap instruction is used to swap a byte or word quantity between a register and external memory This instruction is implemented as a memory read followed by a memory write which are locked together the processor cannot be interrupted until both operations have completed and the memory manager is warned to treat them as inseparable This class of instruction is particularly useful for implementing software semaphores The swap address is determined by the contents of the base register Rn The processor first reads the contents of the swap address Then it writes the contents of the source register Rm to the swap address and stores the old memory contents in the destination register Rd The same register may be specified as both the source and destination The LOCK output goes HIGH for the du
88. 5 Figure 5 5 Switching from FCLK to BCLK in Asynchronous Mode ELECTRONICS 5 3 CLOCK MODES ARM920T PROCESSOR NOTES 5 4 ELECTRONICS S3C SERIES MASK ROM ORDER FORM Product description Device Number S3C write down the ROM code number Product Order Form Pellet Wafer Package Type Package Marking Check One Standard Custom 10 chars Max 10 chars each line SEC YWW YWW YWW Device Name Device Name o E Assembly site code Y Last number of assembly year WW Week of assembly Delivery Dates and Quantities ROM code Not applicable See ROM Selection Form Risk order See Risk Order Sheet Please answer the following questions For what kind of product will you be using this order New product Upgrade of an existing product Replacement of an existing product Other If you are replacing an existing product please indicate the former product name 5 What are the main reasons you decided to use a Samsung microcontroller in your product Please check all that apply Price Product quality Features and functions Development system Technical support Delivery time Used same micom before Quality of documentation Samsung reputation Mask Charge US Won Customer Information Company Name Telephone number Signatures Person pla
89. 53 2410 SPI SPECIAL REGISTERS SPI CONTROL REGISTER SPI INTERFACE SPCONO 0x59000000 SPI channel 0 control register SPCON1 0 59000020 R W channel 1 control register Determine how and by what SPTDAT is read written 00 polling mode 01 interrupt mode SPI Mode Select SMOD SCK Enable ENSCK Master Slave Select MSTR Clock Polarity Select 2 CPOL Clock Phase Select 1 CPHA Tx Auto Garbage Data mode enable TAGD ELECTRONICS 10 DMA mode 11 reserved Determine whether you want SCK enable or not for only master 0 disable 1 enable Determine the desired mode master or slave 0 slave 1 master NOTE n slave mode there should be set up time for master to initiate Tx Rx 0 Determine an active high or active low clock 0 active high 1 active low Select one of two fundamentally different transfer formats 0 format A 1 format B Decide whether the receiving data only needs or not 0 normal mode 1 Tx auto garbage data mode NOTE n normal mode if you only want to receive data you should transmit dummy OxFF data 22 7 SPI INTERFACE 3C2410A SPI STATUS REGISTER SPSTAO 0x59000004 SPI channel 0 status register SPSTA1 ox59000024 R SPI channel 1 status register Data Collision Error This flag is set if the SPTDATn is written or the SPRDATn DCOL is read while a transfer is in progress and cleared by readin
90. 8 NA 1 1 1 2 2 1 3 4 NOTES 1 Where PC is the address of the BL SWI Undefined Instruction fetch which had the prefetch abort 2 Where PC is the address of the instruction which did not get executed since the FIQ or IRQ took priority 3 Where PC is the address of the Load or Store instruction which generated the data abort 4 The value saved in R14_svc upon reset is unpredictable FIQ The FIQ Fast Interrupt Request exception is designed to support a data transfer or channel process and in ARM state has sufficient private registers to remove the need for register saving thus minimizing the overhead of context switching FIQ is externally generated by taking the nFIQ input LOW This input can except either synchronous or asynchronous transitions depending the state of the ISYNC input signal When ISYNC is LOW nFIQ and are considered asynchronous and a cycle delay for synchronization is incurred before the interrupt can affect the processor flow Irrespective of whether the exception was entered from ARM or Thumb state a FIQ handler should leave the interrupt by executing SUBS PC R14_fiq 4 FIQ may be disabled by setting the CPSR s F flag but note that this is not possible from User mode If the F flag is clear ARM920T checks for a LOW level on the output of the FIQ synchronizer at the end of each instruction ELECTRONICS 2 11 PROGRAMMER S MODEL S3C2410A IRQ The IRQ Interrupt Request excep
91. DMA Run Observation IN DMA RUN 1 R W Start DMA operation 0 Stop 1 R W R Set DMA mode If the IN RUN OB has been CLEAR wrtten as 0 and reaches 0 DMA_MODE_EN bit will be cleared by USB 0 Interrupt mode 1 DMA mode lt lt lt lt lt lt 0 j 1 ELECTRONICS 13 21 USB DEVICE 53 2410 UNIT COUNTER REGISTER UNIT This register is valid in Demand mode In other modes this register value must be to 0x01 RW Reset Value EP1 DMA UNIT 0x52000204 L R W EP1 DMA transfer unit counter base register 0x00 0x52000207 B byte 2 UNIT 0x5200021C L EP2 DMA transfer unit counter base register 0x00 0x5200021F B byte B UNIT 0x52000244 L R W EP3 DMA transfer unit counter base register 0x00 0 52000247 byte 4 UNIT 0x5200025C L R W EP4 DMA transfer unit counter base register 0x00 0 5200025 byte EPn_UNIT_CNT 7 0 RW R EP DMA transfer unit counter value 13 22 ELECTRONICS 53 2410 USB DEVICE DMA FIFO COUNTER REGISTER EPN_DMA_FIFO This register has values in byte size in FIFO to be transferred by DMA In case of OUT_DMA_RUN enabled the value in OUT FIFO Write Count Register1 will be loaded in this register automatically In case of INDMA mode the MCU should set proper value by software Reset Value EP1
92. ELECTRONICS ARM920T PROCESSOR PROGRAMMER S MODEL The operations which can be carried out upon a single cache line identify the line using the data passed in the MCR instruction The data is interpreted using one of the following formats 31 _____________ fo fo fo fo fo SBZ Figure 2 2 Register 7 MVA Format 26 25 24 23 22 21 20 19 18 17 16 15 1413121110 9 8 7 54321 Po SBZ SBZ Figure 2 3 Register 7 Index Format The use of register 7 is discussed in Chapter 4 Caches Write Buffer and Physical Address TAG PATAG RAM ELECTRONICS 2 17 PROGRAMMER S MODEL ARM920T PROCESSOR REGISTER 8 TLB OPERATIONS Register 8 is a write only register used to manage the translation lookaside buffers TLBs the instruction TLB and the data TLB TLB operations are defined and the function to be performed is selected by the 2 and CRm fields in the MCR instruction used to write CP15 register 8 Writing other opcode_2 or CRm values is unpredictable Reading from CP15 register 8 is unpredictable Table 2 17 on page 2 18 shows instructions that can be used to perform TLB operations using register 8 Table 2 17 TLB Operations Register 8 Invalidate TLB s MCR p15 0 Rd c8 c7 0 Invalidate TLB MCR p15 0 Rd c8 c5 0 SBZ Invalidate D TLB SBZ MCR p15 0 Rd c8 c6 0 Invalidate D TLB single entry using MVA MVA format MCR p15 0 Rd c8 c6 1 NOTE These functions invalidate all the
93. Enable nBE 3 0 Upper Byte Lower Byte Enable In case of 16 bit SRAM nWBE 3 0 Oo Write Byte Enable 1 20 ELECTRONICS 3 2410 PRODUCT OVERVIEW Table 1 3 S3C2410A Signal Descriptions Continued Descriptions NAND Flash Configuration If NAND Flash Controller isn t used it has to be tied on pull up resistor NAND Flash Ready Busy If NAND Flash Controller isn t used it has to be tied on pull up resistor LCD Control Unit VD 23 0 O STN TFT SEC TFT LCD Data Bus LCD PWREN O STN TFT SEC TFT LCD panel power enable control signal STN TFT LCD clock signal VFRAME O STN LCD Frame signal STN LCD line signal oO STN VM alternates the polarity of the row and column voltage oO TFT Vertical synchronous signal o TFT Horizontal synchronous signal TFT Data enable signal TFT Line End signal o SEC TFT SEC Samsung Electronics Company TFT LCD panel control signal SEC TFT SEC Samsung Electronics Company TFT LCD panel control signal LCD_HCLK o SEC TFT SEC Samsung Electronics Company TFT LCD panel control signal T SEC TFT SEC Samsung Electronics Company TFT LCD panel control signal ISIH o SEC TFT SEC Samsung Electronics Company TFT LCD panel control signal LCDVF 2 0 O SEC TFT Timing control signal for specific TFT LCD OE REV REVB Interrupt Control Unit EINT 23 0 EM External Interrupt request 1 0 1 External DMA request
94. GPHDAT AND Pull up disable register for port H Reserved oxse000070 Rese Undefned GPHCON se GPH10 21 20 00 Input 01 Output 10 CLKOUT1 11 Reserved GPH9 19 18 Input 01 Output 10 CLKOUTO 11 Reserved 10 RXD2 11 nCTS1 GPH6 13 12 00 Input 01 Output 10 TXD2 11 nRTS1 GPH5 11 10 00 Input 01 Output 10 RXD1 11 Reserved GPH4 00 Input 01 Output 10 TXD1 11 Reserved GPH3 7 6 00 Input 01 Output 10 RXDO 11 reserved 0 0 0 0 00 Input 01 Output 0 0 0 GPH8 17 16 00 Input 01 Output 10 UEXTCLK 11 Reserved 0 GPH2 5 4 Input 01 Output 10 TXDO 11 Reserved GPH1 3 2 00 Input 01 Output 10 nRTSO 11 Reserved 1 0 00 Input 01 Output 10 nCTSO 11 Reserved S 0 11 GPH 10 0 10 0 When the port is configured as input port data from external sources can be read to the corresponding pin When the port is configured as output port data written in this register can be sent to the corresponding pin When the port is configured as functional pin undefined value will be read GPHUP O GPH 10 0 10 0 0 The pull up function attached to to the corresponding port pin is enabled 1 The pull up function is disabled ELECTRONICS 9 19 PORTS 53 2410 MISCELLANEOUS CONTROL REGISTER MISCCR Pads related USB are controlled by this register for
95. Interface with 16 bit ROM 5 8 5 8 Memory Interface with 16 bit 1 an 5 9 5 9 Memory Interface with 16 bit SRAM x 2 5 9 5 10 Memory Interface with 16 bit SDRAM 8MB 1Mb x 16 x 5 5 10 5 11 Memory Interface with 16 bit SDRAM 16MB 1Mb x 16 x 4banks x 2 5 10 5 12 53 2410 5 Timing Diagram T 5 11 5 13 S3C2410A SDRAM Timing Diagram L 5 12 xxii 3C2410A MICROPROCESSOR List of Figures continued Figure Title Page Number Number 6 1 NAND Flash Controller Block Diagram sse 6 2 6 2 NAND Flash Operation 6 2 6 3 TACLS 0 TWRPHO 1 TWRPH1 0 6 3 6 4 NAND Flash Memory nnns 6 5 7 1 Clock Generator Block Diagram L unu 7 3 7 2 PLL Phase Locked Loop Block 7 5 7 3 Main Oscillator Circuit a 7 5 7 4 Power On Reset Sequence when the external clock source is a crystal oscillator 7 6 7 5 Changing Slow Clock by Setting PMS Value sese 7 7 7 6 Changing CLKDIVN Register Value a 7 8 7 7 The Clock Distribution Block Diagram
96. LCD Interrupt Mask LPC3600 Control NFSTAT 0x4E000010 R Flash Operation Status 0x4E000014 NAND Flash ECC ELECTRONICS 1 29 PRODUCT OVERVIEW 3 2410 Table 1 4 S3C2410A Special Registers Continued Register Address Address Acc Read Function Name B Endian L Endian Unit Write UART ULCONO 0x50000000 lt W RW UART Line Control UCONO 0x50000004 UART 0 Control UFCONO 0x50000008 UART 0 FIFO Control UMCONO 0x5000000C UART 0 Modem Control UTRSTATO 0x50000010 R UART 0 Tx Rx Status UERSTATO 0x50000014 UART 0 Rx Error Status UART 0 FIFO Status UART 0 Modem Status 0x50000023 0x50000020 UART 0 Transmission Hold R UARTOReceive Buter Lemos omes w RW UART o Baue Pare Diso _____ R W UART 1 Line Control UARTiConro UART 1 Modem ae Se Sets o FUART1RxErrorStatus UART 1 FIFO Status UART 1 Modem Status 1 Modem UART 1 Modem Status W _ 1 Transmission Hold UART UART 1 Transmission Hold Transmission Hold UART Receive Buter ULCON2 0x50008000 4 R W UART 2 Line Control UCON2 0x50008004 UART 2 Control 2 UART 2 Control UFCON2 0x50008008 UART 2 FIFO Control 2 UART 2 FIFO Control Control UART 2 Rx Error Status w UART2 Transmission n Receive Bufer UART 2 FIFO Status 2 UART 2 FIFO Status Status 1 30 ELECTRONICS 3 2410 PRODUCT OVERVIEW Table 1 4 S3C241
97. LSL n MVN Ra Ra RSB Ra Ra 0 5 Multiplication by 2 1 3 7 15 LSL Rt Rb n SUB Ra Rb Rb LSL n SUB Ra Rb Rt Multiplication by any C 24n 1 2 n 1 2 n or 2 1 2 n Effectively this is any of the multiplications in 2 to 5 followed by a final shift This allows the following additional constants to be multiplied 6 10 12 14 18 20 24 28 30 34 36 40 48 56 60 62 2 5 2 5 LSL Ra Ra n MOV Ra Ra LSL n 4 40 ELECTRONICS 3C2410A THUMB INSTRUCTION SET GENERAL PURPOSE SIGNED DIVIDE This example shows a general purpose signed divide and remainder routine in both Thumb and ARM code Thumb code signed_divide Signed divide of R1 by returns quotient in RO remainder in R1 Get abs value of RO into R3 ASR R2 RO 31 Get 0 or 1 R2 depending on sign of RO EOR RO R2 EOR with 1 OxFFFFFFFF if negative SUB R3 RO R2 and ADD 1 SUB 1 to get abs value SUB always sets flag so go amp report division by 0 if necessary BEQ divide_by_zero Get abs value of R1 by xoring with OxFFFFFFFF and adding 1 if negative ASR RO R1 31 Get 0 or 1 depending on sign of R1 EOR R1 RO EOR with 1 OxFFFFFFFF if negative SUB R1 RO and ADD 1 SUB 1 to get abs value signs 0 or 1 in RO 8 R2 for later use in determining sign of quotient 4 remainder PUSH RO R2 Justification shift 1 bit at a time until divisor RO value
98. MHz Crystal clock input cycle time 5 10 ns ______ w 7 6 cock ruri wah teow 7 fee HCLK internal to CLKOUT Reset assert time after clock stabilization tresw or EXTCLK et x Power_OFF mode return oscillation setting time losc2 65536 or EXTCLK The interval before CPU runs after nRESET is tRsT2RUN 7 or released EXTCLK ELECTRONICS 24 31 ELECTRICAL DATA 3 2410 Table 24 7 ROM SRAM Bus Timing Constants V Vppiarm 1 8V 0 15 2 0 V 0 1 40 to 85 C VDDMOP 3 3V 0 3V ___________ Symbol Typ Uni we 9 ROM SRAM Chip select Delay lao 2 9 85 n ROM SRAM Output enable Delay top 2 8 75 ns ROM SRAM read Data Setup time s 4 ROM SRAM read Data Hold time 0 m ROM SRAM Byte Enable Delay 2 8 75 n ROM SRAM Write Byte Enable Delay wap 2 10 95 ms ROM SRAM output Data Delay trop 3 _ 12 115 ms ROM SRAM external Wait Setup time ROM SRAM external Wait Hold time ROM SRAM Write enable Delay 9 8 5 Table 24 8 Memory Interface Timing Constants 3 3V Vppi
99. MMU ARM920T PROCESSOR HARDWARE TRANSLATION PROCESS TRANSLATION TABLE BASE The hardware translation process is initiated when the TLB does not contain a translation for the requested modified virtual address The translation table base TTB register points to the base address of a table in physical memory which contains section and or Page descriptors The 14 low order bits of the TTB register are set to zero on a read and the table must reside on a 16KB boundary 31 14 13 0 Figure 3 2 Translation Table Base Register The translation table has up to 4096 x 32 bit entries each describing 1MB of virtual memory This allows up to 4GB of virtual memory to be addressed Figure 3 1 on page 3 5 illustrates the table walk process 3 6 ELECTRONICS ARM920T PROCESSOR MMU LEVEL ONE FETCH Bits 31 14 of the translation table base register are concatenated with bits 31 20 of the modified virtual address to produce a 30 bit address as illustrated in Figure 3 3 on page 3 7 This address selects a 4 byte translation table entry which is a level one descriptor for either a section or a page table Modified virtual address 31 20 19 0 Translation table base 31 14 13 0 Translation base _ oO 12 18 31 14 13 210 Translation base Table index o 0 Level one descriptor 31 0 Figure 3 3 Accessing the Translation Table Level One Descriptors ELECTRONICS 3 7 MMU ARM920T PROCESSOR LEVEL ONE DESCRIPTOR The level one desc
100. MV Value for Each Display Mode Me The LCDBASEU register value is the first address value of the frame buffer The lowest 4 bits must be eliminated for burst 4 word access The LCDBASEL register value depends on LCD size and LCDBASEU The LCDBASEL value is given by the following equation LCDBASEL LCDBASEU LCDBASEL offset ELECTRONICS 15 39 LCD CONTROLLER S3C2410A Example 1 160 x 160 4 level gray 80 frame sec 4 bit single scan display HCLK frequency is 60 MHz WLH 1 WDLY 1 Data transmission rate 160 x 160 x 80 x 1 4 512 kHz CLKVAL 58 VCLK 517 kHz HOZVAL 39 LINEVAL 159 LINEBLANK 10 LCDBASEL LCDBASEU 3200 NOTE The higher the system load is the lower the cpu performance is Example 2 Virtual Screen Register 4 level gray Virtual screen size 1024 x 1024 LCD size 320 x 240 LCDBASEU 0x64 4 bit dual scan 1 halfword 8 pixels 4 level gray Virtual screen 1 line 128 halfword 1024 pixels LCD 1 line 320 pixels 40 halfword OFFSIZE 128 40 88 0x58 PAGEWIDTH 40 0x28 LCDBASEL LCDBASEU PAGEWIDTH OFFSIZE x LINEVAL 1 100 40 88 x 120 0 3064 Known Problem of STN LCD If Enable and Disable Video output ENVID of LCDCON1 Register it is repeated over 100times there could be 1Word data loss in case of STN But the probability of this symptom is very low gt Workaround You should insert the below function in your code right be
101. Module Signal 24 35 24 14 SD MMC Interface Transmit Receive Timing Constants 24 35 24 15 SPI Interface Transmit Receive Timing Constants 24 36 24 16 USB Electrical Specifications esses 24 36 24 17 USB Full Speed Output Buffer Electrical Characteristics 24 37 24 18 USB Low Speed Output Buffer Electrical Characteristics 24 37 24 19 NAND Flash Interface Timing 24 38 xxviii 3C2410A MICROPROCESSOR List of Table Concluded Figure Title Page Number Number 2 1 ARM9TDMI Implementation Option I 2 2 2 2 15 Lu u nier to 2 4 2 3 CPIS una aun 2 5 2 4 Address Types 920 2 6 2 5 Register 0 GOGe uei er ihe deeper 2 7 2 6 Cache Register 2 8 2 7 Gache Size ENCOING ieri 2 9 2 8 Cache associativity encoding ener 2 9 2 9 Line Length Encoding ccecccceseeneeeseeenseeeeeeeeeeeseeneeseseaeeeeeeaaneeeeseceneeseeeeneeeeeeeneees 2 10 2 10 Control Register 1 bit Functions
102. OHCI Rev 1 0 Refer to Open Host Controller Interface Rev 1 0 specification for detail information Table 12 1 OHCI Registers for USB Host Controller 0000 HeCommonStatus 0400008 F 0400000 NE UNE 0400004 e HePerodCureniED ec HeConweeadED 0449000020 HeContlCurentED 0649000024 HeBukHeadeD 0400008 HeBukCurenteD oeoo uec HeDonetiead 0400000 HoFmRemainng 0400008 NECEM HoFmNumber 0490000 rcu HePerodistat 0400000 poem HST EET DN NECEM 0400000 NECEM HoRhPonsiatust 0649000054 5 HeRhPorstatus2 6490008 Lo 12 2 ELECTRONICS 53 2410 USB DEVICE USB DEVICE CONTROLLERS OVERVIEW Universal Serial Bus USB device controller is designed to provide a high performance full function controller solution with DMA interface USB device controller allows bulk transfer with DMA interrupt transfer and control transfer USB device controller supports Full soeed USB device controller compatible with the USB specification version 1 1 DMA interface for bulk transfer Five endpoints with FIFO EPO 16byte Register EP1 64byte IN OUT FIFO dual port asynchronous RAM inte
103. Opcodes Continued m e exer Operand Operand Codes Set NEG Neate Y __ RoR SBC a Poo oes p EE RENE lt lt lt eal swi NOTES 1 The condition codes are unaffected by the format 5 12 and 13 versions of this instruction 2 The condition codes are unaffected by the format 5 version of this instruction 4 4 ELECTRONICS 3C2410A THUMB INSTRUCTION SET FORMAT 1 MOVE SHIFTED REGISTER 10 6 5 3 2 0 14 ome 2 0 Destination Register 5 3 Source Register 10 6 Immediate Vale 12 11 Opcode 0 LSL 1 LSR 2 ASR Figure 4 2 Format 1 OPERATION These instructions move a shifted value between Lo registers The THUMB assembler syntax is shown in Table 4 2 NOTE All instructions in this group set the CPSR condition codes Table 4 2 Summary of Format 1 Instructions THUMB Assembler ARM Equipment LSL Rd Rs Offset5 MOVS Rs LSL Offset5 Rs left by a 5 bit immediate value and store the result in Rd LSR Rd Rs Offset5 MOVS Rd Rs LSR Offset5 Perform logical shift right on Rs by a 5 bit immediate value and store the result in Rd ASR Rd Rs Offset5 MOVS Rd Rs ASR Offset5 Perform arithmetic shift right on Rs by a 5 bit immediate value and store the result in Rd ELECTRONICS 4 5 THUMB INSTRUCTION SET S
104. Operation codes 0000 AND Rd Op1 AND Op2 0001 EOR Rd Op1 EOR Op2 0010 SUB Rd Op1 Op2 0011 RSB Rd Op2 Op1 0100 ADD Rd 1 2 0101 1 2 0110 SBC Rd OP1 Op2 C 1 0111 RSC Rd 2 1 1 1000 TST set condition codes on Op1 AND Op2 1001 TEO set condition codes on OP1 EOR Op2 1010 CMP set condition codes on Op1 Op2 1011 SMN set condition codes on Op1 Op2 1100 ORR Rd Op1 OR Op2 1101 MOV Rd Op2 1110 BIC Rd Op1 AND NOT Op2 1111 MVN Rd NOT Op2 25 Immediate operand 0 Operand 2 is a register 1 Operand 2 is an immediate value 11 0 Operand 2 type selection 11 3 4 0 3 0 2nd operand register 11 4 Shift applied to Rm 11 8 7 7 0 Unsigned 8 bit immediate value 11 8 Shift applied to Imm 31 28 Condition field Figure 3 4 Data Processing Instructions ELECTRONICS 3 9 ARM INSTRUCTION SET 53 2410 The instruction produces a result by performing a specified arithmetic or logical operation one or two operands The first operand is always a register Rn The second operand may be a shifted register Rm or a rotated 8 bit immediate value Imm according to the value of the I bit in the instruction The condition codes in the be preserved or updated as a result of this instruction according to the value of the S bit in the instruction Certain operations TST TEQ CMP CMN do not write the resul
105. R14 svc upon entering the software interrupt trap with the PC adjusted to point to the word after the SWI instruction MOVS PC R14 svc will return to the calling program and restore the Note that the link mechanism is not re entrant so if the supervisor code wishes to use software interrupts within itself it must first save a copy of the return address and SPSR COMMENT FIELD The bottom 24 bits of the instruction are ignored by the processor and may be used to communicate information to the supervisor code For instance the supervisor may look at this field and use it to index into an array of entry points for routines which perform the various supervisor functions INSTRUCTION CYCLE TIMES Software interrupt instructions take 2S 1N incremental cycles to execute where S and N are defined as sequential S cycle and non sequential N cycle ELECTRONICS 3 49 ARM INSTRUCTION SET 53 2410 ASSEMBLER SYNTAX SWI cond lt expression gt Two character condition mnemonic Table 3 2 lt expression gt Evaluated and placed in the comment field which is ignored by ARM920T Examples SWI ReadC Get next character from read stream SWI Writel k Output a k to the write stream SWINE 0 Conditionally call supervisor with 0 in comment field Supervisor code The previous examples assume that suitable supervisor code exists for instance 0x08 B Supervisor SWI entry point EntryTable Addresses of
106. R15 in Transfer List and S Bit Set User Bank Transfer The registers transferred are taken from the User bank rather than the bank corresponding to the current mode This is useful for saving the user state on process switches Base write back should not be used when this mechanism is employed R15 not in List and S Bit Set User Bank Transfer For both LDM and STM instructions the User bank registers are transferred rather than the register bank corresponding to the current mode This is useful for saving the user state on process switches Base write back should not be used when this mechanism is employed When the instruction is LDM care must be taken not to read from a banked register during the following cycle inserting a dummy instruction such as MOV RO RO after the LDM will ensure safety USE OF R15 AS THE BASE R15 should not be used as the base register in any LDM or STM instruction ELECTRONICS 3 43 ARM INSTRUCTION SET S3C2410A INCLUSION OF THE BASE IN THE REGISTER LIST When write back is specified the base is written back at the end of the second cycle of the instruction During a STM the first register is written out at the start of the second cycle A STM which includes storing the base with the base as the first register to be stored will therefore store the unchanged value whereas with the base second or later in the transfer order will store the modified value A LDM will always overwrite the updated base if th
107. R3 R4 R1 R2 R3 UMLALS R1 R5 R2 R3 R5 R1 R2 R3 R5 R1 also setting condition codes ELECTRONICS 3 27 ARM INSTRUCTION SET 53 2410 SINGLE DATA TRANSFER LDR STR The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 14 The single data transfer instructions are used to load or store single bytes or words of data The memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register The result of this calculation may be written back into the base register if auto indexing is required 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0 PPF Lo 15 12 Source Destination Registers 19 16 Base Register 20 Load Store Bit 0 Store to memory 1 Load from memory 21 Write back Bit 0 No write back 1 Write address into base 22 Byte Word Bit 0 Transfer word quantity 1 Transfer byte quantity 23 Up Down Bit 0 Down subtract offset from base 1 Up add offset to base 24 Pre Post Indexing Bit 0 Post add offset after transfer 1 Pre add offset before transfer 25 Immediate Offset 0 Offset is an immediate value 11 0 Offset 11 0 11 0 Unsigned 12 bit immediate offset 11 4 3 0 3 0 Offset register 11 4 Shift applied to Rm 31 28 Condition Field Figure 3 14 Single Data Transfer Instructions 3 28 ELECTRONICS
108. REGISTER PRIORITY PRIORITY 0x4A00000C IRQ priority control register ARB_SEL6 20 19 Arbiter 6 group priority order set 00 REQ 0 1 2 3 4 5 01 REQ 0 2 3 4 1 5 10 REQ 0 3 4 1 2 5 11 REQ 0 4 1 2 3 5 ARB_SEL5 18 17 Arbiter 5 group priority order set 00 REQ 1 2 3 4 01 REQ 2 3 4 1 10 REQ 3 4 1 2 11 REQ 4 1 2 3 ARB_SEL4 16 15 Arbiter 4 group priority order set 00 REQ 0 1 2 3 4 5 01 REQ 0 2 3 4 1 5 10 REQ 0 3 4 1 2 5 11 REQ 0 4 1 2 3 5 ARB_SEL3 14 13 Arbiter 3 group priority order set 00 REQ 0 1 2 3 4 5 01 REQ 0 2 3 4 1 5 10 REQ 0 3 4 1 2 5 11 REQ 0 4 1 2 3 5 ARB_SEL2 12 11 Arbiter 2 group priority order set 00 REQ 0 1 2 3 4 5 01 REQ 0 2 3 4 1 5 10 REQ 0 3 4 1 2 5 11 REQ 0 4 1 2 3 5 ARB_SEL1 10 9 Arbiter 1 group priority order set 00 REQ 0 1 2 3 4 5 01 REQ 0 2 3 4 1 5 10 REQ 0 3 4 1 2 5 11 REQ 0 4 1 2 3 5 ARB_SELO 8 7 Arbiter 0 group priority order set 00 REQ 1 2 3 4 01 REQ 2 3 4 1 10 REQ 3 4 1 2 11 REQ 4 1 2 3 Arbiter 6 group priority rotate enable 0 Priority does not rotate 1 Priority rotate enable Arbiter 5 group priority rotate enable ARB_MODE6 ARB_MODE5 5 0 Priority does not rotate 1 Priority rotate enable ARB_MODE4 4 Arbiter 4 group priority rotate enable 0 Priority does not rotate 1 Priority rotate enable ARB_MODE3 3 Arbiter 3 group priority rotate enable 0 Priority does not rotate 1 Priority rotate enable AR
109. Section Page 001000 valid MVA of access access or NCB read 061010 valid causing abort NOTES 1 Data FSR only Alignment faults may write either 000001 060011 into FS 3 0 Invalid values in domain 3 0 occur because the fault is raised before a valid domain field has been read from a page table descriptor Any abort masked by the priority encoding may be regenerated by fixing the primary abort and restarting the instruction NCNB means Non Cacheable and Non Bufferable NCB means Non Cacheable but Bufferable 2 Instruction FSR only The same priority applies as for the Data fault status register except that alignment faults cannot occur and external aborts apply only to NC Non cacheable reads 3 18 ELECTRONICS ARM920T PROCESSOR MMU DOMAIN ACCESS CONTROL MMU accesses are primarily controlled via domains There are 16 domains and each has a 2 bit field to define access to it Two types of user are supported clients and managers See Table 3 5 The domains are defined in the domain access control register Figure 3 10 illustrates how the 32 bits of the register are allocated to define the 16 2 bit domains 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 161514131211109 8 7 6 5 4 32 1 0 ps 14 2 7 5 Figure 3 10 Domain Access Control Register Format Table 3 5 defines how the bits within each domain are interpreted to specify the access permissions Table 3 5 In
110. States in Power OFF Mode The pin state of the Power OFF mode is as follows Pin Type Pin Example Pin States in Power OFF Mode GPIO output pin GPBO output Output GPIO data register value is used nGCS0 Output the last output level is held pin nwa ELECTRONICS 7 15 CLOCK amp POWER MANAGEMENT 53 2410 Power Control of VDDi VDDiarm In Power_OFF mode only VDDi and VDDiarm will be turned off which is controlled by PWREN pin If PWREN signal is active H VDDi and VDDiarm are supplied by an external voltage regulator If PWREN is inactive L the VDDi and VDDiarm are turned off NOTE Although VDDi VDDiarm VDDi_MPLL and VDDi_UPLL may be turned off the other power pins have to be supplied 1 8V 2 0V Regulator 1 8V 2 0V 1 8V 2 0V Rover 83 2410 lt g RTC Alarm Power CTRL Alive Block VDDi Alive Block VDDiarm VDDi MPLL VDDi UPLL External Interrupt Core amp Peripherals 3 3V Power Figure 7 12 Power OFF Mode 7 16 ELECTRONICS 53 2410 CLOCK 8 POWER MANAGEMENT Signaling EINT 15 0 for Wakeup The 3 2410 can be woken up from Power_OFF mode only if the following conditions are met a Level signals H or L or edge signals rising or falling or both are asserted on EINTn input pin b The EINTn pin has to be configured as EINT in the GPIO control register c nBATT_FLT pin has to be H level It is important to configure th
111. Timing Trp 2 2 Tcl 2 24 18 24 21 SDRAM MRS TAMING s n csc asia e eta eter tere a Fa ee qasaqa apas 24 19 24 22 SDRAM Single READ Timing l Trp 2 Trcd 2 Tcl 2 24 20 24 23 SDRAM Single READ Timing ll Trp 2 2 Tcl 3 24 21 24 24 SDRAM Auto Refresh Timing Trp 2 4 24 22 24 25 SDRAM Page Hit Miss READ Timing Trp 2 Trcd 2 Tcl 2 24 23 24 26 SDRAM Self Refresh Timing Trp 2 24 24 24 27 SDRAM Single Write Timing Trp 2 Troed 2 24 25 24 28 SDRAM Page Hit Miss Write Timing Trp 2 2 Tcl 2 24 26 24 29 External DMA Timing Handshake Single transfer 24 27 24 30 TFT LCD Controller 24 27 24 31 IS Interface Timmilig tio rex dene acest ote 24 28 24 32 Interface 24 28 24 33 SD MMC Interface 24 29 24 34 SPI Interface Timing 1 CPOL 1 24 29 24 35 NAND Flash Address Command 24 30 24 36 NAND ElasFi 24 30 25
112. Tx Data Register 7 0 This field contains the data to be transmitted over the SPI channel SPI Rx Data Register SPRDATO 0x59000014 R SPI channel 0 Rx data register 0x00 SPRDAT 1 0x59000034 R SPI channel 1 Rx data register 0x00 Rx Data Register 7 0 This field contains the data to be received over the SPI channel 22 10 ELECTRONICS 53 2410 BUS PRIORITIES BUS PRIORITIES OVERVIEW The bus arbitration logic determines the priorities of bus masters It supports a combination of rotation priority mode and fixed priority mode BUS PRIORITY MAP The S3C2410A holds eleven bus masters including SDRAM refresh controller LCD_DMA DMA1 DMA2 DMA3 USB_HOST_DMA EXT_BUS_MASTER Test interface controller TIC and ARM920T The following list shows the priorities among these bus masters after a reset SDRAM refresh controller LCD_DMA DMAO 2 DMA3 USB host DMA External bus master TIC 0 ARM920T Reserved PN Among those bus masters four DMAs operate under the rotation priority while others run under the fixed priority ELECTRONICS 23 1 BUS PRIORITIES 53 2410 23 2 ELECTRONICS 53 2410 ELECTRICAL DATA 2 ELECTRICAL DATA ABSOLUTE MAXIMUM RATINGS Table 24 1 Absolute Maximum Rating DC Supply Voltage 1 8 2 0V DC Input Voltage 3 3V Input buffer RECOMMENDED OPERATING CONDITIONS Table
113. USB host or for USB device Reset Value MISCCR 0x56000080 Miscellaneous control register 0x10330 MISCCR Reserved 21 20 Reserved to 00b nEN_SCKE 19 0 Normal 1 L level Used to protect SDRAM during the Power_OFF moe nEN_SCLK1 18 0 SCLK1 SCLK 1 SCLK1 L level Used to protect SDRAM during the Power_OFF moe nEN_SCLKO 17 0 SCLKO SCLK 1 SCLKO L level Used to protect SDRAM during the Power_OFF moe nRSTCON 16 nRSTOUT software control SW_RESET 0 nRSTOUT 0 1 nRSTOUT 1 Reserved 15 14 Reserved to 00b USBSUSPND1 13 13 USB Port 1 mode 0 Normal 1 Suspend USBSUSPNDO 12 12 USB Port 0 mode 0 Normal 1 Suspend 11 Reserved to Ob CLKSEL1 10 8 CLKOUT1 output singnal source 000 MPLL 001 UPLLCLK 010 FCLK 011 100 PCLK 101 DCLK1 11x Reserved Reeves n ooo CLKSELO 6 4 CLKOUTO output singnal source 000 MPLL CLK 001 UPLLCLK 010 FCLK 011 100 PCLK 101 DCLKO 11x Reserved USBPAD 3 0 Use pads related USB for USB device 1 Use pads related USB for USB host SPUCR_L 1 DATA 15 0 port pull up resister 0 Enabled 1 Disabled SPUCR_H DATA 31 16 port pull up resister 0 Enabled 1 Disabled NOTE CLKOUT is prepared only for monitoring an internal clock situation On Off status or frequency Description 9 20 ELECTRONICS 53 2410 PORTS DCLK CONTROL REGISTERS DCLKCON This register defines DCLKn signals whi
114. VD6 VD5 VD4 VD7 VD6 VD5 VD4 R1 G1 B1 R2 G2 B2 R3 G3 4 bit Dual Scan Display VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 R1 G1 B1 R2 G2 B2 R3 G3 1 Pixel 4 bit Single Scan Display VD7 VD6 VD5 VD4 VD3 VD2 VD1 VDO R1 G1 B1 R2 G2 B2 R3 G3 1 Pixel 8 bit Single Scan Display Figure 15 3 Color Display Types STN 15 12 ELECTRONICS 3C2410A LCD CONTROLLER Timing Requirements Image data should be transferred from the memory to the LCD driver using the VD 7 0 signal VCLK signal is used to clock the data into the LCD driver s shift register After each horizontal line of data has been shifted into the LCD driver s shift register the VLINE signal is asserted to display the line on the panel The VM signal provides an AC signal for the display The LCD uses the signal to alternate the polarity of the row and column voltages which are used to turn the pixels on and off because the LCD plasma tends to deteriorate whenever subjected to a DC voltage It can be configured to toggle on every frame or to toggle every programmable number of VLINE signals Figure 15 4 shows the timing requirements for the LCD driver interface ELECTRONICS 15 13 LCD CONTROLLER S3C2410A Full Frame Timing MMODE 0 INT_FrSyn VM VLINE LINE1 INES I Full Frame Timing MMODE 1 MVAL 0x2 I INT_FrSyn GEN 1 VM VLINE LIN
115. as NCNB or NCB The only way this can occur is if the operating system changes the value of the C and B bits in a page table descriptor while the cache contains data from the area of virtual memory controlled by that descriptor The cache and memory system behavior resulting from changing the page table descriptor in this way is unpredictable If the operating system needs to change C and B bits of a page table descriptor it must ensure that the caches do not contain any data controlled by that descriptor In some circumstances the operating system may need to clean and flush the caches to ensure this ELECTRONICS 4 7 CACHES WRITE BUFFER ARM920T PROCESSOR A linefill performs an 8 word burst read from the ASB and places it as a new entry in the cache possible replacing another line at the same location within the cache The location which is replaced called the victim is chosen from the entries which are not locked using either a random or round robin replacement policy If the cache line being replaced is marked as dirty indicating that it has been modified and that main memory has not been updated to reflect the change a cache writeback occurs Depending on whether one or both halves of the cache line are dirty the writeback will perform a 4 or 8 word sequential burst write access on the ASB The writeback data is placed in the write buffer and then the linefill data is read from the ASB The CPU can the continue while the writeback dat
116. bit Single Scan Display STN LCD Timing 15 14 15 5 16BPP Display Types enne enne 15 21 15 6 TFT EGD Timing Example en it tree deret zi erem 15 22 15 7 Example of Scrolling in Virtual Display Single Scan 15 24 15 8 Example of PWREN Function PWREN 1 INVPWREN 0 15 25 16 1 ADC and Touch Screen Interface Block 16 2 16 2 Example of ADC and Touch Screen sse 16 3 16 3 Timing Diagram in Auto Sequential X Y Position Conversion 16 6 17 1 Real Time Clock Block Diagram as 17 2 17 2 Main Oscillator Circuit Example L n u 17 4 18 1 Watchdog Timer Block 18 2 19 1 deed ec ipa c cte tco rta 19 2 20 1 Di gra Mi aun a pu nnn tnnt ns 20 2 20 2 Start and Stop Condition esses entente 20 3 20 3 IIC Bus Interface Data 20 4 20 4 Data Transfer on the 20 5 20 5 Acknowledge on the
117. bit immediate value This value is zero extended to 32 bits and then subject to a rotate right by twice the value in the rotate field This enables many common constants to be generated for example all powers of 2 WRITING TO R15 When Rd is a register other than R15 the condition code flags in the CPSR may be updated from the ALU flags as described above When Rd is R15 and the S flag in the instruction is not set the result of the operation is placed in R15 and the CPSR is unaffected When is R15 and the S is set the result of the operation is placed in R15 and the SPSR corresponding to the current mode is moved to the CPSR This allows state changes which atomically restore both PC and CPSR This form of instruction should not be used in User mode USING R15 AS AN OPERANDY If R15 the PC is used as an operand in a data processing instruction the register is used directly The PC value will be the address of the instruction plus 8 or 12 bytes due to instruction prefetching If the shift amount is specified in the instruction the PC will be 8 bytes ahead If a register is used to specify the shift amount the PC will be 12 bytes ahead TEQ TST CMP AND CMN OPCODES NOTE TEQ TST CMP and CMN do not write the result of their operation but do set flags in the CPSR An assembler should always set the S flag for these instructions even if this is not specified in the mnemonic The TEQP form of the TEQ instruction used in e
118. can transmit 8 bit data to CPU as Binary Coded Decimal BCD values using the STRB LDRB ARM operation The data include the time by second minute hour date day month and year The RTC unit works with an external 32 768 kHz crystal and also can perform the alarm function FEATURES BCD number second minute hour date day month and year Leap year generator Alarm function alarms interrupt or wake up from power off mode Year 2000 problem is removed Independent power pin RTCVDD Supports millisecond tick time interrupt for RTOS kernel time tick Round reset function ELECTRONICS 17 1 REAL TIME CLOCK RTC 83 2410 REAL TIME CLOCK OPERATION TICNT TIME TICK Time Tick Generator 128 Hz RTCRST 215 Clock Divider Reset Register Leap Year Generator XTOrtc T n STE EXC Control con Rear Alarm Generator i PMWKUP ALMINT Figure 17 1 Real Time Clock Block Diagram LEAP YEAR GENERATOR The leap year generator can determine the last date of each month out of 28 29 30 or 31 based on data from BCDDATE BCDMON and BCDYEAR This block considers leap year in deciding on the last date An 8 bit counter can only represent 2 BCD digits so it cannot decide whether 00 year the year with its last two digits zeros is a leap year or not For example it cannot discriminate between 1900 and 2000 To solve this problem the RTC block in S3C2410A has hard wired logic to support the leap yea
119. code on an SDRAM S3C2410A boot code can be executed on an external NAND flash memory In order to support NAND flash boot loader the 53 2410 is equipped with an internal SRAM buffer called Steppingstone When booting the first 4 KBytes of the NAND flash memory will be loaded into Steppingstone and the boot code loaded into Steppingstone will be executed Generally the boot code will copy NAND flash content to SDRAM Using hardware ECC generating the NAND flash data validity will be checked Upon the completion of the copy the main program will be executed on the SDRAM FEATURES e NAND Flash mode Support read erase program NAND flash memory Auto boot mode The boot code is transferred into Steppingstone after reset After the transfer the boot code will be executed on the Steppingstone e Hardware ECC generating block for hardware generating and software correcting e The Steppingstone 4 KB internal SRAM buffer can be used for another purpose after NAND flash booting ELECTRONICS 6 1 NAND FLASH CONTROLLER S3C2410A BLOCK DIAGRAM System Bus Internal Buffer Buffer Control Control State Machine Register Bank CLE ALE Ecc nCE Encoder Ris Decoder R nB I O0 l O7 Figure 6 1 NAND Flash Controller Block Diagram OPERATION SCHEME Auto Boot Mode CPU Access Boot Code Steppingstone 4 KB Buffer NAND Flash Controller User Access Special Function Registers NAND
120. data phase the MCU sets DATA END at the same time OUT PKT RDY SET Set by the USB once a valid token is written to the FIFO An interrupt is generated when the USB sets this bit The MCU clears this bit by writing a 1 to the SERVICED OUT PKT RDY bit ELECTRONICS 13 13 USB DEVICE 53 2410 END POINT IN CONTROL STATUS REGISTER IN_CSR1_REG IN_CSR2_REG CSR1_REG 0x52000184 L R W IN END POINT control status register1 0x00 0x52000187 B byte 7 CLR DATA Used in Set up procedure TOGGLE 0 There are alternation of DATAO and DATA1 1 The data toggle bit is cleared and PID in packet will maintain DATAO SENT STALL Set by the USB when an IN token issues a STALL handshake after the MCU sets SEND STALL bit to start STALL handshaking When the USB issues a STALL handshake IN PKT RDY is cleared FIFO FLUSH 3 R W CLEAR Set by the MCU if it intends to flush the packet in Input related FIFO This bit is cleared by the USB when the FIFO is flushed The MCU is interrupted when this happens If a token is in process the USB waits until the transmission is complete before FIFO flushing If two packets are loaded into the FIFO only first packet The packet is intended to be sent to the host is flushed and the corresponding IN PKT RDY bit is cleared en SSS SEND STALL 4 W R 0 The MCU clears this bit to finish the STALL condition 1 The MCU issues a STALL handshake to the USB
121. difference between the address of the last half word displayed on the previous LCD line and the address of the first half word to be displayed in the new LCD line PAGEWIDTH 10 0 Virtual screen page width the number of half words 000000000 This value defines the width of the view port in the frame NOTE The values of PAGEWIDTH and OFFSIZE must be changed when ENVID bit is 0 Example 1 LCD panel 320 240 16gray single scan Frame start address 0x0c500000 Offset dot number 2048 dots 512 half words LINEVAL 240 1 Oxef PAGEWIDTH 320 4 16 0x50 OFFSIZE 512 0x200 LCDBANK 0x0c500000 gt gt 22 0x31 LCDBASEU 0x100000 gt gt 1 0x80000 LCDBASEL 0 80000 0x50 0x200 Oxef 1 Oxa2b00 Example 2 LCD panel 320 240 16gray dual scan Frame start address 0x0c500000 Offset dot number 2048 dots 512 half words LINEVAL 120 1 0x77 PAGEWIDTH 320 4 16 0x50 OFFSIZE 512 0x200 LCDBANK 0x0c500000 gt gt 22 0x31 LCDBASEU 0x100000 gt gt 1 0x80000 LCDBASEL 0 80000 0x50 0x200 0x77 1 0x91580 Example 3 LCD panel 320 240 color single scan Frame start address 0x0c500000 Offset dot number 1024 dots 512 half words LINEVAL 240 1 Oxef PAGEWIDTH 320 8 16 0xa0 OFFSIZE 512 0x200 LCDBANK 0x0c500000 gt gt 22 0x31 LCDBASEU 0x100000 gt gt 1 0x80000 LCDBASEL 0 80000 0xa0 0x200 Oxef 1
122. downloading code the EmbeddedICE JTAG debug features updating an exception vector entry another bus master such as a DMA controller modifying a cacheable area main memory turning the MMU on or off e changing the virtual to physical mappings in the MMU page tables e turning the ICache or DCache on if its contents are no longer coherent The DCache should be cleaned and both caches invalidated before the cache and write buffer configuration of an area of memory is changed by modifying Ctt or Btt in the MMU translation table descriptor This is not necessary if it is known that the caches cannot contain any entries from the area of memory whose translation table descriptor is being modified Changing the process ID in CP15 register 13 does not change the contents of the cache or memory and does not affect the mapping between cache entries and physical memory locations It only changes the mapping between ARM9TDMI addresses and cache entries This means that changing the process ID does not lead to any coherency issues No cache cleaning or cache invalidation is required when the process ID is changed At reset the DCache and ICache entries are all invalidated and the DCache and are disabled The software design also needs to consider that the pipelined design of the ARM9TDMI core means that it fetches three instructions ahead of the current execution point So for example the three instructions following an MCR which
123. enable Ed 8 Determine data bus width for bank 2 EM 8 bit 01 16 bit 10 32 bit 11 reserved Determine SRAM for using UB LB for bank 1 0 Not using UB LB The pins are dedicated nWBE 3 0 1 Using UB LB The pins are dedicated nBE 3 0 WAIT status for bank 1 EA WAIT disable 1 WAIT enable 5 4 Determine data bus width for bank 1 00 8 bit 01 16 bit 10 32 bit 11 reserved DWO 2 1 Indicate data bus width for bank 0 read only 01 16 bit 10 32 bit The states are selected by OM 1 0 pins NOTES 1 types of master clock in this memory controller correspond to the bus clock For example HCLK in SRAM is the same as the bus clock and SCLK in SDRAM is also the same as the bus clock In this chapter Memory Controller one clock means one bus clock 2 nBE 3 0 is the AND signal nWBE 3 0 and nOE 5 14 ELECTRONICS 53 2410 MEMORY CONTROLLER BANK CONTROL REGISTER BANKCONN nGCS0 nGCS5 Tacs 14 13 Address set up time before nGCSn 00 0 clock 01 1 clock 10 2 clocks 11 4 clocks Tcos 12 11 Chip selection set up time before nOE 00 0 clock 01 1 clock 10 2 clocks 11 4 clocks Tcoh 7 6 Chip selection hold time after nOE 00 0 clock 01 1 clock 10 2 clocks 11 4 clocks Tcah 5 4 Address hold time after nGCSn 00 0 clock 01 1 clock 10 2 clocks 11 4 clocks Tacp 3 2 Page mode access cycle Page mode 00 2 clocks 01 2 3 clocks 10 4 clocks 11
124. for data transmission If the receiver gets more bits than its word length the bits after the LSB are ignored On the other hand if the receiver gets fewer bits than its word length the missing bits are set to zero internally And therefore the MSB has a fixed position whereas the position of the LSB depends on the word length The transmitter sends the MSB of the next word at one clock period whenever the IISLRCK is changed Serial data sent by the transmitter may be synchronized with either the trailing HIGH to LOW or the leading LOW to HIGH edge of the clock signal However the serial data must be latched into the receiver on the leading edge of the serial clock signal and so there are some restrictions when transmitting data that is synchronized with the leading edge The LR channel select line indicates the channel being transmitted IISLRCK may be changed either on a trailing or leading edge of the serial clock but it does not need to be symmetrical In the slave this signal is latched on the leading edge of the clock signal The IISLRCK line changes one clock period before the MSB is transmitted This allows the slave transmitter to derive synchronous timing of the serial data that will be set up for transmission Furthermore it enables the receiver to store the previous word and clear the input for the next word MSB LEFT JUSTIFIED MSB left justified bus format is the same as IIS bus format architecturally Only different from t
125. has been read The frame error indicates that the received data does not have a valid stop bit Receive time out condition occurs when it does not receive any data during the 3 word time this interval follows the setting of Word Length bit and the Rx FIFO is not empty in the FIFO mode ELECTRONICS 11 3 UART 53 2410 Auto Flow Control AFC The S3C2410A s UART 0 and UART 1 support auto flow control with nRTS and nCTS signals In case it can be connected to external UARTs If users want to connect a UART to a Modem disable auto flow control bit in UMCONn register and control the signal of nRTS by software In AFC nRTS depends on the condition of the receiver and nCTS signals control the operation of the transmitter The UART s transmitter transfers the data in FIFO only when nCTS signals are activated in AFC nCTS means that other UART s FIFO is ready to receive data Before the UART receives data nRTS has to be activated when its receive FIFO has a spare more than 2 byte and has to be inactivated when its receive FIFO has a spare under 1 byte in AFC nRTS means that its own receive FIFO is ready to receive data Transmission case in Reception case in UART A UART A Figure 11 2 UART AFC Interface NOTE UART 2 does not support AFC function because the S8C2410A has no nRTS2 and nCTS2 Example of Non Auto Flow control controlling nRTS and nCTS by software Rx operation with FIFO 1 Select receive mode Interrupt or D
126. if the baud rate is 115200 bps and PCLK or UEXTCLK is 40 MHz UBRDIVn is UBRDIVn int 40000000 115200 x 16 1 in in n 7 1 21 1 20 ww ww Baud rate ww UBRDIV 15 0 Baud rate division value UBRDIVn gt 0 11 20 ELECTRONICS 53 2410 USB HOST CONTROLLER USB HOST CONTROLLERS OVERVIEW 3C2410A supports 2 USB host interface as follows e Rev 1 0 compatible e USB Rev1 1 compatible e Two down stream ports e Support for both LowSpeed and FullSpeed USB devices gt OHCI ROOT HUB REGS N HCI RCFO_RegData 32 SLAVE APP_SDATA 32 92 BLOCK CONTROL USB CONTROL STATE HGI_DATA 32 CONTROL DEn CONTROL REGS CONTROL EM ME __ LIST TxDmns gt ED TD DATA 32 ED TD STATUS 32 ED amp TD RcvData APP MDATA 32 REGS Ws eg HCM_ADR MASTER RevDpls 5 STATUS CONTROL RcvDmns HC DATA RH DATA 8 DF DATA DF DATA 8 Addr 6 DATA 8 FIFO_DATA 8 EXT FIFO STATUS Figure 12 1 USB Host Controller Block Diagram ELECTRONICS 12 1 USB HOST CONTROLLER 3C2410A USB HOST CONTROLLER SPECIAL REGISTERS The S3C2410A USB host controller complies with
127. in Figure 3 12 The multiply and multiply accumulate instructions use an 8 bit Booth s algorithm to perform integer multiplication 31 28 27 22 21 20 19 16 15 12 11 ow ooo offs ow po Do roo 15 12 11 8 3 0 Operand Registers 19 16 Destination Register 20 Set Condition Code 0 Do not after condition codes 1 Set condition codes 21 Accumulate 0 Multiply only 1 Multiply and accumulate 31 28 Condition Field Figure 3 12 Multiply Instructions The multiply form of the instruction gives Rd Rm Rs is ignored and should be set to zero for compatibility with possible future upgrades to the instruction set The multiply accumulate form gives Rd Rm Rs Rn which can save an explicit ADD instruction in some circumstances Both forms of the instruction work on operands which may be considered as signed 2 s complement or unsigned integers The results of a signed multiply and of an unsigned multiply of 32 bit operands differ only in the upper 32 bits the low 32 bits of the signed and unsigned results are identical As these instructions only produce the low 32 bits of a multiply they can be used for both signed and unsigned multiplies For example consider the multiplication of the operands Operand A Operand B Result OxFFFFFFF6 0 0000001 OxFFFFFF38 3 22 ELECTRONICS 53 2410 ARM INSTRUCTION SET If the Operands Are Interpreted as Signed Operand A has the value 10 operand B has the val
128. in Rb Isb uses Rc TST Rb Rb LSR 1 Top bit into carry MOVS Rc Ra RRX 33 bit rotate right ADC Rb Rb Rb Carry into 166 of Rb EOR Re Re Ra LSL 12 involved EOR Ra Rc Rc LSR 20 similarly involved new seed in Ra Rb as before MULTIPLICATION BY CONSTANT USING THE BARREL SHIFTER Multiplication by 2 1 2 4 8 16 32 MOV Ra Rb LSL n Multiplication by 2 1 3 5 9 17 ADD Ra Ra Ra LSL n Multiplication by 24n 1 3 7 15 RSB Ra Ra Ra LSL n ELECTRONICS 3 61 ARM INSTRUCTION SET Multiplication by 6 ADD Ra Ra Ra LSL 1 MOV Ra Ra LSL 1 Multiply by 10 and add in extra number ADD Ra Ra Ra LSL 2 ADD Ra Re Ra LSL 1 General recursive method for Rb Ra C C a constant 1 If C even say 2 n D D D 1 MOV Rb Ra LSL sin 0 lt gt 1 Rb Ra D MOV Rb Rb LSL n 2 If C MOD 4 1 say C 24n D 1 D odd n gt 1 D 1 ADD Rb Ra Ra LSL sin 0 lt gt 1 Rb Ra D ADD Rb Ra Rb LSL n 3 If C MOD 4 3 say 2 n D 1 D odd n gt 1 D 1 RSB Rb Ra Ra LSL 0 lt gt 1 Rb Ra D RSB Rb Ra Rb LSL n S3C2410A Multiply by 3 and then by 2 Multiply by 5 Multiply by 2 and add in next digit This is not quite optimal but close An example of its non optimality is multiply by 45 which is done by RSB Rb Ra Ra LSL 2 RSB Rb Ra Rb LSL 2 ADD Rb Ra Rb LSL 2 rather than by ADD Rb Ra Ra LSL 3 ADD Rb Rb Rb LSL 2 3 62 Multiply by 3 Multiply by 4 3 1 11 M
129. in physical memory The MMU provides the logic needed to traverse this translation table and load entries into the TLB There are up to two stages to the hardware table walking and hence permission checking process The number of stages depends on whether the address in question has been marked as a section mapped access or a page mapped access There is one size of section and three sizes of page mapped access large pages small pages and tiny pages The translation process always starts out in the same way with a level one fetch A section mapped access requires only a level one fetch but a page mapped access requires a subsequent level two fetch 3 4 ELECTRONICS ARM920T PROCESSOR Indexed by modified virtual address bits 31 20 ELECTRONICS Translation table 4096 entries Level one fetch Section base Indexed by modified virtual address bits 19 0 Coarse page table base Indexed by modified virtual address bits 19 12 Tiny page table base Indexed by modified virtual address bits 19 10 Figure 3 1 Translating Page Tables Section 1MB Coarse page table 256 entries Fine page table 1024 entries MMU Level two fetch Large page base Large page Indexed by modified virtual address bits 15 0 Small page base Small page Indexed by modified virtual address bits 11 0 Tiny page base Tiny page Indexed by modified virtual address bits 9 0 3 5
130. includes an instruction cache data cache a write buffer and a Physical Address TAG RAM to reduce the effect of main memory bandwidth and latency on performance The ARM920T implements separate 16KB instruction and 16KB data caches The caches have the following features Virtually addressed 64 way associative cache 8 words per line 32 bytes per line with one valid bit and two dirty bits per line allowing half line write backs Write through and write back cache operation write back caches are also known as copy back caches selected per memory region by the C and B bits in the MMU translation tables for data cache only Pseudo random or round robin replacement selectable via RR bit in CP15 register 1 Low power CAM RAM implementation Caches independently lockable with granularity of 1 64th of cache which is 64 words 256 bytes For compatibility with Microsoft WindowsCE and to reduce interrupt latency the physical address corresponding to each data cache entry is stored in the physical address TAG RAM for use during cache line write backs in addition to the virtual address TAG stored in the cache CAMs This means that the MMU is not involved in cache write back operations removing the possibility of TLB misses related to the write back address Cache maintenance operations to provide efficient cleaning of the entire data cache and to provide efficient cleaning and invalidation of small regions of virtual memory The latter
131. line in the range base to 63 locking in the cache the lines with index in the range 0 to base 1 Data is loaded and locked into the DCache by first ensuring the data to be locked is not already in the cache This can be ensured by cleaning and flushing either the whole DCache or specific lines A short software routine can then be used to load the data into the DCache The software routine to load the data operates by writing to CP15 register 9 to force the replacement counter to a specific DCache line and then executing a load instruction to perform a cache lookup This will miss and a linefill will be performed bringing 8 words of data into the cache line specified by the replacement counter in the segment specified by bits 7 5 of the modified virtual address accessed by the load To load further lines into the cache the software routine can loop performing one load from each line to be loaded As each line contains 8 words each loop should add 32 bytes to the load address The software routine needs to move the victim counter to the next index after it has loaded a line into the last available segment with the current index As there are 8 segments this will occur after 8 cache lines have been loaded Once all the data has been loaded it is locked by writing to CP15 register 9 to move the replacement counter base to be one higher than the highest index of the locked cache lines The software routine that loads and locks the data i
132. lock down register Locking entries in the TLB guarantees that accesses to the locked page or section can proceed without incurring the time penalty of a TLB miss This allows the execution latency for time critical pieces of code such as interrupt handlers to be minimized ELECTRONICS 3 3 MMU ARM920T PROCESSOR All the CP15 MMU registers except register 8 contain state and can be read using MRC instructions and written using MCR instructions Registers 5 and 6 are also written by the MMU during a data abort Writing to Register 8 causes the MMU to perform a TLB operation to manipulate TLB entries This register cannot be read The instruction TLB I TLB and data TLB D TLB both have a copy of register 10 the 2 field in the CP15 instruction is used to determine which one is accessed The system control coprocessor CP15 is described in Programmer s Model on page 2 1 Details of register format and the coprocessor instructions to access them are given there ADDRESS TRANSLATION The MMU translates virtual addresses generated by the CPU core and by CP15 register 13 into physical addresses to access external memory It also derives and checks the access permission using a translation lookaside buffer TLB The MMU table walking hardware is used to add entries to the TLB The translation information which comprises both the address translation data and the access permission data resides in a translation table located
133. loop ASSEMBLER SYNTAX MCR MRC cond p lt expression1 gt Rd cn cm lt expression2 gt MRC Move from coprocessor to ARM920T register L 1 MCR Move from ARM920T register to coprocessor L 0 cond Two character condition mnemonic See Table 3 2 p The unique number of the required coprocessor lt 1 gt Evaluated to a constant and placed in the CP field Rd An expression evaluating to a valid ARM920T register number cn and cm Expressions evaluating to the valid coprocessor register numbers CRn and CRm respectively lt expression2 gt Where present is evaluated to a constant and placed in the CP field EXAMPLES MRC p2 5 R3 c5 c6 Request coproc 2 to perform operation 5 c5 c6 and transfer the single 32 bit word result back to R3 MCR p6 0 R4 c5 c6 Request coproc 6 to perform operation 0 R4 and place the result in c6 MRCEQ p3 9 R3 c5 c6 2 Conditionally request coproc 3 to perform operation 9 type 2 on c5 and c6 and transfer the result back to ELECTRONICS 3 57 ARM INSTRUCTION SET 83 2410 UNDEFINED INSTRUCTION The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction format is shown in Figure 3 28 31 2827 2524 on 7 1 Figure 3 28 Undefined Instruction If the condition is true the undefined instruction trap will be taken Note that
134. not support AFC function because the S3C2410A has no nRTS2 and nCTS2 11 14 ELECTRONICS 3C2410A UART UART TX RX STATUS REGISTER There are three UART Tx Rx status registers including UTRSTATO UTRSTAT1 and UTRSTAT2 in the UART block rms oeoo ums UART chanel Tax status register os ums oco 8 UART channel 2 Tux status reiser 06 Transmitter empty Set to 1 automatically when the transmit buffer register has no valid data to transmit and the transmit shift register is empty 0 Not empty 1 Transmitter transmit buffer amp shifter register empty Receive buffer data ready Set to 1 automatically whenever receive buffer register contains valid data received over the RXDn port 0 Empty 1 The buffer register has a received data In Non FIFO mode Interrupt or DMA is requested If the UART uses the FIFO users should check Rx FIFO Count bits and Rx FIFO Full bit in the UFSTAT register instead of this bit Transmit buffer empty Set to 1 automatically when transmit buffer register is empty 0 The buffer register is not empty 1 Empty In Non FIFO mode Interrupt or DMA is requested In FIFO mode Interrupt or DMA is requested when Tx FIFO Trigger Level is set to 00 Empty If the UART uses the FIFO users should check Tx FIFO Count bits and Tx FIFO Full bit in the UFSTAT register instead of this bit
135. number is unloaded by the MCU Reset Value OUT_FIFO_CNT1_ 0x52000198 L R End Point out write count register1 0x00 REG 0x5200019B B byte OUT CNT LOW 7 0 R w Lower byte of write count OUT_FIFO_CNT2_REG 0x5200019C L R End Point out write count register2 0x00 0x5200019F B byte OUT CNT HIGH 7 0 W Higher byte of write count The OUT CNT HIGH may be always 0 normally 13 20 ELECTRONICS 53 2410 USB DEVICE DMA INTERFACE CONTROL REGISTER 1_ 0 52000200 R W EP1 DMA interface control register 0x00 0x52000203 byte 2 0x52000218 R W EP2 interface control register 0x00 0x5200021B byte EP3 0 52000240 R W EP3 interface control register 0x00 0x52000243 byte 4 CON 0 52000258 R W EP4 interface control register 0x00 0x5200025B byte RUN 7 R W W Read IN_DMA_Run Observation 0 DMA is stopped 1 DMA is running Write Ignore _ _ _ register 0 DMA requests will be stopped if EPn n reaches 0 1 requests will be continued although EPn n reaches 0 STATE 6 4 W State Monitoring DEMAND_MODE 3 R W DMA Demand mode enable bit 0 Demand mode disable 1 Demand mode enable OUT_RUN_OB 2 R W R W Functionally separated into write and read OUT RUN operation Write operation 0 Stop 1 Run Read operation OUT
136. number of 8 bit multiplier array cycles required to complete the multiply which is controlled by the value of the multiplier operand specified by Rs Its possible values are as follows For Signed INSTRUCTIONS SMULL SMLAL e If bits 31 8 of the multiplier operand are all zero or all one e If bits 31 16 of the multiplier operand are all zero or all one e f bits 31 24 of the multiplier operand are all zero or all one e other cases For Unsigned Instructions UMULL UMLAL If bits 31 8 of the multiplier operand are all zero e If bits 31 16 of the multiplier operand are all zero e If bits 31 24 of the multiplier operand are all zero e In all other cases and are defined as sequential S cycle and internal respectively 3 26 ELECTRONICS 3C2410A ARM INSTRUCTION SET ASSEMBLER SYNTAX Table 3 5 Assembler Syntax Descriptions UMULL cond S RdLo RdHi Rm Rs Unsigned Multiply Long 32 x 32 64 UMLAL cond S RdLo RdHi Rm Rs Unsigned Multiply amp Accumulate Long 32 x 32 64 64 SMULL cond S RdLo RdHi Rm Rs Signed Multiply Long 32 x 32 64 SMLAL cond S RdLo RdHi Rm Rs Signed Multiply amp Accumulate Long 32 x 32 64 64 where Two character condition mnemonic See Table 3 2 S Set condition codes if S present RdLo RdHi Rm Rs Expressions evaluating to a register number other than R15 EXAMPLES UMULL R1 R4 R2
137. of the LCD frame buffer FRAME Buffer Start Address 2 Register LCDSADDR2 0X4D000018 STN TFT Frame buffer start address 2 register 0x00000000 20 0 LCDBASEL For dual scan LCD These bits indicate A 21 1 of the start address of 0x0000 the lower address counter which is used for the lower frame memory of dual scan LCD For single scan LCD These bits indicate A 21 1 of the end address of the LCD frame buffer LCDBASEL the fame end address gt gt 1 1 LCDBASEU PAGEWIDTH OFFSIZE x LINEVAL 1 NOTE Users can change the LCDBASEU and LCDBASEL values for scrolling while the LCD controller is turned on But users must not change the value of the LCDBASEU and LCDBASEL registers at the end of FRAME by referring to the LINECNT field in LCDCON1 register for the LCD FIFO fetches the next frame data prior to the change in the frame So if you change the frame the pre fetched FIFO data will be obsolete and LCD controller will display an incorrect screen To check the LINECNT interrupts should be masked If any interrupt is executed just after reading LINECNT the read LINECNT value may be obsolete because of the execution time of Interrupt Service Routine ISR 15 32 ELECTRONICS 3C2410A LCD CONTROLLER FRAME Buffer Start Address 3 Register LCDSADDR3 0 4000001 STN TFT Virtual screen address set 0x00000000 OFFSIZE 21 11 Virtual screen offset size the number of half words 00000000000 This value defines the
138. of zeros This preserves the sign in 2 s complement notation For example ASR 5 is shown in Figure 3 8 Contents of Rm carry out Value of Operand 2 Figure 3 8 Arithmetic Shift Right The form of the shift field which might be expected to give ASR 0 is used to encode ASR 32 Bit 31 of Rm is again used as the carry output and each bit of operand 2 is also equal to bit 31 of Rm The result is therefore all ones or all zeros according to the value of bit 31 of Rm ELECTRONICS 3 13 ARM INSTRUCTION SET 3 2410 Rotate right ROR operations reuse the bits which overshoot in logical shift right operation by reintroducing them at the high end of the result in place of the zeros used to fill the high end in logical right operations For example ROR 5 is shown in Figure 3 9 31 5 4 0 Contents of Rm carry out Value of Operand 2 Figure 3 9 Rotate Right The form of the shift field which might be expected to give ROR 0 is used to encode a special function of the barrel shifter rotate right extended RRX This is a rotate right by one bit position of the 33 bit quantity formed by appending the CPSR C flag to the most significant end of the contents of Rm as shown in Figure 3 10 Contents of Rm in Value of Operand 2 Figure 3 10 Rotate Right Extended 3 14 ELECTRONICS 53 2410 ARM INSTRUCTION SET Register Specified Shift Amount Only the least significant byte of the contents of Rs is used
139. on chip coprocessor also So then all coprocessor instructions will cause the undefined instruction trap to be taken on the S3C2410A These coprocessor instructions can be emulated by the undefined trap handler Even though external coprocessor can not be connected to the 53 2410 the coprocessor instructions are still described here in full for completeness Remember that any external coprocessor described in this section is a software emulation 31 28 27 24 23 20 19 16 15 12 11 8 7 5 4 3 I plo 3 0 Coprocessor operand register 7 5 Coprocessor information 11 8 Coprocessor number 15 12 Coprocessor destination register 19 16 Coprocessor operand register 23 20 Coprocessor operation code 31 28 Condition Field Figure 3 25 Coprocessor Data Operation Instruction Only bit 4 and bits 24 to 31 The coprocessor fields are significant to ARM920T The remaining bits are used by coprocessors The above field names are used by convention and particular coprocessors may redefine the use of all fields except CP as appropriate The CP field is used to contain an identifying number in the range 0 to 15 for each coprocessor and a coprocessor will ignore any instruction which does not contain its number in the CP field The conventional interpretation of the instruction is that the coprocessor should perform an operation specified in the CP Opc field and possibly in the CP field on the conte
140. output 31 ELECTRONICS 3 29 ARM INSTRUCTION SET S3C2410A memory register LDR from word aligned address memory register LDR from address offset by 2 Figure 3 15 Little Endian Offset Addressing Big Endian Configuration A byte load LDRB expects the data on data bus inputs 31 through 24 if the supplied address is on a word boundary on data bus inputs 23 through 16 if it is a word address plus one byte and so on The selected byte is placed in the bottom 8 bits of the destination register and the remaining bits of the register are filled with zeros Please see Figure 2 1 A byte store STRB repeats the bottom 8 bits of the source register four times across data bus outputs 31 through 0 The external memory system should activate the appropriate byte subsystem to store the data A word load LDR should generate a word aligned address An address offset of 0 or 2 from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 31 through 24 This means that half words accessed at these offsets will be correctly loaded into bits 16 through 31 of the register A shift operation is then required to move and optionally sign extend the data into the bottom 16 bits An address offset of 1 or 3 from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 15 through 8 A word store STR should generate a word aligned address The wo
141. own power on off control port and when port is connected to LCD PWREN pin LCD PWREN VFRAME STN LCD LCD PWREN 1 LCD Panel ON I lt q A i iii nnn 1 FRAME LCD Figure 15 8 Example of PWREN Function PWREN 1 INVPWREN 0 ELECTRONICS 15 25 LCD CONTROLLER 53 2410 LCD CONTROLLER SPECIAL REGISTERS LCD Control 1 Register LCDCON1 0X4D000000 LCD control 1 register 0x00000000 LINECNT 27 18 Provide the status of the line counter 0000000000 read only Down count from LINEVAL to 0 CLKVAL 17 8 Determine the rates of and CLKVAL 9 0 0000000000 STN VCLK HCLK CLKVAL x 2 CLKVAL 22 VCLK HCLK CLKVAL 1 x 2 CLKVAL 20 MMODE 7 Determine the toggle rate of the VM 0 Each Frame 1 The rate defined by the MVAL PNRMODE 6 5 Select the display mode 00 4 bit dual scan display mode STN 01 4 bit single scan display mode STN 10 8 bit single scan display mode STN 11 TFT LCD panel BPPMODE 4 1 Select the BPP Bits Per Pixel mode 0000 1 bpp for STN Monochrome mode 0001 2 bpp for STN 4 level gray mode 0010 4 bpp for STN 16 level gray mode 0011 8 bpp for STN color mode 0100 12 bpp for STN color mode 1000 1 bpp for TFT 1001 2 bpp for TFT 1010 4 bpp for TFT 1011 8 bpp for TFT 1100 16 bpp for TFT 1101 24 bpp for TFT ENVID LCD video output and the logic enable disable 0 Disable the video output and the LCD contro
142. page For large pages ap3 is selected by the top 16KB of the page and ap0 is selected by the bottom 16KB of the page The selected AP bits are then interpreted in exactly the same way as for a section see Table 3 6 on page 3 20 the only difference being the fault generated is a page permission fault If the level one descriptor defines a page mapped access and the level two descriptor is for a tiny page the AP bits of the level one descriptor define whether or not the access is allowed in the same way as for a section The fault generated is a page permission fault 3 23 MMU ARM920T PROCESSOR EXTERNAL ABORTS In addition to the MMU generated aborts the ARM920T can be externally aborted by the AMBA bus which may be used to flag an error on an external memory access However not all accesses can be aborted in this way and the Bus Interface Unit BIU ignores external aborts that can not be handled The following accesses may be aborted non cached reads unbuffered writes read lock write sequence to non cacheable memory In the case of a read lock write SWP sequence in which the read aborts the write will always be attempted 3 24 ELECTRONICS ARM920T PROCESSOR MMU INTERACTION OF THE MMU AND CACHES The MMU is enabled and disabled using bit 0 of the CP15 control register ENABLING THE MMU To enable the MMU 1 Program the translation table base and domain access control registers 2 Program level 1 and level 2 pa
143. page walk a small or large page has a non identical sub page permission only the sub page being accessed is written into the TLB For example 16KB large page sub page entry will be written into the TLB if the sub page permission differs and a 64KB entry will be put in the TLB if the sub page permissions are identical When sub page permissions are used and the page entry then needs invalidating all four sub pages must be invalidated separately MMU FAULTS AND CPU ABORTS The MMU generates an abort on the following types of faults e alignment faults data accesses only e translation faults e domain faults permission faults In addition an external abort may be raised by the external system as a result of certain types of external data access Alignment fault checking is enabled by the A bit in CP15 register 1 Alignment fault checking is not affected by whether or not the MMU is enabled Translation domain and permission faults are only generated when the MMU is enabled The access control mechanisms of the MMU detect the conditions that produce these faults If a fault is detected as the result of a memory access the MMU will abort the access and signal the fault condition to the CPU core The MMU retains status and address information about faults generated by the data accesses in the fault status register and fault address register see section Fault address and fault status registers on page 3 18 The MMU does not reta
144. purpose of evaluation each master should detect the address bits While each master generates the slaver address it should also detect the address bit on the SDA line because the SDA line is likely to get Low rather than to keep High Assume that one master generates a Low as first address bit while the other master is maintaining High In this case both masters will detect Low on the bus because the Low status is superior to the High status in power When this happens Low as the first bit of address generating master will get the mastership while High as the first bit of address generating master should withdraw the mastership If both masters generate Low as the first bit of address there should be an arbitration for the second address bit again This arbitration will continue to the end of last address bit ABORT CONDITIONS If a slave receiver cannot acknowledge the confirmation of the slave address it should hold the level of the SDA line High In this case the master should generate a Stop condition and to abort the transfer If a master receiver is involved in the aborted transfer it should signal the end of the slave transmit operation by canceling the generation of an ACK after the last data byte received from the slave The slave transmitter should then release the SDA to allow a master to generate a Stop condition CONFIGURING IIC BUS To control the frequency of the serial clock SCL the 4 bit prescaler value can be programm
145. range is from 0 28 1 Reserved 7 6 Reserved These two bits must be 00 in normal operation Watchdog Timer 5 Enable or disable bit of Watchdog timer 0 Disable 1 Enable Clock Select 4 3 Determine the clock division factor 00 16 01 32 10 64 11 128 Interrupt Generation Enable or disable bit of the interrupt 0 Disable 1 Enable Reserved 1 Reserved This bit must be 0 in normal operation Reset Enable or disable bit of Watchdog timer output for reset signal Enable Disable 1 Assert reset signal of the 53 2410 at watchdog time out 0 Disable the reset function of the watchdog timer ELECTRONICS 18 3 WATCHDOG TIMER DATA WTDAT REGISTER The WTDAT register is used to specify the time out duration The content of WTDAT cannot be automatically loaded into the timer counter at initial watchdog timer operation However using 0x8000 initial value will drive the first time out In this case the value of WTDAT will be automatically reloaded into WTCNT WTDAT 0x53000004 Watchdog timer data register 0x8000 Count Reload Value 15 0 Watchdog timer count value for reload 0x8000 WATCHDOG TIMER COUNT WTCNT REGISTER The WTCNT register contains the current count values for the watchdog timer during normal operation Note that the content of the WTDAT register cannot be automatically loaded into the timer count register when the watchdog timer is enabled initially so the WTCNT register must be se
146. refresh mode by setting the REFRESH 22 1b 10 Wait until SDRAM self refresh is effective 11 Set MISCCR 19 17 111b to make SDRAM signals SCLKO SCLK1 and SCKE protected during Power OFF mode 12 Set the Power OFF mode bit in the CLKCON register 7 14 ELECTRONICS 3 2410 CLOCK amp POWER MANAGEMENT Procedure to Wake up from Power_OFF mode 1 The internal reset signal will be asserted if one of the wake up sources is issued This reset duration is determined by the internal 16 bit counter logic and the reset assertion time is calculated as tRST 65535 XTAL frequency Check GSTATUS2 2 in order to know whether or not the power up is caused by the wake up from Power OFF mode Release the SDRAM signal protection by setting MISCCR 19 17 000b Configure the SDRAM memory controller Wait until the SDRAM self refresh is released Mostly SDRAM needs the refresh cycle of all SDRAM row The information in GSTATUS3 4 can be used for user s own purpose because the value in GSTATUS3 4 has been preserved during Power_OFF mode For EINT 3 0 check the SRCPND register For EINT 15 4 check the EINTPEND instead of SRCPND SRCPND will not be set although some bits of EINTPEND set For alarm wake up check the RTC time because the RTC bit of SRCPND isn t set at the alarm wake up If there was the nBATT assertion during POWER OFF mode the corresponding bit of SRCPND has been set Pin
147. register on page 2 8 e Register 1 Control register on page 2 10 e Register 2 Translation table base TTB register on page 2 12 e Register 3 Domain access control register on page 2 13 e Register 4 Reserved on page 2 14 e Register 5 Fault status registers on page 2 14 e Register 6 Fault address register on page 2 15 e Register 7 Cache operations on page 2 15 e Register 8 TLB operations on page 2 18 e Register 9 Cache lock down register on page 2 19 e Register 10 TLB lock down register on page 2 21 e Registers 11 12 amp 14 Reserved on page 2 22 e Register 13 Process ID on page 2 22 e Addresses in ARM920T on page 2 6 e Register 15 Test configuration register on page 2 24 ELECTRONICS 2 3 PROGRAMMER S MODEL ARM920T PROCESSOR CP15 REGISTER MAP SUMMARY CP15 defines 16 registers The register map for CP15 is shown in Table 2 2 Table 2 2 CP15 Register Map 5 Fusus E Fata 5 jupa 77 1 Register location 0 provides access to more than one register The register accessed depends upon the value of the opcode 2 field See the register description for details 2 Separate registers for instruction and data See the register description for details 2 4 ELECTRONICS ARM920T PROCESSOR PROGRAMMER S MODEL ACCESSING CP15 REGISTERS Throughout this section the following terms and abbreviations are used Table 2 3 CP15 Abbrev
148. requested 1 Requested EINTO of 0 Not requested ELECTRONICS 1 Requested Reseed f B wa 14 15 INTERRUPT CONTROLLER S3C2410A INTERRUPT OFFSET INTOFFSET REGISTER The value in the interrupt offset register shows which interrupt request of IRQ mode is in the INTPND register This bit can be cleared automatically by clearing SRCPND and INTPND INTOFFSET 0x4A000014 R indicate the IRQ interrupt request source 0x00000000 INT Source The OFFSET Value INT Source The OFFSET Value INT RTC INT SPH INT UARTO INT INT USBH INT USBD Reserved INT_UART1 INT_SPIO INT_SDI INT_DMA3 INT_DMA2 INT DMA1 INT DMAO INT LCD wmm wmm m wmm 2 wmm wmm ee m ees 1 m ma ms ewe 3 3 2 2 2 2 2 2 2 2 2 2 1 0 9 8 7 6 5 4 3 2 1 0 19 18 17 16 NOTE FIQ mode interrupt does not affect the INTOFFSET register as the register is available only for IRQ mode interrupt 14 16 ELECTRONICS 53 2410 INTERRUPT CONTROLLER SUB SOURCE PENDING SUBSRCPND REGISTER You can clear a specific bit of the SUBSRCPND register by writing a data to this register It clears only the bit positions of the SUBSRCPND register corresponding to those set to one in the data The bit positions corresponding to those that are set to 0 in the data remains as
149. screen This is the data of line 11 of virtual screen LCDBASEU Before Scrolling LCDBASEL This is the data 1 of virtual screen This i the data of line 1 of virtual screen This is the data of line 2 of virtual screen This is the data of line 2 of virtual screen This is the data of line 3 of virtual screen This is the data of line 4 of virtual screen This is the data of line 5 of virtual screen This is the data of line 6 of virtual screen This is the data of line 7 of virtual screen This is the data of line 8 of virtual screen This is the data of line 9 of virtual screen This is the data of line 9 of virtual screen This is the data of line 10 of virtual screen This is the data of line 10 of virtual screen This is the data of line 11 of virtual screen This is the data of line 11 of virtual screen After Scrolling Figure 15 7 Example of Scrolling in Virtual Display Single Scan 15 24 ELECTRONICS 3C2410A LCD CONTROLLER LCD POWER ENABLE STN TFT The S3C2410A provides Power enable PWREN function When PWREN is set to make PWREN signal enabled the output value of LCD PWREN pin is controlled by ENVID In other words If LCD PWREN pin is connected to the power on off control pin of the LCD panel the power of LCD panel is controlled by the setting of ENVID automatically The 53 2410 also supports INVPWREN bit to invert polarity of the PWREN signal This function is available only when LCD panel has its
150. set to 0 in the data remains as they are SRCPND 0 4 000000 R W Indicate the interrupt request status 0x00000000 0 The interrupt has not been requested 1 The interrupt source has asserted the interrupt request 14 6 ELECTRONICS 3C2410A SOURCE PENDING SRCPND REGISTER Continued INTERRUPT CONTROLLER 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested hosa _ _ INT_TIMER4 14 0 Not requested INT_TIMER3 13 INT_TIMER2 12 INT_TIMER1 11 0 Not requested INT_TIMER0 0 Not requested INT_WDT 0 Not requested 0 Not requested 0 Not requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested EINT1 0 Not requested 1 Requested EINTO of 0 Not requested ELECTRONICS 1 Requested Reseed f B wa INTERRUPT CONTROLLER S3C2410A INTERRUPT MODE INTMOD REGISTER This register is composed of 32 bits each of which is related to an interrupt source If a specific bit is set to 1 the corresponding interrupt is processed in the FIQ fast interrupt mode Otherwise it is processed in the IRQ mode normal interrupt Note that only one interrup
151. the current victim pointer for all cache segments Bits 25 0 should be zero The victim counter specifies the cache line to be used as the victim for the next linefill This is incremented using either a random or round robin replacement policy determined by the state of the RR bit in register 1 The victim counter generates values in the range base to 63 This locks lines with index values in the range 0 to base 1 If base 0 there are no locked lines Writing to CP15 register 9 updates the base pointer and the current victim pointer The next linefill will use and then increment the victim pointer The victim pointer will continue incrementing on linefills and will wrap around to the base pointer For example setting the base pointer to 0x3 prevents the victim pointer from selecting entries 0 0 to Ox2 locking them into the cache Load a cache line into ICache line 0 and lock it down MCR to CP15 register 9 opcode 2 0 1 Victim Base 0 0 MCR I prefetch Assuming the misses a linefill will occur to line 0 MCR to CP15 register 9 2 0 1 Victim Base 0 1 Further linefills will now occur into lines 1 63 Load a cache line into DCache line 0 and lock it down MCR to CP15 register 9 opcode_2 0 0 Victim 0 0 Data load LDR LDM Assuming the DCache misses a linefill will occur to line 0 MCR to CP15 register 9 opcode_2 0 0 Victim Base 0 1 Further DC
152. the memory controller there will be four successive word data transfers from system memory to internal FIFO The total size of FIFO is 28 words which consists of 12 words FIFOL and 16 words FIFOH respectively The S3C2410A has two FIFOs to support the dual scan display mode In case of single scan mode one of the FIFOs FIFOH can only be used ELECTRONICS 15 3 LCD CONTROLLER S3C2410A STN LCD CONTROLLER OPERATION TIMING GENERATOR TIMEGEN The TIMEGEN generates the control signals for the LCD driver such as VFRAME VLINE VCLK and VM These control signals are closely related to the configuration on the LCDCON1 2 3 4 5 registers in the REGBANK Based on these programmable configurations on the LCD control registers in the REGBANK the TIMEGEN can generate the programmable control signals suitable to support many different types of LCD drivers The VFRAME pulse is asserted for the duration of the entire first line at a frequency of once per frame The VFRAME signal is asserted to bring the LCD s line pointer to the top of the display to start over The VM signal helps the LCD driver alternate the polarity of the row and column voltages which are used to turn the pixel on and off The toggling rate of VM signals depends on the MMODE bit of the LCDCON1 register MVAL field of the LCDCON4 register If the MMODE bit is 0 the VM signal is configured to toggle on every frame If the MMODE bit is 1 the VM signal is configured to toggle o
153. to a more significant position The least significant bits of the result are filled with zeros and the high bits of Rm which do not map into the result are discarded except that the least significant discarded bit becomes the shifter carry output which may be latched into the C bit of the CPSR when the ALU operation is in the logical class see above For example the effect of LSL 5 is shown in Figure 3 6 Contents of Rm carry out Value of Operand 2 00000 Figure 3 6 Logical Shift Left NOTE LSL 0 is a special case where the shifter carry out is the old value of the CPSR C flag The contents of Rm are used directly as the second operand A logical shift right LSR is similar but the contents of Rm are moved to less significant positions in the result LSR 5 has the effect shown in Figure 3 7 3 12 ELECTRONICS 3C2410A ARM INSTRUCTION SET 31 5 4 0 Contents of Rm carry out 00000 Value of Operand 2 Figure 3 7 Logical Shift Right The form of the shift field which might be expected to correspond to LSR 0 is used to encode LSR 32 which has a zero result with bit 31 of Rm as the carry output Logical shift right zero is redundant as it is the same as logical shift left zero so the assembler will convert LSR 0 and ASR 0 and ROR 0 into LSL 0 and allow LSR 32 to be specified An arithmetic shift right ASR is similar to logical shift right except that the high bits are filled with bit 31 of Rm instead
154. valid address tags It should be noted that the two instructions after the MCR to write the will have been fetched with the old ProclD ProclD 0 MOV 1 SHL 25 Fetched with ProclD 0 MCR p15 0 r0 c13 c0 0 Fetched with ProclD 0 Al Fetched with 0 A2 Fetched with ProclD 0 A3 Fetched with 1 REGISTER 15 TEST CONFIGURATION REGISTER Register 15 is used for test purposes Accessing reading or writing this register will cause the 920 to have unpredictable behavior 2 24 ELECTRONICS ARM920T PROCESSOR MMU Appendix 3 MMU ABOUT THE MMU ARMS920T implements an enhanced ARM Architecture V4 MMU to provide translation and access permission checks for the instruction and data address ports of the ARM9TDMI The MMU is controlled from a single set of two level page tables stored in main memory and are enabled by M Bit in CP15 register 1 providing a single address translation and protection scheme The instruction and data TLBs in the MMU can be independently locked and flushed The MMU features are standard ARM V4 MMU mapping sizes domains and access protection scheme e mapping sizes are 1MB sections 64KB large pages 4KB small pages and new 1KB tiny pages access permissions for sections access permissions for large pages and small pages can be specified separately for each quarter of the page these quarters are called sub pages 16 domains implem
155. with a 32 bit result SMLAL Rd Rt Rm Rn 4 107 cycles TEQ Rt Rd ASR 31 1 cycle and a register BNE overflow 3 60 ELECTRONICS 3C2410A 5 Overflow in unsigned multiply accumulate with a 64 bit result UMULL RI Rh Rm Rn 3106 cycles ADDS RI RI Ra1 Lower accumulate ADC Rh Rh Ra2 Upper accumulate BCS overflow 1 cycle and 2 registers 6 Overflow in signed multiply accumulate with a 64 bit result SMULL RI Rh Rm Rn 3106 cycles ADDS RI Rl Rat Lower accumulate ADC Rh Rh Ra2 Upper accumulate BVS overflow 1 cycle and 2 registers NOTE ARM INSTRUCTION SET Overflow checking is not applicable to unsigned and signed multiplies with a 64 bit result since overflow does not occur in such calculations PSEUDO RANDOM BINARY SEQUENCE GENERATOR It is often necessary to generate pseudo random numbers and the most efficient algorithms are based on shift generators with exclusive OR feedback rather like a cyclic redundancy check generator Unfortunately the sequence of a 32 bit generator needs more than one feedback tap to be maximal length i e 2 32 1 cycles before repetition so this example uses a 33 bit register with taps at bits 33 and 20 The basic algorithm is newbit bit 33 eor bit 20 shift left the 33 bit number and put in newbit at the bottom this operation is performed for all the newbits needed i e 32 bits The entire operation can be done in 5 S cycles Enter with seed in Ra 82 bits Rb 1 bit
156. with the five data lines for shifting and sampling of the information Making the appropriate bit settings to the SDIPRE register depends on the transmission frequency You can modify its frequency to adjust the baud rate data register value Programming Procedure common SDI modules can be programmed following these basic steps 1 Set SDICON to configure properly with clock and interrupt 2 Set SDIPRE to configure with a proper value 3 Wait 74 SDCLK clock cycle in order to initialize the card CMD Path Programming 1 Write command argument 32 bit to SDICARG register 2 Determine command types and start command by setting SDICCON 8 3 Confirm the end of SDI command operation when the specific flag of SDICSTA is set Ifthe type of command is no response the flag is SDICSTA 11 lf the type of command is with response the flag is SDICSTA 9 4 Clear the corresponding flag of the SDICSTA register by writing one to the flag bit DAT Path Programming Write timeout period to SDIDTIMER register 2 Write block size block length to SDIBSIZE register normally 0x200 byte 3 Determine the mode of block wide bus DMA etc and start data transfer with setting SDIDCON register 4 Write Tx data to SDIDAT register while Tx FIFO is available by checking SDIFSTA available half or empty register 5 Read Rx data from SDIDAT register while Rx FIFO is available by checking SDIFSTA available half or be last data register
157. 0 L W UART channel 1 transmit buffer register UTXH2 0x50008020 L W UART channel 2 transmit buffer register TXDATAn 7 0 _ Transmit data for UARTn DL m NOTE L The endian mode is Little endian B The endian mode is Big endian UART RECEIVE BUFFER REGISTER HOLDING REGISTER amp FIFO REGISTER There are three UART receive buffer registers including URXHO URXH1 and URXH2 in the UART block URXHn has an 8 bit data for received data URXHO 0x50000024 L R UART channel 0 receive buffer register 0x50000027 B by byte URXH1 0x50004024 R UART channel 1 receive buffer register 0x50004027 B by byte URXH2 0x50008024 L R UART channel 2 receive buffer register 0x50008027 B by byte RXDATAn 7 0 Receive data for UARTn 20 2 NOTE When an overrun error occurs the URXHn must be read If not the next received data will also make an overrun error even though the overrun bit of UERSTATn had been cleared ELECTRONICS 11 19 UART S3C2410A UART BAUD RATE DIVISOR REGISTER There are three UART baud rate divisor registers including UBRDIV0 UBRDIV1 and UBRDIV2 in the UART block The value stored in the baud rate divisor register UBRDIVn is used to determine the serial Tx Rx clock rate baud rate as follows UBRDIVn int PCLK bps x 16 or UBRDIVn int UEXTCLK bps x 16 Where the divisor should be from 1 to 2 5 1 and UEXTCLK should be smaller than PCLK For example
158. 0000000 0 The interrupt has not been requested 1 The interrupt source has asserted the interrupt request NOTES 1 Ifthe mode interrupt occurs the corresponding bit of INTPND will not be turned on as the INTPND register is available only for IRQ mode interrupt 2 Cautions in clearing the INTPND register The INTPND register is cleared to 0 by writing 1 If the INTPND bit which has 1 is cleared by 0 the INTPND register amp INTOFFSET register may have unexpected value in some case So you never write 0 on the INTPND bit having 1 The convenient method to clear the INTPND register is writing the INTPND register value on the INTPND register In even our example code this guide hasn t been applied yet 14 14 ELECTRONICS 53 2410 INTERRUPT CONTROLLER 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested hosa _ _ INT_TIMER4 14 0 Not requested INT_TIMER3 13 INT_TIMER2 12 INT_TIMER1 11 0 Not requested INT_TIMER0 0 Not requested INT_WDT 0 Not requested 0 Not requested 0 Not requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested 1 Requested EINT1 0 Not
159. 00000000 TCMPB3 0x51000034 Timer 3 compare buffer register 0x00000000 Timer 3 compare buffer register 15 0 Set compare buffer value for Timer 3 0x00000000 Timer 3 count buffer register 15 0 Set count buffer value for Timer 3 0x00000000 TIMER 3 COUNT OBSERVATION REGISTER TCNTO3 0x51000038 Timer 3 count observation register 0x00000000 Timer 3 observation register 15 0 Set count observation value for Timer 3 0x00000000 10 18 ELECTRONICS 53 2410 TIMER 4 COUNT BUFFER REGISTER TCNTB4 v m gt TCNTB4 0x5100003C Timer 4 count buffer register 0x00000000 Timer 4 count buffer register 15 0 Set count buffer value for Timer 4 TIMER 4 COUNT OBSERVATION REGISTER TCNTO4 TCNTO4 0x51000040 R Timer 4 count observation register Timer 4 observation register 15 0 Set count observation value for Timer 4 ELECTRONICS Initial State 0x00000000 Reset Value 0x00000000 Initial State 0x00000000 10 19 PWM TIMER 3 2410 NOTES 10 20 ELECTRONICS 53 2410 UART 11 OVERVIEW The 53 2410 UART Universal Asynchronous Receiver and Transmitter provides three independent asynchronous serial I O SIO ports each of which can operate in Interrupt based or DMA based mode In other words the UART can generate an interrupt or a DMA request to transfer data between CPU and the UART The UART can support bit rates of up to 230 4K bps using system clock If
160. 0A Special Registers Continued Register Address Address Acc Read Function Name B Endian L Endian Unit Write PWM Timer TCFGO 0x51000000 lt R W Timer Configuration TCFG1 0x51000004 Timer Configuration Timer Control TCON 0x51000008 TONTBO 0x5100000C Timer Count Buffer 0 TONTOO 0x51000014 R Timer Count Observation 0 TCNTB1 0x51000018 R W TCMPBO 0x51000010 Timer Compare Buffer 0 Timer Count Buffer 1 TCMPB1 0x5100001C TCNTO1 0x51000020 R Timer Count Observation 1 Timer Compare Buffer 1 Timer Count Buffer 2 Timer Compare Buffer 2 RW Timer Count Observation 2 R W Timer Count Buffer Timer Compare Buffer 3 Timer Count Observation 3 R W Timer Count Buffer 4 Timer Count Observation 4 ELECTRONICS 1 3 PRODUCT OVERVIEW 3 2410 Table 1 4 S3C2410A Special Registers Continued Register Name Address Address Acc Read Function B Endian L Endian Unit Write USB Device FUNC ADDR REG 0x52000143 0x52000140 B R W Function Address PWR REG 0x52000147 0x52000144 Power Management EP INT REG 0x5200014B 0x52000148 EP Interrupt Pending and Clear USB INT REG 0x5200015B 0x52000158 USB Interrupt Pending and Clear EP INT EN REG 0x5200015F 0x5200015C Interrupt Enable USB INT EN REG 0x5200016F 0x5200016C Interrupt Enable Frame Number LowerByie EPO CSR 0x52000187 0x52000184 Endpoint 0 Status 1 32 ELECTRONICS 3 2410 PRODUCT OVERV
161. 1 Total Vppi Vppio Bus Rate 1 24 Typical idle mode power NOTE S 124 177 mW NOTE 2 Typical slow mode power NOTE 3 33 33 mW FCLK 12MHz Total Vppi Vppio Bus Rate 1 1 1 Maximum Power_OFF mode power 80 100 uA Just running 32 768KHz NOTE 3 8 50 uA oscillator for RTC all other Typical Power OFF mode power NOTE 3 static Maximum RTC power 5 5 uA X tal 32 768KHz for RTC Typical RTC power NOTE 3 3 3 uA VDDartc 1 8V NOTES 1 Playing matrix2 wmv on PPC2003 2 threads ready to run on 2003 3 Room temperature specification ELECTRONICS 24 3 ELECTRICAL DATA 3 2410 ELECTRICAL CHARACTERISTICS tXTALCYC 1 2 1 2 NOTE The clock input from the pin Figure 24 1 XTIpII Clock Timing tEXTCYC tEXTHIGH lt tEXTLOW VIH 1 2 1 2 NOTE The clock input from the EXTCLK pin Figure 24 2 EXTCLK Clock Input Timing EXTCLK HCLK internal Figure 24 3 EXTCLK HCLK in case that EXTCLK is used without the PLL 24 4 ELECTRONICS S3C2410A EXTCLK HCLK internal tHC2CK CLKOUT HCLK SCLK ELECTRICAL DATA nRESET ELECTRONICS Figure 24 5 Manual Reset Input Timing 24 5 ELECTRICAL DATA S3C2410A PLL can operate after OM 3 2 is latched or EXTCLK Clock Disable is configured by S W first time tPLL E
162. 1 Bank 6 7 Addresses icem ee eat ee ee 5 2 5 2 SDRAM Bank Address Configuration 5 4 7 1 Clock Source Selection at 7 2 7 2 Clock and Power State in Each Power 7 10 7 3 CLKSLOW CLKDIVN Register Settings for SLOW Clock 7 11 53 2410 MICROPROCESSOR xxvii List of Tables Continued Table Title Page Number Number 8 1 DMA Request Sources for Each Channel 8 2 8 2 DMA Controller Module Signal Timing Constants 8 3 9 1 S3C2410A Port Configuration ener nnne en 9 2 11 1 Interrupts in Connection with FIFO aras 11 5 12 1 Registers for USB Host 12 2 15 1 Relation Between and CLKVAL STN HCLK 60 MH2 15 5 15 2 Dither Duty Cycle Examples entente nennen nes 15 7 15 3 Relation Between and CLKVAL TFT HCLK 60 MH2 15 15 15 4 5 6 5 EOFffldl cer cadens esc n e a 15 20 15 5 5 5 5 1 iem 15 20 15 6 MV Value for Each Display Mode 15 39 16 1 Condition of Touch Screen Panel Pads in Separat
163. 1 contain the previous converted data ELECTRONICS 16 5 ADC AND TOUCH SCREEN INTERFACE S3C2410A Programming Notes 1 The A D converted data can be accessed by means of interrupt or polling method With interrupt method the overall conversion time from A D converter start to converted data read may be delayed because of the return time of interrupt service routine and data access time With polling method by checking the ADCCON 15 end of conversion flag bit the read time from ADCDAT register can be determined 2 A D conversion can be activated in different way After ADCCON 1 A D conversion start by read mode is set to 1 A D conversion starts simultaneously whenever converted data is read X Conversion Y Gonversion tie I 1 F stylus Down Stylus Up I gt gt lt gt B C D x 1 X Tal Clock or A D x 1 External Clock 1 PCLK D x 1 PCLK DELAY value of ADCDLY Register A B D Figure 16 3 Timing Diagram in Auto Sequential Position Conversion Mode 16 6 ELECTRONICS 3C2410A ADC AND TOUCH SCREEN INTERFACE ADC AND TOUCH SCREEN INTERFACE SPECIAL REGISTERS ADC CONTROL ADCCON REGISTER ADCCON 0x58000000 ADC control register Ox3FC4 15 ECFLG End of conversion flag read only 0 A D conversion in process 1 End of A D conversion PRSCEN 14 A D converter prescaler enable 0 Disable 1 Enable PRSCVL 13 6 A D converter prescaler value Data value 1 255
164. 10 BIG ENDIAN FORMAT In Big Endian format the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte Byte 0 of the memory system is therefore connected to data lines 31 through 24 Higher Address Word Address Lower Address significant byte is at lowest address Word is addressed by byte address of most significant byte Figure 2 1 Big Endian Addresses of Bytes within Words LITTLE ENDIAN FORMAT In Little Endian format the lowest numbered byte in a word is considered the word s least significant byte and the highest numbered byte the most significant Byte 0 of the memory system is therefore connected to data lines 7 through 0 Higher Address Word Address Lower Address Least significant byte is at lowest address is addressed by byte address of least significant byte Figure 2 2 Little Endian Addresses of Bytes within Words INSTRUCTION LENGTH Instructions are either 32 bits long in ARM state or 16 bits long in THUMB state Data Types 920 supports byte 8 bit halfword 16 bit and word 32 bit data types Words must be aligned to four byte boundaries and half words to two byte boundaries 2 2 ELECTRONICS 3C2410A PROGRAMMER S MODEL OPERATING MODES ARM920T supports seven modes of operation e User usr The normal ARM program execution state Designed to support a data tra
165. 10 USB DEVICE INTERRUPT ENABLE REGISTER INT REG USB INT REG Corresponding to each interrupt register The USB device controller also has two interrupt enable registers except resume interrupt enable By default usb reset interrupt is enabled If bit 0 the interrupt is disabled If bit 2 1 the interrupt is enabled EP INT EN REG 0x5200015C L R W Determine which interrupt is enabled OxFF 0x5200015F B byte EPINT EN REG mcu USB Description _______ Initial State EP4_INT_EN 4 R W a Interrupt Enable bit Interrupt disable 1 Enable EP3_INT_EN 8 R W d Interrupt Enable bit Interrupt disable 1 Enable EP2_INT_EN 2 R W e Interrupt Enable bit 1 Interrupt disable 1 Enable EP1_INT_EN 1 R W d Interrupt Enable bit 1 Interrupt disable 1 Enable EPO INT EN R W di Interrupt Enable bit 1 Interrupt disable 1 Enable Register Address Description Reset Value USB_INT_EN_REG 0x5200016C L R W Determine which interrupt is enabled 0x04 0x5200016F B byte RESET INT _ EN 2 R W 2 interrupt enable bit Interrupt disable 1 Enable REN 1 SUSPEND_INT_EN 0 R W nis interrupt enable bit Interrupt disable 1 Enable ELECTRONICS 13 9 USB DEVICE 53 2410 FRAME NUMBER REGISTER FPAME_NUM1_REG FRAME_NUM2_REG When the host transfers USB packets each Start Of Frame SOF packet includes a frame number The USB device controller catches this frame number and loa
166. 15 12 REDLUT 11 8 REDLUT 7 4 and REDLUT 3 0 are assigned to each red level The possible combination of 4 bits each field is 16 and each red level should be assigned to one level among possible 16 cases In other words the user can select the suitable red level by using this type of lookup table For green color the GREENVAL 31 0 of the GREENLUT register is assigned as the lookup table as was done in the case of red color Similarly the BLUEVAL 15 0 of the BLUELUT register is also assigned as a lookup table For blue color 2 bits are allocated for 4 blue levels different from the 8 red or green levels 4096 Level Color Mode Operation The S3C2410A LCD controller can support a 12 bit per pixel 4096 color display mode The color display mode can generate 4096 levels of color using the dithering algorithm and FRC The 12 bit per pixel are encoded into 4 bit for red 4 bit for green and 4 bit for blue The 4096 color display mode does not use lookup tables 15 6 ELECTRONICS 3C2410A LCD CONTROLLER DITHERING AND FRAME RATE CONTROL For STN LCD displays except monochrome video data must be processed by a dithering algorithm The DITHFRC block has two functions such as Time based Dithering Algorithm for reducing flicker and Frame Rate Control FRC for displaying gray and color level on the STN panel The main principle of gray and color level display on the STN panel based on FRC is described For example to display the third gray
167. 15 8 These 8 bits determine prescaler value for Timer 2 3 and 4 7 0 These 8 bits determine prescaler value for Timer 0 and 1 ELECTRONICS 10 11 PWM TIMER 3 2410 TIMER CONFIGURATION REGISTER1 TCFG1 TCFG1 0x51000004 5 MUX amp DMA mode selecton register 0x00000000 0000000 DMA mode 23 20 Select DMA request channel 0000 0000 No select all interrupt 0001 0010 Timer1 0011 Timer2 0100 Timer3 0101 Timer4 0110 Reserved MUX 4 19 16 Select MUX input for PWM Timer4 0000 0000 1 2 0001 1 4 0010 1 8 0011 1 16 01xx External TCLK1 3 15 12 Select MUX input for PWM Timers 0000 0000 1 2 0001 1 4 0010 1 8 0011 1 16 01xx External TCLK1 MUX 2 11 8 Select MUX input for PWM Timer2 0000 0000 1 2 0001 1 4 0010 1 8 0011 1 16 01xx External TCLK1 1 7 4 Select MUX input for PWM Timer 0000 0000 1 2 0001 1 4 0010 1 8 0011 1 16 01xx External TCLKO MUX 0 3 0 Select MUX input for PWM 0000 0000 1 2 0001 1 4 0010 1 8 0011 1 16 01xx External TCLKO 10 12 ELECTRONICS 53 2410 TIMER CONTROL TCON REGISTER PWM TIMER TCON Bit Description Timer 4 auto reload on off 22 Determine auto reload on off for Timer 4 0 One shot 1 Interval mode auto reload Timer 4 manual update note 21 Determine the manual update for Timer 4 0 operation 1 Update TCNTB4 Timer 4
168. 2 2 4 010 HCLK 2 48 MHz 4 4 8 011 EXTCLKor EXTCLKor EXTCLKor HCLK HCLK 2 48 MHz 6 XTIpII 6 12 100 EXTCLKor EXTCLKor EXTCLK or HCLK HCLK 2 48 MHz 8 XTIpII 8 16 101 EXTCLKor EXTCLKor EXTCLKor HCLK HCLK 2 48 MHz 10 10 20 110 EXTCLK or EXTCLKor HCLK HCLK 2 48 MHz 12 12 24 111 EXTCLK or EXTCLKor HCLK HCLK 2 48 MHz 14 14 28 In SLOW mode PLL will be turned off to reduce the PLL power consumption When the PLL is turned off in the SLOW mode and the user changes power mode from SLOW mode to NORMAL mode the PLL needs clock stabilization time PLL lock time This PLL stabilization time is automatically inserted by the internal logic with lock time count register The PLL stability time will take 150us after the PLL is turned on During PLL lock time the FCLK becomes SLOW clock ELECTRONICS 7 11 CLOCK amp POWER MANAGEMENT 53 2410 Users can change the frequency by enabling SLOW mode bit CLKSLOW register PLL on state SLOW clock is generated during the SLOW mode Figure 7 9 shows the timing diagram SLOW_BIT Slow mode enable Slow mode disable MP
169. 2 a3 a3 a3 a3 LSR 1 S loop2 al a4 ip ip ASL 1 a1 a1 0 a2 a2 0 Ir Justification stage shifts 1 bit at a time NB LSL 1 is always OK if LS succeeds ELECTRONICS 3C2410A THUMB INSTRUCTION SET DIVISION BY A CONSTANT Division by a constant can often be performed by a short fixed sequence of shifts adds and subtracts Here is an example of a divide by 10 routine based on the algorithm in the ARM Cookbook in both Thumb and ARM code Thumb Code 10 Take argument in a1 returns quotient in a1 remainder in a2 MOV a2 al LSR a3 al 2 SUB 1 LSR a3 al 4 ADD al a3 LSR a3 a1 8 ADD a1 a3 LSR a3 al 16 ADD al a3 LSR al 3 ASL a3 al 2 ADD a3 ASL 1 SUB a2 a3 CMP a2 10 BLT FTO ADD al 1 SUB a2 10 0 MOV Ir ARM Code 10 Take argument in a1 returns quotient in a1 remainder in a2 SUB a2 a1 10 SUB al al al Isr 2 ADD a1 al a1 Isr 4 ADD a1 a1 a1 Isr 8 ADD a1 al a1 Isr 16 MOV a1 a1 Isr 3 ADD a3 a1 a1 asl 2 SUBS a2 a2 a3 asl 1 ADDPL a1 a1 1 ADDMI a2 a2 10 MOV Ir ELECTRONICS 4 43 THUMB INSTRUCTION SET S3C2410A NOTES 4 44 ELECTRONICS 53 2410 MEMORY CONTROLLER OVERVIEW The S3C2410A s memory controller provides memory control signals required for external memory access The 3 2410 has the following features Little Big endian selectable by a software Addr
170. 2 EINT1 ARBITERO 4 REQ3 EINT2 4 REQ4 EINT3 ARBITER6 lt REQO EINT4_7 lt REQ1 EINT8 23 1 REQ2 reserved 4 lt TIMERO X REGZINT TIMER lt ARBITER2 REQ3 INT_TIMER3 REQ4 INT_TIMER4 lt UART2 ARM IRQ 4 REQO INT_LCD HEQ INT DMAT 4 amp ARBITERS 4 lt _ REQA INT DMA3 4 REQS INT_SDI REQO INT SPIO 4 EA reserve ARBITER4 4 USBD lt REQ4 INT USBH REQB INT REQ1 INT UARTO ARBITER5 lt REQ4 INT ADC Figure 14 2 Priority Generating Block 14 4 ELECTRONICS 3C2410A INTERRUPT CONTROLLER INTERRUPT PRIORITY Each arbiter can handle six interrupt requests based on the one bit arbiter mode control ARB_MODE and two bits of selection control signals ARB_SEL as follows If ARB SEL bits are 006 the priority order is REQ2 REQ3 REQ4 REQ5 If ARB_SEL bits are 016 the priority order is REQO REQ2 REQ3 REQ4 5 If ARB SEL bits are 10b the priority order is REQ3 REQ4 REQ2 and REQ5 If ARB SEL bits are 11b the priority order is REQO REQ4 REQ1 REQ2 REQ3 and 5 Note that REQO of an arbiter always has the highest priority and REQ5 has the lowest one In addition by changing the ARB_SEL bits we can rotate the priority of REQ1 to REQ4
171. 21 S3 C2410A 032007 USER S MANUAL 53 2410 200MHz amp 266MHz 32 Bit RISC Microprocessor Revision 1 1 ELECTRONICS S3C2410A 200MHz amp 266MHz 32 BIT RISC MICROPROCESSOR USER S MANUAL Revision 1 1 ELECTRONICS Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication Samsung assumes no responsibility however for possible errors or omissions or for any consequences resulting from the use of the information contained herein Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others Samsung makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation any consequential or incidental damages Typical parameters can and do vary in different applications All operating parameters including must be validated for each customer application by the cus
172. 22 21 20 19 18 17 16 NC 5 5 5 1 vb 23 22 21 20 19 18 17 16 15 14 13 12 RED 2 nc NOTE The unused VD pins can be used as GPIO ELECTRONICS 15 17 LCD CONTROLLER 53 2410 8BPP Display BSWP 0 HWSWP 0 LCD Panel 15 18 ELECTRONICS 3C2410A LCD CONTROLLER 4BPP Display BSWP 0 HWSWP 0 D22724 93 2 onone 512 m Pe Po Po P7 Ps PH Pi2 P Pis Pre _ Pz Po P Per __ 11114 41414 BSWP 1 HWSWP 0 DIS 2724 93 2 onone Pr Pe P5 pe Pe ae ee Ae nr j ee 12 0 12 22 4222 2BPP Display BSWP 0 HWSWP 0 ran mra 0624 ps22 nzagl mor Ps a Ps m D osa 332 mwa 0H P27 P28 P29 P30 L l1 Ad T L L T T ELECTRONICS 15 19 LCD CONTROLLER S3C2410A 256 PALETTE USAGE TFT Palette Configuration and Format Control The S3C2410A provides 256 color palette for TFT LCD Control The user can select 256 colors from the 64K colors in these two formats The 256 color palette consists of the 256 depth x 16 bit SPSRA
173. 24 2 Recommended Operating Conditions Parameter Rating Goomnz 2 DC Input Voltage 3 3V Input buffer 3 3 0 3 3 3V Interface 5V Tolerant 3 0 5 25 input buffer DC EM Voltage 3 3V ae buffer 83 03 30 3 Industrial 40 to 85 um ELECTRONICS 24 1 ELECTRICAL DATA S3C2410A D C ELECTRICAL CHARACTERISTICS Table 24 3 and 24 4 define the DC electrical characteristics for the standard LVCMOS buffers Table 24 3 Normal I O PAD DC Electrical Characteristics 3 3 0 3V T4 40 to 85 C Parameters Condition Type Max Unit High level input voltage Low level input voltage ee 8 VT jSwihigtresod 1 v Semitmggerpestwegongmeson emos vr rigger negative going threshold emos os v High level input current s Input buffer with pull up NOTES 1 B6 means 6mA output driver cell 2 Type B8 means 8mA output driver cell 3 Type B12 means 12mA output driver cells 24 2 ELECTRONICS 53 2410 ELECTRICAL DATA Table 24 4 USB DC Electrical Characteristics Symb Parameter Condition Unit e weena __ _ es v Table 24 5 S3C2410A Power Supply Voltage and Current Parameter zoome unt Cono Typical normal mode power NOTE 3 259 335 mW NOTE
174. 3 VD21 GPD13 I2SLRCK GPEO GPEO I2SSCLK GPE1 GPE1 e e e wssop vss P P T4 P4 N5 U4 6 R5 T5 P5 N6 U5 U6 6 N7 P7 R7 T7 U7 M7 N8 L7 M8 U8 T8 1 12 ELECTRONICS 3 2410 PRODUCT OVERVIEW Table 1 2 272 Pin FBGA Pin Assignments Continued Function BUS REQ nRESET N9 VDDOP VDDOP P t t L9 U9 T9 s3 P d3o dic t t 5 t i i i i i vsSam P M L P10 EINT18 GPG10 GPG10 J t d d t12 d B A A u u Al u u R14 s3 s3 A 8 8 8 8 o 3i 8 6 6 6 s s s s s s s s s o t 0 r1 ELECTRONICS 1 13 PRODUCT OVERVIEW S3C2410A Table 1 2 272 Pin FBGA Pin Assignments Continued MED omo zm Sa Function QBUS REQ PWR off nRESET ur Aw A ms m ______ _ u i no Pi5b VDAADCC P P R7 xroc O g Pi6 o RTVOD P P P Pi4 vobi mpi jvoiwer P P _ de _ JVSSMPLL Jvsswe
175. 3 10 xviii 3C2410A MICROPROCESSOR Table of Contents Concluded Appendix 3 MMU Continued Eevel TWO Deser s t nines ade ne cbe rd odd eee te ee a Translating Large Page Translating Small Page Translating Tiny Page SUD IU L Paasi MWMm Faults and CPU AbortS s a eint Fault Address and Fault Status Si octo pt a a NELLE med Sei UE DomalMmACCESS Fault Checking Pct EET Transla lon Fault ze etta peu eee nsi ir qua ati ne ud DELL opata REP TR Ye ER RR TI NR RA SEE External tette EE RO pie ei Acc LINDE p PLE Interaction of the MMU and Enabling the u u u y Disabling ii
176. 3C2410A INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 2 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES LSR R2 R5 27 Logical shift right the contents of R5 by 27 and store the result in R2 Set condition codes on the result 4 6 ELECTRONICS 3C2410A THUMB INSTRUCTION SET FORMAT 2 ADD SUBTRACT 15 14 13 12 11 10 9 8 6 5 3 2 0 o i i nosa 2 0 Destination Register 5 3 Source Register 8 6 Register Immediate Vale 9 Opcode 0 ADD 1 SUB 10 Immediate Flag 0 Register operand 1 Immediate oerand Figure 4 3 Format 2 OPERATION These instructions allow the contents of a Lo register or a 3 bit immediate value to be added to or subtracted from a Lo register The THUMB assembler syntax is shown in Table 4 3 NOTE All instructions in this group set the CPSR condition codes Table 4 3 Summary of Format 2 Instructions THUMB Assembler ARM Equipment ADD Rs Rn ADDS Rs Rn Add contents of Rn to contents of Rs Place result in Rd ADD Rs Offset3 ADDS Rs Offset3 Add 3 bit immediate value to contents of Rs Place result in Rd SUB Rs Rn SUBS Rs Rn Subtract contents of Rn from contents of Rs Place result in Rd 1 SUB Rs Offset3 SUBS Rd Rs Offset3 Subtract 3 bit immediate va
177. 410A UART UART FIFO CONTROL REGISTER There are three UART FIFO control registers including UFCONO UFCON1 and UFCON2 in the UART block Tx FIFO Trigger Level Determine the trigger level of transmit FIFO 00 Empty 01 4 byte 10 8 byte 11 12 byte Rx FIFO Trigger Level Determine the trigger level of receive FIFO 00 4 byte 01 8 byte 10 12 byte 11 16 byte mew Tx FIFO Reset 2 Auto cleared after resetting FIFO 0 Normal 1 Tx FIFO reset Rx FIFO Reset 1 Auto cleared after resetting FIFO 0 Normal 1 Rx FIFO reset FIFO Enable 0 0 Disable 1 Enable NOTE When the UART does not reach the FIFO trigger level and does not receive data during 3 word time in DMA receive mode with FIFO the Rx interrupt will be generated receive time out and the users should check the FIFO status and read out the rest ELECTRONICS 11 13 UART 53 2410 UART MODEM CONTROL REGISTER There are two UART MODEM control registers including UMCONO and UMCON1 in the UART block Reseved 00008000 o Reserved 7 5 These bits must be 0 s Auto Flow Control AFC 4 0 Disable 1 Enable Reserved 3 1 These bits must be 05 Request to Send If AFC bit is enabled this value will be ignored In this case the 53 2410 will control nRTS automatically If AFC bit is disabled nRTS must be controlled by software 0 H level Inactivate nRTS 1 L level Activate nRTS NOTE UART 2 does
178. 6 CPSRP EIBUS 3 26 INSTRUCTION muu tr ri uama RIS E es 3 26 otis cca se up onde contient 3 27 MEN M 3 27 3C2410A MICROPROCESSOR Table of Contents Continued Chapter 3 ARM Instruction set Continued Single Data Transfer LDR 56 3 28 Offsets And 3 29 Shifted Register 3 29 WOOS erar cts pasay ise get 3 29 OKNI 3 31 EI 3 31 Data ADOMS a EE 3 31 aite ne Aui 3 31 ASSOMIDISMS 3 32 EE 3 33 Halfword and Signed Data Transfer LDRH STRH LDRSB LDRSH sse 3 34 Offsets and 3 35 Halfword Load and 90 3 36 mu E EDI RE 3 37 Dat T ELLE 3 37 Instruction Cycle THITles a tco eee ta der e 3 37 mas DTI EIE 3 38 Examples iet e i m 3 39 Block Data Transfer 5 3 40 3 40
179. 6 clocks Tacc 10 8 Access cycle 111 000 1 clock 001 2 clocks 010 3 clocks 011 4 clocks 100 6 clocks 101 8 clocks 110 10 clocks 111 14 clocks NOTE When nWAIT signal is used Tacc 2 4 clocks PMC 1 0 Page mode configuration 00 normal 1 data 01 4 data 10 8 data 11 16 data ELECTRONICS 5 15 MEMORY CONTROLLER 53 2410 BANK CONTROL REGISTER BANKCONn nGCS6 nGCS7 BANKCON6 0x4800001C Bank 6 control register 0x18008 BANKCON7 0x48000020 Bank 7 control register 0x18008 MT 16 15 Determine the memory type for bank6 and bank7 00 ROM or SRAM 01 Reserved Do not use 10 Reserved Do not use 11 Sync DRAM Memory Type ROM or SRAM MT 00 15 bit Tacs 14 13 Address set up time before nGCS 00 Oclock 01 1 clock 10 2 clocks clocks Tcos 12 11 Chip selection set up time before nOE 00 0 01 1 clock 10 2 clocks clocks Tacc 10 8 Access cycle 000 1 clock 001 2 clocks 010 3 clocks 011 4 clocks 100 6 clocks 101 8 clocks 110 10 clocks 111 14 clocks Tcoh 7 6 Chip selection hold time after 00 0 clock 01 1 clock 10 2 clocks 11 4 clocks 5 4 Address hold time after nGCSn 00 0 01 clock 10 2clocks 11 4 clocks 3 2 mode access cycle Page mode 00 2 clocks 01 3 clocks 10 4 clocks 11 6 clocks PMC 1 0 Page mode configuration 00 normal 1 data 01 4 consecutive accesses 10 8 co
180. 7 The Wave form when a Dead Zone Feature is 10 9 10 8 Timer4 DMA Mode Operation U 10 10 11 1 UART Block Diagram With 11 2 11 2 UART AFG Interface pete ee eren ete Lene AMARE DR Rank ande o 11 4 11 3 UART Receiving 4 Characters with 1 Error 11 6 11 4 IrDA Function Block 11 8 11 5 Serial Frame Timing Diagram Normal 11 9 11 6 Infra Red Transmit Mode Frame Timing Diagram 11 9 11 7 Infra Red Receive Mode Frame Timing Diagram 11 9 11 8 nCTS and Delta CTS Timing 11 18 12 1 USB Host Controller Block Diagram sese 12 1 13 1 USB Device Controller Block 13 2 3C2410A MICROPROCESSOR xxiii List of Figures Continued Figure Title Page Number Number 14 1 Interrupt Process 14 1 14 2 Priority Generating Block a a 14 4 15 1 LCD Controller Block 4 n n an 15 3 15 2 Monochrome Display Types 6 44 200440 000 0000 a 15 11 15 3 Color Display Types 5 7 15 12 15 4 8
181. 7600 ELECTRONICS 15 33 LCD CONTROLLER S3C2410A RED Lookup Table Register REDLUT 0X4D000020 STN Red lookup table register 0x00000000 REDVAL 31 0 These bits define which of the 16 shades will be chosen by each of 0x00000000 the 8 possible red combinations 000 REDVAL 3 0 001 REDVAL 7 4 010 REDVAL 1 1 8 011 REDVAL 15 12 100 REDVAL 19 16 101 REDVAL 23 20 110 REDVAL 27 24 111 REDVAL 31 28 GREEN Lookup Table Register GREENLUT 0 40000024 R W 5 Green lookup table register 0 00000000 GREENVAL 31 0 These bits define which of the 16 shades will be chosen by each of 0x00000000 the 8 possible green combinations 000 GREENVAL 3 0 001 GREENVAL 7 4 010 GREENVAL 11 8 011 GREENVAL 15 12 100 GREENVAL 19 16 101 GREENVAL 23 20 110 GREENVAL 27 24 111 31 28 BLUE Lookup Table Register BLUELUT 0X4D000028 STN Blue lookup table register 0x0000 BLUEVAL 15 0 These bits define which of the 16 shades will be chosen by each of 0x0000 the 4 possible blue combinations 00 BLUEVALJ 3 0 01 7 4 10 BLUEVAL 11 8 11 BLUEVAL 15 12 NOTE Address from 0x4D00002C to 0x4D000048 should not be used This area is reserved for Test mode 15 34 ELECTRONICS 3C2410A LCD CONTROLLER Dithering Mode Register DITHMODE 0X4D00004C R W STN Dithering mode register 0x00000 This register reset value is 0x00000 But user can change this val
182. 8 0 15 2 0 V 0 1 V TA 40 to 85 3 3V 0 3V Parameter Symbol Condition Min Max Unit Supply Current Differential Input Sensitivity D D 0 2 V Single Ended Receiver Threshold Output Levels Differential Common Mode VCM Includes VDI range 2 5 Range 2 Static Output Low RL of 1 5Kohm to 3 6V 63 v Static Output High RL of 15Kohm to GND Capacitance 24 36 ELECTRONICS 53 2410 ELECTRICAL DATA Table 24 17 USB Full Speed Output Buffer Electrical Characteristics 1 8 0 15 2 0 V 0 1 V T4 40 to 85 C 3 3V 0 3V Parameter Symbol Condition min Max Unit Driver Characteristics _ O Driver Characteristics Transition Time Rise Time CL 50pF 4 0 2 0 Fall Time CL 4 0 2 0 ow x Output Signal Crossover VCRS i 2 0 Voltage Drive Output Resistance ZDRV Steady state drive Table 24 18 USB Low Speed Output Buffer Electrical Characteristics 1 8 0 15 2 0 V 0 1 V TA 40 to 85 3 3V 0 3V Parameter Symbor Condition Unit Driver Characteristics Transition Time Rising Time CL 50pF 75 ns CL 350pF 300 Falling Time CL 50pF 75 CL 350pF 300 Rise Fall Time Matching TRFM so 120 Output Signal Crossover VCRS 1 3 2 0 V Voltage ELECTRONICS 24 37 ELECTRICAL DATA S3C2410A Table 24 19
183. ABLE DISABLE On reset the entries are all invalidated and the is disabled The ICache is enabled by writing 1 to the bit and disabled by writing 0 to the Icr bit The is usually used with the MMU enabled in which case the bit in the relevant MMU translation table descriptor indicates whether an area of memory is cacheable If the ICache is enabled with the MMU disabled all instruction fetches are treated as cacheable When the is disabled the cache contents are ignored and all instruction fetches appear on the ASB as separate non sequential accesses NOTE ARM920T implements a non sequential access on the ASB as an A TRAN cycle followed by an S TRAN cycle It does not produce N TRAN cycles If the cache is subsequently re enabled its contents will be unchanged If the contents are no longer coherent with main memory the ICache should be invalidated prior to being enabled see Register 7 Cache operations on page 2 15 The MMU and can be enabled simultaneously by writing a 1 to bit 0 and to bit 12 in CP15 register 1 with a single MCR instruction INSTRUCTION CACHE OPERATION If the ICache is disabled each instruction fetch results in a separate non sequential memory access on the ASB giving very low performance to burst memory such as page mode DRAM or synchronous DRAM Therefore the ICache should be enabled as soon as possible after reset If the ICache is en
184. Alarm minute data register 0x00 0x5700005B B by byte m MINDATA 6 4 BCD value for alarm minute 0 5 8 0 0 0000 ALARM HOUR DATA ALMHOUR REGISTER ALMHOUR 0x5700005C L R W Alarm hour data register 0x0 0x5700005F B by byte e HOURDATA 5 4 BCD value for alarm hour a 0 2 3 0 0 000 ELECTRONICS 17 7 REAL TIME CLOCK RTC 83 2410 ALARM DATE DATA ALMDATE REGISTER ALMDATE 0x57000060 L R W Alarm date data register 0x01 0x57000063 B by byte p DATEDATA 5 4 BCD value for alarm date from 0 to 28 29 30 31 0 3 13 0 0 0001 ALARM MON DATA ALMMON REGISTER ALMMON 0x57000064 L R W Alarm month data register 0x01 0x57000067 B by byte p m MONDATA BCD value for alarm month WE i 8 0 0 0001 ALARM YEAR DATA ALMYEAR REGISTER ALMYEAR 0x57000068 L R W Alarm year data register 0x0 0x5700006B B by byte YEARDATA 7 0 BCD value for year 0x0 00 99 17 8 ELECTRONICS 3C2410A REAL TIME CLOCK RTC RTC ROUND RESET RTCRST REGISTER RTCRST 0x5700006C L R W RTC round reset register 0x0 0x5700006F B by byte SRSTEN 3 Round second reset enable 0 Disable 1 Enable SECCR 2 0 Round boundary for second carry generation 011 over than 30 sec 100 over than 40 sec 101 over than 50 sec NOTE If other values 0 1 2 6 or 7 are set no second carry
185. B_MODE2 2 Arbiter 2 group priority rotate enable 0 Priority does not rotate 1 Priority rotate enable 14 12 ELECTRONICS 53 2410 INTERRUPT CONTROLLER PRIORITY REGISTER PRIORITY Continued ARB_MODE1 Arbiter 1 group priority rotate enable 0 Priority does not rotate 1 Priority rotate enable Arbiter 0 group priority rotate enable 0 Priority does not rotate 1 Priority rotate enable ELECTRONICS 14 13 INTERRUPT CONTROLLER 53 2410 INTERRUPT PENDING INTPND REGISTER Each of the 32 bits in the interrupt pending register shows whether the corresponding interrupt request which is unmasked and waits for the interrupt to be serviced has the highest priority Since the INTPND register is located after the priority logic only one bit can be set to 1 and that interrupt request generates IRQ to CPU In interrupt service routine for IRQ you can read this register to determine which interrupt source is serviced among the 32 sources Like the SRCPND register this register has to be cleared in the interrupt service routine after clearing the SRCPND register We can clear a specific bit of the INTPND register by writing a data to this register It clears only the bit positions of the INTPND register corresponding to those set to one in the data The bit positions corresponding to those that are set to 0 in the data remains as they are INTPND 0 4 000010 R W Indicate the interrupt request status 0x0
186. C2410A NOTES 17 12 ELECTRONICS 3C2410A WATCHDOG TIMER WATCHDOG TIMER OVERVIEW The S3C2410A watchdog timer is used to resume the controller operation whenever it is disturbed by malfunctions such as noise and system errors It can be used as a normal 16 bit interval timer to request interrupt service The watchdog timer generates the reset signal for 128 PCLK cycles FEATURES Normal interval timer mode with interrupt request Internal reset signal is activated for 128 PCLK cycles when the timer count value reaches 0 time out ELECTRONICS 18 1 WATCHDOG TIMER 53 2410 WATCHDOG TIMER OPERATION Figure 18 1 shows the functional block diagram of the watchdog timer The watchdog timer uses only PCLK as its source clock The PCLK frequency is prescaled to generate the corresponding watchdog timer clock and the resulting frequency is divided again Interrupt 8 5 Prescaler Reset Signal Generator RESET Down Counter WTCON 15 8 WTCON 4 3 WTCON 2 WTCON O Figure 18 1 Watchdog Timer Block Diagram The prescaler value and the frequency division factor are specified in the watchdog timer control WTCON register Valid prescaler values range from 0 to 2 1 The frequency division factor can be selected as 16 32 64 or 128 Use the following equation to calculate the watchdog timer clock frequency and the duration of each timer clock Cycle t watchdog 1 PCLK Prescaler value
187. CLKOUT 1 0 Clock output signal The CLKSEL of MISCCR register configures the clock output mode among the MPLL CLK UPLL CLK FCLK HCLK and PCLK XTOpll AO Crystal Output for internal osc circuit When OM 3 2 00b is used for MPLL CLK source and UPLL CLK source When OM 3 2 01b XTIpll is used for MPLL CLK source only When OM 3 2 10b XTIpll is used for UPLL CLK source only If it isn t used it has to be a floating pin 1 24 ELECTRONICS 3 2410 PRODUCT OVERVIEW Table 1 3 S3C2410A Signal Descriptions Continued 53 2410 reset block and port status register 1 8V 2 0V It should be always supplied whether in normal mode or in power off mode VDDi VDDiarm P S3C241 core logic 1 8V 2 0V for CPU L ERE VODCWPLL P_ SSGRSTOAMPLL dial vooor IEEE MN 3 3V SCLK up to 133MHz ama vso e semos OO pesce RTC 1 8 V Not support 2 0 and 3 3V This pin must be connected to power Prope if RTC isn t used 52 analog and Vp S20 VSS UP P VDDA ADC P S3C2410A ADC 3 3V VSSA ADC P S3C2410A ADC Vss NOTES 1 means input output 2 means analog input analog output 3 ST means schmitt trigger 4 P means power ELECTRONICS 1 25 PRODUCT OVERVIEW 3 2410 3C2410A SPECIAL REGISTERS Table 1 4 S3C2410A Special R
188. CON GPGDAT and 9 17 Port H Control Registers GPHCON GPHDAT and a 9 19 Miscellaneous Control Register 9 20 Dclk Control Registers DCLKCONJ u 9 21 External Interrupt Control Register 9 22 External Interrupt Filter Register 9 25 External Interrupt Mask Register EINTMASK 9 26 External Interrupt Pending Register 9 27 General Status Register GSTATUSNJ U 9 28 x S3C2410A MICROPROCESSOR Table of Contents Continued Chapter 10 PWM Timer u anid dia 10 1 baat 10 1 PWM Lime Operation ca a a ves otn idest dta cem muyta SLE LM 10 3 DIVIdr i en e n aw E e una EO e 10 3 Basic as on cae mana 10 3 Auto Reload amp Double Buffering l L l n 10 4 Timer Initialization Using Manual Update Bit and Inverter 10 5 Jamer Operations as osi dn cohen ce ayama 10 6 Pu
189. CTRONICS ARM920T PROCESSOR CACHES WRITE BUFFER DATA CACHE AND WRITE BUFFER The ARM920T includes a 16KB data cache and a write buffer to reduce the effect of main memory bandwidth and latency on data access performance The DCache has 512 lines of 32 bytes 8 words arranged as a 64 way set associative cache and uses virtual addresses from the ARM9TDMI CPU core The write buffer can hold up to 16 words of data and 4 separate addresses The operation of the data cache and write buffer are intimately connected The DCache supports write through WT and writeback WB memory regions controlled by the C and B bits in each section and page descriptor within the MMU translation tables For clarity these bits are referred to as Ctt and Btt in the following text For details see Data cache and write buffer operation on page 4 6 Each DCache line has two dirty bits one for the first 4 words of the line the other for the last 4 words and a single virtual TAG address and valid bit for the entire 8 word line The physical address from which each line was loaded is stored in the PA TAG RAM and is used when writing modified lines back to memory A linefill always loads a complete 8 word line When a store hits in the DCache if the memory region is WB the associated dirty bit is set marking the appropriate half line as being modified If the cache line is replaced due to a linefill or if the line is the target of a DCache clean operation the dirty b
190. DATA TRANSFER LDRH STRH LDRSB LDRSH The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 16 These instructions are used to load or store half words of data and also load sign extended bytes or half words of data The memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register The result of this calculation may be written back into the base register if auto indexing is required 31 2827 25 24 23 22 21 20 19 1615 12 11 8 765 4 3 Io 3 0 Offset Register 6 5 S H 0 02 SWP instruction 0 1 2Unsigned halfword 1 1 byte 1 1 Signed halfword 15 12 Source Destination Register 19 16 Base Register 20 Load Store 0 Store to memory 1 Load from memory 21 Write back 0 No write back 1 Write address into base 23 Up Down 0 Down subtract offset from base 1 Up add offset to base 24 Pre Post Indexing 0 Post add subtract offset after transfer 1 Pre add subtract offset bofore transfer 31 28 Condition Field Figure 3 16 Halfword and Signed Data Transfer with Register Offset 3 34 ELECTRONICS 3C2410A ARM INSTRUCTION SET 28 27 25 24 23 22 21 20 19 1615 12 11 8 765 4 3 3 0 Immediate Offset Low Nibble 6 5 H 0 02 SWP instruction 0 1 Unsigned halfword 1 1 Signed byte 1 1 Signed
191. DMA FIFO 0x52000208 L R W EP1 DMA transfer FIFO counter base 0x00 0x5200020B B byte register EP2 DMA FIFO 0x52000220 L R W EP2 DMA transfer FIFO counter base 0x00 0x52000223 B byte register L oe mms EP3 DMA FIFO 0x52000248 L R W EP3 DMA transfer FIFO counter base 0x00 0x5200024B B byte register EP4 DMA FIFO 0x52000260 L R W EP4 DMA transfer FIFO counter base 0x00 0x52000263 B byte register DMA_FIFO Bit MCU USB Description Initial State EPn FIFO 7 0 RW R EPDMAtransfer FIFO counter value ELECTRONICS 13 23 USB DEVICE 53 2410 DMA TOTAL TRANSFER COUNTER REGISTER L M H This register should have total number of bytes to be transferred using total 20 bit counter RW Reset Value EP1 DMA TTC L 0x5200020C L R W DMA total transfer counter lower byte 0x00 0x5200020F B byte TTC M 0x52000210 L R W DMA total transfer counter middle byte 0x00 0x52000213 B byte EP1 DMA TTC H 0x52000214 L R W EP1 DMA total transfer counter higher byte 0x00 0x5200021 7 B byte EP2 DMA TTC L 0x52000224 L R W EP2 DMA total transfer counter lower byte 0x00 0x52000227 B byte EP2 DMA TTC M 0x52000228 L R W EP2 DMA total transfer counter middle byte 0x00 0x5200022B B byte EP2 TTC H 0x5200022C L R W EP2 DMA total transfer counter higher byte 0x00 0x5200022F B byte
192. ECNT VFRAME VM VLINE VCLK VD 7 0 Figure 15 4 8 bit Single Scan Display Type STN LCD Timing 15 14 ELEGTRONEGS 3C2410A LCD CONTROLLER TFT LCD CONTROLLER OPERATION The TIMEGEN generates the control signals for LCD driver such as VSYNC HSYNC VCLK VDEN and LEND signal These control signals are highly related with the configurations on the LCDCON1 2 3 4 5 registers in the REGBANK Base on these programmable configurations on the LCD control registers in the REGBANK the TIMEGEN can generate the programmable control signals suitable for the support of many different types of LCD drivers The VSYNC signal is asserted to cause the LCD s line pointer to start over at the top of the display The VSYNC and HSYNC pulse generation depends on the configurations of both the HOZVAL field and the LINEVAL field in the LCDCON2 3 registers The HOZVAL and LINEVAL can be determined by the size of the LCD panel according to the following equations HOZVAL Horizontal display size 1 LINEVAL Vertical display size 1 The rate of VCLK signal depends on the CLKVAL field in the LCDCON1 register Table 15 3 defines the relationship of VCLK and CLKVAL The minimum value of CLKVAL is 0 VCLK Hz HCLK CLKVAL 1 x2 The frame rate is VSYNC signal frequency The frame rate is related with the field of VSYNC VBPD VFPD LINEVAL HSYNC HBPD HFPD HOZVAL and CLKVAL in LCDCON1 and LCDCON2 3 4 registers Most LCD drivers need their own ade
193. EINT19 11 TCLK1 GPG10 21 20 00 Input 01 Output 5V Tolerant Input 10 EINT18 11 Reserved GPG9 19 18 00 Input 01 Output 5V Tolerant Input 10 EINT17 11 Reserved GPG8 17 16 00 Input 01 Output 5V Tolerant Input 10 EINT16 11 Reserved GPG7 15 14 00 Input 01 Output 10 EINT15 11 SPICLK1 GPG6 13 12 00 Input 01 Output 10 EINT14 11 SPIMOSI1 GPG5 11 10 00 Input 01 Output 10 EINT13 11 SPIMISO1 GPG4 00 Input 01 Output 10 EINT12 11 LCD PWREN GPG3 7 6 00 Input 01 Output 10 EINT11 11 nSS1 GPG2 5 4 00 Input 01 Output 10 EINT10 11 550 GPG1 3 2 00 Input 01 Output 10 EINT9 11 Reserved GPGO 1 0 00 Input 01 Output 10 EINT8 11 Reserved 79 ELECTRONICS 9 17 PORTS 53 2410 GPGDAT Bit GPG 15 0 15 0 When the port is configured as input port data from external sources can be read to the corresponding pin When the port is configured as output port data written in this register can be sent to the corresponding pin When the port is configured as functional pin undefined value will be read Gus B GPG 15 0 15 0 0 The pull up function attached to to the corresponding port pin is enabled 1 The pull up function is disabled GPG 15 11 are pull up disabled state at the initial condition 9 18 ELECTRONICS 3 2410 PORTS PORT H CONTROL REGISTERS GPHCON
194. EQ to be asserted Handshake Mode If XnXDREQ is deasserted DMA deasserts XnXDACK in 2cycles Otherwise it waits until XnXDREQ is deasserted CAUTION XnXDREQ has to be asserted low only after the deassertion high of XnXDACK Demand Mode XnXDREQ XnXDACK Double synch Handshake Mode XnXDREQ Read Write XnXDACK 14 po Double synch Figure 8 2 Demand Handshake Mode Comparison 8 4 ELECTRONICS 3C2410A DMA Transfer Size There are two different transfer sizes unit and Burst 4 DMA holds the bus firmly during the transfer of the chunk of data Thus other bus masters cannot get the bus Burst 4 Transfer Size Four sequential Reads and Writes are performed respectively in the Burst 4 Transfer NOTE Unit Transfer size One read and one write are performed 1 I 1 I I 1 1 I 1 1 I xo ___ d d i f o P o d I I I I I 1 I 1 I I I I I 1 1 gt XnXDACK 1 Double synch Read Read Read Read Write Write Write Write 1 1 Figure 8 3 Burst 4 Transfer Size ELECTRONICS 8 5 DMA S3C2410A EXAMPLES Single service in Demand Mode with Unit Transfer Size The assertion of XnXDREQ is need for every unit transfer Single service mode The operation continues while the XnXDREQ is asserted Demand mode and one pair of Read and Write Single transfer size is performed XnXDREQ XnXDACK Double synch
195. ET ASSEMBLER SYNTAX S3C2410A Items in are optional Items in lt gt must be present B L cond lt expression gt L lt expression gt Examples here BAL CMP BEQ ADDS 3 8 Used to request the Branch with Link form of the instruction If absent R14 will not be affected by the instruction A two character mnemonic as shown in Table 3 2 If absent then AL ALways will be used The destination The assembler calculates the offset here Assembles to OXEAFFFFFE note effect of PC offset there Always condition used as default R1 0 Compare R1 with zero and branch to fred if R1 was zero otherwise continue fred Continue to next instruction sub ROM Call subroutine at computed address R1 1 Add 1 to register 1 setting CPSR flags the result then call subroutine if sub flag is clear which will be the case unless R1 OxFFFFFFFF ELECTRONICS 3C2410A ARM INSTRUCTION SET DATA PROCESSING The data processing instruction is only executed if the condition is true The conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 4 28 27 26 25 24 21 20 19 16 15 12 11 0 5 15 12 Destination register 0 Branch 1 Branch with link 19 16 1st operand register 0 Branch 1 Branch with link 20 Set condition codes 0 Do not after condition codes 1 Set condition codes 24 21
196. FIFO data lt 15 byte 1 Full Tx FIFO Count 7 4 Number of data in Tx FIFO Rx FIFO Count 3 0 Number of data in Rx FIFO Tx FIFO Full Set to 1 automatically whenever transmit FIFO is full during transmit operation 0 0 byte lt Tx FIFO data lt 15 byte 1 Full Set to 1 automatically whenever receive FIFO is full during receive operation ELECTRONICS 11 17 UART 53 2410 UART MODEM STATUS REGISTER There are two UART modem status registers including UMSTATO and UMSTAT1 in the UART block 00000016 UART Modem oo 060040 UART channel 1 Modem stats register ea Delta CTS 4 Indicate that the nCTS input to the 53C2410A has changed state since the last time it was read by CPU Refer to Figure 11 8 0 Has not changed 1 Has changed Clear to Send 0 CTS signal is not activated nCTS is high 1 CTS signal is activated nCTS pin is low Delta CTS Read UMSTAT Figure 11 8 nCTS and Delta CTS Timing Diagram 11 18 ELECTRONICS 3C2410A UART UART TRANSMIT BUFFER REGISTER HOLDING REGISTER amp FIFO REGISTER There are three UART transmit buffer registers including UTXHO UTXH1 and UTXH2 in the UART block UTXHn has 8 bit data for transmission data UTXHO 0x50000020 L UART channel 0 transmit buffer register 0x50000023 B by byte UTXH1 0x5000402
197. Flash Mode Figure 6 2 NAND Flash Operation Scheme ELECTRONICS 53 2410 FLASH CONTROLLER AUTO BOOT MODE SEQUENCE Reset is completed When the auto boot mode is enabled the first 4 KBytes of NAND flash memory is copied onto Steppingstone 4 KB internal buffer The Steppingstone is mapped to nGCSO CPU starts to execute the boot code on the Steppingstone 4 KB internal buffer NOTE In the auto boot mode ECC is not checked So The first 4 KBytes of NAND flash should have no bit error NAND FLASH MODE CONFIGURATION Set NAND flash configuration by register Write NAND flash command onto NFCMD register Write NAND flash address onto NFADDR register Read Write data while checking NAND flash status by NFSTAT register R nB signal should be checked before read operation or after program operation NAND FLASH MEMORY TIMING I CLE ALE i TACLS TWRPHO Figure 6 3 TACLS 0 TWRPHO 1 TWRPH1 0 ELECTRONICS 6 3 NAND FLASH CONTROLLER S3C2410A PIN CONFIGURATION D 7 0 Data Command Address In Out Port shared with the data bus CLE Command Latch Enable Output ALE Address Latch Enable Output nFCE NAND Flash Chip Enable Output nFRE NAND Flash Read Enable Output nFWE NAND Flash Write Enable Output R nB NAND Flash Ready nBusy Input BOOT AND NAND FLASH CONFIGURATIONS 1 9 00b Enable NAND flash controller auto boot mode NAND flash
198. G 15 20 Samsung TFT LCD Panel 3 5 Portrait 256k Color Reflective A SI TFT LCD 15 23 Virtual Display ER 15 24 LCD Power Enable aa 15 25 LCD Controller Special Registers a s sus 15 26 Frame Buffer Start Address 1 15 32 S3C2410A MICROPROCESSOR xiii Table of Contents Continued Chapter 16 ADC amp Touch Screen Interface OVeLVIOW oer Elo D 16 1 REEE oma Y MN UE 16 1 ADC 8 Touch Screen Interface 16 2 Bioteh ER 16 2 Example for Touch 16 3 Function Descriptions eret eee eed eeu EE 16 4 ADC and Touch Screen Interface Special Registers 16 7 ADC Control ADCCON 16 7 ADC Touch Screen Control ADCTSC Register 4 enne 16 8 ADC Start Delay ADCDLY 16 9 ADC Conversion Data ADCDATO 16 10 ADC Conversion Data ADCDAT1 Register
199. G CMP MUL R4 R1 RO R5 R3 R2 R6 RO R7 R3 R3 EOR R4 and set condition codes Rotate Right R1 by the value in RO store the result in R1 and set condition codes Subtract the contents of R3 from zero Store the result in R5 Set condition codes ie R5 R3 Set the condition codes on the result of R2 R6 RO R7 RO and set condition codes ELECTRONICS 3C2410A THUMB INSTRUCTION SET FORMAT 5 HI REGISTER OPERATIONS BRANCH EXCHANGE 9 14 11 CISPISDISI e w e 2 0 Destination Register 5 3 Source Register 6 Hi Operand Flag 2 7 Hi Operand Flag 1 9 8 Opcode Figure 4 6 Format 5 OPERATION There are four sets of instructions in this group The first three allow ADD CMP and MOV operations to be performed between Lo and Hi registers or a pair of Hi registers The fourth BX allows a Branch to be performed which may also be used to switch processor state The THUMB assembler syntax is shown in Table 4 6 NOTE In this group only CMP Op 01 sets the CPSR condition codes The action of H1 0 H2 0 for Op 00 ADD Op 01 CMP and Op 10 MOV is undefined and should not be used Table 4 6 Summary of Format 5 Instructions THUMB assembler ARM equivalent ADD Rd Hs ADD Hs a register the range 8 15 to a register in the range 0 7 ADD Hd Rs ADD Hd Rs Add a register in the range 0 7 toa mga in the range 8 15
200. IEW Table 1 4 S3C2410A Special Registers Continued m B Endian L Endian rite B R W EP2 DMA Interface Control EP2 DMA Total Tx Counter EP2 DMA Total Tx Counter EP2 DMA Total Tx Counter EP3 DMA Interface Control EP3_DMA_UNIT 0x52000247 0 52000244 DMA Tx Unit Counter EP3 DMA Total Tx Counter EP3 DMA Total Tx Counter EP3 DMA Total Tx Counter EP4 DMA Interface Control EP4 DMA Total Tx Counter EP4 DMA Total Tx Counter EP4 DMA Total Tx Counter Watchdog Timer WTCON 0x53000000 R W Watchdog Timer Mode WTDAT 0x53000004 Watchdog Timer Data WTCNT 0x53000008 Watchdog Timer Count w w ELECTRONICS 1 3 PRODUCT OVERVIEW Register Name GPACON GPADAT GPBCON GPBDAT GPBUP GPCCON GPCDAT GPCUP GPDCON GPDDA1T GPDUP GPECON GPEDAT GPEUP GPFCON GPFDAT GPFUP GPGCON GPGDAT GPGUP GPHCON GPHDAT GPHUP MISCCR DCLKCON EXTINTO EXTINT1 EXTINT2 EINTFLTO EINTFLT1 EINTFLT2 EINTFLT3 EINTMASK EINTPEND GSTATUSO GSTATUS1 Address mea a Endian L Endian 0x56000000 0x56000004 0x56000010 0x56000014 0x56000018 0x56000020 0x56000024 0x56000028 0x56000030 0x56000034 0x56000038 0x56000040 0 56000044 0 56000048 0 56000050 0 56000054 0 56000058 0 56000060 0 56000064 0 56000068 0 56000070 0 56000074 0 56000078 0 56000080 0 56000084 0 56000088 0x5600008C 0x56000090 0 56000094 0 56000098 0x5600009C 0 560000 0 0 560000 4
201. LL_OFF FCLK Divided external clock It changes to PLL clock after slow mode off Figure 7 9 Issuing Exit from Slow mode Command PLL on State If the user switches from SLOW mode to Normal mode by disabling the SLOW BIT in the CLKSLOW register after PLL lock time the frequency is changed just after SLOW mode is disabled Figure 7 10 shows the timing diagram Software lock time SLOW_BIT a Slow mode enable Slow mode disable OFF PLLoff PLL on FCLK Divided OSC clock It changes to PLL clock after slow mode off Figure 7 10 Issuing Exit from Slow mode Command After Lock Time 7 12 ELECTRONICS 3 2410 CLOCK amp POWER MANAGEMENT If the user switches from SLOW mode to Normal mode by disabling SLOW_BIT and MPLL_OFF bit simultaneously in the CLKSLOW register the frequency is changed just after the PLL lock time Figure 7 11 shows the timing diagram Hardware lock time 4 Mpll SLOW BIT Slow mode enable Slow mode disable MPLL OFF PLL off on FCLK Divided It changes to PLL clock OSC clock after lock time automatically Figure 7 11 Issuing Exit from Slow mode Command and the Instant PLL on Command Simultaneously ELECTRONICS 7 13 CLOCK amp POWER MANAGEMENT S3C2410A Power_OFF Mode The block disconnects the internal power So there occurs no power consumption due to CPU and the internal logic except the wake up logi
202. LLs one for FCLK HCLK and PCLK and the other dedicated for USB block 48MHz The clock control logic can make slow clocks without PLL and connect disconnect the clock to each peripheral block by software which will reduce the power consumption For the power control logic the 53 2410 has various power management schemes to keep optimal power consumption for a given task The power management block in the 53 2410 can activate four modes NORMAL mode SLOW mode IDLE mode and Power_OFF mode NORMAL mode the block supplies clocks to CPU as well as all peripherals in the S8C2410A In this mode the power consumption will be maximized when all peripherals are turned on It allows the user to control the operation of peripherals by software For example if a timer is not needed the user can disconnect the clock to the timer to reduce power consumption SLOW mode Non PLL mode Unlike the Normal mode the Slow mode uses an external clock or EXTCLK directly as FCLK in the 53 2410 without PLL In this mode the power consumption depends the frequency of the external clock only The power consumption due to PLL is excluded IDLE mode the block disconnects clocks FCLK only to the CPU core while it supplies clocks to all other peripherals The IDLE mode results in reduced power consumption due to CPU core Any interrupt request to CPU can be woken up from the Idle mode Power OFF mode the block disconnects the intern
203. M The palette supports 5 6 5 R G B format and 5 5 5 1 R G B 1 format When the user uses 5 5 5 1 format the intensity data l is used as a common LSB bit of each RGB data So 5 5 5 1 format is the same R 5 l G 5 B 5 l format In 5 5 5 1 format for example the user can write the palette as in Table 15 5 and then connect VD pin to TFT LCD panel R 5 I VD 23 19 VD 18 VD 10 or VD 2 G 5 I VD 15 11 VD 18 VD 10 VD 2 B 5 1 VD 7 3 VD 18 VD 10 VD 2 and set FRM565 of LCDCONS5 register to 0 Table 15 4 5 6 5 Format Pos ws 5 4 2 1 o mres note1 om ra as Ge ae 52 aa anoo Exec pisse a ra ro as Ge as 62 as 52 52 os ao number ove ss 22 Table 15 5 5 5 5 1 Format moeren Pos ss gt s s s 2 5 o mms o mre 64 es ce as ao aa 21 1 ra re ao 21 1 0 40000404 I lll re mro m r0 ae 61 52 1 ss 2 21 20 5 5
204. M booting ROM NOTE SFR means Special Function Register Figure 6 4 NAND Flash Memory Mapping ELECTRONICS 6 5 NAND FLASH CONTROLLER 53 2410 SPECIAL FUNCTION REGISTERS NAND FLASH CONFIGURATION NFCONF REGISTER 0x4E000000 NAND flash configuration Enable Disable NAND flash controller enable disable 0 Disable NAND Flash Controller 1 Enable NAND Flash Controller After auto boot this bit is cleared to 0 automatically For the access to the NAND flash memory this bit must be set Initialize ECC Initialize ECC decoder encoder 0 Not initialize ECC 1 Initialize ECC S3C2410A supports only 512 Byte ECC checking so it is required to set ECC initialization per 512 Bytes NAND Flash Memory NAND flash memory nFCE control chip enable 0 NAND flash L active 1 NAND flash nFCE H inactive After auto boot nFCE will be inactive TACLS 10 8 CLE amp ALE duration setting value 0 7 Duration HCLK TACLS 1 TWRPHO 6 4 TWRPHO duration setting value 0 7 Duration HCLK TWRPHO 1 TWRPH1 2 0 TWRPH1 duration setting value 0 7 Duration HCLK TWRPH1 1 6 6 ELECTRONICS 3C2410A NAND FLASH CONTROLLER NAND FLASH COMMAND SET NFCMD REGISTER NFCMD 0x4E000004 NAND flash command set register 007 mss 7 0 NAND flash memory command value NAND FLASH ADDRESS SET NFADDR REGISTER NFADDR 0
205. MA mode 2 Check the value of Rx FIFO count in UFSTATn register If the value is less than 15 users have to set the value of 0 to 1 activating nRTS and if it is equal or larger than 15 users have to set the value to 0 inactivating nRTS 3 Repeat the Step 2 Tx operation with FIFO 1 Select transmit mode Interrupt or DMA mode 2 Check the value of UMSTATn O If the value is 1 activating nCTS users write the data to Tx FIFO register 11 4 ELECTRONICS 53 2410 UART RS 232C interface If users want to connect the UART to modem interface instead of null modem nRTS nCTS nDSR nDTR DCD and nRI signals are needed In this case the users can control these signals with general I O ports by software because the AFC does not support the RS 232C interface Interrupt DMA Request Generation Each UART of the S3C2410A has five status Tx Rx Error signals Overrun error Frame error Receive buffer data ready Transmit buffer empty and Transmit shifter empty all of which are indicated by the corresponding UART status register UTRSTATn UERSTATn The overrun error and frame error are referred to as the receive error status each of which can cause the receive error status interrupt request if the receive error status interrupt enable bit is set to one in the control register UCONn When a receive error status interrupt request is detected the signal causing the request can be identified by reading the v
206. MA_FIFO 0x248 L 0x24 TTC 1 Ox24C L 0x24 EP3 DMA TTC M Endpoint3 DMA transfer counter middle byte register 0x250 L 0x253 EP3 DMA TTC H 0x254 L 0x247 B EP4 DMA CON 0x258 L 0x25 EP4 DMA UNIT Endpoint4 DMA unit counter register Ox25C L 0x25 EP4 DMA FIFO Endpoint4 DMA FIFO counter register 0x260 L 0x263 4 TTC 0x264 L 0x26 EP4 DMA TTC M Endpoint4 DMA transfer counter middle byte register 0x268 L 0 26 4 TTC Endpoint4 DMA transfer counter high byte register Ox26C L Ox26F B COMMON INDEXED REGISTERS MAXP_REG Endpoint MAX packet register 0x180 L 0x183 B IN INDEXED REGISTERS IN_CSR1_REG EP0O_CSR Endpoint3 DMA control register UJ Endpoint3 DMA unit counter register Endpoint3 DMA FIFO counter register Endpoint3 DMA transfer counter low byte register T5 5 5 5 D Endpoint3 DMA transfer counter high byte register E s Endpoint4 DMA control register an v g 00 Ped E Endpoint4 DMA transfer counter low byte register 2 J Wm KS EP In control status register 1 EP0 control status 0x184 L 0x187 B register EP In control status register 2 0x188 L 0x18B B IN CSR2 REG OUT INDEXED REGISTERS OUT CSR1 REG OUT CSR2 REG OUT FIFO CNT1 REG OUT FIFO CNT2 REG L L L L 0x193 0x197 Ox19B Oxi9F B B B B EP out control stat
207. MON 17 8 Alarm Year Data ALMYEAR 17 8 RTC Round Reset RTCRST Register 17 9 BCD Second snnt intrent 17 9 BCD BCDMIN 17 9 BED Hour BGDHODUR Register 5 tat ee uuu aaah addin 17 10 BED Date BCDDATE Register e eee leaned itr y 17 10 BED Day BGDDAY Register tian tii aee o ee terere dean 17 10 BCD Month BCDMON Register ua a uu a aa paaa neea aeae ua aaa 17 11 BCD Year BCDYEAR Register S3C2410A MICROPROCESSOR Table of Contents Continued Chapter 18 WatchDog Timer SM MI ER IE EI RE MEE TEM 18 1 gute EMIT 18 1 Watchdog Timer 18 2 Cen 18 2 Consideration of Debugging Environment ener nennen 18 2 Watchdog Timer Special 18 3 Watchdog Timer Control WTCON Register U n nennen 18 3 Watchdog Timer Data WTDAT 18 4 Watchdog Timer Count WTCNT
208. NAND Flash Interface Timing Constants Vppi V DDalive V DDiarm 1 8V 0 15 2 0 V 0 1 40 to 85 C Vppio 3 3V 0 3V Parameter Symbo Min Uni tm m NFCON Write Enable delay Read Data Setup requirement time ts 03 m Read Data Hold requirement ten 03 m NNNM S 1 2 2 24 38 ELECTRONICS 53 2410 MECHANICAL DATA MECHANICAL DATA PACKAGE DIMENSIONS o 2 o c z 0 35 0 05 TOLERANCE 0 10 Figure 25 1 272 FBGA 1414 Package Dimension 1 Top View ELECTRONICS 25 1 MECHANICAL DATA S3C2410A 10 Q H 99 ai s I C 20022 gt 272 0 45 0 05 iz os TOLERANCE 0 10 Figure 25 2 272 FBGA 1414 Package Dimension 2 Bottom View The recommended land open size is 390 410 um 0 39 0 41mm diameter 25 2 ELECTRONICS ARM920T PROCESSOR INTRODUCTION Appendix 1 ARM920T INTRODUCTION ABUOT THE INTRODUCTION The ARM920T is a member of the ARM9TDMI family of general purpose microprocessors which includes ARM9TDMI ARM9TDMI core ARM940T ARM9TDMI core plus cache and protection unit ARM920T ARM9TDMI core plus cache
209. NC pulse s high 0X00 level width by counting the number of the VCLK WLH STN STN WLH 1 0 bits determine the VLINE pulse s high level width by counting the number of the HCLK WLH 7 2 are reserved 00 16 HCLK 01 32 HCLK 10 48 HCLK 11 64 HCLK ELECTRONICS 15 29 LCD CONTROLLER S3C2410A LCD Control 5 Register LCDCON5 0X4D000010 LCD control 5 register 0x00000000 31 17 This bit is reserved and the value should be 0 VSTATUS 16 15 TFT Vertical Status read only 00 VSYNC 01 BACK Porch 10 ACTIVE 11 FRONT Porch HSTATUS 14 13 TFT Horizontal Status read only 00 HSYNC 01 BACK Porch 10 ACTIVE 11 FRONT Porch BPP24BL 12 TFT This bit determines the order of 24 bpp video memory 0 LSB valid 1 MSB Valid FRM565 11 TFT This bit selects the format of 16 bpp output video data 0 5 5 5 1 Format 1 5 6 5 Format STN TFT This bit indicates the VLINE HSYNC pulse polarity 0 Normal INVVLINE 1 Inverted INVVFRAME STN TFT This bit indicates the VFRAME VSYNC pulse polarity 0 Normal 1 Inverted INVVD 7 STN TFT This bit indicates the VD video data pulse polarity 0 Normal 1 VD is inverted INVVCLK 10 STN TFT This bit controls the polarity of the VCLK active edge 0 The video data is fetched at VCLK falling edge 1 The video data is fetched at VCLK rising edge 15 30 ELECTRONICS 3C2410A LCD CONTROLLER LCD Control 5 Register Continued INVVDEN TFT T
210. NSTRUCTION CYCLE TIMES This instruction format does not have an equivalent ARM instruction Table 4 20 The BL Instruction 1 temp next instruction address LR OffsetLow lt lt 1 LR temp 1 EXAMPLES BL faraway Unconditionally Branch to faraway next and place following instruction address ie next in R14 the Link register and set bit 0 of LR high Note that the THUMB opcodes will contain the number of halfwords to offset faraway Must be Half word aligned ELECTRONICS 4 39 THUMB INSTRUCTION SET 53 2410 INSTRUCTION SET EXAMPLES The following examples show ways in which the THUMB instructions may be used to generate small and efficient code Each example also shows the ARM equivalent so these may be compared MULTIPLICATION BY A CONSTANT USING SHIFTS AND ADDS The following shows code to multiply by various constants using 1 2 or 3 Thumb instructions alongside the ARM equivalents For other constants it is generally better to use the built in MUL instruction rather than using a sequence of 4 or more instructions Thumb ARM 1 Multiplication by 2 n 1 2 4 8 LSL Ra Rb LSL n MOV Ra Rb LSL n 2 Multiplication by 24n 1 3 5 9 17 LSL Rt Rb n ADD Ra Rb Rb LSL n ADD Ra Rt Rb 3 Multiplication by 2 1 3 7 15 LSL Rt Rb n RSB Ra Rb Rb LSL n SUB Ra Rt Rb 4 Multiplication by 2An 2 4 8 LSL Ra Rb n MOV Ra Rb
211. Note that division factor is N 1 when the prescaler value is N NOTE ADC frequency should be set less than PCLK by 5 times Ex 10 2 ADC Frequency lt 2 2 5 3 Analog input channel select 000 0 001 AIN 1 010 AIN 2 011 100 4 101 5 110 6 111 7 XP 2 Standby mode select 1 SEL_MUX M READ A D conversion start by read START 0 Disable start by read operation 1 Enable start by read operation ENABLE A D conversion starts by setting this bit START If READ START is enabled this value is not valid 0 No operation 1 A D conversion starts and this bit is cleared after the start up 0 Normal operation mode 1 Standby mode ELECTRONICS 16 7 ADC AND TOUCH SCREEN INTERFACE S3C2410A ADC TOUCH SCREEN CONTROL ADCTSC REGISTER ADCTSC 0x58000004 ADC touch screen control register 0x058 This bit should be zero Select output value of YMON 0 YMON output is 0 YM Hi Z 1 YMON output is 1 YM GND ADCTSC Reserved YM_SEN YP_SEN Select output value of nYPON 0 nYPON output is 0 YP External voltage 1 nYPON output is 1 YP is connected with AIN 5 XP_SEN Pull up switch enable 0 XP pull up enable 1 XP pull up disable Automatically sequencing conversion of X position and Y position PULL_UP AUTO_PST 0 Normal ADC conversion 1 Auto Sequential X Y Position Conversion Mode XY_PST 1 0 Man
212. O QUO OD XO X WT OUO ODDO EOD OG OO Qu XQ O OO Uu D OXIDE X U OX OO GO QOO OQ XO O0 0 X QUOD D qo EO o L l COD OU DOO OOO OC Oro QI CONO OO OD DC ODD EOD GO DO OO o QOO XO OOO xv OX x QUO OG EVO OD OX OO QOO XI DOO OU EH SO QOO DO UD SUDO O O O O O O O O O O O O O O O O OO ere O O e O O O e O O O O O O O O O O O O O O O O QOO O OG 1 OOO OOO 15 16 17 BOTTOM VIEW Figure 1 2 S3C2410A Pin Assignments 272 FBGA 3 2410 ELECTRONICS 3 2410 PRODUCT OVERVIEW Table 1 1 272 Pin FBGA Pin Assignments Pin Number Order A3 DATA16 B16 nBE1 nWBE1 DQM1 D12 ADDR10 8s DT ADDRMGPAS os pae o ppo o oje N ELECTRONICS 1 7 PRODUCT OVERVIEW S3C2410A Table 1 1 272 Pin FBGA Pin Assignments Pin Number Order Continued F8 VSSMOP H6 TCK K15 TXDO GPH2 amp roca J vsem us VSO tv G 0 O N AJOJN z 1 8 ELECTRONICS 3 2410 PRODUCT OVERVIEW Table 1 1 272 Pin FBGA Pin Assignments Pin Number Order Continued pe SPICLKOIGPETS po M13 VSSi MPLL P10 EINT18 GPG10 T7 SPIMISO0 GPE11 po m amp
213. O causing its oscillation frequency to increase or decrease linearly as a function of variations in average voltage When the Fvco matches Fref in terms of frequency as well as phase the PFD stops sending control signals to the charge pump which in turn stabilizes the input voltage to the loop filter The VCO frequency then remains constant and the PLL remains fixed onto the system clock Usual Conditions for PLL amp Clock Generator PLL amp Clock Generator generally uses the following conditions Loop filter capacitance External X tal frequency 10 20 MHz note External capacitance used for X tal 15 22 pF 5 1 The value could be changed 2 must be more than three times X tal or EXTCLK 2 3X tal or 7 4 ELECTRONICS 3 2410 CLOCK amp POWER MANAGEMENT MPLLCAP UPLLCAP Fret Loop Filter P 5 0 Fvco Divider M 7 0 Internal External Divider SI1 0 MPLL UPLL Figure 7 2 PLL Phase Locked Loop Block Diagram External OSC a X TAL Oscillation OM 3 2 00 b External Clock Source OM 3 2 11 Figure 7 3 Main Oscillator Circuit Examples ELECTRONICS 7 5 CLOCK amp POWER MANAGEMENT 83 2410 CLOCK CONTROL LOGIC The clock control logic determines the clock source to be used i e the PLL clock Mpll or the direct external clock XTIpll or EXTCLK When PLL is configured to a new frequency value the clock control logic dis
214. O DZ can never be turned on simultaneously LE LIL Deadzone Interval lt Figure 10 7 The Wave Form When a Dead Zone Feature is Enabled ELECTRONICS 10 9 PWM TIMER 3 2410 DMA REQUEST MODE The PWM timer can generate a DMA request at every specific time The timer keeps DMA request signals nDMA low until the timer receives an ACK signal When the timer receives the ACK signal it makes the request signal inactive The timer which generates the DMA request is determined by setting DMA mode bits in TCFG1 register If one of timers is configured as DMA request mode that timer does not generate an interrupt request The others can generate interrupt normally DMA mode configuration and DMA interrupt operation on ov m meo or ow o o o ww ow Or o o ow INT4tmp DMAreq en 101 nDMA ACK nDMA REQ INT4 Figure 10 8 Timer4 DMA Mode Operation 10 10 ELECTRONICS 53 2410 PWM TIMER PWM TIMER CONTROL REGISTERS TIMER CONFIGURATION REGISTERO TCFGO Timer input clock Frequency PCLK prescaler value 1 divider value prescaler value 0 255 divider value 2 4 8 16 TCFGO 0x51000000 Configures the two 8 bit prescalers 0x00000000 Dead zone length 23 16 These 8 bits determine the dead zone length The 1 unit time 0x00 of the dead zone length is equal to that of timer 0
215. O interrupt is requested when LCD FIFO reaches trigger level ELECTRONICS 15 37 LCD CONTROLLER S3C2410A LCD Interrupt Mask Register LCDINTMSK 0X4D00005C R W Determine which interrupt source is masked 0x3 The masked interrupt source will not be serviced LCDINTMSK Description Determine the trigger level of LCD FIFO 0 4 words 1 8 words INT_FrSyn 1 Mask LCD frame synchronized interrupt 1 0 The interrupt service is available 1 The interrupt service is masked Mask LCD FIFO interrupt 0 The interrupt service is available 1 The interrupt service is masked INT_FiCnt LPC3600 Control Register LPCSEL 0 40000060 This register controls the LPC3600 modes Lm em RES_SEL 1 240x320 LPCSEL LPC_EN Determine LPC3600 Enable Disable 0 LPC3600 Disable 1 LPC3600 Enable 15 38 ELECTRONICS 3C2410A LCD CONTROLLER Register Setting Guide STN The LCD controller supports multiple screen sizes by special register setting The CLKVAL value determines the frequency of VCLK This value has to be determined such that the VCLK value is greater than data transmission rate The data transmission rate for the VD port of the LCD controller is used to determine the value of CLKVAL register The data transmission rate is given by the following equation Data transmission rate HS x VS x FR x MV HS Horizontal LCD size VS Vertical LCD size FR Frame rate MV Mode dependent value Table 15 6
216. OCESSOR OPERATING STATES From the programmer s point of view the ARM920T be in one of two states e ARM state which executes 32 bit word aligned ARM instructions e THUMB state which can execute 16 bit halfword aligned THUMB instructions In this state the PC uses bit 1 to select between alternate halfwords NOTE Transition between these two states does not affect the processor mode or the contents of the registers SWITCHING STATE Entering THUMB State Entry into THUMB state can be achieved by executing a BX instruction with the state bit bit 0 set in the operand register Transition to THUMB state will also occur automatically on return from an exception IRQ FIQ UNDEF ABORT SWI etc if the exception was entered with the processor in THUMB state Entering ARM State Entry into ARM state happens On execution of the BX instruction with the state bit clear in the operand register e On processor taking an exception IRQ RESET UNDEF ABORT SWI etc In this case the PC is placed in the exception mode s link register and execution commences at the exception s vector address MEMORY FORMATS 920 views memory as a linear collection of bytes numbered upwards from zero Bytes 0 to 3 hold the first stored word bytes 4 to 7 the second and so ARM920T can treat words in memory as being stored either Big Endian or Little Endian format ELECTRONICS 2 1 PROGRAMMER S MODEL 53 24
217. ORM 31 0 Inform register This register is cleared by nRESET or watchdog timer Otherwise preserve data value INFORM 31 0 Inform register This register is cleared by nRESET or watchdog timer Otherwise preserve data value 9 28 ELECTRONICS 53 2410 PWM TIMER PWM TIMER OVERVIEW The S3C2410A has five 16 bit timers Timer 0 1 2 and 3 have Pulse Width Modulation PWM function Timer 4 has an internal timer only with no output pins The timer 0 has a dead zone generator which is used with a large current device The timer 0 and 1 share an 8 bit prescaler while the timer 2 3 and 4 share other 8 bit prescaler Each timer has a clock divider which 5 different divided signals 1 2 1 4 1 8 1 16 and TCLK Each timer block receives its own clock signals from the clock divider which receives the clock from the corresponding 8 bit prescaler The 8 bit prescaler is programmable and divides the PCLK according to the loading value which is stored in TCFGO and TCFG1 registers The timer count buffer register TCNTBn has an initial value which is loaded into the down counter when the timer is enabled The timer compare buffer register has an initial value which is loaded into the compare register to be compared with the down counter value This double buffering feature of TCNTBn and TCMPBn makes the timer generate a stable output when the frequency and duty ratio are changed Each timer has its own 16 bit down counter
218. R SDI response register 2 0xy0 Response2 31 0 Unused short card status 63 32 long 0x00000000 SDI Response Register 3 SDIRSP3 SDIRSP3 0x5A000020 R SDI response register 3 Response3 31 0 Unused short card status 31 0 long 0x00000000 9 8 ELECTRONICS 53 2410 MMC SD SDIO HOST CONTROLLER SDI Data Timer SDIDTIMER Register Register Address R W Description Reset Value SDIDTIMER 0x5A000024 SDI data timer register 0x2000 SDIDTIMER DataTimer SDI Block Size SDIBSIZE Register 15 0 Data timeout period 0 65535 cycle 0x2000 Register Reset Value SDIBSIZE 0x5A000028 SDI block size register 0x0 BlkSize NOTE In Case of mult ELECTRONICS 11 0 Block size value 074095 byte Do not care when stream mode 0x000 i block BlkSize should be divided by word 4byte BlkSize 1 0 00 19 MMC SD SDIO HOST CONTROLLER S3C2410A SDI Data Control SDIDCON Register Register Address Description Reset Value SDIDCON 0x5A00002C data control register 5010 Interrupt Determine whether SDIO Interrupt period is 2 cycle or extend Period Type more cycle when last data block is transferred for 5010 PrdType 0 exactly 2 cycle 1 more cycles like single block Transmit After Determine when data transmit start after response receive or Response not TARSP 0 directly after DatMode set 1 after response receive assume DatMode sets to 2 b11 Rece
219. R11 fia D R12 D R13 fia D R14 Supervisor Abort Undefined R15 PC R15 PC ARM State Program Status Registers PXSPSR svc P SPSR_abt XSPSR_irq banked register Figure 2 3 Register Organization in ARM State ELECTRONICS 3C2410A PROGRAMMER S MODEL The THUMB State Register Set The THUMB state register set is a subset of the ARM state set The programmer has direct access to eight general registers RO R7 as well as the Program Counter PC a stack pointer register SP a link register LR and the CPSR There are banked Stack Pointers Link Registers and Saved Process Status Registers SPSRs for each privileged mode This is shown in Figure 2 4 THUMB State General Registers and Program Counter System amp User FIQ Supervisor Abort IRQ Undefined THUMB State Program Status Registers banked register Figure 2 4 Register Organization in THUMB state ELECTRONICS 2 5 PROGRAMMER S MODEL S3C2410A The relationship between ARM and THUMB state registers The THUMB state registers relate to the ARM state registers in the following way e THUMB state R0 R7 and ARM state R0 R7 are identical e THUMB state CPSR and SPSRs and ARM state CPSR and SPSRs are identical THUMB state SP maps onto ARM state R13 THUMB state LR maps onto ARM state R14 e The THUMB state Program Counter maps onto the ARM state Program Counter R15 This relationship is shown in Figure 2 5 THUMB st
220. RM920T will switch to BCLK to perform the access The delay when switching from FCLK to BCLK is a minimum of one FCLK phase and a maximum of one BCLK cycle An example of the clock switching is shown in Figure 5 3 The delay when switching from BCLK to FCLK is a maximum of one FCLK phase Figure 5 3 Switching from FCLK to BCLK in Synchronous Mode Care must be taken if BCLK is stopped by the system so that when BCLK is restarted it does not violate any of the above restrictions 5 2 ELECTRONICS ARM920T PROCESSOR CLOCK MODES ASYNCHRONOUS MODE This mode is typically used in systems with low speed memory In this mode of operation GCLK can be sourced from BCLK and FCLK BCLK is used to control the AMBA memory interface FCLK is used to control the internal ARM9TDMI processor core and any cache operations The one restriction is that FCLK must have a higher frequency than BCLK An example is shown in Figure 5 4 Figure 5 4 Asynchronous Clocking Mode If the ARM920T performs an external access for example a cache miss or a cache line fill ARM920T will switch to BCLK to perform the access The delay when switching from FCLK and BCLK is a minimum of one BCLK cycle and a maximum of one and a half BCLK cycles An example of the clock switching is shown in Figure 5 4 When switching from BCLK to FCLK the minimum delay is one FCLK cycle and the maximum delay is one and a half FCLK cycles An example of the clock switching is shown in Figure 5
221. RONICS 4 9 THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES S3C2410A All instructions in this format have an equivalent ARM instruction as shown in Table 4 4 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES MOV CMP ADD SUB RO 128 R2 62 R1 255 R6 145 RO 128 and set condition codes Set condition codes on R2 62 R1 R1 255 and set condition codes R6 R6 145 and set condition codes ELECTRONICS 3C2410A THUMB INSTRUCTION SET FORMAT 4 ALU OPERATIONS 15 14 13 12 11 10 9 6 5 3 2 0 2 0 Source Destination Register 5 3 Source Register 2 9 6 Opcode Figure 4 5 Format 4 OPERATION The following instructions perform ALU operations on a Lo register pair NOTE All instructions in this group set the CPSR condition codes Table 4 5 Summary of Format 4 Instructions THUMB Assembler _ARMEquipment 1000 TST Rd Rs TST Rs Set condition codes on Rd AND Rs 0111 ROR Rs MOVS Rd ROR Rs Rd Rd ROR Rs 1010 CMP Rs CMP Rs Set condition codes on Rd Rs ELECTRONICS 4 11 THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES S3C2410A All instructions in this format have an equivalent ARM instruction as shown in Table 4 5 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES EOR ROR NE
222. S350Q1 PD1 and PD2 has Horizontal Sampling Clock HCLK These two HCLKs may cause a confusion So note that HCLK of the S3C2410A is HCLK and other HCLK of the LTS350 is LCD HCLK Check that the HCLK of SEC TFT LCD panel LTS350Q1 PD1 and PD2 is changed to LCD HCLK ELECTRONICS 15 23 LCD CONTROLLER 83 2410 VIRTUAL DISPLAY TFT STN The S3C2410A supports hardware horizontal or vertical scrolling If the screen is scrolled the fields of LCDBASEU and LCDBASEL LCDSADDR 1 2 registers need to be changed see Figure 15 7 except the values of PAGEWIDTH and OFFSIZE The video buffer in which the image is stored should be larger than the LCD panel screen in size PAGEWIDTH OFFSIZE This is the data of line 1 of virtual screen This is the ddta of line 2 of virtual screen This is the ddta of line 3 of virtual screen This is the ddta of line 4 of virtual screen LINEVAL 1 This is of line 5 of virtual screen This is of line 6 of virtual screen is the data of line 7 of virtual scraen This is the data of line irtual screen This is data of line 8 of virtual This is the data of line 8 of virtual screen View Port This is the data of line 9 of virtual screen This is the data of line 9 of virtual screen The same size of LCD panel This s the data of line 10 of virtual screen This is the data of line 10 of virtual screen is the data of line 11 of virtual
223. SI Certificate No FM24653 All semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives Samsung Electronics Co Ltd San 24 Nongseo Dong Giheung Gu Yongin City Gyeonggi Do Korea 37 Suwon 449 900 TEL 82 031 209 1934 FAX 82 031 209 1899 Home Page http www samsung com Printed in the Republic of Korea Table of Contents Chapter 1 Product Overview INTO GUCTION u S anun A 1 1 EE 1 2 Diagt aiT u de irr re br i ee eee een 1 5 icti e iR XE 1 6 Signal Descriptions a 1 20 S3C2410A Special 1 26 Chapter 2 Programmer s model uya fonte c elei te asit reac ce dado E A eae 2 1 Processor Operating States e n tee i e bee Per bt e eats 2 1 SWITCHING tale ciae crime eet UE eet eite e et daa the 2 1 Memory Formats FC detis feret eed dd reste 2 1 Bio Endan Formats S AIC wee ei fer ee eo pde Leite P ee sts 2 2 Eittle Endian FEormat iet Cede ee b nli etd hence 2 2 Instruction
224. SK issued or not OUT_PKT_RDY condition happens This is only useful for DMA mode 0 Interrupt Enable 1 Interrupt Disable d REG ISO Determine endpoint transfer type 0 Configures endpoint to Bulk mode 1 Reserved ELECTRONICS 13 17 USB DEVICE 53 2410 END POINT FIFO REGISTER EPN_FIFO_REG The EPn_FIFO_REG enables the MCU to access to the EPn FIFO RIW EPO FIFO 0x520001 CO L R W End FIFO register OxXX 0x520001C3 B byte EP1 FIFO 0x520001C4 L R W End FIFO register OxXX 0x520001C7 B byte EP2_FIFO 0x520001 C8 L R W End FIFO register OxXX 0 520001 byte EP3_FIFO 0x520001CC L R W End Point3 FIFO register OxXX 0x520001CF B byte EPA FIFO 0x520001 DO L R W End Point4 FIFO register OxXX 0x520001D3 B byte FIFO_DATA 7 0 FIFO data value 13 18 ELECTRONICS 53 2410 USB DEVICE MAX PACKET REGISTER MAXP_ REG MAXP_REG 0x52000180 L End Point MAX packet register 0x01 0x52000183 B byte MAXP 3 0 R W 0000 Reserved 0001 MAXP 8 Byte0010 MAXP 16 Byte 0100 MAXP 32 Byte1000 MAXP 64 Byte For MAXP 8 is recommended For EP1 4 32 or MAXP 64 is recommended And if MAXP 32 the dual packet mode will be enabled automatically ELECTRONICS 13 19 USB DEVICE 53 2410 END POINT OUT WRITE COUNT REGISTER OUT_FIFO_CNT1_REG OUT_FIFO_CNT2_REG These registers maintain the number of bytes in the packet as the
225. Settings In Normal Operation Mode During the operation of the S3C2410A in NORMAL mode the user can change the frequency by writing the PMS value and the PLL lock time will be automatically inserted During the lock time the clock is not supplied to the internal blocks in the 53 2410 Figure 7 5 shows the timing diagram u PMS setting FCLK It changes to new PLL clock after automatic lock time Figure 7 5 Changing Slow Clock by Setting PMS Value USB Clock Control USB host interface and USB device interface needs 48Mhz clock In the S3C2410A the USB dedicated PLL UPLL generates 48MHz for USB UCLK does not fed until the PLL UPLL is configured After reset or EXTCLK After configuring UPLL L during PLL lock time On 48MHz after PLL lock time UPLL is turned off by CLKSLOW register or EXTCLK UPLL is turned on by CLKSLOW register 48MHz ELECTRONICS 7 7 CLOCK amp POWER MANAGEMENT 53 2410 HCLK is used by ARM920T HCLK is used for AHB bus which is used by the ARM920T the memory controller the interrupt controller the LCD controller the DMA and the USB host block PCLK is used for APB bus which is used by the peripherals such as IIS 12 PWM timer MMC interface ADC UART GPIO RTC and SPI The S3C2410A supports selection of Dividing Ratio between and PCLK This ratio is determined by HDIVN and PDIVN of CLKDIVN control
226. T When the nRESET signal goes LOW ARM920T abandons the executing instruction and then continues to fetch instructions from incrementing word addresses When nRESET goes HIGH again ARM920T 1 Overwrites R14 svc and SPSR svc by copying the current values of the PC and CPSR into them The value of the saved PC and SPSR is not defined Forces M 4 0 to 10011 Supervisor mode sets the and F bits in the CPSR and clears the CPSR s T bit Forces the PC to fetch the next instruction from address 0x00 Execution resumes in ARM state ELECTRONICS 2 15 PROGRAMMER S MODEL S3C2410A NOTES 2 16 ELECTRONICS 3C2410A ARM INSTRUCTION SET ARM INSTRUCTION SET INSTRUCTION SET SUMMAY This chapter describes the ARM instruction set in the ARM920T core FORMAT SUMMARY The ARM instruction set formats are shown below 31 30 29 28 27 26 25 24 23 22 2120 19 1817 1615 1413 1211109876543210 Opcode S Rn Operand2 Data Processing PSR Transfer Multiply Feo mato ms an wut Lo cone Fe 101010 Single Daia Snan n Rm Cond jojo o t o o t t t o o o Branch and Exchange Cond Rn 1 S H 1 Rm Halfword Data Transfer register offset Rn Offset Offset Halfword Data Transfer immendiate offset Cond U 1IWIL Sig Dat aret RR T sss nmt Cond 1 1 1 CP Opc Rm Coprocessor Data Operation Opc Cond 1 1 1 Ignored by proce
227. Table 3 14 3 9 Tiny Page Translation from a Fine Page 3 16 3 10 Domain Access Control Register Formatl a 3 19 3 11 Sequence for Checking Faults a 3 21 xxvi 3C2410A MICROPROCESSOR List of Tables Table Title Page Number Number 1 1 272 Pin FBGA Pin Assignments Pin Number Order sss 1 7 1 2 272 Pin FBGA Pin Assignments a 1 10 1 3 53 2410 Signal Descriptions 1 20 1 4 S3C2410A Special u 1 26 2 1 PSR Mode Bit Vale Sireen enaar aa earainn aaien aad dak taadaa aA aaeei 23 2 9 2 2 Exception ENntry Exit pee rt oi utet ARAA a ENAA NEATE E A 2 11 2 3 Exception Mecltors au ua E aT E eaa dei aeaa 2 13 3 1 The ARM Instruction Set U 3 2 3 2 Condition Code 3 4 3 3 ARM Data Processing 3 11 3 4 Incremental Cycle Times U entres 3 16 3 5 Assembler Syntax 3 27 3 6 Addressing Mode 3 45 4 1 THUMB Instr
228. UMB assembler syntax is shown below Table 4 7 Summary of PC Relative Load Instruction LDR PC lmm LDR Rd R15 Add unsigned offset 255 words 1020 bytes in Imm to the current value of the PC Load the word from the resulting address into Rd NOTE The value specified by 1 is a full 10 bit address but must always be word aligned ie with bits 1 0 set to 0 since the assembler places lmm gt gt 2 in field Word 8 The value of the PC will be 4 bytes greater than the address of this instruction but bit 1 of the PC is forced to 0 to ensure it is word aligned 4 16 ELECTRONICS 3C2410A THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES LDR R3 PC 844 Load into R3 the word found at the address formed by adding 844 to PC bit 1 of PC is forced to zero Note that the THUMB opcode will contain 211 as the Word8 value ELECTRONICS 4 17 THUMB INSTRUCTION SET S3C2410A FORMAT 7 LOAD STORE WITH REGISTER OFFSET 15 14 13 12 11 10 9 8 6 5 3 2 0 ee ee ee m 2 0 Source Destination Register 5 3 Base Register 8 6 Offset Register 10 Byte Word Flag 0 Transfer word quantity 1 Transfer byte quantity 11 Load Store Flag 0 Store to memory 1 Load from memory Figure 4 8 Format 7
229. UP END C H SERVICED OUT _ 6 W LEAR The MCU should write a 1 to this bit to PKT RDY clear OUT PKT RDY SEND STALL 5 R W CLEAR MCU should write a 1 to this bit at the 0 same time it clears OUT PKT RDY if it decodes an invalid token 1 The USB issues a STALL and shake to the current control transfer SETUP END 4 SET Set by the USB when a control transfer ends before DATA END is set When the USB sets this bit an interrupt is generated to the MCU When such a condition occurs the USB flushes the FIFO and invalidates MCU access to the FIFO DATA END 3 SET Set by the MCU on the conditions below the FIFO at the same time IN PKT RDY is set 2 While it clears OUT PKT RDY after unloading the last packet of data 3 For a zero length data phase f m 0 Finish the STALL condition 1 After loading the last packet of data into SENT STALL CLEAR SET Setby the USB if a control transaction is stopped due to a protocol violation An interrupt is generated when this bit is set The MCU should write 0 to clear this bit 13 12 ELECTRONICS 53 2410 USB DEVICE END POINTO CONTROL STATUS REGISTER CSR Continued IN PKT RDY 1 SET CLEAR Set by the MCU after writing a packet of data into EPO FIFO The USB clears this bit once the packet has been successfully sent to the host An interrupt is generated when the USB clears this bit so as the MCU to load the next packet For a zero length
230. VCO output frequency by s which is Mpll the output frequency from MPLL block the phase difference detector the charge pump and the loop filter The output clock frequency Mpll is related to the reference input clock frequency Fin by the following equation m Fin p 2 m M the value for divider M 8 p P the value for divider P 2 The UPLL within the clock generator is the same as the MPLL in every aspect The following sections describe the operation of the PLL including the phase difference detector the charge pump the Voltage controlled oscillator VCO and the loop filter Phase Frequency Detector PFD The PFD monitors the phase difference between Fref and Fvco and generates a control signal tracking signal when it detects a difference The Fref means the reference frequency as shown in the Figure 7 2 Charge Pump PUMP The charge pump converts PFD control signals into a proportional charge in voltage across the external filter that drives the VCO Loop Filter The control signal which the PFD generates for the charge pump may generate large excursions ripples each time the Fvco is compared to the Fref To avoid overloading the VCO a low pass filter samples and filters the high frequency components out of the control signal The filter is typically a single pole RC filter with a resistor and a capacitor Voltage Controlled Oscillator VCO The output voltage from the loop filter drives the VC
231. Vppiarm 1 8 0 15 2 0 V 0 1 V T4 40 to 85 C 3 3V 0 3V ES ZC SDRAM Chip Select Delay 2 6 55 ns SDRAM Row active Delay te 1 5 45 ns SDRAM Column active Delay 1 5 45 ns SDRAM Byte Enable Delay 2 6 55 ns SDRAM read Data Setup time los 4 21 ns SDRAM read Data Hold time oe i SDRAM output Data Delay lp 2 7 55 ns SDRAM Clock Enable Delay t p 2 5 45 ns Se 0 3 C 0 0 MEE TM 2 24 32 ELECTRONICS 53 2410 ELECTRICAL DATA Table 24 9 External Bus Request Timing Constants 1 8 0 15 2 0 V 0 1 V T4 40 to 85 C 3 3V 0 3V Parameter Mm Me Um wees xema Bis Request Hating ans 05 teo 9 379 0 uw Site 4 Table 24 10 DMA Controller Module Signal Timing Constants 1 8 0 15 2 0 V 0 1 V T4 40 to 85 C 3 3V 0 3V smi Wn We Me inky Taos w S Goes 10 Ack Delay when High wanton ex 79 e 2 Sak ELECTRONICS 24 33 ELECTRICAL DATA S3C2410A Table 24 11 TFT LCD Controller Module Signal Timing Constants
232. WM TIMER PWM TIMER OPERATION PRESCALER amp DIVIDER An 8 bit prescaler and a 4 bit divider make the following output frequencies 4 bit divider settings Minimum resolution Maximum resolution Maximum interval prescaler 0 prescaler 255 TCNTBn 65535 1 2 PCLK 66 5 MHz 0 0300 us 33 2500 MHz 7 6992us 129 8828 KHz 0 5045 sec 1 4 PCLK 66 5 MHz 0 0601 us 16 6250 MHz 15 3984 64 9414 KHz 1 0091 sec 1 8 66 5 MHz 0 1203 us 8 3125 MHz 30 7968 32 4707 KHz 2 0182 sec 1 16 66 5 MHz 0 2406 us 4 1562 61 5936 us 16 2353 KHz 4 0365 sec BASIC TIMER OPERATION Start bit 1 Timer is started TCNTn TCMPn Auto reload TCNTn TCMPn Timer is stopped 1 Manual update 1 Manual update 0 Auto reload 1 Auto reload 1 Figure 10 2 Timer Operations A timer except the timer ch 5 has TCNTBn TCNTn TCMPBn and TCMPn TCNTn and TCMPn are the names of the internal registers The TCNTn register can be read from the TCNTOn register The TCNTBn and the TCMPBn are loaded into the TCNTn and the TCMPn when the timer reaches 0 When the TCNTn reaches 0 interrupt request will occur if the interrupt is enabled ELECTRONICS 10 3 PWM TIMER 3 2410 AUTO RELOAD amp DOUBLE BUFFERING 53 2410 PWM Timers have a double buffering function enabling the reload value changed for the next timer operation without stopping the current timer operation So although the n
233. a is written to memory via the ASB Load multiple LDM instructions accessing NCNB or NCB regions perform sequential bursts on the ASB Store multiple STM instructions accessing NCNB regions also perform sequential bursts on the ASB The sequential burst will be split into two bursts if it crosses a 1KB boundary This is because the smallest MMU protection and mapping size is 1KB so the memory regions on each size of the 1KB boundary may have different properties This means that no sequential access generated by ARM920T will cross a 1KB boundary which be exploited to simplify memory interface design For example a simple page mode DRAM controller could perform a page mode access for each sequential access provided the DRAM page size is 1KB or larger See also Cache coherence on page 4 10 DATA CACHE REPLACEMENT ALGORITHM The DCache and ICache replacement algorithm is selected by the RR bit in the CP15 Control register CP15 register 1 bit 14 Random replacement is selected at reset Setting the RR bit to 1 selects round robin replacement SWAP INSTRUCTIONS Swap instruction SWP or SWPB behavior is dependent on whether the memory region is cacheable or non cacheable Swap instructions to cacheable regions of memory are useful for implementing semaphores or other synchronization primitives in multithreaded uniprocessor software systems Swap instructions to non cacheable memory regions are useful for synchronization betwe
234. a word B 0 between 920 register and memory The action of LDR B and STR B instructions is influenced by the BIGEND control signal of ARM920T core The two possible configurations are described below Little Endian Configuration A byte load LDRB expects the data on data bus inputs 7 through 0 if the supplied address is on a word boundary on data bus inputs 15 through 8 if it is a word address plus one byte and so on The selected byte is placed in the bottom 8 bits of the destination register and the remaining bits of the register are filled with zeros Please see Figure 2 2 A byte store STRB repeats the bottom 8 bits of the source register four times across data bus outputs 31 through 0 The external memory system should activate the appropriate byte subsystem to store the data A word load LDR will normally use a word aligned address However an address offset from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 0 to 7 This means that half words accessed at offsets 0 and 2 from the word boundary will be correctly loaded into bits 0 through 15 of the register Two shift operations are then required to clear or to sign extend the upper 16 bits A word store STR should generate a word aligned address The word presented to the data bus is not affected if the address is not word aligned That is bit 31 of the register being stored always appears on data bus
235. able index T B Level one descriptor Low DI Pl 31 10 9 21 0 Coarse page table base address L2 table index 0 0 Level two descriptor 1211109 8 7 65 4 3 2 1 eese To 00 Physical address 12 11 Figure 3 8 Small Page Translation from a Coarse Page Table 3 14 ELECTRONICS ARM920T PROCESSOR MMU TRANSLATING TINY PAGE REFERENCES Figure 3 9 on page 3 16 illustrates the complete translation sequence for a 1KB tiny page Page translation involves one additional step beyond that of a section translation the level one descriptor is the fine page table descriptor and this is used to point to the level one descriptor NOTE The domain specified in the level one description and access permissions specified in the level one description together determine whether the access has permissions to proceed See section Domain access control on page 3 19 for details ELECTRONICS 3 15 MMU ARM920T PROCESSOR Modified virtual address 20 19 Table index L2 table index Translation table base 14 13 Translation base 18 Translation base Table index T a Level one descriptor 12 11 D Jes Fine page table base address L2 table index T m Level two descriptor TI 1 Physical address 31 10 9 0 Figure 3 9 Tiny Page Translation from a Fine Page Table 3 16 ELECTRONICS ARM920T PROCESSOR MMU SUB PAGES Access permissions can be defined for sub pages of small and large pages during a
236. abled an ICache lookup is performed for each instruction fetch regardless of the setting of the Ctt bit in the relevant MMU translation table descriptor If the required instruction is found in the cache the lookup is called a cache hit If the required instruction is not found in the cache the lookup is called a cache miss If the instruction fetch is a cache hit and Ctt 1 indicating a cacheable region of memory then the instruction is returned from the cache to the ARM9TDMI CPU core If it is a cache miss and Ctt 1 then an 8 word linefill will be performed possibly replacing another entry The entry to be replaced called the victim is chosen from the entries which are not locked using either a random or round robin replacement policy If Ctt 0 indicating a non cacheable region of memory then a single non sequential memory access will appear on the ASB NOTE If Ctt 0 indicating a non cacheable region of memory then the cache lookup should result in a cache miss The only way that it can result in a cache hit is if software has changed the value of the Ctt bit in the MMU translation table descriptor without invalidating the cache contents This is a programming error as the behavior in this case is architecturally unpredictable and varies between implementations ELECTRONICS 4 3 CACHES WRITE BUFFER ARM920T PROCESSOR INSTRUCTION CACHE REPLACEMENT ALGORITHM The and DCache replacement algorithm is selected by th
237. ables the until the PLL output is stabilized using the PLL locking time The clock control logic is also activated at power on reset and wakeup from power down mode Power On Reset XTIpll Figure 7 4 shows the clock behavior during the power on reset sequence The crystal oscillator begins oscillation within several milliseconds When nRESET is released after the stabilization of OSC clock the PLL starts to operate according to the default PLL configuration However PLL is commonly known to be unstable after power on reset so Fin is fed directly to FCLK instead of the Mpll PLL output before the software newly configures the PLLCON Even if the user does not want to change the default value of PLLCON register after reset the user should write the same value into PLLCON register by software The PLL restarts the lockup sequence toward the new frequency only after the software configures the PLL with a new frequency FCLK can be configured as PLL output Mpll immediately after lock time Power PLL can operate after OM 3 2 is latched nRESET OSC XTIpll Y PLL is configured by S W first time Clock Disable Lock Time VCO is adapted new clock frequency VCO The logic operates by 1 FCLK is new frequency Figure 7 4 Power On Reset Sequence when the external clock source is a crystal oscillator 7 6 ELECTRONICS 53 2410 CLOCK 8 POWER MANAGEMENT Change PLL
238. ache linefills will now occur into lines 1 63 NOTE Writing CP15 register 9 with the CRm field set to 0b0001 updates the current victim pointer only for the specified segment only Bits 31 26 specify the victim bits 7 5 specify the segment for a 16KB cache and all other bits should be zero This encoding is intended for debug use It is not necessary and not advised to use this encoding ELECTRONICS 2 19 PROGRAMMER S MODEL ARM920T PROCESSOR Figure 2 5 shows the format of bits in register 9 31 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12111098 7 6 5 4 3 2 1 0 __________ __ _ __ _ __________ ____ _ UNP SBZ Figure 2 5 Register 9 Table 2 18 shows the instructions needed to access the cache lock down register Table 2 18 Accessing the Cache Lock Down Register 9 Read DCache lock down base MRC p15 0 Rd c9 c0 0 Write DCache victim and lockdown base MCR p15 0 Rd c9 c0 0 Read lock down base p15 0 Rd c9 c0 1 Write victim and lockdown base MCR p15 0 Rd c9 c0 1 2 20 ELECTRONICS ARM920T PROCESSOR PROGRAMMER S MODEL REGISTER 10 TLB LOCK DOWN REGISTER Register 10 is the TLB lock down register The TLB lock down register is 0x0 on reset There is a TLB lock down register for each of the TLBs the value of opcode 2 determines which TLB register to access opcode 2 0 0 causes the D TLB register to be accessed opcode 2 0 1 causes the TLB register to be accessed Re
239. ad 7 5 4 3 9 8 ELECTRONICS 3 2410 PORTS PORT CONTROL REGISTERS GPBDAT and GPBCON 0x56000010 Configure the pins of port B GPBDAT 0x56000014 The data register for port B Undefined 0 0 GPBUP 0x56000018 Pull up disable register for port B 0x5600001C Reserved Undefined GPECON BesHpin 21 20 GPB10 GPB9 s m a s GPB8 17 16 GPB7 LENIN 00 Input 10 2 nXDREQO 00 Input 10 nXDACKO 00 Input 10 nXDREQ1 00 Input 10 nXDACK1 00 Input 10 00 Input 10 00 Input 10 TCLKO 00 Input 10 TOUT3 00 Input 10 TOUT2 00 Input 10 TOUT1 00 Input 10 TOUTO 01 Output 11 reserved 01 Output 11 reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 reserved 01 Output 11 reserved 01 Output 11 reserved 01 Output 11 reserved 01 Output 11 reserved 01 Output 11 reserved 01 Output 11 reserved Depo When the port is configured as input port data from external sources can be read to the corresponding pin When the port is configured as output port data written in this register can be sent to the corresponding pin When the port is configured as functional pin undefined value will be read 0 The pull up function attached to to the corresponding por
240. ad or store write or swap instruction including LDR LDRB LDRH LDM LDC STR STRB STRH STC SWP and SWPB To ensure accesses appear on the ASB in program order 920 will wait for all writes in the write buffer to complete on the ASB before starting any other ASB access The ARM9TDMI CPU core can continue executing at full speed reading instructions and data from the caches and writing to the DCache and write buffer while buffered writes are being written to memory via the ASB Table 4 1 describes the DCache and write buffer behavior for each type of memory configuration Ctt AND Ccr means the bitwise Boolean AND of Ctt with Ccr 4 6 ELECTRONICS ARM920T PROCESSOR CACHES WRITE BUFFER Table 4 1 Data Cache and Write Buffer Configuration Ctt and Ccr Data cache write buffer and memory access behavior Non cached non buffered NCNB Reads and writes are not cached and always perform accesses on the ASB and may be externally aborted Writes are not buffered The CPU halts until the write is completed on the ASB Cache hits should never occur 2 Non cached buffered NCB Reads and writes are not cached and always perform accesses on the ASB Cache hits should never occur Writes are placed in the write buffer and will appear on the ASB The CPU continues execution as soon as the write is placed in the write buffer Reads may be externally aborted Writes can not be externally aborted Cached write t
241. addition to the control signals the 53 2410 has the data ports for video data which are VD 23 0 as shown in Figure 15 1 The LCD controller consists of a REGBANK LCDCDMA VIDPRCS TIMEGEN and LPC3600 See the Figure 15 1 LCD Controller Block Diagram The REGBANK has 17 programmable register sets and 256x16 palette memory which are used to configure the LCD controller The LCDCDMA is a dedicated DMA which can transfer the video data in frame memory to LCD driver automatically By using this special DMA the video data can be displayed on the screen without CPU intervention The VIDPRCS receives the video data from the LCDCDMA and sends the video data through the VD 23 0 data ports to the LCD driver after changing them into a suitable data format for example 4 8 bit single scan or 4 bit dual scan display mode The TIMEGEN consists of programmable logic to support the variable requirements of interface timing and rates commonly found in different LCD drivers The TIMEGEN block generates VFRAME VLINE VCLK VM and so on The description of data flow is as follows FIFO memory is present in the LCDCDMA When FIFO is empty or partially empty the LCDCDMA requests data fetching from the frame memory based on the burst memory transfer mode consecutive memory fetching of 4 words 16 bytes per one burst request without allowing the bus mastership to another bus master during the bus transfer When the transfer request is accepted by bus arbitrator in
242. ading CP15 register 10 returns the value of the TLB lock down counter base register the current victim number and the preserve bit P bit Note that bits 19 1 are unpredictable when read Writing CP15 register 10 updates the TLB lock down counter base register the current victim pointer and the state of the preserve bit Bits 19 1 should be zero when written Table 2 19 shows the instructions needed to access the TLB lock down register Table 2 19 Accessing the TLB Lock Down Register 10 Read D TLB lock down TLB lock down MRC 15 0 10 0 0 Write D TLB lock down TLB lock down MCR p15 0 Rd c10 c0 0 Read TLB lock down TLB lock down MRC p15 0 Rd c10 c0 1 Write TLB lock down TLB lock down MCR p15 0 Rd c10 c0 1 Figure 2 6 shows the format of bits in register 10 31 26 25 20191817161514131211109 8 7 654 32 1 0 Base __ L UNP SBZ Figure 2 6 Register 10 The entries in the TLBs are replaced using a round robin replacement policy This is implemented using a victim counter which counts from entry 0 up to 63 and then wraps back round to the base value and continues counting wrapping around to the base value from 63 each time There are two mechanisms available for ensuring entries are not removed from the TLB Locking an entry down prevents it from being selected for overwriting during a table walk this is achieved by pr
243. akes effect Figure 20 7 Operations for Master Receiver Mode 20 8 ELECTRONICS S3C2410A IIC BUS INTERFACE Slave Tx mode has been configured IIC detects start signal and IICDS receives data IIC compares IICADD and IICDS the received slave address The IIC address match interrupt is generated Write data to IICDS Clear pending bit to resume N The data of the IICDS is shifted to SDA Interrupt is pending Figure 20 8 Operations for Slave Transmitter Mode ELECTRONICS 20 9 IIC BUS INTERFACE 53 2410 Slave Rx mode has been configured IIC detects start signal and IICDS receives data IIC compares IICADD and IICDS the received slave address The IIC address match interrupt is generated Clear pending bit to resume SDA is shifted to IICDS Interrupt is pending Figure 20 9 Operations for Slave Receiver Mode 20 10 ELECTRONICS 53 2410 IIC BUS INTERFACE IIC BUS INTERFACE SPECIAL REGISTERS MULTI MASTER IIC BUS CONTROL IICCON REGISTER IICCON 0x54000000 control register Acknowledge 7 IIC bus acknowledge enable bit generation note 1 0 Disable 1 Enable In Tx mode the IICSDA is free in the ack time In Rx mode the IICSDA is L in the ack time Tx clock source Source clock of transmit clock prescaler selection bit selection 0 16 1 IICCLK
244. al power So there occurs no power consumption due to CPU and the internal logic except the wake up logic in this mode Activating the Power OFF mode requires two independent power sources One of the two power sources supplies the power for the wake up logic The other one supplies other internal logics including CPU and should be controlled for power on off In the Power OFF mode the second power supply source for the CPU and internal logics will be turned off The wakeup from Power OFF mode can be issued by the EINT 15 0 or by RTC alarm interrupt ELECTRONICS 7 1 CLOCK amp POWER MANAGEMENT 53 2410 FUNCTIONAL DESCRIPTION CLOCK ARCHITECTURE Figure 7 1 shows a block diagram of the clock architecture The main clock source comes from an external crystal or an external clock EXTCLK The clock generator includes an oscillator Oscillation Amplifier which is connected to an external crystal and also has two PLLs Phase Locked Loop which generate the high frequency clock required in the 53 2410 CLOCK SOURCE SELECTION Table 7 1 shows the relationship between the combination of mode control pins and 2 and the selection of source clock for the 53 2410 The OM 3 2 status is latched internally by referring the and OM2 pins at the rising edge of nRESET Table 7 1 Clock Source Selection at Boot Up Mode 3 2 MPLL State UPLL State Main Clock source USB Clock Source x O O o
245. allows ICache coherency to be efficiently maintained when small code changes occur for example self modifying code and changes to exception vectors The write buffer can hold 16 words of data and four addresses ELECTRONICS 4 1 CACHES WRITE BUFFER ARM920T PROCESSOR INSTRUCTION CACHE ARM920T includes a 16KB instruction cache The has 512 lines of 32 bytes 8 words arranged as 64 way set associative cache and uses modified virtual addresses translated by CP15 register 13 see Address translation on page 3 4 from the ARM9TDMI core The ICache implements allocate on read miss Random or round robin replacement can be selected under software control via the RR bit CP15 register 1 bit 14 Random replacement is selected at reset Instructions can also be locked in the ICache such that they cannot be overwritten by a linefill This operates with a granularity of 1 64th of the cache which is 64 words 256 bytes All instruction accesses are subject to MMU permission and translation checks Instruction fetches which are aborted by the MMU will not cause linefills or instruction fetches to appear on the ASB For clarity the bit bit 12 in CP15 register 1 is referred to as the Icr bit throughout the following text The C bit from the MMU translation table descriptor corresponding to the address being accessed is referred to as Ctt 4 2 ELECTRONICS ARM920T PROCESSOR CACHES WRITE BUFFER INSTRUCTION CACHE EN
246. alue of UERSTSTn When the receiver transfers the data of the receive shifter to the receive FIFO register in FIFO mode and the number of received data reaches Rx FIFO Trigger Level Rx interrupt is generated if Receive mode in control register UCONn is selected as 1 Interrupt request or polling mode In the Non FIFO mode transferring the data of the receive shifter to the receive holding register will cause Rx interrupt under the Interrupt request and polling mode When the transmitter transfers data from its transmit FIFO register to its transmit shifter and the number of data left in transmit FIFO reaches Tx FIFO Trigger Level Tx interrupt is generated if Transmit mode in control register is selected as Interrupt request or polling mode In the Non FIFO mode transferring data from the transmit holding register to the transmit shifter will cause Tx interrupt under the Interrupt request and polling mode If the Receive mode and Transmit mode in control register are selected as the DMAn request mode then DMAn request occurs instead of Rx or Tx interrupt in the situation mentioned above Table 11 1 Interrupts in Connection with FIFO FIFO Mode Non FIFO Mode Rx interrupt Generated whenever receive data reaches the Generated by the receive holding register trigger level of receive FIFO whenever receive buffer becomes full Generated when the number of data in FIFO does not reaches Rx FIFO trigger Level and does not receive any data du
247. ammer s MOdel nila tla beanie t ee e ER 2 1 About ARM9TDMI Programmer s 2 2 Pata Abon Model n eR ed 2 2 Instruction Set Extension u ua u q entente enne sterii nnns 2 3 Cp15 Register Map Summary thee y epe tede rette i ce eee db EE ds 2 4 Accessing re t epe aee E er et Ute 2 5 Register ID Code Register n t eee dee bb I ent p etl ea 2 7 Register 0 Cache Type 2 8 Register 1 Control Register isise ah eee TR S 2 10 Register 2 Translation Table Base TTB 2 12 Register 3 Domain Access Control 2 13 Register 4 deed eet re eee est eed neret 2 14 Register 5 Fault Status 2 14 Register 6 Fault Address 2 15 Register 7 Cache Operations ied tad e ate tide tite esee RR 2 15 Register 8 TLB Operations u e IE ee e tU Rente Pretorio rie AREE 2 18 Register 9 Cache Lock Down Register enne nennen nennen nennen 2 19 Regi
248. an external device provides the UART with UEXTCLK then the UART can operate at higher speed Each UART channel contains two 16 byte FIFOs for receive and transmit The S3C2410A UART includes programmable baud rates infra red IR transmit receive one or two stop bit insertion 5 bit 6 bit 7 bit or 8 bit data width and parity checking Each UART contains a baud rate generator a transmitter a receiver and a control unit as shown in Figure11 1 The baud rate generator can be clocked by PCLK or UEXTCLK The transmitter and the receiver contain 16 byte FIFOs and data shifters Data is written to FIFO and then copied to the transmit shifter before being transmitted The data is then shifted out by the transmit data pin TxDn Meanwhile received data is shifted from the receive data pin RxDn and then copied to FIFO from the shifter FEATURES RxD1 TxD1 RxD2 and TxD2 with DMA based or interrupt based operation UART Ch 0 1 and 2 with IrDA 1 0 4 16 byte FIFO UART Ch0 and 1 with nRTSO nCTSO nRTS1 and nCTS1 Supports handshake transmit receive ELECTRONICS 11 1 UART S3C2410A BLOCK DIAGRAM Peripheral BUS Transmitter Transmit FIFO Register FIFO mode Transmit Buffer Register 16 Byte gister 16 Byte Transmit Holding Register Non FIFO mode Transmit Shifter Control Buad rate Unit Generator Receiver Receive Shifter Receive Holding Register Receive Buffer Non FIFO mode on
249. and MMU The ARM9TDMI processor core is a Harvard architecture device implemented using a five stage pipeline consisting of fetch decode execute memory and write stages and can be provided as a stand alone core which can be embedded into more complex devices The stand alone core has a simple bus interface that allows users to design their own caches memory systems around it The ARMSTDMI family of microprocessors supports both the 32 bit ARM and 16 bit Thumb instruction sets allowing the user to trade off between high performance and high code density The ARM920T is a Harvard cache architecture processor which is targeted at multiprogrammer applications where full memory management high performance and low power are all important The separate instruction and data caches in this design are 16KB each in size with an 8 word line length The ARM920T implements an enhanced ARM Architecture V4 MMU to provide translation and access permission checks for instruction and data addresses The ARM920T supports the ARM debug architecture and includes logic to assist in both hardware and software debug The ARM920T also includes support for coprocessors exporting the instruction and data buses along with simple handshaking signals The 920 interface to the rest of the system is via unified address and data buses This interface is compatible with the Advanced Microcontroller Bus Architecture AMBA bus scheme either as a fully compliant AMBA b
250. and V of CPSR SPSR mode without affecting the control bits In this case the top four bits of the specified register contents or 32 bit immediate value are written to the top four bits of the relevant PSR OPERAND RESTRICTIONS e n user mode the control bits of the CPSR are protected from change so only the condition code flags of the CPSR can be changed In other privileged modes the entire CPSR can be changed Note that the software must never change the state of the T bit in the CPSR If this happens the processor will enter an unpredictable state e SPSR register which is accessed depends on the mode at the time of execution For example only SPSR fiq is accessible when the processor is in FIQ mode e You must not specify R15 as the source or destination register Also do not attempt to access an SPSR in User mode since no such register exists 3 18 ELECTRONICS 3C2410A ARM INSTRUCTION SET MRS transfer PSR contents to a register 31 28 27 23 22 21 16 15 12 11 1 15 12 Destination Register 22 Source PSR 0 1 SPSR_ lt current mode 31 28 Condition Field MSR transfer register contents to PSR 31 28 27 23 22 21 12 11 4 Cond oo Paf 1010011 00000000 3 0 Source Register 22 Destination PSR 0 1 SPSR_ lt current mode gt 31 28 Condition Field MSR transfer register contents or immediate value to PSR flag bits only 31
251. ard Protocol version 1 0 e Bytes FIFO for Tx Rx e DMA based or Interrupt based operation e Compatible with Multimedia Card Protocol version 2 11 SPI Interface e Compatible with 2 ch Serial Peripheral Interface Protocol version 2 11 e 2x8 bits Shift register for Tx Rx e DMA based or interrupt based operation Operating Voltage Range Core 1 8V 200MHz 83C2410A 20 2 0V for 266MHz 83C2410A 26 e Memory amp IO 3 3V Operating Frequency Up to 266MHz Package 272 ELECTRONICS 3 2410 BLOCK DIAGRAM ARM920T ARM9TDMI Processor core Internal Embedded ICE 31 0 Instruction CACHE 16KB IV A 31 0 15 0 DV A 31 0 e DPA 31 0 Data CACHE 16KB LCD LCD CONT DMA USB Host CONT gt ExtMaster NAND CONT NAND Flash Boot gt Loader PRODUCT OVERVIEW External Coproc Interface WriteBack WBPA 31 0 PA Tag RAM BUS CONT Arbitor Decode Interrupt CONT Power Management Memory CONT SRAM NOR SDRAM id Generator id PLL Bridge amp DMA 4Ch UART 0 1 2 gt USB gt SDIMMC gt Je Timer PWM gt 0 3 4 Internal 12 25 lt GPIO RTC ADC Figure 1 1 S3C2410A Block Diagram ELECTRONICS PRODUCT OVERVIEW PIN ASSIGNMENTS QUO QD DO 6 es al HE O Q O C O O QUO DOT
252. arlier ARM processors must not be used the PSR transfer operations should be used instead The action of TEQP in the ARM920T is to move SPSR mode to the CPSR if the processor is in a privileged mode and to do nothing if in User mode INSTRUCTION CYCLE TIMES Data Processing instructions vary in the number of incremental cycles taken as follows Table 3 4 Incremental Cycle Times Data processing with register specified shift 15 11 Data processing with PC written 25 1N Data processing with register specified shift and PC written 2 1N 1 NOTE 5 defined sequential S cycle non sequential N cycle and internal I cycle respectively 3 16 ELECTRONICS 3C2410A ARM INSTRUCTION SET ASSEMBLER SYNTAX e MOV MVN single operand instructions lt opcode gt cond S Rd lt Op2 gt e CMP CMN TEQ TST instructions which do not produce a result opcode cond Rn lt Op2 gt AND EOR SUB RSB ADD ADC SBC RSC ORR BIC lt opcode gt cond S Rd Rn lt Op2 gt where lt Op2 gt Rm lt shift gt or expression cond A two character condition mnemonic See Table 3 2 S Set condition codes if S present implied for CMP CMN TEQ TST Rd Rn and Rm Expressions evaluating to a register number lt expression gt If this is used the assembler will attempt to generate a shifted immediate 8 bit field to match the expression If this is impossible it will give an error lt shif
253. ask Trigger DMASKTRIG Register nennen nennen nnne nennen 8 13 Chapter 9 Ports OVOIVIOW etii a bt o a tee tc e c 9 1 Port Control Description S eL eee n Oed e E bee ha i t P TI er hee d erede 9 7 Port Configuration Register GPACON GPHCON J a 9 7 Port Data Register SPADAT GPHDAT u aa u ai kania enters nnns ennt enses snnt 9 7 Port Pull up Register 9 7 Miscellaneous Control 9 7 External Interrupt Control Register 9 7 Power Mode and I O aaa 9 7 l O Port Control Register ci tee ee ett et er ua Aa mna 9 8 Port A Control Registers GPACON GPADAT nnns nnne 9 8 Port B Control Registers GPBCON GPBDAT and 9 9 Port C Control Registers GPCCON GPCDAT and 9 10 Port D Control Registers GPDCON GPDDAT and GPDUP nnn 9 12 Port E Control Registers GPECON GPEDAT and 9 14 Port F Control Registers GPFCON GPFDAT and 9 16 Port Control Registers GPG
254. asked NT 0 Service available 1 Masked 0 Service available 1 Masked 0 Service available 1 Masked 0 Service available 1 Masked 0 Service available 1 Masked 0 Service available 1 Masked INTRO 0 0 Service available 1 Masked 14 18 ELECTRONICS 3C2410A LCD CONTROLLER LCD CONTROLLER OVERVIEW The LCD controller in the S3C2410A consists of the logic for transferring LCD image data from a video buffer located in system memory to an external LCD driver The LCD controller supports monochrome 2 bit per pixel 4 level gray scale or 4 bit per pixel 16 level gray scale mode on a monochrome LCD using a time based dithering algorithm and Frame Rate Control FRC method and it can be interfaced with a color LCD panel at 8 bit per pixel 256 level color and 12 bit per pixel 4096 level color for interfacing with STN LCD It can support 1 bit per pixel 2 bit per pixel 4 bit per pixel and 8 bit per pixel for interfacing with the palettized TFT color LCD panel and 16 bit per pixel and 24 bit per pixel for non palettized true color display The LCD controller can be programmed to support different requirements on the screen related to the number of horizontal and vertical pixels data line width for the data interface interface timing and refresh rate FEATURES STN LCD displays Supports 3 types of LCD panels 4 bit dual scan 4 bit single scan and 8 bit single scan display typ
255. ate ARM state 1 2 4 Lo registers 1 2 4 5 7 5 z LR 7 R10 rogram Counter R15 Hi registers Figure 2 5 Mapping of THUMB State Registers onto ARM State Registers 2 6 ELECTRONICS 3C2410A PROGRAMMER S MODEL Accessing Hi Registers in THUMB State In THUMB state registers R8 R15 the Hi registers are not part of the standard register set However the assembly language programmer has limited access to them and can use them for fast temporary storage A value may be transferred from a register in the range RO R7 a Lo register to a Hi register and from a Hi register to a Lo register using special variants of the MOV instruction Hi register values can also be compared against or added to Lo register values with the CMP and ADD instructions For more information refer to Figure 3 34 THE PROGRAM STATUS REGISTERS The ARM92OT contains a Current Program Status Register CPSR plus five Saved Program Status Registers SPSRs for use by exception handlers These register s functions are e Hold information about the most recently performed ALU operation e Control the enabling and disabling of interrupts Set the processor operating mode The arrangement of bits is shown in Figure 2 6 Condition Code Flags Reserved Control Bits 31 30 29 28 27 26 25 24 23 Overflow Mode bits Carry Borrow Extend State bit Zero FIQ disable Negative Less Than IRQ disable
256. ate is 115200 bps and PCLK UEXTCLK is 40 MHz UBRDIVn is determined UBRDIVn int 40000000 115200 x 16 1 int 21 7 1 21 1 20 Baud Rate Error Tolerance UART Frame error should be less than 1 87 3 160 tUPCLK UBRDIVn 1 x 16 x 1Frame PCLK tUPCLK Real UART Clock tUEXACT 1Frame baud rate tUEXACT Ideal UART Clock UART error tUPCLK tUEXACT tUEXACT x 100 NOTES 1 1Frame start bit data bit parity bit stop bit 2 specific condition we can support baud rate up to 921 6 bps For example when is 60 2 you can use baud rate of 921 6K bps under UART error of 1 69 Loopback Mode The S3C2410A UART provides a test mode referred to as the Loopback mode to aid in isolating faults in the communication link This mode structurally enables the connection of RXD and TXD in the UART In this mode therefore transmitted data is received to the receiver via RXD This feature allows the processor to verify the internal transmit and to receive the data path of each SIO channel This mode can be selected by setting the loopback bit in the UART control register UCONn ELECTRONICS 11 7 UART 53 2410 Infra Red Mode The S3C2410A UART block supports infra red IR transmission and reception which be selected by setting the Infra red mode bit in the UART line control register ULCONn Figure 11 4 illustrates how to implement the IR mode In IR transmit mode th
257. ble 0 Disable 1 Enable Transmit DMA service request Receive DMA service request Receive channel idle command In Idle state the IISLRCK is inactive Pause Rx 0 Not idle 1 Idle 0 Disable 1 Enable 0 Disable stop 1 Enable start IIS prescaler IIS interface Transmit channel idle command In Idle state the IISLRCK is inactive Pause Tx 0 Not idle 1 Idle NOTES 1 The IISCON register is accessible for each byte halfword and word unit using STRB STRH STR and LDRB LDRH LDR instructions or char short int int type pointer in Little Big endian mode 2 Li HW W Little HalfWord Word Bi HW W Big HalfWord Word ELECTRONICS 21 5 IIS BUS INTERFACE 53 2410 IIS MODE REGISTER IISMOD REGISTER IISMOD 0x55000004 Li W Li HW Bi W 15 mode register 0x55000006 Bi HW Master slave mode select 0 Master mode IISLRCK and IISCLK are output mode 1 Slave mode IISLRCK and IISCLK are input mode Transmit receive mode select 00 No transfer 01 Receive mode 10 Transmit mode 11 Transmit and receive mode Active level of left right channel 5 0 Low for left channel High for right channel 1 High for left channel Low for right channel Serial interface format IIS compatible format a MSB Left justified format Serial data bit per channel 0 8 bit 1 16 bit Master clock frequency select 0 256fs 1 384fs fs sampling frequency Serial bit clock frequenc
258. c in this mode Activating the Power_OFF mode requires two independent power sources One of the two power sources supplies the power for the wake up logic The other one supplies other internal logics including CPU and should be controlled for power on off In the Power_OFF mode the second power supply source for the CPU and internal logics will be turned off The wakeup from Power_OFF mode can be issued by the EINT 15 0 or by RTC alarm interrupt Procedure to Enter Power_OFF mode 1 Setthe GPIO configuration adequate for Power_OFF mode 2 Mask all interrupts in the INTMSK register Configure the wake up sources properly including RTC alarm The bit of EINTMASK corresponding to the wake up source has not to be masked in order to let the corresponding bit of SRCPND or EINTPEND set Although a wake up source is issued and the corresponding bit of EINTMASK is masked the wake up will occur and the corresponding bit of SRCPND or EINTPEND will not be set 4 Set USB pads as suspend mode MISCCR 13 12 11b 5 Save some meaning values into GSTATUS3 4 register These register are preserved during Power OFF mode 6 Configure MISCCR 1 0 for the pull up resisters on the data bus D 31 0 If there is an external BUS holder such as 74L VCH162245 turn off the pull up resistors If not turn on the pull up resistors 7 Stop LCD by clearing LCDCON1 ENVID bit 8 Read rREFRESH and rCLKCON registers in order to fill the TLB 9 Let SDRAM enter the self
259. can be 1 An expression which generates an address The assembler will attempt to generate an instruction using the PC as base anda corrected immediate offset to address the location given by evaluating the expression This will be a PC relative pre indexed address If the address is out of range an error will be generated 2 A pre indexed addressing specification Rn offset of zero Rn lt expression gt offset of lt expression gt bytes 3 A post indexed addressing specification Rn lt expression offset of lt expression gt bytes n write back the base register set the W bit if is present Rn is an expression evaluating to a valid ARM920T register number NOTE If Rn is R15 the assembler will subtract 8 from the offset value to allow for ARM920T pipelining EXAMPLES LDC p1 c2 table Load c2 of coproc 1 from address table using a PC relative address STCEQL p2 c3 R5 24 Conditionally store c3 of coproc 2 into an address 24 bytes up from 5 write this address back to R5 and use long transfer option probably to store multiple words NOTE Although the address offset is expressed in bytes the instruction offset field is in words The assembler will adjust the offset appropriately ELECTRONICS 3 55 ARM INSTRUCTION SET 53 2410 COPROCESSOR REGISTER TRANSFERS MRC The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The i
260. ce for 64KB large page As the upper four bits of the page index and low order four bits of the coarse page table index overlap each coarse page table entry for a large page must be duplicated 16 times in consecutive memory locations in the coarse page table If a large page descriptor is included in a fine page table the upper six bits of the page index and low order six bits of the fine page table index overlap each fine page table entry for a large page must therefore be duplicated 64 times 3 12 ELECTRONICS ARM920T PROCESSOR MMU Modified virtual address 20 19 1615 12 11 0 Translation table base 1413 Translation base 18 Translation base Table index iD B Level one descriptor O e DI PE 31 10 9 21 0 Coarse page table base address L2 table index 0 0 Level two descriptor 16 15 1211109 8 7 65 4 3 2 1 a Physical address 16 15 Figure 3 7 Large Page Translation from a Coarse Page Table ELECTRONICS 3 13 MMU ARM920T PROCESSOR TRANSLATING SMALL PAGE REFERENCES Figure 3 8 illustrates the complete translation sequence for a 4KB small page If a small page descriptor is included in a fine page table the upper two bits of the page index and low order two bits of the fine page table index overlap Each fine page table entry for a small page must therefore be duplicated four times Modified virtual address 20 19 12 11 Translation table base 1413 Translation base 18 Translation base T
261. cessary Multiply by 4 Test value Complete multiply by 5 Complete multiply by 6 Discrete test Range test IF lt OR Rc ASCII 127 THEN 3 59 ARM INSTRUCTION SET 83 2410 Division and Remainder A number of divide routines for specific applications are provided in source form as part of the ANSI C library provided with the ARM Cross Development Toolkit available from your supplier A short general purpose divide routine follows Enter with numbers in Ra and Rb MOV Rent 1 Bit to control the division Div1 CMP Rb 0x80000000 Move Rb until greater than Ra CMPCC Rb Ra MOVCC Rb Rb ASL 1 MOVCC Rent Rent ASL 1 BCC Div1 MOV Rc 0 Div2 CMP Ra Rb Test for possible subtraction SUBCS Ra Ra Rb Subtract if ok ADDCS Re Re Rent Put relevant bit into result MOVS Rent Rent _LSR 1 Shift control bit MOVNE Rb Rb LSR 1 Halve unless finished BNE Div2 Divide result in Rc remainder in Ra Overflow Detection in the ARM920T 1 Overflow in unsigned multiply with a 32 bit result UMULL Rd Rt Rm Rn 3106 cycles TEQ Rt 0 1 cycle and a register BNE overflow 2 Overflow in signed multiply with a 32 bit result SMULL Rd Rt Rm Rn 3106 cycles TEQ Rt Rd ASR 31 1 cycle and a register BNE overflow 3 Overflow in unsigned multiply accumulate with a 32 bit result UMLAL Rd Rt Rm Rn 4 107 cycles TEQ Rt 0 1 cycle and a register BNE overflow 4 Overflow in signed multiply accumulate
262. ch work as clocks for external sources See the following figure for how to make the DCLKn signals The DCLKCON can actually operate only when CLKOUTT 1 0 is set to send the DCLKn signals DCLKCON 0x56000084 DCLKO 1 control register 0 0 DCLKCON DCLK1CMP 27 24 DCLK1 Compare value clock toggle value lt DCLK1DIV If the DCLK1CMP is n Low level duration is n 1 High level duration is DCLK1DIV 1 n 1 DCLK1DIV 23 20 DCLK1 Divide value DCLK1 frequency source clock DCLK1DIV 1 Reserved 918 ooo DCLK1SeICK 17 Select DCLK1 source clock 0 PCLK 1 UCLK USB DCLK1EN 16 DCLK1 Enable 0 Disable 1 Enable Reserved 15 12 _ 0000b DCLKOCMP 11 8 DCLKO Compare value clock toggle value lt DCLKODIV If the DCLKOCMP is n Low level duration is n 1 High level duration is DCLKODIV 1 n 1 DCLKODIV 7 4 DCLKO Divide value DCLKO frequency source clock DCLKODIV 1 BE DCLKOSeICK 1 Select DCLKO source clock 0 PCLK 1 UCLK USB DCLKOEN DCLKO Enable 0 Disable 1 Enable 1 LJ 1 1 Lz I 1 1 1 1 1 1 1 1 1 1 DCLKnCMP 1 1 DCLKnDIV 1 ELECTRONICS 9 21 PORTS 53 2410 EXTERNAL INTERRUPT CONTROL REGISTER EXTINTn The 24 external interrupts can be requested by various signaling methods The EXTINTn configures the signaling method between the level trigger and edge
263. chronous Mode t ded d p oec t e o p d Het eee Uu E eu eee Asynchronous Mode tia tede ke eerte be dee e de eu oe bea o dee ode opo ua epe e ee 53 2410 MICROPROCESSOR xix List of Figures Figure Title Page Number Number 1 1 S3C2410A Block 1 5 1 2 S3C2410A Pin Assignments 272 1 6 2 1 Big Endian Addresses of Bytes within Words 2 2 2 2 Little Endian Addresses of Bytes within Words sse 2 2 2 3 Register Organization in ARM L eene 2 4 2 4 Register Organization in THUMB 2 5 2 5 Mapping of THUMB State Registers onto ARM State Registers 2 6 2 6 Program Status Register 2 7 3 1 ARM Instruction Set Format l I L n a 3 1 3 2 Branch and Exchange 3 5 3 3 Branch MStruCtOnss iiie eie kaa 3 7 3 4 Data Processing 3 9 3 5 ARM Shift Operation Sisirin edite petentes tet etd eerta 3 12 3 6 Kore e ee INN E 3 12 3 7 Eogical Shift RIONU bete 3 13 3 8 Arithmetic Shift Right 3 13
264. cing the order Technical Manager For duplicate copies of this form and for additional ordering information please contact your local Samsung sales representative Samsung sales offices are listed on the back cover of this book S3C SERIES REQUEST FOR PRODUCTION AT CUSTOMER RISK Customer Information Company Name Department Telephone Number Fax Date Risk Order Information Device Number 3 write down the ROM code number Package Number of Pins Package Type Intended Application Product Model Number Customer Risk Order Agreement We hereby request SEC to produce the above named product in the quantity stated below We believe our risk order product to be in full compliance with all SEC production specifications and to this extent agree to assume responsibility for any and all production risks involved Order Quantity and Delivery Schedule Risk Order Quantity PCS Delivery Schedule Signatures Person Placing the Risk Order SEC Sales Representative For duplicate copies of this form and for additional ordering information please contact your local Samsung sales representative Samsung sales offices are listed on the back cover of this book 53 2410 MASK OPTION SELECTION FORM Device Number 3C2410A write down the ROM code number Attachment Check one Diskette PROM Customer Checksum Company Name Signature E
265. clear or N clear and V set less than 1100 BGT label BGT label Branch if Z clear and either N set and V set or N clear and V clear greater than 1101 BLE label BLE label Branch if Z set or N set and V clear or N clear and V set less than or equal NOTES 1 While label specifies a full 9 bit two s complement address this must always be halfword aligned ie with bit 0 set to 0 since the assembler actually places label gt gt 1 in field SOffset8 2 1110 is undefined and should not be used Cond 1111 creates the SWI instruction see INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 1 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES CMP 45 Branch to over if RO gt 45 BGT over Note that the THUMB opcode will contain the number of halfwords to offset over Must be halfword aligned ELECTRONICS 4 35 THUMB INSTRUCTION SET 83 2410 FORMAT 17 SOFTWARE INTERRUPT 14 13 11 10 15 12 9 8 7 0 ili ves 7 0 Comment Field Figure 4 18 Format 17 OPERATION The SWI instruction performs a software interrupt On taking the SWI the processor switches into ARM state and enters Supervisor SVC mode The THUMB assembler syntax for this instruction is shown below Table 4 18 The SWI Instruction SWI Value 8 SWI Va
266. cription Reset Value SDIDCNT 0x5A000030 SDI data remain counter register 0 0 BlkNumCnt 23 12 Remaining block number 0x000 BlkCnt 11 0 Remaining data byte of 1 block 0x000 ELECTRONICS 19 11 MMC SD SDIO HOST CONTROLLER S3C2410A SDI Data Status SDIDSTA Register Register Address R Description Reset Value AN SDIDSTA 0x5A000034 R W SDI data status register 0x0 Read Wait Read wait request signal transmits to SD card The request Request Occur signal is stopped and this flag is cleared by setting one to this RWaitReq bit for SDIO 0 not occur 1 Read wait request occur SDIO Interrupt Detect lOIntDet SDIO interrupt detects This flag is cleared by setting one to this bit for SDIO 0 not detect 1 SDIO interrupt detect FIFO Fail error FF fail FIFO fail error when FIFO occurs overrun underrun misaligned data saving This flag is cleared by setting one to this bit 0 not detect 1 FIFO fail CRC Status error when data block sent CRC check failed returned from card This flag is cleared by setting one to this bit 0 not detect 1 crc status fail CRC Status Fail CrcSta Data Time Data receive timeout This flag is cleared by setting one to this DatTout bit 0 not detect 1 timeout Data Transfer Data transfer completes data counter is zero This flag is Finish DatFin cleared by setting one to this bit 0 not detect 1 data fin
267. ction EXAMPLES The following sequence performs a mode change MRS RO CPSR Take a copy of the CPSR BIC RO RO 0x1F Clear the mode bits ORR RO RO new_mode Select new mode MSR CPSR RO Write back the modified CPSR When the aim is simply to change the condition code flags in a PSR a value can be written directly to the flag bits without disturbing the control bits The following instruction sets the N Z C and V flags MSR CPSR_flg 0xFO000000 Set all the flags regardless of their previous state does not affect any control bits No attempt should be made to write an 8 bit immediate value into the whole PSR since such an operation cannot preserve the reserved bits INSTRUCTION CYCLE TIMES PSR transfers take 1S incremental cycles where S is defined as Sequential S cycle 3 20 ELECTRONICS 3C2410A ASSEMBLY SYNTAX e MRS transfer PSR contents to a register Rd lt psr gt MSR transfer register contents to PSR lt psr gt Rm ARM INSTRUCTION SET e MSR transfer register contents to PSR flag bits only MSR cond lt psrf gt Rm The most significant four bits of the register contents are written to the N Z C amp V flags respectively e MSR transfer immediate value to PSR flag bits only MSR cond lt psrf gt lt expression gt The expression should symbolise a 32 bit value of which the most significant four bits are written to the N Z C and V flags res
268. cture Reference Manual The ARM9TDMI Technical Reference Manual gives implementation details including instruction execution cycle times The ARM v4T architecture specifies small number of implementation options The options selected in the ARM9TDMI implementation are listed Table 2 1 For comparison the options selected for the ARM7TDMI implementation are also shown Table 2 1 ARM9TDMI Implementation Option Processor core ARM architecture Data abort model Value stored by direct STR STRT STM of PC Base updated Address of Inst 12 The ARM9TDMI is code compatible with the ARM7TDMI with two exceptions The ARM9TDMI implements the base restored data abort model which significantly simplifies the software data abort handler e The ARM9TDMI fully implements the instruction set extension spaces added to the ARM 32 bit instruction set in architecture v4 and v4T These differences are explained in more detail below DATA ABORT MODEL The base restored data abort model differs from the base updated data abort model implemented by ARM7TDMI The difference in the data abort model affects only a very small section of operating system code the data abort handler It does not affect user code With the base restored data abort model when a data abort exception occurs during the execution of a memory access instruction the base register is always restored by the processor hardware to the value the register con
269. cycle written at any point in the current PWM cycle by ISR or other routine ELECTRONICS 10 7 PWM TIMER 3 2410 OUTPUT LEVEL CONTROL Inverter off l l l l l Inverter on _______ Initial State Period 1 Period2 1 Stop Figure 10 6 Inverter On Off The following procedure describes how to maintain TOUT as high or low assume the inverter is off 1 Turn off the auto reload bit And then TOUTn goes to high level and the timer is stopped after the TCNTn reaches 0 recommended 2 Stop the timer by clearing the timer start stop bit to 0 If lt TCMPn the output level is high If TCNTn gt the output level is low 3 The TOUTn can be inverted by the inverter on off bit in TCON The inverter removes the additional circuit to adjust the output level 10 8 ELECTRONICS 53 2410 PWM TIMER DEAD ZONE GENERATOR The dead zone is for the PWM control in a power device This function enables the insertion of the time gap between a turn off of a switching device and a turn on of another switching device This time gap prohibits the two switching devices from being turned on simultaneously even for a very short time TOUTO is the PWM output nTOUTO is the inversion of the TOUTO If the dead zone is enabled the output wave form of TOUTO and nTOUTO will be TOUTO DZ and nTOUTO 02 respectively nNTOUTO_DZ is routed to the TOUT pin In the dead zone interval TOUTO DZ and nTOUT
270. d R11 with the sign extended contents of the halfword address contained in RO Generate PC relative offset to address FRED Store the halfword in R5 at address FRED 3 39 ARM INSTRUCTION SET 53 2410 BLOCK DATA TRANSFER LDM STM The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 18 Block data transfer instructions are used to load LDM or store STM any subset of the currently visible registers They support all possible stacking modes maintaining full or empty stacks which can grow up or down memory and are very efficient instructions for saving or restoring context or for moving large blocks of data around main memory THE REGISTER LIST The instruction can cause the transfer of any registers in the current bank and non user mode programs can also transfer to and from the user bank see below The register list is a 16 bit field in the instruction with each bit corresponding to a register A 1 in bit 0 of the register field will cause RO to be transferred a 0 will cause it not to be transferred similarly bit 1 controls the transfer of R1 and so on Any subset of the registers or all the registers may be specified The only restriction is that the register list should not be empty Whenever R15 is stored to memory the stored value is the address of the STM instruction plus 12 31 28 27 25 24 23 22 21 20 19 16 15 0
271. d have overwritten the base with data ie it has the base in the transfer list the overwriting is prevented All register overwriting is prevented after an abort is indicated which means in particular that R15 always the last register to be transferred is preserved in an aborted LDM instruction The abort mechanism allows the implementation of a demand paged virtual memory system In such a system the processor is allowed to generate arbitrary addresses When the data at an address is unavailable the Memory Management Unit MMU signals an abort The abort handler must then work out the cause of the abort make the requested data available and retry the aborted instruction The application program needs no knowledge of the amount of memory available to it nor is its state in any way affected by the abort After fixing the reason for the abort the handler should execute the following irrespective of the state ARM or Thumb SUBS PC R14_abt 4 fora prefetch abort or SUBS PC R14 abt 48 for a data abort This restores both the PC and the CPSR and retries the aborted instruction 2 12 ELECTRONICS 3C2410A PROGRAMMER S MODEL Software Interrupt The software interrupt instruction SWI is used for entering Supervisor mode usually to request a particular supervisor function A SWI handler should return by executing the following irrespective of the state ARM or Thumb MOV PC R14 svc This restores the PC and CPSR and returns to
272. d write buffer configuration for each memory region When the DCache is disabled the cache contents are ignored and all data accesses appear on the Advanced System Bus as separate non sequential accesses If the cache is subsequently re enabled its contents will be unchanged Depending on the software system design the cache may need to be cleaned after it is disabled and invalidated before it is re enabled See Cache coherence on page 4 10 The MMU and DCache can be enabled or disabled simultaneously with a single MCR which changes bit 0 and bit 2 in the control register CP15 register 1 DATA CACHE AND WRITE BUFFER OPERATION The DCache and write buffer configuration of each memory region is controlled by the C and B bits in each section and page descriptor in the MMU translation tables For clarity these bits are referred to as Ctt and Bit in the following text The configuration is modified by the DCache enable bit in the CP15 control register which is referred to as If the DCache is enabled DCache lookup is performed for each data access initiated by the ARM9TDMI CPU core regardless of the value of the Ctt bit in the relevant MMU translation table descriptor If the accessed virtual address matches the virtual address of an entry in the cache the lookup is called a cache hit If the required address does not match any entry in the cache the lookup is called a cache miss In this context a data access means any type of load re
273. ddresses Bank 6 Start address 0 3000_0000 0x3000 0000 0x3000_0000 0x3000_0000 0x3000_0000 0x3000_0000 0x3000_0000 End address 0 3011 ffff 0 3031 0x3071 Ox30ff 0x31 0x33ff_ffff 0x37ff_ffff Bank 7 Start address 0x3020_0000 0x3040_0000 0x3080_0000 0x3100_0000 0x3200_0000 0x3400_0000 0x3800_0000 End address 0 3031 0 3071 OxSOff ffff 0x31 ff_ffff 0x33ff_ffff 0x37ff_ffff Ox3fff_ffff NOTE Bank 6 and 7 must have the same memory size 5 2 ELECTRONICS 53 2410 MEMORY CONTROLLER FUNCTION DESCRIPTION BANKO BUS WIDTH The data bus of BANKO 50 should be configured to either 16 bit or 32 bit accordingly Because the BANKO works as the booting ROM bank map to 0x0000_0000 the bus width of BANKO should be determined before the first ROM access which will depend on the logic level of OM 1 0 at Reset OM1 Operating Mode 1 Operating Mode 0 Booting ROM Data width 09 UL sw o H i MEMORY SROM SDRAM ADDRESS PIN CONNECTIONS MEMORY ADDR PIN 3C2410A ADDR 53 2410 ADDR 3C2410A ADDR 8 bit DATA BUS 16 bit DATA BUS 32 bit DATA BUS ELECTRONICS 5 3 MEMORY CONTROLLER 53 2410 SDRAM BANK ADDRESS CONNECTION Table 5 2 SDRAM Bank Address Configuration se p tm Memory Configuration Bank Address 16Mb 1M x 8 x 2banks x 1 ea 16Mb 2Mx 4x 2 4x2banks x2ea x2ea BB x 16 x 2banks 2
274. ddressing Mode Names Se om vm ostnerement Load 9 imm o DA wm 9 9 mememwsee sw sme o Fostinerement sore sm o o Preecrement sw sm o o ostDecrement Sine smeo smo e o o FD ED FA EA define pre post indexing and the up down bit by reference to the form of stack required The F and E refer to a full or empty stack i e whether a pre index has to be done full before storing to the stack The A and D refer to whether the stack is ascending or descending If ascending a STM will go up and LDM down if descending vice versa IA IB DA DB allow control when LDM STM are not being used for stacks and simply mean Increment After Increment Before Decrement After Decrement Before ELECTRONICS 3 45 ARM INSTRUCTION SET EXAMPLES LDMFD 1 2 STMIA RO RO R15 LDMFD 15 LDMFD 15 STMFD 13 0 14 53 2410 Unstack 3 registers Save all registers R15 SP CPSR unchanged R15 SP CPSR lt SPSR_mode allowed only in privileged modes Save user mode regs on stack allowed only in privileged modes These instructions may be used to save state on subroutine entry and restore it efficiently on return to the calling routine STMED SP RO R3 R14 BL somewhere LDMED SP RO R3 R15 3
275. device controller All special function register is byte accessible or word accessible If you access byte mode offset address is different in little endian and big endian All reserved bit is zero Common indexed registers depend on INDEX register INDEX_REG offset address 0x178 value For example if you want to write EPO CSR register you must write 0x00 on the INDEX_REG before writing IN CSR1 register NOTE All register must be resettled after performing Host Reset Signaling Register Name Description NON INDEXED REGISTERS FUNC ADDR REG PWR REG Offset Address 0x140 L Ox144 L 0x143 0x147 L 0 14 USB interrupt register 0x158 L 0x15B 0x15C L Ox15F B 0x16C L Ox16F B L 0x173 B Frame number 2 register 0x174 L 0x177 B 0x178 L 0x17B EndpointO FIFO register 0x1CO0 L 0x1C3 EP1 FIFO REG Endpoint1 FIFO register 0x1C4 L 0x1C7 EP2 FIFO REG Endpoint2 FIFO register 0x1C8 L 0x1CB B EP3 FIFO REG Endpoint3 FIFO register 0x1CC L Ox1CF B 4 FIFO REG Endpoint4 FIFO register 0x1DO L 0x1D3 B EP1 DMA CON Endpoint1 DMA control register 0x200 L 0x203 B EP1 DMA UNIT Endpoint DMA unit counter register 0x204 L 0x207 B FIFO Endpoint DMA FIFO counter register 0x208 L 20 EP1_DMA_TTC_L Ox20C L 0 20 EP1_DMA_TTC_M 0x210 L Ox213 B EP1_DMA_TTC_H 0x214 L 0x217 B EP2_DMA_CON 0x218 L 0x21B B EP2 DMA UNIT L 0 21 EP2 DMA FIFO L 0x223 B EP2 DMA TTC L L
276. down state 1 Stylus up state AUTO_PST 14 Automatic sequencing conversion of X position and Y position 0 Normal ADC conversion 1 Sequencing measurement of X position Y position mug XPDATA X position conversion data value include Normal ADC conversion data Normal ADC value Data value 0 XY PST 13 12 Manual measurement of X position or Y position 00 No operation mode 01 X position measurement 10 Y position measurement 11 Waiting for Interrupt Mode 16 10 ELECTRONICS 53 2410 ADC AND TOUCH SCREEN INTERFACE ADC CONVERSION DATA ADCDAT1 REGISTER ADCDAT1 0x58000010 R ADC conversion data register o UPDOWN 15 Up or down state of Stylus at Waiting for Interrupt Mode 0 Stylus down state 1 Stylus up state AUTO_PST 14 Automatically sequencing conversion of X position and Y position 0 Normal ADC conversion 1 Sequencing measurement of X position Y position ma YPDATA 9 0 Y position conversion data value Data value 0 XY PST 13 12 Manual measurement of X position or Y position 00 No operation mode 01 X position measurement 10 Y position measurement 11 Waiting for Interrupt Mode ELECTRONICS 16 11 ADC AND TOUCH SCREEN INTERFACE S3C2410A NOTES 16 12 ELECTRONICS 3C2410A REAL TIME CLOCK RTC REAL TIME CLOCK RTC OVERVIEW The Real Time Clock RTC unit can be operated by the backup battery while the system power is off The RTC
277. ds it into this register automatically RIW Reset Value FRAME 1 REG 0x52000170 L R Frame number lower byte register 0x00 0x52000173 B byte FRAME NUM 1 7 0 R w Frame number lower byte value O FRAME_NUM2_REG 0x52000174 L R Frame number higher byte register 0x00 0x52000177 B byte FRAME_NUM2 7 0 w _ Frame number higher byte value O 13 10 ELECTRONICS 53 2410 USB DEVICE INDEX REGISTER INDEX_REG The INDEX register is used to indicate certain endpoint registers effectively The MCU can access the endpoint registers MAXP_REG IN_CSR1_REG IN CSR2 REG OUT_CSR1_REG OUT CSR2 REG OUT_FIFO_CNT1_REG and OUT_FIFO_CNT2_REG for an endpoint inside the core using the INDEX register RIW Reset Value INDEX REG 0x52000178 L R W Register index register 0x00 0x5200017B B byte INDEX 7 0 RW R Indicate a certain endpoint O ELECTRONICS 13 11 USB DEVICE 53 2410 END POINTO CONTROL STATUS REGISTER CSR This register has the control and status bits for Endpoint 0 Since a control transaction is involved with both IN and OUT tokens there is only one CSR register mapped to the CSR1 register share INT CSR and can access by writing index register 0 and read write INT CSR Reset Value EPO CSR 0x52000184 L R W Endpoint 0 status register 0x00 0 52000187 byte SERVICED SETUP _ 7 W CLEAR The MCU should write a 1 to this bit to END clear SET
278. ds the deasserted DREQ it deasserts DACK and waits for another asserted DREQ In contrast in the Demand mode DMA controller does not wait until the DREQ is deasserted It just deasserts DACK and then starts another transfer if DREQ is asserted We recommend using Handshake mode for external DMA request sources to prevent unintended starts of new transfers SYNC 30 Select DREQ DACK synchronization 0 DREQ and DACK are synchronized to PCLK APB clock 1 DREQ and are synchronized to HCLK AHB clock Therefore for devices attached to AHB system bus this bit has to be set to 1 while for those attached to APB system it should be set to 0 For the devices attached to external systems the user should select this bit depending on which the external system is synchronized with between AHB system and APB system INT i e CURR_TC becomes 0 TSZ 28 Select the transfer size of an atomic transfer i e transfer performed each time DMA owns the bus before releasing the bus 0 a unit transfer is performed 1 a burst transfer of length four is performed ELECTRONICS 8 9 29 Enable Disable the interrupt setting for CURR_TC terminal count 0 CURR_TC interrupt is disabled The user has to view the transfer count in the status register i e polling 1 interrupt request is generated when all the transfer is done DMA 53 2410 DMA CONTROL REGISTER Continued SERVMODE HWSRCSEL SWHW SEL RELOAD Se
279. e Supports the monochrome 4 gray levels and 16 gray levels Supports 256 colors and 4096 colors for color STN LCD panel Supports multiple screen size Typical actual screen size 640x480 320x240 160x160 and others Maximum virtual screen size is 4Mbytes Maximum virtual screen size in 256 color mode 4096x1024 2048x2048 1024x4096 and others TFT LCD displays Supports 1 2 4 or 8 bpp bit per pixel palettized color displays for TFT Supports 16 bpp non palettized true color displays for color TFT Supports 24 bpp non palettized true color displays for color TFT Supports maximum 16M color TFT at 24 bit per pixel mode Supports multiple screen size Typical actual screen size 640x480 320x240 160x160 and others Maximum virtual screen size is 4Mbytes Maximum virtual screen size in 64K color mode 2048x1024 and others ELECTRONICS 15 1 LCD CONTROLLER S3C2410A COMMON FEATURES The LCD controller has a dedicated DMA that supports to fetch the image data from video buffer located in system memory Its features also include Dedicated interrupt functions INT_FrSyn and INT_FiCnt The system memory is used as the display memory Supports Multiple Virtual Display Screen Supports Hardware Horizontal Vertical Scrolling Programmable timing control for different display panels Supports little and big endian byte ordering as well as WinCE data formats Supports SEC TFT LCD panel SAMSUNG 3 5 Portrait
280. e 13 Control PCLK into GPIO block 0 Disable 1 Enable UART2 12 Control PCLK into UART2 block 0 Disable 1 Enable UART1 11 Control PCLK into UART1 block 0 Disable 1 Enable Control into UARTO block 0 Disable 1 Enable Control PCLK into SDI interface block 0 Disable 1 Enable PWMTIMER Control PCLK into PWMTIMER block 0 Disable 1 Enable USB device 7 Control PCLK into USB device block 0 Disable 1 Enable USB host Control HCLK into USB host block 0 Disable 1 Enable LCDC 5 Control HCLK into LCDC block 0 Disable 1 Enable NAND Flash Controller 4 Control HCLK into NAND Flash Controller block 0 Disable 1 Enable POWER_OFF 3 Control Power Off mode of 5362410 0 Disable 1 Transition to Power OFF mode IDLE BIT 2 Enter IDLE mode This bit is not cleared automatically 0 Disable 1 Transition to IDLE mode Reseved Reseved 2 SM BIT SPECIAL mode 0 is recommended normally This bit can be used to enter SPECIAL mode in only the special condition OM3 1 amp wake up by nRESET Please contact us to use this bit ELECTRONICS 7 21 CLOCK amp POWER MANAGEMENT 53 2410 CLOCK SLOW CONTROL CLKSLOW REGISTER CLKSLOW 0x4C000010 Slow clock control register 0x00000004 UCLK ON 7 0 UCLK ON UPLL is also turned on and the UPLL lock time is inserted automatically 1 UCLK OFF UPLL is also turned off MPLL OFF 5 0 PLL is turned on Aft
281. e 1 drive the previous level The SPIMISO MISO and SPIMOSI MOSI data pins are used for transmitting and receiving serial data When the SPI is configured as a master SPIMISO MISO is the master data input line SPIMOSI MOSI is the master data output line and SPICLK SCK is the clock output line When the SPI becomes a slave these pins perform reversed roles In a multiple master system SPICLK SCK pins SPIMOSI MOSI pins and SPIMISO MISO pins are tied to configure a group respectively A master SPI can experience a multi master error when other SPI device working as a master selects the 53 2410 SPI as a slave When this error is detected the following actions are taken immediately But you must previously set SPPINn s ENMUL bit if you want to detect this error 1 The SPCONn s MSTR bit is forced to 0 to operate slave mode 2 The SPSTAn s MULF flag is set and an SPI interrupt is generated ELECTRONICS 22 9 SPI INTERFACE 3C2410A SPI Baud Rate Prescaler Register Register Address R W Description Reset Value SPPREO 0x5900000C SPI cannel 0 baud rate prescaler register SPPRE1 0x5900002C SPI cannel 1 baud rate prescaler register Prescaler Value 7 0 Determine SPI clock rate as above equation 0x00 Baud rate PCLK 2 Prescaler value 1 NOTE Baud rate should be less than 25 MHz SPI Tx Data Register SPTDATO 0x59000010 SPI channel 0 Tx data register SPTDAT1 0x59000030 SPI channel 1 Tx data register
282. e ARM920T such as big or little endian operation The registers defined in CP15 are accessible with MCR and MRC instructions These are described in CP15 register map summary on page 2 4 The ARM920T also features an external coprocessor interface which allows the attachment of a closely coupled coprocessor on the same chip for example a floating point unit Registers and operations provided by any coprocessors attached to the external coprocessor interface will be accessible with appropriate coprocessor instructions Memory accesses for instruction fetches and data loads and stores may be cached or buffered Cache and write buffer configuration and operation is described in detail in following chapters The MMU page tables which reside in main memory describe the virtual to physical address mapping access permissions and cache and write buffer configuration These are created by the operating system software and accessed automatically by the ARM920T MMU hardware whenever an access causes a TLB miss The ARM920T has a Trace Interface Port which allows the use of Trace hardware and tools for real time tracing of instructions and data ELECTRONICS 2 1 PROGRAMMER S MODEL ARM920T PROCESSOR ABOUT THE ARM9TDMI PROGRAMMER S MODEL The ARM9TDMI processor core implements ARM v4T architecture and so executes the ARM 32 bit instruction set and the compressed Thumb 16 bit instruction set The programmer s model is fully described in the ARM Archite
283. e LCD controller can be directly connected to the LCD driver and the 4 pins VD 7 4 for the LCD output are not used 8 bit Single Scan Display Type An 8 bit single scan display uses 8 parallel data lines to shift data to successive single horizontal lines of the display at a time until the entire frame has been shifted and transferred The 8 pins VD 7 0 for the LCD output from the LCD controller can be directly connected to the LCD driver 256 Color Displays Color displays require 3 bits Red Green and Blue of image data per pixel and so the number of horizontal shift registers for each horizontal line corresponds to three times the number of pixels of one horizontal line resulting in a horizontal shift register of length 3 times the number of pixels per horizontal line This RGB is shifted to the LCD driver as consecutive bits via the parallel data lines Figure 15 3 shows the RGB and order of the pixels in the parallel data lines for the 3 types of color displays 4096 Color Displays Color displays require 3 bits Red Green and Blue of image data per pixel and so the number of horizontal shift registers for each horizontal line corresponds to three times the number of pixels of one horizontal line This RGB is shifted to the LCD driver as consecutive bits via the parallel data lines This RGB order is determined by the sequence of video data in video buffers 15 8 ELECTRONICS 3C2410A LCD CONTROLLER MEMORY DATA FORMAT STN
284. e EINTn in the GPIO control register as an external interrupt pins considering the condition a above Just after the wake up the corresponding EINTn pin will not be used for wakeup This means that the pin can be used as an external interrupt request pin again Entering IDLE Mode If CLKCON 2 is set to 1 to enter the IDLE mode the S3C2410A will enter IDLE mode after some delay until the power control logic receives ACK signal from the CPU wrapper PLL On Off The PLL can only be turned off for low power consumption in slow mode If the PLL is turned off in any other mode MCU operation is not guaranteed When the processor is in SLOW mode and tries to change its state into other state with the PLL turned on then SLOW BIT should be clear to move to another state after PLL stabilization Pull up Resistors on the Data Bus and Power OFF Mode In Power OFF mode the data bus D 31 0 or D 15 0 is in Hi z state But because of the characteristics of I O pad the data bus pull up resistors have to be turned on for low power consumption in Power OFF mode D 31 0 pin pull up resistors can be controlled by the GPIO control register MISCCR However if there is an external bus holder such as 74LVCH162245 on the data bus turning off the data bus pull up resistors will be reduce power consumption ELECTRONICS 7 17 CLOCK amp POWER MANAGEMENT S3C2410A Output Port State and Power_OFF Mode The output port should have a proper logic l
285. e RR bit in the CP15 control register CP15 register 1 bit 14 Random replacement is selected at reset Setting the RR bit to 1 selects round robin replacement INSTRUCTION CACHE LOCKDOWN Instructions can be locked into the causing the ICache to guarantee a hit and providing optimum and predictable execution time Instructions are locked into the by first ensuring the code to be locked is not already in the cache This is tested by flushing either the whole or specific lines A short software routine can then be used to load the instructions into the ICache The software routine must either be non cacheable or already in the ICache but not in an line which is about to be overwritten The instructions to be loaded must be from a memory region which is cacheable The software routine operates by writing to CP15 register 9 to force the replacement counter to a specific ICache line and by using the prefetch ICache line operation available via CP15 register 7 to force the ICache to perform a lookup This will miss and a linefill will be performed loading the cache line into the entry specified by the replacement counter Once all the instructions have been loaded they are then locked by writing to CP15 register 9 to set the replacement counter base to be one higher than the number of locked cache lines See Data cache lockdown on page 4 9 for a more complete explanation of cache locking 4 4 ELE
286. e X Y Position Conversion Mode 16 4 16 2 Condition of Touch Screen Panel Pads in Auto Sequential X Y Position Conversion nt eat een dnt ie 16 5 16 3 Condition of Touch Screen Panel Pads in Waiting for Interrupt 16 5 21 1 CODEC clock CODECLK 256 3846 sse 21 4 21 2 Usable Serial Bit Clock Frequency IISCLK 16 or 32 or 48 5 21 5 24 1 Absolute Maximum 24 1 24 2 Recommended Operating Conditions 24 1 24 3 Normal I O PAD DC Electrical 0 24 2 24 4 USB DC Electrical 24 3 24 5 S3C2410A Power Supply Voltage and 24 3 24 6 Glock Timing Constants ete Late t e Lfd 24 31 24 7 ROM SRAM Bus Timing Constants rasa 24 32 24 8 Memory Interface Timing Constants 24 32 24 9 External Bus Request Timing 24 33 24 10 DMA Controller Module Signal Timing 24 33 24 11 TFT LCD Controller Module Signal Timing Constant 24 34 24 12 IIS Controller Module Signal Timing Constants 24 34 24 13 IIC BUS Controller
287. e base is in the list DATA ABORTS Some legal addresses may be unacceptable to a memory management system and the memory manager can indicate a problem with an address by taking the ABORT signal HIGH This can happen on any transfer during a multiple register load or store and must be recoverable if ARM920T is to be used in a virtual memory system Abort during STM Instructions If the abort occurs during a store multiple instruction ARM920T takes little action until the instruction completes whereupon it enters the data abort trap The memory manager is responsible for preventing erroneous writes to the memory The only change to the internal state of the processor will be the modification of the base register if write back was specified and this must be reversed by software and the cause of the abort resolved before the instruction may be retried Aborts during LDM Instructions When ARM920T detects a data abort during a load multiple instruction it modifies the operation of the instruction to ensure that recovery is possible Overwriting of registers stops when the abort happens The aborting load will not take place but earlier ones may have overwritten registers The PC is always the last register to be written and so will always be preserved e The base register is restored to its modified value if write back was requested This ensures recoverability in the case where the base register is also in the transfer list and may ha
288. e burst mode address is increased during the burst transfer but the address is recovered to its first value after the transfer ELECTRONICS 8 7 DMA S3C2410A DMA INITIAL DESTINATION DIDST REGISTER D_ADDR 30 0 Base address start address of destination for the transfer This bit 0x00000000 value will be loaded into CURR_SRC only if the CURR_DST is 0 and the DMA ACK is 1 DMA INITIAL DESTINATION CONTROL DIDSTC REGISTER Bit 1 is used to select the location of destination 0 the destination is in the system bus 1 the destination is in the peripheral bus APB Bit 0 is used to select the address increment 0 Increment 1 Fixed If it is 0 the address is increased by its data size after each transfer in burst and single transfer mode If it is 1 the address is not changed after the transfer In the burst mode address is increased during the burst transfer but the address is recovered to its first value after the transfer 8 8 ELECTRONICS 3C2410A DMA DMA CONTROL DCON REGISTER DMD_HS 31 Select one between Demand mode and Handshake mode 0 Demand mode is selected 1 Handshake mode is selected In both modes DMA controller starts its transfer and asserts DACK for a given asserted DREQ The difference between the two modes is whether it waits for the deasserted DACK or not In the Handshake mode DMA controller waits for the deasserted DREQ before starting a new transfer If it fin
289. e contents will not be modified This includes the read portion of a swap SWP or SWPB instruction A write to a non cacheable NCB or NCNB region which unexpectedly hits in the cache will update the cache and will still cause an access on the ASB PHYSICAL ADDRESS TAG RAM The ARM920T implements a PA TAG RAM in order to perform write backs from the data cache A write back occurs when dirty data that is about to be overwritten by linefill data comes from a memory region that is marked as a write back region This data is written back to main memory to maintain memory coherency Dirty data is data that has been modified in the cache but not updated in main memory When a line is written into the data cache the physical address TAG DPA 31 5 is written into the PA TAG RAM If this line comes to be written back to main memory the PA TAG RAM is indexed into by the data cache and the physical address WBPA 31 0 is returned to the AMBA Bus interface so that it can perform the write back The PA TAG RAM Array for a 16k data cache comprises 8 segments x 64 rows segment x 26 bits row There are two test interfaces to the PA TAG RAM Debug interface see Scan chain 4 debug access to the PA TAG RAM AMBA test interface see PA TAG RAM test 4 12 ELECTRONICS ARM920T PROCESSOR CLOCK MODES Appendix 5 CLOCK MODES OVERVIEW The ARM920T has two functional clock inputs and FCLK Internally the 920 is clocked by GCLK
290. e count value for UCLK OxFFF U_LTIME gt 150uS M_LTIME 11 0 MPLL lock time count value for HCLK and PCLK OxFFF M LTIME 150uS PLL Control Register MPLLCON and UPLLCON m Fin p 2 m MDIV 8 p PDIV 2 s SDIV NOTE Although there is the rule for choosing PLL value we recommend only the values in the PLL value recommendation table If you have to use another value please contact us MPLLCON 0x4C000004 MPLL configuration register 0x0005C080 UPLLCON 0x4C000008 UPLL configuration register 0x00028080 m asot NOTE When you set MPLL amp UPLL values simultaneously set UPLL value first and then MPLL value Needs intervals approximately 7 NOP ELECTRONICS 7 19 CLOCK amp POWER MANAGEMENT 53 2410 PLL VALUE SELECTION TABLE It is not easy to find a proper PLL value So We recommend referring to the following PLL value recommendation table wow NOTE The 48 00 2 output is used for UPLLCON register 7 20 ELECTRONICS 53 2410 CLOCK 8 POWER MANAGEMENT CLOCK CONTROL REGISTER CLKCON CLKCON 0 4 00000 Clock generator control register Ox7FFFO CLKCON __ Bit Description Initial State Control PCLK into SPI block 0 Disable 1 Enable Control PCLK into IIS block 0 Disable 1 Enable Control PCLK into RTC control block Even if this bit is cleared to 0 RTC timer is alive 0 Disable 1 Enabl
291. e transmit pulse comes out at a rate of 3 16 the normal serial transmit rate when the transmit data bit is zero In IR receive mode the receiver must detect the 3 16 pulsed period to recognize a zero value see the frame timing diagrams shown in Figure 11 6 and 11 7 IrDA Tx IrDA Rx Encoder Decoder Figure 11 4 IrDA Function Block Diagram 11 8 ELECTRONICS 3C2410A UART 4 510 Frame gt Stat 4 Data Bits _ Stop 4 Figure 11 5 Serial 1 Frame Timing Diagram Normal UART IR Transmit Frame F n start 4 Data Bits Stop 4 lt Pulse Width 3 16 Bit Frame Figure 11 6 Infra Red Transmit Mode Frame Timing Diagram 4 IR Receive Frame gt gt c sP N Start Datta Bis Stop Figure 11 7 Infra Red Receive Mode Frame Timing Diagram ELECTRONICS 11 9 UART 53 2410 UART SPECIAL REGISTERS UART LINE CONTROL REGISTER There are three UART line control registers including ULCONO ULCON1 and ULCON2 in the UART block meme m Infra Red Mode Determine whether or not to use the Infra Red mode 0 Normal mode operation 1 Infra Red Tx Rx mode Ec Parity Mode 5 3 Specify the type of parity generation and checking during UART transmit and receive operation No parity 100 Odd parity 101 Even par
292. ed in the IICCON register The interface address is stored in the IIC bus address IICADD register By default the interface address has an unknown value 20 6 ELECTRONICS 53 2410 IIC BUS INTERFACE FLOWCHARTS OF OPERATIONS IN EACH MODE The following steps must be executed before any IIC Tx Rx operations 1 Write own slave address on IICADD register if needed 2 Set IICCON register a Enable interrupt b Define SCL period 3 IICSTAT to enable Serial Output Master Tx mode has been configured Write slave address to IICDS Write OxFO M T Start to IICSTAT The data of the IICDS is transmitted ACK period and then interrupt is pending Write OxDO M T Stop to IICSTAT N Write new data transmitted to IICDS Clear pending bit to resume The data of the IICDS is shifted to SDA Clear pending bit Wait until the stop condition takes effect Figure 20 6 Operations for Master Transmitter Mode ELECTRONICS 20 7 IIC BUS INTERFACE 53 2410 START Master Rx mode has been configured Write slave address to IICDS Write OxBO M R Start to IICSTAT The data of the IICDS slave address is transmitted ACK period and then interrupt is pending Read a new data from Write 0x90 M R Stop to IICDS IICSTAT Clear pending bit to Clear pending bit Wait until the stop SDA is shifted to IICDS condition t
293. egisters Register Address Address Read Function Name B Endian L Endian Write Memory Controller BWSCON 0x48000000 lt W R W Bus Width Wait Status Control Boot ROM Control MRSRB6 0x4800002C Mode register set for SDRAM MRSRB7 0x48000030 Mode register set for SDRAM 1 26 ELECTRONICS 3 2410 PRODUCT OVERVIEW Table 1 4 S3C2410A Special Registers Continued Register Name Address Address B Endian L Endian USB Host Controller HcRevision HcControl HcCommonsStatus HclnterruptStatus Control and Status Group 0x4900000C HclnterruptEnable 0x49000010 HclnterruptDisable 0x49000014 HcHCCA 0x49000018 Memory Pointer Group HcControlHeadED 0x49000020 Frame Counter Group Interrupt Controller Interrupt Controller SRCPND 0X4A000000 Interrupt Request Status INTMOD 0X4A000004 ow Interrupt Mode Control INTMSK 0X4A000008 Interrupt Mask Contro Root Hub Group W Q Pry Contr source ofset ELECTRONICS 1 27 PRODUCT OVERVIEW 3 2410 Table 1 4 S3C2410A Special Registers Continued Register Address Address Read Name B Endian L Endian Write DMA 0 Current Source DCDSTO 0x4B00001C DMA 0 Current Destination DMA 1 Initial Source DMA 1 Initial Source Control DMA 1 Initial Destination DMA 1 Initial Destination Control 0x4B000050 DMA 1 Contro
294. egment See Data cache organization on page 4 9 DCache ICache and memory coherence is generally achieved by cleaning the DCache to ensure memory is up to date with all changes e invalidating the ICache to ensure that the ICache is forced to re load instructions from memory Software can minimize the performance penalties of cleaning and invalidating caches by e Cleaning only small portions of the cache when only a small area of memory needs to be made coherent for example when updating an exception vector entry e invalidating only small portions of the ICache when only a small number of instructions are modified for example when updating an exception vector entry e invalidating the ICache in situations where it is known that the modified area of memory cannot be in the cache for example when mapping a new page into the currently running process The ICache needs to be made coherent with a changed area of memory after any changes to the instructions which appear at a virtual address and before the new instructions are executed Dirty data in the DCache can be pushed out to main memory by cleaning the cache 4 10 ELECTRONICS ARM920T PROCESSOR CACHES WRITE BUFFER Situations which necessitate cache cleaning and invalidating include e writing instructions to a cacheable area of memory using STR or STM instructions for example self modifying code JIT compilation copying code from another location
295. el tuve dp ee atto eed eti 5 5 Programmable Access Cycle siete eee reete ei iach aha nag 5 11 Bus Width amp Wait Control Register BWSCON sse enne 5 13 Bank Control Register BANKCONN 50 95 5 15 Bank Control Register BANKCONN NGCS6 NGCS7 eene nnne 5 16 Refresh Control Register vaca u citt ee nette n eet 5 17 Banksize Register iim tg rtc Pa ete Gene tete te oq teet det aee 5 18 SDRAM Mode Register Set Register MRSR I 5 19 viii 3C2410A MICROPROCESSOR Table of Contents Continued Chapter 6 NAND Flash Controller OM PEE 6 1 zu 6 1 ori PER ead esr uin rated euch oix Rd 6 2 Operation Schieme segetes E 6 2 Auto Boot Mode 6 3 Nand Flash Mode 6 3 Flash Memory rere et REFERRE ORE ste ri FRE 6 3 STe Info Ur NIETO EUER 6 4 Boot Nand Flash Configurations n enne 6 4 512 Byte Ecc Parity Code Assignment 6 4 Nand Flash Memory
296. en two bus masters in a multi master bus system This could be two processors or a processor and a DMA controller When a swap instruction accesses a cacheable region of memory WT or WB the DCache and write buffer behavior will be the same as having a load followed by a store according to the normal rules described The BLOK pin will not be asserted during the execution of the instruction It is guaranteed that no interrupt can occur between the load and store portions of the swap When a swap instruction accesses a non cacheable NCB or NCNB region of memory the write buffer is drained and a single word or byte will be read from the ASB The write portion of the swap will then be treated as non bufferable regardless of the value of Btt and the processor stalled until the write is completed on the ASB The BLOK pin will be asserted to indicate that the read and write should be treated as an atomic operation on the bus Like all other data accesses a swap to a non cacheable region which hits in the cache indicates a programming error 4 8 ELECTRONICS ARM920T PROCESSOR CACHES WRITE BUFFER DATA CACHE ORGANIZATION The DCache is organized as 8 segments each containing 64 lines and each line containing 8 words The line s position within its segment is a number from 0 to 63 which is called the index A line in the cache can be uniquely identified by its segment and index The index is independent of the line s virtual address The segm
297. enne nennen enne 16 11 Chapter 17 Real Time Clock RTC xiv OVOIVIOW e oi eeu ble t a 17 1 Features iti dtt re eet ede deti bie oet ata 17 1 R al Time Glock Operation tete eere pee 17 2 Leap Year Generators suene tia edit etant ei awia a yaaa 17 2 Read Write ai Wie tila n ded ah Dee LO E ARRA 17 3 Backup Battery Operation ee deett ten apt eee ea te etd einai 17 8 cs Ret e Rete iei e e HER ne 17 3 Tiek Time Pret iether 17 3 Round Reset Function iuo e eet ie ed et e ede et 17 3 32 768kHz X Tal Connection 17 4 Real Time Clock Special Registers U n nnns nnne nnne 17 5 Real Time Clock Control RTCCON 17 5 Tick Time Count TICNT 17 5 RTC Alarm Control RTCALM 17 6 Alarm Second Data ALMSEC 17 7 Alarm Min Data ALMMIN Register 17 7 Alarm Hour Data ALMHOUR 17 7 Alarm Date Data ALMDATE Register aaa 17 8 Alarm Mon Data ALM
298. ent instructions decoded as THUMB instructions If bitO of Rn 0 subsequent instructions decoded as ARM instructions 31 28 Condition Field Figure 3 2 Branch and Exchange Instructions INSTRUCTION CYCLE TIMES The BX instruction takes 2S 1N cycles to execute where S and N are defined as sequential S cycle and non sequential N cycle respectively ASSEMBLER SYNTAX BX branch and exchange BX cond Rn cond Two character condition mnemonic See Table 3 2 Rn is an expression evaluating to a valid register number USING R15 AS AN OPERAND If R15 is used as an operand the behavior is undefined ELECTRONICS 3 5 ARM INSTRUCTION SET Examples 3 6 ADR RO Into THUMB 1 BX RO CODE16 Into THUMB ADR R5 Back to_ARM BX R5 ALIGN CODE32 Back to_ARM S3C2410A Generate branch target address and set bit 0 high hence arrive in THUMB state Branch and change to THUMB state Assemble subsequent code as THUMB instructions Generate branch target to word aligned address hence bit 0 is low and so change back to ARM state Branch and change back to ARM state Word align Assemble subsequent code as ARM instructions ELECTRONICS 53 2410 ARM INSTRUCTION SET BRANCH AND BRANCH WITH LINK B BL The instruction is only executed if the condition is true The various conditions are defined Table 3 2 The instruction encoding is shown in Figure 3 3 below 31 28 27 252423
299. ent is selected by bits 7 5 of the virtual address of the line Bits 4 2 of the virtual address specify which word within a cache line is accessed For halfword operations bit 1 of the virtual address specifies which halfword is accessed within the word For byte operations bits 1 0 specify which byte within the word is accessed Bits 31 8 of the virtual address of the each cache line is called the TAG The virtual address TAG is stored in the cache along with the 8 words of data when the line is loaded by a linefill Cache lookups compare bits 31 8 of the modified virtual address of the access with the stored TAG to determine whether the access is a hit or miss The cache is therefore said to be virtually addressed DATA CACHE LOCKDOWN Data can be locked into the DCache causing the DCache to guarantee a hit and providing optimum and predictable execution time When no data is locked in the DCache and a linefill occurs the replacement algorithm chooses a victim cache line to be replaced by selecting an index in the range 0 to 63 The segment is specified by bits 7 5 of the virtual address of the data access which missed Data is locked into the DCache by restricting the range of victim numbers produced by the replacement algorithm so that some cache lines are never selected as victims The base pointer for the DCache victim generator can be set by writing to CP15 register 9 The replacement algorithm chooses a victim cache
300. ented in hardware e 64 entry instruction TLB and 64 entry data TLB e hardware page table walks e round robin replacement algorithm also called cyclic e invalidate whole TLB via CP15 Register 8 e invalidate TLB entry selected by modified virtual address via CP15 register 8 e independent lockdown of instruction TLB and data TLB via CP15 register 10 ACCESS PERMISSIONS AND DOMAINS For large and small pages access permissions are defined for each sub page 1KB for small pages 16KB for large pages Sections and tiny pages have a single set of access permissions All regions of memory have an associated domain A domain is the primary access control mechanism for a region of memory and defines the conditions in which an access can proceed The domain determines whether the access permissions are used to qualify the access the access is unconditionally allowed to proceed the access is unconditionally aborted In the latter two cases the access permission attributes are ignored There are 16 domains which are configured using the domain access control register ELECTRONICS 3 1 MMU ARM920T PROCESSOR TRANSLATED ENTRIES Each TLB caches 64 translated entries During CPU memory accesses the TLB provides the protection information to the access control logic If the TLB contains a translated entry for the modified virtual address the access control logic determines whether access is permitted e lf access is permitted and an
301. entry using Writes the specified cache line to main memory if the line is marked valid and either index or modified virtual dirty note address The line is marked not valid Prefetch cache line Performs an ICache lookup of the specified modified virtual address If the cache misses and the region is cacheable a linefill will be performed NOTE Dirty data is data that has been modified in the cache but not yet written to main memory ELECTRONICS 2 15 PROGRAMMER S MODEL ARM920T PROCESSOR The function of each cache operation is selected by the opcode 2 and CRm fields in the MCR instruction used to write CP15 register 7 Writing other opcode_2 or CRm values is unpredictable Reading from CP15 register 7 is unpredictable Table 2 16 on page 2 16 shows instructions that can be used to perform cache operations with register 7 Table 2 16 Cache Operations Register 7 Function D instruction Invalidate ICache SBZ Invalidate ICache single entry using MVA Prefetch ICache line using MVA Invalidate DCache SBZ Invalidate DCache single entry using MVA Clean DCache single entry using MVA Clean and Invalidate DCache entry using MVA Clean DCache single entry using index Clean and Invalidate DCache entry using index Drain write 1 SBZ Wait for interrupt 2 SBZ NOTES 1 Will stop execution until the write buffer has drained 2 Will stop execution in a LOW power state until an interrupt occurs 2 16
302. equential S cycle non sequential and internal respectively ASSEMBLER SYNTAX lt SWP gt cond B Rd Rm Rn cond Two character condition mnemonic See Table 3 2 B If B is present then byte transfer otherwise word transfer Rd Rm Rn Expressions evaluating to valid register numbers Examples SWP RO R1 R2 Load RO with the word addressed by R2 and store R1 at R2 SWPB R2 R3 R4 Load R2 with the byte addressed by R4 and Store bits 0 to 7 of at SWPEQ RO RO R1 Conditionally swap the contents of the word addressed by R1 with RO 3 48 ELECTRONICS 3C2410A ARM INSTRUCTION SET SOFTWARE INTERRUPT SWI The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 24 below 31 28 27 24 23 0 Cond 1111 Comment Field Ignored by Processor 31 28 Condition Field Figure 3 24 Software Interrupt Instruction The software interrupt instruction is used to enter Supervisor mode in a controlled manner The instruction causes the software interrupt trap to be taken which effects the mode change The PC is then forced to a fixed value 0x08 and the CPSR is saved in SPSR_sve If the SWI vector address is suitably protected by external memory management hardware from modification by the user a fully protected operating system may be constructed RETURN FROM THE SUPERVISOR The PC is saved in
303. er PLL stabilization time minimum 150us SLOW BIT can be cleared to 0 1 PLL is turned off PLL is turned off only when SLOW BIT is 1 SLOW BIT 4 FCLK Mpll MPLL output 1 SLOW mode FCLK input clock 2 x SLOW VAL SLOW VAL gt 0 FCLK input clock SLOW VAL 0 input clock or EXTCLK SLOW VAL 2 0 The divider value for the slow clock when SLOW BIT is on 0x4 CLOCK DIVIDER CONTROL CLKDIVN REGISTER CLKDIVN 0x4C000014 Clock divider control register 0x00000000 HDIVN1 2 Special bus clock ratio available 1 4 4 0 Reserved 1 HCLK has the clock same as the FCLK 4 PCLK has the clock same as the FCLK 4 Note If this bit is 061 HDIVN and PDIVN must be set ObO HDIVN PDIVN 0 HCLK has the clock same as the FCLK 1 HCLK has the clock same as the FCLK 2 0 PCLK has the clock same as the HCLK 1 PCLK has the clock same as the HCLK 2 d 7 22 ELECTRONICS 3C2410A DMA DMA OVERVIEW The S3C2410A supports four channel DMA controller that is located between the system bus and the peripheral bus Each channel of DMA controller can perform data movements between devices in the system bus and or peripheral bus with no restrictions In other words each channel can handle the following four cases 1 both source and destination are in the system bus 2 the source is in the system bus while the destination is in the peripheral bus 3 the source is in the periphe
304. er should be written using the read modify write method Bits 31 8 should be zero 2 14 ELECTRONICS ARM920T PROCESSOR PROGRAMMER S MODEL REGISTER 6 FAULT ADDRESS REGISTER Register 6 is the fault address register FAR which contains the modified virtual address of the access being attempted when the last fault occurred The FAR is only updated for data faults not for prefetch faults The address for a prefetch fault can be found in R14 The following instructions can be used to access the FAR MRC p15 0 0 read FAR data MCR p15 0 Rd 0 write FAR data The ability to write to the FAR is intended for a debugger to restore a previous state REGISTER 7 CACHE OPERATIONS Register 7 is a write only register used to manage the instruction and data caches ICache and DCache The cache operations provided by register 7 are described in Table 2 15 Table 2 15 Function Descriptions Register 7 Function __ Desrpion Invalidate cache Invalidates all cache data including any dirty data note Use with caution Invalidate single entry using Invalidates a single cache line discarding any dirty data note modified virtual address Use with caution Clean D single entry using either Writes the specified cache line to main memory if the line is marked valid and index or modified virtual address dirty and marks the line as not dirty note The valid bit is unchanged Clean and Invalidate D
305. er width of EINT23 FLTCLK22 23 Filter clock of EINT22 0 PCLK 1 EXTCLK OSC_CLK Selected by OM pin EINTFLT22 22 16 Filter width of EINT22 FLTCLK21 15 Filter clock of EINT21 0 PCLK 1 EXTCLK OSC_CLK Selected by OM pin EINTFLT21 14 8 Filter width of EINT21 FLTCLK20 7 Filter clock of EINT20 0 PCLK 1 EXTCLK OSC_CLK Selected by OM pin EINTFLT20 6 0 Filter width of EINT20 ELECTRONICS 9 25 PORTS 53 2410 EXTERNAL INTERRUPT MASK REGISTER EINTMASK Interrupt mask register for 20 external interrupts EINT 23 4 Reset Value EINTMASK 0 560000 4 External interupt mask register OxOOFFFFFO EINT23 0 Enable Interrupt 1 Masked EINT19 0 Enable Interrupt 1 Masked EINT18 0 Enable Interrupt 1 Masked EINT14 0 Enable Interrupt 1 Masked EINT13 0 Enable Interrupt 1 Masked EINT10 0 Enable Interrupt 1 Masked 0 Enable Interrupt 1 Masked 0 Enable Interrupt 1 Masked el 6 o Enabelntemupt t Masked 0 Enable Interrupt 1 Masked 0 Enable Interrupt 1 Masked Reserved 9 26 ELECTRONICS 3 2410 PORTS EXTERNAL INTERRUPT PENDING REGISTER EINTPENDn Interrupt pending register for 20 external interrupts EINT 23 4 You can clear a specific bit of the ENITPEND register by writing 1 on the corresponding bit of this register Reset Value EINTPEND 0 560000 8 External interupt pending register 23 0 Not requested 1
306. errupt 0 Disable 1 Enable Enable the UART to generate an interrupt upon an exception such as a frame error or overrun error during a receive operation Rx Error Status Interrupt Enable 0 Do not generate receive error status interrupt 1 Generate receive error status interrupt Loopback Mode Setting loopback bit to 1 causes the UART to enter the loopback mode This mode is provided for test purposes only 0 Normal operation 1 Loopback mode Reserved Reserved ELECTRONICS 11 11 UART 83 2410 UART CONTROL REGISTER Continued Transmit Mode 3 2 Determine which function is currently able to write Tx data to the UART transmit buffer register UART Tx Enable Disable 00 Disable 01 Interrupt request or polling mode 10 request Only for UARTO request Only for UART2 11 request Only for UART1 Receive Mode 1 0 Determine which function is currently able to read data from UART receive buffer register UART Rx Enable Disable 00 Disable 01 Interrupt request or polling mode 10 DMAO request Only UARTO request Only for UART2 11 request Only for UART1 NOTE When the UART does not reach the FIFO trigger level and does not receive data during 3 word time in DMA receive mode with FIFO the Rx interrupt will be generated receive time out and the users should check the FIFO status and read out the rest 11 12 ELECTRONICS 3C2
307. es are pre indexed using a 6 bit immediate value The THUMB assembler syntax is shown in Table 4 11 Table 4 11 Halfword Data Transfer Instructions STRH Rb lmm STRH Rb lmm Add lmm to base address in Rb and store bits 0 15 of Rd at the resulting address 0 15 from the resulting address into Rd and set bits 16 31 to zero LDRH Rb Imm LDRH Rb Imm Add Imm to base address in Rb Load bits NOTE Imm is a full 6 bit address but must be halfword aligned ie with bit O set to 0 since the assembler places lmm gt gt 1 in the Offset5 field 4 24 ELECTRONICS 3C2410A THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 11 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES STRH R6 R1 56 Store the lower 16 bits of R4 at the address formed by adding 56 R1 Note that the THUMB opcode will contain 28 the Offset5 value LDRH R4 R7 4 Load into R4 the halfword found at the address formed by adding 4 to R7 Note that the THUMB opcode will contain 2 as the Offset5 value ELECTRONICS 4 25 THUMB INSTRUCTION SET S3C2410A FORMAT 11 SP RELATIVE LOAD STORE 15 14 13 7 0 12 11 10 8 m p ord _____ 7 0 Immediate Value 10 8 Destination Register 11 Load Store Bit 0 Store to me
308. eserved 01 Output 11 Reserved ELECTRONICS 3 2410 PORTS GPDDAT GPD 15 0 15 0 When the port is configured as input port data from external sources can be read to the corresponding pin When the port is configured as output port data written in this register can be sent to the corresponding pin When the port is configured as functional pin undefined value will be read _ GPDUP 005 GPD 15 0 15 0 0 The pull up function attached to to the corresponding port pin is enabled 1 The pull up function is disabled GPD 15 12 are pull up disabled state at the initial condition ELECTRONICS 9 13 PORTS 53 2410 PORT CONTROL REGISTERS GPECON GPEDAT and GPEUP Reserved os6000046 Reserved GPECON S GPE15 91 30 00 Input 01 Output open drain output 10 IICSDA 11 Reserved This pad is open drain There is no Pull up option GPE14 29 28 00 Input 01 Output open drain output 10 IICSCL 11 Reserved s pad is open drain There is no Pull up option GPE13 27 26 Input 01 Output io SPICLKO 11 Reserved GPE12 25 24 Input 01 Output SPIMOSIO 11 Reserved GPE11 23 22 Input 01 Output SPIMISOO 11 Reserved GPE10 21 20 Input 01 Output SDDAT3 11 Reserved 19 18 01 Output 155 SDDAT2 11 Reserved 17 16 Input 01 Output ioc SDDAT 1 11 Reserved
309. ess space 128Mbytes per bank total 1GB 8 banks Programmable access size 8 16 32 bit for all banks except 16 32 bit Total 8 memory banks Six memory banks for ROM SRAM etc Remaining two memory banks for ROM SRAM SDRAM etc Seven fixed memory bank start address Adjustable start address for the last bank Programmable bank size for the last two banks Programmable access cycles for all memory banks External wait to extend the bus cycles Supporting self refresh and power down mode for SDRAM ELECTRONICS MEMORY CONTROLLER MEMORY CONTROLLER 53 2410 OM 1 0 01 10 OM 1 0 00 OxFFFE_FFFF gt 0x6000 0000 gt SFR Area SFR Area 0 4800 0000 0 4000 OFFF gt BootSRAM 0 4000 0000 SROM SDRAM SROM SDRAM 2MB 4MB 8MB 16MB nGCS7 nGCS7 32MB 64MB 128MB 0x3800 0000 gt Refer to SROM SDRAM SROM SDRAM nGCS6 nGCS6 0x3000 0000 gt SROM SROM nGCS5 nGCS5 0 2800 0000 gt 2MB 4MB 8MB 16MB 32MB 64MB 128MB Table 5 1 nGCS4 nGCS4 02000 0000 nGCS3 nGCS3 0x1800 0000 SROM SROM 0x1000_0000 gt SROM SROM nGCS1 nGCS1 0x0800 0000 SROM Boot Internal nGCS0 0x0000 0000 SRAM 4KB Not using NAND flash for boot ROM Using NAND flash for boot ROM NOTES 1 SROM means ROM or SRAM type memory 2 SFR means Special Function Register Figure 5 1 S3C2410A Memory Map after Reset Table 5 1 Bank 6 7 A
310. etermines the processor state on entry to the routine Bit0 0 Causes the processor to enter ARM state Bit 0 1 Causes the processor to enter THUMB state NOTE The action of H1 1 for this instruction is undefined and should not be used 4 14 ELECTRONICS 3C2410A EXAMPLES Hi Register Operations ADD PC R5 CMP R4 R12 MOV R15 R14 Branch and Exchange ADR R1 0utof THUMB MOV R11 R1 BX R11 ALIGN CODE32 outof THUMB USING R15 AS AN OPERAND THUMB INSTRUCTION SET PC R5 but don t set the condition codes Set the condition codes on the result of R4 R12 Move R14 LR into R15 PC but don t set the condition codes eg return from subroutine Switch from THUMB to ARM state Load address of outofTHUMB into R1 Transfer the contents of R11 into the PC Bit 0 of R11 determines whether ARM or THUMB state is entered ie ARM state here Now processing ARM instructions If R15 is used as an operand the value will be the address of the instruction 4 with bit 0 cleared Executing a BX PC in THUMB state from a non word aligned address will result in unpredictable execution ELECTRONICS THUMB INSTRUCTION SET S3C2410A FORMAT 6 PC RELATIVE LOAD 15 14 13 7 0 12 11 10 8 _ 7 0 Immediate Value 10 8 Destination Register Figure 4 7 Format 6 OPERATION This instruction loads a word from an address specified as a 10 bit immediate offset from the PC The TH
311. etup gt lt gt lt gt i Tvd2chdld ui add Tvd2csetup gt Tde2chold 1 gt Tde2csetup l Tle2chold lt Tlewidth gt lt Figure 24 30 TFT LCD Controller Timing ELECTRONICS 24 27 ELECTRICAL DATA 3 2410 IISCLK IISLRCK tLRCK gt tSDO Figure 24 31 15 Interface Timing fSCL tSCLHIGH tSCLLOW tSTOPH BUF tSTARTS IICSDA Figure 24 32 Interface Timing 24 28 ELECTRONICS ELECTRICAL DATA S3C2410A Be 0 out SDDATA 3 BWW 0 in SDDATA 3 iming Figure 24 33 SD MMC Interface T tSPIMOD SPIMOSI MO SPIMOSI SI tSPISOD SPIMISO SO ANA SPIMISO CPHA 1 CPOL 1 iming Figure 24 34 SPI Interface T 24 29 ELECTRONICS ELECTRICAL DATA S3C2410A TACLS TWRPHO TWRPH1 TACLS TWRPHO TWRPH1 lt _ lt lt lt 1 I I I I DATA 7 0 Figure 24 35 NAND Flash Address Command Timing TWRPHO TWRPH1 TWRPHO TWRPH1 DATA 7 0 DATA 7 0 Figure 24 36 NAND Flash Timing 24 30 ELECTRONICS 53 2410 ELECTRICAL DATA Table 24 6 Clock Timing Constants V DDalive V DDiarm 1 8V 0 15 2 0 V 0 1 40 to 85 C VDDMOP 3 3V 0 3 Crystal clock input frequency 10 2
312. evel in power off mode which makes the current consumption minimized If there is no load on an output port pin H level is preferred If output is L the current will be consumed through the internal parasitic resistance if the output is H the current will not be consumed For an output port the current consumption can be reduced if the output state is H Battery Fault Signal nBATT_FLT There are two functions in nBATT_FLT pin as follows When CPU is not in Power_OFF mode nBATT_FLT pin will cause the interrupt request The interrupt attribute of the nBATT_FLT is L level triggered While CPU is in Power_OFF mode assertion of the nBATT_FLT will prohibit the wake up from the power down mode So Any wake up source will be masked if nBATT FLT is asserted which is protecting the system malfunction of the low battery capacity ADC Power Down The ADC has an additional power down bit in ADCCON If the S8C2410A enters the Power_OFF mode the ADC should enter its own power down mode S W Work Around After wake up from the Power_OFF mode by RTC_ALARM the RTC source pending bit of the SRCPND register is not set So the ALARM date has to be checked after the wake up from Power_OFF mode 7 18 ELECTRONICS 53 2410 CLOCK 8 POWER MANAGEMENT CLOCK GENERATOR amp POWER MANAGEMENT SPECIAL REGISTER LOCK TIME COUNT REGISTER LOCKTIME LOCKTIME 0 4 000000 PLL lock time count register OxOOFFFFFF U_LTIME 23 12 UPLL lock tim
313. ew timer value is set a current timer operation is completed successfully The timer value can be written into Timer Count Buffer register TCNTBn and the current counter value of the timer can be read from Timer Count Observation register TCNTOn If the TCNTBn is read the read value does not indicate the current state of the counter but the reload value for the next timer duration The auto reload operation copies the TCNTBn into TCNTn when the TCNTn reaches 0 The value written into the is loaded to the TCNTn only when the TCNTn reaches 0 and auto reload is enabled If the TCNTn becomes 0 and the auto reload bit is 0 the TCNTn does not operate any further Write Write TCNTBn 100 TCNTBn 200 Start TCNTBn 150 Auto reload _ lt gt lt gt lt gt lt gt 150 100 200 Interrupt _ j Figure 10 3 Example of Double Buffering Function 10 4 ELECTRONICS 53 2410 PWM TIMER TIMER INITIALIZATION USING MANUAL UPDATE BIT AND INVERTER BIT An auto reload operation of the timer occurs when the down counter reaches 0 So a starting value of the TCNTn has to be defined by the user in advance In this case the starting value has to be loaded by the manual update bit The following steps describe how to start a timer 1 Write the initial value into TCNTBn and TCMPBn 2 Set the manual update bit of the corresponding timer It is recommended that you configure the inverter on o
314. f whether the SWI was executed in ARM THUMB state Copies the CPSR into the appropriate SPSR Forces the CPSR mode bits to a value which depends on the exception Forces the PC to fetch the next instruction from the relevant exception vector It may also set the interrupt disable flags to prevent otherwise unmanageable nestings of exceptions If the processor is in THUMB state when an exception occurs it will automatically switch into ARM state when the PC is loaded with the exception vector address Action on Leaving an Exception On completion the exception handler 1 Moves the Link Register minus an offset where appropriate to the PC The offset will vary depending on the type of exception Copies the SPSR back to the CPSR Clears the interrupt disable flags if they were set on entry NOTE An explicit switch back to THUMB state is never needed since restoring the CPSR from the SPSR automatically sets the T bit to the value it held immediately prior to the exception 2 10 ELECTRONICS 3C2410A PROGRAMMER S MODEL Exception Entry Exit Summary Table 2 2 summarizes the PC value preserved in the relevant R14 on exception entry and the recommended instruction for exiting the exception handler Table 2 2 Exception Entry Exit Return Instruction Previous State ARM R14 x THUMB R14_x MOV PC R14 MOVS R14 svc MOVS PC R14 und SUBS PC R14 4 SUBS PC R14 4 SUBS PC R14 abt 4 SUBS PC R14_abt
315. face AIN 3 Convert 2 Controller ADC Input Interrupt Control Generation AIN O VSSA ADC Waiting for Interrupt Mode Figure 16 1 ADC and Touch Screen Interface Block Diagram 16 2 ELECTRONICS 3C2410A ADC AND TOUCH SCREEN INTERFACE EXAMPLE FOR TOUCH SCREEN In this example AIN 7 is connected with XP and AIN 5 is connected with YP pad of the touch screen panel To control pads of the touch screen panel XP XM YP and YM four external transistors are applied and control signals including nYPON YMON nXPON and XMON are connected with four external transistors EINT 22 External ENTIN 2 EINT 20 External Voltage Source XP XM YP YM Touch Panel S3C2410A Figure 16 2 Example of ADC and Touch Screen Interface The following procedure is suggested 1 Connect pads of the touch screen panel to the S3C2410A using external transistor see Figure 16 2 2 Select Separate X Y Position Conversion Mode or Auto Sequential X Y Position Conversion Mode to get X Y position Set Touch Screen Interface to Waiting Interrupt Mode If interrupt occurs then appropriate conversion Separate X Y Position Conversion Mode or Auto Sequential X Y Position Conversion Mode is activated 5 After get the proper value of X Y position return to Waiting for Interrupt Mode NOTES 1 External voltage source should be 3 3 V 2 Internal resistance of the external transistor should be under 5 ohm
316. ff bit whether use inverter or not 3 Set start bit of the corresponding timer to start the timer and clear the manual update bit If the timer is stopped by force the TCNTn retains the counter value and is not reloaded from TCNTBn If a new value has to be set perform manual update NOTE Whenever TOUT inverter on off bit is changed the TOUTn logic value will also be changed whether the timer runs Therefore it is desirable that the inverter on off bit is configured with the manual update bit ELECTRONICS 10 5 PWM TIMER 3 2410 TIMER OPERATION Figure 10 4 Example of a Timer Operation Figure 10 4 shows the result of the following procedure 1 10 11 Enable the auto reload function Set TCNTBn to 160 50 110 and the TCMPBn to 110 Set the manual update bit and configure the inverter bit on off The manual update bit sets TCNTn and TCMPn to the values of TCNTBn and TCMPBn respectively And then set the TCNTBn and the TCMPBn to 80 40 40 and 40 respectively to determine the next reload value Set the start bit provided that manual update is 0 and the inverter is off and auto reload is on The timer starts counting down after latency time within the timer resolution When the TCNTn has the same value as that of the TCMPn the logic level of the TOUTn is changed from low to high When the TCNTn reaches 0 the interrupt request is generated and TCNTBn value is loaded into a temporary registe
317. ffer then automatically start to transfer 8 Seta GPIO pin which acts as nSS to high to deactivate MMC or SD card oi D ELECTRONICS 22 3 SPI INTERFACE 53 2410 SPI Transfer Format The S3C2410A supports 4 different formats to transfer the data Figure 22 2 shows four waveforms for SPICLK CPOL 0 CPHA 0 Format A Cycle 1 2 3 4 5 6 7 8 scc LJ LI LI LI LU LI LL MOSI MSB MSB of previous frame CPOL 0 CPHA 1 Format B ow TT2T T4T e sec L LE LE LS LPL LL aay ss MISO LSB LSB of next frame CPOL 1 CPHA 0 Format A Cycle Es MOSI MISO MSB MSB of previous frame CPOL 1 CPHA 1 Format B Cycle 1 2 3 4 5 6 7 8 srk LE LE LILI LILI LI MOSI I MISO LSB LSB of next frame Figure 22 2 SPI Transfer Format 22 4 ELECTRONICS 53 2410 SPI INTERFACE Transmitting Procedure by DMA N gt gi The SPI is configured as DMA mode DMA is configured properly The SPI requests DMA service DMA transmits 1byte data to the SPI The SPI transmits the data to card Return to Step 3 until DMA count becomes 0 The SPI is configured as interrupt or polling mode with SMOD bits Receiving Procedure by DMA The SPI is configured as DMA start with SMOD bits and set
318. fore Enable Video output Lcd Workaround void int loop 7 rLCDCON5 rLCDCON5 amp 1 lt lt 3 Disable LCD_PWREN If you don t use LCD PWREN you can remove this line 1 0 lt I rLCDCON1 1 ENVID ON rLCDCON1 rLCDCON1 amp Ox3fffe ENVID Off rLCDCON5 1 lt lt 3 Enable LCD_PWREN If you don t use LCD_PWREN then you can remove this line 15 40 ELECTRONICS 3C2410A LCD CONTROLLER Gray Level Selection Guide The 53 2410 LCD controller can generate 16 gray level using Frame Rate Control FRC The FRC characteristics may cause unexpected patterns in gray level These unwanted erroneous patterns may be shown in fast response LCD or at lower frame rates Because the quality of LCD gray levels depends on LCD s own characteristics the user has to select an appropriate gray level after viewing all gray levels on user s own LCD Select the gray level quality through the following procedures 1 Get the latest dithering pattern register value from SAMSUNG 2 Display 16 gray bar in LCD 3 Change the frame rate into an optimal value 4 Change the VM alternating period to get the best quality 5 As viewing 16 gray bars select a good gray level which is displayed well on your LCD 6 Use only the good gray levels for quality LCD Refresh Bus Bandwidth Calculation Guide The S3C2410A LCD controller can support various LCD display sizes To select a suitable size f
319. ftware Interrupt ense nennen 4 36 terrence ert rere eer ES rere core 4 36 Instruction Cycle Tines as 4 36 desc e e MIEL ER UT iD 4 36 Format 18 Unconditional e nennen enne 4 37 Operation IET iss 4 37 Eram DES Urt CU esas 4 37 Format 19 Long Branch With enne nnne enn 4 38 Opera T 4 38 Instruction Cycle TIMES ierra iit ahd Dee cae 4 39 EX AIM PIGS u w u wy 4 39 Instruction Set Example S ar rn a a a a E a a aE aaa aa aaa Ea a a S 4 40 Multiplication by a Constant Using Shifts and Adds I 4 40 General Purpose Signed Divide 4 41 Division by a Constante EE 4 43 Chapter 5 Memory Controller OVOIVIOW tite tira at e napua 5 1 Function Descriptions oerte rre dad eee nae Rd vede 5 3 Bus Width xii eei EE ee e et ee at e Te dte seb deeds 5 3 Memory SROM SDRAM Address Pin Conneclions a 5 3 Sdram Bank Address Pin Connection esses enne nennen nnne enne 5 4 Nwait Pin ODerationig oo deer etn n
320. g ADDRESSING MODES ARM920T is responsible for providing the address used by the memory system for the transfer and the addressing modes available are a subset of those used in single data transfer instructions Note however that the immediate offsets are 8 bits wide and specify word offsets for coprocessor data transfers whereas they are 12 bits wide and specify byte offsets for single data transfers The 8 bit unsigned immediate offset is shifted left 2 bits and either added to U 1 or subtracted from U 0 the base register Rn this calculation may be performed either before P 1 or after P 0 the base is used as the transfer address The modified base value may be overwritten back into the base register if W 1 or the old value of the base may be preserved W 0 Note that post indexed addressing modes require explicit setting of the W bit unlike LDR and STR which always write back when post indexed The value of the base register modified by the offset in a pre indexed instruction is used as the address for the transfer of the first word The second word if more than one is transferred will go to or come from an address one word 4 bytes higher than the first transfer and the address will be incremented by one word for each subsequent transfer ADDRESS ALIGNMENT The base address should normally be a word aligned quantity The bottom 2 bits of the address will appear on A 1 0 and might be interpreted by the memor
321. g Register amp FIFO Register 11 19 Uar Baud Rate 1 s ar SSS aps m s a ai DS w enn 11 20 S3C2410A MICROPROCESSOR xi Table of Contents Continued Chapter 12 USB Host Controller iu P 12 1 USB Host Controller Special Registers nnns 12 2 Chapter 13 USB Device Controller xii OVOIVIOW sett ett d tenete E end orsi etd 13 1 Features ince et e ee oda et eden eet ea eda d eq ied 13 1 USB Device Controller Special Registers L 13 3 Function Address Register Addr Reg ener 13 5 Power Management Register Pwr_Reg eene nnns nnne nennen 13 6 Interrupt Register Ep Int Reg Usb Int 13 7 Interrupt Enable Register Ep Int En Reg Usb Int En 13 9 Frame Number Register Fpame Num1 Reg Frame Num2 Reg 13 10 Index Register Index Reg cec er tee ette eee b et pereo eer ee as 13 11 End PointO Control Status Register enne 13 12 End Point In Control Status Register In_Csr1_Reg In_Csr2_Reg 13 14 End Point Out Control Status Register Out Csr1_Reg Out_Csr2_Reg
322. g the SPSTAn 0 not detect 1 collision error detect reading SPSTAn 0 not detect 1 multi master error detect Transfer Ready Flag This bit indicates that SPTDATn or SPRDATnR is ready to REDY transmit or receive This flag is automatically cleared by writing data to SPTDATn 0 not ready 1 data Tx Rx ready Multi Master Error Flag This flag is set if the nSS signal goes to active low while MULF the SPI is configured as a master and SPPINn s ENMUL bit is multi master errors detect mode MULF is cleared by 22 8 ELECTRONICS 53 2410 SPI INTERFACE SPI PIN CONTROL REGISTER When the SPI system is enabled the direction of pins except nSS pin is controlled by MSTR bit of SPCONn register The direction of nSS pin is always input When the SPI is a master nSS pin is used to check multi master error provided the SPPIN s ENMUL bit is active and another GPIO should be used to select a slave If the SPI is configured as a slave the nSS pin is used to select SPI as a slave by one master SPPINO 0x59000008 SPI channel 0 pin control register SPPIN1 0x59000028 SPI channel 1 pin control register gp Y Multi Master error detect The SS pin is used as an input to detect multi master error Enable ENMUL when the SPI system is a master 0 disable general purpose 1 multi master error detect enable Master Out Keep KEEP Determine MOSI drive or release when 1byte transmit is completed only master 0 releas
323. g the processor ABORT input HIGH whereupon the Data Abort trap will be taken It is up to the system software to resolve the cause of the problem then the instruction can be restarted and the original program continued INSTRUCTION CYCLE TIMES Normal LDR instructions take 1S 1N 11 and LDR PC take 2S 2N 11 incremental cycles where S N are defined as sequential S cycle non sequential N cycle and internal respectively STR instructions take 2N incremental cycles to execute ELECTRONICS 3 31 ARM INSTRUCTION SET ASSEMBLER SYNTAX S3C2410A lt LDR STR gt cond B T Rd lt Address gt where LDR STR cond B T Rn and Rm lt Address gt can be 1 lt shift gt 3 32 Load from memory into a register Store from a register into memory Two character condition mnemonic See Table 3 2 If B is present then byte transfer otherwise word transfer If T is present the W bit will be set in a post indexed instruction forcing non privileged mode for the transfer cycle T is not allowed when a pre indexed addressing mode is specified or implied An expression evaluating to a valid register number Expressions evaluating to a register number If Rn is R15 then the assembler will subtract 8 from the offset value to allow for ARM920T pipelining In this case base write back should not be specified An expression which generates an address The assembler will attempt to ge
324. ge tables as required 3 Enable the MMU by setting bit 0 in the control register Care must be taken if the translated address differs from the untranslated address as several instructions following the enabling of the MMU may have been prefetched with the MMU off using physical virtual address flat translation and enabling the MMU may be considered as a branch with delayed execution A similar situation occurs when the MMU is disabled Consider the following code sequence MRC p15 0 R1 c1 CO 0 Read control rejection ORR R1 0x1 MCR p15 0 R1 C1 0 0 Enable MMUS Fetch Flat Fetch Flat Fetch Translated The instruction and data caches can be enabled simultaneously with the MMU using a single MCR instruction DISABLING THE MMU To disable the MMU clear bit 0 in the control register The data cache should be disabled prior to or at the same time as the MMU is disabled by clearing Bit 2 of the control register See the paragraph in Enabling the MMU regarding prefetch effects NOTE If the MMU is enabled then disabled and subsequently re enabled the contents of the TLBs will have been preserved If these are now invalid the TLBs should be invalidated before the MMU is re enabled See Register 8 TLB operations on page 2 18 ELECTRONICS 3 25 MMU ARM920T PROCESSOR NOTES 3 26 ELECTRONICS ARM920T PROCESSOR CACHES WRITE BUFFER Appendix 4 CACHES WRITE BUFFER ABOUT THE CACHES AND WRITE BUFFER The ARM920T
325. gister or writing to a non writable register will cause unpredictable results The opcode_1 opcode 2 and CRm fields should be zero except when the values specified are used to select the desired operations in all instructions which access CP15 Using other values will result in unpredictable behavior ELECTRONICS 2 5 PROGRAMMER S MODEL ARM920T PROCESSOR Addresses in ARM920T Three distinct types of address exist in an 920 system e virtual address VA e modified virtual address MVA e physical address PA Below is an example of the address manipulation when the ARM9TDMI requests an instruction 1 The VA of the instruction IVA is issued by the ARM9TDMI 2 This is translated by the ProcID to the instruction MVA IMVA It is the IMVA that the instruction cache and MMU see 3 If the protection check carried out by the IMMU on the IMVA does not abort and the IMVA tag is in the instruction cache the instruction data is returned to the ARM9TDMI 4 Ifthe instruction cache misses the IMVA tag is not in the instruction cache then the IMMU performs a translation to produce the instruction PA IPA This address is given to the AMBA bus interface to perform an external access Table 2 4 Address Types in ARM920 2 6 ELECTRONICS ARM920T PROCESSOR PROGRAMMER S MODEL REGISTER 0 ID CODE REGISTER This is a read only register which returns a 32 bit device ID code The ID code register is accessed by reading CP15 regis
326. h 16 bit SDRAM 16MB 1Mb x 16 x 4banks x 2ea NOTE Refer to Table 5 2 for the Bank Address configurations of SDRAM 5 10 ELECTRONICS MEMORY CONTROLLER 53 2410 PROGRAMMABLE ACCESS CYCLE 2 cycles 2 cycles Tcoh 1 cycle Tacp Tcah o 2 gt o Tacs 1 cycle Tcos 1 cycle Tacc Figure 5 12 53 2410 nGCS Timing Diagram 5 11 ELECTRONICS 53 2410 MEMORY CONTROLLER Ca 3 BL 1 2 CL Read CL Bank Precharge 2 cycle Tcas 2 cycle Tcp 2 2 Trp Figure 5 13 S3C2410A SDRAM Timing Diagram ELECTRONICS 5 12 53 2410 MEMORY CONTROLLER BUS WIDTH amp WAIT CONTROL REGISTER BWSCON BWSCON 0x48000000 Bus width amp wait status control register 0x000000 BWSCON Description itial state ST7 31 Determine SRAM for using UB LB for bank 7 0 Not using UB LB The pins are dedicated nWBE 3 0 1 Using UB LB The pins are dedicated nBE 3 0 WS7 30 Determine WAIT status for bank 7 0 WAIT disable 1 WAIT enable DW7 29 28 Determine data bus width for bank 7 00 8 bit 01 16 bit 10 32 bit 11 reserved ST6 27 Determine SRAM for using UB LB for bank 6 0 Not using UB LB The pins are dedicated nWBE 3 0 1 Using UB LB The pins are dedicated nBE 3 0 WS6 26 Determine WAIT status for bank 6 0 WAIT disable 1 WAIT enable DW6 25 24
327. halfword 11 8 Immediate Offset High Nibble 15 12 Source Destination Register 19 16 Base Register 20 Load Store 0 Store to memory 1 Load from memory 21 Write back 0 No write back 1 Write address into base 23 Up Down 0 Down subtract offset from base 1 Up add offset to base 24 Pre Post Indexing 0 Post add subtract offset after transfer 1 Pre add subtract offset bofore transfer 31 28 Condition Field Figure 3 17 Halfword and Signed Data Transfer with Immediate Offset and Auto Indexing OFFSETS AND AUTO INDEXING The offset from the base may be either a 8 bit unsigned binary immediate value in the instruction or a second register The 8 bit offset is formed by concatenating bits 11 to 8 and bits to 0 of the instruction word such that bit 11 becomes the MSB and bit 0 becomes the LSB The offset may be added to U 1 or subtracted from U 0 the base register Rn The offset modification may be performed either before pre indexed P 1 or after post indexed P 0 the base register is used as the transfer address The W bit gives optional auto increment and decrement addressing modes The modified base value may be written back into the base W 1 or the old base may be kept W 0 In the case of post indexed addressing the write back bit is redundant and is always set to zero since the old base value can be retained if necessary by setting the offset to zero Therefore post i
328. he IIS bus format the MSB justified format realizes that the transmitter always sends the MSB of the next word whenever the IISLRCK is changed ELECTRONICS 21 3 IIS BUS INTERFACE 53 2410 MSB justified Format N 8 16 Figure 21 2 IIS Bus and MSB Left justified Data Interface Formats SAMPLING FREQUENCY AND MASTER CLOCK Master clock frequency PCLK can be selected by sampling frequency as shown in Table 21 1 Because PCLK is made by IIS prescaler the prescaler value and PCLK type 256 or 384fs should be determined properly Serial bit clock frequency type 16 32 48fs can be selected by the serial bit per channel and PCLK as shown in Table 21 2 Table 21 1 CODEC clock CODECLK 256 or 384fs IISLRCK 8 000 11 025 16 000 22 050 32 000 44 100 48 000 64 000 88 200 96 000 fs kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz 256fs o MHz 38415 21 4 ELECTRONICS 3C2410A IIS BUS INTERFACE Table 21 2 Usable Serial Bit Clock Frequency IISCLK z 16 or 32 or 48fs Serial clock frequency IISCLK CODECLK 384fs 16fs 32fs 48fs 3215 4815 liS BUS INTERFACE SPECIAL REGISTERS 15 CONTROL IISCON REGISTER IISCON 0x55000000 Li HW Li W Bi W m 15 control register 0x100 0x55000002 GUB Left Right channel index 0 Left Read only 1 Right Transmit FIFO ready flag empty Read only not empty Receive FIFO ready flag full 22 not full Read only 0 Disable 1 Ena
329. he condition that total bytes of 1 line are 4n bytes If the x size of LCD is 120 dot in mono mode x 120 cannot be supported because 1 line consists of 15 bytes Instead x 128 in mono mode can be supported because 1 line is composed of 16 bytes 4n LCD panel driver will discard the additional 8 dot LINEBLANK STN These bits indicate the blank time in one horizontal line duration STN time These bits adjust the rate of the VLINE finely The unit of LINEBLANK is HCLK X 8 Ex If the value of LINEBLANK is 10 the blank time is inserted to VCLK during 80 HCLK HFPD TFT 7 0 Horizontal front porch is the number of VCLK periods between 0X00 the end of active data and the rising edge of HSYNC Programming NOTE In case of STN LCD LINEBLANK WLH WDLY value should be bigger than 14 12xTmax LINEBLANK WDLY 14 8xTmax1 4xTmax2 14 12xTmax LEGEND 1 14 SDRAM Auto refresh bus acquisition cycles 2 8x Tmax1 Cache fill cycle X the Slowest Memory access time Ex ROM 3 4 2 address Frame memory Access time 4 4 Tmax Large one of the Tmax1 and Tmax2 15 28 ELECTRONICS 3C2410A LCD CONTROLLER LCD Control 4 Register LCDCON4 0 4000000 LCD control 4 register 0x00000000 MVAL 15 8 STN These bit define the rate at which the VM signal will toggle if the 0X00 MMODE bit is set to logic 1 HSPW TFT 7 0 TFT Horizontal sync pulse width determines the HSY
330. he instruction cache size Table 2 7 on page 2 9 shows the meaning of values used for cache size encoding Table 2 7 Cache Size Encoding owo KB Bits 17 15 give the data cache associativity Bits 5 3 give the instruction cache associativity Table 2 8 on page 2 9 shows the meaning of values used for cache associativity encoding Table 2 8 Cache associativity encoding O oS o 168 16 Bits 13 12 give the data cache line length Bits 1 0 give the instruction cache line length ELECTRONICS 2 9 PROGRAMMER S MODEL ARM920T PROCESSOR Table 2 9 shows the meaning of values used for line length encoding Table 2 9 Line Length Encoding 13 12 Bits 1 0 Words Per Line _____ 2 REGISTER 1 CONTROL REGISTER This register contains the control bits of the ARM920T All reserved bits should either be written with zero or one as indicated or written using read modify write The reserved bits have an unpredictable value when read To read and write this register MRC p15 0 Rd c1 0 read control register MCR p15 0 c1 0 write control register All defined control bits are set to zero on reset except the V Bit which is set to zero at reset if the VINITHI pin is LOW or one if the VINITHI pin is HIGH The functions of the control bits are shown in Table 2 10 2 10 ELECTRONICS ARM920T PROCESSOR PROGRAMMER S MODEL Table 2 10 Control Register 1 b
331. his bit indicates the VDEN signal polarity 0 Normal 1 Inverted INVPWREN INVLEND This bit indicates the PWREN signal polarity 0 Normal 1 Inverted TFT This bit indicates the LEND signal polarity 0 Normal 1 Inverted TFT LEND output signal enable disable 0 Disable LEND signal 1 Enable LEND signal STN TFT Byte swap control bit 0 Swap Disable 1 Swap Enable ENLEND BSWP HWSWP STN TFT Half Word swap control bit 0 Swap Disable 1 Swap Enable PWREN 3 STN TFT LCD PWREN output signal enable disable 0 Disable PWREN signal 1 Enable PWREN signal ELECTRONICS 15 31 LCD CONTROLLER 83 2410 FRAME BUFFER START ADDRESS 1 REGISTER LCDSADDR1 OX4D000014 STN TFT Frame buffer start address 1 register 0 00000000 LCDBANK 29 21 These bits indicate A 30 22 of the bank location for the video buffer in the system memory LCDBANK value cannot be changed even when moving the view port LCD frame buffer should be within aligned 4MB region which ensures that LCDBANK value will not be changed when moving the view port So care should be taken to use the malloc function LCDBASEU 20 0 For dual scan LCD These bits indicate A 21 1 of the start address of 0x000000 the upper address counter which is for the upper frame memory of dual scan LCD or the frame memory of single scan LCD For single scan LCD These bits indicate A 21 1 of the start address
332. hrough mode WT Reads which hit in the cache will read the data from the cache and do not perform an access on the ASB Reads which miss in the cache cause a linefill All writes are placed in the write buffer and will appear on the ASB The CPU continues execution as soon as the write is placed in the write buffer Writes which hit in the cache update the cache Writes cannot be externally aborted Cached write back mode WB Reads which hit in the cache will read the data from the cache and do not perform an ASB access Reads which miss in the cache cause a linefill Writes which miss in the cache are placed in the write buffer and will appear on the ASB The CPU continues execution as soon as the write is placed in the write buffer Writes which hit in the cache update the cache and mark the appropriate half of the cache line as dirty and do not cause an ASB access Cache write backs are buffered Writes Cache write misses and cache write backs cannot be externally aborted NOTES 1 The control register C bit Ccr being zero disables all lookups in the cache while the translation table descriptor C bit Ctt being zero only stops new data being loaded into the cache With Ccr 1 and Ctt 0 the cache will still be searched on every access to check whether the cache contains an entry for the data 2 an operating system software error if a cache hit occurs when reading from or writing to a region of memory marked
333. iations Unpredictable For reads the data returned when reading from this location is unpredictable it could have any value For writes writing to this location will cause unpredictable behavior or an unpredictable change in device configuration Should be zero When writing to this location all bits of this field should be 0 In all cases reading from or writing any data values to any CP15 registers including those fields specified as unpredictable or should be zero will not cause any permanent damage All CP15 register bits that are defined and contain state are set to zero by BnRES except V Bit in register 1 which takes the value of macrocell input VINITHI when BnRES is asserted CP15 registers can only be accessed with MRC and MCR instructions in a privileged mode The instruction bit pattern of the MCR and MRC instructions is shown in Figure 2 1 The assembler for these instructions is MCR MRC cong P15 opcode_1 Rd CRn CRm opcode_2 28 27 26 25 2423 212019 16 15 1211109 8 7 5 4 3 I Figure 2 1 CP15 MRC and MCR Bit Pattern Instructions CDP LDC and STC along with unprivileged MRC and MCR instructions to CP15 will cause the undefined instruction trap to be taken The CRn field of MRC and MCR instructions specifies the coprocessor register to access The CRm field and opcode_ 2 field are used to specify a particular action when addressing registers Attempting to read from a non readable re
334. ied data format The interface provides DMA transfer mode for FIFO access instead of an interrupt It can transmit and receive data simultaneously as well as transmit or receive data alternatively at a time ELECTRONICS 21 1 IIS BUS INTERFACE 53 2410 BLOCK DIAGRAM TxFIFO RxFIFO IPSR_A IPSR B Figure 21 1 15 Block Diagram FUNCTIONAL DESCRIPTIONS Bus interface register bank and state machine BRFC Bus interface logic and FIFO access are controlled by the state machine 5 bit dual prescaler IPSR One prescaler is used as the master clock generator of the IIS bus interface and the other is used as the external CODEC clock generator 64 byte FIFOs TxFIFO and RxFIFO In transmit data transfer data are written to TxFIFO and in the receive data transfer data are read from RxFIFO Master IISCLK generator SCLKG In master mode serial bit clock is generated from the master clock Channel generator and state machine CHNO IISCLK and IISLRCK are generated and controlled by the channel state machine 16 bit shift register SFTR Parallel data is shifted to serial data output in the transmit mode and serial data input is shifted to parallel data in the receive mode TRANSMIT OR RECEIVE ONLY MODE Normal Transfer 15 control register has FIFO ready flag bits for transmit and receive FIFOs When FIFO is ready to transmit data the FIFO ready flag is set to 1 if transmit FIFO is not empty If trans
335. ified as the register offset Rm When R15 is the source register Rd of a Half word store instruction the stored address will be address of the instruction plus 12 DATA ABORTS A transfer to or from a legal address may cause problems for a memory management system For instance in system which uses virtual memory the required data may be absent from the main memory The memory manager can signal a problem by taking the processor ABORT input HIGH whereupon the Data Abort trap will be taken It is up to the system software to resolve the cause of the problem then the instruction can be restarted and the original program continued INSTRUCTION CYCLE TIMES Normal LDR H SH SB instructions take 15 1N 11 LDR H SH SB PC take 25 2N 11 incremental cycles S N and l are defined as sequential S cycle non sequential N cycle and internal I cycle respectively instructions take 2N incremental cycles to execute ELECTRONICS 3 37 ARM INSTRUCTION SET ASSEMBLER SYNTAX S3C2410A lt LDR STR gt cond lt H SH SB gt Rd lt address gt LDR STR cond H SB SH Rd lt address gt can be 1 3 38 Load from memory into a register Store from a register into memory Two character condition mnemonic See Table 3 2 Transfer halfword quantity Load sign extended byte Only valid for LDR Load sign extended halfword Only valid for LDR An expression evaluating to a valid register number A
336. il Interrupt 11 Enable CrcSta Interrupt 10 Enable DatCrc Interrupt Enable DatTout Interrupt Enable DatFin Interrupt 7 Enable BusyFin Interrupt Enable Reserved TFHalf Interrupt Enable TFEmpty Interrupt Enable RFLast Interrupt Enable RFFull Interrupt Enable RFHalf Interrupt Enable RA ELECTRONICS Response CRC error interrupt 0 disable 1 interrupt enable Command sent without response interrupt 0 disable 1 interrupt enable Command response timeout interrupt 0 disable 1 interrupt enable Command response received interrupt 0 disable 1 interrupt enable Read wait request interrupt 0 disable 1 interrupt enable SD host receives SDIO Interrupt from the card for SDIO 0 disable FIFO fail error interrupt 0 disable CRC status errors interrupt 0 disable 1 interrupt enable Data CRC fail interrupt 0 disable Data timeout interrupt 0 disable Data counter zero interrupt 0 disable 1 interrupt enable Busy checks complete interrupt 0 disable 1 interrupt enable 1 interrupt enable 1 interrupt enable 1 interrupt enable 1 interrupt enable Tx FIFO half interrupt 0 disable Tx FIFO empty interrupt 0 disable 1 interrupt enable Rx FIFO has last data interrupt 0 disable 1 interrupt enable Rx FIFO full interrupt 0 disable Rx FIFO half interrupt 0 disable 1 interrupt enable
337. in status about faults generated by instruction fetches An access violation for a given memory access inhibits any corresponding external access with an abort returned to the CPU core ELECTRONICS 3 17 MMU ARM920T PROCESSOR FAULT ADDRESS AND FAULT STATUS REGISTERS On a data abort the MMU places an encoded 4 bit value FS 3 0 along with the 4 bit encoded domain number in the Data fault status register FSR Similarly on a prefetch abort in the Prefetch fault status register intended for debug purposes only In addition the modified virtual address associated with the data abort is latched into the fault address register FAR If an access violation simultaneously generates more than one source of abort they encoded in the priority given Table 3 4 The fault address register is not updated by faults caused by instruction prefetches FAULT STATUS The remainder of this chapter describes the various access permissions and controls supported by the data MMU and details how these are interpreted to generate faults Table 3 4 Priority Encoding of Fault Status Highest Alignment 0b00x1 invalid MVA of access priority causing abort Translation Section Page 0b0101 invalid MVA of access 0b0111 valid causing abort Domain Section Page 0b1001 valid MVA of access 0b1011 valid causing abort Permission Section Page 0b1101 valid MVA of access 0b1111 valid causing abort Lowest priority External
338. invalidates the ICache will have been read from the ICache before it is invalidated ELECTRONICS 4 11 CACHES WRITE BUFFER ARM920T PROCESSOR CACHE CLEANING WHEN LOCKDOWN 15 IN USE The clean D single entry using index and clean and invalidate D entry using index operations can leave the victim pointer set to the index value used by the operation In some circumstances if DCache locking is in use this could leave the victim pointer in the locked region leading to locked data being evicted from the cache The victim pointer can be moved outside the locked region by implementing the cache loop enclosed by the reading and writing of the Base and Victim pointer MRC p15 0 Rd c9 c0 0 Read D Cache Base into Rd Index Clean or Index Clean and Invalidate loops MCR p15 0 Rd c9 c0 0 Write D Cache Base and Victim from Rd Clean D single entry using VA and clean and invalidate D entry using VA operations do not move the victim pointer so there is no need to reposition the victim pointer after using these operations IMPLEMENTATION NOTES This section describes the behavior of the ARM920T implementation in areas which are architecturally unpredictable For portability to other ARM implementations software should not depend on this behavior A read from a non cacheable NCB or NCNB region which unexpectedly hits in the cache will still read the required data from the ASB The contents of the cache will be ignored and the cach
339. ion will make the IIC bus free When a master initiates a Start condition it should send a slave address to notify the slave device One byte of address field consists of a 7 bit address and a 1 bit transfer direction indicator showing write or read If bit 8 is 0 it indicates a write operation transmit operation if bit 8 is 1 it indicates a request for data read receive operation The master will finish the transfer operation by transmitting a Stop condition If the master wants to continue the data transmission to the bus it should generate another Start condition as well as a slave address In this way the read write operation can be performed in various formats Start Stop Condition Condition Figure 20 2 Start and Stop Condition ELECTRONICS 20 3 IIC BUS INTERFACE 53 2410 DATA TRANSFER FORMAT Every byte placed on the SDA line should be eight bits in length The bytes can be unlimitedly transmitted per transfer The first byte following a Start condition should have the address field The address field can be transmitted by the master when the IIC bus is operating in Master mode Each byte should be followed by an acknowledgement bit The MSB bit of the serial data and addresses are always sent first Write Mode Format with 7 bit Addresses Slave Address 7bits DATA 1Byte F Lo Write Data Transferred Data Acknowledge Read Mode Format with 7 bit Addresses Slave Add
340. is generated But second value can be reset BCD SECOND BCDSEC REGISTER BCDSEC 0x57000070 L R W BCD second register Undefined 0x57000073 B by byte SECDATA 6 4 BCD value for second lt 0 5 13 0 0 BCD MINUTE BCDMIN REGISTER BCDMIN 0x57000074 L R W BCD minute register Undefined 0x57000077 B by byte MINDATA 6 4 BCD value for minute 0 5 0 ELECTRONICS 17 9 REAL TIME CLOCK RTC 53 2410 BCD HOUR BCDHOUR REGISTER BCDHOUR 0x57000078 L R W BCD hour register Undefined 0x5700007B B by byte p _ _ HOURDATA 5 41 BCD value for hour NN 0 2 0 BCD DATE BCDDATE REGISTER BCDDATE 0x5700007C L R W BCD date register Undefined 0x5700007F B by byte pp DATEDATA 5 4 BCD value for date mE 0 3 0 BCD DAY BCDDAY REGISTER BCDDAY 0x57000080 L R W BCD a day of the week register Undefined 0x57000083 B by byte ea C DAYDATA 2 0 BCD value for a day of the week 1 7 17 10 ELECTRONICS 53 2410 REAL TIME CLOCK RTC BCD MONTH BCDMON REGISTER BCDMON 0x57000084 L R W BCD month register Undefined 0x57000087 B by byte MONDATA BCD value for month 0 1 3 0 0 9 BCD YEAR BCDYEAR REGISTER BCDYEAR 0x57000088 L R W BCD year register Undefined 0x5700008B B by byte YEARDATA 7 0 BCD value for year 00 99 ELECTRONICS 17 11 REAL TIME CLOCK RTC S3
341. is 1 ACK was not received 53 2410 ELECTRONICS 53 2410 IIC BUS INTERFACE MULTI MASTER IIC BUS ADDRESS IICADD REGISTER IICADD 0x54000008 IIC Bus address register Slave address 7 0 7 bit slave address latched from the IIC bus XXXXXXXX When serial output enable 0 in the IICSTAT IICADD is write enabled The IICADD value can be read any time regardless of the current serial output enable bit IICSTAT setting Slave address 7 1 Not mapped 0 MULTI MASTER IIC BUS TRANSMIT RECEIVE DATA SHIFT IICDS REGISTER Reset Value IICDS 0x5400000C IIC Bus transmit receive data shift register Data shift 7 0 8 bit data shift register for IIC bus Tx Rx operation XXXXXXXX When serial output enable 1 in the IICSTAT IICDS is write enabled The IICDS value can be read any time regardless of the current serial output enable bit IICSTAT setting ELECTRONICS 20 13 IIC BUS INTERFACE 53 2410 NOTES 20 14 ELECTRONICS 53 2410 IIS BUS INTERFACE 2 1 IIS BUS INTERFACE OVERVIEW Currently many digital audio systems are attracting the consumers on the market in the form of compact discs digital audio tapes digital sound processors and digital TV sound The S3C2410A Inter IC Sound 15 bus interface can be used to implement a CODEC interface to an external 8 16 bit stereo audio CODEC IC for mini disc and portable applications The IIS bus interface supports both IIS bus data format and MSB justif
342. is just lt than dividend R1 value To do this shift dividend right by 1 and stop as soon as shifted value becomes gt LSR RO R1 1 MOV R2 R3 B FTO just LSL R2 1 0 CMP R2 RO BLS just RO 0 Set accumulator to 0 B FTO Branch into division loop div 1 LSR R2 1 0 CMP R1 R2 Test subtract BCC FTO SUB R1 R2 If successful do a real subtract 0 ADC RO RO Shift result and add 1 if subtract succeeded CMP R2 R3 Terminate when R2 ie we have just BNE div 1 tested subtracting the ones value ELECTRONICS 4 41 THUMB INSTRUCTION SET S3C2410A Now fix up the signs of the quotient R0 and remainder R1 ARM Code signed_divide ip bit 31 sign of result POP EOR EOR SUB EOR SUB MOV ANDS RSBMI EORS ip bit 30 sign of a2 RSBCS R2 R3 R3 R2 RO R3 R0 R3 R1 R2 R1 R2 pc Ir a4 a1 amp 80000000 a1 a1 0 ip a4 a2 ASR 32 a2 a2 0 5 5 5 Get dividend divisor signs back Result sign Negate if result sign 1 Negate remainder if dividend sign 1 Effectively zero a4 as top bit will be shifted out later Central part is identical code to udiv without MOV a4 0 which comes for free as part of signed entry sequence just 1 div_ 4 42 MOVS BEQ CMP MOVLS BLO CMP ADC SUBCS TEQ MOVNE BNE MOV MOVS RSBCS RSBMI MOV a3 a1 divide_by_zero a3 a2 LSR 1 a3 a3 LSL 1 loop a2 a3 a4 a4 a4 a2 a
343. ish detect Busy Finish BusyFin e Only busy check finish This flag is cleared by setting one to this bit 0 not detect 1 busy finish detect des 2 Reserved Tx Data progress On TxDatOn Rx Data Progress On RxDatOn Data transmit in progress 0 not active 1 data Tx in progress Data receive in progress 0 not active 1 data Rx in progress Data Receive CRC Data block received error CRC check failed calculated by Fail DatCrc host This flag is cleared by setting one to this bit 0 not detect 1 receive crc fail 19 12 ELECTRONICS 53 2410 MMC SD SDIO HOST CONTROLLER SDI FIFO Status SDIFSTA Register Register Address Description Reset Value SDIFSTA 0x5A000038 FIFO status register FIFO available Indicate that FIFO data is available for transmission when Detect for Tx DatMode SDIDCON 12 is data transmit mode If DMA mode is TFDET enable SD host requests DMA operation 0 not detect FIFO full 1 detect 0 lt FIFO lt 63 FIFO available 12 Indicate that FIFO data is available for reception when DatMode Detect for Rx SDIDCON 12 is data receive mode If DMA mode is enable RFDET host requests DMA operation detect FIFO empty 1 detect 1 lt FIFO lt 64 Tx FIFO Half Full 11 Set to 1 whenever Tx FIFO is less than 33byte TFHalf 0 33 lt Tx FIFO lt 64 1 0 lt Tx FIFO lt 32 Rx FIFO Last Da
344. it Functions Asynchronous clock select See Table 2 11 on page 2 11 notFastBus select See Table 2 11 on page 2 11 Reserved Read Unpredictable Write Should be zero Round robin replacement 0 Random replacement 1 Round robin replacement 13 V bit Base location of exception 0 Low addresses 0x0000 0000 registers 1 High addresses OxFFFF 0000 Instruction cache enable 0 Instruction cache disabled 1 Instruction cache enabled 11 10 Reserved Read 00 Write 00 14 ROM protection This bit modifies the MMU protection system See Table 3 6 on page 3 20 S bit System protection This bit modifies the MMU protection system See Table 3 6 on page 3 20 Big endian little endian 0 Little endian operation 1 Big endian operation Reserved Read 1111 Write 1111 C bit Data cache enable 0 Data cache disabled 1 Data cache enabled A bit Alignment fault enable Data address alignment fault checing 0 Fault checking disabled 1 Fault checking enabled MMU enable 0 MMU disabled 1 MMU enabled Register 1 bits 31 30 select the clocking mode of the ARM920T as shown in Table 2 11 12 7 6 3 2 1 Table 2 11 Clocking Modes i m meme o j Z ELECTRONICS 2 11 PROGRAMMER S MODEL ARM920T PROCESSOR Enabling the MMU Care must be taken with the address mapping of the code sequence used to enable the MMU see Enabling the MMU on page 3 25 See Instruction cache e
345. it has to be High 3 3V OM 3 2 OM 3 2 determines how the clock is made OM 3 2 006 Crystal is used for MPLL CLK source and UPLL CLK source 3 2 016 Crystal is used for MPLL CLK source and EXTCLK is used for UPLL CLK source OM 3 2 106 EXTCLK is used for MPLL CLK source and Crystal is used for UPLL CLK source 3 2 116 EXTCLK is used for MPLL CLK source and UPLL CLK source ELECTRONICS 1 23 PRODUCT OVERVIEW S3C2410A Table 1 3 S3C2410A Signal Descriptions Continued Signal Description Reset Clock amp Power Continued EXTCLK External clock source When OM 3 2 11b EXTCLK is used for MPLL CLK source and UPLL CLK source When OM 3 2 10b EXTCLK is used for MPLL CLK source only When OM 3 2 01b EXTCLK is used for UPLL CLK source only If it isn t used it has to be High 3 3V XTIpll Crystal Input for internal osc circuit When OM 3 2 00b is used for MPLL CLK source and UPLL CLK source When OM 3 2 01b XTIpll is used for MPLL CLK source only When OM 3 2 10b is used for UPLL CLK source only If it isn t used has to be High 3 3V MPLLCAP Loop filter capacitor for main clock Loop filter capacitor for USB clock UPLLCAP 32 768 kHz crystal input for RTC If it isn t used it has to be in High RTCVDD 1 8 XTOrtc 32 768 kHz crystal output for RTC If it isn t used it has to be Float
346. its are not altered Also your program should not rely on them containing specific values since in future processors they may read as one or zero ELECTRONICS 2 9 PROGRAMMER S MODEL 53 2410 EXCEPTIONS Exceptions arise whenever the normal flow of a program has to be halted temporarily for example to service an interrupt from a peripheral Before an exception can be handled the current processor state must be preserved so that the original program can resume when the handler routine has finished It is possible for several exceptions to arise at the same time If this happens they are dealt with in a fixed order See Exception Priorities on page 2 14 Action on Entering an Exception When handling an exception the ARM920T 1 Preserves the address of the next instruction in the appropriate Link Register If the exception has been entered from ARM state then the address of the next instruction is copied into the Link Register that is current PC 4 or PC 8 depending on the exception See Table 2 2 on for details If the exception has been entered from THUMB state then the value written into the Link Register is the current PC offset by a value such that the program resumes from the correct place on return from the exception This means that the exception handler need not determine which state the exception was entered from For example in the case of SWI MOVS PC R14 svc will always return to the next instruction regardless o
347. its are used to decide whether the whole half or none of the line is written back to memory The line is written back to the same physical address from which it was loaded regardless of any changes to the MMU translation tables The DCache implements allocate on read miss Random or round robin replacement can be selected under software control via the RR bit CP15 register 1 bit 14 Random replacement is selected at reset Data can also be locked in the DCache such that it cannot be overwritten by a linefill This operates with a granularity of 1 64th of the cache which is 64 words 256 bytes All data accesses are subject to MMU permission and translation checks Data accesses which are aborted by the MMU will not cause linefills or data accesses to appear on the ASB For clarity the C bit bit 2 in CP15 register 1 is referred to as the Ccr bit throughout the following text ELECTRONICS 4 5 CACHES WRITE BUFFER ARM920T PROCESSOR DATA CACHE AND WRITE BUFFER ENABLE DISABLE On reset all DCache entries are invalidated the DCache is disabled and the write buffer contents are discarded There is no explicit write buffer enable bit implemented in ARM920T Situations in which the write buffer is used are described below The DCache is enabled by writing 1 to the bit and disabled by writing 0 to the Ccr bit The DCache must be enabled only when the MMU is enabled This is because the MMU translation tables define the cache an
348. itten with the loaded value ADDRESS ALIGNMENT The address should normally be a word aligned quantity and non word aligned addresses do not affect the instruction However the bottom 2 bits of the address will appear on A 1 0 and might be interpreted by the memory system 0x100C 0x100C 0x1000 0x1000 4 OxOFF4 1 y l 0 00 0x100C 0x1000 0x1000 0x0FF4 0x0FF4 Figure 3 19 Post Increment Addressing ELECTRONICS 3 41 ARM INSTRUCTION SET 3 42 Rn 3 0 100 0 1000 0 100 gt Figure 3 20 Pre Increment Addressing 0x100C 0x1000 R1 4 Rn gt 2 7 5 1 4 Figure 3 21 Post Decrement Addressing 0x100C 0x1000 OxOFF4 0x100C 0x1000 OxOFF4 0x100C 0x1000 OxOFF4 0x100C 0x1000 OxOFF4 S3C2410A ELECTRONICS 3C2410A ARM INSTRUCTION SET 0x100C 0x100C 0x1000 0x1000 OxOFF4 OxOFF4 1 0x100C 0x100C 0x1000 0x1000 OxOFF4 OxOFF4 Figure 3 22 Pre Decrement Addressing USE OF THE S BIT When the 5 bit is set in a LDM STM instruction its meaning depends on whether or not R15 is in the transfer list and on the type of instruction The S bit should only be set if the instruction is to execute in a privileged mode LDM with R15 in Transfer List and S Bit Set Mode Changes If the instruction is then SPSR mode is transferred to CPSR at the same time as R15 is loaded STM with
349. ity 110 Parity forced checked as 1 111 Parity forced checked as 0 M 7 Number of Stop Bit 2 Specify how many stop bits are to be used for end of frame signal 0 One stop bit per frame 1 Two stop bit per frame Word Length 1 0 Indicate the number of data bits to be transmitted or received per frame 00 5 bit 01 6 bit 10 7 bit 11 8 bit 11 10 ELECTRONICS 3C2410A UART UART CONTROL REGISTER There are three UART control registers including UCONO and UCONe in the UART block Clock Selection 10 Select or UEXTCLK for the UART baud rate 0 PCLK UBRDIVn int PCLK bps x 16 1 1 UEXTCLK GPH8 UBRDIVn int UEXTCLK bps x 16 1 Tx Interrupt Type Interrupt request type 0 Pulse Interrupt is requested as soon as the Tx buffer becomes empty in Non FIFO mode or reaches Tx FIFO Trigger Level in FIFO mode 1 Level Interrupt is requested while Tx buffer is empty in Non FIFO mode or reaches Tx FIFO Trigger Level in FIFO mode Interrupt request type 0 Pulse Interrupt is requested the instant Rx buffer receives the data in Non FIFO mode or reaches Rx FIFO Trigger Level in FIFO mode 1 Level Interrupt is requested while Rx buffer is receiving data in Non FIFO mode or reaches Rx FIFO Trigger Level in FIFO mode Rx Time Out Enable Disable Rx time out interrupt when UART FIFO is enabled mM Bl __ Rx Interrupt Type Enable The interrupt is a receive int
350. ive After Determine when data receive start after command sent or not Command 0 directly after DatMode set RACMD 1 after command sent assume DatMode sets to 2 b10 Busy After Determine when busy receive start after command sent or not Command 0 directly after DatMode set 1 after command sent assume DatMode sets to 2 b01 Block mode Data transfer mode 0 stream data transfer 1 block data transfer Wide bus enable Determine enable wide bus mode WideBus 0 standard bus mode only SDIDAT O0 used 1 wide bus mode SDIDAT 3 0 used DMA Enable Enable DMA EnDMA 0 disable polling 1 dma enable When DMA operation is completed this bit should be disabled Stop by force 14 Determine whether data transfer stop by force or not STOP 0 normal 1 stop by force Data Transfer 13 12 Determine the direction of data transfer Mode DatMode 00 ready 01 only busy check start 10 data receive start 11 data transmit start BlkNum 11 0 Block Number 074095 Do not care when stream mode NOTES 1 If you want one of TARSP RACMD and BACMD bits SDIDCON 20 18 to 1 you need to write on SDIDCON register head of on SDICCON register always need for SDIO 2 When DMA operation is completed DMA Enable 15 bit of SDIDCON register should be disabled 19 10 ELECTRONICS 53 2410 MMC SD SDIO HOST CONTROLLER SDI Data Remain Counter SDIDCNT Register Register Address Des
351. k General Port GPn 116 0 EN General input output ports some ports are output only TIMMER PWM TOUT 3 0 O Timer Output 3 0 TCLK 1 0 EE External timer clock input JTAG TEST LOGIC nTRST nTRST TAP Controller Reset resets the TAP controller at start If debugger is used A 10K pull up resistor has to be connected If debugger black ICE is not used nTRST pin must be issued by a low active pulse Typically connected to nRESET o TMS TAP Controller Mode Select controls the sequence of the TAP controller s states A 10K pull up resistor has to be connected to TMS pin TCK TCK TAP Controller Clock provides the clock input for the JTAG logic A 10K pull up resistor must be connected to TCK pin TDI TDI TAP Controller Data Input is the serial input for test instructions and data A 10K pull up resistor must be connected to TDI pin 0 TDO TAP Controller Data Output is the serial output for test instructions and data Reset Clock amp Power nRESET ST nRESET suspends any operation in progress and places S3C2410A into a known reset state For a reset nRESET must be held to L level for at least 4 FCLK after the processor power has been stabilized nRSTOUT For external device reset control nRSTOUT nRESET amp nWDTRST SW RESET PWREN nBATT_FLT 2 0V core power on off control signal Probe for battery state Does not wake up at power off mode in case of low battery state If it isn t used
352. l DMA 1 Current Source DMA 1 Current Destination R W DMA 1 Mask Trigger DMA 2 Initial Source DMA 2 Initial Source Control DMA 2 Initial Destination DMA 2 Initial Destination Control DMA 2 Current Source DMA 2 Current Destination RW DMA 3 Initial Source Control Initial 3 Initial Source Control Control DMA 3 Initial Destination DMA EM 3 Initial Destination Control Destination Control DCSRC3 0 4 000008 DMA DMA Current Source DMA 3 Current Source Source DSTAT3 0x4B0000D4 DMA 3 DCDST3 0x4B0000DC DMA 3 Current Destination 3 Current Destination Destination DMA 3 Mask Trigger DMASKTRIG3 0 4 0000 0 1 28 ELECTRONICS 3 2410 PRODUCT OVERVIEW Table 1 4 S3C2410A Special Registers Continued Register Address Address Acc Read Function Name B Endian L Endian Unit Write Clock amp Power Management RW w Generator Control CLKSLOW 0x4C000010 Clock Control CLKDIVN 0 4 000014 divider Control LCD Controller 0 0000000000 Controller KI T LCD Control 1 Address1 STN TFT Frame Buffer Start Address2 STN TFT Virtual Screen Address Set STN Red Lookup Table STN Green Lookup Table STN Blue Lookup Table STN Dithering Mode TFT Temporary Palette NAND Flash Tw NAND Flash Command NAND Flash Address NAND Flash Data LCD Interrupt Pending LCD Interrupt Source
353. l signal 1 Enable the video output and the LCD control signal 15 26 ELECTRONICS 3C2410A LCD CONTROLLER LCD Control 2 Register LCDCON2 0X4D000004 LCD control 2 register 0x00000000 VBPD 31 24 TFT Vertical back porch is the number of inactive lines at the start of 0x00 a frame after vertical synchronization period STN These bits should be set to zero on STN LCD LINEVAL 23 14 TFT STN These bits determine the vertical size of LCD panel 0000000000 VFPD 13 6 TFT Vertical front porch is the number of inactive lines at the end of 00000000 a frame before vertical synchronization period STN These bits should be set to zero on STN LCD VSPW 5 0 TFT Vertical sync pulse width determines the VSYNC pulse s high 000000 level width by counting the number of inactive lines STN These bits should be set to zero on STN LCD ELECTROUNICS 15 27 LCD CONTROLLER S3C2410A LCD Control 3 Register LCDCON3 0X4D000008 LCD control 3 register 0x00000000 HBPD TFT 25 19 TFT Horizontal back porch is the number of VCLK periods between 0000000 the falling edge of HSYNC and the start of active data WDLY STN STN WDLY 1 0 bits determine the delay between VLINE VCLK by counting the number of the HCLK WDLY 7 2 are reserved 00 16 HCLK 01 32 HCLK 10 48 HCLK 11 64 HCLK HOZVAL 18 8 TFT STN These bits determine the horizontal size of LCD panel 00000000000 HOZVAL has to be determined to meet t
354. l stop time can be detected as soon as the channel on off bit DMASKTRIGn 1 is set to off This stop is actual stop ON OFF 1 DMA channel on off bit 0 DMA channel is turned off DMA request to this channel is ignored DMA channel is turned on and the DMA request is handled This bit is automatically set to off if we set the DCONn 22 bit to no auto reload and or STOP bit of DMASKTRIGn to stop Note that when DCON 22 bit is no auto reload this bit becomes 0 when CURR reaches 0 If the STOP bit is 1 this bit becomes 0 as soon as the current atomic transfer is completed NOTE This bit should not be changed manually during DMA operations i e this has to be changed only by using DCON 22 or STOP bit SW TRIG Trigger the DMA channel in S W request mode 1 it requests a DMA operation to this controller Note that this trigger gets effective after S W request mode has to be selected DCONn 23 and channel ON OFF bit has to be set to 1 channel on When DMA operation starts this bit is cleared automatically NOTE You can freely change the values of DISRC register DIDST registers and TC field of register Those changes take effect only after the finish of current transfer i e when CURR TC becomes 0 On the other hand any change made to other registers and or fields takes immediate effect Therefore be careful in changing those registers and fields ELECTRONICS 8 13 DMA S3C2410A S W Work A
355. le for supplying the memory address and the coprocessor supplies or accepts the data and controls the number of words transferred 28 27 25 24 23 22 21 20 19 16 15 12 11 0 7 0 Unsigned 8 Bit Immediate Offset 11 8 Coprocessor Number 15 12 Coprocessor Source Destination Register 19 16 Base Register 20 Load Store Bit 0 Store to memory 1 Load from memory 21 Write back Bit 0 No write back 1 Write address into base 22 Transfer Length 23 Up Down Bit 0 Down subtract offset from base 1 Up add offset to base 24 Pre Post Indexing Bit 0 Post add offset after transfer 1 Pre add offset before transfer 31 28 Condition Field Figure 3 26 Coprocessor Data Transfer Instructions ELECTRONICS 3 53 ARM INSTRUCTION SET S3C2410A THE COPROCESSOR FIELDS The CP field is used to identify the coprocessor which is required to supply or accept the data and a coprocessor will only respond if its number matches the contents of this field The CRd field and the N bit contain information for the coprocessor which may be interpreted in different ways by different coprocessors but by convention CRd is the register to be transferred or the first register where more than one is to be transferred and the N bit is used to choose one of two transfer length options For instance N 0 could select the transfer of a single register and N 1 could select the transfer of all the registers for context switchin
356. lect the service mode between Single service mode and Whole service mode 0 Single service mode is selected in which after each atomic transfer single or burst of length four DMA stops and waits for another DMA request 1 Whole service mode is selected in which one request gets atomic transfers to be repeated until the transfer count reaches to 0 In this mode additional request are not required Note that even in the Whole service mode DMA releases the bus after each atomic transfer and then tries to re get the bus to prevent starving of other bus masters Select DMA request source for each DMA DCONO 000 nXDREQO 001 UARTO 010 SDI 011 Timer 100 USB device 000 nXDREQ1 001 UART1 010 25501 011 5 1 100 USB device EP2 DCON2 000 1255 DCONG 000 UART2 001 I2SSDI 001 SDI 010 SDI 010 SPI 011 Timer 100 USB device 011 Timer 100 USB device EP4 These bits control the 4 1 MUX to select the DMA request source of each DMA These bits have meanings only if H W request mode is selected by DCONn 23 Select the DMA source between software S W request mode and hardware H W request mode 0 S W request mode is selected and DMA is triggered by setting SW TRIG bit of DMASKTRIG control register 1 DMA source selected by bit 26 24 triggers the DMA operation Set the reload on off option 0 auto reload is performed when a current value of transfer count becomes 0 i e all the required tra
357. level one descriptor holds the 4 bit domain field which selects one of the 16 2 bit domains in the domain access control register The two bits of the specified domain are then checked for access permissions as detailed in Table 3 6 on page 3 20 In the case of a section the domain is checked once the level one descriptor is returned and in the case of a page the domain is checked once the level one descriptor is returned If the specified access is either no access 00 or reserved 10 then either a section domain fault or page domain fault occurs 3 22 ELECTRONICS ARM920T PROCESSOR PERMISSION FAULT MMU If the 2 bit domain field returns 01 client then access permissions are checked as follows Section Large page small page Tiny page ELECTRONICS If the level one descriptor defines a section mapped access the AP bits of the descriptor define whether or not the access is allowed according to Table 3 6 on page 3 20 Their interpretation is dependent upon the setting of the S and R bits control register bits 8 and 9 If the access is not allowed a section permission fault is generated If the level one descriptor defines a page mapped access and the level two descriptor is for a large or small page four access permission fields are specified each corresponding to one quarter of the page Hence for small pages is selected by the top 1KB of the page and is selected by the bottom 1KB of the
358. lf Assembles to OxE7FE Note effect of PC offset B jimmy Branch to jimmy Note that the THUMB opcode will contain the number of halfwords to offset jimmy Must be halfword aligned ELECTRONICS 4 37 THUMB INSTRUCTION SET S3C2410A FORMAT 19 LONG BRANCH WITH LINK 15 14 13 10 12 11 ili 10 0 Long Branch and Link Offset High Low 11 Low High Offset Bit 0 Offset high 1 Offset low Figure 4 20 Format 19 OPERATION This format specifies a long branch with link The assembler splits the 23 bit two s complement half word offset specified by the label into two 11 bit halves ignoring bit 0 which must be 0 and creates two THUMB instructions Instruction 1 H 0 In the first instruction the Offset field contains the upper 11 bits of the target address This is shifted left by 12 bits and added to the current PC address The resulting address is placed in LR Instruction 2 H 1 In the second instruction the Offset field contains an 11 bit representation lower half of the target address This is shifted left by 1 bit and added to LR LR which now contains the full 23 bit address is placed in PC the address of the instruction following the BL is placed in LR and bit 0 of LR is set The branch offset must take account of the prefetch operation which causes the PC to be 1 word 4 bytes ahead of the current instruction 4 38 ELECTRONICS 3C2410A THUMB INSTRUCTION SET I
359. lse Width Modulation u 10 7 Output Eevel Gontrol n hin eA ae an suqta 10 8 Dead Zone Generators mu Se d t Aie nm m at wama sns 10 9 Dma hequest Mode mene teen d biu e e e iue ie eue wa A un 10 10 PWM Timer Control 10 11 Timer Configuration Register 0 10 11 Timer Configuration Register 1 1 10 12 Timer Control TCON 10 13 Timer 0 Count Buffer Register amp Compare Buffer Register 10 15 Timer 0 Count Observation Register TCNTO0 L n nnne nenas 10 15 Timer 1 Count Buffer Register amp Compare Buffer Register TCNTB1 TCMPB1 10 16 Timer 1 Count Observation Register 10 16 Timer 2 Count Buffer Register amp Compare Buffer Register 2 2 10 17 Timer 2 Count Observation Register 2 U 10 17 Timer 3 Count Buffer Register amp Compare Buffer Register 10 18 Timer 3 Count Observation Register TCNTO9 10 18 Timer
360. lthough you does not use the IIC interrupt ELECTRONICS 20 11 IIC BUS INTERFACE MULTI MASTER CONTROL STATUS IICSTAT REGISTER IICSTAT 0x54000004 I C Bus control status register IICSTAT Mode selection 7 6 Busy signal status START STOP condition Arbitration status flag Read Only Address as slave status flag Read Only Address zero status flag Read Only Last received bit status flag Read Only 20 12 IIC bus master slave Tx Rx mode select bits 00 Slave receive mode 01 Slave transmit mode 10 Master receive mode 11 Master transmit mode I C Bus busy signal status bit 0 read Not busy when read write STOP signal generation 1 read Busy when read write START signal generation The data in IICDS will be transferred automatically just after the start signal IIC bus data output enable disable bit 0 Disable Rx Tx 1 Enable Rx Tx IIC bus arbitration procedure status flag bit 0 Bus arbitration successful 1 Bus arbitration failed during serial I O IIC bus address as slave status flag bit 0 Cleared when START STOP condition was detected 1 Received slave address matches the address value in the IICADD IIC bus addresses zero status flag bit 0 Cleared when START STOP condition was detected 1 Received slave address is 000000006 IIC bus last received bit status flag bit 0 Last received bit is 0 ACK was received 1 Last received bit
361. lue 8 Perform Software Interrupt Move the address of the next instruction into LR move CPSR to SPSR load the SWI vector address 0x8 into the PC Switch to ARM state and enter SVC mode NOTE Value8 is used solely by the SWI handler it is ignored by the processor INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 18 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES SWI 18 Take the software interrupt exception Enter Supervisor mode with 18 as the requested SWI number 4 36 ELECTRONICS 3C2410A THUMB INSTRUCTION SET FORMAT 18 UNCONDITIONAL BRANCH 15 14 13 10 0 1 12 11 ili o 10 0 Immediate Value Figure 4 19 Format 18 OPERATION This instruction performs a PC relative Branch The THUMB assembler syntax is shown below The branch offset must take account of the prefetch operation which causes the PC to be 1 word 4 bytes ahead of the current instruction Table 4 19 Summary of Branch Instruction B label BAL label halfword offset Branch PC relative Offset11 lt lt 1 where label is PC 2048 bytes NOTE The address specified by label is a full 12 bit two s complement address but must always be halfword aligned ie bit 0 set to 0 since the assembler places label gt gt 1 in the Offset11 field EXAMPLES here B here Branch onto itse
362. lue from contents of Rs Place result in Rd d ELECTRONICS 4 7 THUMB INSTRUCTION SET S3C2410A INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 3 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES ADD RO R3 R4 RO R4 and set condition codes on the result SUB R6 R2 6 R2 6 and set condition codes 4 8 ELECTRONICS 3C2410A THUMB INSTRUCTION SET FORMAT 3 MOVE COMPARE ADD SUBTRACT IMMEDIATE 15 14 13 7 0 12 11 10 8 Popo ome 7 0 Immediate Vale 10 8 Source Destination Register 12 11 Opcode 0 1 2 ADD 3 SUB Figure 4 4 Format 3 OPERATIONS The instructions in this group perform operations between a Lo register and an 8 bit immediate value The THUMB assembler syntax is shown in Table 4 4 NOTE All instructions in this group set the CPSR condition codes Table 4 4 Summary of Format 3 Instructions 00 MOV Ra Offset8 MOVS Ra Offset8 Move 8 bit immediate value into Rd CMP Rd Offset8 CMP Rd Offset8 Compare contents of Rd with 8 bit immediate value 10 ADD Ra Offset8 ADDS Offset8 Add 8 bit immediate value to contents of Rd and place the result in Rd 11 SUB Rad Offset8 SUBS Fad Rd Offset8 Subtract 8 bit immediate value from contents of Rd and place the result in Rd ELECT
363. ly Register 16 Byte Receive FIFO Register FIFO mode In FIFO mode all 16 Byte of Buffer register are used as FIFO register In non FIFO mode only 1 Byte of Buffer register is used as Holding register Figure 11 1 UART Block Diagram with FIFO 11 2 ELECTRONICS 3C2410A UART UART OPERATION The following sections describe the UART operations that include data transmission data reception interrupt generation baud rate generation Loopback mode Infra red mode and auto flow control Data Transmission The data frame for transmission is programmable It consists of a start bit 5 to 8 data bits an optional parity bit and 1 to 2 stop bits which can be specified by the line control register ULCONn The transmitter can also produce the break condition which forces the serial output to logic 0 state for one frame transmission time This block transmits break signals after the present transmission word is transmitted completely After the break signal transmission it continuously transmits data into the Tx FIFO Tx holding register in the case of Non FIFO mode Data Reception Like the transmission the data frame for reception is also programmable It consists of a start bit 5 to 8 data bits an optional parity bit and 1 to 2 stop bits in the line control register ULCONn The receiver can detect overrun error and frame error The overrun error indicates that new data has overwritten the old data before the old data
364. m clocks by software for the reduction of power consumption in the 53 2410 These schemes are related to PLL clock control logics HCLK and PCLK and wakeup signals Figure 7 7 shows the clock distribution of the S8C2410A The 53 2410 has four power modes The following section describes each power management mode The transition between the modes is not allowed freely For available transitions among the modes see Figure 7 8 Clock Control Register Jt Input Clock Power gt Management UCLK 48 MHz FCLK defination If SLOW mode FCLK input clock divider ratio Nand Flash Normal mode P M amp S value Controller FCLK MPLL clock Mpll Device Figure 7 7 The Clock Distribution Block Diagram ELECTRONICS 7 9 CLOCK amp POWER MANAGEMENT S3C2410A IDLE_BIT 1 Interrupts EINT 0 23 RTC alarm NORMAL SLOW_BIT 0 EINT 15 0 RTC alarm SLOW SLOW_BIT 1 POWER_OFF BIT 1 POWER OFF Figure 7 8 Power Management State Diagram Table 7 2 Clock and Power State in Each Power Mode ARM920T AHB Modules 1 Power 32 768kHz APB Modules 2 Management RTC clock amp USBH LCD NAND OFF NOTES Pp o OFF Wait for wake Previous up event state 1 USB host LCD and NAND are excluded 2 WDTis excluded RTC interface for CPU access is included 3 SEL selectable O X O enable X disable OFF power is turned off L L L o o s
365. mediately proceeds to the FIQ vector A normal return from FIQ will cause the data abort handler to resume execution Placing data abort at a higher priority than FIQ is necessary to ensure that the transfer error does not escape detection The time for this exception entry should be added to worst case FIQ latency calculations 2 14 ELECTRONICS 3C2410A PROGRAMMER S MODEL INTERRUPT LATENCIES The worst case latency for FIQ assuming that it is enabled consists of the longest time the request can take to pass through the synchronizer Tsyncmax if asynchronous plus the time for the longest instruction to complete the longest instruction is an which loads all the registers including the PC plus the time for the data abort entry Texc plus the time for entry At the end of this time 920 will be executing the instruction at Ox1C Tsyncmax is 3 processor cycles Tldm is 20 cycles Texc is 3 cycles and Tfiq is 2 cycles The total time is therefore 28 processor cycles This is just over 1 4 microseconds in a system which uses a continuous 20 MHz processor clock The maximum IRQ latency calculation is similar but must allow for the fact that FIQ has higher priority and could delay entry into the IRQ handling routine for an arbitrary length of time The minimum latency for FIQ or IRQ consists of the shortest time the request can take through the synchronizer Tsyncmin plus Tfiq This is 4 processor cycles RESE
366. memory page size should be 512Bytes NCON NAND flash memory address step selection 0 3 Step addressing 1 4 Step addressing 512 BYTE ECC PARITY CODE ASSIGNMENT TABLE emm peras DATA2 DATA DATAS S3C2410A generates 512 Byte ECC Parity Code during Write Read operation ECC Parity Code consists of 3 Bytes per 512 Byte data 24 bit ECC Parity Code 18 bit Line parity 6 bit Column Parity ECC generator block executes the followings 1 When MCU writes data to NAND the ECC generator block generates ECC code 2 When MCU reads data from NAND the ECC generator block generates ECC code and users compare it with pre written ECC code 6 4 ELECTRONICS 3C2410A NAND FLASH CONTROLLER NAND FLASH MEMORY MAPPING OxFFFF_FFFF Not Used Not Used 0 6000_0000 SFR Area SFR Area 0 4800 0000 0 4000 OFFF BootSRAM Not Used 0 4000 0000 4KBytes SDRAM SDRAM BANK7 nGCS7 BANK7 nGCS7 0x3800_0000 SDRAM SDRAM BANK6 nGCS6 BANK6 nGCS6 0x3000_0000 SROM SROM 5 nGCS5 5 nGCS5 0x2800_0000 SROM SROM nGCS4 BANK4 nGCS4 0x2000_0000 SROM SROM nGCS3 nGCS3 0x1800 0000 SROM SROM BANK2 nGCS2 BANK2 nGCS2 0 1000_0000 SROM SROM BANK1 nGCS1 BANK1 nGCS1 0x0800 0000 22 BootSRAM 0 0 0000 0000 KBytes 1 0 01 10 OM 1 0 00 a Not using NAND flash a Using NAND flash for for booting RO
367. mines the bus width of nGCSO The pull up down resistor determines the logic level during the RESET cycle 00 Nand boot 01 16 bit 10 32 bit 11 Test mode ADDR 26 0 o ADDR 26 0 Address Bus outputs the memory address of the corresponding bank DATA 31 0 DATA 31 0 Data Bus inputs data during memory read and outputs data during memory write The bus width is programmable among 8 16 32 bit nGCS 7 0 nGCS 7 0 General Chip Select are activated when the address of a memory is within the address region of each bank The number of access cycles and the bank size can be programmed nWE Write Enable indicates that the current bus cycle is a write cycle E o nOE Output Enable indicates that the current bus cycle is a read cycle nXBREQ nXBREQ Bus Hold Request allows another bus master to request control of the local bus BACK active indicates that bus control has been granted nXBACK nXBACK Bus Hold Acknowledge indicates that the S3C2410A has surrendered control of tis local bus to another bus master nWAIT nWAIT requests to prolong a current bus cycle As long as nWAIT is L the current bus cycle cannot be completed If nWAIT signal isn t used in your system nWAIT signal must be tied on pull up resistor SDRAM SRAM nSRAS SDRAM Row Address Strobe nSCAS SDRAM Column Address Strobe nSCS 1 0 O SDRAM Chip Select DOM 3 0 SDRAM Data Mask SCLK 1 0 SDRAM Clock SCKE O SDRAM Clock
368. mit FIFO is empty FIFO ready flag is set to 0 When receive FIFO is not full the FIFO ready flag for receive FIFO is set to 1 it indicates that FIFO is ready to receive data If receive FIFO is full FIFO ready flag is set to 0 These flags can determine the time that CPU is to write or read FIFOs Serial data can be transmitted or received while the CPU is accessing transmit and receive FIFOs in this way 21 2 ELECTRONICS 3C2410A IIS BUS INTERFACE DMA Transfer In this mode transmit or receive FIFO is accessible by the DMA controller DMA service request in transmit or receive mode is made by the FIFO ready flag automatically Transmit and Receive Mode In this mode IIS bus interface can transmit and receive data simultaneously AUDIO SERIAL INTERFACE FORMAT IIS BUS FORMAT The IIS bus has four lines including serial data input IISDI serial data output IISDO left right channel select IISLRCK and serial bit clock IISCLK the device generating IISLRCK and IISCLK is the master Serial data is transmitted in 2 s complement with the MSB first The MSB is transmitted first because the transmitter and receiver may have different word lengths The transmitter does not have to know how many bits the receiver can handle nor does the receiver need to know how many bits are being transmitted When the system word length is greater than the transmitter word length the word is truncated least significant data bits are set to 0
369. mory 1 Load from memory Figure 4 12 Format 11 OPERATION The instructions in this group perform an SP relative load or store The THUMB assembler syntax is shown in the following table Table 4 12 SP Relative Load Store Instructions STR SP STR Rd R13 lmm Add unsigned offset 255 words 1020 bytes in Imm to the current value of the SP R7 Store the contents of Rd at the resulting address LDR Imm LDR Rd R13 lmm Add unsigned offset 255 words 1020 bytes in Imm to the current value of the SP R7 Load the word from the resulting address into Rd NOTE The offset supplied in Imm is a full 10 bit address but must always be word aligned ie bits 1 0 set to 0 since the assembler places gt gt 2 in the Word8 field 4 26 ELECTRONICS 3C2410A THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 12 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES STR R4 SP 492 Store the contents of R4 at the address formed by adding 492 to SP R13 Note that the THUMB opcode will contain 123 as the Word8 value ELECTRONICS 4 27 THUMB INSTRUCTION SET 53 2410 FORMAT 12 LOAD ADDRESS 15 14 13 7 0 12 11 10 8 ra J 7 0 8 bit Unsigned Constant 10 8 Destination Register 11 Sou
370. mposed of 32 bits each of which is related to an interrupt source Each bit is set to 1 if the corresponding interrupt source generates the interrupt request and waits for the interrupt to be serviced Accordingly this register indicates which interrupt source is waiting for the request to be serviced Note that each bit of the SRCPND register is automatically set by the interrupt sources regardless of the masking bits in the INTMASK register In addition the SRCPND register is not affected by the priority logic of interrupt controller In the interrupt service routine for a specific interrupt source the corresponding bit of the SRCPND register has to be cleared to get the interrupt request from the same source correctly If you return from the ISR without clearing the bit the interrupt controller operates as if another interrupt request came in from the same source In other words if a specific bit of the SRCPND register is set to 1 it is always considered as a valid interrupt request waiting to be serviced The time to clear the corresponding bit depends on the user s requirement If you want to receive another valid request from the same source you should clear the corresponding bit first and then enable the interrupt You can clear a specific bit of the SRCPND register by writing a data to this register It clears only the bit positions of the SRCPND corresponding to those set to one in the data The bit positions corresponding to those that are
371. multaneously with an external device serial clock line is synchronized with the two data lines for shifting and sampling of the information When the SPI is the master transmission frequency can be controlled by setting the appropriate bit to SPPREn register You can modify its frequency to adjust the baud rate data register value When the SPI is a slave other master supplies the clock When the programmer writes byte data to SPTDATn register SPI transmit receive operation will start simultaneously In some cases nSS should be activated before writing byte data to SPTDATn Programming Procedure When a byte data is written into the SPTDATn register SPI starts to transmit if ENSCK and MSTR of SPCONn register are set You can use a typical programming procedure to operate an SPI card To program the SPI modules follow these basic steps Set Baud Rate Prescaler Register SPPREn Set SPCONn to configure properly the SPI module Write data OxFF to SPTDATn 10 times in order to initialize MMC or SD card Set a GPIO pin which acts as nSS to low to activate the MMC or SD card Tx data Check the status of Transfer Ready flag REDY 1 and then write data to SPTDATn Rx data 1 SPCONn s TAGD bit disable normal mode write OxFF to then confirm REDY to set and then read data from Read Buffer 7 2 SPCONn s TAGD bit enable Tx Auto Garbage Data mode confirm REDY to set and then read data from Read Bu
372. n P P P17 _____ o jvoiUPL P P P f de Ni5 vssiuptt jvssuu P P P si His JULLCAP A Nie jv 1 voor P P P 49 Nia ENTUGPFO ero 1 7 ENT GPF Gerh ENTZGPFO ere 8 Mi ENTSGPF Gers 1 6 Mi5 1 e Mi4 ENTSGPFS 1 8 Lis Gere 1 L7 JENTZGPF7 Ger 1 Li6 jUEXrcLKGPH8 1 PHO 1 8 2 nRTSUGPHi eem om f 8 Kis om 1 8 Kir ehs 1 8 Ki6 GPH4 om f e Kw RXbugPHh 1 1 14 ELECTRONICS 3 2410 PRODUCT OVERVIEW Table 1 2 272 Pin FBGA Pin Assignments Continued a 30 Function BUS REQ off nRESET amme 12 nRESET nRESET P Waw ass SEN wr 08 P pe j NN NEC d war scs su hz ed T TIT 2 LIL 5 gt SISI 89
373. n equivalent ARM instruction as shown in Table 4 15 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES PUSH RO R4 LR Store RO R1 R2 R3 R4 and R14 LR at the stack pointed to by R13 SP and update R13 Useful at start of a sub routine to Save workspace and return address POP R2 R6 PC Load R2 R6 and R15 PC from the stack pointed to by R13 SP and update R13 Useful to restore workspace and return from sub routine 4 32 ELECTRONICS 3C2410A THUMB INSTRUCTION SET FORMAT 15 MULTIPLE LOAD STORE 15 14 13 7 0 1 12 11 10 8 ili 7 0 Register List 10 8 Base Register 11 Load Store Bit 0 Store to memory 1 Load from memory Figure 4 16 Format 15 OPERATION These instructions allow multiple loading and storing of Lo registers The THUMB assembler syntax is shown in the following table Table 4 16 The Multiple Load Store Instructions STMIA Rb Rlist STMIA Rb Rlist Store the registers specified by Rlist starting at the base address in Rb Write back the new base address LDMIA Rb Rlist LDMIA Rb Rlist Load the registers specified by Rlist starting at the base address in Rb Write back the new base address INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 16 The instruction cycle times for the THUMB instructi
374. n expression which generates an address The assembler will attempt to generate an instruction using the PC as a base anda corrected immediate offset to address the location given by evaluating the expression This will be a PC relative pre indexed address If the address is out of range an error will be generated A pre indexed addressing specification Rn offset of zero Rn lt expression gt offset of lt expression gt bytes Rn Rm offset of contents of index register A post indexed addressing specification Rn lt expression gt Rn Rn and Rm are expressions evaluating to a register number If Rn is R15 then the assembler will subtract 8 from the offset value to allow for ARM920T pipelining In this case base write back should not be specified offset of expression bytes offset of contents of index register Writes back the base register set the W bit if is present ELECTRONICS 3C2410A EXAMPLES LDRH STRH LDRSB LDRNESH HERE STRH FRED ELECTRONICS R1 R2 R3 R3 R4 14 R8 R2 223 R11 RO R5 PC FRED HERE 8 ARM INSTRUCTION SET Load R1 from the contents of the halfword address contained in R2 R3 both of which are registers and write back address to R2 Store the halfword in R3 at R14 14 but don t write back Load R8 with the sign extended contents of the byte address contained in R2 and write back R2 223 to R2 Conditionally loa
375. n the DCache can be located in a cacheable region of memory providing it does not contain any loads or stores other than the loads which are used to bring the data to be locked into the DCache The data to be loaded must be from a memory region which is cacheable ELECTRONICS 4 9 CACHES WRITE BUFFER ARM920T PROCESSOR CACHE COHERENCE The and DCache contain copies of information normally held in main memory If these copies of memory information get out of step with each other because one is updated and the others are not updated they are said to have become incoherent If the DCache contains a line which has been modified by a store or swap instruction and the main memory has not been updated the cache line is said to be dirty Clean operations force the cache to write dirty lines back to main memory On ARM920T software is responsible for maintaining coherence between main memory the and the DCache Register 7 Cache operations page 2 15 describes facilities for invalidating the entire or individual lines and for cleaning or invalidating DCache lines or for invalidating the entire DCache To clean the entire DCache efficiently software should loop though each cache entry using the clean D single entry using index operation or the clean and invalidate D entry using index operation This should be performed by a two level nested loop going though each index value for each s
376. n the every event of the elapse of the specified number of VLINE by the MVAL 7 0 value Figure 15 4 shows an example for MMODE 0 and for MMODE 1 with the value of MVAL 7 0 0x2 When MMODE 1 the VM rate is related to MVAL 7 0 as shown below VM Rate VLINE Rate 2 MVAL The VFRAME and VLINE pulse generation relies on the configurations of the HOZVAL field and the LINEVAL field in the LCDCON2 3 register Each field is related to the LCD size and display mode In other words the HOZVAL and LINEVAL can be determined by the size of the LCD panel and the display mode according to the following equation HOZVAL Horizontal display size Number of the valid VD data line 1 In color mode Horizontal display size 3 Number of Horizontal Pixel In the 4 bit single scan display mode the Number of valid VD data line should be 4 In case of 4 bit dual scan display the Number of valid VD data line should also be 4 while in case of 8 bit single scan display mode the Number of valid VD data line should be 8 LINEVAL Vertical display size 1 In case of single scan display type LINEVAL Vertical display size 2 1 In case of dual scan display type The rate of VCLK signal depends on the configuration of the CLKVAL field in the LCDCON1 register Table 15 1 defines the relationship of VCLK and CLKVAL The minimum value of CLKVAL is 2 VCLK Hz HCLK CLKVAL x 2 The frame rate is the VFRAM signal frequency The frame rate is cl
377. nable disable on page 4 3 and Data cache and write buffer enable disable on page 4 6 for restrictions and effects of having caches enabled with the MMU disabled REGISTER 2 TRANSLATION TABLE BASE TTB REGISTER This is the translation table base register for the currently active first level translation table The contents of register 2 are shown in Table 2 12 Table 2 12 Register 2 Translation Table Base 31 14 Pointer to first level translation table base Read write Reserved Read Unpredictable Write Should be zero Reading from register 2 returns the pointer to the currently active first level translation table in bits 31 14 Writing to register 2 updates the pointer to the first level translation table from the value in bits 31 14 of the written value Bits 13 0 should be zero when written and are unpredictable when read The following instructions can be used to access the TTB MRC p15 0 Rd c2 c0 0 read TTB register MCR p15 0 c2 0 write TTB register 2 12 ELECTRONICS ARM920T PROCESSOR PROGRAMMER S MODEL REGISTER 3 DOMAIN ACCESS CONTROL REGISTER Register 3 is the read write domain access control register consisting of sixteen 2 bit fields Each of these 2 bit fields defines the access permissions for the domains shown in Table 2 13 Table 2 13 Register 3 Domain Access Control mers Dom mm m wm gt p _ 98 B m m The encoding of the two bit domain access
378. nd Point out control status register1 0x00 0x52000193 B byte CLR DATA 7 RAN CLEAR When the MCU writes a 1 to this bit the data TOGGLE toggle sequence bit is reset to DATAO SENT STALL 6 R SET Set by the USB when an OUT token is ended with a STALL handshake The USB issues a stall handshake to the host if it sends more than MAXP data for the OUT TOKEN FIFO FLUSH 4 R W CLEAR The MCU writes a 1 to flush the FIFO This bit can be set only when OUT_PKT_RDY 00 is set The packet due to be unloaded by the MCU will be flushed meme CSCS OUT_PKT_RDY R SET Set by the USB after it has loaded a packet CLEAR of data into the FIFO Once the MCU reads the packet from FIFO this bit should be cleared by MCU write 0 SEND_STALL 5 R W 0 The MCU clears this bit to end the STALL condition handshake IN PKT RDY is cleared 1 The MCU issues a STALL handshake to the USB The MCU clears this bit to end the STALL condition handshake IN PKT RDY is cleared 13 16 ELECTRONICS 53 2410 USB DEVICE END POINT OUT CONTROL STATUS REGISTER OUT_CSR1_REG OUT_CSR2_REG Continued OUT_CSR2_REG 0x52000194 L R W Point out control status register2 0x00 0x52000197 B byte AUTO CLR If the MCU is set whenever the MCU reads data from the OUT FIFO OUT PKT RDY will automatically be cleared by the logic without any intervention from the MCU OUT Determine whether the interrupt should be MA
379. ndexed data transfers always write back the modified base The Write back bit should not be set high W 1 when post indexed addressing is selected ELECTRONICS 3 35 ARM INSTRUCTION SET 53 2410 HALFWORD LOAD AND STORES Setting 5 0 and H 1 may be used to transfer unsigned Half words between ARM920T register and memory The action of LDRH and STRH instructions is influenced by the BIGEND control signal The two possible configurations are described in the section below Signed byte and halfword loads The S bit controls the loading of sign extended data When S 1 the H bit selects between Bytes H 0 and Half words H 1 The L bit should not be set low Store when Signed S 1 operations have been selected The LDRSB instruction loads the selected Byte into bits 7 to 0 of the destination register and bits 31 to 8 of the destination register are set to the value of bit 7 the sign bit The LDRSH instruction loads the selected Half word into bits 15 to 0 of the destination register and bits 31 to 16 of the destination register are set to the value of bit 15 the sign bit The action of the LDRSB and LDRSH instructions is influenced by the BIGEND control signal The two possible configurations are described in the following section Endianness and byte halfword selection Little Endian Configuration A signed byte load LDRSB expects data on data bus inputs 7 through to 0 if the supplied address is on a word boundary
380. ne times pixel off and the 13th gray level should have 4 times pixel on and one times pixel off and the gray level should always have pixel off as shown in Table 15 2 Table 15 2 Dither Duty Cycle Examples foray level number level number __ _ 2 x s 0l w o J o ELECTRONICS 15 7 LCD CONTROLLER S3C2410A Display Types The LCD controller supports 3 types of LCD drivers 4 bit dual scan 4 bit single scan and 8 bit single scan display mode Figure 15 2 shows these 3 different display types for monochrome displays and Figure 15 3 show these 3 different display types for color displays 4 bit Dual Scan Display Type A 4 bit dual scan display uses 8 parallel data lines to shift data to both the upper and lower halves of the display at the same time The 4 bits of data in the 8 parallel data lines are shifted to the upper half and 4 bits of data is shifted to the lower half as shown in Figure 15 2 The end of frame is reached when each half of the display has been shifted and transferred The 8 pins VD 7 0 for the LCD output from the LCD controller can be directly connected to the LCD driver 4 bit Single Scan Display Type A 4 bit single scan display uses 4 parallel data lines to shift data to successive single horizontal lines of the display at a time until the entire frame has been shifted and transferred The 4 pins VD 3 0 for the LCD output from th
381. nerate an instruction using the PC as a base anda corrected immediate offset to address the location given by evaluating the expression This will be a PC relative pre indexed address If the address is out of range an error will be generated A pre indexed addressing specification Rn offset of zero Rn lt expression gt Rn Rm lt shift gt offset of lt expression gt bytes offset of contents of index register shifted by lt shift gt A post indexed addressing specification Rn lt expression gt Rn Rm lt shift gt offset of lt expression gt bytes offset of contents of index register shifted as by lt shift gt General shift operation see data processing instructions but you cannot specify the shift amount by a register Writes back the base register set the W bit if is present ELECTRONICS 3C2410A EXAMPLES STR STR LDR LDR LDREQB STR PLACE ELECTRONICS R1 R2 R4 R1 R2 R4 R1 R2 46 R1 R2 R3 LSL 2 R1 R6 5 R1 PLACE ARM INSTRUCTION SET Store R1 at R2 R4 both of which are registers and write back address to R2 Store R1 at R2 and write back R2 R4 to R2 Load R1 from contents of R2 16 but don t write back Load R1 from contents of R2 R3 4 Conditionally load byte at R6 5 into R1 bits O to 7 filling bits 8 to 31 with zeros Generate PC relative offset to address PLACE 3 33 ARM INSTRUCTION SET S3C2410A HALFWORD AND SIGNED
382. ng 10ms if this bit is set in suspend mode SET Set by USB automatically when the device CLEAR enter into suspend mode It is cleared under the following conditions 1 The MCU clears the MCU_RESUME bit by writing 0 in order to end remote resume signaling 2 The resume signal form host is received R W Suspend mode enable control bit 0 Disable default The device will not enter suspend mode 1 Enable suspend mode 13 6 ELECTRONICS 53 2410 USB DEVICE INTERRUPT REGISTER EP_INT_REG USB_INT_REG The USB core has two interrupt registers These registers act as status registers for the MCU when it is interrupted The bits are cleared by writing 1 not 0 to each bit that was set Once the MCU is interrupted MCU should read the contents of interrupt related registers and write back to clear the contents if it is necessary Reset Value EP INT REG 0x52000148 L R W EP interrupt pending clear register 0x00 0x5200014B B byte EP1 EP4 Interrupt 4 1 R SET For BULK INTERRUPT IN endpoints CLEAR Set by the USB under the following conditions 1 IN PKT RDY bit is cleared 2 FIFO is flushed 3 SENT STALL set For BULK INTERRUPT OUT endpoints Set by the USB under the following conditions 1 Sets OUT PKT RDY bit 2 Sets SENT bit NOTE Conditions 1 and 2 are mutually exclusive EPO Interrupt R SET to endpoint 0 interrupt CLEAR Set by the USB under the following conditio
383. ngineer Please answer the following questions Application Product Model ID Audio Video Telecom L LCD Databank Industrials Home Appliance Office Automation Remocon Other Please describe in detail its application For duplicate copies of this form and for additional ordering information please contact your local Samsung sales representative Samsung sales offices are listed on the back cover of this book
384. ns 1 OUT_PKT_RDY bit is set 2 IN PKT RDY bit is cleared 3 SENT bit is set 4 SETUP END bit is set 5 DATA END bit is cleared it indicates the end of control transfer ELECTRONICS 13 7 USB DEVICE 53 2410 INTERRUPT REGISTER EP_INT_REG USB_INT_REG Continued 0x52000158 L R W 0x5200015B B byte USB USB_INT_REG USB INT REG Bit M RESET Interrupt 2 RESUME Interrupt R 1 R SET CLEAR R SET CLEAR If the RESET interrupt is occurred all USB device registers should be re configured SUSPEND Interrupt NOTE USB interrupt pending clear register Set by the USB when it receives reset signaling Set by the USB when it receives resume signaling while_in Suspend mode If the resume occurs due to a USB reset then the MCU is first interrupted with a RESUME interrupt Once the clocks resume and the SEO condition persists for 2 5us USB RESET interrupt will be asserted NOTE If S W can t recognize the RESUME interrupt bit before RESET interrupt is asserted resume interrupt bit will be cleared by RESET interrupt Set by the USB when it receives suspend signalizing This bit is set whenever there is no activity for 3ms on the bus Thus if the MCU does not stop the clock after the first suspend interrupt it will continue to be interrupted every 3ms as long as there is no activity on the USB bus By default this interrupt is disabled ELECTRONICS 53 24
385. nsecutive accesses 11 16 consecutive accesses Memory Type SDRAM MT 11 4 bit 3 2 RAS to CAS delay 00 2clocks 01 10 4 clocks 1 0 Column address number 00 8 bit 01 9 bit 10 10 bit 5 16 ELECTRONICS 53 2410 MEMORY CONTROLLER REFRESH CONTROL REGISTER REFRESH 0x48000024 SDRAM refresh control register 0 0000 REFEN 23 SDRAM Refresh Enable 0 Disable 1 Enable self auto refresh TREFMD 22 SDRAM Refresh Mode 0 Auto Refresh 1 Self Refresh In self refresh time the SDRAM control signals are driven to the appropriate level Trp 21 20 SDRAM RAS pre charge Time 00 2 clocks 01 3 clocks 10 4 clocks 11 Not support Tsrc 19 18 SDRAM Semi Row Cycle Time 00 4 clocks 01 5clocks 10 6clocks 11 7 clocks SDRAM s Row Cycle time Trc Trp If Trp 3 clocks amp Tsrc 7 clocks Trc 3 7 10 clocks ism 506 Refresh SDRAM refresh count value Counter Refresh period 2 refresh_count 1 HCLK Ex If refresh period is 15 6 us and HCLK is 60 MHz the refresh count is as follows Refresh count 211 1 60x15 6 1113 ELECTRONICS 5 17 MEMORY CONTROLLER 53 2410 BANKSIZE REGISTER BANKSIZE 0x48000028 Flexible bank size register 0x0 EN ARM core burst operation enable 0 Disable burst operation 1 Enable burst operation eee m wn SCKE_EN 5 SCKE enable control 0 SDRAM SCKE disable
386. nsfer or channel process e irq Used for general purpose interrupt handling Supervisor svc Protected mode for the operating system e Abort mode abt Entered after a data or instruction prefetch abort System sys A privileged user mode for the operating system e Undefined und Entered when an undefined instruction is executed Mode changes may be made under software control or may be brought about by external interrupts or exception processing Most application programs will execute in User mode The non user modes known as privileged modes are entered in order to service interrupts or exceptions or to access protected resources REGISTERS ARM920T has a total of 37 registers 31 general purpose 32 bit registers and six status registers but these cannot all be seen at once The processor state and operating mode dictate which registers are available to the programmer The ARM State Register Set In ARM state 16 general registers and one or two status registers are visible at any one time In privileged non User modes mode specific banked registers are switched in Figure 2 3 shows which registers are available in each mode the banked registers are marked with a shaded triangle The ARM state register set contains 16 directly accessible registers RO to R15 All of these except R15 are general purpose and may be used to hold either data or address values In addition to these there is a seventeenth register
387. nsfers are performed 1 DMA channel DMA REQ is turned off when a current value of transfer count becomes 0 The channel on off bit DMASKTRIGn 1 is set to 0 DREQ off to prevent unintended further start of new DMA operation Data size to be transferred 00 Byte 01 Half word 10 Word 11 reserved Initial transfer count or transfer beat Note that the actual number of bytes that are transferred is computed by the following equation DSZ x TSZ x TC Where DSZ TSZ 1 or 4 and TC represent data size DCONn 21 20 transfer size DCONn 28 and initial transfer count respectively This value will be loaded into CURR_SRC only if the CURR_SRC is 0 and the DMA ACK is 1 00000 nm ELECTRONICS 3C2410A DMA DMA STATUS DSTAT REGISTER oet ostat 0000054 n countregiter _ R DMA 2 countresier oss oen R countregsier STAT 21 20 Status of this DMA controller 00 Indicates that DMA controller is ready for another DMA request 01 Indicates that DMA controller is busy for transfers CURR_TC 19 0 Current value of transfer count 00000h p Note that transfer count is initially set to the value of 19 0 register and decreased by one at the end of every atomic transfer DMA CURRENT SOURCE DCSRC REGISTER DCSRCO 0x4B000018 R
388. nstruction encoding is shown in Figure 3 27 This class of instruction is used to communicate information directly between 920 and a coprocessor example of a coprocessor to 920 register transfer MRC instruction would be a FIX of a floating point value held in a coprocessor where the floating point number is converted into a 32 bit integer within the coprocessor and the result is then transferred to ARM920T register A FLOAT of a 32 bit value in ARM920T register into a floating point value within the coprocessor illustrates the use of ARM920T register to coprocessor transfer MCR An important use of this instruction is to communicate control information directly from the coprocessor into the ARM920T CPSR flags As an example the result of a comparison of two floating point values within a coprocessor can be moved to the CPSR to control the subsequent flow of execution 28 27 2423 212019 16 15 12 11 7 5 4 3 Jeep De FL 3 0 Coprocessor Operand Register 7 5 Coprocessor Information 11 8 Coprocessor Number 15 12 ARM Source Destination Register 19 16 Coprocessor Source Destination Register 20 Load Store Bit 0 Store to coprocessor 1 Load from coprocessor 21 Coprocessor Operation Mode 31 28 Condition Field Figure 3 27 Coprocessor Register Transfer Instructions THE COPROCESSOR FIELDS The field is used as for all coprocessor instructions to specify which co
389. nts of CRn and CRm and place the result in CRd ELECTRONICS 3 51 ARM INSTRUCTION SET S3C2410A INSTRUCTION CYCLE TIMES Coprocessor data operations take 1S bl incremental cycles to execute where b is the number of cycles spent in the coprocessor busy wait loop 5 and are defined as sequential S cycle and internal Assembler syntax p lt expression1 gt cd cn cm lt expression2 gt Two character condition mnemonic See Table 3 2 p The unique number of the required coprocessor lt expression1 gt Evaluated to a constant and placed in the CP field cd cn and cm Evaluate to the valid coprocessor register numbers CRd CRn and CRm respectively lt expression2 gt Where present is evaluated to a constant and placed in the CP field EXAMPLES CDP p1 10 c1 c2 c3 Request coproc 1 to do operation 10 on CR2 and and put the result CDPEQ 2 5 1 2 3 2 If Z flag is set request coproc 2 to do operation 5 type 2 on CR2 and and put the result in 3 52 ELECTRONICS 53 2410 ARM INSTRUCTION SET COPROCESSOR DATA TRANSFERS LDC STC The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 26 This class of instruction is used to load LDC or store STC a subset of a coprocessors s registers directly to memory 920 is responsib
390. of a data packet 2clocks after In case of last block interrupt period begins at last A but it does not end at B CMD53 case Read Wait Request Regardless of 1 bit or 4 bit mode Read Wait Request signal transmits to SDDAT2 pin in the condition below read multiple operation request signal transmission begins 2clocks after the end of data block Transmission ends when the user writes one to SDIDSTA 10 19 4 ELECTRONICS 53 2410 MMC SD SDIO HOST CONTROLLER SDI SPECIAL REGISTERS SDI Control SDICON Register Reset Value SDICON 0x5A000000 SDI control register 0 0 Byte Order Determine byte order type when you read write data from to ByteOrder SD host FIFO with word boundary 0 Type A 1 Receive SDIO Determine whether SD host receives SDIO Interrupt from the Interrupt from card card or not for SDIO RcvIOInt 0 ignore 1 receive 5010 Interrupt Read Wait Enable Determine read wait request signal generate when SD host RWaitEn waits the next block in multiple block read mode This bit needs to delay the next block to be transmitted from the card for SDIO 0 disable no generate 1 Read wait enable use SDIO FIFO Reset FRST 1 Reset FIFO value This bit is automatically cleared 0 normal mode 1 FIFO reset Clock Type CTYP Determines which clock type is used as SDCLK 0 Type 1 SD NOTE Byte Order Type Type A 0 7
391. of the EINTO 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered 9 22 ELECTRONICS 3 2410 PORTS a EINT15 30 28 Set the signaling method of the EINT15 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered 27 EINT14 26 24 Set the signaling method of the EINT14 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered s EINT13 22 20 Set the signaling method of the EINT13 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered s EINT12 18 16 Set the signaling method of the EINT12 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered s EINT11 14 12 Set the signaling method of the EINT11 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered m EINT10 10 8 Set the signaling method of the EINT10 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered EINT9 6 4 Set the signaling method of the EINT9 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered EINT8 2 0 Set the signaling method of the
392. off chip access is required the MMU outputs the appropriate physical address corresponding to the modified virtual address e f access is permitted and an off chip access is not required the cache services the access e f access is not permitted the MMU signals the CPU core to abort TLB misses it does not contain an entry for the virtual address the translation table walk hardware is invoked to retrieve the translation information from a translation table in physical memory Once retrieved the translation information is written into the TLB possibly overwriting an existing value The entry to be written is chosen by cycling sequentially through the TLB locations To enable use of TLB locking features the location to be written can be specified using CP15 register 10 TLB lockdown When the MMU is turned off as happens on reset no address mapping occurs and all regions are marked as non cacheable and non bufferable See About the caches and write buffer on page 4 1 3 2 ELECTRONICS ARM920T PROCESSOR MMU MMU PROGRAM ACCESSIBLE REGISTERS Table 3 1 shows system control coprocessor CP15 registers which are used in conjunction with page table descriptors stored in memory to determine the operation of the MMU Table 3 1 CP15 Register Functions Control register 1 Contains bits to enable the MMU M bit enable data address alignment checks A bit and to control the access protection scheme S bit and R bi
393. ogramming the base value to which the victim counter reloads For example if the bottom 3 entries 0 2 are to be locked down the base counter should be programmed to 3 An entry can also be preserved during an Invalidate All instruction This is done by ensuring the P bit is set when the entry is loaded into the TLB ELECTRONICS 2 21 PROGRAMMER S MODEL ARM920T PROCESSOR Load a single entry into TLB location 0 make it immune to Invalidate All and lock it down MCR to CP15 register 10 opcode_2 0x1 Base Value 0 Current Victim 0 P 1 MCR prefetch Assuming an TLB miss occurs then entry 0 will be loaded MCR to CP15 register 10 2 0 1 Base Value 1 Current Victim 1 P 0 Load a single entry into D TLB location 0 make it immune to Invalidate All and lock it down MCR to CP15 register 10 opcode_2 0x0 Base Value 0 Current Victim 0 P 1 Data load LDR LDM or store STR STM Assuming a D TLB miss occurs then entry 0 will be loaded MCR to CP15 register 10 2 0 0 Base Value 1 Current Victim 1 P 0 REGISTERS 11 12 amp 14 RESERVED Accessing reading or writing any of these registers will cause unpredictable behavior REGISTER 13 PROCESS ID Register 13 is the process identifier register The process identifier register is 0x0 on reset Reading from CP15 register 13 returns the value of the process identifier Writing CP15 register 13 updates the process identifie
394. on are identical to that of the equivalent ARM instruction EXAMPLES STMIA RO R3 R7 Store the contents of registers R3 R7 Starting at the address specified in RO incrementing the addresses for each word Write back the updated value of RO ELECTRONICS 4 33 THUMB INSTRUCTION SET S3C2410A FORMAT 16 CONDITIONAL BRANCH 15 14 13 11 8 7 0 1 12 om P sm 7 0 8 bit Signed Immediate 11 8 Condition Figure 4 17 Format 16 OPERATION The instructions in this group all perform a conditional Branch depending on the state of the CPSR condition codes The branch offset must take account of the prefetch operation which causes the PC to be 1 word 4 bytes ahead of the current instruction The THUMB assembler syntax is shown in the following table Table 4 17 The Conditional Branch Instructions THUMB assembler ARM equiva Branch if Z clear not equal Branch if C set unsigned higher or same Branch if C clear unsigned lower Branch if N clear positive or zero Branch if V clear no overflow Branch if C set and Z clear unsigned higher 4 34 ELECTRONICS 53 2410 THUMB INSTRUCTION SET Table 4 17 The Conditional Branch Instructions Continued 1001 BLS label BLS label Branch if C clear or Z set unsigned lower or same 1010 BGE label BGE label Branch if N set and V set or N clear and V clear greater or equal 1011 BLT label BLT label Branch if N set and V
395. on data bus inputs 15 through to 8 if it is a word address plus one byte and so on The selected byte is placed in the bottom 8 bit of the destination register and the remaining bits of the register are filled with the sign bit bit 7 of the byte Please see Figure 2 2 A halfword load LDRSH or LDRH expects data on data bus inputs 15 through to 0 if the supplied address is on a word boundary and on data bus inputs 31 through to 16 if it is a halfword boundary A 1 1 The supplied address should always be on a halfword boundary If bit O of the supplied address is HIGH then the ARM920T will load an unpredictable value The selected halfword is placed in the bottom 16 bits of the destination register For unsigned half words LDRH the top 16 bits of the register are filled with zeros and for signed half words LDRSH the top 16 bits are filled with the sign bit bit 15 of the halfword A halfword store STRH repeats the bottom 16 bits of the source register twice across the data bus outputs 31 through to 0 The external memory system should activate the appropriate halfword subsystem to store the data Note that the address must be halfword aligned if bit O of the address is HIGH this will cause unpredictable behaviour 3 36 ELECTRONICS 53 2410 ARM INSTRUCTION SET Big Endian Configuration A signed byte load LDRSB expects data on data bus inputs 31 through to 24 if the supplied address is on a word boundary on data bus inputs 23 thr
396. onding bits of SRCPND register are set to 1 and at the same time only one bit of the INTPND register is set to 1 automatically after arbitration procedure If interrupts are masked the corresponding bits of the SRCPND register are set to 1 This does not cause the bit of INTPND register changed When a pending bit of the INTPND register is set the interrupt service routine starts whenever the I flag or F flag is cleared to 0 The SRCPND and INTPND registers can be read and written so the service routine must clear the pending condition by writing a 1 to the corresponding bit in the SRCPND register first and then clear the pending condition in the INTPND registers by using the same method Interrupt Mask Register This register indicates that an interrupt has been disabled if the corresponding mask bit is set to 1 If an interrupt mask bit of INTMSK is 0 the interrupt will be serviced normally If the corresponding mask bit is 1 and the interrupt is generated the source pending bit will be set 14 2 ELECTRONICS 3C2410A INTERRUPT CONTROLLER INTERRUPT SOURCES The interrupt controller supports 56 interrupt sources as shown in the table below ELECTRONICS 14 3 INTERRUPT CONTROLLER S3C2410A INTERRUPT PRIORITY GENERATING BLOCK The priority logic for 32 interrupt requests is composed of seven rotation based arbiters six first level arbiters and one second level arbiter as shown in Figure 14 2 below 4 REQ1 EINTO lt REQ
397. onfigures the signaling method among the low level trigger high level trigger falling edge trigger rising edge trigger and both edge trigger for the external interrupt request The 8 external interrupt pin has a digital filter refer to EINTFLTn on page 9 25 Only 16 EINT pins EINT 15 0 are used for wakeup sources POWER OFF MODE AND I O PORTS All GPIO register values are preserved in Power OFF mode Refer to the Power OFF mode in the chapter Clock amp Power Management The EINTMASK can t prohibit the wake up from Power OFF mode But If ENTMASK is masking one of EINT 15 4 the wake up can be done but the 4 7 bit and EINT8 23 bit of the SRCPND will not set to 1 just after the wake up ELECTRONICS 9 7 PORTS 53 2410 PORT CONTROL REGISTER PORT A CONTROL REGISTERS GPACON GPADAT Reserved 0666000008 Reserved J ndeined Reserved 06600000 Reseed Bk GPA22 22 0 Output 1 GPA21 21 0 Output 1 nRSTOUT nRSTOUT nRESET amp nWDTRST 8 SW RESET MISCCR 16 11 11 0 Output 1 ADDR26 GPA10 10 0 Output 1 ADDR25 GP ___ ____ 1540080 O _ eras M Output 1 ADURIB O _ GPADAT GPA 22 0 22 0 When the port is configured as output port the pin state is the same as the that of the corresponding bit When the port is configured as functional pin undefined value will be re
398. oo 1 EN ADD Hd Hs ADD Hd Hd Hs Add two registers in the range 8 15 01 CMP Rd Hs CMP Rd Hs Compare a register in the range 0 7 with a register in the range 8 15 Set the condition code flags on the result CMP Rs CMP Hd Rs Compare a register in the range 8 15 ELECTRONICS 4 13 with a register in the range 0 7 Set the condition code flags on the result THUMB INSTRUCTION SET 53 2410 Table 4 6 Summary of Format 5 Instructions Continued 01 1 1 CMP Hd Hs CMP Hd Hs Compare two registers in the range 8 15 Set the condition code flags on the result 10 1 Hs Hs Move a value from a register in the range 8 15 to a register in the range 0 7 10 1 MOV Hd Rs MOV Hd Rs Move a value from a register in the range 0 7 to a register in the range 8 15 10 MOV Hd Hs MOV Hd Hs Move a value between two registers in the range 8 15 BX Rs BX Rs Perform branch plus optional state change to address in a register in the range 0 7 BX Hs BX Hs Perform branch plus optional state change to address in a register in the range 8 15 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 6 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction THE BX INSTRUCTION BX performs a Branch to a routine whose start address is specified in a Lo or Hi register Bit 0 of the address d
399. or the flicker free LCD system application the user have to consider the LCD refresh bus bandwidth determined by the LCD display size bit per pixel bpp frame rate memory bus width memory type and so on LCD Data Rate Byte s bpp x Horizontal display size x Vertical display size x Frame rate 8 LCD DMA Burst Count Times s LCD Data Rate Byte s 16 Byte LCD DMA using 4words 16Byte burst Pdma means LCD DMA access period In other words the value of Pdma indicates the period of four beat burst 4 words burst for video data fetch So Pdma depends on memory type and memory setting Eventually LCD System Load is determined by LCD DMA Burst Count and Pdma LCD System Load LCD DMA Burst Count x Pdma Example 3 640 x 480 8bpp 60 frame sec 16 bit data bus width SDRAM 2 Trcd 2HCLK CL 2HCLK and HCLK frequency is 60 MHz LCD Data Rate 8 x 640 x 480 x 60 8 18 432Mbyte s LCD DMA Burst Count 18 432 16 1 152M s Trp Trcd CL 2 x 4 1 x 1 60 MHz 0 250ms LCD System Load 1 152 x 250 0 288 System Bus Occupation Rate 0 288 1 x 100 28 8 ELECTRONICS 15 41 LCD CONTROLLER S3C2410A Register Setting Guide TFT LCD The CLKVAL register value determines the frequency of VCLK and frame rate Frame Rate 1 VSPW 1 VBPD 1 LIINEVAL 1 1 x HSPW 1 HBPD 1 HFPD 1 HOZVAL 1 x 2 x CLKVAL 1 HCLK For applications the
400. osely related to the field of WLH 1 0 VLINE pulse width WDLY 1 0 the delay width of after VLINE pulse HOZVAL LINEBLANK and LINEVAL in the LCDCON1 2 3 4 registers as well as VCLK and HCLK Most LCD drivers need their own adequate frame rate The frame rate is calculated as follows frame rate Hz 1 1 VCLK x HOZVAL 1 1 HCLK x A B LINEBLANK x 8 x LINEVAL 1 A B 201 15 4 ELECTRONK S 3C2410A LCD CONTROLLER Table 15 1 Relation Between VCLK and CLKVAL STN HCLK 60 MHz CLKVAL 60 MHz X VCLK 1023 60 2 2046 29 3 kHz VIDEO OPERATION The S3C2410A LCD controller supports 8 bit color mode 256 color mode 12 bit color mode 4096 color mode 4 level gray scale mode 16 level gray scale mode as well as the monochrome mode For the gray or color mode it is required to implement the shades of gray level or color according to time based dithering algorithm and Frame Rate Control FRC method The selection can be made following a programmable lockup table which will be explained later The monochrome mode bypasses these modules FRC and lookup table and basically serializes the data in FIFOH and FIFOL if a dual scan display type is used into 4 bit or 8 bit if a 4 bit dual scan or 8 bit single scan display type is used streams by shifting the video data to the LCD driver The following sections describe the operation on the gray and color mode in terms of the lookup table and FRC
401. ough to 16 if it is a word address plus one byte and so on The selected byte is placed in the bottom 8 bit of the destination register and the remaining bits of the register are filled with the sign bit bit 7 of the byte Please see Figure 2 1 A halfword load LDRSH or LDRH expects data on data bus inputs 31 through to 16 if the supplied address is ona word boundary and on data bus inputs 15 through to 0 if it is a halfword boundary A 1 1 The supplied address should always be on a halfword boundary If bit 0 of the supplied address is HIGH then the ARM920T will load an unpredictable value The selected halfword is placed in the bottom 16 bits of the destination register For unsigned half words LDRH the top 16 bits of the register are filled with zeros and for signed half words LDRSH the top 16 bits are filled with the sign bit bit 15 of the halfword A halfword store STRH repeats the bottom 16 bits of the source register twice across the data bus outputs 31 through to 0 The external memory system should activate the appropriate halfword subsystem to store the data Note that the address must halfword aligned if bit 0 of the address is HIGH this will cause unpredictable behaviour USE OF R15 Write back should not be specified if R15 is specified as the base register Rn When using R15 as the base register you must remember it contains an address 8 bytes on from the address of the current instruction R15 should not be spec
402. p 1 Start for Timer 1 NOTE The bits have to be cleared at next writing ELECTRONICS Initial state 10 13 PWM TIMER 3 2410 TIMER CONTROL TCON REGISTER Continued Reserved Dead zone enable 4 Determine the dead zone operation 0 Disable 1 Enable Timer 0 auto reload on off 3 Determine auto reload on off for Timer 0 0 One shot 1 Interval mode auto reload Timer 0 output inverter on off Determine the output inverter on off for Timer 0 0 Inverter off 1 Inverter on for TOUTO Timer 0 manual update note 1 Determine the manual update for Timer 0 0 operation 1 Update TCNTBO TCMPBO Timer 0 start stop Determine start stop for Timer 0 0 Stop 1 Start for Timer 0 NOTE The bit have to be cleared at next writing 10 14 ELECTRONICS 53 2410 PWM TIMER TIMER 0 COUNT BUFFER REGISTER amp COMPARE BUFFER REGISTER TCNTBO 0x5100000C R W Timer 0 count buffer register 0x00000000 TCMPBO 0x51000010 Timer 0 compare buffer register 0x00000000 15 0 Set compare buffer value for Timer 0 0x00000000 15 0 Set count buffer value for Timer 0 0x00000000 TIMER 0 COUNT OBSERVATION REGISTER TCNTOO TCNTOO 0 51000014 R Timer 0 count observation register 0x00000000 Timer 0 observation register 15 0 Set count observation value for Timer 0 0x00000000 TCMPBO Timer 0 compare buffer register TCNTBO Timer 0 count buffer registe
403. pectively CPSR CPSR all SPSR or SPSR all CPSR and CPSR are synonyms as are SPSR Where this is used the assembler will attempt to generate a shifted immediate 8 bit field to match the expression If this is impossible it will give an error Key cond Two character condition mnemonic See Table 3 2 Rd and Rm Expressions evaluating to a register number other than R15 lt psr gt and SPSR all lt psrf gt CPSR_flg or SPSR_flg lt expression gt EXAMPLES In User mode the instructions behave as follows MSR CPSR all Rm MSR CPSR flg Rm MSR CPSR_flg 0xA0000000 MRS Rd CPSR In privileged modes the instructions behave as follows MSR CPSR all Rm MSR CPSR flg Rm MSR CPSR_flg 0x50000000 MSR SPSR all Rm MSR SPSR flg Rm MSR SPSR_flg 0xC0000000 MRS Rd SPSR ELECTRONICS CPSR 31 28 lt Rm 31 28 CPSR 31 28 lt Rm 31 28 CPSR 31 28 lt set N C clear Z V Rd 31 0 lt CPSR 31 0 CPSR 31 0 Rm 31 0 CPSR 31 28 Rm 31 28 CPSR 31 28 lt 0x5 set Z V clear N C SPSR_ lt mode gt 31 0 lt Rm 31 0 SPSR_ lt mode gt 31 28 lt Rm 31 28 SPSR_ lt mode gt 31 28 lt OxC set N Z clear C V 31 0 lt SPSR_ lt mode gt 31 0 3 21 ARM INSTRUCTION SET 53 2410 MULTIPLY AND MULTIPLY ACCUMULATE MUL MLA The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown
404. permission field is given in Table 3 5 on page 3 19 The following instructions can be used to access the domain access control register MRC p15 0 Rd c3 c0 0 read domain 15 0 access permissions MCR p15 0 Rd c3 0 write domain 15 0 access permissions ELECTRONICS 2 13 PROGRAMMER S MODEL ARM920T PROCESSOR REGISTER 4 RESERVED Accessing reading or writing this register will cause unpredictable behavior REGISTER 5 FAULT STATUS REGISTERS Register 5 is the fault status register FSR The FSR contains the source of the last data fault indicating the domain and type of access being attempted when the data abort occurred Table 2 14 Fault Status Register UNP when read SBZ for write ____8 read SBZ for write Domain being accessed when fault occurred 015 00 The fault type encoding is shown in Fault address and fault status registers on page 3 18 The data FSR is defined in ARM architecture v4T Additionally a pipelined prefetch FSR is available for debug purposes only The pipeline matches that of the ARM9TDMI The following instructions can be used to access the data and prefetch FSR MRC p15 0 Rd c5 c0 0 read data FSR value MCR p15 0 Rd c5 c0 0 write data FSR value MRC p15 0 c5 1 read prefetch FSR value MCR p15 0 c5 0 1 prefetch FSR value The ability to write to the FSR is useful for a debugger to restore the value of the FSR The regist
405. processor is being called upon The CP Opc CRn CP and CRm fields are used only by the coprocessor and the interpretation presented here is derived from convention only Other interpretations are allowed where the coprocessor functionality is incompatible with this one The conventional interpretation is that the CP Opc and CP fields specify the operation the coprocessor is required to perform CRn is the coprocessor register which is the source or destination of the transferred information and CRm is a second coprocessor register which may be involved in some way which depends on the particular operation specified 3 56 ELECTRONICS 53 2410 ARM INSTRUCTION SET TRANSFERS TO R15 When a coprocessor register transfer to ARM920T has R15 as the destination bits 31 30 29 and 28 of the transferred word are copied into the N Z C and V flags respectively The other bits of the transferred word are ignored and the PC and other CPSR bits are unaffected by the transfer TRANSFERS FROM R15 A coprocessor register transfer from ARM920T with R15 as the source register will store the PC 12 INSTRUCTION CYCLE TIMES MRC instructions take 15 6 1 1 incremental cycles to execute where S and C are defined as sequential S cycle internal and coprocessor register transfer C cycle respectively MCR instructions take 1S bl 1C incremental cycles to execute where b is the number of cycles spent in the coprocessor busy wait
406. pter 22 SPI Interface e MC FO ALUN CS o terere GR ere AR Coi P eret A T Block Diagram u ede cos ck eee itai i Dat HORE D ee tees SPI Operation iet tetas fr Gg ete D pa direi tien etre fr Ad SPBLSpeclal Registers uu 3 pnr t eae et obra Eo Pad oda Ir Re dep p Feng orte E Erat SPI Gontrol Register perdi o SPI Status Beglster uini petere dO aede p e Me E pin te SPI Pin Control Register xvi 3C2410A MICROPROCESSOR Table of Contents Continued Chapter 23 BUS Priorities Overview EDU 23 1 Bus Priority Map rp toc ue toes gana us saya 23 1 Chapter 24 Electrical Data Absolute Maximum Ratings et titt ERE nee e eite LP ee Pe ge pe be 24 1 Recommended Operating 24 1 D G Electrical GharacteristiCs iren ee tette ree tn ethane 24 2 Electrical Gharacteristi6s aee n ebbe nos ette cei reti i nad 24 4 Chapter 25 Mechanical Data Package Dimensions eingetreten ede eee re e deuda ge a pee eua 25 1 3C2410A MICROPROCESSOR xvii Table of Contents Continued Appendix 1 ARM920T Introduction the 1 1 Processor Functional Block 1 2 Appendix 2 Programmer s Model About rhe Progr
407. put and output respectively The I O state OnRESET shows the pin status in the nRESET duration below n 4FCLK nRESET nRESET r wT depre 1 18 ELECTRONICS 3 2410 PRODUCT OVERVIEW 7 The table below shows I O types and the descriptions Type Descriptions d1i vdd1ih s3i vss3i 1 8V 2 0V Vpp Vss for internal logic dic vddiih core s3i vss3i 1 8V 2 0V Vpp Vss for internal logic without input driver d3o vdd3op s3o vss3op 3 3V Vpp Vss for external logic usps abb m26 phsoscm26 Oscillator cell with enable and feedback resistor te phtbsu100ct6sm Bi directional pad 5V tolerant LVCMOS Schmitt trigger 100Kohm pull up resistor with control tri state lo t8 phbsu100ct8sm Bi directional pad LVCMOS Schmitt trigger 100Kohm pull up resistor with control tri state lo 8mA t12 phbsu100ct12sm Bi directional pad LVCMOS Schmitt trigger 100Kohm pull up resistor with control tri state lo 12 d8 phbsud8sm Bi directional pad LVCMOS Schmitt trigger control open drain lo 8mA ELECTRONICS 1 19 PRODUCT OVERVIEW S3C2410A SIGNAL DESCRIPTIONS Table 1 3 S3C2410A Signal Descriptions Signal vo Deseriptions O Bus Controller OM 1 0 OM 1 0 sets S3C2410A in the TEST mode which is used only at fabrication Also it deter
408. put port data written in this register can be sent to the corresponding pin When the port is configured as functional pin undefined value will be read Br BesHpim GPC 15 0 15 0 0 The pull up function attached to to the corresponding port pin is enabled 1 The pull up function is disabled ELECTRONICS 9 11 PORTS 53 2410 PORT D CONTROL REGISTERS GPDCON GPDDAT and GPDUP Pull up disable register for port D Reserved Rese Undefned GPOCON s _ Den SSS GPD15 31 30 _ 00 Input 10 VD23 GPD14 29 28 00 Input 10 VD22 GPD13 27 26 00 Input 10 VD21 GPD12 25 24 00 Input 10 VD20 GPD11 23 22 00 Input 10 VD19 GPD10 21 20 00 Input 10 VD18 GPD9 19 18 00 Input 10 VD17 GPD8 17 16 00 Input 10 VD16 GPD7 15 14 00 Input 10 15 13 12 00 Input 10 VD14 11 10 00 Input 10 VD13 00 Input 10 VD12 7 6 00 Input 10 VD11 5 4 00 Input 10 VD10 3 2 00 Input 10 VD9 1 0 00 Input 10 VD8 01 Output 11 550 01 Output 11 2 nSS1 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 R
409. quate frame rate The frame rate is calculated as follows Frame Rate 1 VSPW 1 VBPD 1 LIINEVAL 1 1 x HSPW 1 HBPD 1 1 HOZVAL 1 x 2 x CLKVAL 1 HCLK Table 15 3 Relation Between VCLK and CLKVAL TFT HCLK 60 MHz CLKVAL 60 MHz X VCLK 1023 60 MHz 2048 30 0 kHz VIDEO OPERATION The TFT LCD controller within the 53 2410 supports 1 2 4 or 8 bpp bit per pixel palettized color displays and 16 or 24 bpp non palettized true color displays 256 Color Palette The S3C2410A can support the 256 color palette for various selection of color mapping providing flexible operation for users ELECTRONICS 15 15 LCD CONTROLLER S3C2410A MEMORY DATA FORMAT TFT This section includes some examples of each display mode 24BPP Display BSWP 0 HWSWP 0 BPP24BL 0 BSWP 0 HWSWP 0 BPP24BL 1 we ww Dume Dum EIL es re Pa Pa es LCD Panel VD Pin Descriptions at 24BPP VD 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 6 5 4 3 2 RD 1716 5 1 7 6 514 312 1 0 15 16 ELECTRONICS 53 2410 LCD CONTROLLER 16BPP Display BSWP 0 HWSWP 0 LCD Panel VD Pin Connections at 16BPP 5 6 5 __ 23
410. r 2000 Note 1900 is not leap year while 2000 is leap year Therefore two digits of 00 in S3C2410A denote 2000 not 1900 17 2 ELECTRONICS 53 2410 REAL TIME CLOCK RTC READ WRITE REGISTERS Bit 0 of the RTCCON register must be set high in order to write the BCD register in RTC block To display the second minute hour date month and year the CPU should read the data in BCDSEC BCDMIN BCDHOUR BCDDAY BCDDATE BCDMON and BCDYEAR registers respectively in the RTC block However a one second deviation may exist because multiple registers are read For example when the user reads the registers from BCDYEAR to BCDMIN the result is assumed to be 2059 Year 12 Month 31 Date 23 Hour and 59 Minute When the user read the BCDSEC register and the value ranges from 1 to 59 Second there is no problem but if the value is 0 sec the year month date hour and minute may be changed to 2060 Year 1 Month 1 Date 0 Hour and 0 Minute because of the one second deviation that was mentioned In this case the user should re read from BCDYEAR to BCDSEC if BCDSEC is zero BACKUP BATTERY OPERATION The RTC logic can be driven by the backup battery which supplies the power through the RTCVDD pin into the RTC block even if the system power is off When the system is off the interfaces of the CPU and RTC logic should be blocked and the backup battery only drives the oscillation circuit and the BCD counters to minimize powe
411. r ELECTRONICS 10 15 PWM TIMER 3 2410 TIMER 1 COUNT BUFFER REGISTER amp COMPARE BUFFER REGISTER TCNTB1 TCMPB1 TCNTB1 0x51000018 R W Timer 1 count buffer register 0x00000000 TCMPB1 0x5100001C Timer 1 compare buffer register 0x00000000 Timer 1 compare buffer register 15 0 Set compare buffer value for Timer 1 0x00000000 Timer 1 count buffer register 15 0 Set count buffer value for Timer 1 0x00000000 TIMER 1 COUNT OBSERVATION REGISTER TCNTO1 TCNTO1 0x51000020 Timer 1 count observation register 0x00000000 Timer 1 observation register 15 0 Set count observation value for Timer 1 0x00000000 10 16 ELECTRONICS 53 2410 PWM TIMER TIMER 2 COUNT BUFFER REGISTER amp COMPARE BUFFER REGISTER TCNTB2 TCMPB2 TCNTB2 0x51000024 R W Timer 2 count buffer register 0x00000000 TCMPB2 0x51000028 Timer 2 compare buffer register 0x00000000 15 0 Set compare buffer value for Timer 2 0x00000000 15 0 Set count buffer value for Timer 2 0x00000000 TIMER 2 COUNT OBSERVATION REGISTER TCNTO2 TCNTO2 0x5100002C Timer 2 count observation register 0x00000000 Timer 2 observation register 15 0 Set count observation value for Timer 2 0x00000000 TCMPB2 Timer 2 compare buffer register TCNTB2 Timer 2 count buffer register ELECTRONICS 10 17 PWM TIMER 3 2410 TIMER 3 COUNT BUFFER REGISTER amp COMPARE BUFFER REGISTER TCNTB3 TCMPB3 TCNTB3 0x51000030 R W Timer 3 count buffer register 0x
412. r At the next timer tick the TCNTn is reloaded with the temporary register value TCNTBn In Interrupt Service Routine ISR the TCNTBn and the TCMPBn are set to 80 204 60 and 60 respectively for the next duration When the TCNTn has the same value as the TCMPn the logic level of TOUTn is changed from low to high When the TCNTn reaches 0 the TCNTn is reloaded automatically with the TCNTBn triggering an interrupt request In Interrupt Service Routine ISR auto reload and interrupt request are disabled to stop the timer When the value of the TCNTn is same as the TCMPn the logic level of the TOUTn is changed from low to high Even when the TCNTn reaches 0 the TCNTn is not any more reloaded and the timer is stopped because auto reload has been disabled No more interrupt requests are generated ELECTRONICS 53 2410 PWM TIMER PULSE WIDTH MODULATION PWM Write Write Write 60 40 TCMPBn 30 Write Write Write TCMPBn 50 TCMPBN 30 TCMPBn Next PWM Value Figure 10 5 Example of PWM PWM function can be implemented by using the TCMPBn PWM frequency is determined by TCNTBn Figure 10 5 shows a PWM value determined by TCMPBn For a higher PWM value decrease the TCMPBn value For a lower PWM value increase the TCMPBn value If an output inverter is enabled the increment decrement may be reversed The double buffering function allows the TCMPBn for the next PWM
413. r dissipation ALARM FUNCTION The RTC generates an alarm signal at a specified time in the power off mode or normal operation mode In normal operation mode the alarm interrupt ALMINT is activated In the power off mode the power management wakeup PMWKUP signal is activated as well as the ALMINT The RTC alarm register RTCALM determines the alarm enable disable status and the condition of the alarm time setting TICK TIME INTERRUPT The RTC tick time is used for interrupt request The TICNT register has an interrupt enable bit and the count value for the interrupt The count value reaches 0 when the tick time interrupt occurs Then the period of interrupt is as follows Period n 1 128 second n Tick time count value 1 127 This RTC time tick may be used for real time operating system RTOS kernel time tick If time tick is generated by the RTC time tick the time related function of RTOS will always synchronized in real time ROUND RESET FUNCTION The round reset function can be performed by the RTC round reset register RTCRST The round boundary 30 40 or 50 sec of the second carry generation can be selected and the second value is rounded to zero in the round reset For example when the current time is 23 37 47 and the round boundary is selected to 40 sec the round reset changes the current time to 23 38 00 NOTE All RTC registers have to be accessed for each byte unit using the STRB and LDRB instructions o
414. r char type pointer ELECTRONICS 17 3 REAL TIME CLOCK RTC S3C2410A 32 768KHZ X TAL CONNECTION EXAMPLE The Figure 17 2 shows a circuit of the RTC unit oscillation at 32 768 kHz 15 22pF 32768Hz Figure 17 2 Main Oscillator Circuit Example 17 4 ELECTRONICS 3C2410A REAL TIME CLOCK RTC REAL TIME CLOCK SPECIAL REGISTERS REAL TIME CLOCK CONTROL RTCCON REGISTER The RTCCON register consists of 4 bits such as the RTCEN which controls the read write enable of the BCD registers CLKSEL CNTSEL and CLKRST for testing RTCEN bit can control all interfaces between the CPU and the RTC so it should be set to 1 in an RTC control routine to enable data read write after a system reset Also before power off the RTCEN bit should be cleared to 0 to prevent inadvertent writing into RTC registers RTCCON 0x57000040 L R W RTC control register 0x0 0x57000043 B by byte CLKRST 3 RTC clock count reset 0 reset 1 Reset CNTSEL BCD count select 0 Merge BCD counters 1 Reserved Separate BCD counters CLKSEL 1 BCD clock select 0 XTAL 1 215 divided clock 1 Reserved XTAL clock only for test RTCEN RTC control enable 0 Disable 1 Enable NOTE Only BCD time count and read operation can be performed NOTES 1 All RTC registers have to be accessed for each byte unit using STRB and LDRB instructions or char type pointer 2 0 Little endian B Big endian TICK TIME COUNT TICNT
415. r to the value in bits 31 25 Bits 24 0 should be zero Register 13 bit assignments are shown in Figure 2 7 31 25 24 23 22 21 20 19 18 17 16 15 14 131211109 8 7 6 5 4 3 2 1 L j SBZ Figure 2 7 Register 13 Register 13 can be accessed using the following instructions MRC p15 0 Rd c13 c0 0 read process identifier MCR p15 0 c13 0 write process identifier 2 22 ELECTRONICS ARM920T PROCESSOR PROGRAMMER S MODEL Using the process Identifier Addresses issued by the ARM9TDMI core in the range 0 to 32MB are translated by CP15 register 13 the register Address A becomes A ProclID x 32MB It is this translated address that is seen by both the Caches and MMU Addresses above 32MB undergo no translation This is shown in Figure 2 8 on page 2 23 The ProclD is a seven bit field enabling 64 x 32MB processes to be mapped NOTE If ProclD is zero as it is on reset then there is a flat mapping between the ARM9TDMI and the Caches and MMU Virtual address VA Modified virtual address MVA issued by ARM9TDMI input to caches and MMU Figure 2 8 Address Mapping Using CP15 Register 13 ELECTRONICS 2 23 PROGRAMMER S MODEL ARM920T PROCESSOR Changing the performing a fast context switch A fast context switch is done by writing to CP15 register 13 The contents of the caches and TLBs do not have to be flushed after a fast context switch because they still hold
416. ral bus while the destination is in the system bus and 4 both source and destination are in the peripheral bus The main advantage of the DMA is that it can transfer the data without CPU intervention The operation of DMA can be initiated by software or requests from internal peripherals or external request pins ELECTRONICS 8 1 DMA S3C2410A DMA REQUEST SOURCES Each channel of the DMA controller can select one of DMA request source among four DMA sources if HW DMA request mode is selected by DCON register Note that if S W request mode is selected this DMA request sources have no meaning at all Table 8 1 shows four DMA sources for each channel Table 8 1 DMA Request Sources for Each Channel nXDREQ0 UARTO USB device 1 nXDREQ1 UART1 2550 SPIO USB device EP2 1258800 125801 SDI USB device EP3 UART2 SDI SPI USB device EP4 Here nXDREQO and nXDREQ1 represent two external sources External Devices and 125500 and 12550 represent IIS transmitting and receiving respectively DMA OPERATION DMA uses three state FSM finite state machine for its operation which is described in the three following steps State 1 As an initial state the DMA waits for a DMA request If it comes it goes to state 2 At this state DMA ACK and INT REQ are 0 State 2 In this state DMA ACK becomes 1 and the counter CURR TO is loaded from DCON 19 0 register Note that the DMA ACK remains 1 until it is cleared later State 3 In this s
417. rand are all zero or all one 3 If bits 32 24 of the multiplier operand are all zero or all one 4 In all other cases ASSEMBLER SYNTAX MUL cond S Rd Rm Rs MLA cond S Rd Rm Rs Rn Two character condition mnemonic See Table 3 2 S Set condition codes if S present Rd Rm Rs and Rn Expressions evaluating to a register number other than R15 EXAMPLES MUL R1 R2 R3 R1 R2 R3 MLAEQS R1 R2 R3 R4 Conditionally R1 R2 R3 R4 Setting condition codes 3 24 ELECTRONICS 3C2410A ARM INSTRUCTION SET MULTIPLY LONG AND MULTIPLY ACCUMULATE LONG MULL MLAL The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 13 The multiply long instructions perform integer multiplication on two 32 bit operands and produce 64 bit results Signed and unsigned multiplication each with optional accumulate give rise to four variations 31 28 27 23 22 21 20 19 16 15 12 11 Lus 43 Ts Insel 11 8 3 0 Operand Registers 19 16 15 12 Source Destination Registers 20 Set Condition Code 0 Do not alter condition codes 1 Set condition codes 21 Accumulate 0 Multiply only 1 Multiply and accumulate 22 Unsigned 0 Unsigned 1 Signed 31 28 Condition Field Figure 3 13 Multiply Long Instructions The multiply forms UMULL and SMULL take two 32 bit numbers and multiply them to produce a 64 bit
418. rates the complete section translation sequence Note that access permissions contained in the level one descriptor must be checked before the physical address is generated 20 19 Translation table base 1413 Translation base 12 18 Translation base Table index Section level one descriptor 20 19 1211109 8 Dellsee 01501010 Physical address 20 19 Figure 3 5 Section Translation 3 10 ELECTRONICS ARM920T PROCESSOR MMU LEVEL TWO DESCRIPTOR If the level one fetch returns either a coarse page table descriptor or a fine page table descriptor this provides the base address of the page table to be used The page table is then accessed and a level two descriptor is returned This defines either a tiny a small or a large page descriptor a tiny page descriptor provides the base address of a 1KB block of memory asmall page descriptor provides to the base address of a 4KB block of memory alarge page descriptor provides the base address of a 64KB block of memory Coarse page tables have 256 entries each entry describing 4KB These entries can provide base addresses for either small or large pages Large page descriptors must be repeated in 16 consecutive entries Fine page tables have 1024 entries each entry describing 1KB These entries can provide base addresses for either tiny small or large pages Small page descriptors must be repeated in 4 consecutive entries and large page descriptors mus
419. ration of the read and write operations to signal to the external memory manager that they are locked together and should be allowed to complete without interruption This is important in multi processor systems where the swap instruction is the only indivisible instruction which may be used to implement semaphores control of the memory must not be removed from a processor while it is performing a locked operation BYTES AND WORDS This instruction class may be used to swap a byte B 1 or a word B 0 between an ARM920T register and memory The SWP instruction is implemented as a LDR followed by a STR and the action of these is as described in the section on single data transfers In particular the description of Big and Little Endian configuration applies to the SWP instruction ELECTRONICS 3 47 ARM INSTRUCTION SET S3C2410A USE OF R15 Do not use R15 as an operand Rd Rn or Rs in a SWP instruction DATA ABORTS If the address used for the swap is unacceptable to a memory management system the memory manager can flag the problem by driving ABORT HIGH This can happen on either the read or the write cycle or both and in either case the Data Abort trap will be taken It is up to the system software to resolve the cause of the problem then the instruction can be restarted and the original program continued INSTRUCTION CYCLE TIMES Swap instructions take 15 2N 11 incremental cycles to execute where S N and are defined as s
420. rce 0 PC 1 SP Figure 4 13 Format 12 OPERATION These instructions calculate an address by adding an 10 bit constant to either the PC or the SP and load the resulting address into a register The THUMB assembler syntax is shown in the following table Table 4 13 Load Address ADD Rd PC ADD Rd R15 lmm Add lmm to the current value of the program counter PC and load the result into Rd 1 ADD Ra SP lmm ADD R13 lmm Add to the current value of the stack pointer SP and load the result into Rd NOTE The value specified by Imm is a full 10 bit value but this must be word aligned ie with bits 1 0 set to 0 since the assembler places lmm gt gt 2 in field Word 8 Where the PC is used as the source register SP 0 bit 1 of the PC is always read as 0 The value of the PC will be 4 bytes greater than the address of the instruction before bit 1 is forced to 0 The CPSR condition codes are unaffected by these instructions 4 28 ELECTRONICS 3C2410A THUMB INSTRUCTION SET INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 13 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES ADD R2 PC 572 R2 572 but don t set the condition codes bit 1 of PC is forced to zero Note that the THUMB opcode will contain 143 as the Word8 value ADD R6 SP 212
421. rd presented to the data bus is not affected if the address is not word aligned That is bit 31 of the register being stored always appears on data bus output 31 3 30 ELECTRONICS 3C2410A ARM INSTRUCTION SET USE OF R15 Write back must not be specified if R15 is specified as the base register Rn When using R15 as the base register you must remember it contains an address 8 bytes on from the address of the current instruction R15 must not be specified as the register offset Rm When 15 is the source register Rd of a register store STR instruction the stored value will be address of the instruction plus 12 Restriction on the use of base register When configured for late aborts the following example code is difficult to unwind as the base register Rn gets updated before the abort handler starts Sometimes it may be impossible to calculate the initial value After an abort the following example code is difficult to unwind as the base register Rn gets updated before the abort handler starts Sometimes it may be impossible to calculate the initial value EXAMPLE LDR RO R1 R1 Therefore a post indexed LDR or STR where Rm is the same register as Rn should not be used DATA ABORTS A transfer to or from a legal address may cause problems for a memory management system For instance in a system which uses virtual memory the required data may be absent from main memory The memory manager can signal a problem by takin
422. reen size in 256 color mode 4096x1024 2048x2048 1024x4096 and others TFT Thin Film Transistor Color Displays Feature e Supports 1 2 4 or 8 bpp bit per pixel palette color displays for color TFT e Supports 16 bpp non palette true color displays for color TFT e Supports maximum 16M color TFT at 24 bpp mode e Supports multiple screen size e Typical actual screen size 640x480 320x240 160x160 and others e Maximum virtual screen size is 4Mbytes e Maximum virtual screen size in 64K color mode 2048x1024 and others PRODUCT OVERVIEW FEATURES Continued Watchdog Timer e 16 bit Watchdog Timer e Interrupt request or system reset at time out IIC Bus Interface 1 ch Multi Master IIC Bus e Serial 8 bit oriented and bi directional data transfers can be made at up to 100 Kbit s in Standard mode or up to 400 Kbit s in Fast mode IIS Bus Interface e 1 ch IIS bus for audio interface with DMA based operation e Serial 8 16 bit per channel data transfers 128 Bytes 64 Byte 64 Byte FIFO for Tx Rx e Supports IIS format and MSB justified data format USB Host e 2 port USB Host e Complies with Rev 1 0 e Compatible with USB Specification version 1 1 USB Device 1 port USB Device 5 Endpoints for USB Device e Compatible with USB Specification version 1 1 1 4 S3C2410A SD Host Interface e Compatible with SD Memory Card Protocol version 1 0 e Compatible with SDIO C
423. register HDIVN1 HDIVN PDIVN FCLK HCLK PCLK FCLK FCLK FCLK Depa FCLK FOLK FCLK 2 FCLK FCLK 2 2 FCLK FCLK 2 FCLK 4 2 4 FCLK FCLK 4 FCLK 4 After setting PMS value it is required to set CLKDIVN register The setting value of CLKDIVN will be valid after PLL lock time The value is also available for reset and changing Power Management Mode The setting value can also be valid after 1 5 HCLK Only 1HCLK can validate the value of CLKDIVN register changed from Default 1 1 1 to other Divide Ratio 1 1 2 1 2 2 1 2 4 and 1 4 4 FCLK 1 I CLKDIVN 0x00000000 0x00000001 1 1 2 0x00000003 1 2 4 f 0 00000000 1 1 1 1 HCLK PCLK 1 HCLK 4 gt 1 5 HCLK 1 5 HCLK Figure 7 6 Changing CLKDIVN Register Value NOTES CLKDIVN should be set carefully not to exceed the limit of HCLK and PCLK 2 If HDIVN 1 the CPU bus mode has to be changed from the fast bus mode to the asynchronous bus mode using following instructions MMU SetAsyncBusMode pl5 0 r0 cl c0 0 orr 0 1 nF OR R1 iA mcr 15 0 0 1 0 0 If HDIVN 1 and the CPU bus mode is the fast bus mode the CPU will operate by the HCLK This feature can be used to change the CPU frequency as a half without affecting the HCLK and PCLK 7 8 ELECTRONICS 53 2410 CLOCK 8 POWER MANAGEMENT POWER MANAGEMENT The power management block controls the syste
424. ress 7 bits DATA H m La Read Data Transferred Data Acknowledge NOTES 1 5 Start rS Repeat Start Stop A Acknowledge 2 From Master to Slave 0 From Slave to Master Figure 20 3 IIC Bus Interface Data Format 20 4 ELECTRONICS 53 2410 IIC BUS INTERFACE Acknowledgement Acknowledgement Signal from Receiver Signal from Receiver ACK t Byte Complete Interrupt Clock Line Held Low by within Receiver receiver and or transmitter Figure 20 4 Data Transfer on the IIC Bus ACK SIGNAL TRANSMISSION To complete a one byte transfer operation the receiver should send an ACK bit to the transmitter The ACK pulse should occur at the ninth clock of the SCL line Eight clocks are required for the one byte data transfer The master should generate the clock pulse required to transmit the ACK bit The transmitter should release the SDA line by making the SDA line High when the ACK clock pulse is received The receiver should also drive the SDA line Low during the ACK clock pulse so that the SDA keeps Low during the High period of the ninth SCL pulse The ACK bit transmit function can be enabled or disabled by software IICSTAT However the ACK pulse on the ninth clock of SCL is required to complete the one byte data transfer operation Data Output by Transmitter Data Output by Receiver SCL from Master Condition Clock Pulse for Acknowledgment Figure 20 5 Acknowledge on the IIC Bu
425. result of the form RdHi RdLo Rm Rs The lower 32 bits of the 64 bit result are written to RdLo the upper 32 bits of the result are written to RdHi The multiply accumulate forms UMLAL and SMLAL take two 32 bit numbers multiply them and add a 64 bit number to produce a 64 bit result of the form RdHi RdLo Rm Rs RdHi RdLo The lower 32 bits of the 64 bit number to add is read from RdLo The upper 32 bits of the 64 bit number to add is read from RdHi The lower 32 bits of the 64 bit result are written to RdLo The upper 32 bits of the 64 bit result are written to RdHi The UMULL and UMLAL instructions treat all of their operands as unsigned binary numbers and write an unsigned 64 bit result The SMULL and SMLAL instructions treat all of their operands as two s complement signed numbers and write a two s complement signed 64 bit result ELECTRONICS 3 25 ARM INSTRUCTION SET 83 2410 OPERAND RESTRICTIONS e R15 must not be used as an operand or as a destination register e RdLo and Rm must all specify different registers CPSR FLAGS Setting the CPSR flags is optional and is controlled by the S bit in the instruction The N and Z flags are set correctly on the result N is equal to bit 63 of the result Z is set if and only if all 64 bits of the result are zero Both the C and V flags are set to meaningless values INSTRUCTION CYCLE TIMES MULL takes 15 m 1 l and MLAL 15 m 2 I cycles to execute where m is the
426. ring 3 word time receive time out This interval follows the setting of Word Length bit Tx interrupt Generated whenever transmit data reaches the Generated by the transmit holding register trigger level of transmit FIFO Tx FIFO trigger Level whenever transmit buffer becomes empty Error interrupt Generated when frame error has detected Generated by all errors However if another error occurs at the same time only one interrupt is generated Generated when it gets to the top of the receive FIFO without reading out data in it overrun error ELECTRONICS 11 5 UART 53 2410 UART Error Status FIFO UART has the error status FIFO besides the Rx FIFO register The error status FIFO indicates which data among FIFO registers is received with an error The error interrupt will be issued only when the data which has an error is ready to read out To clear the error status FIFO the URXHn with an error and UERSTATn must be read For example It is assumed that the UART Rx FIFO receives A B C and D characters sequentially and the frame error occurs while receiving The actual UART receive error will not generate any error interrupt because the character which was received with an error has not been read yet The error interrupt will occur when the character is read out Figure 11 3 shows the UART receiving the four characters including the one error seguence Fow __ When characeri
427. riptor returned is either a section descriptor a coarse page table descriptor or a fine page table descriptor A section descriptor provides the base address of a 1MB block of memory The page table descriptors provide the base address of a page table that contains level two descriptors There are two sizes of page table e coarse page tables have 256 entries splitting the 1MB the table describes into 4KB blocks e fine page tables have 1024 entries splitting the 1MB the table describes into 1KB blocks coarse page abi baso aaaross P 0 1 coarse page tanie ooo sente C Fre pasese base assess D 111 Fme page tanie Figure 3 4 Level One Descriptors The two least significant bits indicate the descriptor type Table 3 2 Interpreting Level One Descriptor Bits 1 0 Value Meaning 000 Generates a section translation fault Coarse page table Indicates that this is a coarse page table descriptor Indicates that this is a section descriptor Fine page table Indicates that this is a fine page table descriptor 3 8 ELECTRONICS ARM920T PROCESSOR MMU SECTION DESCRIPTOR Bits 3 2 C amp B indicate whether the area of memory mapped by this section is treated as write back cacheable write through cacheable non cached buffered or non cached non buffered Bit 4 should be written to 1 for backward compatibility Bits 8 5 specify one of the 16 po
428. rnal DMA request acknowledge protocols Single service Demand Single service Handshake and Whole service Handshake mode Each type defines how the signals like DMA request and acknowledge are related to these protocols Basic DMA Timing The DMA service means performing paired Reads and Writes cycles during DMA operation which can make one DMA operation Figure 8 1 shows the basic Timing in the DMA operation of the S8C2410A setup time and the delay time of XnXDREQ and XnXDACK are the same in all the modes If the completion of XnXDREQ meets its setup time it is synchronized twice and then XnXDACK is asserted After assertion of XnXDACK DMA requests the bus and if it gets the bus it performs its operations XnXDACK is deasserted when DMA operation is completed XnXDACK I Read X Write Read write Figure 8 1 Basic DMA Timing Diagram Table 8 2 DMA Controller Module Signal Timing Constants Vpp 1 8 V 0 15 V 2 0V 0 1V 40 to 85 Vey 3 3V 0 3V ss ELECTRONICS 8 3 DMA S3C2410A Demand Handshake Mode Comparison Demand and Handshake modes are related to the protocol between XnXDREQ and XnXDACK Figure 8 2 shows the differences between the two modes At the end of one transfer Single Burst transfer DMA checks the state of double synched XnXDREQ Demand Mode If XnXDREQ remains asserted the next transfer starts immediately Otherwise it waits for XnXDR
429. round The DMA auto reload is occurred only when the DMA request is issued after the DMA counter reaches 0 So the following code should be used in the DMA done interrupt handler before setting the DMA source address destination address and counter register for the next auto reload This code will wait until the first DMA request is issued and the previous auto reload value is loaded while rDSTATn amp Oxfffff 0 8 14 ELECTRONICS 53 2410 PORTS PORTS OVERVIEW The S3C2410A has 117 multi functional input output port pins The ports are Port A GPA 23 output port Port B GPB 11 input output port Port C GPC 16 input output port Port D GPD 16 input output port Port E GPE 16 input output port Port F GPF 8 input output port Port G GPG 16 input output port Port H GPH 11 input output port Each port can be easily configured by software to meet various system configurations and design requirements You have to define which function of each pin is used before starting the main program If a pin is not used for multiplexed functions the pin can be configured as ports Initial pin states are configured seamlessly to avoid problems ELECTRONICS 9 1 PORTS 53 2410 Table 9 1 S3C2410A Port Configuration Port A Selectable Pin Functions Owwoy GPAm mRSTQU 7 7 Omuoy
430. rrupt or DMA EP2 64byte IN OUT FIFO dual port asynchronous RAM interrupt or DMA 64byte IN OUT FIFO dual port asynchronous RAM interrupt DMA EP4 64byte IN OUT FIFO dual port asynchronous RAM interrupt or DMA Integrated USB Transceiver FEATURE Fully compliant with USB Specification Version 1 1 Full speed 12Mbps device Integrated USB Transceiver Supports control interrupt and bulk transfer Five endpoints with FIFO One bi directional control endpoint with 16 byte FIFO Four bi directional bulk endpoints with 64 byte FIFO EP1 EP2 EP3 and EP4 Supports DMA interface for receive and transmit bulk endpoints EP1 EP2 EP3 and EP4 Independent 64byte receive and transmit FIFO to maximize throughput Supports suspend and remote wakeup function NOTE PCLK should be more than 20MHz to use USB Device Controller stably ELECTRONICS 13 1 USB DEVICE 53 2410 MC ADDR 13 0 MC DATA IN 31 0 RT VM IN MC_DATA_OUT 31 0 ___________ P_IN USB_CLK lt SYS_CLK lt SYS_RESETN RT_VP_OUT 4 WR lt 9 RT_VM_OUT ee WR_RDN lt RT_UX_OEN MC_CSN gt MC_INTR RT_UXSUSPEND gt DREQN 3 0 DACKN 3 0 Figure 13 1 USB Device Controller Block Diagram 13 2 ELECTRONICS 53 2410 USB DEVICE USB DEVICE CONTROLLER SPECIAL REGISTERS This section describes detailed functionalities about register sets of USB
431. s ELECTRONICS 20 5 IIC BUS INTERFACE 53 2410 READ WRITE OPERATION In Transmitter mode when the data is transferred the IIC bus interface will wait until IIC bus Data Shift IICDS register receives a new data Before the new data is written into the register the SCL line will be held low and then released after it is written The S3C2410A should hold the interrupt to identify the completion of current data transfer After the CPU receives the interrupt request it should write a new data into the IICDS register again In Receive mode when a data is received the IIC bus interface will wait until IICDS register is read Before the new data is read out the SCL line will be held low and then released after it is read The S3C2410A should hold the interrupt to identify the completion of the new data reception After the CPU receives the interrupt request it should read the data from the IICDS register BUS ARBITRATION PROCEDURES Arbitration takes place on the SDA line to prevent the contention on the bus between two masters If a master with a SDA High level detects the other master with a SDA active Low level it will not initiate a data transfer because the current level on the bus does not correspond to its own The arbitration procedure will be extended until the SDA line turns High However when the masters simultaneously lower the SDA line each master should evaluate whether or not the mastership is allocated to itself For the
432. s and memory control signals are Hi z state as shown in Table 1 1 When nXBREQ is de asserted the nXBACK will also be de asserted If nXBREQ is asserted the S3C2410A will respond by lowering nXBACK If nXBACK eto O og oo Figure 5 3 S3C2410A nXBREQ nXBACK Timing Diagram ELECTRONICS 5 6 53 2410 MEMORY CONTROLLER ROM Memory Interface Examples Figure 5 4 Memory Interface with 8 bit ROM Figure 5 5 Memory Interface with 8 bit ROM x 2 ELECTRONICS 5 7 MEMORY CONTROLLER 53 2410 nWBE2 nGCSn Figure 5 6 Memory Interface with 8 bit ROM x 4 Figure 5 7 Memory Interface with 16 bit ROM 5 8 ELECTRONICS 53 2410 MEMORY CONTROLLER SRAM Memory Interface Examples Figure 5 9 Memory Interface with 16 bit SRAM x 2 ELECTRONICS 5 9 MEMORY CONTROLLER 53 2410 SDRAM Memory Interface Examples 000 001 0092 003 004 005 006 007 008 009 0010 0011 0012 0013 0014 0015 nSCS SCKE nSRAS SCLK nSCAS nWE UDQM Figure 5 10 Memory Interface with 16 bit SDRAM 8MB 1Mb x 16 x 4banks AO DQ0 DQ0 1 001 001 A2 DQ2 DQ2 A3 DQ3 DQ3 A4 004 004 5 005 005 006 006 7 DQ7 DQ7 A8 DQ8 DQ8 A9 DQ9 DQ9 A10 DQ10 DQ10 11 0011 0011 0012 0012 BAO DQ13 BAO DQ13 0914 0914 0915 LDQM DQ15 UDQM UDQM nSCS 5 5 SCKE nSRAS SCKE nSRAS SCLK nSCAS SCLK nSCAS nWE nWE Figure 5 11 Memory Interface wit
433. s complement signed The C flag will be set to the carry out of bit 31 of the ALU the Z flag will be set if and only if the result was zero and the N flag will be set to the value of bit 31 of the result indicating a negative result if the operands are considered to be 2 s complement signed ELECTRONICS 3 11 ARM INSTRUCTION SET S3C2410A SHIFTS When the second operand is specified to be a shifted register the operation of the barrel shifter is controlled by the Shift field in the instruction This field indicates the type of shift to be performed logical left or right arithmetic right or rotate right The amount by which the register should be shifted may be contained in an immediate field in the instruction or in the bottom byte of another register other than R15 The encoding for the different shift types is shown in Figure 3 5 11 L I 1 6 5 Shift type 6 5 Shift type 00 logical left 01 logical right 00 logical left 01 logical right 10 arithmetic right 11 rotate right 10 arithmetic right 11 rotate right 11 7 Shift amount 11 8 Shift register 5 bit unsigned integer Shift amount specified in bottom byte of Rs Figure 3 5 ARM Shift Operations Instruction specified shift amount When the shift amount is specified in the instruction it is contained in a 5 bit field which may take any value from 0 to 31 A logical shift left LSL takes the contents of Rm and moves each bit by the specified amount
434. shown in the following figure 15 14 13 12 11 10 Move Shifted register Add subtract Offset8 Move compare add subtract immediate ALU operations H2 Hi register operations branch exchange Words PC relative load Load store with register offset 1 1 H S 1 Load store sign extended byte halfword Offset5 Load store with immediate offset Offset5 Rb Load store halfword SP relative load store Load address Add offset to stack pointer Push pop register Multiple load store Conditional branch Software interrupt Unconditional branch Long branch with link 15 14 13 12 11 Figure 4 1 THUMB Instruction Set Formats 4 2 ELECTRONICS 3C2410A THUMB INSTRUCTION SET OPCODE SUMMARY The following table summarizes the THUMB instruction set For further information about a particular instruction please refer to the sections listed in the right most column Table 4 1 THUMB Instruction Set Opcodes Lo Register Hi Register Condition Operand Operand Codes Set Add lamin gE uneonattonal brane v o ee lt lt 9 CMP Compare o LDMIA Load multiple m Y hs lage sag or v uw vove v 5 lt S lt lt lt H lt lt ELECTRONICS 4 3 THUMB INSTRUCTION SET S3C2410A Table 4 1 THUMB Instruction Set
435. sible gray levels The 2 bit per pixel gray lookup table uses the BULEVAL 15 0 in Blue Lookup Table BLUELUT register as same as blue lookup table in color mode The gray level 0 will be denoted by BLUEVAL 3 0 value If BLUEVAL 3 0 is 9 level 0 will be represented by gray level 9 among 16 gray levels If BLUEVAL 3 0 is 15 level 0 will be represented by gray level 15 among 16 gray levels and so on Following the same method as above level 1 will also be denoted by BLUEVAL 7 4 the level 2 by BLUEVAL 11 8 and the level 3 by BLUEVAL 15 12 These four groups among BLUEVAL 15 0 will represent level 0 level 1 level 2 and level 3 In 16 gray levels there is no selection as in the 16 gray levels ELECTRONICS 15 5 LCD CONTROLLER 53 2410 256 Level Color Mode Operation The S3C2410A LCD controller can support an 8 bit per pixel 256 color display mode The color display mode can generate 256 levels of color using the dithering algorithm and FRC The 8 bit per pixel are encoded into 3 bits for red 3 bits for green and 2 bits for blue The color display mode uses separate lookup tables for red green and blue Each lookup table uses the REDVAL 31 0 of REDLUT register GREENVAL 31 0 of GREENLUT register and BLUEVAL 15 0 of BLUELUT register as the programmable lookup table entries Similar to the gray level display 8 group or field of 4 bits in the REDLUR register i e REDVAL 831 28 REDLUT 27 24 REDLUT 23 20 REDLUT 19 16 REDLUT
436. sition Conversion Mode x xe w w w 16 4 ELECTRONICS 53 2410 ADC AND TOUCH SCREEN INTERFACE 3 Auto Sequential X Y Position Conversion Mode Auto Sequential X Y Position Conversion Mode AUTO_PST 1 and XY_PST 0 is operated in the following way The Touch Screen Controller automatically converts X position and Y position The Touch Screen Controller writes X measurement data to XPDATA of ADCDATO and then writes Y measurement data to YPDATA of ADCDAT1 After Auto Sequential Position Conversion The Touch Screen Controller generates Interrupt source INT_ADC to Interrupt Controller Table 16 2 Condition of Touch Screen Panel Pads in Auto Sequential X Y Position Conversion Mode v w 4 Waiting for Interrupt Mode When Touch Screen Controller is in Waiting for Interrupt Mode it waits for Stylus down The controller generates Interrupt INT_TC signals when the Stylus is down on Touch Screen Panel After an interrupt occurs X and Y position can be read by the proper conversion mode Separate X Y position conversion Mode or Auto X Y Position Conversion Mode Table 16 3 Condition of Touch Screen Panel Pads in Waiting for Interrupt Mode Low m w w Waiting for Interrupt Mode Pull up AINI Standby Mode Standby mode is activated when STDBM of ADCCON register is set to 1 In this mode A D conversion operation is halted and XPDATA Normal ADC of ADCDATO and YPDATA of ADCDAT
437. sor mode Only those explicitly described shall be used The user should be aware that if any illegal value is programmed into the mode bits M 4 0 then the processor will enter an unrecoverable state If this occurs reset should be applied Reserved bits The remaining bits in the PSRs are reserved When changing a PSR s flag or control bits you must ensure that these unused bits are not altered Also your program should not rely on them containing specific values since in future processors they may read as one or zero 2 8 ELECTRONICS 3C2410A PROGRAMMER S MODEL Table 2 1 PSR Mode Bit Values M 4 0 Visible THUMB state registers Visible ARM state registers 10000 User R7 RO R14 RO LR SP PC CPSR PC CPSR 10001 FIQ R7 RO R7 RO LR fig SP fiq R14 fig R8 fig PC CPSR SPSR fiq PC CPSR SPSR fiq 10010 R7 RO R12 R0 SP_irq R14 R13 irq PC CPSR SPSR irq PC CPSR SPSR irq 10011 Supervisor R7 R0 R12 R0 LR_svc SP_svc 14 svc R13 svc PC CPSR SPSR PC CPSR SPSR 10111 Abort R7 R0 R12 R0 LR_abt SP_abt R14 abt R13 abt PC CPSR SPSR abt PC CPSR SPSR abt 11011 Undefined R7 RO 12 LR_und SP_und R14 und R13 und PC CPSR SPSR_und PC CPSR 11111 System R7 R0 R14 R0 LR SP PC CPSR PC CPSR Reserved bits The remaining bits in the PSR s are reserved When changing a PSR s flag or control bits you must ensure that these unused b
438. sreadow AB Gand Disreccved The frame error in B interrupt occurs The B has to be read out 7 AtterBisreadout _ _ _ _ mecsre O O O ToS AfterDisreadout RX FIFO Error Status FIFO Frame Error UERSTATn Error Status Generator Unit Figure 11 3 UART Receiving 4 Characters with 1 Error 11 6 ELECTRONICS 53 2410 UART Baud Rate Generation Each UART s baud rate generator provides the serial clock for the transmitter and the receiver The source clock for the baud rate generator can be selected with the 53 2410 internal system clock or UEXTCLK In other words dividend is selectable by setting Clock Selection of UCONn The baud rate clock is generated by dividing the source clock PCLK or UEXTCLK by 16 and 16 bit divisor specified in the UART baud rate divisor register UBRDIVn The UBRDIVn can be determined by the following expression UBRDIVn int PCLK bps x 16 1 Where the divisor should be from 1 to 216 1 For accurate UART operation the 53 2410 also supports UEXTCLK as a dividend If the 53 2410 uses UEXTCLK which is supplied by an external UART device or system then the serial clock of UART is exactly synchronized with UEXTCLK So the user can get the more precise UART operation The UBRDIVn can be determined UBRDIVn int UEXTCLK bps x 16 1 Where the divisor should be from 1 to 219 1 and UEXTCLK should be smaller than PCLK For example if the baud r
439. ssible domains held in the domain access control registers that contain the primary access controls Bit 9 is always written as 0 Bits 11 10 AP specify the access permissions for this section Bits 19 12 are always written as 0 Bits 31 20 form the corresponding bits of the physical address for a section COARSE PAGE TABLE DESCRIPTOR Bits 3 2 are always written as 0 Bit 4 is always written as 1 Bits 8 5 specify one of the 16 possible domains held in the Domain access control registers that contain the primary access controls Bit 9 is always written as 0 Bits 31 10 form the base for referencing the level two descriptor The coarse page table index for the entry is derived from the modified virtual address If a coarse page table descriptor is returned from the level one fetch a level two fetch is initiated FINE PAGE TABLE DESCRIPTOR Bits 3 2 are always written as 0 Bit 4 is always written as 1 Bits 8 5 specify one of the 16 possible domains held in the domain access control registers that contain the primary access controls Bits 11 9 are always written as 0 Bits 31 12 form the base for referencing the level two descriptor The fine page table index for the entry is derived from the modified virtual address If a fine page table descriptor is returned from the level one fetch a level two fetch is initiated ELECTRONICS 3 9 MMU ARM920T PROCESSOR TRANSLATING SECTION REFERENCES Figure 3 5 illust
440. ssor Software Interrupt 3130 29 28 27 26 25 24 23 22 2120 19 1817 1615 1413 1211109876543210 Figure 3 1 ARM Instruction Set Format ELECTRONICS 3 1 ARM INSTRUCTION SET 53 2410 NOTE Some instruction codes are not defined but do not cause the Undefined instruction trap to be taken for instance a Multiply instruction with bit 6 changed to a 1 These instructions should not be used as their action may change in future ARM implementations INSTRUCTION SUMMARY Table 3 1 The ARM Instruction Set 7 Mnemonic instruction Adon a CDP Coprocessor specific EOR Rd Rn AND NOT Op2 OR Op2 AND NOT Rn LDM Stack manipulation Pop MCR Move CPU register to coprocessor cRn rRn lt op gt cRm register MLA Multiply Accumulate Rd Rm x Rs Rn 3 2 ELECTRONICS 3C2410A ARM INSTRUCTION SET Table 3 1 The ARM Instruction Set Continued Move from coprocessor register to Rn cRn lt op gt cRm CPU register om o STM Stack manipulation Push sw Swe ELECTRONICS 3 3 ARM INSTRUCTION SET 53 2410 THE CONDITION FIELD In ARM state all instructions are conditionally executed according to the state of the CPSR condition codes and the instruction s condition field This field bits 31 28 determines the circumstances under which an instruction is to be executed If the state of the C N Z and V flags fulfils the conditions encoded by the field the instruction is
441. start stop 20 Determine start stop for Timer 4 0 Stop 1 Start for Timer 4 Timer 3 auto reload on off 19 Determine auto reload on off for Timer 3 0 One shot 1 Interval mode auto reload Timer output inverter on off 18 Determine output inverter on off for Timer 0 Inverter off 1 Inverter on for TOUTS Timer manual update note 17 Determine manual update for Timer 3 0 No operation 1 Update TCNTB3 TCMPB3 Timer 3 start stop 16 Determine start stop for Timer 0 Stop 1 Start for Timer 3 Timer 2 auto reload on off 15 Determine auto reload on off for Timer 2 0 One shot 1 Interval mode auto reload Timer 2 output inverter on off 14 Determine output inverter on off for Timer 2 0 Inverter off 1 Inverter on for TOUT2 Timer 2 manual update te 13 Determine the manual update for Timer 2 0 operation 1 Update TCNTB2 TCMPB2 Timer 2 start stop 12 Determine start stop for Timer 2 0 Stop 1 Start for Timer 2 Timer 1 auto reload on off 11 Determine the auto reload on off for Timer1 0 One shot 1 Interval mode auto reload Timer 1 output inverter on off 10 Determine the output inverter on off for Timer1 0 Inverter off 1 Inverter on for TOUT1 Timer 1 manual update note Determine the manual update for Timer 1 0 operation 1 Update TCNTB1 TCMPB1 Timer 1 start stop Determine start stop for Timer 1 0 Sto
442. ster 10 TLB Lock Down E E ES 2 21 Registers 11 12 amp 14 Reserved tac need ied en e dee e it e ie ende ee f 2 22 Register 13 Process Du fe ee nete epic 2 22 Register 15 Test Configuration Register eee 2 24 Appendix 3 MMU MMU ae t dit He a e Peu areal eed 3 1 Access Permissions And 3 1 Translated ENTIE S eae ede d e e E e E E ER at 3 2 Mmu Program Accessible Registers U u u u u 3 3 Address Translation nu Ee RD a ed ae ae 3 4 Hardware Translation Process iiuen ununi ini nerti aapa na ra Via E aE 3 6 Translation Table pue ede eel Ne 3 6 Level One Eetch dni e Het i S Rad ee 3 7 LevelOne Descriptors ii Ceci c doe ep Mi e eri d eg Heer det eee ee 3 8 Section Descriptor een He ER 3 9 Coarse Page Table 3 9 Fine Page Table en a nns sense lues nnn abya 3 9 Translating Section References senten enne entren enn sensi nnns entren
443. supervisor routines DCD ZeroRtn DCD ReadCRin DCD WritelRtn eee Zero EQU 0 ReadC EQU 256 Writel EQU 512 Supervisor SWI has routine required in bits 8 23 and data if any in bits 0 7 Assumes R13 svc points to a suitable stack STMFD R13 RO R2 R14 Save work registers and return address LDR RO R14 4 Get SWI instruction BIC RO RO 0xFFO00000 Clear top 8 bits MOV R1 RO LSR 8 Get routine offset ADR R2 EntryTable Get start address of entry table LDR R15 R2 R1 LSL 2 Branch to appropriate routine WritelRtn Enter with character in RO bits 0 7 LDMFD R13 RO R2 R15 Restore workspace and return restoring processor mode and flags 3 50 ELECTRONICS 53 2410 ARM INSTRUCTION SET COPROCESSOR DATA OPERATIONS CDP The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The instruction encoding is shown in Figure 3 25 This class of instruction is used to tell a coprocessor to perform some internal operation No result is communicated back to ARM920T and it will not wait for the operation to complete The coprocessor could contain a queue of such instructions awaiting execution and their execution can overlap other activity allowing the coprocessor and 920 to perform independent tasks in parallel COPROCESSOR INSTRUCTIONS The S3C2410A unlike some other ARM based processors does not have an external coprocessor interface It does not have a
444. system timing must be considered to avoid under run condition of the fifo of the Icd controller caused by memory bandwidth contention Example 4 TFT Resolution 240 x 240 VSPW 2 VBPD 14 LINEVAL 239 VFPD 4 HSPW 25 HBPD 15 HOZVAL 239 HFPD 1 CLKVAL 5 HCLK 60M Hz The parameters below must be referenced by LCD size and driver specifications VSPW VBPD LINEVAL VFPD HSPW HBPD HOZVAL and HFPD If target frame rate is 60 70Hz then CLKVAL should be 5 So Frame Rate 67Hz Known Problems Problem In a MDS such as Multi ICE some of the LCD controller registers may be displayed incorrectly in the memory view window of the ARM debugger Solution The LCD controller register will be displayed correctly unless the memory view window is used Instead use command in the debugger console window 15 42 ELECTRONICS 3C2410A ADC AND TOUCH SCREEN INTERFACE ADC amp TOUCH SCREEN INTERFACE OVERVIEW The 10 bit CMOS analog to digital converter ADC of the S8C2410A is a recycling typed device with 8 channel analog inputs It converts the analog input signal into 10 bit binary digital codes at a maximum conversion rate of 500KSPS with 2 5 MHz A D converter clock The A D converter operates with on chip sample and hold function and power down mode is supported The S3C2410A supports Touch Screen Interface which consists of a touch screen panel four external transistors an external voltage source
445. t Translation table Holds the physical address of the base of the translation base register table maintained in main memory This base address must be on a 16KB boundary and is common to both TLBs Domain access Comprises sixteen 2 bit fields control register Each field defines the access control attributes for one of 16 domains 015 00 Fault status register Indicates the cause of a data and prefetch abort and the domain number of the aborted access when an abort occurs Bits 7 4 specify which of the 16 domains D15 D0 was being accessed when a fault occurred Bits 3 0 indicate the type of access being attempted The value of all other bits is unpredictable The encoding of these bits is shown in Table 3 4 on page 3 18 Fault address Holds the virtual address associated with the access that register caused the data abort See Table 3 4 on page 3 18 for details of the address stored for each type of fault ARMSTDMI Register 14 can be used to determine the virtual address associated with a prefetch abort TLB operations Writing to this register causes the MMU to perform TLB register maintenance operations either invalidating all the unpreserved entries in the TLB or invalidating a specific entry TLB lock down Allows specific page table entries to be locked into the register TLB and the TLB victim index to be read written opcode 2 0x0 accesses the D TLB lock down register opcode 2 0x1 accesses the TLB
446. t be repeated in 64 consecutive entries The figure below shows the format of level one descriptors 16 15 1211109 8 7 6 5 4 3 2 1 O o UT arse page se aaaress v v JoJo of tase nae ers c o sman pase trv pagenascossress vo Figure 3 6 Page Table Entry Level One Descriptor Bits 1 0 indicate the page size and validity and are interpreted as follows Table 3 3 Interpreting Page Table Entry Bits 1 0 Meaning 0 Generates a page translation fault Large page Indicates that this is a 64KB page Small page Indicates that this is a 4KB page Tiny page Indicates that this is a 1KB page ELECTRONICS 3 11 MMU ARM920T PROCESSOR Bit 3 2 C amp B indicate whether the area of memory mapped by this page is treated as write back cacheable write through cacheable non cached buffered or non cached non buffered Domain access control on page 3 19 and Fault checking sequence on page 3 21 show how to interpret the access permission ap bits NOTE Tiny pages do not support sub page permissions and therefore only have one set of access permission bits Bits 31 10 tiny pages 31 12 small pages or bits 31 16 large pages are used to form the corresponding bits of the physical address TRANSLATING LARGE PAGE REFERENCES Figure 3 7 on 3 13 illustrates the complete translation sequen
447. t gt lt Shiftname gt lt register gt or lt shiftname gt expression or RRX rotate right one bit with extend lt shiftname gt s ASL LSL LSR ASR ROR ASL is a synonym for LSL they assemble to the same code EXAMPLES ADDEQ R2 R4 R5 If the Z flag is set make R2 R4 R5 TEQS R4 3 Test R4 for equality with 3 The S is in fact redundant as the assembler inserts it automatically SUB R4 R5 R7 LSR R2 Logical right shift R7 by the number in the bottom byte of R2 subtract result from R5 and put the answer into MOV PC R14 Return from subroutine MOVS PC R14 Return from exception and restore CPSR from SPSR_mode ELECTRONICS 3 17 ARM INSTRUCTION SET 53 2410 PSR TRANSFER MRS MSR The instruction is only executed if the condition is true The various conditions are defined in Table 3 2 The MRS and MSR instructions are formed from a subset of the Data Processing operations and are implemented using the TEQ TST CMN and CMP instructions without the S flag set The encoding is shown in Figure 3 11 These instructions allow access to the CPSR and SPSR registers The MRS instruction allows the contents of the CPSR or SPSR mode to be moved to a general register The MSR instruction allows the contents of a general register to be moved to the CPSR or SPSR_ lt mode gt register The MSR instruction also allows an immediate value or register contents to be transferred to the condition code flags N Z C
448. t pin is enabled 1 The pull up function is disabled ELECTRONICS 9 9 PORTS 53 2410 PORT CONTROL REGISTERS GPCCON GPCDAT and GPCUP Pull up disable register for port C Reserved oxse000020 ea GPCCON SSS GPC15 31 30 00 Input 10 VD 7 GPC14 29 28 00 Input 10 VD 6 GPC13 27 26 00 Input 10 VD 5 GPC12 25 24 00 Input 10 VD 4 GPC11 23 22 00 Input 10 VD 3 GPC10 21 20 00 Input 10 VD 2 GPC9 19 18 00 Input 10 VD 1 GPC8 17 16 00 Input 10 VD 0 GPC7 15 14 00 Input 10 LCDVF2 13 12 00 Input 10 LCDVF1 11 10 00 Input 10 LCDVFO 00 Input 10 VM 7 6 00 Input 10 VFRAME 5 4 00 Input 10 VLINE 3 2 00 Input 10 VCLK 1 0 00 Input 10 LEND 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved 01 Output 11 Reserved ELECTRONICS 3 2410 PORTS GPCDAT GPC 15 0 15 0 When the port is configured as input port data from external sources can be read to the corresponding pin When the port is configured as out
449. t source can be serviced in the FIQ mode in the interrupt controller you should use the FIQ mode only for the urgent interrupt Thus only one bit of INTMOD can be set to 1 INTMOD 0 4 000004 R W Interrupt mode regiseter 0x00000000 0 IRQ mode 1 FIQ mode NOTE If an interrupt mode is set to mode in the INTMOD register interrupt will not affect both INTPND and INTOFFSET registers In this case the two registers are valid only for IRQ mode interrupt source 14 8 ELECTRONICS 53 2410 INTERRUPT CONTROLLER 1 FIQ 1 FIQ 1 FIQ 1 FIQ 1 FIQ 1 FIQ 1 FIQ sua SSCS INT_UART2 15 0 IRQ INT_TIMER4 14 0 IRQ INT_TIMER3 13 0 IRQ INT_TIMER2 12 0 IRQ 1 FIQ INT_TIMER1 11 0 IRQ 1 FIQ 1 FIQ 1 FIQ 1 FIQ 1 FIQ 1 FIQ 1 FIQ 1 FIQ 1 FIQ 1 FIQ 1 FIQ 1 FIQ INT_TIMERO 10 0 IRQ 1 INT 0 IRQ INT_TICK nBATT_FLT 0 IRQ 1 FIQ 1 FIQ 1 FIQ Reseed we 1 FIQ 1 FIQ 1 FIQ 1 FIQ EINT1 1 0 IRQ 1 ELECTRONICS 1 INTERRUPT CONTROLLER 53 2410 INTERRUPT MASK INTMSK REGISTER This register also has 32 bits each of which is related to an interrupt source If a specific bit is set to 1 the CPU does not service the interrupt request from the corresponding interrupt source note that even in such a case the corresponding bit of SRCPND register is set to 1 If the mask bit is 0 the in
450. t to Rd They are used only to perform tests and to set the condition codes on the result and always have the S bit set The instructions and their effects are listed in Table 3 3 3 10 ELECTRONICS 3C2410A ARM INSTRUCTION SET CPSR FLAGS The data processing operations may be classified as logical or arithmetic The logical operations AND EOR TST TEQ ORR MOV BIC MVN perform the logical action on all corresponding bits of the operand or operands to produce the result If the S bit is set and Rd is not R15 see below the V flag in the CPSR will be unaffected the C flag will be set to the carry out from the barrel shifter or preserved when the shift operation is LSL 0 the Z flag will be set if and only if the result is all zeros and the N flag will be set to the logical value of bit 31 of the result Table 3 3 ARM Data Processing Instructions Assembler Mnemonic OPCode WUB Om oeno OOOO MOV Operand2 operand1 is ignored BIC Operand1 AND NOT operand Bit clear MVN operand2 operand is ignored The arithmetic operations SUB RSB ADD ADC SBC RSC CMP CMN treat each operand as a 32 bit integer either unsigned or 2 s complement signed the two are equivalent If the S bit is set and Rd is not R15 the V flag in the CPSR will be set if an overflow occurs into bit 31 of the result this may be ignored if the operands were considered unsigned but warns of a possible error if the operands were 2
451. t to an initial value before enabling it WTCNT 0x53000008 Watchdog timer count register 0x8000 Count Value 15 0 The current count value of the watchdog timer 0x8000 8 4 ELECTRONICS 53 2410 MMC SD SDIO HOST CONTROLLER MMC SD SDIO HOST CONTROLLER OVERVIEW The S3C2410A SD Host controller can support MMC SD card and SDIO devices FEATURES SD Memory Card Spec ver 1 0 MMC Spec 2 11 compatible SDIO Card Spec ver 1 0 compatible 16 words 64 bytes FIFO depth 16 for data Tx Rx 40 bit Command Register SDICARG 81 0 SDICCON 7 0 136 bit Response Register SDIRSPn 127 0 SDICSTA 7 0 8 bit Prescaler logic Freq System Clock 2 P 1 CRC7 amp CRC16 Generator Polling Interrupt and DMA Data Transfer Mode Byte or Word transfer 1 bit 4 bit wide bus Mode amp Block Stream Mode Switch support Supports up to 25 MHz in data transfer mode for SD SDIO Supports up to 20 MHz in data transfer mode for MMC ELECTRONICS 19 1 MMC SD SDIO HOST CONTROLLER S3C2410A BLOCK DIAGRAM CMD Reg CMD Control 5byte PADDR 8bit Shift Reg Resp Reg CRC7 PSEL 17byte POLK 1 32 DAT Control TxDAT 3 0 31 0 32bit Shift Reg 3 0 PRDATA 64byte 32 CRC16 4 RxDAT 3 0 31 0 DREQ DACK INT Figure 19 1 Block Diagram 19 2 ELECTRONICS 53 2410 MMC SD SDIO HOST CONTROLLER SDI OPERATION A serial clock line is synchronized
452. ta at a frequency is determined by its corresponding control register settings If you only want to transmit received data can be dummy Otherwise if you only want to receive you should transmit dummy 1 data There 4 I O pin signals associated with SPI transfers the SCK SPICLKO 1 the MISO SPIMISOO 1 data line MOSI SPIMOSIO 1 data line and the active low 55 nSS0 1 pin input FEATURES SPI Protocol compatible 8 Shift Register for transmit 8 Shift Register for receive 8 0 Prescaler logic Polling Interrupt and DMA transfer mode ELECTRONICS 22 1 SPI INTERFACE BLOCK DIAGRAM 22 2 LSB MSB Tx 8bit Shift Reg 0 Slave Master MSB LSB Slave Rx 8bit Shift Reg 0 Master SPI Clock 8bit Prescaler 0 Slave a CLOCK Logico 4 Master CPOL Prescaler Register 0 DEDE Status Register 0 INT 0 INT 1 REQ1 HERRA ACKO ACK1 LSB M Tx 8bit Shift Reg 1 SB MSB LSB Rx 8bit Shift Reg 1 k SPI Clock Master 8bit Prescaler 1 Prescaler Register 1 Status Register 1 INTO INT 1 lt REQO REQ1 4 ACKO ACK1 APB I F 1 INT DMA 1 Figure 22 1 SPI Block Diagram Pin Control Logic 0 Pin Control Logic 1 3C2410A ELECTRONICS 53 2410 SPI INTERFACE SPI OPERATION Using the SPI interface the S3C2410A can send receive 8 bit data si
453. ta Setto 1 whenever Rx FIFO has last data of all block Ready RFLast KEE not received yet 1 Last data ready Rx FIFO Full Set to 1 whenever Rx FIFO is full RFFull 0 0 lt FIFO lt 63 1 Full 64byte Rx FIFO Half Full 7 Set to 1 whenever Rx FIFO is more than 31byte RFHalf 0 0 lt RxFIFO lt 31 1 32 lt Rx FIFO lt 64 FIFO Count Number of data byte in FIFO 0000000 FFCNT Tx FIFO Empty 10 i to 1 whenever Tx FIFO is empty TFEmpty 1 lt Tx FIFO lt 64 1 Empty Obyte ELECTRONICS 19 13 MMC SD SDIO HOST CONTROLLER S3C2410A SDI Data SDIDAT Register Register Address R W Description Reset Value SDIDAT 0x5A00003C Li W SDI data register Li B Bi W 0x5A00003F Bi B SDIDAT Bit Description Data Register 31 0 This field contains the data to be transmitted or received over 0x00000000 the SDI channel NOTES 1 LIW Li B Access by Word Byte unit when endian mode is Little 2 Bi W Access by Word unit when endian mode is Big 3 Bi B Access by Byte unit when endian mode is 19 14 ELECTRONICS 53 2410 MMC SD SDIO HOST CONTROLLER SDI Interrupt Mask SDIIMSK Register Register Address R W Description Reset Value SDIIMSK 0x5A000040 SDI interrupt mask register 0x0 RspCrc Interrupt 17 Enable CmdSent Interrupt 16 Enable CmdTout Interrupt 15 Enable RspEnd Interrupt 14 Enable RWaitReq Interrupt 13 Enable IOIntDet Interrupt 12 Enable FFfa
454. tained before the instruction was executed This removes the need for the data abort handler to unwind any base register update which may have been specified by the aborted instruction 2 2 ELECTRONICS ARM920T PROCESSOR PROGRAMMER S MODEL INSTRUCTION SET EXTENSION SPACES All ARM processors implement the undefined instruction space as one of the entry mechanisms for the undefined instruction exception That is ARM instructions with opcode 27 25 06011 and opcode 4 1 are undefined on all ARM processors including the ARM9TDMI and ARM7TDMI ARM architecture v4 and v4T also introduced a number of instruction set extension spaces to the ARM instruction set These are arithmetic instruction extension space e control instruction extension space coprocessor instruction extension space load store instruction extension space Instructions in these spaces are undefined they cause an undefined instruction exception The ARM9TDMI fully implements all the instruction set extension spaces defined in ARM architecture v4T as undefined instructions allowing emulation of future instruction set additions The system control coprocessor CP15 allows configuration and control of the caches MMU protection system and clocking mode of the ARM920T The ARM920T coprocessor 15 registers are described under the following sections e Accessing CP15 registers on page 2 5 e Register 0 ID code register on page 2 7 e Register 0 Cache type
455. tate sub FSM handling the atomic operation of DMA is initiated The sub FSM reads the data from the source address and then writes it to destination address In this operation data size and transfer size single or burst are considered This operation is repeated until the counter TC becomes 0 in Whole service mode while performed only once in Single service mode The main FSM this FSM counts down the CURR TC when the sub FSM finishes each of atomic operation In addition this main FSM asserts the INT REQ signal when CURR TC becomes 0 and the interrupt setting of DCON 29 register is set to 1 In addition it clears DMA ACK if one of the following conditions is met 1 CURR TC becomes 0 in the Whole service mode 2 Atomic operation finishes in the Single service mode Note that in the Single service mode these three states of main FSM are performed and then stops and waits for another DMA REQ And if DMA REQ comes in all three states are repeated Therefore DMA ACK is asserted and then deasserted for each atomic transfer In contrast in the Whole service mode main FSM waits at state 3 until CURR becomes 0 Therefore DMA ACK is asserted during all the transfers and then deasserted when TC reaches 0 However INT REQ is asserted only if CURR TC becomes 0 regardless of the service mode Single service mode or Whole service mode 8 2 ELECTRONICS 3C2410A DMA EXTERNAL DMA DREQ DACK PROTOCOL There are three types of exte
456. ter O with the opcode 2 field set to any value other than 1 the CRm field should be zero when reading For example MRC p15 0 Rd c0 c0 0 returns ID register The contents of the ID code are shown in Table 2 5 Table 2 5 Register 0 ID Code 23 20 Specification revision 19 16 Architecture version 4T ELECTRONICS 2 7 PROGRAMMER S MODEL ARM920T PROCESSOR REGISTER 0 CACHE TYPE REGISTER This is a read only register which contains information about the size and architecture of the caches allowing operating systems to establish how to perform such operations as cache cleaning and lockdown Future ARM cached processors will contain this register allowing RTOS vendors to produce future proof versions of their operating systems The cache type register is accessed by reading CP15 register 0 with the opcode_2 field set to 1 For example p15 0 Rd c0 c0 1 returns cache details The format of the register is shown in Table 2 6 Table 2 6 Cache Type Register Format e mam 9 ma m uw mew o ws S ws Bits 28 25 indicate which major cache class the implementation falls into 0 6 means that the cache provides e Cache clean step operation e Cache flush step operation e Lock down facilities 2 8 ELECTRONICS ARM920T PROCESSOR PROGRAMMER S MODEL Bits 20 18 give the data cache size Bits 8 6 give t
457. terpreting Access Control Bits in Domain Access Control Register No Access Any access will generate a domain fault Client Accesses are checked against the access permission bits in the section or page descriptor Reserved Currently behaves like the no access mode Manager Accesses are not checked against the access permission bits so a permission fault cannot be generated ELECTRONICS 3 19 MMU ARM920T PROCESSOR Table 3 6 shows how to interpret the access permission AP bits and how their interpretation is dependent upon the S and R bits control register bits 8 and 9 Table 3 6 Interpreting Access Permission AP Bits Supervisor User Permissions Permissions No access No access Any access generates a permission fault 1 Read only Read only Any write generates a permission fault o mee J j 01 x x Read write No access Access allowed only in supervisor mode 10 x x Read write Read only Writes in user mode cause permission fault 11 x x Read write Read write All access types permitted in both modes po eee 3 20 ELECTRONICS ARM920T PROCESSOR MMU FAULT CHECKING SEQUENCE The sequence by which the MMU checks for access faults is different for sections and pages The sequence for both types of access is shown below The conditions that generate each of the faults are described on the following pages Modified virtual address Check address alignment Misaligned Section transla
458. terrupt request can be serviced INTMSK 0 4 000008 R W Determine which interrupt source is masked The OxFFFFFFFF masked interrupt source will not be serviced 0 Interrupt service is available 1 Interrupt service is masked 14 10 ELECTRONICS 53 2410 INTERRUPT CONTROLLER IN B mitalState 0 Service available 1 Masked 0 Service available 1 Masked 0 Service available 1 Masked 0 Service available 1 Masked 0 Service available 1 Masked 0 Service available 1 Masked 0 Service available 1 Masked 0 Service available 1 Masked 0 Service available 1 Masked 0 Service available 1 Masked 0 Service available 1 Masked 0 Service available 1 Masked 0 Service available 1 Masked 0 Service available 1 Masked 0 Service available 1 Masked 0 Service available 1 Masked INT_TIMER4 0 Service available 1 Masked INT TIMER3 0 Service available 1 Masked INT 1 0 Service available 1 Masked INT_WDT o Service available 1 Masked 0 Service available 1 Masked 0 Service available 1 Masked _ 0 Service available 1 Masked 0 Service available 1 Masked 0 Service available 1 Masked 0 Service available 1 Masked 1 0 Service available 1 Masked EN Tt 0 Service available 1 Masked ELECTRONICS 14 11 INTERRUPT CONTROLLER 83 2410 PRIORITY
459. the condition codes Note that the THUMB opcode will contain 26 the Word7 value and S 1 4 30 ELECTRONICS 3C2410A THUMB INSTRUCTION SET FORMAT 14 PUSH POP REGISTERS 14 11 7 0 Register List 8 PC LR Bit 0 Do not store LR Load PC 1 Store LR Load PC 11 Load Store Bit 0 Store to memory 1 Load from memory Figure 4 15 Format 14 OPERATION The instructions in this group allow registers 0 7 and optionally LR to be pushed onto the stack and registers 0 7 and optionally PC to be popped off the stack The THUMB assembler syntax is shown in Table 4 15 NOTE The stack is always assumed to be Full Descending Table 4 15 PUSH and POP Instructions L THUMB assembler ARM equivalent PUSH Rlist STMDB R13 Rlist EE EN the registers specified by Rlist onto the stack Update the stack pointer PUSH Rlist LR STMDB R13 Push the Link Register and the registers Rlist R14 specified by Rlist if any onto the stack Update the stack pointer 1 POP Rlist R13 Rlist Pop values off the stack into the registers specified by Rlist Update the stack pointer 1 1 POP Rlist PC R13 Rlist R15 Pop values off the stack and load into the registers specified by Rlist Pop the PC off the stack Update the stack pointer ELECTRONICS 4 31 THUMB INSTRUCTION SET 53 2410 INSTRUCTION CYCLE TIMES All instructions in this format have a
460. the instruction following the SWI NOTE nFIQ nIRQ ISYNC LOCK BIGEND and ABORT pins exist only in the ARM920T CPU core Undefined Instruction When ARM920T comes across an instruction which it cannot handle it takes the undefined instruction trap This mechanism may be used to extend either the THUMB or ARM instruction set by software emulation After emulating the failed instruction the trap handler should execute the following irrespective of the state ARM or Thumb MOVS PC R14 und This restores the CPSR and returns to the instruction following the undefined instruction Exception Vectors The following table shows the exception vector addresses Table 2 3 Exception Vectors _____ ELECTRONICS 2 13 PROGRAMMER S MODEL S3C2410A Exception Priorities When multiple exceptions arise at the same time a fixed priority system determines the order in which they are handled Highest priority 1 Reset 2 Data abort 3 FIQ 4 IRQ 5 Prefetch abort Lowest priority 6 Undefined Instruction Software interrupt Not All Exceptions Can Occur at Once Undefined Instruction and Software Interrupt are mutually exclusive since they each correspond to particular non overlapping decodings of the current instruction If a data abort occurs at the same time as and are enabled ie the CPSR s F flag is clear ARM920T enters the data abort handler and then im
461. the undefined instruction mechanism involves offering this instruction to any coprocessors which may be present and all coprocessors must refuse to accept it by driving CPA and CPB HIGH INSTRUCTION CYCLE TIMES This instruction takes 2S 11 1N cycles where 5 N and are defined as sequential S cycle non sequential N cycle and internal ASSEMBLER SYNTAX The assembler has no mnemonics for generating this instruction If it is adopted in the future for some specified use suitable mnemonics will be added to the assembler Until such time this instruction must not be used 3 58 ELECTRONICS 3C2410A INSTRUCTION SET EXAMPLES ARM INSTRUCTION SET The following examples show ways in which the basic ARM920T instructions can combine to give efficient code None of these methods saves a great deal of execution time although they may save some mostly they just save code USING THE CONDITIONAL INSTRUCTIONS Using Conditionals for Logical OR CMP Rn p BEQ Label CMP Rm q BEQ Label This can be replaced by CMP Rn p CMPNE Rm q BEQ Label Absolute Value TEQ Rn 0 RSBMI Rn Rn 0 Multiplication by 4 5 or 6 Run Time MOV Rc Ra LSL 2 CMP Rb 5 ADDCS Rc Rc Ra ADDHI Combining Discrete and Range Tests TEQ Rc 127 CMPNE Rc 1 MOVLS Rc ELECTRONICS If Rn p OR Rm q THEN GOTO Label If condition not satisfied try other test Test sign and 2 s complement if ne
462. they are SUBSRCPND 0X4A000018 R W Indicate the interrupt request status 0x00000000 0 The interrupt has not been requested 1 The interrupt source has asserted the interrupt request 0 Not requested 1 Requested INT_TC B 0 Not requested 1 Requested INTERR 8 0 Not requested 1 Requested 0 Not requested 1 Requested INTR 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested 0 Not requested 1 Requested o 0 Not requested 1 Requested ELECTRONICS 14 17 INTERRUPT CONTROLLER S3C2410A INTERRUPT SUB MASK INTSUBMSK REGISTER This register has 11 bits each of which is related to an interrupt source If a specific bit is set to 1 the interrupt request from the corresponding interrupt source is not serviced by the CPU note that even in such a case the corresponding bit of the SUBSRCPND register is set to 1 If the mask bit is 0 the interrupt request can be serviced INTSUBMSK 0 4 00001 R W Determine which interrupt source is masked The masked interrupt source will not be serviced 0 Interrupt service is available 1 Interrupt service is masked 0 Service available 1 Masked INT_TC B 0 Service available 1 Masked INTERR 8 0 Service available 1 Masked 0 Service available 1 M
463. thod of the EINT18 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered FLTEN17 Filter Enable for EINT17 0 Disable 1 Enable EINT17 6 4 Set the signaling method of the EINT17 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered FLTEN16 Filter Enable for EINT16 0 Disable 1 Enable EINT16 2 0 Set the signaling method of the EINT16 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered 9 24 ELECTRONICS 3 2410 PORTS EXTERNAL INTERRUPT FILTER REGISTER EINTFLTn The EINTFLTn controls the length of filter for 8 external interrupts EINT 23 16 emm 0660000942 nw err RW Reseed FLTCLK19 31 Filter clock of EINT19 0 PCLK 1 EXTCLK OSC_CLK Selected by OM pin EINTFLT19 30 24 Filter width of EINT19 FLTCLK18 23 Filter clock of EINT18 0 PCLK 1 EXTCLK OSC_CLK Selected by OM pin EINTFLT18 22 16 Filter width of EINT18 FLTCLK17 15 Filter clock of EINT17 0 PCLK 1 EXTCLK OSC_CLK Selected by OM pin EINTFLT17 14 8 Filter width of EINT17 FLTCLK16 7 Filter clock of EINT16 0 PCLK 1 EXTCLK OSC_CLK Selected by OM pin EINTFLT16 6 0 Filter width of EINT16 FLTCLK23 31 Filter clock of EINT23 0 PCLK 1 EXTCLK OSC_CLK Selected by OM pin EINTFLT23 30 24 Filt
464. ting TAGD bit DMA is configured properly The SPI receives 1byte data from card The SPI requests DMA service DMA receives the data from the SPI Write data OxFF automatically to SPTDATn Return to Step 4 until DMA count becomes 0 The SPI is configured as polling mode with SMOD bits and clearing TAGD bit If SPSTAn s REDY flag is set then read the last byte data NOTE Total received data DMA TC values the last data in polling mode Step 9 The first DMA received data is dummy and so the user can neglect it SPI Slave Rx Mode with Format B If the SPI slave Rx mode is activated and SPI format is set to format B then SPI operation will be failed The READY signal one of internal signals becomes high before the SPI_CNT reaches 0 Therefore in DMA mode DATA_READ signal is generated before the last data is latched ELECTRONICS 22 5 SPI INTERFACE 53 2410 Guide 1 DMA mode This mode cannot be used at SPI slave Rx mode with format B 2 Polling mode DATA_READ signal should be delayed by 1phase of SPICLK at SPI slave Rx mode with format B 3 Interrupt mode DATA_READ signal should be delayed 1 of SPICLK at SPI slave Rx mode with format SPI Data Receive Function Error Slave Receive Format B Mode SPI Value E 3 1831 1101 SPICLK i Data Latch READY Internal I gt Data Read DATA_READ vt Internal 22 6 ELECTRONICS
465. tion Get level one descriptor fault Page table entry fault Section No access 00 access 00 et Reserved 10 Check domain status Reserved 10 Client 01 Client 01 Manager 11 Section Page iii TUER E permission Violation Ars Chec Violation permission permissions permissions fault fault Physical address Figure 3 11 Sequence for Checking Faults ELECTRONICS 3 21 MMU ARM920T PROCESSOR ALIGNMENT FAULT If alignment fault is enabled A Bit in CP15 register 1 set the MMU will generate an alignment fault on any data word access the address of which is not word aligned or on any halfword access the address of which is not halfword aligned irrespective of whether the MMU is enabled or not An alignment fault will not be generated on any instruction fetch nor on any byte access NOTE If the access generates an alignment fault the access sequence will abort without reference to further permission checks TRANSLATION FAULT There are two types of translation fault section and page Section A section translation fault is generated if the level one descriptor is marked as invalid This happens if bits 1 0 of the descriptor are both 0 Page A page translation fault is generated if the level one descriptor is marked as invalid This happens if bits 1 0 of the descriptor are both 0 DOMAIN FAULT There are two types of domain fault section and page In both cases the
466. tion cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES STRH R4 R3 RO Store the lower 16 bits of R4 at the address formed by adding to R3 LDSB R2 R7 1 Load into R2 the sign extended byte found at the address formed by adding 1 to R7 LDSH R3 R4 R2 Load into the sign extended halfword found at the address formed by adding R2 to ELECTRONICS 4 21 THUMB INSTRUCTION SET 83 2410 FORMAT 9 LOAD STORE WITH IMMEDIATE OFFSET 15 14 13 12 11 10 6 5 3 2 0 ose a 2 0 Source Destination Register 5 3 Base Register 10 6 Offset Register 11 Load Store Flag 0 Store to memory 1 Load from memory 12 Byte Word Flad 0 Transfer word quantity 1 Transfer byte quantity Figure 4 10 Format 9 4 22 ELECTRONICS 3C2410A THUMB INSTRUCTION SET OPERATION These instructions transfer byte or word values between registers and memory using an immediate 5 or 7 bit offset The THUMB assembler syntax is shown in Table 4 10 Table 4 10 Summary of Format 9 Instructions STR Rd Rb Imm STR Rd Rb Imm Calculate the target address by adding together the value in Rb and Imm Store the contents of Rd at the address LDR Rd Rb LDR Rd Rb Calculate the source address by adding together the value in Rb and Imm Load Rd from the address STRB Rd Rb STRB Rd Rb Calc
467. tion is a normal interrupt caused by a LOW level on the nIRQ input IRQ has a lower priority than FIQ and is masked out when a FIQ sequence is entered It may be disabled at any time by setting the bit in the CPSR though this can only be done from a privileged non User mode Irrespective of whether the exception was entered from ARM or Thumb state an IRQ handler should return from the interrupt by executing SUBS PC R14_irg 4 Abort An abort indicates that the current memory access cannot be completed It can be signaled by the external ABORT input ARM920T checks for the abort exception during memory access cycles There are two types of abort e Prefetch abort occurs during an instruction prefetch e Data abort occurs during a data access If a prefetch abort occurs the prefetched instruction is marked as invalid but the exception will not be taken until the instruction reaches the head of the pipeline If the instruction is not executed for example because a branch occurs while it is in the pipeline the abort does not take place If a data abort occurs the action taken depends on the instruction type e Single data transfer instructions LDR STR write back modified base registers the Abort handler must be aware of this e The swap instruction SWP is aborted as though it had not been executed e Block data transfer instructions LDM STM complete If write back is set the base is updated If the instruction woul
468. to determine the shift amount Rs can be any general register other than R15 If this byte is zero the unchanged contents of Rm will be used as the second operand and the old value of the CPSR C flag will be passed on as the shifter carry output If the byte has a value between 1 and 31 the shifted result will exactly match that of an instruction specified shift with the same value and shift operation If the value in the byte is 32 or more the result will be a logical extension of the shift described above 1 N LSL by 32 has result zero carry out equal to bit 0 of Rm LSL by more than 32 has result zero carry out zero LSR by 32 has result zero carry out equal to bit 31 of Rm LSR by more than 32 has result zero carry out zero ASR by 32 or more has result filled with and carry out equal to bit 31 of Rm ROR by 32 has result equal to Rm carry out equal to bit 31 of Rm ROR by n where n is greater than 32 will give the same result and carry out as ROR by n 32 therefore repeatedly subtract 32 from n until the amount is in the range 1 to 32 and see above NOTE The zero in bit 7 of an instruction with a register controlled shift is compulsory a one in this bit will cause the instruction to be a multiply or undefined instruction ELECTRONICS 3 15 ARM INSTRUCTION SET S3C2410A IMMEDIATE OPERAND ROTATES The immediate operand rotate field is a 4 bit unsigned integer which specifies a shift operation on the 8
469. tomer s technical experts Samsung products are not designed intended or authorized for use as components in systems intended for surgical implant into the body for other applications intended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages expenses and reasonable attorney fees arising out of either directly or indirectly any claim of personal injury or death that may be associated with such unintended or unauthorized use even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product 3C2410A 200MHz amp 266MHz 32 Bit RISC Microprocessor User s Manual Revision 1 1 March 2007 Publication Number 21 S3 C2410A 032007 2007 Samsung Electronics All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electric or mechanical by photocopying recording or otherwise without the prior written consent of Samsung Electronics Samsung Electronics microcontroller business has been awarded full ISO 9001 certification B
470. tration procedure To control multi master IIC bus operations values must be written to the following registers Multi master IIC bus control register IICCON Multi master IIC bus control status register IICSTAT Multi master Tx Rx data shift register IICDS Multi master IIC bus address register IICADD When the IIC bus is free the SDA and SCL lines should be both at High level A High to Low transition of SDA can initiate a Start condition A Low to High transition of SDA can initiate a Stop condition while SCL remains steady at High Level The Start and Stop conditions can always be generated by the master devices A 7 bit address value in the first data byte which is put onto the bus after the Start condition has been initiated can determine the slave device which the bus master device has selected The 8th bit determines the direction of the transfer read or write Every data byte put onto the SDA line should be eight bits in total The bytes can be unlimitedly sent or received during the bus transfer operation Data is always sent from most significant bit MSB first and every byte should be immediately followed by an acknowledge ACK bit ELECTRONICS 20 1 IIC BUS INTERFACE 53 2410 Address Register Comparator IIC Bus Control Logic SCL PCLK ICCON IICSTAT 4 bit Prescaler Shift Register lt SDA Shift Register ICDS Data Bus
471. trigger for the external interrupt request and also configures the signal polarity To recognize the level interrupt the valid logic level on EXTINTn pin must be retained at least for 40ns because of the noise filter EINT 15 0 30 28 EINT7 Set the signaling method of the EINT7 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered EINT6 26 24 Set the signaling method of the EINT6 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered 5 22 20 Set the signaling method of the EINT5 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered EINT4 18 16 Set the signaling method of the EINT4 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered EINT3 14 12 Set the signaling method of the EINT3 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered EINT2 10 8 Set the signaling method of the EINT2 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered EINT1 6 4 Set the signaling method of the EINT1 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered EINTO 2 0 Set the signaling method
472. ual measurement of X position or Y position 00 No operation mode 01 X position measurement 10 Y position measurement 11 Waiting for Interrupt Mode NOTE In Auto mode ADCTSC register should be reconfigured before starting read operation XM_SEN 5 Select output value of XMON 0 XMON output is 0 XM Hi Z 1 XMON output is 1 XM GND Select output value of nXPON 1 0 nXPON output is 0 XP External voltage 1 nXPON output is 1 XP is connected with AIN 7 16 8 ELECTRONICS 3C2410A ADC AND TOUCH SCREEN INTERFACE ADC START DELAY ADCDLY REGISTER ADCDLY 0x58000008 ADC start or interval delay register OxOOff DELAY 15 0 1 Normal Conversion Mode Separate X Y Position Conversion Mode OOff and Auto Sequential X Y Position Conversion Mode X Y Position Conversion Delay Value 2 Waiting for Interrupt Mode When Stylus down occurs in Waiting for Interrupt Mode this register generates Interrupt signal INT TC at intervals of several ms for Auto X Y Position conversion NOTE Do not use Zero value 0x0000 NOTES 1 Before ADC conversion Touch screen uses X tal clock or EXTCLK Waiting for Interrupt Mode 2 During ADC conversion PCLK is used ELECTRONICS 16 9 ADC AND TOUCH SCREEN INTERFACE 53 2410 ADC CONVERSION DATA ADCDATO REGISTER ADCDATO 0x5800000C n ADC conversion data register UPDOWN 15 Up or down state of Stylus at Waiting for Interrupt Mode 0 Stylus
473. uction Set Opcodes sse 4 3 4 2 Summary of Format 1 Instructions a 4 5 4 3 Summary of Format 2 4 7 4 4 Summary of Format 4 9 4 5 Summary of Format 4 4 11 4 6 Summary of Format 5 Instructions asss 4 13 4 7 Summary of PC Relative Load Instruction 1 4 16 4 8 Summary of Format 7 Instructions aa 4 19 4 9 Summary of format 8 instructions enne 4 20 4 10 Summary of Format 9 Instructions a 4 23 4 11 Halfword Data Transfer Instructions sss 4 24 4 12 SP Relative Load Store 1 4 26 4 13 koad Address toate 4 28 4 14 The ADD SP Instruction 4 30 4 15 PUSH and 4 31 4 16 The Multiple Load Store Instructions 4 33 4 17 The Conditional Branch Instructions sse 4 34 4 18 Ihe SWI etc telo 4 36 4 19 Summary of Branch Instruction n nn 4 37 4 20 MISSE cR 4 39 5
474. ue 20 and the result is 200 which is correctly represented as OxFFFFFF38 If the Operands Are Interpreted as Unsigned Operand A has the value 4294967286 operand B has the value 20 and the result is 85899345720 which is represented as 0x13FFFFFF38 so the least significant 32 bits are OxFFFFFF38 Operand Restrictions The destination register Rd must not be the same as the operand register Rm R15 must not be used as an operand or as the destination register All other register combinations will give correct results and Rd Rn and Rs may use the same register when required ELECTRONICS 3 23 ARM INSTRUCTION SET 53 2410 CPSR FLAGS Setting the CPSR flags is optional and is controlled by the S bit in the instruction The N Negative and Z Zero flags are set correctly on the result N is made equal to bit 31 of the result and Z is set if and only if the result is zero The C Carry flag is set to a meaningless value and the V oVerflow flag is unaffected INSTRUCTION CYCLE TIMES MUL takes 15 ml and MLA 15 m 1 I cycles to execute where S and are defined as sequential S cycle and internal respectively m The number of 8 bit multiplier array cycles is required to complete the multiply which is controlled by the value of the multiplier operand specified by Rs Its possible values are as follows 1 If bits 32 8 of the multiplier operand are all zero or all one 2 If bits 82 16 of the multiplier ope
475. ue to 0x12210 Refer to a sample program source for the latest value of this register DITHMODE Bit Description Initial state DITHMODE 18 0 Use one of following value for your LCD 0x00000 0x00000 or 0x12210 ELECTRONICS 15 35 LCD CONTROLLER S3C2410A Temp Palette Register TPAL 0X4D000050 R W TFT Temporary palette register 0x00000000 This register value will be video data at next frame TPALEN 24 Temporary palette register enable bit 0 Disable 1 Enable TPALVAL 23 0 Temporary palette value register 0x000000 TPALVAL 23 16 RED TPALVAL 15 8 GREEN TPALVAL 7 0 BLUE 15 36 ELECTRONICS 53 2410 LCD CONTROLLER LCD Interrupt Pending Register LCDINTPND 0X4D000054 Indicate the LCD interrupt pending register INT_FrSyn 1 LCD frame synchronized interrupt pending bit 0 The interrupt has not been requested 1 The frame has asserted the interrupt request INT_FiCnt LCD FIFO interrupt pending bit 0 The interrupt has not been requested 1 LCD FIFO interrupt is requested when LCD FIFO reaches trigger level LCD Source Pending Register LCDSRCPND 0X4D000058 Indicate the LCD interrupt source pending register Oo 0x0 INT_FrSyn 1 LCD frame synchronized interrupt source pending bit 0 The interrupt has not been requested 1 The frame has asserted the interrupt request INT_FiCnt LCD FIFO interrupt source pending bit 0 The interrupt has not been requested 1 LCD FIF
476. ulate the target address by adding together the value in Rb and Imm Store the byte value in Rd at the address LDRB Rd Rb lmm LDRB Rd Rb lmm Calculate source address by adding together the value in Rb and Imm Load the byte value at the address into Rd NOTE For word accesses 0 the value specified by Imm is a full 7 bit address but must be word aligned ie with bits 1 0 set to 0 since the assembler places lmm gt gt 2 in the Offset5 field INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4 10 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction EXAMPLES LDR R2 R5 116 Load into R2 the word found at the address formed by adding 116 to R5 Note that the THUMB opcode will contain 29 as the Offset5 value STRB R1 80 13 Store the lower 8 bits of R1 at the address formed by adding 13 to RO Note that the THUMB opcode will contain 13 as the Offset5 value ELECTRONICS 4 23 THUMB INSTRUCTION SET S3C2410A FORMAT 10 LOAD STORE HALFWORD 15 14 13 10 6 5 32 0 12 11 _ 2 0 Source Destination Register 5 3 Base Register 10 6 Immediate Value 11 Load Store Flag 0 Store to memory 1 Load from memory Figure 4 11 Format 10 OPERATION These instructions transfer halfword values between a Lo register and memory Address
477. ultiply by 4 11 1 45 Multiply by 9 Multiply by 5 9 45 ELECTRONICS 3C2410A LOADING A WORD FROM AN UNKNOWN ALIGNMENT BIC LDMIA AND MOVS MOVNE RSBNE ORRNE ELECTRONICS Rb Ra 3 Rb Rd Rc Rb Ra 3 Rb Rb LSL 3 Rd Rd LSR Rb Rb Rb 32 Rd Rd Re LSL Rb ARM INSTRUCTION SET Enter with address in Ra 32 bits uses Rb Rc result in Rd Note d must be less than c e g 0 1 Get word aligned address Get 64 bits containing answer Correction factor in bytes how in bits and test if aligned Produce bottom of result word if not aligned Get other shift amount Combine two halves to get result 3 63 ARM INSTRUCTION SET S3C2410A NOTES 3 64 ELECTRONICS 3C2410A THUMB INSTRUCTION SET THUMB INSTRUCTION SET THUMB INSTRUCTION SET FORMAT The thumb instruction sets are 16 bit versions of ARM instruction sets 32 bit format The ARM instructions are reduced to 16 bit versions Thumb instructions at the cost of versatile functions of the ARM instruction sets The thumb instructions are decompressed to the ARM instructions by the Thumb decompressor inside the ARM920T core As the Thumb instructions are compressed ARM instructions the Thumb instructions have the 16 bit format instructions and have some restrictions The restrictions by 16 bit format is fully notified for using the Thumb instructions ELECTRONICS 4 1 THUMB INSTRUCTION SET 53 2410 FORMAT SUMMARY The THUMB instruction set formats are
478. un preserved entries in the TLB Invalidate TLB single entry functions invalidate any TLB entry corresponding to the modified virtual address given in Rd regardless of its preserved state See Register 10 TLB lock down register on page 2 21 Invalidate TLB single entry using MVA MVA format MCR p15 0 Rd c8 c5 1 Figure 2 4 shows the modified virtual address format used for operations on single entry TLB lines using register 8 Figure 2 4 Register 8 MVA Format 2 18 ELECTRONICS ARM920T PROCESSOR PROGRAMMER S MODEL REGISTER 9 CACHE LOCK DOWN REGISTER Register 9 is the cache lock down register The cache lock down register is OxO on reset The cache lock down register allows software to control which cache line in the ICache or DCache respectively is loaded for a linefill and to prevent lines in the ICache or DCache from being evicted during a linefill locking them into the cache There is a register for each of the ICache and DCache the value of opcode 2 determines which cache register to access opcode 2 0x0 causes the DCache register to be accessed opcode 2 0x1 causes the ICache register to be accessed The Opcode 1 and CRm fields should be zero Reading CP15 register 9 returns the value of the cache lock down register which is the base pointer for all cache segments NOTE Only bits 31 26 are returned Bits 25 0 are unpredictable Writing CP15 register 9 updates the cache lock down register both the base and
479. upt request pins the interrupt controller requests FIQ or IRQ interrupt of the ARM920T core after the arbitration procedure The arbitration procedure depends on the hardware priority logic and the result is written to the interrupt pending register which helps users notify which interrupt is generated out of various interrupt sources SUBSRCPND SUBMASK SRCPND DG Request sources without sub register Figure 14 1 Interrupt Process Diagram ELECTRONICS 14 1 INTERRUPT CONTROLLER S3C2410A INTERRUPT CONTROLLER OPERATION F bit and I bit of Program Status Register PSR If the F bit of PSR in ARM920T CPU is set to 1 the CPU does not accept the Fast Interrupt Request FIQ from the interrupt controller Likewise If I bit of the PSR is set to 1 the CPU does not accept the Interrupt Request IRQ from the interrupt controller So the interrupt controller can receive interrupts by clearing F bit or l bit of the PSR to 0 and setting the corresponding bit of INTMSK to 0 Interrupt Mode The ARM920T has two types of Interrupt mode FIQ or IRQ All the interrupt sources determine which mode is used at interrupt request Interrupt Pending Register The S3C2410A has two interrupt pending resisters source pending register SRCPND and interrupt pending register INTPND These pending registers indicate whether or not an interrupt request is pending When the interrupt sources request interrupt service the corresp
480. us master or as a slave for production test The ARM920T also has a TrackingICE mode which allows an approach similar to a conventional ICE mode of operation ELECTRONICS 1 1 INTRODUCTION ARM920T PROCESSOR PROCESSOR FUNCTIONAL BLOCK DIAGRAM Shows the functional block diagram of the ARM920T External Instruction Instruction IPA 31 0 Coprocessor MMU Interface IMVA 31 0 ARM9TDMI AMBA Interface Processor Core Bus Integral EmbeddedICE Interface Write Buffer DPA 31 0 Write Back PA TAG RAM WBPA 31 0 DINDEX 31 0 Figure 1 1 ARM920T Functional Block Diagram 1 2 ELECTRONICS ARM920T PROCESSOR PROGRAMMER S MODEL Appendix 2 PROGRAMMER S MODEL ABOUT THE PROGRAMMER S MODEL ARM920T incorporates the ARM9TDMI integer core which implements the 4 architecture It executes the ARM and Thumb instruction sets and includes Embedded ICE JTAG software debug features The programmer s model of the 920 consists of the programmer s model of the ARM9TDMI with the following additions and modifications The ARM920T incorporates two coprocessors 14 which allows software access to the debug communications channel The registers defined in CP14 are accessible with MCR and MRC instructions The system control coprocessor CP15 which provides additional registers that are used to configure and control the caches MMU protection system the clocking mode and other system options of th
481. us register 1 0x190 a EP out control status register 2 0x194 EP out write count register 1 0x198 EP out write count register 2 0x19C 13 4 ELECTRONICS 53 2410 USB DEVICE FUNCTION ADDRESS REGISTER FUNC_ADDR_REG This register maintains the USB device controller address assigned by the host The Micro Controller Unit MCU writes the value received through a SET_ADDRESS descriptor to this register This address is used for the next token Reset Value FUNC_ADDR_REG 0x520001 40 L R W Function address register 0x00 0x52000143 B byte ADDR_UPDATE 7 R R Set by the MCU whenever it updates the SET CLEAR FUNCTION_ADDR field in this register This bit will be cleared by USB when DATA END bit in EPO CSR register FUNCTION ADDR 6 0 R W The MCU write the unique address assigned by host to this field ELECTRONICS 13 5 USB DEVICE 53 2410 POWER MANAGEMENT REGISTER PWR_REG This register acts as a power control register in the USB block Reset Value PWR_REG 0x52000144 L R W Power management register 0x00 0x52000147 B byte PWR ADDR Bit MCU 74 Set by the USB if reset signaling is received R from the host This bit remains set as long as MCU_RESUME 2 RW SUSPEND MODE SUSPEND_EN reset signaling persists on the bus Set by the MCU for MCU Resume CLEAR The USB generates the resume signaling duri
482. used to store status information Register 14 is used as the subroutine link register This receives a copy of R15 when a Branch and Link BL instruction is executed At all other times it may be treated as a general purpose register The corresponding banked registers R14 R14 R14 fig R14 abt and R14 und are similarly used to hold the return values of R15 when interrupts and exceptions arise or when Branch and Link instructions are executed within interrupt or exception routines Register 15 holds the Program Counter PC In ARM state bits 1 0 of R15 are zero and bits 31 2 contain the PC In THUMB state bit 0 is zero and bits 31 1 contain the PC Register 16 is the CPSR Current Program Status Register This contains condition code flags and the current mode bits FIQ mode has seven banked registers mapped to R8 14 R8 fig R14 fiq In ARM state many FIQ handlers do not need to save any registers User IRQ Supervisor Abort and Undefined each have two banked registers mapped to R13 and R14 allowing each of these modes to have a private stack pointer and link registers ELECTRONICS 2 3 PROGRAMMER S MODEL 2 4 System amp User S3C2410A ARM State General Registers and Program Counter FIQ 222 22 N R8_fiq R9 10 11 12 13 14 R15 Ro R R6 R6 R7 DX R8 PRI D
483. uty cycle frequency and polarity e Dead zone generation e Supports external clock sources RTC Real Time Clock e Full clock feature second minute hour date day month and year 32 768 KHz operation Alarm interrupt Time tick interrupt General Purpose Input Output Ports 24external interrupt ports e multiplexed input output ports UART e 3 channel UART with DMA based or interrupt based operation e Supports 5 bit 6 bit 7 bit or 8 bit serial data transmit receive Tx Rx e Supports external clocks for the UART operation UEXTCLK Programmable baud rate e Supports IrDA 1 0 Loopback mode for testing Each channel has internal 16 byte Tx FIFO and 16 byte Rx FIFO ELECTRONICS PRODUCT OVERVIEW DMA Controller 4 ch DMA controller e Supports memory to memory IO to memory memory to IO and IO to IO transfers e Burst transfer mode to enhance the transfer rate A D Converter amp Touch Screen Interface e 8 ch multiplexed ADC e Max 500KSPS and 10 bit Resolution LCD Controller STN LCD Displays Feature e Supports 3 types of STN LCD panels 4 bit dual scan 4 bit single scan 8 bit single scan display type e Supports monochrome mode 4 gray levels 16 gray levels 256 colors and 4096 colors for STN LCD e Supports multiple screen size e Typical actual screen size 640x480 320x240 160x160 and others e Maximum virtual screen size is 4 Mbytes e Maximum virtual sc
484. ve been overwritten before the abort occurred The data abort trap is taken when the load multiple has completed and the system software must undo any base modification and resolve the cause of the abort before restarting the instruction INSTRUCTION CYCLE TIMES Normal LDM instructions take nS 1N 11 and PC takes n 1 S 2N 11 incremental cycles where S N and are defined as sequential S cycle non sequential N cycle and internal respectively STM instructions take n 1 S 2N incremental cycles to execute where nis the number of words transferred 3 44 ELECTRONICS 3C2410A ARM INSTRUCTION SET ASSEMBLER SYNTAX lt LDM STM gt cond lt FD ED FA EA IA IB IDA DB gt Rn lt Rlist gt where Two character condition mnemonic See Table 3 2 Rn An expression evaluating to a valid register number lt Rlist gt A list of registers and register ranges enclosed in e g RO R2 R7 R10 If present requests write back W 1 otherwise W 0 4 If present 5 bit to load the CPSR along with the or force transfer of user bank when in privileged mode Addressing Mode Names There are different assembler mnemonics for each of the addressing modes depending on whether the instruction is being used to support stacks or for other purposes The equivalence between the names and the values of the bits in the instruction are shown in the following table 3 6 Table 3 6 A
485. x4E000008 NAND flash address set register Coos I ms 2 7 0 NAND flash memory address value NAND FLASH DATA NFDATA REGISTER NFDATA 0x4E00000C NAND flash data register Kwa mew 7 0 NAND flash read program data value In case of write Programming data In case of read Read data ELECTRONICS 6 7 NAND FLASH CONTROLLER S3C2410A NAND FLASH OPERATION STATUS NFSTAT REGISTER NFSTAT 0x4E000010 R NAND flash operation status em RnB NAND flash memory ready busy status This signal is checked through R nB pin 0 NAND flash memory busy 1 NAND flash memory ready to operate NAND FLASH ECC NFECC REGISTER NFECC 0x4E000014 R NAND flash ECC Error Correction Code register ECC2 23 16 Error Correction Code 2 ECC1 15 8 Error Correction Code 1 ECCO 7 0 Error Correction Code 0 Known Problems e Problem NAND flash controller can t be accessed by DMA e Solution Instead of DMA use LDM STM Instructions like our boot loader example code 6 8 ELECTRONICS 53 2410 CLOCK 8 POWER MANAGEMENT CLOCK amp POWER MANAGEMENT OVERVIEW The clock amp power management block consists of three parts clock control USB control and power control The Clock control logic in S8C2410A can generate the required clock signals including FCLK for CPU HCLK for the AHB bus peripherals and PCLK for the APB bus peripherals The 53 2410 has two Phase Locked Loops P
486. y select 2 00 16fs 01 32fs 10 48fs 11 N A NOTES 1 The IISMOD register is accessible for each halfword and wordunit using STRH STR and LDRH LDR instructions or short int int type pointer in Little Big endian mode 2 Li HW W Little HalfWord Word Bi HW W Big HalfWord Word 21 6 ELECTRONICS 53 2410 IIS BUS INTERFACE IIS PRESCALER IISPSR REGISTER IISPSR 0x55000008 Li HW Li W Bi W m IIS prescaler register 0x5500000A Bi HW Prescaler control A Data value 0 31 Note Prescaler A makes the master clock that is used the internal block and division factor is N 1 Prescaler control B Data value 0 31 Note Prescaler B makes the master clock that is used the external block and division factor is N 1 NOTES 1 IISPSR register is accessible for each byte halfword and word unit using STRB STRH STR and LDRB LDRH LDR instructions or char short int int type pointer in Little Big endian mode 2 Li HW W Little HalfWord Word Bi HW W Big HalfWord Word ELECTRONICS 21 7 IIS BUS INTERFACE 53 2410 IIS FIFO CONTROL IISFCON REGISTER IISFCON 0x5500000C Li HW Li W Bi W ELM 15 FIFO interface register 0x5500000E Bi HW Transmit FIFO access mode 15 0 Normal select 1 Receive FIFO access mode 14 0 Normal select 1 Transmit FIFO 13 0 Disable 1 Enable Receive FIFO 12 0 Disable 1 Enable Transmit FIFO data count 11 6 Data count value
487. y system Use of R15 If Rn is R15 the value used will be the address of the instruction plus 8 bytes Base write back to R15 must not be specified DATA ABORTS If the address is legal but the memory manager generates an abort the data trap will be taken The write back of the modified base will take place but all other processor state will be preserved The coprocessor is partly responsible for ensuring that the data transfer can be restarted after the cause of the abort has been resolved and must ensure that any subsequent actions it undertakes can be repeated when the instruction is retried Instruction cycle times Coprocessor data transfer instructions take n 1 S 2N bl incremental cycles to execute where n The number of words transferred b The number of cycles spent in the coprocessor busy wait loop 5 are defined as sequential S cycle non sequential N cycle and internal respectively 3 54 ELECTRONICS 3C2410A ARM INSTRUCTION SET ASSEMBLER SYNTAX lt LDC STC gt cond L p cd lt Address gt LDC Load from memory to coprocessor STC Store from coprocessor to memory L When present perform long transfer N 1 otherwise perform short transfer N 0 Two character condition mnemonic See Table 3 2 p The unique number of the required coprocessor cd An expression evaluating to a valid coprocessor register number that is placed in the field lt Address gt
488. z fast 400 SCL high level pulse width tscLHIGH std 4 0 uS fast 0 6 SCL low level pulse width tecLLOW std 4 7 us fast 1 3 Bus free time between STOP and START std 4 7 fast 1 3 START hold time tsTARTS std 4 0 us fast 0 6 SDA hold time tspAH std 0 std fast uS fast 0 0 9 SDA setup time tspas std 250 ns fast 100 STOP setup time teroPH std 4 0 us fast 0 6 NOTES Std means Standard Mode and fast means Fast Mode 1 data hold time tSDAH is minimum Ons IIC data hold time is minimum Ons for standard fast bus mode in IIC specification v2 1 Please check the data hold time of your device if it s 0 nS or not 2 controller supports only bus device standard fast bus mode C bus device Table 24 14 SD MMC Interface Transmit Receive Timing Constants Vpp 1 8 0 15 2 0 V 0 1 V TA 40 to 85 C 3 3V 0 3V SD Command Dely ime ______ 05 m _ SD Command input Setup time 152 142 m SD Command input Hold time 01 ns ELECTRONICS 24 35 ELECTRICAL DATA S3C2410A Table 24 15 SPI Interface Transmit Receive Timing Constants Vpp 1 8V 0 15 2 0 V 0 1 V 40 to 85 C 3 3V 0 3V Symbol 2707 6 tsPIMIH 1 Note CPOL 0 CPHA 0 CPOL 1 CPHA 1 CPOL 1 CPHA 0 CPOL 0 CPHA 1 Table 24 16 USB Electrical Specifications 1

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