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1. Ete ECL TRIGGER INTERFACE Sdt Sle PERES a ES ES a1 veci vote GND BA ME B DEVICE TYPE REGISTER A3 5 Py 1 4 y A vin YO nciou238H RP8 hu m ECLTRGINO O im Ton B2 sur EL i 5 Pg 4 EW 50 E Kel es ECLTRGINI O a RPIE see ELS 13 o ve 5 2 1 ie cour 2 i Si 50 G ow e L d an Zum tt apre Ti 5 2 3 1 DBLI40 i 8 Li 14 3 ee Ya 15 z 4 16 DBLI30 S 1 16 13 a A3 3 14 L ad 502 veer voce GND la ENEE VTT V VEB 4 ms a gt 5 y5 i DSEDHI 12 ECLTRGO OF 2 D D I li d Ii e3 DOM N a ii BCLTRGOUTO 10 z 8 Se z 12 DBD90 W 1OH1168E 3 8 a va LI DBI80 w BRB a i ECLTRGI O82 10 n ka RP 4 2K 74HCT541 Ye E ECLTRGOUT GND ves A 2 4 l i E EE 50 lk 3 4 s e z e s 10 BI m I CR2ZV Ler al qu L 13 WA RPIB RP Ze A vaf m 16 1 i x m He DBIZI VIT V
2. DB DB15 INTERNAL DATA BUS DBQ gt DB15 MODID TO ee p ___ STATUS e REGISTER D LOGICAL DEVICE BASE 0 l SE READA DBG LAGTAIS gs ADDRESS 0 255 DEVDEPO YY ki DEVDEP 1 d AMQ AMS V DEVDEP2x MFR ID B gen SC ADDRESS DEVDEP3 DEVICE CLASS 1D P D yi DBIS LA gt DECODING s ADDRESS MODE REGISTER LWORD gt ENABLE BA y BAS BA4 REGISTER zan LATAS gs DECODI G BASE 2 N READ BASE 4 Y Y I LATCH ADDRESS STATUS amp ATAS SMATCH MODEL e DEVICE 15 y BG 2 3 INX aI es MEM AVAIL TYPE Ti REGISTER E V IRQ ACKNOWLEDGE 2 pat LEVEL SELECT X BG G 3 OUTx 1 HABENS WRITEX I YY i bus DSgx DBEN ACKADDR CADDR P197 A a MODID 0 15 L B ASx TP195 oo py A en DTACK STATUS D AA ou E p C INTERRUP P187 REGISTER A SYSFAILX CONTROL Si 5 T e D ACK INX PAL P184 CLEAR CLOCK A gt Waysa ra TACKOUTY STATUSWR A RQ B LEVEL
3. DN EH BER eds ab s dl 9041 08d HI m an BER lyd E1490 66511 Component Locator Rev D cedi cecal D i kr LI A Agilent E1490C Schematics Appendix B Pa CARDADRX n G LHORDX 5 6 ACK L Tacks QAL Det ant E ATEN PO ul8 Lists ALIOU 4 74HCT14 AUI gt PI g Un p ANK d ACSI 8 BANK DECODERS AL130 E d D i a BA La uz N EN cl ALII DR CARD BOUNDRY DET
4. Figure 3 3 Data Bus Control Control 0 7 Bits Bits 2 3 4 7 o E E i OOM ONNN keu E J Control Bits Ge m 9 8 15 u ay Doto Bus i e 8 15 3 g On mati x o Figure 3 3 Control Register Access Points Table 3 3 Control Register Bit Definitions Data Bit s Definitions CRO 1 Reset the module User defines reset actions CR1 1 inhibit setting of SYSFAIL if Reset 1 safe CR2 CR14 Device Dependent user assignable CR15 1 Enable access to A24 A32 Registers 0 Disable 54 Using the Agilent E1490C Chapter 3 Writing to the To write to the Control Register from the backplane data lines you must Control Register implement the following signal and control lines 1 Address the module correctly by placing the data shown in Table 3 4 on the backplane address lines Table 3 4 Backplane Address Lines Control Register Lines Data Required Lines A1 A3 Must be set low high low 010 to select the BASE 4 enable line BASE 4 set low provides an enable function at U2B for Control Register drivers U15 U16 to be clocked by the LATCH pulse see Table 2 2 on page 34 Lines A4 A5 Must both be low 0 to enable the 3 to 8 line decoder U21 Lines A6 A13 Must equal the logical address of the module as set on DIP switch SW1 Lines A14 A15 Must always be set high 1 t
5. IN WA Ooo OTE Caio O o oa ota ININ 01 02 00 NY 4S Ne NI AIAN AANI Ooa BER BER 8 SED COM 8 SET 3 COM K101 J K102 71 a RST 71 o RST 6 SET 6 SET RESET RESET 2 12V 2 12V 0 0 1 12V 12V 3 SEN 3 COM 8 SEL COM 7 ON 4 RST 7 K104 4 RST dog o o 6 5 SET 6 5 SET RESET RESET 2 2 10 E 2 12 1 112V 9 1 E12V 8 SE 3 COM 8 SE 3 COM 7 105 4 RST 7 SEW 4 RST 6 5 SET 6 5 SET RESET RESET Z 412v Z 2 riav 9 ai Lo 0 SS BER 8 3 COM 8 3 COM 7 107 4 RST 7 KIOBA sb RST 6 5 SET 6 5 SET RESET RESET 2 19 3 2 12 0 0 12V BER 8 SET 3 COM 8 SET 3 COM 7 109 VV 4 RST 7 K110 A la RST 6 5 SET 6 5 SET RESET RESET B 2 Loy B 2 12V 0 0 12V 12V 8 SET 3 COM 8 SET 3 COM Zei K112 7 L4 RST 7 LA RST 6 5 SET 6 5 SET RESET RESET 2 2 49V 2 12 E Loy B La 8 Sch 3 COM 8 SCH 3 COM 7 ASIAN 4 RST 7 KITA 4 RST 6 5 SET 6 5 SET RESET RESET 2 2 adv piz B fm L 42V S BB ae 8 P 3 COM 8 3 COM KISA K116 7 4 R
6. NI Va DI SEI Sg B H 1 ISI Si e e 8 e nme H H eo a Hi aa Hu SIL GI S SI Sl AS i E 3B H e Eye 7 Terminal Module Power Supply Ground Bus Oe HUE i D I YO o o TO O T2 li MTT TTT A A ANT A AER Ee E Ee e S 8 sodass H 8 3 8 EE EES 8 88833880 TTE 7 8 s b s e 8 H 3 kose 3 Power Supply Ground Bus Top Cover 000000000 o 000000000 00000000 000000000 o 00000000000 000000000000000000000000000000000000000000 000000000 o o o 0000000000 000000000000000000000 000000 o 00000000000 60000000000 000000000 O A Removed 000000000000000000000000000000 ooo o o 0000000000000000000000000000000000000000
7. e Reading the Status Register Reading ID and Device Type Registers Writing Data to the Control Register Control Register Bit Definitions Writing to the Control Register Using Interrupts e EE s w eS me A ue eoo Configuring for Interrupts Generating Interrupt Requests Resetting the Module Hardware Reset Qu ele Software Reset d noua ee EE A eee som ra ad Detecting Errors os Eu WEE Rer RU RUD de ani e Using OtherPowerSupplies llle Example Program Reading the Registers Register Definitions w 22e A SU T u a Reading the ID Register o oo aaa Reading the Device Type Register Writing to the Control Register llle Reading Writing to Custom Registers Appendix A Agilent E1490C Breadboard Specifications Specifications Table Appendix B Agilent E1490C Parts List Component Locator and Schematics Backplane Interface Component Locator Backplane Interface Schematic e e e e on e e e e e e c e e e o c e a an e e e e on 2 Agilent E1490C User s Manual Contents Certification Agilent Technologies certifies that this product met its published specifications at the time of shipment from the factory Agilent Technologies further certifies that
8. a m o gt m m x 4HCT841 O DB 15 0 Figure 2 22 ID Register Table 2 4 shows the ID Register bit definitions Table 2 5 shows possible Addressing Modes and Table 2 6 shows the Device Classes as defined in the VXIbus System Specification Section C 2 1 1 2 Table 2 4 ID Register Bit Definitions Data Bits Definitions DBO DB11 VXI Manufacturer ID Code Range 0 to 4095 DB12 DB13 Addressing Mode see Table 2 5 DB14 DB15 VXIbus Device Classification see Table 2 6 Chapter 2 Configuring the Agilent E1490C 37 Each bit in the ID Register is normally pulled high 1 by RP5 and RP6 The bits can be reconfigured low by closing the appropriate switch SP2 and SP3 If no switches are closed that is all bits are high or 1 s from Tables 2 5 and 2 6 the module will be defined as a register based and A16 device and will have a Manufacturer ID code of 4095 Agilent Technologies Table 2 5 Breadboard Addressing Mode Value Addressing Mode 00 A16 24 01 A16 32 10 RESERVED 11 A16 Only Table 2 6 Breadboard Device Classification Value Device Class 00 Memory 01 Extended 10 Message Based 11 Register Based See Chapter 3 for additional information on using the ID Register Refer to the VXIbus System Specification Section C 2 1 1 2 for detailed information concerning ID Register implementation restr
9. Chapter 1 Introduction 11 Notes 12 Introduction Chapter 1 Chapter 2 Configuring the Agilent E1490C This chapter contains a detailed hardware description of the breadboard module and discusses the backplane interface circuitry It also shows a sample application to control sixteen relays on the module Chapter contents are e Handling Precautions Page 13 e Hardware Description Page 14 e Module Dimensions Page 17 e Cooling Requirements Page 22 e Setting the Logical Address Switch Page 23 e Setting the Interrupt Priority Page 24 e Installing the Breadboard in a Mainframe Page 25 e Terminal Modules Page 26 e Wiring a Terminal Module Page 29 e Attaching a Terminal Module to the Breadboard Page 31 e Backplane Interface Circuitry Page 32 e Custom Circuitry 0 ee eee Page 47 Handling Precautions WARNING WARNING CAUTION WARNINGS CAUTIONS and guidelines to reduce the risk of static discharge damage to the Agilent E1490C follow SHOCK HAZARD Only qualified service trained personnel who are aware of the hazards involved should install remove or configure any module Before you touch any installed module turn off all power to the main
10. iu re LJ O O D DDD DDD DID DO DI DO DI D 00D DDD DD DO 0X2 DID DI Q 11213 6 7 8 9 10 1111213 14115116 A shoro2122 2425 31 O d LILIL TIILILILILILILIITIIL EAT LILILI LJ LITLIETELFLILEFIILEITILELUCHLILLCIITEFEI L CO DD D DD DD DO DD C2 2 C2 DODODDODOD DAD 112 3 41 51 6 71 8 9 110 11 12 1 311 4 15 16 B 1718 1920 2122235 24 252 29130 31 32 ri TTT LJ UNO TO UNO OO OU CJ LI CJ COUTO TOO OU OO DO CJ Fur H H WS DD DIDDDD DI CO C2 ABABA C2 2 DID DD DO DO DO CA C2 C2 GH 1 2 3 4 5 6 7 8 9 10 11112113N 4115116 C 171819202 1 22 23 24 25 26 27 28 29 30 31 32 LILILILILPDPLUCHLITLIHLILILITJILITLIHET LI LIII ENHLTLIITILILTHELPLILITILIILZILUITI KO O O FA LI NOS O A A f S ef f li Figure 2 15 Agilent E1490C Standard Screw type Terminal Module 26 Configuring the Agilent E1490C Chapter 2 Terminal Module Option A3E can be ordered if a crimp and insert terminal module is desired Option A3E Thisallows you to crimp connectors onto wires which are then inserted directly into the breadboard s mating connector Refer to the schematics in Appendix B to make the connections Crimp and Insert The following accessories are necessary for use with crim
11. mm H30 t t t 0 2 4 6 Liters Second Figure 2 11 Pressure Drop vs Air Flow 22 Configuring the Agilent E1490C Chapter 2 Setting the Logical Address Switch The logical address switch LADDR factory setting is 232 Valid addresses are from 1 to 255 Refer to Figure 2 12 for switch position information S Logical Address Es Switch Location nae 28 D 64 e 32 8 32 644 128 232 pl O 6 Si WLG 8 E NEO 4 M C 2 o Oj 4 Ooms a Lu Lu EIS a O O lao ll CLOSED Switch Set To 1 ON OPEN Switch Set To Q OFF Figure 2 12 Setting the Logical Address Chapter 2 Configuring the AgilentE1490C 23 Setting the Interrupt Priority For most applications where the breadboard module is installed in an Agilent 75000 Series C mainframe the interrupt priority jumper does not have to be moved This is because the V XIbus interrupt lines have the same priority and interrupt priority is established by installing modules in slots numerically closest to the command module Thus slot 1 has a higher priority than slot 2 slot 2 has a higher priority than slot 3 and so on Refer to Figure 2 13 to change the interrupt priority You can select eight different interrupt priority levels Level 1 is the lowest priority and Level 7 is the highest priority Level X disables the interrupt The module s factory setting is Level 1 To change re
12. Agilent 75000 SERIES C Agilent E1490C C Size VXIbus Register Based Breadboard Module User s Manual XE Agilent Technologies Sie m PE UE Contents Agilent E1490C User s Manual Warranty cle Re c d ou RU qeu Q ten as QS une A Qu gu 3 WARNINGS e E E amp ee ee eos oe eee E Ee te Beet ee ee 4 Safety Symbols yc gach ea EES x REA AR Pee PAG YY n wol 4 UserNOteS Sosa doe qo ES xx Rue E ER RR CS USOS REO E w RES 5 Chapter 1 Introduction o s ss sss ss ss es 7 Manual CODteDIS 255 is sinus sus RR E P REE ORG DG Eder d P Suq 7 Specification Compliance Warranty eee eee ee 7 Agilent E1490C Description 8 Breadboard Module Features 8 Backplane Interface Features een 8 Agilent EI490C Hardware Features ee ee 11 Chapter 2 Configuring the Agilent E1490C leen 13 Handling Precautions e 13 Reducing Risk of Static Discharge Damage 14 Hardware Description 14 Backplane Connections e 16 Backplane Connector Pins o e 16 Terminal Module Connections o e 17 Module Dimensions 17 Met l StandoffS 2 780 a ER a Gub RG a E 20 Cooling Requirements 22 Setting the Logical Address Switch 23 Setting the Interrupt Priority ooa 24 Installing the Breadboard in a Mainframe llle 25 Terminal Modules 26 Screw type Terminal Module o o e 26 Wiring Guidelines ee 26 Term
13. PIACK enabling buffer U10 57 true 44 57 Power Supply 10 backplane voltages available 63 pin numbers 47 using other 60 voltage 47 60 R READY 36 52 Reading custom register 62 data from registers 51 device type register 10 38 53 61 ID register 10 37 53 61 status register 10 36 52 53 Registers control register 10 40 41 54 56 61 decoding 32 device type register 10 38 53 61 ID register 10 37 53 61 reading data from 51 status register 10 36 52 53 Reset hardware 59 module 10 59 signal SYSRESET 44 59 software 59 S Safety Warnings 4 7 11 13 Schematics 68 71 Setting interrupt priority 24 43 57 logical address switch 23 Shielded Twisted Pair Cable 27 SHOCK HAZARD 13 Software Reset 59 Specifications 63 compliance 7 Standoffs 20 21 Static Sensitivity 13 Status Register access points 52 backplane address lines 52 bit definitions 36 51 disabling 42 enabling 36 Agilent E1490C User s Manual Index 75 S continued Status Register continued reading 10 36 52 timing for reading 53 STATUS 36 40 Stubs 46 SYSCLK 40 41 44 SYSFAIL INHBT 44 SYSFAIL 44 SYSRESET 44 59 T Terminal Block See Terminal Module Terminal Module attaching to breadboard 31 connections 17 26 29 30 crimp and insert option 11 27 28 description 26 maximum current 63 options 11 27 28 screw type 26 wiring 26 29 30
14. LABUS 5 7 5 P2 eu i e e az g 8 EE pou 4 LABUS 4 Nw LRBUS O 9 antan TR 23975 ls ABSO Ny LABUS leja n lE Te SEGER 8 LABUS 2 LABUS I M 4 Aaa H AS S ll tann CABUS EI AM 51 a o lo LABUSCO LABUS 3 18 L PI HP CARDADRE La N VCC 74HCT688 oo AML5 0 AMES 0 Sr E Ki lt LOGIC ADDRESS 3 I r a i Tal a lt ve xG pis SS d 19 16 PIACKX xe o PUI EU LABUS C2 2p He DBL L Fo eN 24HCT688 Leer le 0 H EE EABUS G LABUS 4 sa ACIS x LABUS 5 LABUSCI E M Y4 S Y Y amp LABUS 4 aBUSQ3 7 5 5 LABUS 3 A AA s Je 4 LABUS 2 oe Y 3 LABUS 1 a Yo 2 LABUSCO K 74HCT541 DBC15 0 1 1 vec Alis 1 BANK DECODERS U a m P ns BE B vt PO DEVTYPEX C ya bo status m s n E o DEVDEP0 vi NO DEVDEP It 10 a aes S s SO DEVDEP2 74HCT14 ba M x O DEVBEP3x lt BAI e N w gt hD P4x S ADDRESS LATCH SENE 6 74HC138 lt U DBENx O eka BCARDADRX 2 3 K an z MET Bal N DER i 20 20 Ba ti BA 30 30 i BAZ KR 3 s 6 BA3 4D 40 G BA3 K Ru s 5 BA4 ats 7 TA Bas x Bnd Ti ek d BAS 7D 20 ETE NC Bee 80 LAS NE a L 74HCTS73 SE IRO GND BAL dv SONS B 3 w 7 HO RI BAJ 3 13 ADDRe 3 4 E Y 3 4 2 12 ADDR 5 6 Y3 5 6 3 vet 1 ADDR4 8 Weg Y4 8 4 6 10 ADDR5 9 10 7 ES ADDS m 2 wan Yo mu 6 5 7 ADDR 13 ID 1 R xGeB Y 13 14 Gi 7 15 16 gt NC 15 16 NC X GND 48LS138 J4 ACKADDR O Figure 2
15. 0900000 o o LLL LLL P2 VXI Backplane Figure 2 1 Agilent E1490C Breadboard Module l YO ud Pen pe UL E S Backplane Interface Circuitry p Connectors Chapter 2 Configuring the Agilent E1490C 15 Backplane Connections The breadboard module allows you to interface your custom circuits to any standard C size V XIbus backplane connectors P1 and P2 This enables you to access the backplane control signals data lines address lines trigger buses and power supplies Backplane Connector Table 2 1 lists backplane connectors P1 and P2 pins which connect to the V XIbus Pins backplane Address memory or anything requiring A24 A31 cannot be accessed because there are no pins for the center row on the P2 connector Data wider than 16 bits cannot be sent because the D16 D31 Iines are also on the center row Table 2 1 Backplane Connector Pins Backplane Connector P1 Backplane Connector P2 Row A Row B RowC Row A RowC Pi Pin Mnemonic Mnemonic Mnemonic P2 Pin Mnemonic Mnemonic 1 DO D08 1 ECLTRGO CLK10 2 D1 D09 2 2V CLK10 3 D2 ACFAIL D10 3 ECLTRG1 GROUND 4 DS BGOIN D11 4 GROUND 5 2V 5 D4 BGOOUT D12 5 LBUSAO LBUSCO 6 D5 BG1IN D13 6 LBUSA1 LBUSC1 7 D BG1OUT D14 7 5 22N GROUND 8 D7 BG2IN D15 8 LBUSA2 LBUS
16. 15 VDC General purpose power for high level output drivers Used to derive voltages for precision analog devices such as 15 VDC Power for ECL devices Power for ECL termination loads Power to sustain memory clocks etc when 5 VDC is lost User may supply this power if necessary 60 Using the Agilent E1490C Chapter 3 Example Programs Reading the Registers Register Definitions Reading the ID Register Reading the Device Type Register Writing to the Control Register This section shows example programs to read the ID and Device Type Registers and write to the Control Register The examples in this section show how to use the VXI READ command to read the ID and Device Type Registers Reading the Status Register is similar ID Register Reading the ID Register register 00h returns FFFFh which indicates the manufacturer is Agilent Technologies and the module is an A16 register based device Device Type Register Reading the Device Type Register register 02n returns FF60h which indicates the device is the Agilent E1490C breadboard Status Register All 16 bits can be user defined VXIbus Specifications define bit 2 as self test 0 failed executing self test 1 passed bit 3 as extended self test if O and Status Register bit 2 is 1 the Extended Self test is active bit 14 as module selected by MODID 0 module selected 1 not selected and bit 15 as A24 A32 active 1 A24 A32 Regi
17. C12 0160 4832 12 Capacitor 01 uF 1096 100 V 04222 SA101C103KAAH C13 C14 0160 4822 2 Capacitor 1000 pF 5 100V 04222 SA201A102JAAH C15 C18 0180 1746 4 Capacitor 15uF 10 20V 56289 150D156X902082 DYS CR1 CR4 1900 0233 4 Diode Schottky 50088 1N5711 F1 2110 0712 1 Subminiature Fuse 4 A 125 V 75915 R251004T1 J1 J4 1251 4927 2 Connector Post Type 16 Contact 18873 67997 616 J3 1251 4682 1 Connector Post Type 3 Contact 27264 22 10 2031 Li 9140 1354 1 Fixed Inductor 47 uH 15 28480 9140 1354 P1 J2 1252 1596 2 Connector Post Type 96 Contact 06776 DIN 96CPC SRI TR P2 1252 4743 1 Connector Post Type 64 Contact 00779 650945 5 R1 0757 0417 1 Resistor 562 Q 1 1 4 W 28480 0757 0417 R2 R3 R6 0757 0437 3 Resistor 4 75 kQ 1 lg W 28480 0757 0437 R4 0757 0453 1 Resistor 30 1 kQ 1 1 4 W 28480 0757 0453 R5 0757 0421 1 Resistor 825 Q 1 1 4 W 28480 0757 0421 R7 R8 0757 0394 2 Resistor 51 1 Q 1 1 4 W 28480 0757 0394 RP1 1810 0411 1 Resistor Network 50Q2 x 9 32997 4310R 94Y 500 RP2 RP10 1810 0279 9 Resistor Network 4 7KQ x 9 32997 4310R 6F4 472 SP1 SP5 3101 3066 5 Switch Rocker 15A 30VDC 81073 76YY22968S U1 U1 1820 2848 1 IC Receiver 28480 1820 2848 U2 1820 4197 1 IC Driver 28480 1820 4197 U3 1820 3674 1 IC Driver 27014 MM74HC125N U4 1820 4643 1 IC Gate CMOS 18324 74HCTO2N U5 1820 4057 1 IC Bu
18. DB 9 Yo DBC 5 de Duo 4 8 a 16 DB 10J e kv DBCIZJ 6 g DUOL 5 i 15 BOU e Yo DI 7 e DEZI 6 x a 14 DB 12 y Yo mai 8 gt y D 7 a lt 13 DB 13 y y DBLIS 3 e jJ DU 8 a gt 12 DB 14 Y Va 19 dE 3 m a no DBCISI xj Rox o 34 46LS2458 1 Pa 14 DBL15 0 Figure 2 20 Data Bus Drivers Data buffering is provided for the data lines by two tri state octal bus transceivers U20 buffers DO through D7 and U19 buffers D8 through D15 Note that the data lines are labeled DBO through DB15 on the module side of the buffers U19 and U20 are enabled during a data bus transfer cycle when DBEN Data Bus ENable goes low This occurs whenever the breadboard module is correctly addressed by a match of the module s logical address as set by SP1 0 7 The direction of data transfer is determined by WRITE When WRITE is true a write operation information present on backplane lines DO D15 is transferred to the breadboard module via DBO DB15 When WRITE is false a read operation information present on DBO DB15 is transferred to backplane lines DO D15 During a normal read operation the information present on DBO DB15 is selected by the Address Decode circuitry from one of three sources Status Register U24 U25 ID Register U11 U12 Device Type Register U14 U13 User supplied circuitry can decode the entire module address space allowing for 32 registers maximum Refer to Table 2 2 and Fig
19. WARNING dition that could cause bodily injury or death A I Calls attention to a procedure practice or con J o Frame or chassis ground terminal typically CAUTION dition that could possibly cause damage to connects to the equipment s metal frame equipment or permanent loss of data WARNINGS The following general safety precautions must be observed during all phases of operation service and repair of this product Failure to comply with these precautions or with specific warnings elsewhere in this manual violates safety standards of design manufacture and intended use of the product Agilent Technologies assumes no liability for the customer s failure to comply with these requirements Ground the equipment For Safety Class 1 equipment equipment having a protective earth terminal an uninterruptible safety earth ground must be provided from the mains power source to the product input wiring terminals or supplied power cable DO NOT operate the product in an explosive atmosphere or in the presence of flammable gases or fumes For continued protection against fire replace the line fuse s only with fuse s of the same voltage and current rating and type DO NOT use repaired fuses or short circuited fuse holders Keep away from live circuits Operating personnel must not remove equipment covers or shields Procedures involving the removal of covers or shields are for use by service trained personnel only Under certain conditio
20. guidelines 26 Timing control register writing 56 status register reading 53 U User Access Points 46 Using interrupts 57 other power supplies 60 V VXI READ Command 61 VXI RESET Command 59 VXI WRITE Command 61 W WARNINGS 4 7 11 13 Warranty 3 7 Wiring guidelines 26 terminal module 26 29 30 WRITE 35 true 42 55 Writing control register 10 40 41 54 56 61 custom registers 62 Writing to the Control Register 55 76 Agilent E1490C User s Manual Index Looking for more information 6 Artisan Visit us on the web at http www artisan scientific com for more information QUALITY INSTRUMENTATION GUARANTEED Price Quotations Drivers Technical Specifications Manuals and Documentation Artisan Scientific is Your Source for Quality New and Certified Used Pre owned Equipment Tens of Thousands of In Stock Items Fast Shipping and Delivery Equipment Demos Hundreds of Manufacturers Supported Leasing Monthly Rentals Consignment Service Center Repairs InstraView Remote Inspection Experienced Engineers and Technicians on staff in our Remotely inspect equipment before purchasing with our State of the art Full Service In House Service Center Facility Innovative InstraView website at http www instraview com We buy used equipment We also offer credit for Buy Backs and Trade Ins Sell your excess underutilized and idle used equipment Contact one of our Customer Servi
21. 1 LATCHX U E pt select IRQX ro IRQ PIACK LATCHX S De F LOGICAL PLA a Le es DTKINH DEVICE A OE ADDRESS enis DTACKX N ENABLE m CONTROL DTACK REGISTER SYSRESET ESAS CTL2 DB WRITEX HE GE TX n an A el CLEAR i SYSFAIL INHIBIT Le DBEN RESET Let DB15 Y HRESETx READ DATA BUS CRESETX ENABLE DRIVER lt DIRECTION D D15 B gt DB15 INTERNAL DATA BUS TTLTRGQ 7x DATA ECLTRG 1 BUS SUMBUS E LBUSA2 11 DRIVERS NOTE USER LBUSCQ 11 ACCESS CLK1Q POINTS SERCLK SERDATx ACFAILX ALL POWER SUPPLIES Figure 1 1 Digital Backplane Interface Block Diagram Chapter 1 Introduction 9 Status Register Reading this 16 bit register provides information about the status of the breadboard module Implemented signals are A24 A32 Active MODID Extended and Passed There are also provisions for implementing device dependent status bits See page 36 for information about the Status Register ID Register Reading this 16 bit register identifies the manufacturer identification number the device class and the addressing mode of the breadboard By using the DIP switches the user selects hardwired configurations for these items See page 37 for information about the ID Register Device Type Register Reading this 16 bit register identifies the unique card model as defined by the device manufacturer It also indicates the amount of memory available on the card in bytes for A24 and A32 devices only By us
22. 19 Address Lines and Register Decoding Chapter 2 Configuring the Agilent E1490C 33 Either of the two address modifier hexadecimal codes indicated above will establish A16 addressing per the VXIbus System Specification Section C 2 1 1 5 In the VXIbus addressing scheme for an A16 device A14 and A15 are always set to 1 to select the upper 16K of the 64K A16 address space per the VXIbus System Specification Sections A 2 3 3 and C 2 1 1 1 LWORD is false when decoding short word 16 bit transfers If a second match occurs at U17 its output goes low This triggers a data transfer cycle using the DTACK state machine in the DTACK Interrupt Control IC PAL by the low at U9 input CADDR See page 41 for more information on the DTACK state machine As part of the data transfer cycle U9 sets DBEN low latching the remaining backplane address lines A1 A5 at the U8 outputs to the two 3 to 8 line decoders U7 and U6 Latch U8 ensures that the address information is held valid until the data strobes go false even though the address lines may no longer be valid U7 is enabled if G1 is high and both G2A and G2B are low Therefore A4 and A5 must both be low to select a register for connection to the data bus DO D15 G1 will be high if there was a match at U18 via U15D If U7 is enabled backplane lines A1 A3 are decoded to specify which register Status ID Device Type or Control is to be connected to the data bus User supplied c
23. 59 50 D ve Se a o RPIF RPIG VIT 1 1 8 Ai lis 8 1 t6 Ze vcci vcc2 GND VIT VIT VIT VEE 4 AQ Zeit 5 3 ECLTRGO o2 a a A be 29 ECLTRGOUTO UL OHI L6 E 3 BANC Bm xBxB A m ECLTRGI OL a a a B bo 3 O ECLTRGOUTI 3 4 l 2 l 2 12 Se 14 T J 13 S a 15 RPIB RPIC Rf I CRI CRIA CRI A ST ud l 1 2 l 2 I 8 A 4 4 4 VTT VTT B 2 o BCLK10 UG L Cl4 m 1000pF 1000pF VEE a o BCLKIO H 1 l Pg a EN 50 50 SERLO rs 5 reta gelu CLK10 m 1 1 1 1 R8 R 51 1 51 1 VIT VIT 2 2 VIT VIT Figure 2 27 ECL Trigger Circuit Chapter 2 Configuring the Agilent E1490C 45 User Access Points The breadboard module contains traces stubs for accessing many of the signal lines on backplane connectors P1 and P2 Table 2 10 shows the signal lines that are brought onto the module but not implemented They are available as signal access points for your custom circuits Table 2 10 User Access Points Stubs Signal Lines Description ACFAIL AC Input Power Fail LBUSAO 1 1 Daisy chained Local Bus A LBUSCO 11 Daisy chained Local Bus C SERCLK Synchronizes data transmission on the VMEbus SERDAT Used for VMEbus data transmission SUMBUS Analog Summing Node TTLTRG 0 7 Intermodule Communication Lines TTL Level 5VSTDBY When implemented in the VXI mainframe supplies 5 Vdc to devices needing battery backup Table 2 11 shows all of the implemented signal lines availab
24. ENable DBEN output of U9 If the data transfer cycle is a read operation as indicated by WRITE false the decoded output of U7 enabled by the output of equality detector U17 determines which one of the registers Status ID or Device Type is enabled to put its contents onto the module s internal data bus DBO DB15 The next state then generates a high at the DTACK output of U9 This forces DTACK true on the backplane through USB acknowledging to the system controller that the module has received the request for data and has placed the contents of the specified register onto the data lines With U19 and U20 enabled internal data lines DBO DB15 are connected directly to the backplane data lines DO D15 Chapter 2 Configuring the Agilent E1490C 41 ES A eS n a AR en e RQ TEST POSITIO IRQ TEST i IRO TEST POSITION vent I 2 Pul CONNECTOR n 2 t PUI 3 NORMAL POSITION ver kita ee Deu EN emm EEN ei 2 R3 U15C 4 75K So al 1 IRo 24HCTLA z e UZTA XPR ex 5 IRQ 12 d O PIACKx A 13 XCLR Ne HRESETx c 4HC 4 EAD O DBENt 10 t x e mmm z Ge GND vec UE IRQ Ba us PIACKX 30 1K i DBEN 5 ACKADDR O ACKAUDR ACK
25. HRESETx DB 15 0 Figure 2 24 Control Register Table 2 8 shows the Control Register bit definitions The Control Register is selected for writing to by the BASE 4 enable line see Table 2 2 STATUS going low at the input of U4A combined with a negative pulse for one clock cycle of SYSCLK from the LATCH output of U9 also applied to U4A provides a positive going edge clocking pulse to U22 U23 This pulse clocks whatever is present on DBO DB15 through U22 U23 to the Control Register access points CTL2 CTL15 CTLO and CTL are reset and sysfail inhibit bits The user may connect any or all of these points to his custom circuitry keeping in mind the pre defined bit assignments shown in Table 2 8 Data present on DBO DB15 would have been written there by the same DTACK state machine data transfer cycle that provided the LATCH pulse See page 41 for a discussion of the DTACK state machine operation 40 Configuring the Agilent E1490C Chapter 2 DTACK Interrupt and Control DTACK Table 2 8 Control Register Bit Definitions Data Bit s Definitions CRO 1 Reset the module User defines reset actions CR1 1 inhibit setting of SYSFAIL if Reset 1 safe CR2 CR14 Device Dependent User Assignable CR15 1 Enable access to A24 A32 Registers 0 Disable See pages 54 and 55 for additional information on using the Control Register Refer to the VXIbus System Spe
26. System Specification Section C 2 1 1 2 for detailed information concerning Device Type Register implementation restrictions Table 2 7 shows the Device Type Register bit definitions Table 2 7 Device Type Register Bit Definitions Data Bit s Definitions DBO DB11 Device Type or Model Code Range 0 to 4095 DB12 DB15 Required Memory A24 and A32 devices only Chapter 2 Configuring the Agilent E1490C 39 Control Register CNTRLREG CLR Uee CLK Cit u o o E u Owl w w w w 1 tC tO Nala swm a 8 74HC273 PASSED O A a The Control Register is a 16 bit register which when written to from the backplane data bus causes specific actions to be executed by the breadboard module The primary components of the Control Register are U22 and U23 as shown in Figure 2 24 SYSFAIL U4B 4 SY5FAIL 13 SYSFAILIN org B RESET RESET 8 E SYSFAILIN ual 2 5 D m 19 ID pg 4 vum YXO 2 O CRESETx Pg 2 SYSRESET 3 e Py 4 Pg 4 Py 4 Py 4 33333 r Cn C C C toc f C SYSRESETx Cc 3 u 10 11 a 12 CH 13 14 CH ojojojaoa jam ju jam tg Cic 15 CLK XCLR Ue3 74HC273 24HCT14 74HCT14 Pg 2 4
27. c 4 F n 70 OH CTL14 0 pre SE DEBI 2 n sI 18 DBLBD DBLISI Dk MED PP P EL430 66511 07 B4 cTLI5 YO ron 3 sheet 1B ANA x 74HC273 yf dation 8 Dt90 3 z 17 DBI90 Y DBCIIO 5 G DELON 4 A 16 DBL100 Y mat 6 DII 5 ki 15 DBIIID d DBU30 7 DELI 6 l 2 14 DBLI20 Y mat e la WISEN S E 13 DBLI3D Y DBLISO 8 e E 8 s x 1 DBL140 1 10 DELSI 3 4 M 1 DBLISD e mn TROx Oo 74AL6245A 1 serta c faa DBLI5 01 DL15 00 Appendix B Agilent E1490C Schematics 68 DES CK DJ CON E DC VXIbus BACKPLANE CONNECTORS INPUT POWER FILTERING E di UNUSED GATES PARTS P f E ECH F yo a Ze 4A zeen HP07 12 1 VCC EC cis Jo VCC 15uf 15uf 10 1218 2 2 LES spp I gt CLK 9 GND GND Z dee L ya XCLR ki Eo S 74HC74 ALO l gen L V ai BYPASS CAPACITORS cis 15uF I ale J A13 pan ESA au GND A15 yo ES TRO TEST POSITION A A c Q TES 05 e Q TAS m i 2446 CTL2 CONNECTOR akt py Pio pul GND nis
28. its calibration measurements are traceable to the United States National Institute of Standards and Technology formerly National Bureau of Standards to the extent allowed by that organization s calibration facility and to the calibration facilities of other International Standards Organization members Warranty This Agilent Technologies product is warranted against defects in materials and workmanship for a period of one 1 year from date of shipment Duration and conditions of warranty for this product may be superseded when the product is integrated into becomes a part of other Agilent products During the warranty period Agilent Technologies will at its option either repair or replace products which prove to be defective For warranty service or repair this product must be returned to a service facility designated by Agilent Technologies Buyer shall prepay shipping charges to Agilent and Agilent shall pay shipping charges to return the product to Buyer However Buyer shall pay all shipping charges duties and taxes for products returned to Agilent from another country Agilent warrants that its software and firmware designated by Agilent for use with a product will execute its programming instructions when properly installed on that product Agilent does not warrant that the operation of the product or software or firmware will be uninterrupted or error free Limitation Of Warranty The foregoing warranty shall not apply to defec
29. of this material This document contains proprietary information which is protected by copyright All rights are reserved No part of this document may be photocopied reproduced or translated to another language without the prior written consent of Agilent Technologies Inc Agilent assumes no responsibility for the use or reliability of its software on equipment that is not furnished by Agilent U S Government Restricted Rights The Software and Documentation have been developed entirely at private expense They are delivered and licensed as commercial computer software as defined in DFARS 252 227 7013 Oct 1988 DFARS 252 211 7015 May 1991 or DFARS 252 227 7014 Jun 1995 as a commercial item as defined in FAR 2 101 a or as Restricted computer software as defined in FAR 52 227 19 Jun 1987 or any equivalent agency regulation or contract clause whichever is applicable You have only those rights provided for such Software and Documentation by the applicable FAR or DFARS clause or the Agilent standard software agreement for the product involved Agilent E1490C C Sized VXIbus Register Based Breadboard Module User s Manual Edition 3 Rev 2 Copyright 1996 2006 Agilent Technologies Inc All Rights Reserved Agilent E1490C C Sized VXIbus Register Based Breadboard Module User s Manual 3 Printing History The Printing History shown below lists all Editions and Updates of this manual and the printing date s The first printi
30. state machine passes the daisy chained IACKIN signal through IACKOUT on U9 The IACKOUT signal is gated with an inverted AS to meet release time requirements for IACKOUT as outlined in the VMEbus Specification If the acknowledge level matches the request level the IRQ state machine sets PIACK true releases IRQX and IRQ1 and starts the DTACK state machine for a read cycle PIACK going true also clears the IRQ latch U15 The interrupt handler initiates the read cycle to get the logical device address from the interrupter when it sees IRQ1 go false PIACK true enables U10 to place the module s logical address from SP1 onto the lower eight bits of the internal data bus DBO DB7 The logical address is then transferred to backplane lines DO D7 during the read data transfer cycle In this way the interrupt handler knows which device is asserting IRQ if more than one device has the same interrupt priority assigned to it Control Table 2 9 shows the control signals which are implemented see Appendix B Table 2 9 Control Signals Signal Definition AS Address Strobe used in the IRQ data transfer cycles DSO DS1 Data Strobes used in the data transfer cycles SYSCLK Provides 16 MHz clock signals to the PAL U1 for clocking the state machines SYSFAIL The module can assert this line to the backplane by setting bit SR2 low in the Status Register If the SYSFAIL INHBT line output of the Control Register bit
31. to the Status Register are provided by the user from the custom circuitry on the module Access points STATUS 0 15 on the component side of the module and TP184 TP198 on the trace side are provided on the module to tie into the Status Register as shown in Figure 3 1 See pages 36 and 52 for additional information on using the Status Register Table 3 1 Status Register Bit Definitions Data Bit s Definitions SRO SR1 Device Dependent user assignable SR2 0 failed executing Self test 1 passed Self test SR3 Ready SR4 SR13 Device Dependent user assignable SR14 0 2 module selected by MODID high 1 2 not by MODID SR15 Device Dependent for A16 device Chapter 3 Using the Agilent E1490C 51 Status Bits Cr On mn l CE N A i ES DOUDOU ESEYE Ann z Status Bits oe 8 15 P2 Figure 3 1 Status Register Access Points Reading the Status For example assume you need to use up to 16 bits of the Status Register Reg ister including latching the data in both halves of the register To latch your status data and then read the 16 bit contents of the Status Register onto the backplane you must implement the following signal and control lines 1 Address the module correctly by placing the data shown in Table 3 2 on the backpl
32. warranty is different than the standard Agilent Technologies warranty statement located at the front of this manual While Agilent Technologies is responsible for defects in materials and workmanship of the blank printed circuit board and supplied hardware Agilent is not responsible for the performance of your custom designed circuitry In addition Agilent Technologies is not responsible for damage to or improper operation of your VXI mainframe or other plug in modules caused by the Agilent E1490C Breadboard Module Chapter 1 Introduction 7 Agilent E1490C Description The Agilent E1490C Breadboard Module is a C size register based device that provides a convenient interface to a VXI mainframe backplane It allows you to construct your own custom hardware for use with the mainframe Breadboard Module The module provides VXI A16 D16 register based backplane interface Features circuitry and metal shields to enclose the printed circuit board Your VXT mainframe can communicate with this module configured as an A16 D16 device The breadboard module interface circuitry is implemented and accessible according to the requirements outlined in the VXIbus System Specification Users can still provide custom extensions to expand module addressing capability to A24 or A32 by adding appropriate circuitry according to the VMEbus and VXIbus System Specification Backplane Interface An overview of the Agilent E1490C interface features follows See F
33. 1 is also low not inhibited then SYSFAIL is asserted SYSRESET System reset signal used to initialize the backplane interface circuitry and your own custom circuits to a known state Provides a hardware reset capability As implemented HRESET it clears the Status Register and the Control Register It also asserts the software reset line access point CRESET on the module CRESET can also be asserted via software by writing a high signal to the Control Register bit O providing an input to U2C 44 Configuring the Agilent E1490C Chapter 2 ECL Trigger Logic Figure 2 27 shows the ECL Trigger Circuitry The ECLTRG lines provide an intermodule timing resource Any module including the Slot 0 module may drive or receive information from these lines The asserted state is defined as logical high Trigger information from the VXI backplane ECLTRGO and ECLTRG1 pass through U1 to ECLTRGOUTO and ECLTRGOUT1 for custom use Trigger inputs from user custom circuitry must provide ECL level signals TTL is not compatible to ECLTRGINO and ECLTRGINI CLK10 BUFFER ECI TRIGGER INTERFACE hi NOTE E a veci voce GND VEE D eN D 3 PDI VIT 2V 6 AOUT AJ 7 Py Ue MC1OHL238E ECLTRGINO O den ab BOUT 6 B3 50 12 Pg 4 RPIE ECLTRGINI al ki s de 7 8 a COUT 2
34. 23 81 c31 33 LON ZO LEA TTLTRG2X 36 Do s Ju a MER An mi NE a yo Om Omm A s BI480B BREADBOARD MODULE 7 ye R fuse T FILTERING AND USER l l ZO MH123 ZO IER OO MH124 i 7 V n Ya res iQ CONNECTIONS l 1 YON E y m lues MH128 MH127 ate 1490 66511 e TILTRGSX 1 1 ki sheet 4B 0 M a Appendix B Agilent E1490C Schematics 71 A Access Points control register 54 status register 52 ACKADDR 43 Address decode circuitry 35 lines 8 32 lines backplane 52 55 logical 23 32 modes 38 modifier lines 8 strobe 44 Airflow Requirements 22 AS 44 Asterisk meaning of 8 32 Attaching breadboard to mainframe 25 terminal module 31 B Backplane buffering 10 connections 16 connector pins 16 schematic 69 control register address lines 55 interface circuitry 32 interface features 8 status register address lines 52 Bit Definitions control register 41 54 device type register 39 ID register 37 status register 36 51 Block Diagram 9 Breadboard addressing modes 38 attaching terminal module to 31 block diagram 9 component locator 67 Index Agilent E1490C User s Manual Breadboard continued custom circuitry 47 49 device classifications 38 installing in mainframe 25 interrupt priority 24 43 57 module 15 schematics 68 71 specifications 63 C Cables shielded twisted pair 27 CADDR 41 Card Address CADDR 41 CAUTIONS 13 Certification 3 Clocking Puls
35. 4 Timing for Writing to the Control Register 56 Using the Agilent E1490C Chapter 3 Using Interrupts Configuring for Interrupts Generating Interrupt Requests The breadboard module can be configured to generate an interrupt to the interrupt handler when service is required To configure the module to generate interrupts you must first assign an interrupt priority level to the module Levels 1 7 are available with level 7 being the highest level Jumper JI selects the interrupt REQUEST level interrupt generated on the Agilent E1490C breadboard and Jumper J2 selects the interrupt ACKNOWLEDGE level interrupt passed through the VXI backplane to the Agilent E1490C Both jumpers must be set to the same level To generate the interrupt request and accept the interrupt acknowledgement from the interrupt handler you must implement the following actions You must provide the interrupt request from your custom circuits by setting the IRQ access point low 0 when the interrupt is to occur Interrupts are edge triggered f more than one module in the mainframe has the same interrupter priority level to ensure that this module reacts to its own interrupt acknowledge position the breadboard module in the closest slot to the right of the interrupt handler f you do not implement the interrupter capability you must ensure that the daisy chained IACKIN signal is passed to IACKOUT either on your module or by bypassing the slot ent
36. 4 72 d 20 d 52 xe d X UN A at ME Ing l K PIRE s 9 ENN o a YON 1 1 LBUSAG pae Lsuscs OR MH22 GND 12 Yo 4 ye 78 88 3 ES CL ne mE i mas Na EET a g 53 85 Av 1 LBUSC oft LS os an po B13 c3 E oft ap Oe M 2 78 YO l rar I D maa an LI AYE Be a d e wn o N T i _ A CIE sH BO us 47 N 45 73 N 7 Uf 22 g LBusas o Ys LBUSCB ot MH28 16 T 48 46 80 78 cra AA Pey 25 2 sa N is 7 L mine I MHL 02 MH103 me MON O an ET N 1 laz Yo Y 55 zh i LBUSAS MH2B LBUSC3 Her Pl 1 O ET Pa 1 l 18 1 50 Ni we 82 D cua PA CTLI0 o C too f18 BIB C18 5l 83 i 1 1 NS CN AO es KE cis n MH105 MH107 MH106 LBUSA10 O hes LBUSC10 O O mase D I LA D I 1 ME EL ww D dies Hei P CTL5 ALO T era 020 rezen MENN TEN EN ANECA we i LAN ppo O 2 mm LBUSCII oft H31 1 mi d Em x Liz Ns SE SC O LC os aos Cor o8 TP204 entra o D meu Bas 57 83 23 a 55 y 87 85 i Be3 3 lcs 1 Pa 1 1 88 1 1 1 oA Oy ma Pg TP203 owt veal MENN TUN ki wan vu un IROX LJ mp CTO O EE PO ES a el ff s ME e You Dei a A Pg le l Pg 1 Pg 1 e IE fa 58 Ne ss o ET sa LON 1 as ON ty LATCHK O82 meis ere o Peo CL 04 trees IE a lar SN 57 PIE D MHLIE e MH115 TILTRGOX OP Yonn D 2 E 31 Pg l Pg 1 32 3 TP201 oO alt bs Je st N M NE DS ena A CTLIS _ Tp208 I es 27 B29 s c29 i EE 5 MH117 MH119 MH118 TILTRGIXx ne 30 82 Wu 94 D d LY af se Se A30 31 B30 83 N C30 95 28 vi 1 ai 031
37. ADDR ed L eN LATCH x TACK INX O Raid LI 10 AS 8 JI IRQ ASE Oa Ee CARDADR 3 is I 2 ULSE CADDR k VCC 3 1 w i IRQI 4HCT14 SER reni EM A re IRO2 2 A 5 6 RO3x CARDADRY O DS Ti ud 5 usc AS OIROX 8 3 SC 19 74F38 s Fo TROU A D50 10 3 4 nso B 7 3 10 i IROS 5 WRITE Oa T1 Y BSYSCLK 2 ait avi IROG 6 CLK ULSB fa it IRQ 7 74HCT L4 E NOUN FOW KOUV X 21 Hp D51x o TS LU BERT IROX ap DTAC a Y GND ROX 5 74F38 23 ULSA 19 TACKOUT E 24HCT14 IECH 18 DTACK Dok 5 DTACK 4 4 LATCH T VCC DS0x RS DBEN P 2 end PALVMEIFC E 2 1 562 E SYSCLK E usA 3 1 ES c AS 2 24F38 IM DN 5 GND BSYSCLK O Figure 2 25 DTACK Circuitry If the data transfer cycle is a write operation as indicated by WRITE true an additional state sets the U9 LATCH output low enabling the Control Register to receive data from the data bus drivers for example before DTACK is set true The resulting Control Register outputs CTL2 CTL15 can then control the user s circuits as desired Again DTACK going true tells the system controller that the data transfer cycle is complete In a write operation WRITE going true disables the Status Register the ID Register and the Device Type Register For both read and write operations the DTACK state machine holds DTACK true and the address latched until the data strobes are invalid After the data strobes go invalid the data bus drivers are disa
38. ADDRE 1l 12 LABUSCO 3 LI DBLOD y D aces YE no 8 LABUSOD A 00 yo Z ADDR E D Vv s LABUS O z 74HCT541 3 L 7 sj g 4 HCTS NC 15 16 NC x Lt vce E 748 5138 Sa DBENK o 2 GND 229 ACKADDR TER VC DBC15 00 ap 2 R2 vec 4 75K E paS Pg 1 3 2 1 a STATUS VA Li 5 Sei USD XN a ANB S CNTRLREG passen Od ON S v AGO SYSFAILx Pg 2 4 3j 4HCTO2 1 ar LATCH y n SYSFAILIN 6 pM I ap u22 D gt CLK x DBLOD 3 L Jun RESET RESET PL x WRITE ROAD DBLIO 4 5 SYSFAILIN vac gt TED S 20 a fp Y 3 CRHSETX m DATA BUS BUF Y UBL20 7 6 Py 2 4 SYSRESET 3 EA lt a 3D 30 CTLe er i Y Datan Dk ME m to Cra 3 n Ho S p Es 16 y DRAI 13 l D I Py 24 READX 1 u20 1 5D so Tt READE D Y DBLSD DS MEE SET g o vec Y DBEST 17 16 T 4 7D n re CT si DIOD 2 zl D 18 DBLOD Jk DBL D 18 19 Pa 4 GIES PEYE S m Bl eD 80 0 CTL 74HC273 J15 YO DOI 3 at 3 de ZO DBLIU 20 pees m d DBI 4 y pren 4 p i 15 DBL20 i TEA eta STSRESBIX YO DRI 5 DEZI 5 i A i5 DB 30 i saneti 74HCT14 e DB 4D 6 Cat 5 de j 1 DBL4D Pes ge YO DBESD DESI pi x 13 DO ak 212 HRUSETX Je DBL60 8 E Den 8 1 DBL6O WEN aH 2 Pa 4 DBL O 9 Diu B E S mo DBL 0 S DBLSD a WE PRESS to M 2 Co zn ge Zon Loy id Darin kl WE Ahh H1490B BREADBOARD MODULE Pg 4 4 L 19 A A 4 CTL11 mon L_ACKADDR jJ U DBL121 J SL voc As N G mR y DOE ja aE era VXI DECODER LOGIC TT DB 141 17 15 Pg 4
39. C Crimp and Insert Tools The hand crimp tool part number Agilent 91518A is used for crimping contacts onto a conductor The pin extractor tool part number Agilent 91519A is required for removing contacts from the crimp and insert connector These products are not included with Option A3E or with the terminal option accessories listed earlier Extra Crimp and Insert The crimp and insert connector is normally supplied with Option A3E Connectors Contact Agilent Technologies if additional connectors are needed Order Agilent 91484B 28 Configuring the Agilent E1490C Chapter 2 Wiring a Terminal Module The following illustrations show how to connect field wiring to the terminal module D Remove Clear Cover A Release screws B Press tab forward and release ia Remove and Retain Wiring Exit Panel s Remove 1 of the 3 wire exit panels E Use wire N A size 22 26 po AWG SIS 6 Use wire size 16 26 1 Dri j AWG with VW1 A Flammability Rating Pe dif des Insert wire into terminal Tighten screw Screw Type Crimp and Insert IN Figure 2 17 Wiring the Terminal Module continued on next page Chapter 2 Configuring the Agilent E1490C 29 ym Replace Wiring Exit Panel s Cut required N holes in panels for wire exit k hole as small as possible Keep wiring exit panel NW 7 Rep
40. C2 9 GROUND BG2OUT GROUND 9 LBUSA3 LBUSC3 10 SYSCLK BG3IN SYSFAIL 10 GROUND GROUND 11 GROUND BG30UT 11 LBUSA4 LBUSC4 12 DS1 SYSRESET 12 LBUSA5 LBUSC5 13 DSO LWORD 13 5 2V 2V 14 WRITE AM5 14 LBUSA6 LBUSC6 15 GROUND 15 LBUSA7 LBUSC7 16 DTACK AMO 16 GROUND GROUND 17 GROUND AM1 17 LBUSA8 LBUSC8 18 AS AM2 18 LBUSA9 LBUSC9 19 GROUND AM3 19 5 2V 5 2V 20 IACK GROUND 20 LBUSA10 LBUSC10 21 IACKIN SERCLK 21 LBUSA1 1 LBUSC1 1 22 IACKOUT SERDAT 22 GROUND GROUND 23 AM4 GROUND A15 23 TTLTRGO TTLTRG1 24 A07 IRQ7 A14 24 TTLTRG2 TTLTRG3 25 A06 IRQ6 A13 25 GROUND 26 A05 IRQ5 A12 26 TTLTRG4 TTLTRG5 27 A04 IRQ4 A11 27 TTLTRG6 TTLTRG7 28 A03 IRQ3 A10 28 GROUND GROUND 29 A02 IRQ2 A09 29 30 A01 IRQ1 A08 30 MODID GROUND 31 12v 5STDBY 12v 31 GROUND 24V 32 5v 5v 5v 32 SUMBUS 24V 16 Configuring the Agilent E1490C Chapter 2 Terminal Module Connections Figure 2 1 also shows the user connections and the terminal module Refer to pages 29 and 30 before attempting to wire the terminal module Ignore the pin numbers molded on the terminal module connectors trace your connection through the terminal module connector to ensure proper wiring The silkscreened pin numbers on the terminal module correspond to the silk screened pin numbers on the breadboard module Connector J2 connects the breadboard module to the terminal module The silk screened numbers on the component sid
41. DIE LB Wf DB 15 01 a IK E1490B BREADBOARD MODULE 85 I l 825 j ECLTRG AND CLK10 INTERFACE 1 E1490 66511 i L I sheet 3B MODID GND Appendix B pp Agilent E1490C Schematics 70 USER CONNECTIONS 1 lan Pp 2 LOS 1952 Pg l MH33 mas A MH35 ACFAILK OL 1 al 1P34 32 v v 1 1 1 L 7 mas 1 io 5sTDBY o mr a ol ms m ja g 3 55 i 1 2v O82 CO 1P54 803 05 7 ma l MH39 en MH40 i D8t15 0 G8 Pg 2 Pa 1 EN m a Ka 88 12v o8 P5 Kees 1837 0 1 l MH44 Jwen MH43 WET 1 E DN LA DBLOD 1 es au B Ts as ol CO rese MM 186 1 1 Pg 2 l E Pg l MH45 MH47 C SAAN e TPS CRESETX O TP39 DB 10 1 Ka ER LU O V _ mes QOQOOCOJZO TILTRG6X TTLTRG x MHB Ya one O 1P58 HRASETx ol A ES p4 LL nen l vun wes a i wee natal YAN on Ys d ar 83 1 y 1 ey ECLTRGINO oi O 1939 RBADX oO rent l es m ZO MH52 DBt30 1 Fa ge go ECLTRGINI 02 seio WRITEX OPE C rouz E 4 KEN LOS mes 1 I DBL4D 1 13 yo DENEN Cs ECLTRGOUTO OF _ ess mm 03 8 7 reas AD re E 2 LAN ZO AS Pa 3 YAN Pa 1 3 LA ECLTRGOUTI O TP58 VCC O 9 1 J TP45 DBI
42. E DTKINH high will hold DTACK cycle here Data Strobes means DSO x DS1 and will stay here until DTKINH goes low when going high and DSO DS1 Sync signals with SYSCLK when going low Figure 3 2 Timing for Reading the Status Register Reading ID and The procedure to read the ID and Device Type Registers is the same as that Device Type for the Status Register with two exceptions Registers 1 the contents of these two registers are set by switches and 2 the address enable line used is different see Table 2 1 on page 16 Chapter 3 Using the Agilent E1490C 53 Writing Data to the Control Register The breadboard module contains circuitry for a Control Register You can write to this register from the backplane over data lines DO D15 The data is passed to the internal data bus DBO DB15 and then clocked into the Control Register for use by the custom circuitry on the breadboard at access points CTL2 CTL15 Do not tie anything here that cannot tolerate having a 1 written to it with software reset or do not use software reset See page 59 Control Register Bit Table 3 3 shows the definitions preassigned to Control Register data bits per Definitions the VXibus Specification Section C 2 1 1 2 You may connect any of the Control Register outputs to your custom circuitry using the Control Register access points CR2 CR15 shown in
43. ECT 21 vi E824 6 DBVTYPEx 2 3 13 Pa 1 3 Spi E acu Din 19 CARDLAX LA c Eo STATUS T Se Dun m a ES 5 6 pavppox ml In LABUS 7 LABUS Q 3 Po yi e Di DBVDEP1 x l uis S 0 AMEID 4 3 8 BCARDADR 6 D Pg 4 e s EE Ny LABUS D s TET gi T m a s Ia DEVDBP2x S9 la M ra 3 LABUSIS e LABUS 7 a 74HCTI4 aa E scan s 520 DEVDEP3 Ez 13 14 LABUS 4 LABUS 0 3 Pa 128 wh BA 6 DEVDOP4x 29 5 T az s asa V LABUS 12 TUM Ud ADDRESS LATCH 24HC138 Zell WT Ts Laso Ny Lane a q ACD 13 B gd eo S 05 EELER I S S 1o ls ABUSO NW LABUS 6 16 S EST ren k If ses af Clin aper LABUS 3 is SU um ir BCORTAUR gen I Yet CARDADR 2 ql Zum OnE TREE p 00 acid 3 18 BA Py 4 AM 5 00 5 n a 2 BAI AMI5 00 3 ZU Den D Ir BA2 hi a S E 0 5 18 LOGIC ADDRESS a BEI a a Fas 4 PO gag ALIS 10 O z x 03 Atal 5 5i 5 15 BA4 P8 5 Bra 2 ALSI 7 14 BAS PD lt l DD pH gs Sak Ge BAS SH Bu 16 Pp 70 70 NC PIACK O Ke 18 i 3m oo NC le Pg 2 1 cm lt PUL REH m LABUS C rL H 18 DBL70 L ape pai IRQ E 74HCT688 GND DONC DEER A ED le ve LI BEES GND BER 2 u L emm l 2 NN AEE LABUS 5 la ME DBISI AC140 x zs aL 1 eme kK 1 8 TA A LABUS 4 zl MITE BEIEN ALISI a c Ana sU be 2 E 57 LABUSCO ERBUS GU 5 ls vs UI DOI Y y vcc Di SES zl le 3 TE A LABUS 2 13 EE v 78 4 5 LABUS 3 Y AB Y6 5 10 ADDRS 3 10 e E LABUS OD 8 The DBCIO a w S m 5 S LABUS 2 A a v i M
44. GE 04 HOLE TD FOLD 05 EDGE 10 FOLD 04 FOLD TO FOLD 04 ANGLE 5 NOMINAL DIMENSION OF PART X 342 19 Y 22436 Z 48 Figure 2 4 Agilent E1490C Bottom Shield Dimensions 18 Configuring the Agilent E1490C Chapter 2 Location Qty Part Number Description A1 1 E1490 66511 PC Breadboard Assembly MP1 1 E1400 45101 Top Extraction Lever MP2 1 E1400 45102 Bottom Extraction Lever MP3 1 8160 0686 Clip PNL1 1 E1490 00213 Front Panel SCR1 1 0515 1375 Front Panel Screw M2 5 x 0 5 6 mm long flat head SCR2 3 2 E1400 00610 Shoulder Screw Assembly SCW8 15 8 0515 1135 Screw M3 x 0 5 25 mm long flat head SHD1 1 E1490 00611 Top Shield SHD2 1 E1490 00612 Bottom Shield Figure 2 5 Agilent E1490C Exploded View Chapter 2 Configuring the Agilent E1490C 19 Metal Standoffs Metal standoffs not provided with the module can be installed to increase the maximum component height above the printed circuit board or lead length allowed below the printed circuit board For example if you are wire wrapping components to the PC board you can install additional standoffs to compensate for the long lead length of the wire wrap sockets Top Shield A E S C Batom Shii Figure 2 6 Agilent E1490C Without Spacers If you are using tall components you can in
45. IT 14 3 W d D S l 4 1 BEN 3 a Ei 3 6 5 15 BA Ww i C13 L cn O ECLK10 12 5 DR lua pan N 1000pF E Tem 5 as y 4 I 1000pF VRE a PLO BCLKIO n l g an ell HEI Ww e 10 B 12 DBE10 2 Y H L 3 8 ON ll DON i 2 a tege C E CLK IO Pa GND 50 L 74HCT541 0 CLK10 OF SCH Re GND ao i i O DBLI5 01 I RB R ra T T SCH Zi VTT VIT l 2 2 VIT VIT S C ia is E EEN STATUSX an I E ID REGISTBR 24HCT 7 a READ o 1 4 WRITE Hue Y arly Py 14 UIGE Pg 1 4 m Wiot STATUS REGISTBR O READS TP191 TPIS0 TP189 TP188 TP187 TP186 TPIBS TP184 VCC Et a Ti oc Ue4 18 Kei Q O DBEN 0212 tin 16 1 1 I 1 1 l 1 1 Eier m 19 DROE 15 i REI RN Ween m 3 1 He DBEIU SL D MEE DBI20 y 13 4 s Fis DBL121 x 51 w L DBL30 Ni m s SM Hr BIIN o so 15 DBI y E De a E el al DBI5I N Ti x Sb DBEL100 eu E 7D 70 E DBIBI Ni 3 8 9 Mi i EX A SI MEZ DBL 0 y lasi Yo NE RPS 4 7K L RPS EK 74HCT541 8 N TP13 TP196 TP195 TP194 TP193 TPIS2 TP198 kit be 1 VCC 1 yi2 Es U25 Mal INAR 4 7 8 9 10 oc O e y O oo 7 SY 3 4 5 6 7 8 9 10 e l Loa h E 1 1 1 1 Sr i19 ptei 16 H de Hos pt 3 lay o 18 DBISD y 15 EN W w LI DBEST y 41 so LU PEN 14 3 ge EL DBI5D Nj 2 4D 40 2 DUIN i M ya b DB 4D Y S lo WIE D I l 12 5 M ys LI DBI3D e AW wo L BN Li d le AN LE DBI20 Ww no BN spes x ELE 9 8 3i N I 3 a gp NI 1 EN _ ei _ seta el SE 74HCT541 j O DBL15 00 ann MODID O E api ye HO
46. Manual Contents This manual has three chapters and two appendixes e Chapter 1 Introduction summarizes manual contents warranty status specification compliance and includes a description of the breadboard module e Chapter 2 Configuring the Agilent E1490C describes module hardware and dimensions explains how to install the breadboard and terminal module terminal module options and discusses operation of the backplane interface circuits on the module It also provides a typical application example showing user circuits connected to the backplane interface circuits Chapter 3 Using the Agilent E1490C shows how to use the module in a VXIbus system e Appendix A Agilent E1490C Breadboard Specifications lists the hardware specifications for the Agilent E1490C module Appendix B Parts List Component Locator and Schematics provides Agilent part numbers and descriptions of all parts supplied by Agilent Technologies A complete component locator and schematic of the Agilent E1490C digital backplane interface is included Specification Compliance Warranty WARNING The Agilent E1490C Breadboard Module is designed in full compliance with the VXIbus System Specification Revision 1 4 To prevent shock use only wire rated for the highest input voltage and disconnect all field power before removing terminal block cover or assembly Do not exceed 125 VACrms or 150 VDC on the terminal module connector The Agilent E1490C
47. OS e 5 z 3 15 5 Kam R Cext T C101 DB4 6 15 4 ir era Eeer 14 T1 DB5 7 14 5 8 Cext gt 086 gi 13 6 Hs 4 75 1 kon x ES DB7 9 12 7 R108 pun 9 P3 os e PIO 4 75K VD 4 2 4 s e U101B OT oj 1 213 6 7 VD EN si C1 n S DBO 2455 4198 8 9 10111 12 415 CONNECT TP191 Der 32218 9 R116 DB2 4 17 10 4 75 R117 419 r DB3 5 16 11 R114 4 75K U110 DB0 15 DB4 6 15 12 4 75K R115 1 DB5 7 14 13 R112 nre 4 75 Z 1 DB6 8 13 14 4 75K DB7 9 12 15 4 75K za F101 L101 R111 2 BER BE R110 4 75K 1063 02 el 36403 4 75K z T 0 1 T 0 1 9 VD VD U107A YD EN U104A 8 OP al EU 18 PONE Y a pe 8 2 4 16 R118 YO 10 6 14 R119 4 75K 7 7 cl Tre 11 8 12 4 75K Hor CRESET m id 5 5v 1D 6 U111 13 01020 ol U102C R R120 1 PIACK O ye R121 4 75K 2 4 75K j 4 IRQ 5 19 U107B R122 6 N 4 75K R123 R iac eric Pg 4 75K 8 ee qq R125 o 13 13 A R124 4 75K E 14 15 5 4 75K VD 15 17 3 A Jeer NOTE DO NOT INSTALL Us U13 U14 1 d BE RP9 JM46 JM48 JM61 IN S E STATUS REGISTER 4 menw We Sen Ti H E EN ho mm 8 R128 1 NOTE IS EXAMPLE CIRCUITRY IS NOT R129 4 75K 2 i AVAILABLE ASSEMBLED ON A BOARD 4 75K i pal FROM AGILENT TECHNOLOGIES 5 j U108B 6 EN R131 7 12 11 H L ERS g Lr R133 332 R152 o E 14 15 4 75K VD 15 17 e CH NI I UT NI O0 Jojo a O
48. SO 1 V ONUS Ya MH59 x Q nee A_ O rai LAN KORI y L ri 4 mez MH60 O MH61 BEEN OT SZ PS A ien Wa gon 13 Pg 3 1 Pa l 1 Nes i pue BCLK10 O83 7 mese DOVDEPOx OF LO reas DBIZO 1 ERE MHE3 ws MHB4 I a TP29 Yo NI ga Lo vas 0 ipe DEVDBPIK 0220 rea 8 1 l YON L men MHEG MH67 Eye E S BI OLA DBC80 1 K x a Ys Ny VIT O 0 ea puren 022 rpap ra 1 9 Jwen T ZO An SERDAT O82 7 wes Danae o8 7 ras DES Cy 73 you gan Bai 1 2 I j Pg 1 YON 10 x l m Jwe ZO MH23 SERCLK O TP66 DEVDEP4X OT 1950 Drun Z Z 13 Don om l P 1 E DTACK OPE D men DOVTYPEK O resi 5 LEN DBLIIUI ki ANS ud W e Pg 1 1 Pg 2 LAN TP 5 dou gou go Passan oO sies BSYSOLK OM reo 12 LON l ex ae wen DBL1211 FRONT PANHL CONNECTOR deer Va me Lei Jm O ru 13 I l O Po 2 MH 1 Yo LBUSA0 O22 A LBUSCO E Dati3 Ya or m B Ju D oq O wr 1 33 85 ome um gate MHI 4 Al aoe BI 24 a ea a Jr um l MH84 1 WES LBUSA1 LBUSCI D DBC1401 Ae B2 Ce k 49 E g 81 NU EN TON ES N a al SN 65 M pausas o2 l wis LBUSC2 oO MHI4 x ME 2 fu E Cw CT E Com jwen aki x os BUSU A wt ME a asf 32 UNES 9 we d 32 LBUSA3 mee LBUSC3 B MHIS lt a B 4 d 38 KR 36 70 68 i tds I LON pow iz Pg 2 al s ES N x o 53 Ja La J a NM LBUSA4 of ym LBUSC4 o CO MH18 O rou MENL EN EN Pe 3 N 41 3 73 n LON 1 1 PE vs L bg egeo nam D ca IER MH95 MH94 LBUSAS MH20 LBUSCS V a 10 8 Bib 42 N ay E 7
49. ST AS V 14 RST 6 5 SET 6 5 SET RESET RESET 2 BER N Configuring the Agilent E1490C 49 Chapter 3 Using the Agilent E1490C This chapter shows how to use the backplane interface circuitry on the Agilent E1490C Breadboard Module This chapter includes e Reading Data From Registers Page 51 e Writing Data to the Control Register Page 54 e Using Interrupts Page 57 e Resetting the Module Page 59 e Detecting Errors eremo nee e EE E Page 59 e Using Other Power Supplies Page 60 e Example Programs ccs Ve nied ones bem Page 61 Reading Data From Registers Status Register Bit Definitions The breadboard module contains circuitry for three readable registers as defined by the VXIbus Specification Status Register D Register Device Type Register Table 3 1 shows the Status Register bit definitions It will be used as an example of how to read from a register on the breadboard module As shown in Table 3 1 only four of the sixteen bits in the register are predefined by the VXIbus Specification The other twelve bits are device dependent That is they can represent any condition that you define The inputs
50. VCC VCC VCC VCC VCC VCC E NORMA vce ACKX B20 L l E J TACKIN Be l 2 2 2 2 2 2 ACKOUT Xie 8 8 5 3 S 5 RI wea TTLTRGOX Se pa TTLTRG2x 3 3 3 3 2 f 2145 IR e SS 1 1 Si SS 1 ta O IROX Beb TTLTRG4X TO PAGE 1 B27 T GE a c 67x CC CC S SE re GND GND GND GND GND WE a GND ces 2 4 U21A B23 FS CC ps eR E VCC V RB ld 5 Sa B30 x gt CLK 5 IRG 1 e 8 NN o t KO He de 5 o PIACKK je 84 TO 36 cde 5 5 3 r E ab an 5 B32 5 ce 5 SUMBUS wi cc sel le Pg 1 4 13 Ai e m 9 5 3 8 HRESET O b t 1 74HC74 3 3 q 21 20 DBEINX gt 1 1 gt 1 10 J 3 GND GND GND GND GND GND S L z GN VCC T IRO gt Ra ug PIACKx 30 1K DBENX ACKADDR o Behan gt m van z IRO 2220 LATCHX LACKINK OL 4 SEIS LIVE Tel can A I AS E 8 E AR Ry 3 CARDADRX Uu i P x eso ma DIKINE o 3 REA Ee 1 A CARDADRK o7 D51 LI B D50 10 10 A n H1430B BREADBOARD MODULE P 13 AK BSYSCLK 2 ZE DAG a DO po VXI INTBRFACE LOGIC UI5F FILTERING AND USER CONNECTIONS 74HCT14 7 racy ES el LA i POWER SUPPLIBS MISC GND E a 1ROX 5 O DTACK sheet 2B PT l 19 TACKOU 8 D51 OP TACKOUT 18 7 ACK e VISA DTACK gio DTACK WR ac BS vr BEN D gt E 2 SA y 3 PALVMBIFC 50x OF WE ZR 2 lt 562 Se e fo O TACKOUT SYSCLK o f BSYSCLK o Appendix B Agilent E1490C Schematics
51. ai Componer Kek Without Insulating Ek p 3 2mm 0 125in Grid Hole Spacing 2 5mm 0 1in SIDE VIEW OF COMPONENTS Figure 2 2 Agilent E1490C Dimensions Chapter 2 Configuring the Agilent E1490C 17 q lee toj 325 85 r 10 te POSO Dao SE tt tt eee n EE ES m ez e 1996 623 X 111 X R555 36 59 174 84 26 I ES W yp BUH SIDES 242 1 PI PS 150 5 SEI 635 X 2032 rj E AA DEER j i A A eg EEN O A S rar UC NC DEO DT lt S 1 17 7 tf 3 814 l I n l 111 X V 2223 105 41 NITES 8921 1 TOLERANCES 115 57 i PUNCHED HOLE 4008 HOLE TO HOLE 4025 l y Lo HOLE TO EDGE 03 i 227 35 1 l EDGE TO EDGE 04 a 3x 80701 HOLE TO FOLD 404 EDGE TO FOLD 05 ax n714 FOLD TO FOLD 404 l d l l l l l 1 E on on REOS e ee e J 2x 119 38 Pes MAX FOLD RELIEF ex 23876 4 PLACES 35 56 281 94 341 85 Figure 2 3 Agilent E1490C Top Shield Dimensions DETAIL A 031 THRU sg 06 DEEP DETAIL A 1 Dimple 6 Places amp H X Q R1 98 2 Places 8 73 Fold Relief Q NOTES CD UNLESS OTHERWISE NOTED INSIDE FOLD RADIUS R 0 38 TOLERANCES PUNCHED HOLE 0 08 HOLE TO HOLE 025 HOLE TD EDGE 03 EDGE TO ED
52. ane address lines 2 This is a read operation so READ must remain false 1 to provide the second half of the U24 U25 enable function WRITE 3 Set IACK false 1 to enable address equality detector U18 4 Set both data strobes DSO and DS1 true 0 to indicate a 16 bit data transfer Table 3 2 Backplane Address Lines Status Register Line s Data Required Lines A1 A3 Must be set low high low 010 to select the BASE 4 enable line BASE 4 provides one half of the enable function for line drivers U7 U8 See Table 2 2 on page 34 Lines A4 A5 Must both be low 0 to enable 3 to 8 line decoder U21 Lines A6 A13 Must equal the logical address of the module as set on DIP switch SP1 Lines A14 A15 Must always be set high 1 to access the upper 16K of address space Lines AMO AM5 Must be set to either hexadecimal 29 10 1001 or hexadecimal 2D 10 1101 Refer to the VMEbus Specification Table 2 3 and the VXIbus Specification Rule C 2 10 Line LWORD Must always be set false 1 since this is a D16 device short word transfer 16 bits Figure 3 2 shows timing required for the PAL U9 control and signal lines 52 Using the Agilent E1490C Chapter 3 R W PAR np n t n oec Maris ANE Se T Gan MAN d VERRE ATI o III 8 J DTACK 125 62 5 62 5 62 5 10 10 NOT
53. bled and the address latch is released In the next state DTACK is released and the state machine returns to the idle state If the DTACK INHibit signal DTKINH is set high hard wired low on the Agilent E1490C implementation the user can hold the state machine in the first state of latched address and enabled data bus drivers 42 Configuring the Agilent E1490C Chapter 2 Interrupt A priority interrupt scheme has been implemented using the PAL U9 Another state machine within the PAL controls interrupt request and acknowledge operations See Figure 2 26 for the following discussion The VMEbus interrupt request levels IRQ1 IRQ7 are jumper selectable only one at a time allowed for both the IRQ REQUEST output line and the IRQ ACKNOWLEDGE input line The IRQ REQUEST and ACKNOWLEDGE levels must always be the same level As implemented to generate an interrupt request to the interrupt handler the user s custom circuits must provide a low going signal at the IRQ access point This latches the IRQ signal The output of the Latch U15 drives the IRQ input on PAL US starting the IRQ state machine in the PAL The IRQ state machine monitors the IACK valid DSO IACKIN AS and ACKADDR interrupt related lines to determine its actions If the module is asserting IRQ and the interrupt related lines are in the proper state the IRQ state machine asserts IRQX true on U9 IRQX true pulls the jumper selected IRQ1 line true on the backpla
54. ce Representatives today Talk to a live person 888 88 SOURCE 888 887 6872 Contact us by email sales artisan scientific com Visit our website http www artisan scientific com
55. cification Section C 2 1 1 2 for detailed information concerning Control Register implementation restrictions A programmable array logic IC PAL provides the timing and control signals for standard data transfer cycles and interrupt requests acknowledgements Hardware and software reset signals together with a card fail signal have also been implemented The Data Transfer ACKnowledge DTACK circuitry is centered around the PAL U9 A state machine in the PAL controls all read and write data transfer cycles Operation begins with the state machine in the idle state See Figure 2 25 for the following discussion In the first part of the transfer cycle the system controller places the address of the breadboard module on the backplane address lines A1 A15 and address modifier lines AMO AMS and then sets the appropriate data strobe lines true DSO and DS1 for a D16 device When the address equality detectors U17 U18 detect the address match the output of U17 goes low This low is felt at the Card ADDRess CADDR input to U9 which together with the active data strobes tells the DTACK state machine in the PAL that the module has been addressed for a data transfer cycle This starts the state machine with all signals being clocked by SYSCLK 16 MHz In the first active state the data bus drivers U19 and U20 are enabled and the register specifier part of the address A1 A5 is latched onto the outputs of U8 using the Data Bus
56. cond for adequate cooling and 2 the pressure drop that occurs across the module when the specified airflow is applied Module cooling requirements are described in the VXIbus System Specification Rev 1 4 in Section B 7 2 4 Mainframe cooling requirements are discussed in Section B 7 3 5 For ease of integration you should label the airflow requirements for your finished application circuitry on an outside shield of the module For example the label might read 0 3 liters sec 0 2 mm H2O Due to the nature of a breadboard module it is not possible to specify cooling requirements without knowing the application and the amount of power to be dissipated Given the application however cooling requirements may be estimated as follows 1 Determine the airflow required as a function of power dissipation To maintain a 10 C rise approximately 0 08 liters second are required for every watt dissipated For example if a module dissipates 20 watts 1 6 liter second of airflow is required for cooling 2 Establish the relationship between airflow and pressure drop For a breadboard loaded with typical components such as ICs relays and a few heat sinks the curve shown in Figure 2 11 may be used to determine the pressure drop across the module Determine the pressure drop as the intersection of the curve and the required airflow For example if the airflow required is 1 6 liter second the pressure drop is approximately 0 04 mm H20 A
57. dentify the desired state of all the relays The state of all relays must be specified simultaneously To change just one relay it is necessary to change the one bit that corresponds to that relay in the stored configuration pattern and send the entire pattern again The system controller places the 16 bit relay configuration word onto the backplane data bus DO D15 and transfers it to the breadboard module during a normal write data transfer cycle as described on page 35 The data is passed to the module s internal data bus DBO DB15 when the module is correctly addressed In this application DBO DB15 are connected to two drivers U105 and U106 which are clocked by the BASE 8 low enable line address selection Chapter 2 Configuring the Agilent E1490C 47 Since this is a write operation LATCH goes true for one clock cycle as part of the data transfer cycle With both BASE 8 and LATCH set low the output of U101A briefly goes high clocking the relay selection bit pattern onto the outputs of U105 and U106 which are not yet enabled The outputs of U105 U108 are enabled by the following path The output of U101A is also applied through U101B to U103A a monostable multivibrator When LATCH returns to its normally high state after one clock cycle U101A output goes low and the U101B output goes high triggering U103A U103A produces a low going output pulse at pin 4 Q that enables the outputs of U105 U108 The re
58. ductor Corp Santa Clara CA USA 95052 28480 Agilent Technologies Corporate Palo Alto CA USA 94304 32997 Bourns Networks Inc Riverside CA USA 92507 34371 Harris Corp Melbourne FL USA 32901 50088 SGS Thomson Microelectronics Inc Phoenix AZ USA 85022 56289 Sprague Electric Co Lexington MA USA 02173 75915 Littelfuse Inc Des Plaines IL USA 60016 81073 Grayhill Inc La Grange IL USA 60525 Backplane Interface The E1490 66511 component locator is on page 67 See Chapter 2 for Component Locator Backplane Interface Schematic interface groups information on individual interface groups Schematics begin on page 68 See Chapter 2 for information on individual 66 Agilent E1490C Parts List Component Locator and Schematics Appendix B 67 loo ES Cf a D 3 E u Oo T5 c dan an a 58 le TPS Cl TP64 6 Dol Gal d Jd 89dl 0941 Stol 2941 an Leal e cn See y cdl GBid 8 81 68141 I6ldl Beal To
59. e If the user wants the module to notify the interrupt handler when the relays are settled note that the trailing edge of the Q output pulse from U103 will also clock U104 This produces a high at IRQ When the PAL U1 senses the high at IRQ it starts the IRQ state machine notifying the interrupt handler via IRQI on the backplane that in this case the relays are settled out The system controller can then either poll the Status Register to check the busy bit or it can assume the bit is cleared and proceed To reset U104 and remove the high on IRQ the system controller must drive CRESET true while PIACK is true as part of the interrupt acknowledge cycle U102C and U102D accomplish the reset 48 Configuring the Agilent E1490C Chapter 2 e BASE 8 m AU Ts cece U109 3 U101A C1 LATCH DI 5V DBO 2 19 0 R102 e pei 3 Hee vie i 4 75K RI03 i L R101 10K 0833 163
60. e 40 Component area 11 63 height 11 17 63 lead length 11 63 list of manufacturers 66 Component Locator 67 Configuring for interrupts 57 the E1490C 13 48 Connecting breadboard to mainframe 25 field wiring 29 30 terminal module to breadboard 31 Connections terminal module 26 29 30 Connector 11 backplane 16 schematic 69 crimp and insert 28 front panel schematic 71 terminal module 17 Control Register access points 40 54 backplane address lines 55 bit definitions 41 54 SYSFAIL INHBT line 44 timing for writing to 56 writing to 10 40 41 54 55 61 Agilent E1490C User s Manual Index 73 C continued Control Signals 44 Cooling Requirements 22 CRESET 44 59 access point 59 Crimp and Insert accessories 27 connectors 28 contacts 27 28 option A3E 11 tools 28 Custom Circuitry 47 49 controller notification 48 relay selection 47 D Data buffering 35 bus drivers 8 35 enable DBEN 35 41 lines 8 35 reading from registers 51 strobe lines 41 44 transfer acknowledge circuitry 41 signal 10 writing to control register 54 55 DBEN 35 41 Description 8 Detecting Errors 59 Device Classifications 38 Device Type Register bit definitions 39 disabling 42 reading 10 38 53 61 Dimensions module 17 Documentation History 4 DSO 41 44 true 52 55 DS1 41 44 true 52 55 57 DTACK 41 circuitry 41 42 INHibit DTKINH 42 DTACK 10 tru
61. e 41 42 E ECL Trigger 45 Errors detecting 59 Example Programs 61 F Field Wiring 29 30 Front Panel Connector Schematic 71 G Generating Interrupt Requests 57 Grid Hole Specifications 63 H Handling Precautions 13 Hardware description 14 features 11 reset 59 HRESET 44 59 IACK false 52 55 true 32 43 IACKIN 10 signal 57 through IACKOUT 44 57 true 43 IACKOUT 10 44 passing IACKIN through 57 ID Register addressing modes 38 bit definitions 37 device classifications 38 disabling 42 reading 10 37 53 61 Installing Breadboard in Mainframe 25 Interface circuitry 32 ECL trigger 45 features 8 schematic 70 74 Agilent E1490C User s Manual Index continued Interrupt circuitry 43 configuring for 57 interface 10 priority 10 24 43 57 request levels 43 57 requests generating 57 using 57 Inverse Logic 8 IRQ ACKNOWLEDGE input line 43 57 jumper 24 43 57 REQUEST output line 43 57 J Jumpers interrupt priority 24 43 57 L LADDR 23 LATCH 55 output low 42 LATCH 40 Lead Length 11 17 Logical Address 23 LWORD 34 Mainframe cooling requirements 22 installing breadboard 25 Maximum component height 11 63 component lead length 11 17 63 power dissipation 63 Metal Standoffs 20 21 Mnemonic Asterisk Suffix 8 32 O Option A3E 11 27 P Parts List 65 66 PC Board Standoffs 20 21
62. e of the breadboard columns A B and C row numbers 1 through 32 correspond to the pin numbers on the J2 connector and the silkscreened numbers on the terminal module A20 B25 etc For example A20 on the terminal module matches to column A row 20 on the breadboard module Refer to the breadboard schematics in Appendix B for additional pin wiring information Module Dimensions Figure 2 2 shows the dimensions of the module and the component height and lead length restrictions As shown the maximum component height allowed above the circuit board is 18 0 mm 0 71 inch The maximum component lead length allowed below the circuit board is 3 2 mm 0 125 inch If you need more lead length provide insulation or add standoffs as described on page 20 Do not mount components closer than 4 mm 0 16 inch to the extreme upper or lower edges of the printed circuit board This space is used for shields and to guide the module into the mainframe module slot An area of 460 cm 72 inch is available on the module to install your own circuitry This area does not include the portion of the printed circuit board required to install the backplane interface components 22mm 8 6in 11 5mm 4 5in a Tole 12mm 4 75in 2 5mm lin Grid Hole Inside Diameter 00007 117mm 0 046in Coss 0006 I adum Vee Length M
63. ectors The 5 and 5 2 Vdc interface supplies are fused and filtered 2 Vdc is used but not fused You should fuse and filter all other power supplies used Table 2 12 Power Supply Voltage and Pin Numbers Voltage P1 Connector Pin Voltage P2 Connector Pin Numbers Numbers 5Vdc A32 B32 C32 5 2Vdc A7 A13 A19 C4 C19 5Vstdby B31 24Vdc C31 12Vde C31 24Vdc C32 12Vdc A31 2Ndc A2 C13 All ground pins connect together no ground loops are present in the module The shields are not grounded but access points are provided at the standoffs to connect the shields The front panel connects to the shields Unconnected heavy traces are provided at the circuit board edges for bussing power supplies and ground to custom circuitry This section contains an example which shows one way you can install custom circuitry on the Agilent E1490C breadboard module The example shows a 16 channel general purpose relay application See Appendix B and the fold out on page 49 for the following discussion For this sample application Form C general purpose relays are used that have SET and RESET modes of operation Writing a 1 to a particular relay driver U105 or U106 SETs the relay and writing a 0 to the driver RESETS the relay The system controller specifies which relays are SET and which are RESET by writing an entire 16 bit word of 1 s and 0 s to the module to i
64. et signals are provided to initialize the backplane interface circuitry and your own custom designed circuitry to a known state See page 59 for information about resetting the module Backplane Buffering Buffering is provided for all signals that interface with the VXIbus backplane See page 32 for information about backplane interface circuitry Power Supply 5 Vdc from the backplane is fused at 4 A and filtered for use on the module The 5 2 Vdc is also filtered Other backplane voltages are available See pages 47 and 60 for information about power supplies 10 Introduction Chapter 1 Agile nt E1490C An overview of the Agilent E1490C hardware features follows Hardware Features e Connectors A 96 pin DIN connector connects to the terminal module Crimp and Insert terminal module connectors are available with Option A3E e Component Area An area of approximately 460 cm 72 inches is available on the module to install your own custom circuitry This area does not include the portion of the circuit board required by the backplane interface components Component Height Lead Length The maximum component height allowed above the circuit board is 18 0 mm 0 71 inch The maximum component lead length allowed below the circuit board is 3 2 mm 0 125 inch WARNING Since inputs to the Agilent E1490C Breadboard Module are through a 96 pin DIN connector and a terminal module assembly limit voltage to 250 Vdc 250 Vrms
65. ffer 27014 74F38PC U6 1820 3100 1 IC Decoder 01295 SN74ALS138N U7 1820 3079 1 IC Decoder 28480 1820 3079 U8 U24 U25 1820 4147 3 IC Latch 34371 CD74HCT573E U9 1820 6731 1 IC ASIC Gate Array 27014 SCX6BO4ACE N9 U10 U14 1820 4586 5 IC Driver Receiver 01295 SN74HCT541N Table B 1 is continued on next page Appendix B Agilent E1490C Parts List Component Locator and Schematics 65 Table B 1 Agilent E1490C Breadboard Parts List continued from previous page Reference Agilent Total Designator Part Qty Description Mfr Code Mfr Part Number Number U15 U16 1820 4242 2 IC Schmitt Trigger 34371 CD74HCT14E U17 U18 1820 3631 2 IC Comparator 27014 MM74HCT688N U19 U20 1820 3714 2 IC Transceiver 01295 SN74ALS245A 1N U21 1820 3081 1 IC FF CMOS 01295 SN74HC74N U22 U23 1820 3399 2 IC FF CMOS 01295 SN74HC273N Table B 2 Agilent E1490C Code List of Manufacturers Mfr Code Manufacturer s Name Manufacturer s Address Zip Code 00779 Amp Inc Harrisburg PA USA 17111 01295 Texas Instruments Inc Dallas TX USA 75265 04222 AVX Corp Great Neck NY USA 11021 06776 Robinson Nugent Inc New Albany IN USA 47150 11236 CTS Corp Elkhart IN USA 46514 18873 DuPont E De Nemours 8 Co Wilmington DE USA 19801 26742 Methode Electronics Inc Chicago IL USA 60656 27014 National Semicon
66. frame and to all external devices connected to the mainframe or to any of the modules For electrical shock protection ensure that the module faceplate is securely tightened against the mainframe Since inputs to the Agilent E1490C Breadboard Module are through a 96 pin DIN connector and a terminal module assembly limit voltage to 250 Vdc 250 Vrms STATIC SENSITIVITY The backplane interface circuitry described in this chapter uses static sensitive CMOS integrated circuit devices If you implement the circuitry described herein you must use clean handling and anti static techniques when handling the module to protect the sensitive components from damage due to electrostatic discharge ESD Chapter 2 Configuring the AgilentE1490C 13 Reduci ng Risk of The smallest static voltage most people can feel is about 3500 V It takes Static Di scharge less than one tenth of that about 300 V to destroy or severely damage Dama ge static sensitive circuits Often static damage does not immediately cause a malfunction but significantly reduces the component s life Adhering to the following precautions will reduce the risk of static discharge damage e Keep the module in its conductive plastic bag when not installed in a VXIbus mainframe Save the bag for future module storage Before handling the module select a work area where potential static sources are minimized Avoid working in carpeted areas and non conductive chairs Keep body m
67. ictions Device Type The Device Type Register is a 16 bit register which contains a Reg ister device dependent module type identifier and a memory required field for A24 and A32 devices only These two fields are set on the module by the use of switches SP4 SP5 on the inputs to the data bus line drivers U14 and U13 as shown in Figure 2 23 Each bit in the Device Type Register is normally pulled high 1 by RP7 and RP8 The bits can be reconfigured by closing switches SP4 and SP5 The range of device types for an A24 or A32 device is 0 4095 For an A16 device all 16 bits are available for specifying the device type for a range of 0 65535 Note Per the VXIbus System Specification OBSERV ATION C 2 6 module codes 0 255 are reserved for Slot 0 devices 38 Configuring the Agilent E1490C Chapter 2 DEVICE TYPE REGISTER Pg 1 4 DEVTYPEX READ RPB 4 7K Pg 1 4 a S ms o x um we olulo a lu m ojolu oja uo mn les RP 4 7K 74HCT541 VCC U13 d eia wlo ojos ofua a u m ro o noan as o 4HCT541 Figure 2 23 Device Type Register See Chapter 3 for additional information on using the Device Type Register Refer to the VXIbus
68. igure Features 1 1 Note For hardware operation a mnemonic suffixed with an asterisk such as WRITE indicates inverse logic 0 or low true 1 or high false A high state 1 is defined as a positive voltage usually 5 V and a low state 0 is defined as zero V ground at the specified signal point The Agilent E1490C interface features are Address Lines and Register Decoding The module implements 15 address lines A1 A15 allowing 1 decoding one of 255 switch selectable logical device addresses in the upper fourth of the A16 VME address space and 2 selecting one of the breadboard configuration registers for read write operations The module decodes the address modifier lines AMO AMS and acts on codes 2916 and 2D16 only See page 32 for information about address lines and register decoding e Data Lines Data lines DO D15 are available for use on the breadboard module These 16 lines are buffered by data bus drivers and used for writing to and reading from the configuration registers Status ID Device Type and Control via an internal data bus DBO DB15 See page 35 for information about data bus drivers and data lines 8 Introduction Chapter 1
69. igure 2 8 Dimensions of Amatom s 19968 SS 350 Standoff 20 Configuring the Agilent E1490C Chapter 2 In Figure 2 9 the standoffs are installed between the PC board and the top shield The 30 mm hex standoff shown may also be ordered from the address shown in Figure 2 10 With the recommended standoffs installed this configuration extends the maximum component height above the circuit board from 18 mm 0 71 inch to 48 mm 1 89 inch Eight standoffs are required per module all eight standoffs are installed on the same side of the PC board E ir Screw Top Shield u j C U Bottom Shield ee Ise Standoff Amatom P N 19979 SS 350 Figure 2 9 Agilent E1490C with Tall Standoffs Added 95mm 37 in CH 1 1 2 threads Manufacturer s Address AMATOM N ma aeaa a ZE D Cum 1 800 243 6032 DN d Quantity Required 8 per module M50 x 0 5 SEH an G i Figure 2 10 Dimensions of Amatom s 19979 SS 350 Standoff Chapter 2 Configuring the Agilent E1490C 21 Cooling Requirements Note The VXIbus System Specification requires module manufacturers to establish a cooling specification for each of their modules The specification is to consist of 1 the airflow required in liters se
70. inal Module Option A3E o ee ee 27 Crimp and Insert Terminal Module Accessories oaoa 27 Single Conductor and Contact 27 Shielded Twisted Pair and Contact 27 Jumper Wire and Contacts 28 Crimp and Insert Contacts 28 Crimp and Insert Tools 28 Extra Crimp and Insert Connectors s ooo 28 Wiring a Terminal Module ene non 29 Attaching a Terminal Module to the Breadboard 31 Backplane Interface Coup 32 Address Lines and Register Decoding o o o 32 Data BUS geg o 44 ayi e iye Mt AE e ago ip ap e RR W tp di 35 Stats Register 2 45 0 6 po DG a EU ee oe aen 36 ID REZISTE ip ut ache sok amp 213078 Soe ee BS a A Sa e Gee on 37 Agilent E1490C User s Manual Contents 1 Chapter 2 Configuring the Agilent E1490C continued Device Type Register eee eee Control Register iii eS ne YD ox eve ds eyed DTACK Interrupt and Control ln DENCK kai en AREE NNUS e at nce a InterrUpt Sr cu e eee cS Susu tunay tk Rua e SUS Bee wee Gontrol sgan rn en aqu RET p BCE Tigger Logie VAN sii e siz ae eio h up buah apes User Access Ponts Power Supplies Custom Circuitry s Ql u ua ER AA AAA Relay Selection 5 3 5 esye a e need eeu Notifying the Controller llle Chapter 3 Using the Agilent E1490C Reading Data From Registers Status Register Bit Definitions
71. inches Grid Hole Spacing 2 54 mm 0 1 inch Grid Hole Inside Diameter 1 17 mm 0 046 inch Maximum Component Height 18 0 mm 0 71 inch above PC board Maximum Lead Length 3 2 mm 0 125 inch below PC board Maximum Power Dissipation per module Determined by mainframe cooling Cannot exceed the number of watts per slot total cooling capacity available Backplane interface circuitry consumes 1 75 watts Power Supplies 5 VDC Q 350 milliampheres is required for full backplane interface circuitry Other backplane voltages available as stubs on the module are 5 5 VSTDBY 5 2 V 12 V 12 V 24 V 24 V and 2 V Terminal Module Connector Maximum current 1 0 Amp Derate to 100 mA when using PC board traces Appendix A Agilent E1490C Breadboard Specifications 63 Notes 64 Agilent E1490C Breadboard Specifications Appendix A Appendix B Agilent E1490C Parts List Component Locator and Schematics Table B 1 lists the Agilent E1490C backplane interface circuitry components See pages 68 through 71 for the schematics To order a part contact Agilent Technologies or the vendor listed in Table B 2 and quote the manufacturer s part number desired quantity and the description Table B 1 Agilent E1490C Breadboard Parts List Reference Agilent Total Designator Part Qty Description Mfr Code Mfr Part Number Number C1
72. ing the DIP switches the user selects hardwired configurations for these items See page 38 for information about the Device Type Register Control Register Writing to this 16 bit register causes specific actions to be executed by the device Reset and System Fail Inhibit are implemented Other device dependent control bits may be implemented by using the remaining device dependent bits See page 40 for information about the Control Register Read Write Operations Using the backplane interface circuitry provided it is possible to read the contents of the Status ID or Device Type Registers onto the data bus DO D15 or to write information into the Control Register from the data bus See pages 51 54 for information about reading from and writing to the registers DTACK The interface contains the circuitry required for generating a delayed DTACK data transfer acknowledge signal See page 41 for information about data transfer acknowledge DTACK circuitry Interrupt Interface The breadboard module has D16 interrupter capability It does not contain an interrupt handler Interrupt priority is jumper selectable for pulling the appropriate interrupt request line IRQ1 IRQ7 Interrupts are generated by the IRQ state machine on the DTACK interrupt control IC The daisy chained IACKIN TACKOUT signal pair is implemented See pages 43 and 57 for information about interrupt circuitry Module Reset Both hardware and software res
73. ircuitry can decode the entire module address space This can provide up to 32 registers maximum If additional decoding is necessary A4 and AS are accessible on the module See Table 2 2 Table 2 2 Register Selection A3 A2 A1 Enable Line Register 0 0 0 Base 0 ID 0 0 1 Base 2 Device Type 0 1 0 Base 4 Status Control O 1 1 Base 6 User Assignable 1 0 0 Base 8 User Assignable 1 0 1 Base A User Assignable 1 1 0 Base B User Assignable 1 A 1 Base C User Assignable 34 Configuring the Agilent E1490C Chapter 2 Data Bus Drivers The Agilent E1490C breadboard module is designed to be used as an A16 and a D16 device only As such only backplane address lines A1 A15 and data lines DO D15 have been implemented on the module VXIbus backplane connector J1 contains 16 bi directional data lines labeled DO through D15 The module connects to these data lines using the circuitry shown in Figure 2 20 E WRITE gt lt READ a a E e Es DATA BUS BUFFERS E m m St READX Pg 2 4 READ vcc I DLO DBLO 2 DI 3 Dti DB 2 4 la e DI DB 3 5 a y DO Y DB 4 6 a DU DBCS e DIS kv pri 8 Pg a DIB Y DBC 9 a D7 10 d ACKADDR i3 l uly DIR vee DB 8 2 D 8 2 T 7 18 DB 8 w DBIS 3 VINA x Y mn 4 x DC9 3 a 1
74. irely using jumpers Your system controller and or interrupt handler must react to the signal timing in the PAL U9 for the IRQ and DTACK state machines as shown in Figure 3 5 e The circuitry provided implements a read operation for only the lower eight bits of status ID during the interrupt acknowledge cycle using PIACK to enable buffer U10 If you want to use the upper eight bits also you must provide an additional buffer to the internal data bus that is enabled by PIACK true and DS 1 true For testing purposes only move Jumper J3 from the NORMAL position to the TEST position In the TEST position an interrupt can be generated by writing a 1 to Control Register bit 2 In the NORMAL Position Control Register bit 2 can be used as a user signal CTL2 Chapter 3 Using the Agilent E1490C 57 vi III u a SYSCLK 16MHz WN IRQX icit UA gen UU NN o AN UA PIACK 7 DSO DSO DS1 I Data Valid 7 DBEN T s DTACK Ln 40 125 ug 62 5 62 5 10 10 A DTKINH high will hold DTACK cycle here and will stay here until DTKINH goes low Sync signals with SYSCLK Figure 3 5 Interrupt Timing 58 Using the Agilent E1490C Chapter 3 Resetting the Module A reset signal is provided to initialize the backplane interface circuit and your own custom designed circ
75. lace Clear Cover A Hook the top cover tabs ka onto the fixture l B Press down and tighten SCrews AS HP E1490C Module Extraction Levers Push in the Extraction Levers to Lock the Terminal Module onto the Breadboard Sie E Figure 2 17 Wiring the Terminal Module continued from previous page Chapter 2 30 Configuring the Agilent E1490C Attaching a Terminal Module to the Breadboard SE Extend the extraction levers on the Extraction Lever e I N AN e Use small screwdriver to release the two extraction levers PM Align the terminal module connectors to the Agilent E1490C breadboard module NS x S S S e Module Extraction Lever 3 Apply gentle pressure to attach the terminal module to the breadboard module Push in the extraction levers to lock the terminal module onto the breadboard module E Extraction Levers To remove the terminal module from the Agilent E1490C breadboard use a small screwdriver to release the two extraction levers Push both levers out simultaneously to free the terminal module from the breadboard module J Figure 2 18 Attaching a Terminal Module to the Breadboard Chapter 2 Configuring the Agile
76. lay configuration bit pattern is then applied through U109 and U110 to the relay SET lines U109 and U110 invert the bit pattern and provide current sinks for the selected SET relay coils A 1 at the output of U105 U106 energizes a SET relay coil while a 0 is ignored The outputs of U105 and U106 are also applied to U107 and U108 which place the inverse of the relay selection bit pattern on the RESET lines of the relays through U111 and U112 U111 and U112 provide current sinks for the RESET relay coils Since the inverse state is applied to U111 and U112 those relays not SET are RESET Notifying the For this application only one bit is needed for the Status Register Pin 13 Controller Q output of U103A is connected directly to the SR7 bit line on TP191 This bit is normally always kept low and is used as the module busy bit when set high When U103A produces its low going output pulse at pin 4 Q it also produces a high going output pulse at pin 13 Q The duration of these two pulses is controlled by the values of C101 and R101 which for this application is about 11 ms slightly longer than the settling time of the relays The Q pulse sets the busy bit high in the Status Register while the relays are settling If the system controller polls the module while the relays are still settling to see if the relays are configured yet it will see the busy indication and can do something else while it is waiting for the relays to settl
77. le as access points either as inputs from the backplane to your own custom circuitry or as outputs to the backplane from your custom circuits Table 2 11 User Access Points Implemented Signals Signal Lines Description BA1 BA5 Buffered Backplane Address Lines A1 A5 ID ID Register Enable Line DEVTYPE Device Type Register Enable Line STATUS Status and Control Registers Enable Line REGO User Assignable Enable Line REG1 User Assignable Enable Line REG2 User Assignable Enable Line REG3 User Assignable Enable Line REG4 User Assignable Enable Line CRESET Card Reset software CTLO or hardware SYSRESET CTL2 CTL15 Control Register Output Lines DBO DB15 Breadboard Module Internal Data Bus Lines DTACK Data Transfer Acknowledge DTACK high DTACK low HRESET Hardware Reset from SYSRESET IRQ Interrupt Request Line User Implemented LATCH Latches DBO DB15 onto user circuitry PIACK Peripheral Interrupt Acknowledge Line SRO SR1 Status Register user assignable SR2 Status Register Passed defined by VXIbus Spec SR3 Status Register Ready defined by VXIbus Spec SR4 SR14 Status Register user assignable BCLK10 BCLK10 Buffered CLK10 ECL level 10 MHz clock READ Enables User Data onto BDO DB15 46 Configuring the Agilent E1490C Chapter 2 Power Supplies Custom Circuitry Relay Selection Table 2 12 lists the power supply pins available from the P1 and P2 conn
78. move the 4 pin jumper Agilent P N 1258 0247 from the old priority location and reinstall in the new priority location If the 4 pin jumper is not used the two jumper locations must have the same interrupt priority level selected S Interrupt Priority Using 4 Pin Using 2 Pin Sion Jumper Jumper J IRQ IRQ o ra TEE FEX E 2 EN asse 3 O 3 aana A A Ke gxmm 5 xmmW b aeael 6 garaj amp seam 7 Bam 7 Beene X S Saal X Le Figure 2 13 Setting the Interrupt IRQ Priority 24 Configuring the Agilent E1490C Chapter 2 Installing the Breadboard in a Mainframe Refer to Figure 2 14 to install the breadboard in a mainframe is D Set the extraction levers out 2 Slide the Agilent E1490C into any slot except slot 0 until the backplane connectors touch Extraction Levers Seat the breadboard into the mainframe by pushing in the extraction levers L Tighten the top and bottom screws to secure the breadboard module to the mainframe NOTE The extraction levers will not seat the backplane connectors on older VXIbus mainframes You must manually seat the connectors by pushing in the module until the module s front panel is flush with the front of the mainframe The extraction levers may be used to guide or remove the breadboard Y To remove the breadboard from the mainframe re
79. ne The state machine then waits for the interrupt handler to recognize the interrupt request When the interrupt handler responds it places the code for the interrupt request priority level that it is acknowledging onto lines A1 A3 It then sets IACK true which sets IACKIN true IACK true starts the interrupt acknowledge cycle disabling normal address decoding on the breadboard module When IACKIN goes true the IRQ state machine sets DBEN true to latch A1 A3 into U6 Then it checks to see if its own IRQ level has been acknowledged input line ACKADDR at U9 will be set low by a correct match of U6 s decoded output and the jumper selection for IRO ACKNOWLEDGE ACKADDR r IRQ REQUEST LEVEL SELECT IRQ ACKNOWLEDGE Bal gd I LEVEL SELECT I 2 Ba 2 us Du l Anri i 2 45V SE SE ROIx B YI l 2 p 3 4 RQ2 BA3 3 13 ADDR2 3 4 5 6 MNT ADDR3 E 21 5 6 RQ3 Y3 5 6 IRQX 7 8 5V LI ADDR4 8 U9C Y zwa RQ4x ya 7 8 IRQX 18 3 L 6 x 10 ADDRS 9 e 10 B T 9 10 e RQ5X a 5 Gel YG GER tt 12 13 Hodge t4 RQ6 xG2B v AnD I 13 14 13 14 RQ T 15 16 15 16 15 16 15 16 An 7405138 E 31 Figure 2 26 Interrupt Circuitry Chapter 2 Configuring the Agilent E1490C 43 If its own level is not being acknowledged or if the module is not asserting IRQ the
80. ng of the manual is Edition 1 The Edition number increments by 1 whenever the manual is revised Updates which are issued between Editions contain replacement pages to correct the current Edition of the manual Updates are numbered sequentially starting with Update 1 When a new Edition is created it contains all the Update information for the previous Edition Each new Edition or Update also includes a revised copy of this printing history page Many product updates or revisions do not require manual changes and conversely manual corrections may be done without accompanying product changes Therefore do not expect a one to one correspondence between product updates and manual updates Edition T yc u LA yy Aue dette date ed December 1990 Editio 2 ei cc vh ae LEVE UU Nee eS want LE May 1992 Edition 3 Part Number E1490 90004 March 1996 Edition 3 Rev 2 Part Number E1490 90004 August 2006 Safety Symbols Instruction manual symbol affixed to product Indicates that the user must refer to the man N Alternating current AC ual for specific WARNING or CAUTION information to avoid personal injury or dam age to the product Direct current DC A Indicates hazardous voltages Indicates the field wiring terminal that must _ be connected to earth ground before operating t the equipment protects against electrical Calls attention to a procedure practice or con shock in case of fault
81. ns dangerous voltages may exist even with the equipment switched off To avoid dangerous electrical shock DO NOT perform procedures involving cover or shield removal unless you are qualified to do so DO NOT operate damaged equipment Whenever it is possible that the safety protection features built into this product have been impaired either through physical damage excessive moisture or any other reason REMOVE POWER and do not use the product until safe operation can be verified by service trained personnel If necessary return the product to an Agilent Technologies Sales and Service Office for service and repair to ensure that safety features are maintained DO NOT service or adjust alone Do not attempt internal service or adjustment unless another person capable of rendering first aid and resuscitation is present DO NOT substitute parts or modify equipment Because of the danger of introducing additional hazards do not install substitute parts or perform any unauthorized modification to the product Return the product to an Agilent Technologies Sales and Service Office for service and repair to ensure that safety features are maintained 4 Agilent E1490C C Sized VXIbus Register Based Breadboard Module User s Manual Notes Agilent E1490C C Sized VXlbus Register Based Breadboard Module User s Manual 5 Notes 6 Agilent E1490C C Sized VXIbus Register Based Breadboard Module User s Manual Chapter 1 Introduction
82. ns false e The ACFAIL line has been stubbed onto the module from backplane connector P1 pin B3 and is available as a user access point for your convenience Chapter 3 Using the Agilent E1490C 59 Using Other Power Supplies You can use any of the other power supply voltages from a standard VXIbus backplane as described in the VXIbus Specification All of the available voltages have been stubbed onto the breadboard module as user access points Just remember that you must provide your own fusing and filtering on board the module for each power supply you access from the backplane You must also provide adequate cooling for dissipation of the heat generated by the power requirements of your customs circuitry See page 22 for more information on establishing cooling specifications for your module Recommended power supply voltage applications are listed in Table 3 5 Table 3 5 Power Supply Voltage Applications Supply Application 5 VDC 12 VDC 12 VDC 24 VDC 24 VDC 5 2 VDC 2 VDC 5 VDC stdby Main power source for all systems Used for supplying power to logic devices General purpose power for switching power convertors analog devices and disc drives General purpose power for analog devices and disc drives Not recommended for power convertors General purpose power for high level output drivers Used to derive voltages for precision analog devices such as
83. nt E1490C 31 Backplane Interface Circuitry The backplane interface circuitry allows you to access the backplane control signals data lines address lines trigger buses and power supplies The backplane interface circuitry consists of the following functional groups Address Lines and Register Decoding Data Bus Drivers Status Register ID Register Device Type Register Control Register DTACK Interrupt and Control Backplane Signals and Voltages Available on the Module ECL Trigger Circuitry The following sections discuss the backplane interface functional groups Each section includes a description partial schematic and timing diagrams where applicable See Appendix B for schematics and complete parts list Note In the following hardware discussion a high state 1 is indicated by a positive voltage usually 5 V and a low state 0 is indicated by 0 V ground at the specified signal point A mnemonic suffixed with an asterisk such as WRITE indicates inverse logic 0 or low true 1 or high false Address Lines and Figure 2 19 shows the address line and register decoding circuitry The Reg ister Decoding Agilent E1490C breadboard module is designed to be used as an A16 D16 device As such only backplane address lines A1 A15 and data lines DO D15 have been implemented on the module To address the module the information present on backplane lines A6 A13 must be identical to the logical address as set by addre
84. o access the upper 16K of address space Lines AMO AM5 Must be set to either hexadecimal 29 10 1001 or hexadecimal 2D 10 1101 Refer to the VMEbus Specification Table 2 3 and the VXIbus Specification Rule C 2 10 Line LWORD Must always be set false 1 since this is a D16 device short word transfer 16 bits 2 This is a write operation so WRITE must go true 0 to provide the LATCH signal from the DTACK state machine in U9 LATCH is a one clock cycle negative going pulse that is applied to the other input to U2B With both inputs to U4A set low the output is a positive going pulse that clocks the control data from DBO DB15 through U22 U23 to access points CTL2 CTL 15 3 Set IACK false 1 to enable address equality detector U18 4 Set both data strobes DS0 and DS1 true 0 to indicate a 16 bit data transfer Figure 3 4 shows timing required for the PAL U9 control and signal lines Chapter 3 Using the Agilent E1490C 55 l WW g SYSCLK 16MHz Data Strobes m Address and or W Data Valid 8 ANA i DBEN i LATCH DTACK E 125 K 62 5 62 5 62 5 62 5 10 0 1 NOTE DTKINH high will hold DTACK cycle here Data Strobes means DSO x DS1 and will stay here until DTKINH goes low when going high and DSO DSI Sync signals with SYSCLK when going low Figure 3
85. ovement to a minimum If possible use a controlled static workstation Handle the module only by the metal cover plate Avoid touching any components or edge connectors When you are ready to configure the module remove it from its protective bag and lay it on top of the bag while keeping your free hand in contact with the bag This technique maintains your body and the module at the same static potential Keep one hand in contact with the protective bag as you pick up the module with your other hand Then before installing the module move your free hand to a metal surface on the mainframe thus bringing you the module and the mainframe to the same static potential Do not install a module without its metal shields attached While the module is installed it is protected from static discharge damage Hardware Description Figure 2 1 shows the Agilent E1490C with the metal shields removed As shown the breadboard module consists of a printed circuit board with two backplane connectors P1 and P2 a front panel DIN connector J2 and a terminal module Common traces are provided at the upper and lower edges of the printed circuit board to form power supply or ground buses Do not mount components where they will cross these buses 14 Configuring the Agilent E1490C Chapter 2 User Co nnections II
86. p and insert Terminal Module Option A3E Accessories Figure 2 16 Crimp and Insert Connector Single Conductor and A crimp and insert contact is crimped onto one end of a wire The other Contact endis not terminated Order Agilent 91510A Length 2 meters Wire Gauge 24 AWG SES Quantity 50 each SSS Insulation Rating 105 C maximum a Voltage 300 V Shielded Twisted Pair A crimp and insert contact is crimped onto each conductor at one end of a and Contacts shielded twisted pair cable The other end is not terminated Order Agilent 91511A Length 2 meters Wire Gauge 24 AWG Outside Diameter 0 1 inch Quantity 25 each Insulation Rating 250 C maximum Voltage 600 V Chapter 2 Configuring the Agilent E1490C 27 Jumper Wire and A crimp and insert contact is crimped onto each end of a single conductor Contacts jumper wire This jumper is typically used to tie two pins together in a single crimp and insert connector Order Agilent 91512A Length 10 cm Wire Gauge 24 AWG Quantity 10 each Insulation Rating 105 C maximum Voltage 300 V Crimp and Insert These contacts may be crimped onto a conductor and then inserted into a Contacts crimp and insert connector The crimp tool kit is required to crimp the contacts onto a conductor and remove the contact from the connector Order Agilent 91515A Quantity 250 each Wire Gauge Range 20 26 AWG Ve Plating Gold Plated Contact Maximum Current 2A at 70
87. s enabled during a read status register operation by the STATUS enable line set low decoded from address lines A1 A3 and by READ set low The status information presented to the data bus line drivers U24 and U25 must be static The MODID line P2 pin A30 controls bit D14 of the Status Register at all times Table 2 3 Status Register Bit Definitions Data Bit s Definitions SRO SR1 Device Dependent user assignable SR2 0 failed executing Self test 1 passed Self test SR3 Ready SR4 SR13 Device Dependent user assignable SR14 0 module selected by MODID high 1 not by MODID SR15 Device Dependent for A16 device 36 Configuring the Agilent E1490C Chapter 2 ID Reg ister The ID Register is a 16 bit register which identifies the module s manufacturer addressing mode and classification These identification fields are DIP switch selectable on the inputs to the data bus line drivers U11 and U12 as shown in Figure 2 22 ID REGISTER Pg 1 4 IDx RPS 4 7K P 1 READ SP2 NC DBL Al A2 A3 EM AS AB w foula jaja c5 ro no A o cn co ro A MS RPE 4 7K 74HCT541 o coj olo e c ro Ed E ro co xloj umi o nm
88. ss switch SP1 0 7 These eight bits allow up to 255 different V XIbus logical device addresses to be selected in a VXIbus system If a logical address match occurs and IACK is true equality detector U18 produces a low at its output which enables U17 Next equality detector U17 compares the information on backplane lines A14 A15 AMO AMI and AM3 AMS to a hardwired code of 111011012 Since AM2 is not examined this hard wired code will be a match if all 3 of the following conditions are true e a hexadecimal code of either 2916 or 2D16 is present on AMO AMS e Al4and A15 are both high 1 e WORD is false 1 32 Configuring the Agilent E1490C Chapter 2 CARDADRX O LWORDX O A7 UISA A 1 2 IACK l IACKX O DE 2 B ii 74HCT14 ALLO 4 is PI Y Atl DR d ALG 8 DEN IM DER ERN Da DEN so CARD BOUNDRY DETECT i vy AN UJ 19 CARDLAX l E ii DOEN 2 Tel lr Gene LABUS 3 Zann za Di gt Dei Ze Leer e LABUS S AMLO s 28 14 3 LABUS 5 NW
89. stall additional standoffs to compensate for the extra height requirement With the standoffs installed the module will require an additional one or two mainframe slots depending on the length of the standoffs and whether you use standoffs on both sides of the breadboard or just on one side Figure 2 6 shows the normal module configuration and the module with standoffs installed Figures 2 7 and 2 9 In Figure 2 7 the standoffs are installed between the PC board and the bottom shield The 19 mm hex standoff shown does not carry an Agilent part number but can be ordered from the address shown in Figure 2 8 With the recommended standoffs installed this configuration extends the maximum component lead length below the PC board from 3 2 mm 0 125 inch to 22 2 mm 0 9 inch Eight standoffs are required per module all eight standoffs are installed on the same side of the PC board E Screw Top Shield EC C TDI Circuit tE M 22 2mm 0 875 in Bottom Shed Hex Standoff Amatom P N 19968 SS 350 Figure 2 7 Agilent E1490C With Short Standoffs Added ES e Manufacturer s Address SCH 1 1 2 threods AMATOM Ne EL 06515 SAN YAN ITT IN 1 800 243 6032 m W orum x 24 in Quantity Required 8 per module ke oe NN M3 0 x 0 5 75 in 2 in F
90. sters Accessible The following example reads the ID Register register 0 at logical address 48 The program prints a decimal number representing the sum of the decimal values of the set bits OUTPUT 70900 VXI READ 48 0 ENTER 70900 IDREG PRINT IDREG The following example reads the Device Type Register register 2 at logical address 48 The program returns a decimal value representing the sum of the decimal values of the set bits OUTPUT 70900 VXI READ 48 2 ENTER 70900 DEVREG PRINT DEVREG The example in this section shows how to use the VXI WRITE command to write data to the Control Register Fourteen of the 16 bits can be user defined bits 1 and 2 provide SYSFAILIN and RESET respectively The following example writes data FFFFn to the Control Register register 4 at logical address 48 OUTPUT 70900 VXI WRITE 48 4 HFFFF Chapter 3 Using the Agilent E1490C 61 Reading Writing lO As you add your own custom registers to the breadboard use the REGO Custom Regi sters through REG4 enable lines These lines address registers 6 8 A C E respectively You can read or write to your registers using the same procedures shown by substituting the correct register address 62 Using the Agilent E1490C Chapter 3 Appendix A Agilent E1490C Breadboard Specifications Agilent E1490C Breadboard module specifications follow Item Specification User Component Area 490 cm 76
91. ts resulting from improper or inadequate maintenance by Buyer Buyer supplied products or interfacing unauthorized modification or misuse operation outside of the environmental specifications for the product or improper site preparation or maintenance The design and implementation of any circuit on this product is the sole responsibility of the Buyer Agilent does not warrant the Buyer s circuitry or malfunctions of Agilent products that result from the Buyer s circuitry In addition Agilent does not warrant any damage that occurs as a result of the Buyer s circuit or any defects that result from Buyer supplied products NO OTHER WARRANTY IS EXPRESSED OR IMPLIED Agilent SPECIFICALLY DISCLAIMS THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Exclusive Remedies THE REMEDIES PROVIDED HEREIN ARE BUYER S SOLE AND EXCLUSIVE REMEDIES Agilent SHALL NOT BE LIABLE FOR ANY DIRECT INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES WHETHER BASED ON CON TRACT TORT OR ANY OTHER LEGAL THEORY Notice The information contained in this document is subject to change without notice Agilent Technologies MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Agilent shall not be liable for errors contained herein or for incidental or consequential damages in connection with the furnishing performance or use
92. uitry to a known state Both hardware and software resets are implemented for your convenience Hardware Reset The backplane SYSRESET line drives both the hardware reset HRESET and the software reset CRESET user access points low 0 on the breadboard module HRESET goes to the clear inputs of U22 and U23 which drives all of the Control Register outputs access points CTL2 CTL 15 low 0 Software Reset Control Register output bit CTLO is used for the software reset If you write a to bit CTLO the CRESET access point on the module is driven low 0 by U4C You can use CRESET any way you choose in your custom circuitry CAUTION The VXI RESET logical addr command writes 1 s to all device dependent bits in the Control Register Your custom designed circuitry should tolerate this and not malfunction during reset This is defined in the VXIbus Specification Observation C 2 9 Detecting Errors The breadboard module implements the following error fail circuitry The Status Register implements bit SR2 as a self test Passed Failed bit see Table 3 1 on page 51 If SR2 PASSED access point is set low 0 indicating your custom circuit self test either failed or is currently still executing and the SYSFAIL INHBT bit CTL1 output of the Control Register has been set low 0 then the module sets the backplane SYSFAIL line true through U4B and USD If either SYSFAIL INHBT or the PASSED bit are set high SYSFAIL remai
93. ure 2 19 Chapter 2 Configuring the Agilent E1490C 35 Status Reg ister The 16 bit Status Register Figure 2 21 provides specific status information defined by the VXIbus System Specification and has other bits available for custom device dependent status information implemented by the user Table 2 3 shows the Status Register bit definitions See pages 51 and 52 for additional information on using the Status Register Refer to the VXIbus System Specification Section C 2 1 1 2 for detailed information concerning Status Register implementation restrictions OY Pg d S CX LI STATUS O UM a T Y 12 READ O24 WRITE A UIGE RP10 4 7K 74HCT14 STATUS REGISTER 10 TP U24 91 1P190 TP189 TPI88 TP18 TP186 TP185 TP184 vec ve 10 MWA CHO CC CO Aa I I I I I li eo e s oju s o w Z pl C 19 DBL0l 18 DBLI 17 DBE2 e Yo MI DBL3 Y 15 DBIA se 14 DB 5 d 60 o 113 DBEE y 12 DBI7 Ww kai ON 833 TPI97 TPI96 TPIIS TPIS4 TPIS3 TPIS2 TPI98 3 3 3 E VCC LAZAJ 4 NC NC TITIS L Papa o e oju s o w Z oi 19 DBL8 MEC DB 9 w e 1 DBL1ONS 9 30 16 rd 10 NIE DBLIZNS ui L D8U3y e D BON n 7 o E DIS u w RU dE Aa Esa ey AE OS ay TS RET DEEST NES AY ge Pa 1 3 4 1 LO DB 15 0 Figure 2 21 Status Register The Status Register i
94. verse the procedure Figure 2 14 Installing the Breadboard in a VXIbus Mainframe Chapter 2 Configuring the Agilent E1490C 25 Terminal Modules The Agilent E1490C Breadboard Module is comprised of a component PC board and a screw type standard terminal module If the screw type terminal module is not desired a crimp and insert terminal module Option A3E is available See page 27 for information about the crimp and insert option and accessories Note Refer to pages 29 and 30 before attempting to wire the terminal module Screw type Figure 2 15 shows the breadboard s standard screw type terminal module 8 yp Terminal Module connectors Use the following guidelines for wire connections Wiring Guidelines Be sure that wires make good connections on screw terminals Maximum terminal wire size is No 16 AWG Wire ends should be stripped 6 mm 0 25 inch and tinned to prevent single strands from shorting to adjacent terminals ES SAA T

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