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startWARE-GHS-VR4181A, startWARE-WinCE

1. V3 3 V2 5 V3 3 V3 3 V3 3 A A A A A NWIREEN L2 L3 14 15 16 C6 C7 C8 C9 BMODE1 1K0 100 1K0 100 1K0 100 1K0 100 1K0 100 22pF 22pF 22pF 22pF BMODEO DBUS32 N ZS CLKSEL2 C10 c11 C12 C13 C14 CLKSEL1 47u 47u 47u 47u 47u CLKSELO 516 1 DIVMODE1 Q1 Q2 DIVMODEU 4 C15 C16 C17 C18 C19 32 768 18 432 100nF 100nF 100nF 100nF 100nF
2. gs 25 IS s Li 221 E ole LON 0477 SiS OLUOd su ru lj OE 1 4 aa _____ PC SWI O f U U AU p e air 9 All p O cevaou O N F f 043 gt 1 2 1 5 4 31 youl m N LOT DIS 7 p 5071 920 10688 ZX eau wm gt LU V awa 2 V 00 2184 ueel 2031 N i q31 aWs 0ldid 030 6t LMS lt 9 E 11 11 mmm 2 4 030 070 ZH 15401 49 616 16 1 oalr SINLP MOLe 9LOId9 SLOId9 vL OId9 LOId9 L3QONAIQ 03GONAIG 9 L3dONW8 O03GOlNg N33MHIMN c 13S 19 195719 019510 265080 79 Preliminary Users Manual U16646EE2VOUMOO ircuit Diagrams AppendixA C VR4181A USB RS232 amp Analog Figure A 6 zd u LOd SOH avo ASN EE d snqA OX 0422 8L eol eq asn e9meqd asn sx 69 199 08841 34001 182 2 9921
3. 115 a 924 29900 lt 4022 4 OLX burs 0415 uedo V eoe d 23100 299 4 l Il gt e e o ou ko o o M N N m 11059 Sn8TA Inoszx 1 2 SOVLVG uM i L E EMEN eza 6 gza 9 31949 1HAQM _ 121 yale sav ERE 13634 zal 1 E 2 1 al 9543 adl S33 o 2 E DENN 250 O LSOI 727 p r or _ EH 89 9 ____ a LLLOLGNYT Gss 21 7101 OdL S SHIN _ ET W _ e H0 _ pro ees oan i Ian p Sax 001109 bios 00 640 J mr OOLNAXL 038u p 5 s g Rp ERP 620 820 120 920 Sca Led oza 810 110 Sia cia 80d 90d sod 70 cod 00 LV LLV OLV 60V 80V 10V 90V S0V SOV cOV Lov 0 WOq WOd User s Manual U16646EE2VOUMOO
4. KSCANT GPIO1 216 TC1 IGPIO53 KSCAN0 GPIO0 Rig DRQO 1 E O DAK0 TCOMGPIO52 TPY1 1 m TPYO v3 JTDIRMODE AIN2 L16 v2 Me A AIN H2 O JTRST Q b AIN0 SSS NANNANAN 2 VA 22222222 22222222 a gt D gt gt OOOOO St LO st GN O sti LO LO aT O N hd 9 bd 9 9 C24 x C21 100nF 100nF L7 L8 1 0 100 1 1 1 0 100 1 1 R4 10k0 V V v3 3 C26 V2 5 C23 100nF 100nF Preliminary User s Manual U16646EE2VOUMOO NWIREEN BMODE1 BMODEO DBUS32 CLKSEL2 CLKSEL1 CLKSELO MIPS16EN DIVMODE1 DIVMODEO POWER nRSTSW nRTCRST PWRON MPWR nNMI DCLK HS VSYNC ENAB VPBIAS VPLCD R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 1 RESET GPIO39 GPIO38 GPIO37 CFO_nCD2 CFO_nCD1 _ 101516 CF0_nWAIT CF0_nCE2 CF0_nCE1 CF0_nSTSCHG READY CF0 RESET DIR nEN nREG nVCCEN CLK48 UHDP UHDN UPON UOC UDP UDN GPIO23 GPIO22 GPIO21 GPIO20 RXO TXO nRTSO 50 GPIO17 GPIO16 GPIO15 GPIO14 GPIO13 IRDIN IRDOUT SYNC BITCLK SDATAOUT SDATAIN nSRESET GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 GPIO7 106 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIOO TPX1 1 TPYO AIN3
5. OO OOO N front view 8 nCTSO S Ne 28 Preliminary Users Manual U16646EE2VOUMOO Chapter4 Detailed Functional Description 4 4 5 USB Device Connector X5 The VR4181A evaluation board has a standard Series B USB device receptacle which is directly con nected to the USB device interface on the VR4181A The pinning of this receptacle X5 is shown below Figure 4 8 USB device connector X5 pin assignment Pin 4 4 6 USB Host Connector X6 The VR4181A evaluation board has a standard Series A USB host receptacle which is connected to the USB device interface on the VR4181A The USB power supply is provided through a TPS2014 USB power controller The pinning of this receptacle X6 is shown below Figure 4 9 USB Host connector X6 pin assignment LLL LEN Preliminary User s Manual U16646EE2VOUMOO 29 Chapter4 Detailed Functional Description 4 4 7 LCD Display Connectors X7 X8 and X9 A total of three connectors is provided for the LCD display on the bottom side of the PCB X7 is an 8 pin single in line connector for the high voltage converter for the LCD back light X8 is a 33 pin ZIF connector for the display itself and last but not least X9 is a 4 ZIF connector for the touch panel The Figure 4 10 with the pin assignments uses the signal names as they are used in the circuit dia gram Figure 4 10 LCD display connectors X7 X8 X9 pin assignment High vol
6. 9 e V3 3 A z 2 2 10 2 9o 2 T I 4 4 04 gt R3 10 0 8 8 5 8 2 8 B E X x E 5 a 2 a a a a z 2 s 3 o gt o B a r x o 15 SYSEN POWER SYSDIR RSTSW E RTCRST DI SDCLK POWERON 8 zs MPOWER SDCS3 C13 1 800828 OCB e EY 800818 vi speso DCLKISHCLK T wwiREEN HSYNC LOCLK NWIREEN 714 E MODET 58 RAS VSYNCIFLMBMODE1 21 clo cas ENAB MBMODEO JIT VPBIAS GPO63 RIT DOM3LBE3 VPLCD GPO62 15 DQM2ILBE2 Be FPD15ICF1_READYIGPIO51 DOMO LBEO it FPD14 CF1_STSCHGHGPIO50 12 B FPD13 CF1 CE2 GPIO49 T12 cc C20 west FPD12 CF1_CE1 GPIO48 S EPD11 CF1_CD28 GPIO47 SA10 FPD10 CF1_CD1 GPIO46 FPD9 GPIO45 A4 FPD8 GPIO44 TE A2AICKE1 FPD7 GPIO43 12 FPD6 GPIO42 US A23 RP FPD5 GPIO41 16 JH A22 GPIO61 FPDA GPIO40 vl A21 GPIO60 FPD3 7 A20 GPIO59 FPD2 148 A19 GPIO58 FEDT ee 14 ATBIGPIOS7 FPDO 13 AT7IGPIOSG 16 1055 A45 GPIO54 CF1_RESET DBUS32 V17 DBUS32 po CG A14 a A13 CF1_DIR KPORT4 GPIO39 A12 CF1_EN KPORT5 GPIO38 e 11 CF1 4 37 L2 0 N16 12 1 CF0_CD2 GPIO36 NIE CF0_CD1 GPIO35 NIZ CF0_IOIS168 GPIO34 N1 CF_WAITHGPIO33 Bae 5 2 2 19
7. 1 1 occ CU Y Default Address 0 0 0 0 netmask 255 255 255 255 Platform initailization completed aystem ready Preparing for download Hit ENTER within 3 Seconds to enter static IP address Connected 0 01 43 NT1OD n 15200 8 N 1 SCROLL CAPS Capture Print echo a If your environment provides a DHCP service no further action is required E Boot will wait for three seconds and then contact the DHCP server via broadcast An IP address will be automatically assigned to the target and it should then occur in the Configure Remote Connection dialog of Platform Builder If no DHCP service is available the IP address for the target must be entered manually Hit Enter within three seconds after E Boot begins to prompt for the IP address and then specify an IP address which is in the same subnet than the host PC and which is not used by any network adapter in the host Normally the first six digits are identical to the IP address of the host the rest is different Next E Boot will prompt for a subnet mask normally 255 255 0 0 can be used for this purpose When IP address and subnet mask have been correctly specified the target will broadcast BOOTME to the network The target must then be listed in the Configure Remote Connection dialog of the Plat form Builder this however is reflected by a message like Locked Down Link 1 Sre IP 192 16984 1L 2 Port 0400 Dest IP 192 169 2 202 Port 0889 Eth
8. LO UT GND R2 T BC847C 1K00 gt V12 gt V5 0 VCC 133 _____ 2 10u 6 3V GND gt V2 5 L gt L C4 10u 6 3V 7 GND lt 3 gt 0 gt VDIS 5 10u 6 3V GND lt MPWR IC5A 74LCV04D sweibeig xIpueddy nSYSEN SYSDIR SDCLK nSDCS3 nSDCS2 nSDCS1 nSDCS0 nRAS nCAS DQM3 DQM2 1 DQM0 nWE SA10 CKEO A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00 D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 nROMCS nPCS4 nPCS3 nPCS2 nPCS1 nPCS0 nUBE nRD nWR nlORD nlOWR IORDY nlOCS16 nDRQ1 nDAK1 nTC1 nDRQO nDAKO nTCO JTCK JTMS JTDI JTDO nJTRST nBKTGIO 3 3 lt V 76 Appendix A Circuit Diagrams Figure 2 VR4181A CPU
9. Check power supply plug polarity Connect the power supply to the board Push the cold reset button 53 WindowsCE will then pop up after a while and is ready to use Note Like on the star WARE GHS VR4181A board the first program that is started is the S Boot monitor S Boot waits 5 seconds for an input from the terminal if no input is given WinCE will be started Therefore the start up time for WinCE is relatively long however this is not caused by the VR4181A or the operating system itself 5 1 2 starfWARE Linux VR4181A This chapter gives a step by step description how to start up the board in the starfWARE Linux VR4181A version that has Linux pre installed Check if all jumpers in their default position Check if all DIP switches are in their default position Check power supply plug polarity Connect the power supply to the board Push the cold reset button 53 Linux will then pop up after a while and is ready to use Note Like on the starhWARE GHS VR4181A board the first program that is started is the S Boot monitor S Boot waits 5 seconds for an input from the terminal if no input is given Linux will be started Therefore the start up time for Linux is relatively long however this is not caused by the VR41814 or the operating system itself Preliminary User s Manual U16646EE2VOUMOO 37 Chapter5 Board Operation 5 1 3 5 4181 This chapter giv
10. sbootel map documents Serial Port 0 1 sbootel con connectic 115200 UPGRADE TXT document E Connection Connect to T arqet MONSERY ROM Monitor Connection monserv 2 25 Custom __ monsery sp COM1 baud 115200 Cancel Revert Apply Connected to target rteserv Disconnected from rteserv Connected to target rteserv 5 Disconnected from rteserv Connected to target rteserv Disconnected from rteserv n S ASemiDispTPS SDevSup VR SVr41sxSstarWARE Vr4181A CD startw ARE Vr41814 v2 00 Vorlage fur Ulli Software sboot boardlib c Target mipslelf_compat J Start E X Builder For sbootel bld 413 A Connection Chooser Monitor monserv 9 51251 12 03 46 Preliminary User s Manual U16646EE2V0UM00 Chapter5 Board Operation 5 4 E Boot Operation The E Boot monitor is installed only for operation with the Microsoft WincowsCE Platform Builder Therefore the user is referred to Platform Builder documentation for details of E Boot operation 5 5 Using the WinCE Board Support Package star NARE WinCE VRA4181A comes with a board support package BSP for Microsofts WindowsCE 4 1 operating system This BSP has been prepared with and for Microsofts WindowsCE Platform Builder 4 1 the integrated development environment for WindowsCE Note that the Platform
11. E ER Rud a hee 13 L5 Used Abbreviations 3 3 xe Iv 44 a beta ace ocu a 14 Chapter 2 Board 5 15 Chapter 3 Functional 17 SL Flasn abg Z asia 17 2 Mam Memory 53e Rc xe po wa ua 17 3 0 Memory uy RAxG RI x Rx ow ie usapu RE REX 18 3 4 VR4181A Communication 18 Chapter 4 Detailed Functional 21 4 1 Usage of VR4181A GPIO 21 4 2 Configuration 4 45 20801614 gue sa uu ean dI uy 22 4 2 1 deor 22 4 2 2 Switch SettingS lk ewe ex REG LEA RR ER ERR 22 43 Push SWIICIIGS goes puces D acsi x uu a a s 25 44 5 sos Gu ies ex See as on aie e 26 4 4 1 Power oupply Gonnector err irre dado Pr ot qp doeet 26 4 4 2 Usage of the N Wire ICE Connector 2 27 4 4 3 Analog VO CORECOR yu o 28 4 4 4 Using the Serial Interface 4 28 4 4 5 USB D
12. Figure 4 13 Figure 4 14 Figure 4 15 Figure 5 1 Figure 5 2 Figure 5 3 Figure 5 4 Figure 5 5 Figure 5 6 Figure 5 7 Figure 5 8 Figure 5 9 Figure 5 10 Figure 5 11 Figure 5 12 Figure 5 13 Figure 5 14 Figure 5 15 Figure 5 16 Figure 5 17 Figure 5 18 Figure A 1 Figure A 2 Figure A 3 Figure A 4 Figure A 5 Figure A 6 Figure A 7 Figure A 8 Figure A 9 Figure A 10 List of Figures Simplified Block 16 startWARE VR4181A address map example for kseg1 unmapped 19 DIP switch setting for SW1 default position 22 Jumper and Switch POSITIONS ec u etae esae 25 Power s pply connector Q uu 26 NWE i r 27 N Wire connector X2 pin 27 Analog I O connector pin assignment 28 Serial interface connector 4 28 USB device connector X5 pin assignment 29 USB Host connector pin assignment 29 LCD display connectors X7 X8 X9 pin 30 LCD display connector X7 X
13. User s Manual starWARE VR4181A Starter Kit VR4181A applies to stariWARE GHS VR4181A starrWARE WinCE VR4181A StartWARE Linux VRA181A Document No U16646EE2VOUMOO Date Published September 2003 O NEC Corporation 2003 Printed in Germany The information in this document is subject to change without notice No part of this document may be copied or reproduced any form or by any means without the prior written consent of NEC assumes no liability for infringement of patents or copyrights of third parties by or arising from use of a product described herein NEC Corporation NEC established proven quality assurance procedures for all products manufactured by or on behalf of NEC As part of product qualification process an intensive release test procedure has been established and executed before the products are released for mass production and delivered to our clients NEC Electronics Europe GmbH NEC EE on behalf of NEC would like to inform that the standard quality assurance procedure s have not been fully applied to this product and its documentation and that NEC cannot assure the full and error free function and or the standard quality level Preliminary User s Manual U16646EE2VOUMOO e The information in this document is current as of 02 09 2003 The information is subject to change without notice For actual design in refer to the latest publications of NEC Electronics data sheets or data books etc for the m
14. iminary Prel 82 it Diagrams AppendixA Flash 9 OHOSISU 049 039 049 13534 049 AQV3M 049 23904 049 049 042 ord 39 600 32 804 42 JMU 32 44014 49 49 49 39 39 LEO 42 A gt PPE aue V CEA 39001 0301 954 829 39001 sJojyoede 7 5 4 yoedwod LLX cao dM E 60d 800 OHOSIS PEI MOVdNI LIVM 13534 GSA 1850 COON OJAI Aqu CxO LSA 249 std vid eld eia Hg adl 50106015 HEE JOA BLSIOIU 049 0 42 49 00d 49 00V 30 4 COV dO 0V dO VOV dO 49 90V 40 10V 40 80V 49 60V dO dou 49 047049 101149 90d 42 god 49 vod 42 0d 49 004 049 aou 049 N39SAU 049 0301 eca gt 39 vid 49 EL d 49 Old 49 60 49 80d 49 MIO 35 Nau 49 c A lt 104 49 904 49 god 49 vod 49 00 49 200 49 49 49 42 N3u 42 3MU 49 HMOIU 49 49 30U 49 01 dO 60V 49 80V 40 lt 40 c A lt Svc9V LOVYZ 8213 VZLOI 99191 VOLO Sia cia LLa eod 80d
15. Og QrOAO IZ 890 rO gt 0 SA OSL 48001 GO ioo IF 6 LLOl 200 NaHn Sul 87 10 5 54 8319 30 LNOV NIV ONIV Preliminary User s Manual U16646EE2VOUMOO 80 Appendix A Circuit Diagrams VR4181A LCD amp Touchscreen Figure A 7 4400 49800 39001 ddO0 199 090 699 890 OAd L OXd L 125 2 01 2 1 0 70 08 412 0422 6x E lt ea 6 125 _ L sssi PR Kuwa 8 y s 1 UU 7 7 7 7 7 7 O i 49919 451141 6 4 da Gw he gt K nF s ce dm 2 7 47 lt ous lt 4 0 66 028 412 8 0301 022 SVIEdA AH QINS 80 OIN IX 2 2 39921 1521 owes uo NNASH pue N338HIMN 9sne eq 81 Preliminary Users Manual U16646EE2VOUMOO it Diagrams AppendixA Ethernet 8 qr0AO9 Tr asol 030 LZ9 000 SZ 0089S S LOl jUOL 049 Ove 0 4024 LEN 024 285 81 uo NNI dip 8
16. PI CF0_CE1 GPIO31 E18 STSCHGAIGPIO30 R18 2 CF0_READY GPIO29 1 6 7 A1 RESET GPIO28 17 AO CFO_DIRWGPIO27 216 CFO_EN IGPIO26 D31 CF REG GPIO25 18 D30 24 23 028 4 12 c5 P27 C11 De 026 D3 1 pos BH D24 UPON CT 023 uoc S12 C8 D22 upp D8 B10 D21 UDN 220 K16 Dig SCKIKSCAN11 GPIO23 18 210 1 DB SIKSCAN1OGPIO22 IZ 017 SO KSCANSIGPIO21 15 D16 FRM KSCANB GPIO20 B9 V5 D15 RXDO 8 D14 TXDOICLKSEL2 U9 8 Dis RTSOH GPIO19 CLKSEL1 abr CTSORGPIO18 6 cer DTR0 RTS1 GPIO17ICLKSEL0 D10 DCDORGPIO16 19 DSRO CTS1 GPIO15 1 P8 v10 RXD1 SCL1 GP1014 10 A1 De TXD1 SDA1 GPIO13 B3 Da RXD2 IRDIN WZ D3 TXD2 IRDOUT MIPS16EN 8 MEISE D2 Bs D ii DTR2 SDATAOQUT SDO DIVMODEO DIV MODE Po Romos DCD2 SDATAIN SDI S toJ 54 DSR2 SRESET BI6 PCS3H U10 1 pcs SCLOKPORT7 GPIO12 1 840 SDAO KPORT6 GPIO11 150 pcso PWM2 IKSCANSIGPIO10 ET C0 UBE PWMI KSCANG GPIOO 016 5i PWMO KSCAN7 GPIO8 G16 ATS MEMWR KPORT3 GPIO7 SS O IORD KPORT2IGPIO6 12 KPORT1 GPIO5 18 CIZ IORDY KPORTO GPIO4 IOCS16 Mia e KSCAN3 GPIO3 HU Ec KSCAN2 GPIO2 A12 220
17. SCROLL CAPS NUM Capture Print echo The screen gives information about the current system configuration in the upper right hand corner please see Figure 5 2 Remarks 1 Version information Example 4 22 2 Endianess LE Little Endian BE Big Endian 3 mode start from Flash start from RAM 4 Protection settings P Protected N Not protected The running countdown can be stopped by any input Once the countdown reaches 0 the system will try to boot In the first instance it will try booting from SDRAM if any information is available that there is something loaded If nothing is found it continues to check for information in the Flash memory If there is an application available in any of the Flash locations it starts this application Please see Figure 5 6 startWARE GHS VR4181A Boot Flow Chart on page 44 for a more detailed description of the procedure 40 Preliminary Users Manual U16646EE2VOUMOO Chapter5 Board Operation 5 2 3 S Boot Boot Menu When the countdown is interrupted the S BOOT stops the boot procedure and the boot menu is shown Connected D 10 47 Auto detect 115200 8 1 SCROLL Caps NUM Capture Print Figure 5 3 5 Monitor Boot Menu startWARE GHS VR4181A HyperTerminal EE d x File Edit View Transfer Help Boot loader Ver 4 22 1 1 Boot Menu 1 Boot from SDRAM 2 Boot from FLASH 3 Clear VA
18. 90d Sod vod cod 00 20 90V cov LOV 00V 83 Preliminary Users Manual U16646EE2V0UM00 it Diagrams AppendixA VR4181A Connectors 10 C vsodu SOdu OSOdU Nan 280054 YOLU vau Loudu enoa LAOG NASASU OLVS T 700 9 0 GLX 652 LSOdu SONWOHU Od L dan daHn 8v 19 esodsu 59059 0214 YIASAS 9 S OlU 6 8 2 9 6 v 4 L 700 97 6 149 0339 1 Svou cov 02 81 91 LV 019 80V 90V cov 00V 6 8 2 9 6 L 700 97 0 0 SA lt dl Od L 0cv 81 91 21 019 80V 90V cov 00V 820 920 ved ccd 020 9 vid ora 80d 90 voa cod 00 Si Si Si Si Si O NIVLVGIS 5 11 9 SLOIdS LOIdS 05144 240149 0040149 160149 20149 0Old9 LLOldS 6801 9 901 9 vOld9 091 oyyau N3SASU SONOHU g SOdu LSOdu LNOG danu AQSOI 1 SA G 1 L0 2EL MOS lX User s Manual U16646EE2V0UM00 iminary Prel 84 Although NEC has taken all possible steps toensurethatthe docu
19. AIN2 AIN1 AINO AOUT 9 99 ENUEN su sn 11 s s GND C32 100nF 28F128J3A Place Capacitors around IC R39 V3 3 lt 47K0 R38 ORO C33 lt s s GND 100nF 28F128J3A nROMCS 2 USE 3 181 suieJDeiq no y xipueddy 82 00 1110 2449999 LN ENUEN saesf GND C36 1uF K4S281632D C41 10 6 3V A9 A10 AP A11 A12 NC BA1 NC1 i nWR nRAS i nCS s D D lt D V3 3 116 117 1018 D19 D20 021 122 11023 024 111025 D26 027 028 D29 D30 31 R5 33R0 DQM3 DQM2 CKEO Place Capacitors around IC GND C42 1uF A9 A10 A11 12 NC BAO BA1 NC1 i NWR i nCAS nRAS i nCS T C47 10 6 3V Ps D D D D V3 3 00 D01 002 1003 11004 005 D06 1007 D08 D10 112 D13 D14 D15 R6 33R0 Shield the SDCLK line ainbl4 5 VISITA n311 y it Diagrams Appendix A N Wire Reset amp Configuration Figure A 5 3 aNd 6r9 O O O NOVOOWSL
20. Builder itself is not included in the starWARE WinCE VR4181A deliverables A trial version of Platform Builder is obtainable from Microsoft at the time when this manual is prepared 5 5 1 Preparations for Using the WinCE BSP Downloading and Debugging with WinCE requires an Ethernet connection between the host PC and Star bWARE WinCE VR4181A This Ethernet connection can be provided either with an extra network adapter in the host PC case A or by re using an already available Ethernet based network infrastruc ture case B In case A the extra network adapter must be configured as follows no DHCP P address 192 168 where xxx yyy are numbers between 1 and 255 preferably 1 SubnetMask 255 255 0 0 no IP forwarding Note The IP addresses used here are only examples The extra network adapter must be connected to the star WARE WinCE VnR41814A board with an Ether net cross cable or via an Ethernet hub In case B starhWARE WinCE VR4181A is connected to a free port of an Ethernet hub with a conven tional Ethernet cable so that host PC and star WARE can communicate over the network In such an environment the IP address for the starWARE board is normally automatically assigned DHCP Microsoft Platform Builder must be installed on your host PC with the MIPSII processor selection included Additionally a free serial port of your host PC must be connected to starWARE VR4181A using the serial cable Then starWA
21. RomHdr physfirst 80090000h Download successful Jumping to image at A0090004h Got EDBG CMD JUMPIMG Got EDBG CMD CONFIG 18 42 122 43 20 44 21 45 67 68 69 21 02 2 LLT 2112 1223 1 147 148 165 2266 16 40 14 41 L9 og flags 0x00000000 pCfgData 0x8001020E Flags are 00000000Network Transfer Complete pDriverGlobals 0xA0002100 pDriverGlobals eth EbootMagicNum 0 45424 54 pDriverGlobals eth etherEnabled 0 0 pDriverGlobals gt eth etherFlags 0 1 pDriverGlobals gt eth OdoAddr dwIP 0 201 8 0 pDriverGlobals eth OdoAddr wMAC O0 0 00 pDriverGlobals eth OdoAddr wMAC 1 0x32 pDriverGlobals eth OdoAddr wMAC 2 OxBOO pDriverGlobals eth SubnetMask OxFFFF pDriverGlobals eth DownloadHostAddr dwIP OxCA02AS8CO pDriverGlobals eth DbgHostAddr dwIP 0 0 pDriverGlobals eth KdbgHostAddr dwIP 0x0 pDriverGlobals eth PpshHostAddr dwIP 0x0 Jumping image at A0090004h 22 46 70 94 1 13 1231 126 7 29 47 VE 25 114 152 150 168 24 48 22 96 Zio 49 22 27 T o 1527 Lol 16 26 50 74 98 LLG 134 1 22 170 Preliminary User s Manual U16646EE2VOUMOO 59 Chapter5 Board Operation During start up of the WinCE image target and host PC exchange information via Ethernet and via the serial line The Debug Window within Platform Builder will show a string of messages like this example Kernel debugger is waiting
22. a binary image file Note We recommend to de activate all on line virus scanners while a binary image is created The four build process steps are controlled using the Build menu of the Platform Builder In the follow ing lines the related functions are described briefly for details the user is referred to the Platform Builder on line help function Table 5 1 Build menu and related build process steps Generate Platform Headers starts the SYSGEN process checks if parts of SYSGEN have already been executed and do not need to be repeated Platform Headers starts the SYSGEN process all SYSGEN steps are unconditionally executed Build Platform starts BUILD BUILDREL and MAKEIMG processes checks if an additional SYSGEN is required and executes it eventually Rebuild Platform starts BUILD BUILDREL and MAKEIMG without optimizations checks if an additional SYSGEN is required and executes it eventually without optimizations Makeimg starts MAKEIMG without any check if any of the proceeding steps is required as well very fast but for experienced users only Clean deletes all files that have been processed with SYSGEN and all files in the release directory should normally only be executed if SYSGEN fails in a very early phase without an obvious reason 48 Preliminary Users Manual U16646EE2VOUMOO Chapter5 Board Operation 5 5 3 Integrating the BSP into Platform Builder The BSP for starWARe WinCE VR4181A is deliv
23. and medical equipment for life support etc The quality grade of NEC Electronics products is Standard unless otherwise expressly specified in NEC Electronics data sheets or data books etc If customers wish to use NEC Electronics products in applications not intended by NEC Electronics they must contact NEC Electronics sales representative in advance to determine NEC Electronics s willingness to support a given application Notes 1 NEC Electronics as used in this statement means NEC Electronics Corporation and also includes its majority owned subsidiaries 2 NEC Electronics products means any product developed or manufactured by or for NEC Electronics as defined above 8 02 10 Preliminary User s Manual U16646EE2VOUMOO 3 Regional Information Some information contained in this document may vary from country to country Before using any NEC product in your application please contact the NEC office in your country to obtain a list of authorized representatives and distributors They will verify e Device availability e Ordering information e Product release schedule e Availability of related technical literature e Development environment specifications for example specifications for third party tools and components host computers power plugs AC supply voltages and so forth e Network requirements In addition trademarks registered trademarks export restrictions and other legal issues may also vary f
24. bit ROM width Note that if the switch is positioned for 16 bit ROM width all pre programmed software will not work any more Table 4 3 Boot ROM bus width setting for VR4181A 9 select 32 bit bus width default select 16 bit ROM bus width 2 Pipeline Clock Setting The VR4181A uses three pins CLKSEL 2 0 to configure the pipeline clock AClock these pins are sampled when the RICRST input is de asserted SW1 2 4 control the level of these pins and select the pipeline clock as described in the table below Table 4 4 Pipeline clock setting for VR4181A SW1 2 SW1 3 SW1 4 m Us 73 7 MHz 7 MHz 84 1 MHz 90 7 MHz 118 MHz ma EL Preliminary User s Manual U16646EE2VOUMOO 23 3 4 5 24 Chapter4 Detailed Functional Description NWIREEN setting The NWIREEN pin controls if the on chip debug logic on the VR4181A which is accessed with the so called N Wire interface can be used or not Like with the CLKSEL pins the logical level of this pin is sampled during reset it is selected with the SW1 5 switch Using the N Wire interface requires connecting an N Wire ICE to the connector 2 the default position for this switch is There is normally no need to change this switch position even if the N Wire interface is not used Table 4 5 NWIREEN pin setting for VR4181A 9 enable usage of N Wire interface default disable usage of N Wire interf
25. disk 3 eboot zImage converted to Windows CE binary file 4 eboot initrd zImage and embedded ram disk converted to Windows CE binary file Boot Strategy eboot initrd 4 Enter 4 or hit the return key in order to select eboot initrd As ELinOS allows the simultaneous installation of several Linux kernels it is now required so select one of the appropriate kernels for the actual hardware platform Immediately after installation of the ELinOS package there is only one selec tion for the kernel and the choice is simple Please enter your kernel source tree The suggested order is 19 TJ nucemprpse2 10 Kernel Source Tree 1 1 After entering 1 or hitting the return key all configuration parameters are defined and the cloning proc ess continues while your host system outputs the following information Checking Kernel Source opt elruos linux lrtnux mipe 2 4 09 OE Wiping old kernel ok Setting up new kernel ok Writing Tils GE Writing file Configuring Features home wagenerw src elinos Hello Clone initializing features feature input complete initializing features feature input complete Sw FUNNIN LER ULE COME LOCI bon SEQ Sx prepare done commit done mkefs done kernel done unkernel done merging kernel configuration with feature config Feature build complete Your new project has been set up successf
26. ranging from OxA3FF B000 to OxA3FF FFFF The SDRAM boot flags are stored memory location 0 8 and 0 4 Once an application is loaded into RAM one address is containing the text EXEC the other one contains the execution address of the last recently loaded application S BOOT allocates the reset vector location of the VR4181A i e the Flash block located at address OXBFCO 0000 cannot be used by any target applications There is another monitor delivered with the Starter Kit the Green Hills target monitor located at 2 0000 It is running from Flash memory area which prohibits a programming of the Flash unless the Flash burning algorithm is located in SDRAM In addition S BOOT is protected by H W bit so that no accidental erase may happen Preliminary User s Manual U16646EE2VOUMOO 45 Chapter5 Board Operation 5 3 Green Hills Monitor Operation The Green Hills monitor is used exclusively with the Green Hills Multi 2000 debug environment Prior to using the Green Hills Monitor you must install Multi 2000 by following the instructions on the CD Once a project for example the sbootel project from the starWARE CD has been opened with Multi 2000 you can establish a debug connection to your target system i e stlarWARE GHS VR4181A hardware This requires a monitor program running on the target hardware i e the Green Hills Monitor and a monitor server program running on the host PC side To start up the Gr
27. setting for VR4181A 23 NWIREEN pin setting for VR4181A 24 MIPS16EN pin setting for VR4181A 24 Bus clock division mode setting for VR4181A 24 Push button switch function assignment 25 Build menu and related build process steps 48 Differences between debug and retail image 50 Preliminary User s Manual U16646EE2VOUMOO 11 12 Preliminary User s Manual U16646EE2V0UM00 Chapter1 Introduction 1 1 System Requirements Host PC For Green Hills MULTI 2000 Embedded Development Kit a PC supporting Windows 9x Windows 2000 or Windows NT is required Pentium 133 MHz at least 32 MB of RAM 256 color display 1024 x 768 mouse CD ROM drive and 60 Mbytes of free hard disk space are required to install the GHS compiler and debugger package An x86 based PC with a mainstream Linux distribution like SuSE RedHat or Debian is required to install and run the Elinos tool chain Host I F Serial RS232C interface capable to handle communication at 115200 baud and lower speeds 1 2 Described Products This document des
28. the package Note that the so called Platform Builder the integrated debug environment for WinCE is not included in the starNARE WinCE VR41814A package Figure 2 1 Simplified Block Diagram StarNNARE VR4181A USB host USB device RS232 Compact Flash slot Ethernet Address Data VR4181A 131 320 x 240 TFT with touch panel gen O Display SDRAM Extension 1 11 Extension 1 11 not on starWARE GHS VR4181A 16 Preliminary Users Manual U16646EE2V0UM00 Chapter3 Functional Description The starWARE VR4181A evaluation board is designed to evaluate the VR4181A MIPS RISC processor and uses the SMC LAN91C111 chip for ethernet downloading of software It can also be used as devel opment platform for operating systems like WinCE VxWorks Linux or Integrity StarWARE VR4181A can be used in a stand alone mode using a 12 V AC adapter but it can alternatively be extended with customer specific hardware using its extension connectors It provides 32 MByte of SDRAM memory and 32 MByte of Flash memory with two 128 Mbit chips each The capabilities of the VR4181A evaluation board include an on chip UART USB host and function interfaces an Ethernet interface realized with the LAN9C111 controller analog a colour LCD and touch panel interface as well as other VR4181A interfaces which be accessed the extension connectors These boards are shipped with the NEC S B
29. the respective target If Enable Full Kernel Mode is checked the image will be executed with reduced memory protection Consequently exceptions due to memory protection viola tions will not be handled and the image will simply hang On the other hand execution speed of the image will be higher 50 Preliminary Users Manual U16646EE2VOUMOO Chapter5 Board Operation Figure 5 9 Setting platform options Platform Settings X Settings Far Evan 814 MIPS wins MIPSIT Rele 2 ENEWIADUDA E MIPSII Eg Device Drivers Display H E Input Devices Networking General Build Options Locale Environment Build Options Enable CE Target Control Support Enable Eboot Space in Memory Enable Event Tracking During Boot Enable Full Kernel Made Enable Image For Flash Enable Kernel Debugger Enable KITL f PCI Bus Enable Profiling e Rl Serial Enable Ship Build Storage Devices Flush Events ta Release Directory H E USB Host E YR41814 PCMCIA E 13 Touchpanel Contra att Ethernet Bootloader 0 EET L wINCERDOTAPLATF R BE ie Industrial Automation Device Display The Enable Image for Flash option selects a different base address and prepares an image that can be stored in and executed from Flash memory Enable Profiling Supports program optimization using the Platfor
30. to connect with target 0 PID 0 TID 0 Windows CE Firmware Init PIDSO TIDTO memclear 0 PID 0 TID 0 Memory range from 81819000 to 82000000 0 PID 0 TID 0 End memclear IB S ACLOCK 131 MHZ DIDS CLOCK 9 55 MHZ U PIDO 021040 ECLOG ZU MHZ 0 PID 0 TID 0 Firmware Init Done Kernel debugger connected KDBG stream opened Kernel Version 1169 Checked loaded at 0x80090000 data relocated at 0x81800000 Debugger connection established Target CPU is MIPS Loaded symbols for C WINCE410 PDX M4181A_FINISH RELDIR EVA4181A_MIPSIIRELEASE NK EXE Loaded symbols for C WINCE410 PDX M4181A_FINISH RELDIR EVA4181A_MIPSIIRELEASE KD DLL Finished re loading kernel modules Loaded symbols for C WINCE410 PDX M4181A_FINISH RELDIR EVA4181A_MIPSIIRELEASE COREDLL DLL WINCE410 PDX M4181A_FINISH RELDIR EVA4181A_MIPSIIRELEASE FILESYS EXE WINCE410 PDX M4181A_FINISH RELDIR EVA4181A_ MIPSIIRELEASE FSDMGR DLL WINCE410 PDX M4181A_FINISH RELDIR EVA4181A_MIPSIIRELEASE RELFSD DLL Loaded symbols for Loaded symbols for Loaded symbols for Loaded symbols for WINCE410 PDX M4181A_FINISH RELDIR EVA4181A_MIPSIIRELEASE TOOLHELP DLL Loaded symbols for C WINCE410 PDX M4181A_FINISH RELDIR EVA4181A_MIPSIIRELEASE SHELL EXE Welcome to the Windows CE Shell Type for help Loaded symbols for C WINCE410 PDX M4181A_FINISH RELDIR EVA4181A_MIPS
31. 0UM00 Chapter5 Board Operation Defines allow configuration of further options Defines must be changed by editing the respective source file A brief description of the most frequently used defines is given below 1 5 DUMP FRAMES define in c wince410 platform eva4181a kernel hal smc c Frames sent or received by the kernel debugger are output via the serial debug interface default setting not defined 2 FBBPP define in c wince410 platform eva418la drivers display ddi_4181a vr4181disp h Sets the number of bits per pixel for the display driver default setting 16 3 SCREEN REFRESH 380HZ SCREEN REFRESH 60HZ define in c Nwince410NplatformWN eva4l81aNdriversNdisplayNddi 4181aNddi 4181a h oets the refresh rate for the display default setting 60 4 DDI 4181A Width define in c wince410 platform eva4181la drivers display ddi 4181 4 4181a h oets the horizontal resolution for the display driver default setting 320 5 001 4181A Height define in c wince410 platform eva4181la drivers display ddi 4181 4 4181a h oets the vertical resolution for the display driver default setting 240 5 5 5 Starting WinCE on startWARE WinCE VR4181A This chapter describes the required steps to download a WinCE image to the target system and to start it Before download of the WinCE image file nk bin the remote connection between host PC and target must be configured Platform Builder provides the Target Configure
32. 1A PCMCIA 3 09 15 04 2003 19 04 45 m ip Serial B Touch 0000 15 04 2003 15 43 22 2 29 USB Host amp E Build Selected Features E P USB Host Controllers 0 VR4181A OHCI dv Docking view Alt F6 p Open Workspace G Ethernet Bootloader eboot Required i Hide National Geode 86 TEENS a By NEC DDB Vrc5476 MIPSII FP BH vn p teri DDB Vrc5476 MIPSII 0 NEC DDB V14122 MIPSII Egi Industrial A FileView Core OS Applica pe 3 Device Drivers H 23 Commu btification History H Platform Manager 1 43 Core OS Services 2 Debugging Tools Kernel Features recent notifications found y Featurevi gh Parameter FileView 4 lalx 2 Delete the selected item 7743KB s Finally more configuration possibilities are given by switch settings and defines Common Platform set tings are usually done under the Platform Builder However some switches necessary to operate spe cific modules or operational modes of Windows CE require a different handling from the common settings There are two ways to access those switches 52 The 4 Platform settings gt Environment tab menu is used see Figure 5 11 Editing Platform Switches on page 53 or e A batch file located in the platform root directory is used Preliminary Users Manual U16646EE2VOUMOO Chapter
33. 29 135 type 181 53 4 eboot v4 0 arch Mips R41xx R5xxx Sending file elinos EVA4181A umc3 boot zImage initrd eboot Sent 510739 bytes 1 8 seconds Sending jump packet Acknowledge ok After the download the Linux image is started on the starWARE board in case of the Hello World project the following output or something similar will be visible in the terminal emulation window Sent BOOTME ES 2552 295 255 255 Locked Down Link 1 SEC LE LoS Port 0900 Dest 172 22 2 9 190 Port 0388 EbootSendBootmeAndWaitForTftp Image will be transferred to Memory OFound pTOC signature ROMHDR at Address 81000044h RomHdr ulRAMStart 80000000h RomHdr physfirst 80800000h Download successful Jumping to image at 81000000h Got EDBG CMD JUMPIMG Got CMD CONFIG flags 0x00000000 pCfgData 0x8001020E Flags are 00000000Network Transfer Complete pDriverGlobals 0 0002100 pDriverGlobals eth EbootMagicNum 0 45424 54 pDriverGlobals eth etherEnabled 0 0 pDriverGlobals gt eth etherFlags 0x7 pDriverGlobals gt eth OdoAddr dwIP 0x871D1DAC pDriverGlobals eth OdoAddr wMAC O0 0 00 pDriverGlobals eth OdoAddr wMAC 1 0x32 pDriverGlobals eth OdoAddr wMAC 2 0x3500 pDriverGlobals eth SubnetMask OxCOFFFFFF pDriverGlobals eth DownloadHostAddr dwIP 0xB41D1DAC pDriverGlobals eth DbgHostAddr dwIP 0 0 pDriverGl
34. 5 4 SIS SESE AA usa unpu qa 47 5 5 Using the WinCE Board Support Package 47 5 951 Preparations for Using the WinCE 47 5 52 Remarks on Platform Builder 48 5 5 3 Integrating the BSP into Platform Builder 49 5 5 4 Generating a Demo Image 50 Preliminary Users Manual U16646EE2V0UM00 7 5 5 9 Starting WinCE on startWARE WinCE VR4181A 55 5 5 6 Role of the Releasedirectory 63 5 5 7 WinCE BSP Components and Configuration 64 5 6 Using the ELinOS Board Support 65 5 6 1 Hello World Project Using the Linux Shell 65 5 6 2 Hello World Project Using ELK 68 5 6 3 Downloading an ELinOS Project to startWARE Linux VR4181A 70 5 6 4 Supported functions in ELinOS BSP 72 Appendix A Circuit 75 8 Preliminary User s Manual U16646EE2VOUMOO Figure 2 1 Figure 3 1 Figure 4 1 Figure 4 2 Figure 4 3 Figure 4 4 Figure 4 5 Figure 4 6 Figure 4 7 Figure 4 8 Figure 4 9 Figure 4 10 Figure 4 11 Figure 4 12
35. 5 Board Operation Figure 5 11 Editing Platform Switches Platform Settings Far Device Drivers B MIPSII E em Device Drivers General Build Options Locale Environment Environment Variables BSP KITL POLLING KERNELNOSHAREETH MODULE_CERTIFY E Audio fl Display r J Input Devices Networking fl PCI Bus 8 Serial 1 j Storage Devices USB Function E USB Host A vR41815 PCMCIA H vR41815 Touchpanel 5 Ethernet Bootloader bnot k Cancel Edit Environment Variable POLLING Variable M ame Variable Preliminary Users Manual U16646EE2VOUMOO 53 Chapter5 Board Operation The starWARE WIinCE VR4181A configuration uses the following settings 1 MODULE CERTIFY switch Kernel checks certification of software components when loaded if this switch is activated default setting off 2 USE INTERRUPT switch If this switch is set network controller for kernel debugging is used in interrupt mode If this switch is not set network controller for kernel debugging is used in polling mode Default setting interrupt mode Note It is recommended to have this switch set to interrupt mode Using the IDE to control the switch settings has the disadvantage that most of the switches are not visi ble in the environment variable tab Even if the switches are defined in the CEC fil
36. 54 pDriverGlobals eth etherEnabled 0 0 pDriverGlobals eth etherFlags 0 1 pDriverGlobals eth EdbgFlags 0 0 pDriverGlobals gt eth OdoAddr dwIP 0 201 8 0 pDriverGlobals eth OdoAddr wMAC O 0 00 pDriverGlobals eth OdoAddr wMAC 1 0x32 pDriverGlobals eth OdoAddr wMAC 2 OxBOO pDriverGlobals eth SubnetMask OxFFFF pDriverGlobals eth DownloadHostAddr dwIP OxCA02AS8CO pDriverGlobals eth DbgHostAddr dwIP 0 0 pDriverGlobals eth KdbgHostAddr dwIP 0x0 pDriverGlobals gt eth PpshHostAddr dwIP 0 0 OMERI HSMOIart Control 0 3000 SMC Ethernet card detected at I O base 0 4000300 SMC Ethernet Address 00 0C 32 00 00 0B SMC Reset complete2 SMCImit Device BVA4SIOIALl 19241094142 994 Calling EdbDglnrtbHCP OEMKitlInit Host connected HOSE 192 21 68224202 pork 2161 SetHostCfg KITLGlobalState 0x61 KITL Initialized Windows CE Kernel for MIPS Built on May 31 2002 at 14 35 12 KITL Leaving polling mode SMCEnableInts Preliminary User s Manual U16646EE2VOUMOO 61 Chapter5 Board Operation Finally when WinCE has completely booted up you should see a screen similar to Figure 5 15 on the display of starWARE WIinCE VR4181A Figure 5 15 WinCE desktop example Papierkorb Windows CE net pha 1201 2 For download three different variants need to be differentiated Ethernet debugging KITL R
37. 8 X9 front view 31 Ethernet connector X10 pin assignment 31 CompactFlash connector X11 pin assignment as originally specified 32 Extension connector X12 X16 pin assignment 1 2 33 Logic analyzer connectors X13 X14 X15 pin assignment 35 cc 38 1 6 SC REC 40 a 41 S BOOEFlIash 2 u u _ __ _ 42 o Boot Directory List for star WWARE GHS VR4181A 43 startWARE GHS VR4181A Boot Flow Chalrltl 44 Establish target connection with Multi 2000 46 Importing ther GEG 49 Sening platiormm ODUONS uu uu 51 Adding Removing BSP 52 Editing Plator ova dv u 53 Configuring a Remote Connection 56 5 Message 2 bre Edda 57 Dow
38. CAN11 GPIO23 50 49 SI KSCAN10 GPIO22 SO KSCANS9 GPIO 1 FRM KSCANS GPIO20 PWMO KSCANT7 GPIO8 PWM1 KSCANG GPIO9 PWM2 KSCANBS GPIO10 nCF1_VCCEN KSCAN4 GPIO37 KSCAN3 GPIO3 42 41 KSCAN2 GPIO2 KSCAN1 GPIO1 KSCANO GPIOO SCLO KPORT7 GPIO12 SDA0 KPORT6 GPIO1 1 nCF1 EN KPORT5 GPIO38 CF1 DIR KPORT4 GPIO39 KPORT3 GPIO7 KPORT2 GPIO6 KPORT1 GPIO5 KPORTO GPIO4 GND 29 GND 28 27 GND GPIO53 nTC1 26 25 GPIO52 nTCO nDAK1 nDAKO nDRQ1 nDRQO nNMI nSYSEN SYSDIR nROMCS 4 nPCS3 nPCS2 nPCS1 50 12 11 DQM3 nLBE3 DQM2 nLBE2 EIE DQM1 nLBE1 Preliminary User s Manual U16646EE2VOUMOO 33 Chapter4 Detailed Functional Description Figure 4 14 Extension connector X12 X16 assignment 2 2 b Extension Connector X16 seen from the bottom of the PCB V5 0 V5 0 MPWR A24 CKE1 A23 nRP A22 GPIO61 A21 GPIO60 A20 GPIO59 A19 GPIO58 A18 GPIO57 A17 GPIO56 A16 GPIO55 A15 GPIO54 A14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D01 Fuca Preliminary User s Manual U16646EE2V0UM00 4 4 11 Logic Analyzer Connectors X13 X14 and X15 Chapter 4 Detailed Functional Description For debug purposes the VR4181A evaluation board is equipped with three Mictor connectors for easy hook up of HP logic analysers The pinning of these connectors is i
39. DownsseTFEFTPD OPEN boot bin EbootSendBootmeAndWaitForTftp in the terminal window Note The IP addresses used here are only examples Preliminary User s Manual U16646EE2VOUMOO 57 Chapter5 Board Operation During the actual download process Platform Builder informs you about the download progress in the indicator box shown in Figure 5 14 Figure 5 14 Download progress indicator Downloaded 29 of 0S Image to M4181a_finish 58 Preliminary Users Manual U16646EE2VOUMOO Chapter5 Board Operation Simultaneously the download progress is indicated in the terminal emulation window After download to SDRAM the monitor will automatically jump to the entry address of the WinCE image An example for a download is shown below In case that a Flash image is downloaded the S Boot monitor will take over after the download and copy the downloaded image into Flash Note that this copying takes a substan tial amount of time Image will be transferred to Memory Q og ab 120123 Ta 90 1 392 193 94 995 26 97 30 Sl 52 53 54 55 b9 Dy 59 59 00 061 062 563 04 6S 6 6 15 TE TI TE 779 20 g1 93 04 05 6 ST 998 89 90 99 LOO LOL T02 105 TOA TOS 106 107 109 7109 110 1222 OLD 2524 LAs AS 105 2526 LER LA 135 136 137 138 139 140 141 142 143 144 145 146 pos 55 156 BOIS LIE OL 262 Wes pod TIL AGA 21225137 proc signature ROMHDR at Address A0090044h RomHdr ulRAMStart 81800000h
40. E implementations on the starWWARE VR4181A hardware platform They can also be used as a reference code for driver modifications that are required for adaptations to the user s proprietary hardware Descriptions of the related steps and procedures are found in the Platform Builder documentation and they are not explained in his manual 64 Preliminary User s Manual U16646EE2VOUMOO Chapter5 Board Operation 5 6 Using the ELinOS Board Support Package startWARE Linux VR4181A comes with a board support package for the Linux based ELinOS V2 2 operating system Additionally a complete ELinOS tool chain consisting of cross compiler debugger and a graphic configuration tool is delivered so that the customer has all he needs Before using the ELinOS tool chain its installation on the Host PC is required please consult the ELinOS documentation for installation instructions In the following chapter we will show how a simple project the legendary Hello World project can be generated using a classic Linux shell or alternatively the graphic configuration tool ELK Next we will explain how to run this project on the startWARE VR4181A board 5 6 1 Hello World Project Using the Linux Shell Before working with the ELinOS environment you should be logged into your system with your user name in the following we will use you as a place holder for your user name The first step in the Linux project generation is the initial creation of a ne
41. EE 1394 Driver Support Printing and Printer Drivers Smart Card Support and Drivers Storage Device Support and Drivers Display based and Headless devices Source code information Far the soul BSP Features Preliminary User s Manual U16646EE2VOUMOO 49 Chapter5 Board Operation 5 5 4 Generating a Demo Image After the BSP has been unpacked into the Platform Builder directory tree and after the CEC file has been imported you can open the so called Workspace in Platform Builder with Open Workspace in the File menu The workspace for starWARE WinCE VRA41814A is called M4181A FINISH pbw and can be found in the c wince410 pdx M4181A_FINISH directory In the workspace a multitude of build options is selectable The primary decision to be made is between a Debug and a Retail image This choice is made in the Set Active Configuration dialog of the Build menu The following table summarizes the main differ ences between a Debug and a Retail image Table 5 2 Differences between debug and retail image low compiler optimization easy to debug high compiler optimization tricky to debug large image less large image debug zones can be set no debug zones possible Many of these configuration settings can be selected in the Platform Settings dialog shown in Figure 5 9 Setting platform options on page 51 KITL the kernel independent transport layer is required for a debug connection to
42. G A01 BVD2 A00 nSTSCHG D00 D08 D01 D09 D02 48 D10 49 24 WP nlOlS16 GND2 nCD2 The board prototypes with serial numbers CA20Y0001D CA20Y0004D have been layouted with a wrong footprint for connector X11 and the pin assignment is not as shown in Figure 4 13 As a consequence CompactFlash cards must be inserted upside down on these boards The mechanical protection that normally prevents this has been removed on the prototypes Preliminary User s Manual U16646EE2VOUMOO Chapter 4 Detailed Functional Description 4 4 10 Extension Connectors X12 X16 The VR4181A Evaluation Board has two extension connectors X12 and X16 which can be used for cus tomer specific add on hardware processors address and data bus together with control and chip select signals are available on these connectors They also allow to use the VR4181A interfaces that are not directly wired to the other special function connectors Note that the VR4181A has to be configured accordingly for using these additional interfaces Figure 4 14 Extension connector 12 X16 assignment 1 2 a Extension Connector X12 seen from the bottom of the PCB TxD2 IRDOUT MIPS16EN 64 63 RxD2 IRDIN nDTR2 SDATAOUT SDO DIVMODEO nDCD2 SDATAIN SDI nDSR2 nSRESET 59 nRTS2 SYNC WS DIVMODE1 nCTS2 BITCLK SCLK nDTRO nRTS1 GPIO17 CLKSELO nDCDO GPIO16 nDSRO NCTS1 GPIO15 RxD1 SCL1 GPIO14 54 53 TxD1 SDA1 GPIO13 nCTSO GPIO18 nRTSO GPIO19 CLKSEL1 SCK KS
43. IIRELEASE PM DLL Loaded symbols for C WINCE410 PDX M4181A_FINISH RELDIR EVA4181A_MIPSIIRELEASE CESHELL DLL Loaded symbols for WINCE410 PDX M4181A_FINISH RELDIR EVA4181A_MIPSIIRELEASE EXPLORER EXE Loaded symbols for WINCE410 PDX M4181A_FINISH RELDIR EVA4181A_MIPSIIRELEASE SERVICES EXE Loaded symbols for C WINCE410 PDX M4181A_FINISH RELDIR EVA4181A_MIPSIIRELEASE MSIM DLL Loaded symbols for WINCE410 PDX M4181A_FINISH RELDIR EVA4181A_MIPSIIRELEASE HTTPLITE DLL Loaded symbols for C WINCE410 PDX M4181A_FINISH RELDIR EVA4181A_MIPSIIRELEASE UPNPSVC DLL Loaded symbols for C WINCE410 PDX M4181A_FINISH RELDIR EVA4181A_MIPSIIRELEASE HTTPD DLL Loaded symbols for C WINCE410 PDX M4181A_FINISH RELDIR EVA4181A_MIPSIIRELEASE WSPM DLL Loaded symbols for WINCE410 PDX M4181A_FINISH RELDIR EVA4181A_MIPSIIRELEASE OBEXSRVR DLL Loaded symbols for C WINCE410 PDX M4181A_FINISH RELDIR EVA4181A_MIPSIIRELEASE MSMQD DLL Loaded symbols for C WINCE410 PDX M4181A_FINISH RELDIR EVA4181A_MIPSIIRELEASE NETUI DLL Loaded symbols for C WINCE410 PDX M4181A_FINISH RELDIR EVA4181A_MIPSIIRELEASE SIPSELECT EXE 60 Preliminary Users Manual U16646EE2VOUMOO Chapter5 Board Operation At the other end the messages in the terminal emulation window during WinCE startup look like this example Initializing KITL with interrupts XOEMKitlInit pDriverGlobals 0xA0002100 pDriverGlobals eth EbootMagicNum 0 45424
44. IO38 in another function 18 Preliminary Users Manual U16646EE2VOUMOO Figure 3 1 OxBFFF OxBEOO OxBDFF OxBCOO OxBBFF OxBAOO 800 7 O0xB600 OxB5FF OxB400 OxB3FF 200 000 OxAFFF OxADFF 20 OxAB1F OxAB00 OxAAFF 800 0xA200 0 000 Chapter 3 Functional Description startWARE VR4181A address map example for kseg1 unmapped uncached Reset vector OxBFCO 0000 Flash ROM 32 MByte 0000 FFFF External general purpose space PCS4 0000 FFFF External general purpose space PCS3 0000 FFFF External general purpose space PCS2 0000 FFFF External general purpose space PCS1 0000 External general purpose space 0000 PCS0 FFFF External ISA bus space 0000 FFFF External ISA bus memory space 0000 FFFF PCI bus window 1 0000 FFFF Internal PCI bus space 0 0000 FFFF 0000 FFFF Internal register space 0000 FFFF unused 0000 FFFF SDRAM area empty 0000 used by on board devices SDRAM 32 MByte usable by off board devices 0000 Preliminary User s Manual U16646EE2VOUMOO 19 MEMO 20 Preliminary Users Manual U16646EE2V0UM00 Chapter4 Detailed Functional Description 4 4 Usage of VR4181A GPIO Pins Many of VR4181A GPIO pins are shared with other pin function
45. LID Flag in 4 Start 53 download and execute 5 Start 53 download 6 Start binary download and execute 7 disable boot sector protection FLASH status menu select the menu item any key to start default program This is main menu of the system and provides access to various other options of the 5 The user may manually boot from RAM or FLASH 1 2 Boot from SDRAM SBOOT tries to boot from memory location most recently loaded with an application Boot from Flash SBOOT tries to boot from a valid Flash memory location available in the directory list and marked as default start up Clear VALID Flag in RAM Makes an application located in main memory unavailable for next boot process Start 53 download and execute Implies the option to download an S record type file and start it directly after download Start S3 download Behaves like item 4 but does not automatically start the application Start binary download and execute Using this option starts a download of a raw binary file recommended for larger images Once this option is invoked the user is asked for a a flash memory address where the application is downloaded to b astart address of the application This is necessary for images providing a different entry point than the first target address is Disable boot sector protection This option allows you to overwrite the current S Boot image in flash and is only used for S Boot updates Normally
46. OUMOO 27 Chapter4 Detailed Functional Description 4 4 3 Analog I O connector The VR4181A processor has four A D input channels and a single D A output channel for simple meas urement and signalling functions These analog l Os are made available on a multipoint connector which is directly wired to the respective VR4181A pins So there is no amplification nor filtering provided on the board The connection scheme for the analog is shown below Figure 4 6 Analog connector pin assignment PCB top side N X3 front view AIN1 AINO se AOUT AIN2 alo GND ola GND GND AIN3 4 4 4 Using the Serial Interface X4 The VR4181A processor has three on chip serial interfaces called 5100 SIU1 SIU2 serial inter face unit The SIUn interfaces conform to the 5232 communication standard and support up to 1 15 Mbps The units are functionally compatible with the 516550 For details refer to the VR4181A Users Manual The different SIUs provide different numbers of control and handshake signals SIUO can be operated as a full 7 wire interface however on the VR4181 evaluation board it is configured as a 4 wire interface The processors serial interface 5100 is connected to a RS232 C electrical interface a level con verter It uses a standard male 9 pin SUB D connector X4 on the CPU PCB The pin definitions are described in the following figure Figure 4 7 Serial interface connector X4 RXO
47. R4181A address data bus via bi directional buffers 1 16 IC17 and to the CF control signals of the VR181A directly starWARE VR4181A allows to operate an LCD display with a connector for the actual display signals and an additional connector for the back light inverter Display connector X8 is prepared for a 64k col our TFT display however it is also possible to configure VR4181A to operate with cheaper displays This may require an individual adapter between X8 and the actually used display The same holds basi cally true for the back light connector X7 Most signals on X7 and X8 are directly connected to the VR4181A Only the HSYNC line has a buffer which is required to operate the N Wire interface and a display simultaneously The touch panel connector X9 has a very simple RC network R21 C58 61 for noise reduction Apart from this it is directly connected to the VR4181A Star NARE VRA4181A is equipped with an Ethernet interface that is implemented with a LAN91C1 11 controller from SMSC This device is directly connected to the VR4181A address data bus and it uses 0 as programmable chip select From software point of view the Ethernet controller can be accessed in polling mode or interrupt mode For interrupt mode the interrupt output of the LAN91C1 11 is connected to GPIO38 of the VR4181A GPIO38 must then be configured as interrupt input The con nection can be de activated by removing jumper J2 for applications that require to use GP
48. Re VR41814A can be powered up Messages on the serial interface show if the Ethernet connection has been successfully established Note Make sure that E Boot has been configured as default executable monitor program Preliminary User s Manual U16646EE2VOUMOO 47 Chapter5 Board Operation 5 5 2 Remarks on Platform Builder Building a binary WinCE image with Platform Builder is basically done in four process steps e SYSGEN e BUILD e BUILDREL e MAKEIMG In the SYSGEN phase the user selected components for a specific WinCE project are copied into a directory under the WinCE project directory typical name wince410 pdx 4181 finish wince410 eva4181la cesysgen With m4181A_finish being the project directory Next the build process for the basic functions of the BSP is started Details can be found in the Platform Builder on line help under platform headers build process or sysgen phase The SYSGEN phase is widely under user control by selecting components from the BSP function cata log and by setting build and environment options These options will be described later In the BUILD process the platform specific components are built as a rule of thumb these are the components found below the specific platform directory winCE410 platform eva4181a BUILDREL copies the relevant files generated in the SYSGEN and BUILD processes into the so called Release Directory Finally MAKEIMG glues these files together to
49. Remote Connection dialog see Figure 5 12 Configuring a Remote Connection on page 56 for this purpose If no active named con nection has been prepared so far this needs to be done now with the Add New button Ethernet must be selected for both download and kernel transport in the Services for active named connection sec tion of the dialog The Configure button allows you to test if Platform Builder is able to find a target system With Avail able Devices you should see an entry like 4181 11 see Figure 5 12 Configuring a Remote Connection on page 56 In case that your Ethernet connection does not provide a DHCP service this will require additional settings on the target system that have to be done via a terminal emulation pro gram In case that 4181 11 is listed as available device the Configure Remote Connection dialog be closed and the download can be started with Target Download Initialize Before the actual download takes place additional settings must be done on the target side Start a ter minal emulation on the host PC 115200 bps 8 bits no parity 1 stop bit no flow control and reset starNNARE WinCE VRA41814A This will start execution of the S Boot monitor program and your terminal window will show you a message as shown in Figure 5 2 Startup Screen on page 40 S Boot must be configured in such a way that the E Boot monitor is the default executable file details are gi
50. The power consumption of the board is approximately 800 mA 9 12 V with the LCD dis play activated and no external hardware connected The power supply that is delivered together with the board is able to 1 25 A 12 V If you would like to use other power supplies be sure to supply 12 V if the board is operated with dis play If the board is operated without display lower voltages can be applied as well Figure 4 3 Power supply connector X1 X1 12V Caution We urgently recommend to check polarity of the power supply that comes together with the board before connecting it to X1 26 Preliminary Users Manual U16646EE2VOUMOO Chapter4 Detailed Functional Description 4 4 2 Usage of the N Wire ICE Connector X2 For using the N Wire ICE RTE 1000 TP connect the ICE to the N Wire connector X2 Figure 4 4 N Wire Connector X2 1 O O O O O O B2 top view O O O O O 2 is directly connected the VR4181A N Wire Interface Note that the DIP switch SW1 5 must set to ON if an N Wire ICE is used The pin assignment for the connector is as follows Figure 4 5 N Wire connector X2 pin assignment GND GND GND GND GND GND GND GND GND B5 GND GND A6 B6 GND JTDI A7 GND JTCK B8 GND JTMS A9 GND JTDO B10 GND nJTRST B11 NC nBKTGIO B12 NC NC B13 VDD3 3 Preliminary User s Manual U16646EE2V
51. ace MIPS16EN setting The VR4181A processor supports the MIPS16 instruction set extension To allow the processor to switch to MIPS16 mode the MIPS16EN must be pulled high during reset This is done with DIP switch SW1 8 set to ON By default MIPS16 is disabled Table 4 6 MIPS16EN setting for VR4181A enable usage of MIPS16 instruction set disable usage of MIPS16 instruction set default DIVMODE Setting With the CLKSEL 2 0 pins the VR4181A can be configured to various pipeline clock speeds Addi tionally the external bus clock for SDRAM accesses and for the internal bus named TClock can be set to 1 2 or 1 3 of the pipeline clock speed The DIVMODE 1 0 pins are used for this purpose their setting is controlled with DIP switches SW1 9 and SW1 10 Table 4 7 Bus clock division mode setting for VR4181A SW1 9 SW1 10 DIVMODEO DIVMODE1 bus clock division mode Div2 mode TClock 1 2 AClock default OFF OF ON OF Div3 mode TClock 1 3 AClock ELEME Preliminary User s Manual U16646EE2VOUMOO Chapter 4 Detailed Functional Description 4 3 Push Button Switches The VR4181A evaluation board has three push button switches which are connected to VR4181A inputs S3 generates a low level pulse on the RTCRST input and causes a cold reset on the VR4181A This resets the processor completely 52 generates a low level pulse on the RSTSW input which issues a reset as well however leaves cou
52. cribes three products starWARE GHS VR4181A starWARE WinCE VRA4181A and star NARE Linux VR4181A All products are based on the same hardware platform As far as pos sible they will be commonly referenced under the name startWARE VR41814A We will use the original product names only when required 1 3 Package Contents Please verify that you have received all parts listed in the package contents list attached to the starNNARE VRA4181A package If any part is missing or seems to be damaged please contact the dealer from whom you purchased your starWARE VR41814A Note Updates to this User Manual additional documentation and or utilities for starWARE VR4181A if available may be downloaded from the NEC WEB page s http www nec de support 1 4 Related Documents VR4181A User s Manual Hardware Doc Number U16049EJ1VOUMOO VR4181A Data Sheet NEC Doc Number U16277EJ1VODS00 VR4100 Series Users Manual Architecture Doc Number U15509EJ2VOUMOO Green Hills Documentation is provided with the installation of the MULTI software ELinOS documentation is included in the ELinOS package that is a part of star WARE Linux VR41814 Preliminary User s Manual U16646EE2VOUMOO 13 Chapter1 Introduction 1 5 Used Abbreviations There are some abbreviations used in this document which may require additional information to be understood correctly 14 RFU NC GND GHS GNU MIPS reserved for future use not connected g
53. e the basic descrip tion file for the platform BSP the settings are NOT visible under 40 Shown below is the batch file of the 4181 c wince410 platform eva4181a eva4181a bat to initialize the platform as currently implemented REM Disable the Cursor for touch panel access set BSP NOCURSOR 1 REM Use interrupts for KITL if not set polling mode is used REM Recommended and default is to use interrupt mode set KITL USE INTERRUPT 1 REM Default is no audio support on EVA4181A set BSP NOAUDIO 1 REM Enable always the touch screen set BSP NOTOUCH REM No battery handling is implemented skip this driver set BSP NOBATTERY 1 REM We don t use USB slave functionality skip this driver set BSP NOUSBSER 1 REM Enable handling for 4181 Revl 2 BCU set BCU 12 1 REM Describe handling for EVA4181A board using serial I F DCD pin REM Default is no DCD connected SET BSP SERIAL VR4181A USE DCD Any change in this batch file will have impact on the next build process There are 4 classes of switches available S YSGEN switches defining the modules used for system build process BSP xxx switches to explicitly include BSP features from build BSP NOxxx switches to explicitly exclude BSP features from build IMG xxx switches related to the image building process DE For more details please refer to the Windows help files provided along with the platform builder 54 Preliminary User s Manual U16646EE2V
54. een Hills Monitor on starWARE GHS VR4181A just power up the board and wait until the S Boot countdown has expired Then open the Connection Choser dialog in Multi 2000 by hit ting the Connect icon 1 and select monserv as connection method 2 You have to modify parameters for the connection with the Edit icon 3 Make sure that the connection parameters are set to 115 kbps in the connection editor 4 The screen shot in Figure 5 7 illustrates this process and the Green Hills manuals on the CD will give you all the details Please refer especially to the Target Connection Users Guide for MIPS manual When the connection is successfully established you will be informed in the lower portion of the Multi 2000 builder screen 5 Figure 5 7 Establish target connection with Multi 2000 gt Builder for sbootel bld File Edit Project Build Debug Target Version Config Windows Help gt c 4 D 8 Filenarne FileType Version Control Version Control sbootel bld NL program sboot rmip assembly T II RAE E adb mip assembly C flashif c C Name MONSERV strataflash c C Type ROM Monitor Connection monserv main c C s3loader c C v Log Connection to file binloader c C version h include 1 sboot h include f types h include 1 Connection REESE Debug strataflash h include 1 ldscript lx linker fi 1 f mn
55. er Kit This manual presents the hardware manual of starWARE VR4181A Starter Kit This system specification describes the following sections Board Features Detailed Functional Description Board Operation Symbols and notation are used as follows Weight in data notation Left is high order column right is low order column Active low notation XXX pin or signal name is over scored or slash before signal name or xxxit hash after signal name Memory map address High order at high stage and low order at low stage Note Explanation of Note in the text Caution Item deserving extra attention Remark Supplementary explanation to the text Numeric notation Binary or Decimal XXXX Hexadecimal XXXXH or 0 Prefixes representing powers of 2 address space memory capacity K kilo 210 1024 M mega 229 1024 1 048 576 giga 299 10243 1 073 741 824 Preliminary User s Manual U16646EE2V0UM00 Table of Contents Preface 26 ee 5 Chaptep i IntroducllOH iu ro l wae ean uu xw KW 13 11 System 13 12 escribed uoo Cen ca esate SENS Phara Ed a 13 1 3 gests ace eters PR ERR dur Ede EE 13 14 Related DOCUmenls
56. ered as a ZIP file the enclosed CD filename EVA4181A CE41 V2 2 zip similar This ZIP file must unpacked with the Recurse Folders option checked The WinCE410 directory typically C wince410 must be selected as target direc tory Platform Builder requires that any platform is introduced using a CEC file which has information about the drivers that are implemented as part of the BSP Importing the CEC file goes like this Select Manage Catalog Features in the Platform Builder File menu Select Import e Specify the path to the file eva4181a cec typically c wince410 platform eva4181a cec files and select this file Select OK Figure 5 8 illustrates these steps Figure 5 8 Importing the CEC file x Manage Catalog Features Imported catalog feature Files boston eagle cec emulator geode cec Integrator cec cec Iubback cec 1394 printing cec smartcard cec storage abase CEC saurcetags cec evadl8la cec Vendor Microsoft Microsoft Microsoft Microsoft Microsoft Microsoft Microsoft Microsoft Microsoft Microsoft Microsoft Microsoft Microsoft Microsoft Electro Description Boston Features LEPC BSP Features Remove Eagle Features Emulator BSP Features Import Geode BSP Features ARM Integrator BSP Features kepwest BSP Features Aun Lubbock BSP Features IE
57. es a step by step description how to start up the board in the starWARE GHS VR4181A version which has no operating system pre installed Check if all jumpers in their default position e Check if all DIP switches are in their default position Connect the starWARE GHS VR4181A evaluation board with a serial cable to a host PC with a terminal emulation program 115200 baud 8 bit no parity 1 stop bit no handshake e Check the power supply plug polarity Connect the power supply to the board Start the terminal emulation program Push the cold reset button S3 e LED1 will be activated and the following welcome message from the NEC bootloader program S Boot will be displayed in the terminal emulation window Figure 5 1 Startup Screen startwARE GHS YR4181 HyperTerminal File Edit View Call Transfer Help NEC Bootloader Ver 4 22 1 1 system Information Top Memory address 000000 Flash address Manufacturer ID 00180018 Device ID 00890089 8 W W W W W W W W W W W W TW W W YW w W W W TW W W W Y W YW Y W Y W W cr rrr rr rcr rr rn Press any Key to enter menu or wait for countdown to start your default application woche c W W W W W W Ww W W W W Ww W W W W W W W W W W W TT 4 Connected 0 02 26 Auto detect 1115200 8 4 1 SCROLL caps NUM Capture Print echo When the countdown has expired S Boot will automatica
58. etail The functionality from CEShell starting programs setting breakpoints process visualisation is available ii Ethernet debugging KITL Debug The complete functionality from i is available addition ally you can set debug zones you can single step and show all variables ii no KITL The image is downloaded and executed from its base address Subsequently no control of debugging of the target is possible Debug messages can still be output but only in the terminal emulation window and not in the Platform Builder debug window 62 Preliminary Users Manual U16646EE2VOUMOO Chapter5 Board Operation 5 5 6 Role ofthe Releasedirectory The releasedirectory within platform builder s fairly complex file structure is one of the most important directories within Platform Builder It contains all files which are combined to the final image in the MAKEIMG process however not all files in the releasedirectory are integrated into the image In case of the 4181 platform the releasedirectory is found in c wince410 pdx M4181A_FINISH RelDir EVA4181A_MIPSII Debug for the debug version and in c wince410 pdx M4181A_FINISH RelDir EVA4181A_MIPSII Release for the release version If CEShell CE target control support KITL is present it is possible to utilize components executables DLLs from the releasedirectory directly When accessing a file WinCE tries first to find it in Flash then in RAM and last but not least in the relea
59. evice Conneclor XD Pee Padres 29 4 4 6 USB Host Connector 29 4 4 7 LCD Display Connectors X7 X8 and 9 30 4 4 8 Ethernet Connector 10 31 4 4 9 CompactFlash Connector XTi ner p cob 32 4 4 10 Extension Connectors X12 16 33 4 4 11 Logic Analyzer Connectors X13 X14 and X15 35 Chapter 5 Board 37 eer RE ee ee ee ede Sulu Be ee ae 37 5 1 1 stariWARE WinCE VR4181A 37 5 1 2 418 1 37 5 1 3 statWARE GHS VR4181A 38 5 2 SBoor Operation ne Swa 39 5 2 1 L CIO te GES 39 5 2 2 S Boot Startup Message 40 5 2 3 S BOOLBOODIIGDLI 4 de Hos Bate oho sa bed doe dd 41 5 2 4 Flash Option 42 5 2 5 HeSeL Process FIOW s 5254 E Al 44 5 2 6 S BOOT Specification 45 5 3 Green Hills Monitor Operation 46
60. ey to return Flags VL VFL VL Dize 00005000 00005614 Ver 4 22 LE BP m Description protected target monitor Connected 0 16 06 Auto detect 115200 B N 1 SCROLL Caps Capture Print echo Preliminary User s Manual U16646EE2VOUMOO 43 Chapter5 Board Operation 5 2 5 Reset Process Flow Figure 5 6 startWARE GHS VR4181A Boot Flow Chart Init No BCU Yes Relocate to upper SDRAM space No Default font Yes SDRAM Yes Start application No FLASH Yes Start application valid i e E Boot No Start SBOOT 44 Preliminary User s Manual U16646EE2V0UM00 Chapter5 Board Operation 5 2 6 S BOOT Specification 1 2 3 Interrupts S BOOT does not use any interrupt The serial units are used in polling mode only All interrupts are routed to addresses 0x8000 0000 0x8000 0080 0x8000 0100 and 0x8000 0180 It is recommended that all user applications are making usage of the BEV bit so that own interrupt handling routines can be entered at the desired locations The non maskable interrupt NMI is treated as ordinary reset no special handling implemented in here Initialization The caches are initialized prior to any download A timer is not implemented Only the peripheral units that are necessary for the operation of S BOOT are supplied with a clock and are initialized Memory Usage The memory area used by S BOOT is from
61. f NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers must incorporate sufficient safety measures in their design such as redundanoy fire containment and anti failure features NEC Electronics products are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to NEC Electronics products developed based on a customer designated quality assurance program for a specific application The recommended applications of NEC Electronics product depend on its quality grade as indicated below Customers must check the quality grade of each NEC Electronics product before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots opecial Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support opecific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems life support systems
62. fault executable entry by selecting function 3 in S Boot s flash status menu After the next reset S Boot will be started first and after five seconds waiting time the default executa ble block i e Linux will boot up 5 6 4 Supported functions in ELinOS BSP StarNNARE Linux VRA181A has a Linux operating system pre installed that was generated based on the ELinOS board support package This board support package can handle the following VR4181A peripherals Serial interface 100 Mbps Ethernet interface via off chip Ethernet controller USB host e CompactFlash Heal Time Clock e 320 x 240 pixel TFT LCD display e Touchscreen The pre installed image serves just as an example that illustrates the possibilities of ELinOS other con figurations and adaptations to user specific hardware and software requirements can be created using the ELinOS tool chain 72 Preliminary Users Manual U16646EE2VOUMOO MEMO Chapter5 Board Operation Preliminary User s Manual U16646EE2V0UM00 73 74 Preliminary Users Manual U16646EE2V0UM00 9 99 LN ENUEN su sn GZ X1 NEB 21 R GND GND 15MQ040N H1 250 125 H2 250 125 1 0 A 100 16V GND GND H3 250 125 GND H4 250 125 GND IC1 L1 IC2 LM2595S50 220uH LP3964EMP 3 3 220p 6 3V LO 7 lt 7 S gt 52 GND D2 GND 15MQ040N IC3 LP3964EMP 2 5 IC4 LP3964EMP 3 3
63. ication interfaces of the VR4181A directly acces sible on standard connectors a UART USB host and function Compact Flash display and touch panel Additionally the N Wire debug interface is wired out however it is not mandatory to have an N Wire based debugging tool available in order to operate the board VR4181A has several UARTs on chip that can be configured to work with different sets of control sig nals From these UARTs UARTO in a 4 line configuration Rx Tx CTS and RTS is available on standard Sub D connector X4 A Maxim MAX3232CUE level converter IC11 ensures correct RS 232 signal levels at the connector Note that jumper J1 must be inserted to operate UARTO as it is at the time of shipment The VR4181A processor provides USB 1 1 host and function interfaces The USB host interface is accessible via a standard Type A USB connector Its signal lines are directly connected to the VR4181A USB power switching and over current control is implemented with a Texas Instruments TPS2014 device IC13 The USB function interface is wired to a standard Type B USB connector VR4181A supports two Compact Flash interfaces one of these interfaces be accessed using standard CF card Of course this interface can not only be used for flash memory extensions but also for disk drives modems WLAN cards etc under the assumption that the required driver software is available and installed Electrically the CF slot is connected to the V
64. lk ELK will try to open an existing project in the current directory If this is not possible ELK will ask for ini tial project actions to be taken as shown in Figure 5 16 We select Clone an existing project and choose Hello from the list of projects Next we are asked by the ELK configuration wizard for the vari ous configuration options that have also been set in the Linux shell in Chapter 5 6 1 World Project Using the Linux Shell on page 65 Figure 5 16 ELK start up screen iBi Project Options View Help Welcome to ELK X Welcome to ELK the Embedded Linux Konfig Tool Please select one of the following operations Create new project Clone an existing project E Load an existing project 68 Preliminary Users Manual U16646EE2VOUMOO Chapter5 Board Operation After these basic configuration settings have been made ELK will come up with the project editor screen that allows you to perform settings with respect to Features included in the project Kernel configuration User application inclusion File system and Bootfiles Selecting one of these configuration item categories in the project navigation bar will generate different lists of options in the lower portion of the ELK window Figure 5 17 shows the screen for the kernel con figuration step After going through these configuration categories one by one the buttons are arranged i
65. llustrated below Figure 4 15 Logic analyzer connectors X13 X14 X15 pin assignment Mictor connector X13 seen from the bottom of the PCB SDCLK nWE D31 D30 D29 D28 D27 D26 D25 14 024 D23 13 D22 D21 12 020 019 11 018 D17 29 10 016 Preliminary Users Manual U16646EE2V0UM00 Mictor connector X14 seen from the bottom of the PCB IORDY CKE0 nIORD nlOWR nRAS nCAS nRD nWR nSDCSO 14 A24 23 13 22 21 12 A20 A19 11 A18 A17 10 A16 Mictor connector X15 seen from the bottom of the PCB NC NC nSDCS1 9 28 nSDCS2 nSDCS3 nUBE CLK48 30 UPON UHDP 31 UHDN UDP 32 UDN TPO TPI nROMCS nPCS1 nPCS3 NC 35 MEMO 36 Preliminary Users Manual U16646EE2V0UM00 Chapter5 Board Operation This chapter explains practical usage of the starWARE VR4181A evaluation board As board operation is slightly different for the WindowsCE and the Green Hills version of the VR4181A evaluation board both versions will be treated separately in this chapter 5 1 Getting Started In this chapter the very first steps for a vitality test of starWARE VR4181A will be described 5 1 1 startWARE WinCE VnR4181A This chapter gives a step by step description how to start up the board the star WARE WinCE VR4181A version that has WinCE pre installed Check if all jumpers in their default position Check if all DIP switches are in their default position
66. lly invoke the Green Hills debug monitor to which you can connect after starting Multi 38 Preliminary Users Manual U16646EE2VOUMOO Chapter5 Board Operation 5 2 S Boot Operation 5 2 1 Features A simple boot monitor named S BOOT is implemented on both versions of the VRA181A evaluation board This monitor offers the following features e A fast serial connection using the CPUs SIUO at 115200 Baud Download capabilities to SDRAM Download to FLASH e Automatic programmable start of applications available in RAM or Flash Flash File System with simple directory structure Preliminary User s Manual U16646EE2VOUMOO 39 Chapter5 Board Operation 5 2 2 S Boot Startup Message Once the VR4181A evaluation board is powered up and turned on you will find this screen on the host PC Figure 5 2 Startup Screen start WARE GHS R41814 HyperTerminal BENE Lim xl File Edit Call Transfer Help Bootloader Ver 4 22 1 1 system Information Top Memory address 000000 Flash address Manufacturer ID 00180018 Device ID 00890089 W W W W W W W W W W W TW W W YW W Y W W Y W W W rrr cr rr nr rr cr rr Press any Key to enter menu or wait for countdown to start your default application woche W W W W W W W W w W W W W Ww W W w W W oc oc Ne CN Te Y Te Te Y T w 4 Connected 0 02 26 Auto detect 115200 8 1
67. m Builder s profiling tool Finally Enable CE Target Control Support links CEShell functions into the image Another important step in the creation of a WinCE image is the selection of the desired BSP compo nents for a specific image This is simply done with drag and drop of BSP components from the alog View into the Feature View of the platform Removal of a component from a platform is done by marking it in the Feature View and subsequently hitting the Delete key Figure 5 10 Adding Removing BSP Components on page 52 illustrates these views Preliminary User s Manual U16646EE2VOUMOO 51 Chapter5 Board Operation Figure 5 10 Adding Removing BSP Components newiad004 Platform Builder Welcome to Platform Builder File Edit View Project Platform Target Build Tools Window Help x gt Win32 WCE MIPSII Release 1 122210 Za ags relo mima e m al xl El 0 004 features Variant ALL El d 4181 MIPSII E 2 23 Device Drivers El El Catalog Display a BSPs 51 423 Input Devices CEPC 86 22 2 Emulator x86 2 3 Net Resolve Feature s B EVA4181 MIPSII a 3 Remove Anchor fram Feature s B 5 Sal 16 04 2003 12 17 50 isplay 0 E PCMCIA Card H ap Sto Feature Dependencies 8 VR418
68. mentation supplied to our customers is complete bug free and up to date we readily accept that From errors may occur Despite allthe care and precautions we ve taken you may Name encounter problems in the documentation Please complete this form whenever Company 4 T you d like to report errors or suggest improvements to us Tel FAX Address Thank you for your kind support North America Hong Kong Philippines Oceania Asian Nations except Philippines NEC Electronics Inc NEC Electronics Hong Kong Ltd NEC Electronics Singapore Pte Ltd Corporate Communications Dept Fax 852 2886 9022 9044 Fax 465 250 3583 Fax 1 800 729 9288 1 408 588 6130 P o tronics Hong Kong Ltd CS iconductor Technical Hotli ectronics Hong Kong Ltd emiconductor Technical Hotline Sou Branch Fax 81 44 435 9608 Market Communication Dept Fax 82 2 528 4411 Fax 49 211 6503 274 South America Taiwan NEC do Brasil S A NEC Electronics Taiwan Ltd Fax 55 11 6462 6829 Fax 886 2 2719 5951 would like to report the following error make the following suggestion Document title Documentnumber Page number If possible please fax the referenced page or drawing Document Rating Excellent Clarity 0 Technical Accuracy El Organization
69. mper 42 controls if the interrupt output of the LAN91C111 ethernet controller is directly connected to GPIOS8 of the VR4181A Applications that use the ethernet controller an interrupt driven way require this jumper set Other applications that require GPIO38 as output require this jumper removed An overview about the placement of the jumpers on the evaluation board is shown in figure 4 2 at the end of chapter 4 2 At time of shipment both jumpers are inserted by default 4 2 2 Switch Settings The VR4181A evaluation board has a 10 position DIP switch SW1 which is used for various initial set tings of the VR4181A processor This chapter explains the functions and the default settings of SW1 An illustration of the switch and its default positions is given in Figure 4 1 Figure 4 1 DIP switch setting for SW1 default position oW1 at CL C ON OFF 10 Table 4 2 DIP switch function assignment SW1 1 ROM bus width setting SW1 2 4 pipeline clock speed setting SW1 5 enable N Wire usage SW1 6 must always be switched on SW1 7 must always be switched off SW1 8 MIPS16 instruction set usage 22 Preliminary Users Manual U16646EE2VOUMOO Chapter 4 Detailed Functional Description 1 Boot ROM Bus Width Setting The VR4181A processor uses the DBUS32 pin to control the width of the boot ROM On the VR4181A evaluation board a 32 bit wide ROM configuration is provided therefore this switch is positioned for 32
70. n the normal sequence of usage you generate the downloadable system with the equivalent to the makeboot command by pushing the Bootfiles button This will make another set of buttons accessible and with the Create Files buttons the system generation ELK is started The many steps of the system generation are recorded and documented in the ELK window At the suc cessful end of system generation you should see something similar to Figure 5 18 ELK Bootfiles screen after system generation on page 70 Figure 5 17 ELK project editor screen helloELK ES Ioj Project Options View Help E gt Features Kernel Filesystem Boottiles up TER 1 Yes Multi Processing support B LinuxMIPS Kernel Configuration Code maturity level options Loadable module support support for SMI RM200 PCI Machine selection CPU selection setup Technology Devices MT Parallel port support Support for Lexra LX PB2DK board Plug and Play configuration Block devices support for Toshiba T3827 Default BAUD Rate Multi device support RAID and L E Networking options Support for NEC startWARE vr4181A Telephony Support PAT AIDEMFMRLL support FES CS support support far LBAC VvEAT81A lA device support 1 eboot_initrd mips rake ica home vagenerw Hello Clone ELK hellaELK 2 Preliminary U
71. nload progress 58 WinCE desktop example x uu 62 Slab Up SCI GON 68 ELK project editor Screen unuy ieee a ee 69 ELK Bootfiles screen after system generation 70 POWO ie sy Sh as aa kaka ie ot 75 GPU 76 77 ux unu xnana oe E ae 78 N Wire Reset pu pa o P a 79 VR4181A USB RS292 a 80 VR41T81A LCDS uu pa HER CER ta Oe ve 81 PIU ET TE T 82 Senece T I TEE 83 G0ODI6C 06rSxu RENE I UU M TMMM 84 Preliminary User s Manual U16646EE2VOUMOO 9 10 Preliminary User s Manual U16646EE2V0UM00 Table 4 1 Table 4 2 Table 4 3 Table 4 4 Table 4 5 Table 4 6 Table 4 7 Table 4 8 Table 5 1 Table 5 2 List of Tables VP4181A GPIO DID USAGE _ _ 21 DIP switch function assignment 22 Boot ROM bus width setting for VR4181A 23 Pipeline clock
72. obals eth KdbgHostAddr dwIP 0x0 pDriverGlobals eth PpshHostAddr dwIP 0x0 Jumping image at 81000000h CKCkCk KO xk xk ck k k x x x x x ok x k ok ck Ko xk k x kk x x x lt loaded at 81000000 81007000 relocated to 80800000 80807000 zimage 81034538 8107 Preliminary User s Manual U16646EE2VOUMOO 71 Chapter5 Board Operation relocated to 8080 000 808535B2 i2 scs 10027908 91034539 relocated to 80854000 80880 60 first four zImage words 08088 1 40 60760300 756 696 Uncompressing Linux at load address 80100000 Now booting the kernel Autodetected SDRAM base 00000000 size 32MB CPU revision is 00000c74 Primary instruction cache 8kb linesize 32 bytes Primary data cache 8kb linesize 32 bytes Note The IP addresses used here are only examples Downloading an ELinOS image to the starWARE VR4181A board with the E Boot monitor does not generate any changes in the S Boot flash directory Therefore if your downloaded image has been flashed manual changes in the S Boot flash directory are required Restart your starWARE VR4181A board with a serial terminal connection established and press any key within five seconds after start up so that S Boot is not left Then enter 8 to come to the flash status menu and 7 to create a new block entry After entering the required parameters S Boot re programs the flash memory accordingly you can make this new entry the de
73. oot and E Boot monitors and an additional Green Hills monitor pre installed in Flash memory Furthermore WinCE 4 1 is installed on starAWARE WinCE VR4181A and ELinOS V2 2 on startWARE Linux VR4181A 3 1 Flash Memory The VR4181A evaluation board has 32 MByte on board Flash memory where the user can store data or transfer code to The Flash memory is implemented using two 128 Mbit Intel Strata Flash 28F128J3A chips IC7 and IC8 IC8 is connected to the lower 16 bits of the VR4181A data bus IC7 is connected to the upper 16 bits The system normally boots from the on board Flash memory Due to the VR4181A s flexible address assignment almost 4 MByte of the complete Flash memory are used as boot memory the remaining 28 MByte can be filled with application programs like WinCE or ELinOS The upper 4 MByte cover an address range from OxBFCO 0000 to OxBFFF FFFF After reprogramming the ROMCS register in the VR4181A the full 32 MByte range can be used as an address range from OxBEOO 0000 to OxBFFF FFFF Flash memory is accessed via the VR4181A chip selects signal ROMCS If the VR4181A is configured to 16 bit wide boot memory only one half of the physically pro vided Flash memory can be used Write operations to the Flash memory by VR4181A program execution are possible note that electri cally the Flash memory is permanently write enabled therefore watch your step when writing to the ROM area 3 2 Main Memory The VR4181A Evaluation board has 32 MB
74. ost up to date specifications of NEC Electronics products Not all products and or types are available in every country Please check with an NEC sales representative for availability and additional information No part of this document be copied or reproduced any form or by any means without prior written consent of NEC Electronics NEC Electronics assumes no responsibility for any errors that may appear in this document NEC Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such NEC Electronics products No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Electronics or others e Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these circuits software and information in the design of customer s equipment shall be done under the full responsibility of customer NEC Electronics no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information While NEC Electronics endeavors to enhance the quality reliability and safety o
75. ound in the on line help function of the Platform Builder The BSP has a display driver ready for the 320 x 240 pixel colour TFT that is mounted in the starWARE WinCE VR4181A housing Documentation for the dis play be found on the star WARE CD Adaptations to other display types possible but they require changes to the driver The display has resistive touch panel film mounted starWWARE WinCE VR4181A uses the touch panel as standard input device for the WindowsCE GUI Extensions can be connected using the CompactFlash slot The CompactFlash driver in the WindowsCE BSP supports Flash memory extension cards Other cards for networking or disk drivers may require additional drivers which are not part of the star WARE WinCE Vn4181A The serial interface 0 SIUO please see processor documentation for details of the VRA181A can be used as normal communication interface within WinCE using this driver It is accessible on SUB D connector X4 The maximum speed is 115 kbps An OHCI 1 0 compliant USB driver is included in the BSP as well It has been ver ified with a USB keyboard and a mouse Mouse operation does not support a mouse pointer Audio playback of WAV files the AC 97 interface of the VR4181A is supported with this driver Note that this requires to connect an external AC 97 compliant codec device at the extension connectors of the starWARE VR4181A PCB These drivers can be used for building other WinC
76. ple of internal VR4181A settings parts of registers in the RTC GIU PWM and PMU units unchanged Please consult the VR4181A user manual for details Push button switch S1 is connected to the POWER input of the VR4181A If the VR4181A has been driven into the hibernate mode by software S1 will restart the processor Table 4 8 Push button switch function assignment activation from hibernate mode Warm Reset connected to the RSTSW input Cold Reset connected to the RTCRST input Figure 4 2 Jumper and Switch Positions 7 504 wa Jes R32 R29 _ R30 H IC11 L 2 1 _ c70 HEB oL 823 11 42 15 R22 1 creas J1 2 Ul ET NEC IC9 startWARE VR4181A 1 by Avionic Design X8 R40 48 1 74 RSS C73 R35 H2 37 38 1 _ X13 X15 2 2 121 O TCs x16 R4 R37 IC17 IC16 R18 R17 Preliminary Users Manual U16646EE2V0UM00 25 Chapter4 Detailed Functional Description 4 4 Connectors The VR4181A evaluation board provides several connectors for testing purpose and for system exten sions This chapter will describe usage of the connectors one by one 4 4 1 Power Supply Connector X1 The power supply connection is done with a conventional coaxial type connector with the positive line at the centre
77. rom country to country NEC Electronics Inc U S Santa Clara California Tel 408 588 6000 800 366 9782 Fax 408 588 6130 800 729 9288 NEC Electronics Europe GmbH Duesseldorf Germany 0211 65 03 01 Fax 0211 65 03 327 Sucursal en Espana Madrid Spain 091 504 27 87 Fax 091 504 28 60 Succursale Fran aise V lizy Villacoublay France 01 30 67 58 00 Fax 01 30 67 58 99 Filiale Italiana Milano Italy Tel 02 66 75 41 Fax 02 66 75 42 99 Branch Netherlands Eindhoven Netherlands 040 244 58 45 040 244 45 80 Branch Sweden Taeby Sweden Tel 08 63 80 820 Fax 08 63 80 388 United Kingdom Branch Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Hong Kong Ltd Hong Kong Tel 2886 9318 Fax 2886 9022 9044 NEC Electronics Hong Kong Ltd Seoul Branch oeoul Korea 02 528 0303 Fax 02 528 4411 NEC Electronics Singapore Pte Ltd Singapore Tel 65 253 8311 Fax 65 250 3583 NEC Electronics Taiwan Ltd Taipei Taiwan 02 2719 2377 Fax 02 2719 5951 NEC do Brasil S A Electron Devices Division Guarulhos Brasil 55 11 6465 6810 Fax 55 11 6465 6829 Preliminary User s Manual U16646EE2V0UM00 Readers Purpose Organization Legend Preliminary Users Manual U16646EE2V0UM00 Preface This manual is intended for users who want to understand the functions of the 4181 Start
78. round Green Hills S W supplied under General Public License GLP Microprocessor without interlocked pipeline stages Preliminary User s Manual U16646EE2VOUMOO Chapter2 Board Features StarWARE VR4181A is a low cost evaluation board for NEC s VR4181A 64 bit high performance microprocessor It allows evaluation of the processor s performance as well as potential system per formance because the VR4181A can also be operated together with its typical system environment The starWARE VR4181A board has a VR4181A 131 processor soldered processor speed is config urable via DIP switch The VR4181A is directly connected to 32 MByte of SDRAM built up with 2 Sam sung K4S281632 devices total bus width 32 bit The SDRAM supports a max 65 5 MHz SDRAM clock 32 MByte of Intel Strata flash are connected to the VR4181A memory bus directly Mictor con nectors are attached to the memory bus before the isolation buffer A short summary of the board fea tures is given below VR4181A 131 CPU 32 MByte Flash 32 MByte SDRAM N wire debug interface via KEL connector as used with the Midas ICE Serial interface on conventional SUB D connector buffered RS232 line driver Ethernet Interface 91 111 controller with RJ45 connector USB host and function interfaces available One Compact Flash slot available Analog inputs and output directly accessible on multipoint connector oystem bus and most other interfaces available on two ex
79. s This chapter explains which of the GPIO pins have been used on the VR4181A evaluation board and which ones are still usable Generally all unused GPIO pins have been wired to extension connector X12 Their exact position at connector X12 is explained in the respective chapter With the VR4181A internal PINMODEn registers these pins can be configured to be either GPIO pins or to provide other interface functions Please consult the VR4181A user manual for details The following table lists the usage of all GPIO pins the freely usable pins 22 pins in total are shown as shaded Table 4 1 VR4181A GPIO pin usage Preliminary Users Manual U16646EE2V0UM00 21 Chapter4 Detailed Functional Description 4 2 Configuration Settings The VR4181A evaluation board has two jumpers and ten DIP switches for configuration purposes Their position should be checked carefully before powering up the board Function and default position of jumpers and switches are explained in this chapter 4 2 1 Jumper settings Before power on the board should be configured through the jumpers J1 and J2 Jumper J1 connects an output of the serial driver IC11 to the CTSO input of the VR4181A This is required for proper oper ation of the RS 232 interface on the VR4181A evaluation board The CTS0 input of the VR4181A can also be configured as GPIO19 a potential output To avoid driver conflicts you have to remove J1 if you want to use the CTSOZ GPIO19 pin as GPIO Ju
80. sedirectory Thus it is possible to leave certain components outside the image and to have them downloaded if required This is very use ful during development of new programs and or DLLs In this case you must make sure that none of these files is registered in any bib file common bib project bib and platform bib For verification it is most simple to look at the ce bib file in the releasedirectory Ce ib holds the summarised content of all bib files after evaluation of all command line switches furthermore ce bib Is newly generated with every MAKEIMG If it is guaranteed that the file under test is not part of the image this file can be started stopped modified and re started arbitrar ily without rebuilding the complete image Reginit ini is another file in the releasedirectory it holds all entries in the start up registry of the image Reginit ini Is also generated with every MAKEIMG Preliminary User s Manual U16646EE2VOUMOO 63 Chapter5 Board Operation 5 5 7 WinCE BSP Components and Configuration This chapter summarises the characteristics of the main BSP components It starts with some remarks about the kernel and describes the peripheral drivers BSP Kernel LCD Display Touch Panel CompactFlash Serial Interface USB Host Audio AC 97 The BSP kernel supports profiling check the Enable Profiling box in the Plat form Settings dialog in order to use it Details about profiling kernel can be f
81. ser s Manual U16646EE2V0UM00 69 Chapter5 Board Operation Figure 5 18 ELK Bootfiles screen after system generation ELK helloELK inl x Project Options View Help 15 74 21 _ Kema Fiesystem Bootes Create Files Clean Files Validate stop Validation 3 Leaving directory home wagenerw Hello Clone ELE linux arch mips zboot vrdl81a make 2 Leaving directory home wagenerw Hello Clone ELE linux arch mips zboot make 1 Leaving directory home wagenerw Hello Clone ELE linux binzrom output filename boot zImage initrd eboot 0 61000000 input filename boot zImage initrd bin start 0 01000000 input filedes 3 ink lInput Mem start 0x40001000 length 14B890 0 40142890 binerom Image length 14898 NOTE You may want to customise this script to meet special requirements of vour target hardware For instance you could add the commands neccessary to copy the boot files to a floppy disk or to the download directory of your tftp server Ihe script is located here fhome wagenerw Hello Clone ELE makeboot star MvARE vrd1814 eboot initrd mips rake ELK helloELK 5 6 3 Downloading an ELinOS Project to startWARE Linux VRA181A Af
82. tage converter connector X7 LCD display connector X8 Touch panel connector X9 1 V12 1 1 TPXI 2 2 3 GND 3 3 5 GND 7 GND 26 GND ENAB 28 VDIS VDIS 30 GND GND 32 GND 30 Preliminary User s Manual U16646EE2V0UM00 Chapter4 Detailed Functional Description Figure 4 11 LCD display connector X7 X8 X9 front view PCB top side X9 X8 X7 1 1 1 Mg 4 4 8 Ethernet Connector X10 The VR4181A evaluation board provides a standard RJ45 ethernet connector with integrated status LEDs The green LED indicates an ongoing transfer the yellow LED indicates the speed of the cur rently established Ethernet connection LED on 10 Mbps LED off 100 Mbps Figure 4 12 Ethernet connector X10 pin assignment green LED yellow LED transfer 10 100 Mbit 3 Re L4 Ne 25 Ne _6 Rc Preliminary Users Manual U16646EE2V0UM00 31 Chapter4 Detailed Functional Description 4 4 9 CompactFlash Connector 11 The VR4181A supports a maximum of two CompactFlash slots one of them CF0 is made available on CompactFlash connector X11 If required a second CompactFlash slot can be realized with external hardware Connector X11 provides a 3 3 V slot Figure 4 13 CompactFlash connector X11 pin assignment as originally specified Caution 32 nlOWR 10 09 nWE 11 08 RDY IREG 12 A07 VCC2 13 nCSEL 14 A06 nVS2 A05 RESET A04 nWAIT A03 nINPACK A02 nRE
83. tension connectors Mictor Connectors for measurement purpose 4 LEDs for lowest level debugging purposes 10 DIP switches for selection of SDRAM clock bus clock and other settings oingle Voltage Power Supply startWARE WinCE VR4181A and star WARE Linux VRA1814A are additionally equipped with A 5 5 QVGA TFT display NEC NL3224BC35 20 with back light power supply Touch screen panel Plastic housing The common board software on both versions consists of three monitor programs A simple download monitor program named S Boot The S Boot monitor downloads files to the processors SDRAM and or Flash memory and optionally starts the program A standard terminal emulation program can be used on the host PC side for communication The E Boot download monitor for high speed downloads via Ethernet E Boot is identical to the WinCE Ethernet Bootloader The Green Hills target monitor that can communicate with the Green Hills Multi Compiler Debugger on the host PC Preliminary User s Manual U16646EE2VOUMOO 15 Chapter2 Board Features Depending on the starWARE VR4181A version you will also find the following software added For starWARE GHS VR4181A an evaluation license of Multi 2000 is included in the package on CD e On starWARE WIinCE VR4181A a complete WinCE 4 1 operating system is pre installed e On stariWARE Linux VR4181A the ELinOS Embedded Linux Operating System V2 2 is pre installed The ELinOS tool chain is included in
84. ter generating the Linux operating system on command line or GUI level the new binary file must be downloaded to the starWWARE Linux VRA181A board This is done using the E boot monitor on the starWARE VR4181A board and a utility called ethload that is part of the ELinOS distribution The startWARE VR4181A board and your host computer must have a serial and an Ethernet con nection Preferably your network environment should provide DHCP service and the Ethernet connec tion between target board and host PC should go via an Ethernet hub Before the actual download takes place additional settings must be done on the target side Start a ter minal emulation on the host PC 115200 bps 8 bits no parity 1 stop bit no flow control and reset StarftWARE Linux VR4181A This will start execution of the S Boot monitor program and your terminal window will show you a message as shown in Figure 5 2 Startup Screen on page 40 S Boot must be configured in such a way that the E Boot monitor is the default executable file details are given in Chapter 5 2 4 Flash Option menu on page 42 Next the target must be reset again S Boot and sub sequently E Boot monitors will be executed E Boot will generate a message as shown if Figure 5 13 E Boot start up message on page 57 and prompt you for a static IP address If your environment provides a DHCP service no further action is required E Boot will wait for three seconds and then contact the DHCP ser
85. the boot sector should always be protected The option is disabled on starNNARE VRA1814A Flash status menu Opens a submenu handling the various Flash options Preliminary User s Manual U16646EE2VOUMOO 41 Chapter5 Board Operation 5 2 4 Flash Option menu There are several options available making the handling of the Flash memory easier Several target applications may reside in Flash memory and can be managed by S BOOT Figure 5 4 S Boot Flash Menu Start WARE GHS R41314 HyperTerminal E _ x Connected 0 13 14 Auto detect 115200 8 1 SCROLL caps Num Capture Print echo 42 File Edit Call Transfer Help NEC Bootloader Wer 4 22 LE 4P ES Flash Menu 1 List all VALID blocks 2 Imnvalidate a block 3 Make block DEFAULT executable 4 Change block description 5 Execute program in block 6 Erase entire device Create a block entry select the menu item any key to return to main menu _ EL List all VALID blocks Displays a list of applications available in the Flash memory The default screen on starWARE GHS VR4181A looks as shown in Figure 5 5 S Boot Directory List for startWARE GHS VR4181A on page 43 Invalidate a block Disables the directory entry and makes the application unavailable for the next boot process Make block DEFAULT executable Gives the option to boot an application from a block specified by the user after the S Boot count down has expired The applica
86. tion must have a valid entry in the directory block structure before it can be started by default boot process Here the GHS target monitor is the default application to start with The least recently downloaded application to Flash will automatically get the DEFAULT boot flag This menu entry gives the user the option to change it manually Change block description Allows to change the block description of a downloaded application if the automatically provided name is not sufficient It is a simple text entry to name that directory entry into a more specific description A maximum number of 32 characters is allowed here Execute program in block Offers the option to start any of the available applications manually Erase entire device The entire FLASH device is erased except for the protected boot block All applications are lost and the directory entry list is emptied as well Create a block entry Allows manual entry of start and entry address of a program block This way become necessary after download with a software other than S boot Preliminary User s Manual U16646EE2VOUMOO Chapter5 Board Operation Figure 5 5 S Boot Directory List for startWARE GHS VR4181A Start WARE GHS R41314 HyperTerminal File Edit Call Transfer Help NEC Bootloader Entry Address Entry address 01 BFCZO03B 02 4 40004 press any k
87. ully To work on it type sh cd home wagenerw src elinos Hello Clone sh ELINOS sh CLONING DONE 66 Preliminary Users Manual U16646EE2VOUMOO Chapter5 Board Operation After successful cloning the new project has been generated under you yourcomp Hello Clone The next step is now to source the newly generated script ELINOS sh When this script is asking for input after sh please enter make boot as shown below Make boot starts a lengthy process and the out put messages are not printed below sh Hello Clone shi ELINOS sh STARTING ELINOS SESSION Setting up CDK mips rokle for Libes SELINOS BOARD StartWARE Vr4181A SELINOS BIN PREFIX mips r3kle SELINOS PROJECT home wagenerw src elinos Hello Clone SELINOS DOSNAME hello OCC mips r3kle gcc SCXX mips r3kle g SAS mips_r3kle as SGDB mips r3kle gdb sh make boot The project is now ready to download download itself is described in Chapter 5 6 3 Downloading an ELinOS Project to startWARE Linux VR4181A on page 70 Preliminary User s Manual U16646EE2VOUMOO 67 Chapter5 Board Operation 5 6 2 Hello World Project Using ELK The ELinOS development environment contains a graphic configuration tool named ELK Embedded Linux Konfigurator This chapter will basically describe how to repeat the steps from the previous chapter in a more graphic windows style fashion After ELK has been started with sh opt elinos bin e
88. ven in Chapter 5 2 4 Flash Option menu on page 42 Next the target must be reset again S Boot and sub sequently E Boot monitors will be executed E Boot will generate a message as shown if Figure 5 13 E Boot start up message on page 57 and prompt you for a static IP address Preliminary User s Manual U16646EE2VOUMOO 55 56 Chapter5 Board Operation Figure 5 12 Configuring a Remote Connection Configure Remote Connection medi 0 mr Use Hardware Debugger 2101 Configure Ethernet Download Service 11 Preliminary User s Manual U16646EE2VOUMOO Chapter5 Board Operation Figure 5 13 E Boot start up message StartWARE YR4181A HyperTerminal E File Edit View Call Transfer Help trying SDRAM trying FLASH ix at address OxBFC40004 Microsoft Windows CE Ethernet Bootloader Common Library Version 1 0 Built May 24 2002 21 50 41 Copyright 2000 2001 Microsoft Corporation Microsoft Windows CE Ethernet Bootloader 4 0 for 41813 Feb 6 2003 EBOOT Ver 1 30 clock report ACLOCK 131 MHz TCLOCE 65 MHz LCLOCK 32 MHz TSHCInit Ethernet card detected at I O base 4000200 Ethernet Address OO 0C 32 00 00 26 SHCInit lir W W Y T W rr rr lr rr rr rr nr rr r TW W rr TW 5 SMC Ethernet Address 00 07 32 00 00 2 6 5 Device name
89. ver via broadcast An IP address will be automatically assigned to the target and the starAWARE VR4181A board will begin to broadcast a BOOTME message into the network If no DHCP service is available the IP address for the target must be entered manually Hit Enter within three seconds after E Boot begins to prompt for the IP address and then specify an IP address which is in the same subnet than the host PC and which is not used by any network adapter in the host Normally the first six digits are identical to the IP address of the host the rest is different Next E Boot will prompt for a subnet mask normally 255 255 0 0 can be used for this purpose 70 Preliminary Users Manual U16646EE2VOUMOO Chapter5 Board Operation When address and subnet mask have been correctly specified the target will broadcast BOOTME to the network as in the DHCP case Now the ethload utility must be started in your ELinOS shell like this sh opt elinos bin ethload SE boot zlImage initrd eboot Ethload will then try to find a boot device in the network after finding a device the specified file will be downloaded Ethload s responses will look like this ethload v1 2 c 1999 2001 Ludovic LANGE ethload comes with ABSOLUTELY NO WARRANTY for details see COPYING This is free software and you are welcome to redistribute it under certain conditions see COPYING for details Waiting for any device to boot Got BOOIME from device 172 29
90. w project the easiest way of doing this is cloning an already existing reference project with the clone project function Cloning allows but does not require changing the project name and important configuration parameters The ELinOS installation already comprises a project named Hello which can be cloned to the new project Hello Clone in the Linux shell like this yvouGyourcomp elinos 5 opt elinos bin elinos cloneproject opt elinos7 demos Hello Hello Clone CLONING PROJECT Hello Clone FROM opt elinos demos Hello Checking existing project Jyopt elinosy demos Hellos s ok Checking new project Hello Clone ok Cloning project optyelinos demos Hello as OK CONFIGURING PROJECT Current Settings ELINOS BOARD custom CPU mips FL LNOS ARCH r3kle ELILNOS hrBC 1 6 ELINOS DOSNAME hello ELINOS BOOT SIRAT floppy Please select your board type 1 startWARE VR4181A 2 UMC VR4181A 3 custom Board Type custom 1 Now enter 1 to select the starWARE VR4181A board Next you are prompted for the name of the new project Project Name 8 characters at most no blanks hello Preliminary User s Manual U16646EE2VOUMOO 65 Chapter5 Board Operation We take over the project name as it is by hitting the return key You must now select the boot strategy for your new project 1 zImage simple zImage 2 zlmage_initrd zlmage with embedded ram
91. yte of main memory implemented in one physical bank and realized with two SAMSUNG 4 2816320 128 Mbit SDRAM chips connected to the SDCSO chip select They can be accessed with a maximum SDRAM clock frequency of 65 5 MHz The physical address map for this memory is 0x0000 0000 to 0x01FF FFFF CPU address is 0 000 0000 to OxA1FF FFFF for uncached or 0x8000 0000 to 0x81FF FFFF for cached accesses Preliminary User s Manual U16646EE2VOUMOO 17 Chapter 3 Functional Description 3 3 Memory Mapping The VR4181A uses a flexible memory mapping scheme that allows to move certain address blocks within the device s total addressing space The 32 bit physical address space encompasses a total of 4 GByte however these 4 GByte consist of 8 mirror images of a 512 MByte space subdivided in SDRAM ROM and I O spaces The most significant address bits control if the 512 MByte space is accessed cached or uncached respectively mapped or unmapped Figure 3 1 shows an example for the memory map of the starWARE VR4181A board for uncached and unmapped addresses kseg1 ranging from 0xA000 0000 to OxBFFF FFFF This configuration is used by the WinCE operating system that is pre installed on the VR4181A evaluation board Note that the same structure is seen for other address space segments like ksegO 0x8000 0000 to Ox9FFF FFFF Consult the processor documentation for details 3 4 VR4181A Communication Interfaces starWARE VR4181A has the most important commun

startWARE-GHS-VR4181A, startWARE-WinCE

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