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User Manual DNMEG_V6HXT
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1. 00 C 95401 Guo exi Figure 34 FMC Pin Assignments HPC 96 inigroup com www d DNMEG_V6HXT User Manual HARDWARE DESCRIPTION 7 3 Power and Reset The Texas Instruments PTHO8T230WAZ DC DC Converter is used to create the VADJ supply for the FMC Mezzanine Card set to 2 5V 6A see Figure 32 TP22 12 R34 100R 1 VADJ F5 PSU1 EN 1 gt 12VFUSED FI NY f p TT 2 vin P_FMC_VADJ 29 7 C531 C530 C56 C40 TIRANS C66 C68 C537 C532 C74 47uF 1500 1500 470 FMC TRACK 9 RACK senge 5 __ P_EMC_SNSp 2 2uF 47uF Sb 330uF L 330uF SL 33042 16V 16V 16V 16V 16V SENSE Le P FMC SNSn 6 3V 6 3V 6 3V ji 6 3V T 6 3V 20 20 20 20 10 20 20 20 20 20 TANT TANT CER GER TANT TANT TANT 8 1 7 e SMARTSYNC VoADJ N2n UN P FMCn 2 pg16 29 30 PSU SEQ EN2n lt WS 1K THOBT230W DIP10 Silkscreen VOLT ADJ Note Place Jumper and VADJ resistors close PTHOBT230WAZ j to pin 6 7 of the PSU The jumper option piso eias pa T d b may degrade performan
2. P3 3VD P2 5VD P2 5VD o o o R633 5 R632 lt gt R629 lt gt R628 R631 lt gt R630 R627 R626 J36 1 lt 4 7K lt 47K lt 47K 4 7K 4 7K lt 47K 1 1 20 SFP_LS1_TxFAULT 2 VEET VEET 19 SFP_LS1_TxDn 917 SFP_LS1_TxFAULT XK SFP TSI TXDTS 1 IXFAULT TD SFP STDP pg17 SFP_LS1_TxDIS lt SFP IST SDA IXDISABLE H7 pg18 151 SDA lt lt SFP IST 5 SDA VEET 16 P3 3V VCCT 151 918 151 SCL lt lt 6 15 _5 51 917 LS1 MOD ABSXC sFP LS1 RS0 7 VOD ABS aq pg17 151 RS0 C SFP TET HxLOS 1 8 VEER 43 151 RxDp 917 SFP 151 HxLOS SFP LS1 RSi 1 g LOS RD 12 SFP LSi RxDn pgi7 SFP L81 RS1 107 RS1 RD Hii t 4 P3 3VD TINK VEER VEER 9 2007637 8 E R658 150R LED SFP 151 0515 LED GRN m Figure 25 SFP Interface channel 1 shown Refer to pat 3 2 GTX GTH Transceiver Clocks for clocking information 4 3 3 Connections between 2x2 SFP Connectors and the FPGA Due to an IO constraint on the FPGA all the SFP control signals are multiplexed using a CPLD U53 The I C signals are routed point to point directly to the FPGA IO Bank 35 Table 27 lists the connections between the 2x2 SFP connectors J36 J37 and the FPGA 034 Table 27 Connections between 2x2 SFP Connectors and the FP
3. R344 R343 78 78 78 78 PCI Express Clock Source LVDS CLK Monitor TP PCIE RECLK 1 55 3 ___ _ 1 r R56 18 eee pr S gs PCIEI RECLKn e 13 CLP PCIET QA0n R57 OR ONERE PCIE CLKn QA0n ONI 4 7K 4 7K 7 1 CIK PCIE QAipr R51 PCIE 1 R351 100R 20 GLK PCIET 1 R46 OR CLK PCIET CLK F SELO 6 scio TP24 POIELGIKT SELL 9 PCIET_CLKF SEL2 16 F SE CLK _ 11 8 GLK ___8364 108 CLK OEB 15 Moa 5 0 01uF 10uF PCIE CLK MR 5 2 sov 63 6 3V Vibe 10 220 20 Rage Rass Rass R349 Rose 34 veo 0 5874003 057 55 57 1555 8740038G 05LF 2 2uF 2 2uF 2 2uF Tes 6 3V 6 3V Note Default Setting 250MHz Figure 20 PCI Express Clock Jitter Attenuator 3 3 1 Selecting between Upstream or Downstream Auxiliary Signals In order to toggle between upstream and downstream mode DIP switches on the board need to be set e To set PCIE Cable Connection Port 0 3 to Upstream Mode turn ON all switches on dipswitch S1 Turn OFF
4. Signal Name SFP Connector FPGA SFP_LS8_RS1 J37 69 U53 96 SFP_LS8_RXLOS J37 68 U53 97 SFP_LS8_SCL J37 65 034 10 158 SDA 37 64 U34 K10 SFP_LS8_TXDIS J37 63 U53 126 SFP_LS8_TXFAULT J37 62 U53 125 High Speed Interconnect from SFP Connectors to FPGA 034 SEP 151 TXDP 36 18 U34 AA3 SFP LS1 TXDN 36 19 U34 AA4 SFP_LS1_RXDP 36 13 U34 Y5 SFP LS1 RXDN 36 12 U34 Y6 SEP 152 TXDP 36 38 U34 Y1 SFP LS2 TXDN 36 39 U34 Y2 SFP 152 RXDP 36 33 U34 W7 SFP LS2 RXDN 36 32 U34 W8 SEP LS3 TXDP 36 58 U34 W3 SFP LS3 TXDN 36 59 U34 W4 SFP_LS3_RXDP 36 53 U34 V5 SFP LS3 RXDN 36 52 U34 V6 SFP LS4 TXDP J36 78 U34 V1 SFP_LS4_TXDN 36 79 U34 V2 154 RXDP 36 73 U34 U7 SFP LS4 RXDN J36 72 U34 U8 SFP_LS5_TXDP J37 18 U34 AE3 SFP_LS5_TXDN J37 19 U34 AE4 SFP_LS5_RXDP J37 13 U34 AD5 SFP_LS5_RXDN J37 12 U34 AD6 SFP_LS6_TXDP J37 38 U34 AD1 SFP_LS6_TXDN J37 39 U34 AD2 SFP_LS6_RXDP J37 33 U34 AC7 SFP_LS6_RXDN J37 32 U34 AC8 SEP 157 TXDP 37 58 U34 AC3 DNMEG_V6HXT User Manual www dinigroup com 75 HARDWARE DESCRIPTION Signal Name SFP Connector SFP_LS7_TXDN J37 59 SFP_LS7_RXDP J37 53 SFP_LS7_RXDN J37 52 SFP_LS8_TXDP J37 78 SFP_LS8_TXDN J37 79 SFP_LS8_RXDP J37 73 SFP_LS8_RXDN J37 72 4 4 SFP Interface up to 11 182Gbps The 10GBASE SFP modules offer customers a wide variety of 10 Gigabit Ethernet connectivity options for data center enterprise wiring closet and se
5. 8 3 3v DOn 3 3 TX9p N C 51 OEE Den n 51 DOn CFP D8 12 aav TX8p S1 TX3p 14 93V GND 15 3 3V TXn 1_ 2 Te 3 3V 51 3 3V_GND GND CFP Tx 1 3 3V GND TX6n 1_TXin Ep T9 3 3V GND TX6p 51 20 3 3V GND GND 3 3V_GND TX6n S1_TXOn xl WD 10 A S1 TX0p 55 GND Dn R59 DNI CFP_TX MCLKn 1 24 GND Dan CFP D p pui TX MCLK R59 DNI CFP TX MCLKp 25 4 26 MCLKp GND DGn 37 GND 9 Tan x ND I0 C 9 TX3p X 29 VND_IO_D A GND CFP DOn 4 ND IO E Ten T pg29 CFP_PRG_CNTL1_a3 lt lt at 33 30 CNTLI p 929 PRG CNTL2 33 lt CEP PRG CNTL3 33 32 PRG_CNTL2 GND PRG CNTL3 33 lt lt PRG ALRMI 33 55 5 CFP TXip pg29 PRG ALRM 33 X amp cFP PRG ALRM2 33 34 PRG 929 PRG ALRN2 33 lt lt CFP PRG ALRM3 33 35 PRG ALRM2 n GND Txon 929 PRG ALRM3 33 lt lt Tx DIS PRG_ALRM3 pe Txon 29 TX DIS 33 36 Tx Dis MOD LOPWR 33 37 m p pg29 CFP MOD LOPWR_33 MOD ABS 33 38 MOD LOPWR GND 929 MOD ABS 33 MOD ABS a GND 51 RX pg29 MOD RSTn
6. SFP_HS4_RXDN J38 12 4 5 GTX Expansion Interface 224 pin high speed header is provided to allow the user access to the GTX Transceiver pairs on the FPGA The SEAM interface provides 8 differential channels of high speed serial data to the FPGA Differential Pair signaling is specified to operate up to 10 5GHz or 21Gbps see Samtec Performance Specification Dini Group provides some daughter cards for this form factor currently available is e DNSEAM 4 e DNSEAM PCIE e DNSEAM SEP The GTX Expansion Interface could also be used to connect to a custom daughter card The boatd is populated with a Samtec P N SEAM 20 03 5 S 08 2 A and mates with a Samtec P N SEAE 20 03 5 S 08 2 A on the daughter card 4 5 1 GTX Expansion Circuit Diagram Eight high speed differential channels connect directly to the GTX Transceivers on the FPGA 034 Four REFCLK signals are provided DNMEG V6HXT User Manual www dinigroup com 80 HARDWARE DESCRIPTION CLK_REFCLK_SEAMG_A0 1p n and CLK_REFCLK_SEAMG_B0 1p n making four independent interfaces on one DNSEAM connection possible Additionally for the purpose of control there are 16 low speed IO signals that connects to FPGA IO pins routed as LVDS pairs A REFCLK is provided for source synchronous applications SEAMG_IO_D0 1p n_CC These signals are routed to clock capable pins on the FPGA Low speed IO is fixed at 2 5V signaling levels Three voltages are provide
7. 1 5 2 Connections between FPGA and the 39 KOL 85232 POT i esa 40 1 6 1 5232 Circuit Diagram 40 1 6 2 Connections between FPGA and the 5232 Port 40 1 7 Backup Battery nocens 2 41 1 71 Backup Battery Circuit 1 7 2 Backup Battery Loads 18 VCCINT Switching Power Supply 2 2 1 2 2 LED Serial POrt RS232 qaa aspa es 2 2 1 5232 Circuit Diagram 52 222 Connections between MCU LCD and the 5232 44 2 3 Temperature Montforiys a rete ON vain eet ete Yale te hee 44 2 3 1 Temperature Sensor Circuit 232 Connection between the MCU and Temperature Sensor ecceceescesesseesseseeeseeseesecsecseceeceseeseesecsecaececeseeaeesecsecaeceseaeeaeeaecaeeneeeeeeeeenees 45 ENTIS 3 CLOCKING NETWORKS id 3 1 CLOCK Methodology 3 2 GTX GTH Transceiver 49 324 GTX GTH Transce
8. 9 1 Board Dimensions 9 2 JStandard Daughter Card Size i ec e Re Y HR IM URINE GU rhe ea done 120 93 Daughter Card Spacing sotran tei die 120 APPENDIX 122 10 APPENDIX AS 122 11 ORDERING INFORMA TION D DNO aa ua unupa m ALGUNOS TLD LE SCRE aaa oes 122 List of Figures Figure 1 DNMBG VGH XT Logie Em lation Board 2 Figure 2 USB Flash Drive Directory Structure Figure 3 DNMEG V6HXT Logic Emulation Board Block Diagram Figure 4 Mode Select Resistors M 2 0 default Slave Select MAP Figure 5 FPGA JTAG Interface Figure 6 DDR2 DD3 SDRAM Memory Interface Solution Figure 7 UDIMM Switching Power Supply 1 5V Figure 8 VTT Linear Power Supply 4 0 75V Figure 9 FPGA EEPROM Figure 10 CFPGA MCU Serial Port Figure 11 Backup Battery Supply Figure 12 VCCINT Switching Supply for the FPGA Figure 13 USB2 0 Host Type A Figure 14 LCD Serial Port RS232 Figure 15 Temperature Sensor Figure 16 MCU Trace Debug Header Figure 17 Clocking Block Diagram Figure 18 GTX GTH Clock Circuit Figure 19 PCI Express Cable Reference Clock Buffer HCSL Figure 20 PCI Express Clock Jitter Attenuator Figure 21 SATA II Clock Oscillator Figure 22 Daughter Card Global Clock Input Output Figure 23 Daughter Card Header Feedback Clock Figure 24 MEG Array Daughter C
9. _ J24 42 GTP_SEAMG_RXAOP J24 10 GTP_SEAMG_RXAON J24 18 34 P13 34 N13 34 515 34 015 34 14 34 14 34 H14 34 G14 34 K13 34 13 34 115 34 815 34 15 34 145 34 13 34 013 C 34 AN8 34 AN7 34 AH10 34 AH9 34 AF10 34 AF9 34 AD10 34 AD9 34 AN3 34 AN4 34 AL7 34 AL8 eee a Gey GG DNMEG_V6HXT User Manual www dinigroup com 82 HARDWARE DESCRIPTION Signal Name GTX Expansion FPGA Header 34 1 34 2 34 5 34 34 AL3 34 AL4 34 AJ7 34 AJ8 34 1 34 2 34 5 34 34 34 34 5 34 34 AH1 34 AH2 34 8 34 34 34 4 34 AF5 34 34 AF1 34 AF2 34 34 8 GTP_SEAMG_TXA1P J24 36 SEAMG 1 24 44 GTP_SEAMG_RXA1P J24 12 GTP_SEAMG_RXAIN J24 20 GTP_SEAMG_TXA2P 24 66 GTP_SEAMG_TXA2N J24 58 GTP_SEAMG_RXA2P J24 14 GTP_SEAMG_RXA2N J24 22 GTP_SEAMG_TXA3P J24 68 GTP_SEAMG_TXA3N J24 60 GTP_SEAMG_RXA3P J24 38 GTP_SEAMG_RXA3N J24 46 GTP_SEAMG_TXBOP J24 127 GTP_SEAMG_TXBON J24 119 GTP_SEAMG_RXBOP J24 151 GTP_SEAMG_RXBON J24 143 GTP_SEAMG_TXB1P J24 125 GTP_SEAMG_TXBIN J24 117 GTP_SEAMG_RXBIN J24 141 GTP_SEAMG_RXB1P J24 149 GTP_SEAMG_TXB2P J24 103 GTP_SEAMG_TXB2N J24 95 GTP_SEAMG_RXB2P J24 147 GTP_SEAMG_RXB
10. FB8 P2 5VF OSC SATA GND VDD C SIS34 SMT 8 2 2uF BLMISAGI025N1D LV7745DW 150 0M 400 Note Frequency 150MHz Figure 29 SATA II GTX Oscillator 4 6 2 Connections between FPGA and SATA Connectors Table 31 shows the connections between the FPGA GTX Transceivers and the SATA II connector pins Table 31 Connections between FPGA and SATA II Connectors Oscillator Signal Name OSC SATA FPGA SATA Clock CLK_SATAP 2 4 34 V35 CLK_SATAN X25 34 V36 OSC SATA FSO 2 8 34 AN34 OSC_SATA_FS1 07 34 34 1 MGT105 SATA1 TXP 172 34 42 SATA1_TXN 77 3 34 41 1_ 17 6 34 Y40 SATA1_RXN 17 5 34 39 SATA 2 DEVICE MGT105 SATA2_TXP 16 2 34 738 SATA2_TXN 16 5 34 737 SATA2 J6 6 34 Y44 SATA2_RXN Jo 5 34 Y43 SATA 3 HOST MGT105 SATA3_TXP J13 2 34 W42 SATA3_TXN J13 3 34 W41 DNMEG_V6HXT User Manual www dinigroup com 85 HARDWARE DESCRIPTION Signal Name OSC SATA SATA3_RXP J13 6 SATA3_RXN 13 5 SATA 4 DEVICE 105 4_ 19 2 SATA4 TXN 19 3 4 19 6 4 RXN j9 5 4 7 PCI Express Cable One iPass connector x4 configured for PCI Express DownStream and one iPass connector x4 configured for PCI Express UpStream is connected to the FPGA The PCI Express External Cabl
11. 15 ieee ave 24 RXi 16 23 QSFP1_RXip 1 17 0 GND 22 QSFP1_RXx2p OSFPT_AXIn 185 RXip QSFPTI HXn 187 RX2n 50 1 19 end 29 34 39 CAGE cace IH CAGE CAGE 42 CAGE Hay 42 CAGE Hig 41 CAGE ae CAGE CAGE Loc toc Hx CONN GSFP 1761987 9 4 2 2 Connection between Connectors and the FPGA Table 25 shows the connection between the QSFP connectors and the FPGA Table 25 Connection between the QSFP Connector and the FPGA Signal Name QSFP Connector Clocking CLK_QSFP_MGT117P U40 11 CLK_QSFP_MGT117N U40 12 CLK_QSFP_MGT118P U40 9 CLK_QSFP_MGT118N U40 10 QSFP 1 QSFP1_TX1P J34 36 QSFP1_TX1N J34 37 QSFP1_RX1P J34 17 QSFP1_RX1N J34 18 QSFP1_TX2P J34 3 QSFP1_TX2N J34 2 QSFP1_RX2P J34 22 QSFP1_RX2N J34 21 QSFP1_TX3P J34 33 QSFP1_TX3N J34 34 QSFP1_RX3P J34 14 Cr Gy C C Gara DNMEG_V6HXT User Manual www dinigroup com 68 HARDWARE DESCRIPTION Signal Name QSFP Connector QSFP1_RX3N J34 15 QSFP1_TX4P J34 6 QSFP1_TX4N J34 5 QSFP1_RX4P J34 25 QSFP1_RX4N J34 24 QSFP1_INTN J34 28 QSFP1_LPMODE 34 31 QSFP1_MODPRSN J34 27 QSFP1_MODSELN J34 8 QSFP1_RESETN J34 9 QSFP1_SCL J34 11 QSFP1_SDA J34 12 QSFP 2 QSFP2_TX1P QSFP2_TX1N QSFP2_RX1P QSFP2_RX1N QSFP2_TX2P QSFP2_TX2N QSFP2_RX2P QSFP2_RX2N QSFP2_TX3P QSFP2_T
12. C1026 uF oR 10 TSM 136 01 T DV LTC2804 1 SSOP16 LTC2804CGN 1 PBF Figure 14 LCD Serial Port RS232 The two signals that are relevant to the LCD are Transmit Data MCU_LCD_TXD Receive Data MCU_LCD_RXD DNMEG V6HXT User Manual www dinigroup com 43 HARDWARE DESCRIPTION 2 2 2 Connections between MCU LCD and the 5232 Port The connections between the MCU LCD and the RS232 Port are shown in Table 11 Table 14 Connections between MCU LCD and the RS232 Port Signal Name MCU LCD MCU_LCD_TXD U26 39 MCU_LCD_RXD 026 40 MCU_RS232_TXD1 J31 2 MCU_RS232_RXD1 J31 3 2 3 Temperature Monitor The MCU monitors the FPGA temperature using the MAX6639 U42 The MAX6639 monitors its own temperature and the FPGA diode connected transistor The 2 wite serial interface accepts standard System Management Bus write byte read byte send byte and receive byte commands to read the temperature data and program the alarm thresholds Temperature data can be read at any time over the SMBus and three programmable alarm outputs can be used to generate interrupts throttle signals or over temperature shutdown signals The temperature data is also used by the internal dual PWM fan speed controller to adjust the speed of up to two cooling fans J1 J26 thereby minimizing noise when the system is running cool but providing maximum cooling when power dissipation i
13. CLK DN 2 5 N lt 12V XP12VFUSED_DCA pg24 3 are DCA_CLK_UP_OUTp TOP _ ge UP OUTp TOP lt lt DEA CLK UP CUT TOP F3 UP 25 P RSVD DCA pgi8 DCA_CLK_UP_OUTn_TOP CLK UP 2 5 N gt RSVD_PW p KP M B2 P3 3VFUSED DC 3 3V 1 62 lt P3 3VFUSED_DCA pg24 0466005 NR 2 5V_LDO R16 10K lt lt 4PVGGO DCA Veco cap walpa PES C27 2 2uF 6 3V a CONN_MEGARRAY_84520 102LF 84520102LF Figure 22 Daughter Card Global Clock Input Output DCA CLK FB P N is looped back from an output of the FPGA to a clock input on the same FPGA IO Bank 24 see Figure 23 DNMEG_V6HXT User Manual www dinigroup com 55 HARDWARE DESCRIPTION Meg Array Connector Daughter Card 4 I Your Board Base Board Short Length Device DC_FEEDBACK flip flop vo Input flip flop Figure 23 Daughter Card Header Feedback Clock The routing length of this feedback clock is equal to the routing length of the signals to the Daughter Card header This allows the option to have a clock inside the FPGA that is phase aligned with the arrival of the clock at the Daughter Card header 3 5 2 Connection between MEG Array Daughter Card Clocks and the FPGA The connection between the Meg Array Daughter Card clocks and the FPGA are shown i
14. ATX power supply and verify the ATX PWR OR LED 0528 is ON indicating the presence of 12V located at the bottom left side of the board DNMEG V6HXT User Manual www dinigroup com 12 GETTING STARTED 6 Periods will be displayed when the board is powered ON Verify that the board was correctly identified as a 02187 in the terminal window Serial COM1 CRT File Edit View Options Transfer Script Tools Help 35 33 13 3 BA SSI 9 M Seria COM1 Detected DNO218 Main Menu DDR3 Test requires ECC module Set 515338 Clks RocketIO Test Restart and Check status RocketIo Test Check status only I2C Test Test requires loopback connector Clock Frequencies check Misc Pins Test FMC IO Test requires FMC loopback connector Enter Option AND ENTER Serial COM1 29 1 29 Rows 78 Cols VT100 3 Using the Reference Design Main This section lists detailed instructions for executing the reference design Ensure the DNV6 HXT Logic Emulation board is powered ON and a Terminal Window is open to exetcise the reference design options 7 Select test option 6 Clock Frequencies Check in the Terminal window and vetify that the test displays VALID frequencies DNMEG V6HXT User Manual www dinigroup com 13 GETTING STARTED 58 Serial COM1 File Edit View Options Transfer Script Tools Help 3 33 122 5 44 1453 9 Seria COM1
15. B12 P5 A13 B0 N4 5 814 0_ 5 P6 A15 BO_NS DCA 6 16 B0_P6 P7 17 7 B18 ae GCC BUS Es 80 N8 GCC BUS F5 BO_P8_GCC_BUS BO H3 BO_N8_GCC_BUS G4 0 9 P10 Hs BO_N9 0 N10 G6 0 10 DCA BO 11 H7 BO_N10 DCA NTI Gg 0 11 12 BO_N11 DCA N12 610 0_ 12 13 H11 B0_N12 B0 N13 G12 0_ 13 14 H13 DCA N14 614 0 14 0 15 H15 0_ 14 0 15 016 0 15 P16 H17 15 B0 N16 G18 B0 P16 P17 H19 BO_N16 N17 20 9 17 BO N17 PYCCO DCA BO A6 C16 B0 VCCO 2 2uF N PLUG 2 6 3V CONN MEGARRAY 84520 102LF 84520102LF Figure 24 MEG Array Daughter Card Clock Secondary 3 5 4 Connection between MEG Array Secondary Clocks and the FPGA The connection between MEG Atray secondary clocks and the FPGA are shown Table 22 These signals may be used as inter connect or clocks Table 22 Connections between MEG Atray Secondary Clocks and the FPGA DC Headers FPGA Daughter Card Bank 0 DNMEG V6HXT User Manual www dinigroup com 57 HARDWARE DESCRIPTION Signal Name DC Headers FPGA DCA B
16. supported Microprocessor driven SelectMAP configuration mode x8 e JTAG Boundary Scan configuration mode The configuration modes are explained in detail in Chapter 2 Configuration Interfaces of the 00360 Virtex 6 FPGA Configuration User Guide The specific configuration mode is selected by setting the appropriate level on the dedicated Mode input pins M 2 0 DNMEG V6HXT User Manual www dinigroup com 16 PROGRAMMING CONFIGURING THE HARDWARE 2 Configuring the FPGA using USB Flash Drive Xilinx does not provide a SPI Flash configuration solution for devices requiring bitstream lengths larger than 128Mb As a result a custom configuration solution using the NXP LPC1754 32 bit ARM microcontroller and was developed The user would transfer the bitfile to a USB Flash Drive and the DNMEG_V6HXT will configure the FPGA via SelectMAP x8 The microcontroller MCU provides an USB 2 0 full speed HOST interface that allows for fast FPGA configuration Table 2 shows the uncompressed configuration file size for the supported Virtex 6 devices Table 2 Virtex 6 Uncompressed Bitstream Length Device Data Size Bits XC6VHX380T 119 784 608 XC6VHX565T 160 655 264 2 1 Setup Configuring the FPGA using USB Flash Drive Before configuring the FPGA ensure the following steps have been completed 1 Attach an ATX Power Supply to the ATX PWR header J3 2 Insert a USB Flash Drive in the USB
17. the mating connector is readily available Dini Group can provide the mating connector at cost custom User daughter cards The 192 signals 96 pairs to from each of these MEG Array expansion connectots are routed differentially and can run at the limit of the Virtex 6 108 710 MHz Clocks resets and presence detection along with abundant fused power are included in each connector DNMEG V6HXT User Manual www dinigroup com 24 HARDWARE DESCRIPTION FMC Vita 57 FPGA Mezzanine Card or FMC as defined in VITA 57 provides a specification describing an IO mezzanine module with connection to an FPGA or other device with reconfigurable IO capability Most vendors of FMC daughter cards tend to ignore the specification making this interface standard a questionable option Also the total number of IOs in the specification is much too small But there are some good A D and D A cards that adhere enough to the specification to be useful Easy Configuration via PCIe USB or Ethernet Configuration of the FPGAs is under the control of an embedded CPU an ARM based LPC1754 from NXP Xilinx is not nice enough to supply a serial PROM large enough to configure the XC6OVHXT565T so we need to use rather exotic methods to create enough onboard EEPROM storage for this function Status LEDs Debug As with all of our ASIC emulation boards DNMEG_ V6HXT is loaded with LEDs The LEDs are stuffed in several different colors red green
18. Enter Option CAND ENTER ref 50 000000 Mhz CLK50 49 948079 Mhz CLK200 199 792316 Mhz CLK100 99 896158 Mhz DCLK BOT 0 000000 Mhz DCLK TOP 0 000000 Mhz DCLK 99 896158 Mhz RIO T 100 106 542056 Mhz RIO 101 97 040498 mhz RIO 102 0 000000 Mhz 204 724818 Mhz 205 295950 mhz 149 844237 mhz 0 000000 mhz 0 000000 Mhz 0 000000 Mhz 0 000000 Mhz 0 000000 Mhz 105 815161 Mhz 92 782970 Mhz 0 000000 Mhz 0 000000 Mhz 108 099688 Mhz 107 528557 Mhz 109 813084 Mhz 0 1 2 3 4 5 6 7 8 9 RIO RIO RIO RIO RIO RIO RIO RIO RIO RIO RIO RIO RIO Serial 1 29 1 29 Rows 78 Cols VT100 CAP NUM 8 Select test option 0 DDR3 Test ECC module required in the Terminal window and verify that the test PASS periods will be displayed as the memory locations ate being tested no DDR3 Module is present the test will display read write errors Serial COM1 CRT File Edit View Options Transfer Script Tools Help Era SJ 23 dA BSE sp spd col 0 0000000 spd bank 0 00000003 spd rank 0 00000009 Main Menu DDR3 Test requires ECC module Set 515338 Clks RocketIO Test Restart and Check status RocketIo Test Check status only I2C Test MegArray Test requires loopback connector Clock Frequencies check Misc Pins Test FMC IO Test requires FMC loopback connector Enter Option
19. PCIE2BUE lt PCIE2BUF FPGAp PCIE BUF IREF 10 SMO 11 CLK PCIE4BUF CABLEn r R40 PCIE2BUF FPGAn AQ CK PCIE2BUF FPGAR 2 TP19 Silkscreen 3 3V GND IN R48 16 15 1 R44 R33 4758 GND VDDOUT FBI P3 3V_PCIE_CLKBUF 49 98 lt 49 9R 05557 067755 20 5 PCIE gueur ri ao 48 9 L ICS557G 06LF C78 078 C P Tes 0 01uF 0 01uF BLM18AG102SN1D 10uF 50V 6 3V 400mA 6 3V Control Signal Setup 1 5557 06 10 10 26 20 CER CER CER 1 Input Selection IN1p IN1n 2 NOT powered down 3 All outputs enabled Figure 19 PCI Express Cable Reference Clock Buffer HCSL PCI Express Clock Jitter Attenuator Upstream to Downstream In addition a resistor capacitor network is provided for the user to select the soutce destination of the clock signals see Figure 20 DNMEG V6HXT User Manual www dinigroup com 52 HARDWARE DESCRIPTION 4 CLK PCIETBUF CABLEp X CTR PCTETBUF CABLES CABLEn Note These components PCIE1 are Note Multiple Termination Share pade ratar to the layout guidelines under certain see clock page R37 Eds for more information 1378 1378 CLK PCIETBUF FPGAp C63 DNI OR 4 C53 oR CLK POIEIBUF FPGAp 49 FFGAn DNLOR T 052 OR pg3 PCIE1BUF FPGAn m
20. The following Rules and Observations are extracts from the FMC specification reference the ANSI VITA 57 1 FPGA Mezzanine Card FMC Standard for more information Observation 5 11 2 CLK1 M2C are defined in the high pin count and low pin count connectors Observation 5 12 CLK2_BIDIR CLK3_BIDIR are defined in the high pin count connector Rule 5 18 Clocks 2 CLK1_M2C shall be driven by the IO Mezzanine module and received by the cartier card Rule 5 19 Clocks CLK2_BIDIR CLK3_BIDIR shall be driven by the IO Mezzanine module and received by the carrier card when CLK_DIR is connected to GND or unconnected by the mezzanine module Rule 5 20 Clocks CLK2_BIDIR CLK3_BIDIR shall be driven by the carrier card and received by the IO Mezzanine module when CLK_DIR is connected via a 10K pull up resistor to 3P3V by the mezzanine module Rule 5 21 CLK 0 3 shall be assigned starting with the lowest ordinal and used in ascending order when DIR is connected to GND or unconnected DNMEG V6HXT User Manual www dinigroup com 61 HARDWARE DESCRIPTION Rule 5 22 CLK 0 1 M2C shall be assigned to clocks driving from the mezzanine module to the carrier card starting with the lowest ordinal and used in ascending order when CLK_DIR is connected via a 10K pull up resistor to 3P3V by the mezzanine module Rule 5 23 CLK 2 3 _BIDIR shall be assigned to clocks driving from the carrier card to the mezzani
21. von E 6 SH 1 2 B 8 sua 3 4 7 SH 3 N C 0 N C 1 73725 0110BLF NUP2201MR6T1G TSOP6 NUP2201MR6T1G Figure 13 USB2 0 Host Type A The AP2161 offer current 1 5A and thermal limiting and short circuit protection as well as controlled rise time and under voltage lockout functionality 2 2 LCD Serial Port RS232 dedicated RS232 serial port U52 15 provided for low speed communication with the Matrix Orbital LCD Display P N GLK19264 7T 1U FGW LTC2804 is a dual RS 232 transceiver in narrow SSOP and chip scale DEN package An integrated DC to DC converter generates power supplies for driving RS 232 levels A logic supply pin allows easy interfacing with different logic levels independent of the DC DC supply Part is compatible with the TIA EIA 232 F standard 2 2 1 RS232 Circuit Diagram Figure 10 shows the implementation of the serial port P2 5VD 052 MCU LCD TXD 8215 47K MCU BIN MCU LCD RXD 16 Rout 24 R2ouT R220 4 7K MCU RS232 ON 11 ON OFF 8 TIOUT T2OUT R1N R2IN voc sw VDD VEE MCU_RS232_TXD1 MCU_RS232_RXD1 MCU RS232 SW 12 P2 5VD 5 0 9 N MCU RS232 CAP C343 0 22uF MCU RS232 VDD MCU RS232 10uH LQH2MCN100K02L 1 R670 J31 lt gt P5 0V LCD x 10
22. 29 53 29 68 R608 2 29 79 R609 2 29 195 29 77 dom N t 38 HARDWARE DESCRIPTION Signal Name FPGA UDIMM DIMM_RASN U34 G19 J29 192 1 4 9 UDIMM Trace Lengths The UDIMM traces length matched and routed to the following lengths refer to Table 9 Table 9 UDIMM PCB Trace Lengths Signal Name Routed Length Description mm DIMM_CKON 128 14 Clock group DIMM_AO 128 38 Control group DIMM DQO 128 18 Data byte group 1 5 EEPROM The AT24C256C U23 provides 262 144 bits of serial electrically erasable and programmable read only memory EEPROM organized as 32 768 words of eight bits each device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential 1 5 4 EEPROM Circuit Diagram Figure 9 shows the implementation of the EEPROM memory circuit 47 1 8391 4 7 PROM 5 AT24C64C SO8 2 2uF AT24C64CN SH B 6 3V Figure 9 FPGA EEPROM Device address 2 A1 and 0 is set up by discrete resistors and is mapped to 1010000x where x is the R W bit The eighth bit of the device address is the read write operation select bit A read operation is initiated if this bit is HIGH and a write operation is initiated if this bit is LOW 1 5 2 Connections between FPGA and the EEPROM The connections between the FPGA and the EEPROM ate sh
23. Daughter Card Daughter Card Receptacle Plug Signal Name TOP BOTTOM DCA P4 CC P1 A11 P2 A11 34 BB12 DCA P5 P1 A13 P2 A13 34 AP21 DCA P6 P1 A15 P2 A15 34 AY18 DCA P7 P1 A17 P2 A17 34 BD11 DCA P8 GCC BUS 34 BB16 DCA_BO_P9 P1 H3 34 AP20 DCA B1 NO P1 D4 34 AW14 DCA B1 P1 D6 AM20 DCA B1 N10 VREF P1 J6 34 AN17 DCA_B1_N11_VREF P1 J8 34 AV13 DCA_B1_N12 P1 J10 34 AK21 DCA_B1_N13_CC P1 J12 34 AJ19 DCA_B1_N14 1 14 34 17 DCA_B1_N15 P1 J16 34 AY13 DCA_B1_N16 P1 J18 34 AN19 DCA_B1_N17 1 20 34 BA15 DCA_B1_N18_CC P1 D22 34 AT15 DCA_B1_N2 P1 D8 34 BA13 DCA_B1_N3 P1 D10 34 AP15 DCA_B1_N4_CC P1 D12 34 AV14 DCA B1 N5 P1 D14 34 16 DCA B1 N6 P1 D16 34 AK18 DCA B1 N7 P1 D18 34 17 DCA_B1_N8_CC P1 D20 34 AT13 DCA B1 N9 1 4 34 21 DCA B1 P1 C3 34 AW15 DCA B1 P1 P1 C5 34 AL20 DCA_B1_P10 P1 K5 34 AN18 DCA_B1_P11 P1 K7 34 AU14 DCA_B1_P12 1 9 34 21 kes c cca CICI J Bow e gt rg 2 oo Ci 9 i 52 alie rg sl G ci DNMEG V6HXT User Manual www dinigroup com 111 HARDWARE DESCRIPTION Daughter Daughter Card Receptacle Plug Signal Name TOP BOTTOM P1 K11 P2 K11 DCA B1 14 P1 K13 P2 K13 DCA _ B1_P15 P1 K15 P2 K15 DCA_B1_P16 P1 K17 P2 K17 DCA 1 19 2 19 DCA B1 P18 CC P1 C21 P2 C21 DCA
24. This chapter desribes the banbvare features of the DNMEG_V6HXT Loge Emulation 1 Description 1 1 Overview The DNMEG_V6HXT is a complete logic prototyping system that enables ASIC or IP designers a vehicle to prototype logic and memory designs for a fraction of the cost of existing solutions A high level block diagram of the DNMEG V6HXT Logic Emulation Board is shown in Figure 3 followed by a brief description of each section DNMEG V6HXT User Manual www dinigroup com 21 HARDWARE DESCRIPTION 4x 10 GbE or 1x 40 GbE 10 GbE CPLD SFP Control Signals 72 bit Data DDR3 UDIMM 16 GB Max 150 to 6 GbE Virtex 6 HXT 10 100 1000 GbE FPGA HT380T 565T FF 1923 100 40 Cray Sun Intel HP et FPGA Contig USB 2 0 PCIe Slot 8 lane 8 7 2 Z CLK_CFP 5 DNMEG_V6HXT CLK_SFP LS Block Diagram v1 03 SPI Flash 515338 Figure 3 DNMEG_V6HXT Logic Emulation Board Block Diagram The DNMEG V6HXT is a complete network interface solution featuring high speed serial IOs The DNMEG_V6HXT can be used stand alone without hosting contact factory for chassis options if required hosted by 8 lane PCIe cable GEN1 GEN2 plugged into ASIC Prototyping boards from the DINI product line as an expansion peripheral FPGA configuration and other miscellaneous bo
25. 20 Mi ED en Vcco gt 2 70 lt 1000 70 1 Source sA a HH Load 2xZQ 5 1000 77 58 061600 e Differential signals should be terminated with the memory device s internal termination or a 100Q differential termination at the load For bidirectional signals termination is needed at both ends of the signal DCI ODT or external termination ZQ Source_P Load P lt 2xZQ 1000 Load_N 103426 20 251620 termination must be placed as close to the load as possible The termination can be placed before or after the load provided that the termination is placed within a small distance of the load pin The allowable distance can be determined by simulation DCI can be used at the FPGA as long as the DCI rules such as VRN VRP followed e The RESET and CKE signals are not terminated These signals should be pulled down during memory initialization with a 4 7 resistor connected to GND e ODT which terminates a signal at the memory and DCI which terminates signal at the FPGA are required The MIG tool should be used to specify the configuration of the memory system for setting the mode register properly Refer to Micron technical note TN 47 01 for additional details on ODT ODT applies to the DQ DOS and DM signals only If ODT is used the mode register must be set appropriately to enable ODT at the memory DNMEG V6HXT User Manual
26. 34 4 34 13 34 8 34 AU5 34 AU1 34 AH13 34 AV2 34 13 34 AM12 34 AR8 34 10 34 5 34 AW4 34 AV4 34 AR7 34 AK11 34 AK13 34 AN11 34 AT3 34 AR5 34 14 ee ail DCA Bi Pi DNMEG_V6HXT User Manual www dinigroup com 114 HARDWARE DESCRIPTION Daughter Daughter Card Receptacle Plug Signal Name TOP BOTTOM DCA B4 NO P1 F7 P2 F7 34 BA3 34 BB4 DCA B4 N2 P1 F11 P2 F11 34 BD4 DCA B4 N3 P1 F13 P2 F13 34 BB11 DCA B4 N4 P1 F15 P2 F15 34 1 34 7 34 10 DNMEG_V6HXT User Manual www dinigroup com 115 HARDWARE DESCRIPTION Daughter Card Daughter Card Receptacle Signal Name TOP D P P P P E13 U34 BA12 E15 U34 BB2 E19 U34 BC6 E21 U34 BC8 E23 U34 BA5 DCA_B4_P9 P1 A21 2 21 034 12 2 2 2 2 17 U34 BB7 2 2 2 8 6 Insertion Removal of Daughter Due to the high density MEG Array connectors the pins on the plug and receptacle of the MEG Array connectors are very delicate When plugging in a daughter card make sure to align the daughter card first before pressing on the connector Be absolutely certain that both the small and the large keys at the narrow ends of the MEG Array headers line up BEFORE applying pressure to mate the connectors Place it down flat then press down gently DNMEG V6HXT User Manual www dinigr
27. PAD 1K lt PTHOBT230W DIP10 Silkscreen VOLT ADJ PTHOBT230WAZ JPA P1 5V DIMM oi P1 8V DIMM P25V DIMO 2 1 TSM 103 01 T DV R214 R221 5 R219 R218 9 09 3 24 lt 31 6K 10K DIMM VOADJ 4 7 itchi sr Figure 7 UDIMM Switching Power Supply 1 5V 1 4 5 VTT Linear Power Supply 0 75V The Texas Instruments TPS51200 is a sink source double data rate DDR termination regulator for termination of DDR3 UDIMMs see Figure 8 42 15 P P2 5VD B POTE VIT SND m ppm woke 5 ly PO 75V_VIT 2 5 606 oR C266 C267 C992 T 2 2uF 47uF L 330uF R169 47K VIT REFIN 1 6 P_VREF_DIMM 6 6 3V 6 3V 1 REFIN _ REFOUT oo 20 20 20 R168 4 7 VIT EN P VREF F TANT C274 R170 C271 C270 C265 4 7K 2 2uF 2 2uF oa 2 2uF 6 3V 6 3V 6 3V cod See _ s 3v 20 20 20 9 20 F FOER PARPAD x CER 551200750 10 TPS51200DRCT Figure 8 VIT Linear Power Supply 0 75V 1 4 6 Serial Presence Detect EEPROM Operation DDR3 SDRAM modules incorporate serial presence detect The SPD data is stored in a 256 byte EEPROM The first 128 bytes are programmed by Micron to comply with JEDEC Standard JC 45 Appendix X Serial Presence Detect SPD for DDR3 SDRAM Modules These bytes identify m
28. The AP2171 is an integrated high side power switch optimized for Universal Serial Bus USB and other hot swap applications The device complies with USB 2 0 and offer current and thermal limiting including short circuit protection as well as controlled rise time and under voltage lockout functionality A 7ms deglitch capability on the open drain Flag output prevents false over current reporting and will turn on LED DS27 during an over current condition see Table 36 Table 36 USB Fault LED Signal Name Source Pin LED USBO OCn U56 5 USB OC DS27 5 5 Miscellaneous LEDs Table 37 describes the miscellaneous status LEDs and their associated soutce DNMEG V6HXT User Manual www dinigroup com 91 HARDWARE DESCRIPTION Table 37 Miscellaneous LEDs Signal Name Source LED CPU LEDs U26 MCU_RSTOUTn 26 11 RST OUT 0511 MCU_HRTBEAT 26 65 HRT BT DS7 USB_UP_LED 026 25 USB UP 059 MGT Clock Generator LOL Indicator MGT_INTR U47 8 LOL DS14 SFP LOS SFP_LS1_RXLOS SFP_LS2_RXLOS SFP_LS3_RXLOS SFP_LS4_RXLOS SFP_LS5_RXLOS SFP_LS6_RXLOS SFP_LS7_RXLOS SFP_LS8_RXLOS SFP_HS1_RxLOS SEP HS2 RxLOS HS3 RxLOS SEP HS4 RxLOS Front Panel PWR LED PWR OK 3 8 ATX PWR 0528 53 78 SFP LOS 0515 53 64 SFP LOS 0516 53 59 SFP LOS DS17 53 59 SFP LOS 0518 53 111 SFP LOS DS19 53 117 SFP LOS DS20 53 100 SFP LOS DS21 53 97 SFP LOS 0522 53 5 SFP
29. The oscillator is powered from a 2 5 and provides a reference clock to the GTX Transceiver on the FPGA see Figure 21 The oscillator power supply 028 is filtered to reduce power supply noise and jitter The SATA II Clock Oscillator is assigned as follows SATA II X2 150MHz P N LV7745DW 150 0M The Pletronics LV77D Series 2 5V Clock Oscillators are recommended for this application and is available in frequencies from 1MHz to 325MHz from Nu Horizons 3 4 1 SATA II Clock Oscillator The differential oscillator X2 outputs are AC coupled to the GTX Transceiver on the FPGA see Figure 21 P2 8VA SATA P2 8VA SATA R458 S R468 R462 4 7K lt 47K 4 7K _ CLK_SATA 919 5 51 lt lt FS1 CLK 1 5 919 OSC SATA 50 lt lt FSO NC c o R463 IK OSC OSC SATA NC P2 5VA 5 SATA 8 9 P2 5VF_OSC SATA 1 Hs GND VDD CE E SI534 SMT 8 2 2uF BLMIBAGI02SN1D LV7745DW 150 0M 63v 400mA 20 CER Note Frequency 150MHz Figure 21 SATA II Clock Oscillator 3 4 2 Connection between SATA II Clock Oscillator and the FPGA The connections between the SATA II Clock Oscillator and the FPGA ate shown in Table 20 These signals are routed as differential pairs LVDS and ate AC coupled Table 20 Connection between SATA II Clock Oscillator
30. uREFCLK Downstream Device Clock from remote REFCLK on cable Downstream Device Clock from local PCI Express Clock Buffer U24 Upstream Subsystem Cable Downstream Subsystem 3 3 Vmain CREFCLKp CREFCLKn dREFCLK gt Connector Connector 4 7 2 Cable Present Power Good signaling is accomplished with the following signals PCIE_CPERSTn PCIE_CPWRON for signaling the status of the Upstream Subsystem and PCIE_CPRSNTn as described within this section PCIE_CPRSNTn assertion by the DNMEG V6HXT User Manual www dinigroup com 87 HARDWARE DESCRIPTION Downstream Subsystem is qualified by the power good condition of the Downstream Subsystem as illustrated in Figure 30 This provides a mechanism for the Upstream Subsystem to determine whether the power is good within the Downstream Subsystem enable the reference clock and initiate Link Training Upstream Subsystem Cable Downstream Subsystem 3 3 Vmain 3 3 Vmain CPRSNT 5 lt uPRSNT dPWRGD E SB RTN Connector Connector Figure 30 CPRSNTZ Signaling with Power Isolation Opto couplers U8 U9 provide power isolation between the Upstream and the Downstream system Note PCIEx_FPGA_CPERSTn PCIEx_FPGA_CPWRON is an active LOW signal in Slave Upstream mode and an active HIGH signal when in From Host Downstream mode Refer to par 3 3 PCI Express Cable Re
31. 10 10 20 CER CER CER CER CER Nr siti as Figure 18 GTX GTH Clock Circuit 3 2 2 Input Connections to the Clock Generator Input connections to the Clock Generator are shown in Table 17 The Clock Generator 515338 provides support for an external clock input via 05 136 pins The SMA J27 J28 inputs AC coupled and terminated for a 1000 differential input Table 17 Input connections to the Clock Generator Signal Name Input Clock Generator SMA CLK EXT J27 U47 5 CLK EXT J28 U47 6 I2C MGT_SCL U34 AT33 U47 12 MGT_SDA U34 AT34 U47 19 3 2 3 Output Connections between the Clock Buffers and the FPGA All of the clock networks on the DNMEG V6HXT are routed point to point using dedicated differential LVPECL traces The arrival times of the clock edges at each FPGA are phase aligned length matched on the PCB within about 100ps These clocks are all suitable for synchronous communication The connections between the FPGA and the Clock Buffers are shown in Table 18 Table 18 Connections between the Clock Buffers and the FPGA DNMEG_V6HXT User Manual www dinigroup com 50 HARDWARE DESCRIPTION Signal Name Clock Buffer FPGA CFP Clocks CML MGT106P CLK MGT106N MGT107P CLK_CFP_MGT107N CLK_CFP_MGT108P CLK_CFP_
32. 25 128 CPC ee Gy Grebe a PER ER DNMEG_V6HXT User Manual www dinigroup com 65 HARDWARE DESCRIPTION Signal Name CFP Connector FPGA CFP_TX5N J25 129 34 K44 _ 5 25 94 34 L37 _ 5 J25 95 34 L38 CFP TX6P J25 131 34 G41 TX6N J25 132 34 G42 RX6P J25 97 34 H39 CFP_RX6N J25 98 34 H40 CFP_TX7P J25 134 34 H43 CFP_TX7N J25 135 34 H44 CFP_RX7P J25 100 34 37 CFP_RX7N 25 101 34 38 TX8P J25 137 34 T43 CFP TX8N J25 138 34 T44 CFP_RX8P J25 103 34 U41 CFP_RX8N J25 104 34 U42 J25 140 34 P43 CFP TX9N J25 141 34 P44 CFP_RX9P J25 106 34 T39 CFP RX9N J25 107 34 T40 CFP PRTADRO J25 46 34 AL30 PRTADR1 J25 45 34 BC32 CFP_PRTADR2 J25 44 34 BB32 CFP_PRTADR3 J25 43 34 BA32 CFP_PRTADR4 J25 42 34 AY32 CFP_RX_LOS J25 40 34 AM31 CFP_TX_DIS J25 36 34 BA30 CFP_GLB_ALRMN 25 41 34 AM32 CFP_MOD_ABS J25 38 34 AU31 CFP MOD LOPWR J25 37 34 BB30 CFP MOD RSTN J25 39 34 AV31 CFP_PRG_ALRM1 J25 33 34 AY31 CFP_PRG_ALRM2 J25 34 34 AJ29 Cyl Gwe GE EG Ere ea EDGE e Grea ea aera DNMEG_V6HXT User Manual www dinigroup com 66 HARDWARE DESCRIPTION Signa
33. 33 33 38 INC 51 RX MCLKn CEP STAX MEIR Pee Mi 929 LOS 33 lt lt ALRMn 33 41 RX LOS e N C 51 MCLKp GLB ALRMn 33 lt lt FP PRTADR4 12 42 GLB ALam GND RX9n pg29 PRTADR4 12 X amp CFP PHTADR3 12 43 PRTADR4 x RX9n CFP HXop 29 PRTADR3 12 amp amp cFP PRTADR2 12 44 PRTADRS e RX9p pg29 PRTADR2 12 lt lt 12 45 PRTADR2 GND pg29 PRTADR 12 lt 12 46 PRTADR1 51 RX3n 929 PRTADRO 12 lt 12 47 PRTADRO RX8p S1_RX3p CFP_MDC_12 MDIO GND 28 RX7n S1 RX2n T 36 GND x RX p S1 RX2p 2 VND_IO F GND 51 _ 25 M RX6n 51 1 54 GND RX6p S1_RXIp X 54 VND_IO_H 4 GND RXn gt VND IO J RX5n S1_RXIn RYD 55 3 3V_GND n RX5p 51 RXOp 3 3V_GND GND S 3 3V_GND 5 29 3 3V GND 3 3V_GND GND Pull up Resistors 50 33V RX3n P1 2VD 62 93V 9 6 23V GND RXen R490 64 3 3 nes 2 R483 51327 mep R479 66 3 3 GND CFP_RXin R480 67 3 3 Bon RXip R475 z E 68 3 3 RXip 69 3 3 GND CFP_RXon 70 3 3V 7171 3
34. 3V_GND RXOp 72 SV GND GND RXMCLKn R584 NI R575 47K GLB ALRMn 33 73 123 ND RXMCLKp R585 NI 8574 4 7K ABS 33 74 93V GND 3 3V_GND GND CAGE CAGE CAGE CAGE CAGE CFP CAGE CAGE CAGE CAGE CAGE CAGE CAGE CAGE CAGE CAGE CAGE Loc Loc DNMEG_V6HXT User Manual CONN 2057630 1 www dinigroup com 64 HARDWARE DESCRIPTION 4 1 2 Connection between CFP Connector and the FPGA Table 24 shows the connection between the CFP connector and the FPGA Table 24 Connection between the CFP Connector and the FPGA Signal Name CFP Connector CLK_CFP_REFCLKP J25 146 CLK_CFP_REFCLKN J25 147 CLK_CFP_MGT106P U34 R41 CLK_CFP_MGT106N U34 R42 CLK_CFP_MGT107P U34 J41 U U 41 15 41 14 41 7 41 6 41 10 41 9 41 12 41 11 34 F43 34 F44 34 G37 34 G38 34 D43 34 D44 34 F39 34 F40 34 A41 34 A42 34 B39 34 B40 34 C41 34 C42 34 D39 34 D40 34 141 34 142 34 K39 34 K40 34 K43 CLK_CFP_MGT107N 34 J42 CLK_CFP_MGT108P 34 41 MGT108N U34 F42 125 113 CFP_TXON J25 114 25 79 CFP_RXON J25 80 CFP_TX1P 125 116 CFP_TX1N J25 117 CFP_RX1P 25 82 CFP RXIN 25 83 _ 2 25 119 CFP_TX2N 25 120 _ 2 25 85 CFP_RX2N 25 86 _ 25 122 CFP_TX3N 25 123 CFP_RX3P 25 88 CFP_RX3N 25 89 CFP TX4P 25 125 CFP_TX4N 125 126 CFP_RX4P 25 91 CFP_RX4N 25 92 _ 5
35. AND ENTER Serial 1 29 1 29Rows 78 Cols VT100 CAP NUM DNMEG V6HXT User Manual www dinigroup com 14 GETTING STARTED The remainder of the reference design functional tests requires various loop back test boatds modules to make them PASS and is not covered in this User Manual Please reference the Customer Support Package on USB Flash Drive for code examples The next section describes configuring and programming the hardware in detail DNMEG_V6HXT User Manual www dinigroup com 15 PROGRAMMING CONFIGURING THE HARDWARE Programming Configuring the Hardware This chapter details the programming and configuration instructions for the DNMEG_V6HXT Loge Emulation Board 1 Introduction This section of the User Manual presents different methods to configure the Xilinx Virtex 6 FPGA e Configuring the FPGA using USB Flash Drive configure the FPGA with a bitfile stored on the USB Flash Drive e Configuring the FPGA using JTAG using the Xilinx Platform Cable USB and JTAG Virtex 6 FPGAs are configured by loading application specific configuration data the bitstream into internal memory Because the Xilinx FPGA configuration memory is volatile it must be configured each time it is powered up The bitstream is loaded into the device through special configuration pins These configuration pins serve as the interface for a number of different configuration modes The following configuration modes
36. B1 P2 P1 C7 P2 C7 1 9 2 9 DCA B1 P4 CC P1 C11 P2 C11 1 13 P2 C13 DCA_B1_P6 P1 C15 P2 C15 DCA_B1_P7 P1 C17 P2 C17 DCA_B1_P8_CC P1 C19 P2 C19 P9 P1 K3 P2 K3 2 0 1 24 P2 B24 DCA_B2_N1 P1 B26 P2 B26 DCA_B2_N10 P1 G26 P2 G26 DCA B2 N11 P1 G28 P2 G28 DCA_B2_N12_CC P1 G30 P2 G30 DCA_B2_N13 P1 G32 P2 G32 DCA_B2_N14 P1 G34 P2 G34 DCA_B2_N15 P1 G36 P2 G36 DCA_B2_N16 P1 G38 P2 G38 DCA_B2_N17 P1 G40 P2 G40 DCA_B2_N18_CC P1 G22 P2 G22 DCA_B2_N2 P1 B28 P2 B28 DCA_B2_N3_CC P1 B30 P2 B30 DCA_B2_N4_VREF P1 B32 P2 B32 DCA_B2_N5_VREF P1 B34 P2 B34 DCA_B2_N6 P1 B36 P2 B36 34 AJ20 34 AP18 34 AW13 34 15 34 AR15 34 BA14 34 AN16 34 AU15 34 AP16 34 AJ18 34 18 34 14 34 AM21 34 AK16 34 AR11 34 15 34 AN14 34 AR12 34 AM16 34 AU12 34 AM14 34 AY8 34 AY6 34 AW6 34 AW11 34 AU10 34 AV8 34 AW10 34 AV6 Q T z ee U U ege ee 5 DNMEG_V6HXT User Manual www dinigroup com 112 HARDWARE DESCRIPTION Daughter Daughter Card Receptacle Plug Signal Name TOP BOTTOM DCA_B2_N7 DCA_B2_N8_CC DCA_B2_N9 DCA B2 PO DCA B2 DCA B2 10 DCA B2 P11 DCA B2 P12 CC DCA B2 14 DCA B2 P15 DCA B2 P16 B2 P17 DCA B2 P18 CC DCA B2 P2 DCA B2 P3 CC DCA B2 P4 DCA B2 P5 DCA B2 P6 DCA B2 P7 DCA B2 P8 CC DCA B2 P9 DCA B3 NO 34 12 DCA_B3_
37. FPGA Table 4 SeleccMAP Bus between Microcontroller and FPGA Signal Name FPGA FPGA_DO 34 BB35 FPGA_D1 34 BA35 FPGA_D2 34 AM35 FPGA_D3 34 AL34 FPGA_D4 34 AV34 FPGA_D5 34 AU34 FPGA_D6 34 AK33 FPGA_D7 34 AJ33 FPGA_CCLK 34 AC33 FPGA_PROGN 34 U33 FPGA_BUSY 34 AE33 FPGA RD WRN 34 W33 FPGA INITN 34 T14 34 A A33 FPGA DONE 34 T13 MO 34 V32 M1 34 132 FPGA M2 34 T33 CG G ae pa rea C HEU E DNMEG_V6HXT User Manual www dinigroup com 29 HARDWARE DESCRIPTION 1 3 3 JTAG Virtex 6 devices support IEEE standards 1149 1 and 1532 IEEE 1532 is a standard for In System Configuration ISC based on the IEEE 1149 1 standard JTAG is acronym for the Joint Test Action Group the technical subcommittee initially responsible for developing the standard This standard provides a means to ensure the board level integrity of individual components and the interconnections between them The IEEE 1149 1 Test Access Port and Boundary Scan Architecture is commonly referred to as JTAG JTAG connector J30 is used to download the configuration files to the FPGA see Figure 5 r JTAG FPGA Figure 5 FPGA JTAG Interface Table 5 shows the connection between the JTAG heade
38. FPGA Status LEDs Signal Name FPGA LED FPGA_LEDO U34 BD34 LEDO DS4 FPGA_LED1 U34 BD35 LED1 053 FPGA_LED2 U34 BA33 LED2 DS2 FPGA_LED3 U34 BA34 LED3 051 5 2 Configuration DONE LEDs After the FPGA have received all the configuration data successfully it releases the DONE pin which is pulled high by a pull up resistor A low to high transition on the DONE indicates configuration is complete and initialization of the device can begin DONE pin drives an N MOSFET and turns ON a blue LED when the DONE pin DNMEG_V6HXT User Manual www dinigroup com 90 HARDWARE DESCRIPTION goes high Table 34 describes the DONE LED and its associated pin assignment on the FPGA Table 34 FPGA DONE LED Signal Name FPGA LED FPGA_DONE U34 T13 DS5 5 3 Platform Manager Status LEDs Numerous LEDs Green are provided to the user as a design aid during debugging The LEDs can be turned ON by driving the corresponding pin HIGH Table 33 describes the Status LEDs and their associated pin assignments on the Platform Manager Table 35 CPLD Status LEDs Signal Name PLTFRM MNGR LED CPLD LEDO U33 R12 LEDO 056 CPLD U33 P10 LED1 058 CPLD LED2 U33 T13 LED2 DS10 U U CPLD LED3 33 P11 LED3 0512 CPLD LED RST 33 T14 RST SYS 0513 Note LEDJ3 0 is intended to indicate PSU failed and also provides heart beat LED for the Power Monitor 5 4 USB Fault LED
39. HXT LL product To minimize data synchronization across clock boundaries important for networking applications it probably makes sense to clock this DDR3 interface at a 3x multiple of the base Ethernet frequency of 156 25 MHz which is 468 75 MHz A 3x phase synchronous clock can be easily generated internal to the FPGA allowing zero latency synchronous data transfers between the Ethernet packet receiving logic and the DDR3 memory controller The DDR3 controller can be optimized in any way you choose Dini Group provide several Verilog examples at no charge All functions of the DDR3 DRAM can be exploited and optimized Up to 8 banks can be open at once Timing variables such as CAS latency and precharge can be tailored to the minimum given your operating frequency and the timing specification of the exact DDR3 memory utilized Alternate UDIMM memories are in development including an RLDRAM and a QDRII option Daughter cards for customization and expansion MEG Array and FMC MEG Array Two 400 pin FCI MEG Array connectors are attached to a single interface on the FPGA One MEG Array connector is on the top and one the bottom The signals are shared The bottom connector is used when this card is designated as a peripheral to our ASIC prototyping product The top connector is used when this card is used stand alone and application of one of our many daughter cards is useful This is a non proprietary industry standard connector
40. PCIE2 RECLKP J5 A14 Schematic Multiple Sources see PCIE2 RECLKN 5 15 Schematic PCIE2 PETPO J5 A2 U34 AJ42 PCIE2 PETNO 5 U34 AJ41 PCIE2_PERPO J5 B2 U34 AH40 PCIE2 PERNO J5 B3 U34 AH39 PCIE2_PETP1 J5 A5 U34 AH44 PCIE2_PETN1 J5 A6 U34 AH43 PCIE2_PERP1 J5 B5 U34 AG38 PCIE2_PERN1 J5 B6 U34 AG37 PCIE2 PETP2 5 A8 U34 AG42 PCIE2 PETN2 5 9 U34 AG41 PCIE2_PERP2 J5 B8 U34 AF40 PCIE2 PERN2 J5 B9 U34 AF39 PCIE2_PETP3 J5 A11 U34 AF44 DNMEG_V6HXT User Manual www dinigroup com 89 HARDWARE DESCRIPTION Signal Name PCI Express Cable FPGA PCIE2 PEIN3 J5 A12 34 AF43 PCIE2 J5 B11 34 AE38 PCIE2 PERN3 J5 B12 34 AE37 PCIE2 CPERSTN 09 6 52 5 34 F15 PCIE2_FPGA_CPWRON U9 7 S2 6 34 G15 PCIE2 CPRSNT 08 1 52 1 34 16 PCIE2_FPGA_CWAKE 08 3 52 2 34 816 5 LED Indicators The DNMEG_V6HXT Logic Emulation board provides various LED s to indicate that status of the board The LEDs are turned ON by driving the GATE of the N MOSFET see Figure 31 P2 5VD 9 024 R70 49 98 LEDF AO 054 AA GRN 3 33 2 GERENS If nom 9mA BSS138 FPGA LEDO Figure 31 LED Indicator 5 1 FPGA Status LEDs Numerous LEDs Green ate provided to the user as a design aid during debugging The LEDs can be turned ON by driving the corresponding pin HIGH Table 33 describes the Status LEDs and their associated pin assignments on the FPGA Table 33
41. available to the user and only the relevant subsections will be addressed 2 1 USB Interface The LPC1754 includes a USB 2 0 full speed device Host OTG controller with dedicated DMA controller and on chip PHY for device Host and OTG functions The USB port J42 is configured as a Host used for configuration with a USB Flash Drive The USB signals are routed as differential traces and connect to the LPC1754 via a common mode filter T1 see Table 13 Table 13 USB Interconnect The NUP2201MR6 D7 transient voltage suppressor is designed to protect the high speed data lines from ESD The AP2161 056 is an integrated high side power switch optimized for Universal Serial Bus USB and other hot swap applications DNMEG_V6HXT User Manual www dinigroup com 42 HARDWARE DESCRIPTION 5 0 5 0 8722 e 4 7K P5 0V_VBUS 056 4 2 7 P5 0V VBUS T C409 C408 R225 0 1uF 10uF 4 8 16V 6 3V T EN 10 2095 C410 4 7K 1 5 CER CER GND FLG 1 P5 0V_ATX 2161 5 0527 9 216150 13 USB OCn R723 475R LED RED Silkscreen USB FAULT J42 n M P5 0V VBUS 1 USB D n 3 2 USB DT n 8226 USB DH n 2 EUS USB 4154941 USB DT p 8227 USB DH p 4 GND 2012 900 2 5 D7 724 S R725 1
42. dipswitch 3 1 e To set PCIE Cable Connection Port 0 3 to Downstream mode turn OFF all switches on dipswitch 51 Turn ON dipswitch 53 1 e To set PCIE Cable Connection Port 4 7 to Upstream Mode turn ON all switches dipswitch 52 Turn OFF dipswitch 53 2 e To set PCIE Cable Connection Port 4 7 to Downstream mode turn OFF all switches on dipswitch 52 Turn ON dipswitch S3 2 Note PCIEx CPRSNT PCIEx_FPGA_CPWRON is an active LOW signal in To Slave Upstream mode and an active HIGH signal when in From Host Downstream mode It is also possible to permanently enable CPRSNT cable present detection when running in downstream mode by stuffing R330 Port 0 3 or R329 Port 4 7 with 00 resistor 3 3 2 Connection between the PCI Express Jitter Attenuator and the FPGA The connection between the PCI Express Jitter Attenuator 015 016 and the GTX Transceiver on the FPGA are shown in Table 19 These signals are routed as differential pairs LVDS and are AC coupled Table 19 Connection between the PCI Express Jitter Attenuator and the FPGA Signal Name FPGA DNMEG_V6HXT User Manual www dinigroup com 53 HARDWARE DESCRIPTION Connector CLK_OSC_PCIE1_GTPp U15 3 U34 AB35 OSC PCIE1 GTPn U15 4 U43 AB36 CLK_OSC_PCIE2_GTPp U16 3 U34 AF35 CLK_OSC_PCIE2_GTPn U16 4 U43 AF36 3 4 SATA II Clock Oscillator LVDS A dedicated LVDS oscillator is provided for the SATA II interface
43. example to put a slave Subsystem into the 53 power management state DNMEG V6HXT User Manual www dinigroup com 86 HARDWARE DESCRIPTION 4 7 1 SB_RTN required The SideBand Return provides a return current path for all single ended sideband signals allowing for power domain isolation between Subsystems CWAKEn required Cable Wake active low signal that is driven by a Downstream Subsystem to re activate the PCI Express hierarchy s main power rails and reference clocks Although optional for Upstream and Downstream Subsystems all cable assemblies shall include CWAKEn It is required on any Subsystem that supports wakeup functionality compliant with the specification 3 3 POWER optional for connector Power provisioning to the connector backshell is provided to allow for active signal conditioning components within the cable assembly A wire shall not be provided within the cable PWR_RIN optional for connector Return path optional for 3 3 V power provisioning Cable Reference Clocking Options To control jitter radiated emissions and crosstalk and allow for future silicon fabrication process changes a low voltage swing current mode differential clock is specified Isolated power domains between the two Subsystems maintained through implementation of AC coupling capacitors at the source Supplying the cable reference clock is required from an Upstream Subsystem AIPRSNTS 4 5 CPRSNT a G
44. ground test equipment DNMEG V6HXT User Manual www dinigroup com 119 HARDWARE DESCRIPTION Note Avoid shorting of any power rails or signals to the bus bars they can conduct a lot of current Mounting holes are provided to allow the PCB to be mounted in a case or chassis 9 2 Standard Daughter Card Size The DNMEG_V6HXT Logic Emulation Board provides mounting hole locations for a Daughter Card with the dimensions given below The DNMEG Obs Daughter Card product conforms to these dimensions View Top Side 400 Pin Receptacle on Back P N 74390 101 5 000 4 250 0 750 lt 1 950 gt 9 3 Daughter Card Spacing With this host plate daughter card arrangement there is a limited Z dimension clearance for backside components on the daughter card This dimension is determined by the daughter card designer s part selection for receptacle DNMEG_V6HXT User Manual www dinigroup com 120 HARDWARE DESCRIPTION GND DAUGHTER CARD 14mm Note that the components on the topside of the daughter card and DNMEG_V6HXT face in opposite directions DNMEG V6HXT User Manual www dinigroup com 121 APPENDIX Appendix 10 Appendix A UCF File See the Customer Support Package USB Flash Drive for the Xilinx User Constraint Files UCF for FPGA 11 Ordering Information Request quotes by emailing sales dinigroup co
45. precharge can be tailored to the minimum given your operating frequency and the timing specification of the exact DDR3 memory utilized Alternate UDIMM memories are in development including an RLDRAM and a QDRII option Daughter cards for customization and expansion MEG Array and FMC MEG Array Two 400 pin FCI MEG Array connectors are attached to a single interface on the FPGA One MEG Array connector is the top and one the bottom The signals are shared The bottom connector is used when this card 15 designated as a peripheral to our ASIC prototyping product The top connector is used when this card is used stand alone and application of one of our many DNMEG daughter cards is useful This is a non proprietary industry standard connector and the mating connector is readily available Dini Group can provide the mating connector at cost custom User daughter catds The 192 signals 96 pairs to from each of these MEG Array expansion connectots are routed differentially and can run at the limit of the Virtex 6 108 710 MHz Clocks resets and presence detection along with abundant fused power are included in each connector FMC Vita 57 FPGA Mezzanine Card or FMC as defined in VITA 57 provides a specification describing an IO mezzanine module with connection to an FPGA or other device with reconfigurable IO capability Most vendors of FMC daughter cards tend to ignore the specification making this interface standard a q
46. single ended input buffer in the will not work An example Verilog implementation of a differential clock input is given below IBUFDS DIFF TERM TRUE sys ibufgds inst I CLK_SYS_BUF2P SYS BUF2N O clk sys ibufgds The pin assignment in the file DNMEG V6HXT User Manual www dinigroup com 46 HARDWARE DESCRIPTION NET CLK_SYS_BUF2P loc AN33 CLK SYS BUF2N loc AP34 Due to limited resources no clock test points ate provided to the user DNMEG_V6HXT User Manual www dinigroup com 47 HARDWARE DESCRIPTION EXT CLOCK 25MHz PCIE Cable Conn 1 PCIE Cable Conn 2 GIX GTH Transceiver Clocks o CFP GTH118 QSFP1 MGTREFCLKP N_118 u CFP Connector GTH108 MGTREFCLKP N 108 SEE s MGTREFCLKP N 107 ae L 4 MGTREFOLKP N 106 SERES SFP HS ALT SFP LS1 4 PCIE1_RECLKp_c SFP LS4 8 ft ALT PCIE2 RECLKp c 8 8 8 5 CLK1 GBT M2C P N 5 CLKO_GBT_M2C_PIN 8 Figure 17 Clocking Block Diagram www dinigroup com DNMEG_V6HXT User Manual 117 QSFP2 MGTREFCLKP N_117 48 HARDWARE DESCRIPTION SFP HS High Speed SFP LS Low Speed e PCI Express Cable Clock 100MHz System Clock o PCI Expre
47. www dinigroup com 32 HARDWARE DESCRIPTION 1 4 3 Design Guidelines DDR3 IO Standards These rules apply to the I O standard selection for DDR3 SDRAMs e Designs generated by the MIG tool use the SSTL15 T DCI and DIFF SSTL15 T DCI standards for all bidirectional I O DQ DQS e The SSTL15 and DIFF_SSTL15 standards are used for unidirectional outputs such as control address and forward memory clocks The MIG tool creates the using the appropriate standard based on input from the GUI 1 4 4 UDIMM Switching Power Supply 1 5V The Texas Instruments PITHO8T230WAZ DC DC Converter is used to create the supply for the DDR3 UDIMM set to 1 5V 6A see Figute 7 TP45 P12V 8179 1008 1 zii P_DIMM 1 2518 pon 1 j 12VFUSEp DIMM p PONT VIN vout H 4 P Dimm C313 7 C1030 C1031 C352 C351 TRANS C319 C312 1009 C1008 47uF 150uF L 150uF 47uF OduF P DIMM TRACK 9 5 P DIMM SNSp 22uF L47uF L 330uF L 330uF L 330uF 16V T 16V 16V 16V 16V TRACK SENSE P DIMM SNSn 6 3V 6 3V 6 3V 6 3V 6 3V 20 20 20 20 10 ggg 257 20 20 20 20 20 CER TANT TANT CER TANT TANT TANT 8 1 7 8 5 SMARTSYNC PSU_SEQ_EN2n RUN P DIMMn 1 2 8 R613 OR aio
48. 0 DN P1 A3 P2 A3 34 BC13 DCA NO DN P1 B4 P2 B4 34 BC12 DCA P13 P1 H11 P2 H11 34 AT17 DCA_BO_N13_CC P1 G12 P2 G12 34 AU16 DCA_BO_P4_CC P1 A11 P2 A11 34 BB12 CC P1 B12 P2 B12 34 BC11 DCA P8 BUS P1 E5 P2 E5 34 BB16 DCA N8 GCC BUS P1 F5 P2 F5 34 BB15 FPGA Daughter Card Bank 1 DCA_B1_N10_VREF P1 J6 P2 J6 34 AN17 DCA_B1_N11_VREF P1 J8 P2 J8 34 AV13 DCA_B1_P13_CC P1 K11 P2 K11 34 AJ20 DCA_B1_N13_CC P1 J12 P2 J12 34 AJ19 DCA_B1_P18_CC P1 C21 P2 C21 34 AR15 DCA_B1_N18_CC P1 D22 P2 D22 34 AT15 DCA_B1_P4_CC 1 11 P2 C11 34 AU15 B1 N4 P1 D12 P2 D12 34 AV14 FPGA Daughter Card Bank 2 DCA B2 P12 P1 H29 P2 H29 34 AP13 DCA_B2_N12_CC P1 G30 P2 G30 34 AR12 DCA_B2_P18_CC P1 H21 P2 H21 34 AV7 DCA_B2_N18_CC P1 G22 P2 G22 34 AW6 DCA_B2_P3_CC P1 A29 P2 A29 34 AU11 B2 N3 P1 B30 P2 B30 34 AU10 DCA B2 P8 P1 A39 P2 A39 34 AV9 B2 N8 CC P1 B40 P2 B40 34 AW8 FPGA Daughter Card Bank 3 DCA_B3_P12_CC P1 K29 P2 K29 34 AR8 DCA_B3_N12_CC P1 J30 P2 J30 34 AT7 DCA_B3_P17_CC P1 K39 P2 K39 34 AR7 DCA_B3_N17_CC P1 J40 P2 J40 34 AR6 DCA_B3_P3_CC P1 C29 P2 C29 34 AN11 DNMEG_V6HXT User Manual www dinigroup com 58 HARDWARE DESCRIPTION Signal Name DC Headers FPGA DCA _ 5 P1 D30 P2 D30 34 AP10 DCA_B3
49. 26 O tuF CLK SATAp c n U34 25 MGTREFCLKOP 105 Wee MGTREFCLKON 105 MGTREFCLKIP 105 125 MGTREFCLKIN 105 i 42 SATA1 c C544 O iuF 5 1 gt GND 105 xN C C543 O uF SATA TxN 3 P 5 no MGTTXNO 105 gt Od Y40 _SATA1 RxP SATAi RxP 5 GND ix 105 SATAi HxN c C781 SATA RN 3 NB MGTRXNO 105 H RX HO Y44 SATA2 GND MGTTXP1_105 _ AxN c 8 MGTTXN 1105 Too 2 m 105 138 __ 2 c Mm o MGTRXNi 108 37 c 67800 5005 E 67800 5005 dh W42 SATAS J6 2 105 W41 __ _ _ 1 gt C798 O 1uF 20900 H X Fes V40 c C798 EE es MGTRXP2 105 yag SATA3 HxN das De gt MGTRXN2 105 C539 RxN STONN 5 V44 SATA4 c C538 O tuF SATA2 6 MGTTXP3 105 V43 SATA4 HxN ri MGTTXN3_105 4 end 038 SATA4 8 5 MGTRXP3 105 MTH SATA TAN c 1 79 8 BC38 MGTRREF 105 67800 5005 MGTRREF_105 me MGT
50. 2N J24 139 GTP_SEAMG_TXB3P J24 101 GTP_SEAMG_TXB3N J24 93 GTP_SEAMG_RXB3P J24 123 GTP_SEAMG_RXB3N J24 115 EL Gs ES EG eae C C 4 6 SATAII Interface Serial ATA SATA or Serial Advanced Technology Attachment is a computer bus interface for connecting host bus adapters to mass storage devices such as hard disk drives and optical drives Serial ATA was designed to replace the older ATA AT DNMEG_V6HXT User Manual www dinigroup com 83 HARDWARE DESCRIPTION Attachment standard also known as EIDE offering several advantages over the older parallel ATA PATA interface reduced cable bulk and cost 7 conductors versus 40 native hot swapping faster data transfer through higher signaling rates and more efficient transfer through an optional I O queuing protocol SATA host adapters and devices communicate via a high speed serial cable over two pairs of conductors To ensure backward compatibility with legacy ATA software and applications SATA uses the same basic ATA and ATAPI command set as legacy ATA devices 4 6 1 SATA IlI Circuit Diagram The SATA II interfaces are hardwired for HOST DEVICE operation Both TX RX signal pairs are differentially routed and AC coupled with 0 1uF capacitors see Figure 28 5 C825 CLK SATAp C8
51. 741 Mod ABS Module Absent connected to VeeT or VeeR in the module RSO Rate Select 0 optionally controls SFP module receiver Rx LOS 3rd Receiver Loss of Signal Indication In FC designated as Rx LOS and in Ethernet designated as Signal Detect Rate Select 1 optionally controls SFP module transmitter Receiver Ground Receiver Ground Inverse Received Data Out Received Data Out Receiver Ground Receivet Power Transmitter Power Transmitter Ground Transmitter Data In Inverse Transmitter Data In Transmitter Ground 4 4 2 SFP Circuit Diagram SFP connectors J38 J39 J40 and J41 on the DNMEG_HXT are single SFP connectors with press fit heatsinked cages applications see Tyco P N 2007464 2 DNMEG_V6HXT User Manual www dinigroup com 77 HARDWARE DESCRIPTION P3 3VD P2 5VD P2 5VD 5 5 R714 8715 5 8716 8717 8718 8719 R720 8721 47K 5 S lt 4 7K S 4 7K lt 47K lt 47K BOTTOM TOP 1 20 EUN DEAL TASSE 2 iT 19 51 17 SEP_HS1_TxDIS 1 TxDISABLE HS HS SFP_HS1_SDA lt 5 51 5 5 SDA VEET 46 P3 3V VCCT HS1 8 SFP HS1 SCL SFE HEI HOD 84 Sot PSSYVCCTCSFE pg17 SFP HSi MOD ABS
52. 85232 VDD _ 16v 8 vee HS BS282 VE 7106 5232 LTC2804 1 SSOP16 LTC2804CGN 1 PBF Figure 10 FPGA MCU Serial Port The two signals that are relevant to the FPGA are Transmit Data FPGA TXD Receive Data FPGA_RXD 1 6 2 Connections between FPGA and the RS232 Port connections between the FPGA and the RS232 Port are shown in Table 11 Table 11 Connections between RS232 Port and the FPGA DNMEG_V6HXT User Manual www dinigroup com 40 HARDWARE DESCRIPTION FPGA U34 BC33 U34 BD33 1 7 Backup Battery The encryption key memory cells are volatile and must receive continuous power to retain their contents During normal operation these memory cells are powered by the auxiliary voltage input VCCAUX although a separate VBATT power input is provided for retaining the key when VCCAUX is removed Because VBATT draws very little current on the order of nanoamperes a small watch battery is suitable for this supply To estimate the battery life refer to 125752 Virtex 6 FPGA Data Sheet DC and Switching Characteristics At less than a 150 nA load the endurance of the battery should be limited only by its shelf life does not draw any current and can be removed while VCCAUX is applied VBATT cannot be used for any purpose other than retaining the encryption keys when VCCAUX is removed Backup Batteries are available Panasonic Lithium Coin Cell 3V 40mAH f
53. AG Setup Configuring the FPGA using JTAG 3 2 Powering Up the E 3 3 Hie PT HARDWARE DESCRIPTION uu a QS SSS wQ u q u auqa ________6___ 21 1 DESCRIPTION 21 1 1 Overview 2221 1 FPGA VIRTEX 6 25 11 2225 12 Summary of Virtex 6 FPGA Features 26 13 FPGA Configuration Virtex 6 28 1 3 1 Mode Select Resistors 2 0 1 3 2 In System Programming using a Microcontroller MCU 1 3 3 JTAG aes ere eae pee 30 14 DDR3 Memory UDIMM 30 1 4 1 DDR3 SDRAM Memory Interface Solution essere nennen a aaa 31 142 Design Guidelines DDR3 Termination sie 1 4 3 Design Guidelines DDR3 IO Standards esses ERE SEEE EE 33 144 UDIMM Switching Power Supply bee eee n 33 1 4 5 VTT Linear Power Supply 0 75V s 1 4 6 Serial Presence Detect EEPROM Operation recie erede ne Re eee rene ehe eee ko y ere ede exe redeo eee 33 1 4 7 Clocking Connections between FPGA and UDIMM 34 1 4 8 Connections between FPGA and UDIMM aaa eene 34 1 4 9 UDIMM Trace Len ath 39 1 5 EEPROM esee 1 5 1 EEPROM Circuit Diagram 39
54. AM device The physical layer PHY side of the design is connected to the DDR2 or DDR3 SDRAM device via FPGA I O blocks IOBs and the user interface UI side is connected to the user design via FPGA logic Alternatively AXIA slave interface is available to connect to an AXIA master not shown in Figure 6 Virtex 6 FPGA Virtex 6 FPGA Memory Interface Solution User Interface DDR2 DDR3 SDRAM Physical Memory Controller User Design l I I 1 l 1 Native Interface DFI Interface Physical Interface l Interface L Figure 6 DDR2 DD3 SDRAM Memory Interface Solution The Memory Interface Generator MIG is a self explanatory wizard tool that can be invoked under the CORE Generator software Xilinx published a memory application note please refer to UG 406 Virtex 6 FPGA Memory Interface Solutions User Guide 1 4 2 Design Guidelines DDR3 Termination These rules apply to termination for DDR3 SDRAM e Unidirectional signals are to be terminated with the memory device s internal termination or a pull up of 5062 to VTT at the load A split 10062 termination to VCCO and 10062 termination to GND can be used but takes more power For bidirectional signals the termination is needed at both ends of the signal DCI ODT ot external termination DNMEG V6HXT User Manual www dinigroup com 31 HARDWARE DESCRIPTION VTT gt Rr 500
55. AVTTRCAL 105 8037 6 80 565 _1923 P1 2VF_MGTAVTT J13 i 1 C553 SATA3 2 gt R451 C552 O iuF SATAS xN 3136 1008 gt C796 0 1uF 5 GND C797 O 1uF SATAS RxN s m 4 7 5 8 3 ale 67800 5005 67800 5005 2 J9 C823 0 1uF SATA4 2 GND C824 SATA4 se gt ne C550 SATA4 RxN 5 OND t C549 0 102 __ 4_ 6 1 H end E 8 5 MTH 678005005 Ed kj 67800 5005 Figure 28 SATA II Interface LVDS Oscillator X2 is AC Coupled to the GTX Transceiver clock inputs on the FPGA Note The frequency select signals of the oscillator are connected to the FPGA and hardwired using discrete resistors R458 R468 The default factory installed oscillator is running at 150MHz fixed They are available from Nu Horizons Pletronics P N LV7745DW 150 0M The oscillator power supply is filtered to reduce power DNMEG V6HXT User Manual www dinigroup com 84 HARDWARE DESCRIPTION supply noise and jitter Please see the LV7745DW 150 0M datasheet for more information 2 5 OSC SATA 2 5 OSC SATA n 919 OSC SATA 51 lt lt 8 SATA FSI x2 7 Y FS1 CLK 019 OSC SATA Fso lt lt OSG SATA FSO 8 R463 1 OSC 2 oE 3 1 OSC_SATA_NC P2 5VA_OSC_SATA
56. CINT Lewy am ce 16V 16V 16V 16V 16V 16V VIN C567 3h zl L 680 680uF 2L 680uF L 680uF V av av av av av 2 20 20 20 20 20 20 20 CER TANT TANT TANT TANT TANT gt TANT 20 20 20 20 20 10 19 CER TANT TANT TANT TANT P1 0V TRACI rR TANS 2 17 1 0 SENSEO R486 OR SHARE 4SENSE cone TENSE HI PLOV SENSEN R485 x N 2 SmartSYNCH CONFIG n vout apy 8 Pit ov vOADJ 8 Ret Te SND DN 13 ND L4 P1 ovo THOBT250W DIP22 RSET PTHOBT250WAZ R487 PSU_SEQ_ENin lt PSULSEQ ENIN 4 x ET 1 2 9 E Figure 12 VCCINT Switching Supply for the FPGA Note Heat sinking on the FPGA was designed for worst case conditions Both and active and passive solution ate provided for when the board is rack mounted 2 MCU The NXP LPC1754 is provided to configure the FPGA via SelectMAP from a USB Flash drive and other miscellaneous housekeeping functions including the LCD Display The LPC1754 is an ARM Cortex M3 based microcontroller for embedded applications featuring a high level of integration and low power consumption The LPC1754 operate at frequencies of up to 100 MHz The MCU code and functionality is not
57. DINI GROUP LOGIC Emulation Source User Manual DNMEG V6HXT LOGIC EMULATION SOURCE DNMEG V6HXT User Manual Version 2 0 Date of Print 1 2013 Dini Group 7469 Draper Ave La Jolla CA92037 Phone 858 454 3419 Fax 858 454 1728 support dinigroup com www dinigroup com Copyright Notice and Proprietary Information Copyright 2011 Dini Group All rights reserved No part of this copyrighted work may be reproduced modified or distributed in any form or by any means without the prior written permission of the Dini Group Right to Copy Documentation Dini Group permits licensee to make copies of the documentation for its internal use only Each copy shall include all copyrights trademarks disclaimers and proprietary rights notices Disclaimer Dini Group has made reasonable efforts to ensure that the information in this document is accurate and complete However the Dini Group assumes no liability for errors or for any incidental consequential indirect or special damages including without limitation loss of use loss or alteration of data delays or lost profits or savings arising from the use of this document or the product which it accompanies Table of Contents i yuonTrUO 1 1 DNMEG V6HXT LOGIC EMULATION IRIT 1 2 DNMEG_V6HXT LOGIC EMULATIO
58. GA Signal Name SFP Connector FPGA SFP Control Signals CPLD U53 to FPGA 034 CLK_CPLD U53 32 U34 BD31 CPLD_R_WN U53 51 U34 BC31 RST_CPLD U53 143 U34 AW30 SFP_MOD ABS U34 F10 U53 42 SFP_RSO U34 E10 U53 43 SFP_RS1 U34 D10 U53 26 SFP_RXLOS U34 E11 U53 28 SEP SELO U34 AY30 U53 23 SEP SEL1 U34 AL29 053 22 SFP_SEL2 U34 AM29 U53 21 SFP_SEL3 U34 BB31 U53 20 DNMEG_V6HXT User Manual www dinigroup com 72 HARDWARE DESCRIPTION Signal Name SFP Connector FPGA SFP_TXDIS U34 P10 U53 41 SFP_TXFAULT U34 P11 U53 40 SFP_MOD ABS U34 F10 U53 42 SFP Control Signals SFP Connectors to CPLD 053 SFP_LS1_MOD ABS 36 6 U53 76 SFP 151 RSO 36 7 53 77 SEP LS1 RS1 J36 9 53 79 SEP LS1 RXLOS 36 8 53 78 SFP LS1 SCL 36 5 34 A8 SEP 151 SDA 36 4 34 B9 SFP_LS1_TXDIS J36 3 53 75 SFP_LS1_TXFAULT J36 2 53 74 53 82 53 91 53 92 SEP LS3 TXFAULT 36 42 SFP_LS4_MOD ABS J36 66 SFP_LS4_RSO J36 67 U U U U U U U SFP 152 MOD ABS J36 26 U53 68 SFP_LS2_RSO J36 27 U53 66 SFP_LS2_RS1 J36 29 U53 80 SFP_LS2_RXLOS J36 28 U53 64 SFP_LS2_SCL J36 25 U34 B12 SFP LS2 SDA 36 24 U34 C13 SFP_LS2_TXDIS J36 23 U53 69 SEP 152 SDA J36 24 U34 C13 SFP_LS2_TXDIS J36 23 U53 69 SEP 152 TXFAULT J36 22 U53 70 SFP_LS3_MOD ABS J36 46 U53 61 SFP_LS3_RSO J36 47 U53 60 SFP_LS3_RS1 J36 49 U53 85 SFP_L
59. HOST connector J42 Note Ensure valid bitfile has been loaded onto the USB Flash Drive e Format FAT e File Name fpga a bit 2 2 Powering Up the Board 3 Power up the board by turning ON the ATX power supply and verify the ATX PWR OK LED 0528 is ON indicating the presence of 12V located at the bottom left side of the board 2 3 Configuring the FPGA Monitor the USB Flash drive LED for a READ indication while the MCU reads the bitfile 4 Verify that the DONE blue LED 055 is enabled indicating successful configuration of the FPGA from the USB Flash Drive Note This process takes approximately 60 seconds to complete DNMEG V6HXT User Manual www dinigroup com 17 PROGRAMMING CONFIGURING THE HARDWARE 3 Configuring the FPGA using JTAG This section lists detailed instructions for programming the Xilinx Virtex 6 FPGA using iMPACT Version 13 1 tools Before configuring the FPGA ensure that the Xilinx software and the Xilinx Platform Cable USB II driver software are installed on the host computer The JTAG Boundary Scan configuration interface is always available regardless of the Mode pin settings The JTAG Boundary Scan configuration mode disables all other configuration modes to prevent conflicts between configuration interfaces Note This User Manual will not be updated for every revision of the Xilinx ISE tools so please be aware of minor differences 3 1 Setup Configuri
60. K amp SFP HST RSD MOD ABS u p917 HS1_RS0 lt SFPF HST RSLOS 24 Rso VEER H3 srP Rxbp 17 HxLOSCSEP 1 9 Los RD SEP HST RxDa pg 7 XOSL 4 10 851 RD mon CUR 1 H veer VEER 21 40 8689 1508 LED SFP HS 0526 LED GRN 22 GAGE 53 CAGE 5 38 54 lt CAGE 55 B 3c Sg CAGE CAGE 57 d 28 5 33 59 E 32 30 31 CONN_SFP 1888247 2 Figure 26 SFP Interface channel 1 shown Refer to pat 3 2 GTX GTH Transceiver Clocks for clocking information 4 4 3 Connections between the SFP Connectors and the FPGA Table 27 lists the connections between the SFP connectors 38 J39 J40 and J41 and the FPGA 034 Table 29 Connections between the SFP Connectors and the FPGA Signal Name SFP Connector SFP Clocks LVPECL CLK_SFP HS_MGT116P U37 9 CLK_SFP HS_MGT116N U37 10 CLK_SFP HS_MGT114P_ALT U37 11 CLK_SFP HS_MGT114N_ALT U37 12 SFP Control SFP_HS1_MOD ABS 141 6 SFP_HS1_RSO 41 7 SFP_HS1_RS1 41 9 SFP_HS1_RXLOS 41 8 SFP_HS1_SCL 41 5 SFP_HS1_SDA 41 4 SFP_HS1_TXDIS 41 3 SFP_HS1_TXFAULT 141 2 SFP_HS2_MOD ABS 140 6 SFP HS2 RSO 740 7 SF
61. LK2_BIDIR or CLK3_BIDIR to the cattier Rule 5 33 The Mezzanine module shall connected CLK_DIR via 10K pull up resistor to 3P3V when it requires the carrier card to drive a clock on either CLK2_BIDIR or CLK3 BIDIR to the mezzanine module DNMEG_V6HXT User Manual www dinigroup com 62 HARDWARE DESCRIPTION 3 6 2 Connection between FMC Mezzanine Card Clocks and the FPGA The connection between the FMC Mezzanine Card clocks and the FPGA are shown in Table 23 Table 23 Connections between FMC Mezzanine Card Clocks and the FPGA Signal Name FMC Mezzanine Card FMC_CLK0_M2C_P J8 H4 FMC_CLK0_M2C_N J8 H5 FMC_CLK1_M2C_P 18 62 FMC_CLK1_M2C_N J8 G3 FMC_CLK2_BIDIR_P J8 K4 FMC_CLK2_BIDIR_N J8 K5 CLK3 BIDIR P J8 J2 FMC_CLK3_BIDIR_N J8 J3 FMC_CLK_DIR J8 B1 _ M2C P J8 H4 Ce eC C C EC 4 High Speed Interfaces 4 1 CFP Interface One C form factor pluggable CFP interface J25 is provided on the DNMEG HXT The Mult Source Agreement MSA defines the form factor of an optical transceiver which can support 40Gbit s and 100Gbit s interfaces for Ethernet Telecommunications and other applications MDIO Contro Alarm RXMCLK optara RXDATA REFCLK TXDATA TXMCLK mora The electrical interface will vary by application but the nominal signaling lane rate is 10Gbit s per lane and docume
62. LOS 0526 53 134 SFP LOS 0525 53 131 SFP LOS 0524 53 17 SFP LOS 0523 6 Power Distribution The DNMEG V6HXT Logic Emulation Board supports a wide range of technologies from legacy devices like serial ports to DDR3 SDRAM Optical Interfaces and Transceivers on the Xilinx FPGA This wide range of technologies including the vatious FPGA power supplies requires a variety of power supplies These are provided on the DNMEG_V6HXT Logic Emulation Board using a combination of switching and linear power regulators 6 1 Stand Alone Operation An external ATX power supply is used to supply power to the DNMEG_V6HXT Logic Emulation Board in stand alone mode see Figure 33 The external power supply connects to a 24 Pin Mini Fit Jr ATX Power header J3 Molex P N 39 29 1248 DNMEG_V6HXT User Manual www dinigroup com 92 HARDWARE DESCRIPTION The user should connect the matching male power connector on the ATX power supply to this header The DNMEG_V6HXT Logic Emulation Board has the following shared power supplies they are generated from the 12V supply on the external power connector J3 In addition P5 0V_A TX and P3 3V_ATX are also used to drive LDO supplies etc Power Supply P12V_ATX P2 5VD P3 3VD P5 0V P FMC VADJ P1 0V VCCINT P2 5VA P DIMM Dini Group recommends a power supply
63. MGT108N QSFP Clocks LVPECL CLK_QSFP_MGT117P CLK_QSFP_MGT117N 41 15 25 146 41 14 25 147 41 7 34 R41 41 6 34 R42 41 10 34 141 41 9 34 J42 41 12 34 41 41 11 34 42 Gaye U U U U U U 40 11 34 4 40 12 34 3 CLK_QSFP_MGT118P 40 9 34 E4 QSFP MGT118N 40 10 34 E3 SFP HS High Speed Clocks LVPECL CLK_SFP HS_MGT116P U37 9 34 R4 CLK_SFP HS_MGT116N U37 10 34 R3 CLK_SFP HS_MGT114P_ALT U37 11 34 Y10 SFP HS MGT114N ALT 037 12 34 Y9 SFP LS Low Speed Clocks LVPECL CLK_SFP LS_MGT114P 32 9 34 AB10 CLK_SFP LS_MGT114N 32 10 34 AB9 CLK_SFP LS_MGT115P 32 11 34 V10 CLK_SFP LS_MGT115N 32 12 34 V9 U U U U U U U U Note The maximum clock frequency for the 515338 clock generator is 710MHz Only two unique frequencies above 350 MHz can be simultaneously output Fvco 4 and Fvco 6 See 3 3 Synthesis Stages on page 17 of the datasheet 3 3 PCI Express Cable Reference Clocks HCSL To control jitter radiated emissions and crosstalk and allow for future silicon fabrication process changes a low voltage swing current mode differential clock is specified Isolated power domains between the two Subsystems are maintained through DNMEG_V6HXT User Manual www dinigroup com 51 HARDWARE DESCRIPTION implementation of AC coupling capacitors at the source Supplying the cable r
64. N BOARD 5 2 5 3 PACKAGE CONTENTS 2 4 INSPECT THE 8 5 ADDITIONAL INFORMATION 8 Pr o 10 1 BEFORE YOU 10 1 1 Configuring the Programmable Components a niii ne We e ERU Hr et 10 1 2 10 1 3 Exploring the Customer Support Package E 2 BOARD SETUP e 2 1 Installing the FPGA SE EEKE EROS 2 1 1 Tools required is 2 1 2 Assembly ova EEE TEREE ETE TE EEIE TE 2 2 Before Powering Up the 23 Powering Up the Board 3 USING THE REFERENCE DESIGN MAIN 13 PROGRAMMING CONFIGURING THE HARDWAFRE 16 1 INTRODUCTION asawa ____________________________ CONFIGURING THE FPGA USING USB FLASH DRIV 2 2 1 Setup Configuring the FPGA using USB Flash Drive 2 2 Powering Up the Boards uento t GRE MENS 2 3 Configuring the FPGA 3 CONFIGURING THE FPGA USING JT
65. N1 34 AV1 DCA_B3_N10 34 12 DCA_B3_N12_CC 34 AT7 B3 N13 VREF 34 AM10 DCA_B3_N14_VREF P2 J34 34 AU4 DCA_B3_N15 P2 J36 34 AW3 d c bo oo 34 AN12 34 AW8 34 AJ15 34 AK17 34 AP11 34 AK15 34 15 34 AP13 34 17 34 AT12 34 AL14 34 AW9 34 AY7 34 AV7 34 AV12 34 AU11 34 AU9 34 AV11 34 AUT 34 AN13 34 AV9 34 AJ16 rg 55 c e Hg RLS rg R 9 i aag gan NIN S GIG rg T a rg a rg T an N pe rg an N ae Jj T gt R 1 rg gt lt rg m gt rg gt 4 rg m gt Ge rg gt Ge rg T a rg 59 rg m g No X rg B N X CC CICCI T c 5 DNMEG_V6HXT User Manual www dinigroup com 113 HARDWARE DESCRIPTION Daughter Card Daughter Card Receptacle Plug Signal Name TOP BOTTOM DCA_B3_N16 DCA_B3_N17_CC DCA_B3_N18 DCA_B3_N2 DCA_B3_N3_CC DCA_B3_N4 DCA_B3_N5 DCA_B3_N6 DCA_B3_N7 DCA_B3_N8_CC DCA_B3_N9 DCA B3 0 DCA B3 P1 DCA B3 P10 DCA B3 P11 DCA B3 P12 CC DCA B3 P13 DCA B3 P14 B3 215 DCA B3 P16 PIT DCA B3 P18 DCA B3 P2 B3 P3 CC DCA B3 P4 B3 P5 DCA B3 P6 34 AT9 DCA_B3_P8_CC 34 AU6 DCA _ P1 K23 P2 K23 U34 AU2 34 AV3 34 34 AK10 34 AK12 34 AP10 34 AT2
66. P_HS2_RS1 DNMEG_V6HXT User Manual 740 9 www dinigroup com CG C HARDWARE DESCRIPTION Signal Name SFP Connector FPGA SFP_HS2_RXLOS J40 8 U53 134 SFP_HS2_SCL J40 5 U34 A12 SFP_HS2_SDA J40 4 U34 A13 SFP_HS2_TXDIS J40 3 U53 137 SFP_HS2_TXFAULT J40 2 U53 138 SFP_HS3_MOD ABS J39 6 U53 133 SEP HS3 RSO J39 7 U53 132 SEP HS3 RS1 J39 9 U53 130 SFP_HS3_RXLOS J39 8 U53 131 SFP_HS3_SCL J39 5 U34 A10 SFP_HS3_SDA J39 4 U34 B11 SFP_HS3_TXDIS J39 3 U53 12 SFP_HS3_TXFAULT J39 2 U53 11 SFP_HS4_MOD ABS J38 6 U53 15 SEP 54 RSO J38 7 U53 16 HS4 RS1 J38 9 U53 18 SEP 54 RXLOS J38 8 U53 17 SFP_HS4_SCL J38 5 U34 R12 SFP_HS4_SDA J38 4 U34 R13 SFP_HS4_TXDIS J38 3 U53 14 SFP_HS4_TXFAULT J38 2 U53 13 GTH High Speed Interconnect from SFP Connectors to FPGA U34 SFP_HS1_TXDP J41 18 U34 12 SEP HS1 TXDN 41 19 U34 T1 SFP_HS1_RXDP 41 13 034 04 SFP_HS1_RXDN 41 12 034 03 SFP_HS2_TXDP J40 18 U34 P2 SFP_HS2_TXDN J40 19 U34 P1 SFP_HS2_RXDP J40 13 U34 T6 SFP_HS2_RXDN 40 12 U34 T5 SFP_HS3_TXDP J39 18 U34 M2 SFP_HS3_TXDN J39 19 U34 M1 DNMEG_V6HXT User Manual www dinigroup com 79 HARDWARE DESCRIPTION Signal Name SFP Connector SFP_HS3_RXDP J39 13 SFP_HS3_RXDN J39 12 SFP_HS4_TXDP J38 18 SFP_HS4_TXDN J38 19 SFP_HS4_RXDP J38 13
67. RE DESCRIPTION SFP HS High Speed SFP LS Low Speed Figure 18 shows the clock generator circuit LED DS14 is used to indicate PLL Loss of Lock PLL_LOL ye 5 lt MGT XTAL IN FA 238 25 0000MB K3 OUT C983 J27 T 1 12 901 144 8RFX 2 5 EXT INI 1 C996 EXT INp i 4 R173 1008 C997 EXT INn 1 22 CLK BUFp 2 5 cuc efr vn z N1 CLKOA 31 CIK BUFR 1 MGTTNS CLKOB 2 INS CLK J28 MGT_IN4 CT 901 144 8RFX F 1 9 Esl Ne 4 CLK_SEP HS_BUFp CUA CIK BUEn 10 CLK SFPsLS R163 R164 L3 CLK SFP LS BUEn 4 7K 5 4 7K i 20 MGTSCL _ 12 15 pgi9 MGT SCL lt 1 MGT SDA 19 SCL VDDO1 45 TP41 pg19 SDA lt lt MOTNA 8 50 T 1 ka Blox PA SVA MGT CLK 23 7 RSVD_GND VDD FB21 R166 R167 25 24 2 5 4 7K GNO vob 3 256 253 6254 0265 0267 0262 cos SI5338 GFN24 O 1UF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF BLMYBAG102SN1D 10uF SI5338A A GM Liev 1 ev 1 16 16 400 63 10 10 10 10
68. S UH MER MARIO 91 5 4 USB Fault 91 55 Miscellaneous LEDs 91 6 POWER DISTRIBUTION 4509 6 1 Stand Alone Operation ote 92 6 1 1 External Power Connector 94 6 2 Voltage Monitors and Reset 6 2 1 Power Sequencing uoo opere ERG IR 6 2 2 7 FMC MEZZANINE CARD ii 7 1 FX exor Jar EMG 511 c 95 7 3 Power and Reset 97 7 4 FMC to FPGA IO Connections 98 8 MEG ARRAY DAUGHTER CARD HEADER 105 8 1 Daughter Card clocking iiis n eite 105 6 2 Daughter Card Header Pin Assighimenis uix ous Cea 105 8 3 Special Pins on the Daughter Card Header 8 3 1 DCA CEK DN IN P N and _ _ _ _ 108 8 3 2 Power Supply 84 Power and Reset 8 5 FPGA to Daughter Card Header IO Connections 109 8 6 Insertion Removal of Daughter Card 116 0 7 G MEGZAL Pay SpecifiCallOnss i eds e d ene EXER EE 118 9 MEGHANICAD R
69. S3_RXLOS 36 48 53 59 SFP_LS3_SCL J36 45 U34 G10 SFP_LS3_SDA 36 44 U34 H11 LS3 TXDIS J36 43 U53 83 U U U DNMEG_V6HXT User Manual www dinigroup com 73 HARDWARE DESCRIPTION Signal Name SFP Connector FPGA 1554 R51 36 69 U53 57 154 RXLOS 36 68 U53 58 154 SCL 36 65 U34 A9 154 SDA 36 64 U34 B10 SFP_LS4_TXDIS 36 63 U53 88 SEP 154 TXFAULT 36 62 U53 87 SEP 155 MOD ABS J37 6 U53 114 SFP_LS5_RSO J37 7 U53 115 SEP 155 51 J37 9 U53 110 SFP_LS5_RXLOS J37 8 U53 111 SEP 155 SCL J37 5 U34 D11 SEP 155 SDA J37 4 U34 E12 SEP 155 IXDIS J37 3 U53 113 155 TXFAULT 37 2 053 112 SEP LS6 MOD ABS J37 26 U53 104 SFP_LS6_RSO J37 27 U53 116 SFP_LS6_RS1 J37 29 U53 118 SFP_LS6_RXLOS J37 28 U53 117 SFP_LS6_SCL J37 25 U34 J11 SFP_LS6_SDA J37 24 U34 K11 SEP 156 TXDIS J37 23 U53 105 SFP_LS6_TXFAULT J37 22 U53 106 SFP_LS7_MOD ABS J37 46 U53 102 SFP_LS7_RSO J37 47 U53 101 SFP_LS7_RS1 J37 49 U53 121 SFP_LS7_RXLOS J37 48 U53 100 SFP_LS7_SCL J37 45 U34 F12 SEP_LS7_SDA J37 44 U34 G12 SFP_LS7_TXDIS J37 43 U53 103 SEP 157 TXPAULT J37 42 U53 120 SFP_LS8_MOD ABS J37 66 U53 128 SFP_LS8_RSO J37 67 U53 98 DNMEG_V6HXT User Manual www dinigroup com 74 HARDWARE DESCRIPTION
70. SEP apro 4 2 1 Circuit 422 Connection between Connectors and the FPGA cccccsccsssssscssssesssecsscessccsscssscessesesssesssesssesssesnscsnsssnesseessaesseeessesenessseesseesseesaees 68 43 SEP Interface Up 10 6 660 a saa e 70 4 3 1 SFP Pin Assignments an 4 3 2 M 72 4 3 3 Connections between 2x2 SFP Connectors and the FPGA 72 44 SFP Interface up to 11 182Gbps ie 44 1 SEP Pin ASSIS MMe 4 4 2 SEP Circuit 4 4 3 Connections between the SFP Connectors and the FPGA s 4 5 GTX Expunsion Interface RED ED EY ENSE OI 4 5 1 GTX Expansion Circuit Did stam 4 5 2 Connections between FPGA and GTX Expansion Header 46 SATA TE Interface 4 6 1 SATA II Circuit Diagram 4 6 2 Connections between FPGA and SATA II Connectors 47 POL Express Cable eee 4 7 1 Cable Reference Clocking Options 4 7 2 Cable niei nei 4 7 3 Connections between FPGA and the PCI Express Cable Connector 5 TE DIINDICATORS 6s instet ine e RO thes 5 1 FPGA Sta US DID CT 90 5 2 BIBT EOM DID e 90 33 Platform Manager Status BED
71. TA ot Serial RapidI O to the mix All or any subset of the above interfaces high speed serial interfaces can be used simultaneously Two GTH channels are connected to high speed SMAs DNMEGV6_HXT User Manual www dinigroup com 2 INTRODUCTION DDR3 Bulk Memory A single PC3 8500 DDR3 UDIMM socket enables up to 16GB plus ECC of memory for bulk storage and lookup With a 16GB UDIMM memory stick the configuration is 2048M x 72 Using a 2 or 3 speed grade FPGA this interface is tested at the maximum FPGA IO frequency 533 MHz 1066 Mb s with DDR You welcome to use this memory 64 bits with 8 bits of error correction ECC or as 72 bit memory without correction This is the same UDIMM interface used in our blockbuster DNPCIe 106 LL product To minimize data synchronization across clock boundaries important for networking applications it probably makes sense to clock this DDR3 interface at a 3x multiple of the base Ethernet frequency of 156 25 MHz which is 468 75 MHz A 3x phase synchronous clock can be easily generated internal to the FPGA allowing zero latency synchronous data transfers between the Ethernet packet receiving logic and the DDR3 memory controller The DDR3 controller can be optimized in any way you choose Dini Group provide several Verilog examples at no charge All functions of the DDR3 DRAM can be exploited and optimized Up to 8 banks can be open at once Timing variables such as CAS latency and
72. X3N QSFP2_RX3P QSFP2_RX3N QSFP2_TX4P QSFP2_TX4N 34 5 34 C4 34 C3 34 D6 34 D5 34 AN31 34 AN32 34 AP31 34 AR32 34 34 AU32 34 AV32 ER C 34 14 35 36 34 13 35 37 34 K6 35 17 34 5 35 18 34 K2 735 3 34 1 35 2 34 18 35 22 3417 35 21 34 04 35 33 34 63 35 34 34 H6 35 14 34 5 35 15 34 H2 35 6 34 1 35 5 QSFP2_RX4P 34 8 35 25 QSFP2_RX4N 34 7 35 24 QSFP2 INTN 35 28 U34 AJ31 QSFP2_LPMODE 35 31 U34 AT30 QSFP2_MODPRSN 35 27 U34 AU30 DNMEG_V6HXT User Manual www dinigroup com 69 HARDWARE DESCRIPTION Signal Name QSFP Connector FPGA QSFP2_MODSELN J35 8 U34 AP30 QSFP2_RESETN J35 9 U34 AL32 QSFP2_SCL J35 11 U34 AR30 QSFP2_ SDA J35 12 U34 AK31 4 3 SFP Interface up to 6 6Gbps The board provides two stacked 2x2 SFP Connectors to allow for 8 channels connected to GTX Transceivers The small form factor pluggable SFP is a compact hot pluggable transceiver used for both telecommunication and data communications applications It interfaces a network device mother board for a switch router media converter or similar device to a fiber optic or copper networking cable It is a popular industry format supported by many network component vendors SFP trans
73. _P8_CC P1 C39 P2 C39 34 AU6 DCA_B3_N8_CC P1 D40 P2 D40 34 AU5 FPGA Daughter Card Bank 4 P18 P1 E37 P2 E37 34 BB5 DCA_B4_N18_CC P1 F37 P2 F37 34 34 BC6 DCA_B4_P6_CC P1 E19 P2 E19 DCA B4 N6 CC P1 F19 P2 F19 34 BD6 B4 P1 E21 P2 E21 34 BC8 DCA B4 N7 CC P1 F21 P2 F21 34 BC7 34 BA5 DCA B4 P8 CC P1 E23 P2 E23 CL CI ee 34 BA4 DCA B4 N8 CC P1 F23 P2 F23 3 6 FMC Mezzanine Card Clocks The FMC also known as VITA 57 standard was developed to provide an industry standard mezzanine form factor in support of a flexible modular IO interface to an FPGA located on a baseboard or carrier card It allows the physical IO interface to be decoupled from the FPGA design while maintaining a close coupling between a physical IO interface and an FPGA The FMC standard specifies Samtec s SEARAY connector set The VITA 57 SEAM SEAF Series system provides 400 IOs in a 40 x 10 configuration or 160 IOs in a selectively loaded 40 x 10 configuration in 8 5mm and 10mm stack heights The DNMEG_HXT provides a High Pin Count HPC FMC connector populated with the Samtec s SEARAY socket P N ASP 134486 01 The mating part is CLK 0 1 M2C P N Differential pairs that are assigned for clock signals which are driven from the IO Mezzanine Module to the carrier card CLK 2 3 BIDIR P N Differential pairs tha
74. and the FPGA Signal Name SATA II OSC FPGA SATAp X24 U34 V35 SATAn X2 5 U34 V36 DNMEG V6HXT User Manual www dinigroup com 54 HARDWARE DESCRIPTION 3 5 Daughter Card Header Clocks MEG Array The 400 pin MEG Array connector P2 on the bottom of the PCB is used to interface to Dini Group Daughter Cards e g DNMEG Obs this allows for IO expansion The IO signals are shared with the exception of the clocks The daughter card header provides a dedicated LVDS clock input from daughter card connected to clock capable pins on the FPGA and a dedicated LVDS clock output input to daughter card In addition each IO bank provides a source synchronous LVDS clock that connects to the FPGA The 400 MEG Array connector P1 on the bottom of the PCBA is used to interface to Dini Group products e g DN2076K10 3 5 1 Daughter Card Global Clock Input Output DCA DN INp n TOP is a global LVDS input clock to the FPGA IO Bank 24 and UP OUTp n TOP is a global LVDS output clock from the FPGA IO Bank 24 see Figure 22 Note These signals are routed as differential pairs LVDS and are NOT AC coupled Refer to the Virtex 6 Data Sheet for IO levels and provide DC isolation on the daughter catd if required P12V ATX 12 1 PLUG DCA CLK DN INp TOP _ 918 CLK INp TOP DCA CIR DRINA EL ck p 25 P EA 18 DCA DN INn TOP
75. and the RS232 Port Table 15 Connection between MCU and the Temperature Sensor Table 16 connection to the LPC1754 Table 17 Input connections to the Clock Generator Table 18 Connections between the Clock Buffers and the FPGA Table 19 Connection between the PCI Express Jitter Attenuator and the FPG Table 20 Connection between SATA II Clock Oscillator and the FPGA Table 21 Connections between MEG Array Daughter Card Clocks and the FPGA Table 22 Connections between MEG Array Secondary Clocks and the FPGA Table 23 Connections between FMC Mezzanine Card Clocks and the FPGA Table 24 Connection between the CFP Connector and the FPGA Table 25 Connection between the QSFP Connector and the FPGA Table 26 SFP Pin Assignments sse een Table 27 Connections between 2x2 SFP Connectors and the FPGA Table 28 SFP Pin Assignments Table 29 Connections between the SFP Connectors and the FPGA Table 30 Connections between FPGA and GTX Expansion Header Table 31 Connections between FPGA and SATA II Connectors Oscillator Table 32 Connections between FPGA and the PCI Express Cable Connector Table 33 FPGA Status LEDs Table 34 FPGA DONE LED Table 35 CPLD Status LEDs Table 36 USB Fault LED Table 37 Miscellaneous LEDs Table 38 Logic Reset for the FPGA Table 39 to FPGA IO Connection Table 40 Daughter VCCO Reset Signal 56 Table 41 FPGA to Daugh
76. ard Clock Secondary Figure 25 SFP Interface channel 1 shown Figure 26 SFP Interface channel 1 shown Figure 27 GTX Expansion Header SEAM Figure 28 SATA II Interface Figure 29 SATA II GTX Oscillator Figure 30 CPRSNT Signaling with Power Isolation Figure 31 LED Indicator Figure 32 ATX Power Supply Figure 33 External Power Connection Figure 34 Pin Assignments Figure 35 FMC VADJ Switching Power Supply 2 5V Figure 36 Daughter Card Header Bank Pin Assignments Figure 37 Vcco Adjustable Linear Power Supply x5 Figure 38 Daughter Card Header Power amp RESET aaa E E EE ARE EA EREINEN ETENE List of Tables Table USB Flash Drive Directory COMEET Table 2 Virtex 6 Uncompressed Bitstream Length Table 3 FPGA Configuration Schemes Table 4 SeleccMAP Bus between Microcontroller and FPGA Table 5 Connection between JTAG Header and the FPGA Table 6 Serial Presence Detect EEPROM Connections Table 7 Clocking Connections between FPGA and the UDIMM Connector Table 8 Connections between FPGA and the UDIMM Connector Table 9 UDIMM PCB Trace Table 10 Connections between FPGA and the EEPROM Table 11 Connections between RS232 Port and the FPGA Table 12 Backup Battery Load Table 13 USB Interconnect Table 14 Connections between MCU LCD
77. ard functions are controlled by the NXP LPC1754 ARM based microcontroller including the front panel LCD single DNMEG V6HXT configured with the Xilinx Virtex 6 XCOVHXT565T FPGA can emulate up to 4 million gates of logic as measuted by a reasonable ASIC gate counting standard This gate count estimate number does not include embedded memories and multipliers resident in each FPGA One hundred percent 100 of the FPGA resources are available to the user application but the user s application must include all necessary MACs and the PCIe Bridge The DNMEG_V6HXT achieves high gate density and allows for fast target clock frequencies by utilizing FPGAs from Xilinx s 40nm Virtex 6 HXT family Virtex 6 HXT FPGAs from Xilinx The DNMEG V6HXT is configured with a Xilinx Virtex 6 HXT family FPGA in the FFG1923 package This package supports 720 IOs and all are utilized The HXT FPGAs contain high speed transceiver PHYs of two different types GTX transceivers DNMEG V6HXT User Manual www dinigroup com 22 HARDWARE DESCRIPTION ate capable of handling data rates of 150 MB s to 6 5 Gb s making these useful for lower speed Ethernet Serial ATA and GEN1 GEN2 PCI Express The transceivets are tuned higher 2 48 to 11 18 Gb s making them applicable to 10 gigabit Ethernet 10 GbE Two possible FPGAs can be stuffed XC6VHX380T or the XC6VHX565T The XC6VHX380T comes in three speeds grades with 3 being the fastest The larger XCOVHX565T i
78. ay 192 x 64 pixel FFSTN Grey White Matrix Orbital P N GLK19264 7T 1U FGW Cable Crossed IDC 10 Pin Socket to DB9 18 PCH Cables P N 000 F903 used to connect the LCD to the DNMEG_V6HXT board Additional DDR3 SDRAM UDIMMs Available upon request 4 Inspect the Board Place the board on an anti static surface and inspect it to ensure that it has not been damaged during shipment Verify that all components are on the board and appear intact 5 Additional Information For additional information please visit http www dinigroup com The following table lists some of the resources you can access from this website You can also directly access these resources using the provided URLs Resource Description URL User Manual This is the main source of technical information The manual should contain most of the answers to your questions Demonstration MEG Array Daughter Card header insertion and removal video Videos Dini Group The web page will contain the latest user manual application notes DNMEGV6_HXT User Manual www dinigroup com 8 INTRODUCTION Resource Description URL Web Site FAQ articles and any device errata and manual addenda Please visit and bookmark http www dinigroup com Data Book Pages from Virtex 6 Databook which contains device specific information on Xilinx device characteristics E Mail You may direct questions and feedback to Dini G
79. ble in order to meet the Virtex 6 power sequencing requirements see Table 40 Table 40 Daughter VCCO Reset Signal Signal Name OD Buffer Daughter Card Header RSTn U5 5 U12 5 U3 5 U11 5 U1 5 and U2 5 8 5 FPGA to Daughter Card Header IO Connections Table 41 lists the input output interconnect between the Virtex 6 FPGA and the Daughter Card headers on the top bottom of the board IO is shared with the exception of the clock inputs outputs Table 41 FPGA to Daughter Card Header IO Connections Signal Name DCA_CLK_UP_OUTP_TOP P1 E3 DCA_CLK_UP_OUTN_TOP P1 F3 DCA_CLK_DN_INP_TOP P1 E1 Daughter Card Receptacle DCA CLK DN INN TOP P1 F1 DCA CLK FB P U34 AW33 DCA CLK FB N U34 AY33 DCA CLK UP OUTP BOT DCA UP OUTN DCA CLK DN INP BOT DCA CLK DN INN BOT Daughter Card Plug BOTTOM GI 34 P15 34 P14 3414 34 H13 34 AW35 34 AY35 34 AK35 34 AL35 34 AV33 34 AW34 cias DNMEG_V6HXT User Manual www dinigroup com 109 HARDWARE DESCRIPTION Daughter Daughter Card Receptacle Plug Signal Name TOP BOTTOM DCA_BO_NO_GCC_DN P1 B4 P2 B4 34 BC12 34 AU19 34 AW18 34 BD16 34 BD13 DCA B0 N3 P1 B10 P2 B10 34 BC14 DCA B0 N4 CC P1 B12 P2 B12 34 BC11 DCA B0 N5 P1 B14 P2 B14 34 AR20 34 BB15 DNMEG_V6HXT User Manual www dinigroup com 110 HARDWARE DESCRIPTION
80. blue orange et al Blinking these LEDs in a controlled fashion can confuse a trout While this is unlikely to be fatal to the little fish make sure an adult is present and wear eye protection when testing this feature These LEDs are user controllable from the FPGAs so can be used as visual feedback in addition to the task of distracting fish A JTAG connector provides an interface to ChipScope Veridae and other third party debug tools 1 FPGA Virtex 6 1 1 Overview Virtex 6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components to enable designers to focus on innovation as soon as their development cycle begins Using the third generation ASMBL Advanced Silicon Modular Block column based architecture the Virtex 6 family contains multiple distinct sub families This overview covers the devices in the LXT SXT and HXT sub families Each sub family contains a different ratio of features to most efficiently address the needs of a wide variety of advanced logic designs In addition to the high performance logic fabric Virtex 6 FPGAs contain many built in system level blocks These features allow logic designers to build the highest levels of performance and functionality into their FPGA based systems Built on a 40 nm state of the art copper process technology Virtex 6 FPGAs are a programmable alternative to custom ASIC technology Virtex 6 FPGAs offer the best sol
81. ce a A b P1 8V FMC o Sb Adjust VOUT ADJ Trim Resistors TSM 103 01 T DV OPEN FMC 1 35V naa S Pos Se Baz Res 324 41 50 9 09K 3 24 31 6 10K 3 4 FMC 41 8V VOADJ 4 3 5 2 57 Figure 35 FMC VAD Switching Power Supply 2 5V The voltage can be adjusted by changing the jumper location of JP1 OPEN 1 35 Pin 3 1 FMC 1 5 Pin 3 4 FMC 1 8V Pin 3 5 FMC 2 5V Note FMC Specification allows VADJ gt 0 3 3V VCCO constraints on Virtex 6 devices limits this voltage to 1 14 2 625V MAX The FMC Specification lists the following recommendations regarding the power pins 12P0V These pins carry 12V power from the carrier to the IO Mezzanine module 3P3V These pins 3 3V power from the carrier to the IO Mezzanine module 3P3VAUX A 33V auxiliary power supply These pins carry an adjustable voltage level power from the carrier to the IO Mezzanine module VREF A 2 This is the reference voltage associated with the signaling standard used by the bank A data pins LAxx and HAxx If the signaling standard on Bank A does not require a reference voltage then this pin can be left unconnected Note This option is not supported DNMEG V6HXT User Manual www dinigroup com 97 HARDWARE DESCRIPTION e _ 2 This is the reference voltage associated with the signali
82. ceivers are designed to support SONET Gigabit Ethernet Fibre Channel and other communications standards SFP transceivers are available with a variety of transmitter and receiver types allowing users to select the appropriate transceiver for each link to provide the required optical reach over the available optical fiber type e g multi mode fiber or single mode fiber Optical SFP modules are commonly available in several different categories 850 nm 550 m multi mode fiber SX e 1310 nm 10 km single mode fiber LX e 1490 nm 10 km single mode fiber BS D 1550 nm 40 km XD 80 km ZX 120 km EX or EZX e 1490 nm 1310 nm BX Single Fiber Bi Directional Gigabit SFP Transceivers e DWDM SFP transceivers are also available with a copper cable interface allowing a host device designed primarily for optical fiber communications to also communicate over unshielded twisted pair networking cable or transport SDI video signal over coaxial cable There are also CWDM single fiber bi directional 1310 1490 nm Upstream Downstream SFPs SFP transceivers are commercially available with capability for data rates up to 4 25 Gbit s An enhanced standard called SFP supports data rates up to 10 0 Gbit s DNMEG_V6HXT User Manual www dinigroup com 70 HARDWARE DESCRIPTION Please note the limitation in operating frequency due to Xilinx Virtex 6 clocking limitations see DS152 Virtex 6 FPGA Data Sheet DC and Switching Charact
83. clock signals are intended to be used as differential clock signals These signals are routed to clock capable MRCC inputs on the FPGA and can be used for global clocking 8 3 2 Vccio Power Supply On the Virtex 6 FPGA each IO bank has its own Veco pins Veco is determined by the IO standard for that particular IO bank Since a daughter card will not always be present a daughter card connector a bias generator is used on the motherboard for each daughter card bank to keep the Vcco pin on the FPGA within its recommended operating range The Daughter Card drives Vcco to the required level for the particular IO standard The Veco impressed by the Daughter Card needs to satisfy the Vimax the FPGA on the host board There are five Adjustable Linear Power Supplies on the board one per daughter card header IO bank refer to Figure 37 Refer to the datasheet for the LT1963A from Linear Technology on how to adjust the output voltages R303 allows the user to remove the powers supply if a of 2 5V is required since that voltage can be supplied by the system R303 DNI OR 1 P2 5VD O cuo DCA Par Li 1 LT1963AES8 SO8 LT1963AES8 SHDNSENSE ADJ C2 3 C10 10uF 0 1uF 5 OND Ne 0 1uF 63 20 GND CER pg22 23 24 RSTn lt RSTn Figure 37 Adjustable Linear Power Supply x5 8 4 Po
84. d to the DNSEAM card 3 3V 12V and VCCO The VCCO supply is fixed at 2 5V however the daughter card designer should keep in mind that future Dini Boards may choose to supply a different probably lower fixed voltage here such as 1 8V The diagram below shows the DNSEAM header pin out see Figure 27 3 3V 2 12V 2 3 3V 1 2 VCCO 2 3 3V 1 3 3V 2 12V 2 Figure 27 GTX Expansion Header SEAM 4 5 2 Connections between FPGA and GTX Expansion Header Table 30 shows the connections between the FPGA GTX Transceivers and the GTX Expansion header pins DNMEG V6HXT User Manual www dinigroup com 81 HARDWARE DESCRIPTION Table 30 Connections between FPGA and GTX Expansion Header Signal Name GTX Expansion Header Low Speed IO SEAMG_IO_DOP_CC J24 78 SEAMG IO DON CC J24 79 SEAMG IO D1P CC J24 83 SEAMG_IO_D1N_CC J24 82 SEAMG_IO_D2P J24 62 SEAMG_IO_D2N J24 70 SEAMG IO D3P 24 64 SEAMG_IO_D3N J24 63 SEAMG_IO_D4P J24 97 SEAMG_IO_D4N J24 98 SEAMG_IO_D5P J24 99 SEAMG_IO_D5N J24 91 SEAMG_IO_D6P J24 80 SEAMG IO D6N J24 72 SEAMG IO D7P J24 81 SEAMG_IO_D7N J24 89 High Speed IO CLK_REFCLK_SEAMG_AOP J24 16 CLK_REFCLK_SEAMG_AON _ J24 24 CLK_REFCLK_SEAMG_A1P 24 40 CLK REFCLK SEAMG A1N J24 48 5 J24 145 CLK REFCLK SEAMG BON J24 137 SEAMG B1P J24 121 CLK SEAMG BIN J24 113 SEAMG TXAOP J24 34 _
85. e provided Debug and trace functions are integrated into the ARM Cortex M3 Serial wire debug and trace functions are supported in addition to a standard JT AG debug and parallel trace functions The ARM Cortex M3 is configured to support up to eight breakpoints and four watch points Figure 16 shows J16 the JTAG connector used to debug the NXP LPC1754 DNMEG V6HXT User Manual www dinigroup com 45 HARDWARE DESCRIPTION P3 3VD P3 3VD S 557 C559 R413 R415 419 5 R421 10uF 0 1uF 4 7K S 4 7K lt 4 7K lt 4 7K _ 6 3 20 MCU_TRSTn CER U TM MCU WDIO MCU_TCK SWDCLK MCU_TDO SWO MCU RSTn R418 R420 4 7K DNI 4 7K JTAG 20Pin 10 88 1201 Figure 16 MCU Trace Debug Header Table 16 shows the connection between the MCU JTAG connector and the NXP LPC1754 Table 16 connection to the LPC1754 Signal Name JTAG Connector MCU_TCK SWDCLK 16 9 MCU_TDI 16 5 MCU_TDO SWO 716 13 MCU_TMS SWDIO 16 7 MCU_RSTn 16 15 MCU_TRSTn 16 3 3 Clocking Networks 3 1 Clock Methodology The DNMEG V6HXT has a flexible and configurable clocking scheme Figure 17 is a block diagram showing the clocking resources and connections All of the clock networks on the DNMEG V6HXT are routed point to point using dedicated differential LVPECL traces Since LVPECL is a low voltage swing differential signal using a
86. eference clock is required from an Upstream Subsystem e Upstream Device Clock from local PCI Express Clock Buffer U14 e Downstream Device Clock from remote REFCLK on cable Buffered U16 Upstream Cable Interconnect Downstream including mated connectors Subsystem Subsystem CREFCLKp uREFCLK AC Coupling A dedicated oscillator X1 100MHz is buffered to provide all the possible clocking requirements see Figure 19 CLK CABLEp _ 5 CLK PCIEIBUF CABLEn PCIEIBUF CABLEp PCIETBUF CABLEn R341 R340 49 9R 49 9R PCIE2BUE CABLEp _ lt CLK_PCIE2BUF_CABLEp 4 lt lt CLK_PCIE2BUF_CABLEn R332 R333 49 9R 49 9R PCIE Cable CLK Buffer HCSL R356 100R 1 3 20 CLK PCIEIBUF CABLEp 33R PCIE1BUE INT CLKA 1 PCIETBUF FPGAp 4 M GLKA 19 PCIEIBUF CABLEn r R39 PCIEIBUF FPGAn GLK PCIETBUF FPGAR boa sec 18 PCIEPBUF CABLEp r R29 33R P3 3V_PCIE_CLKBUF_FIL 7 2 QLKB 17 PCIE2BUF CABLEn r R30 R334 R335 9 25 IN2 CLKB 4998 lt 49 9R R355 1K PCIE_BUF_SEL_1 14 PCIESBUF CABLEp r 831 33R Bs Eid R346 1K BOF 13 CLK PCIESBUF CABLEn r R32 R345 1K PCIE BUF PDn 5 g CLKC 12 PCIE4BUF r _ 845 33R
87. er to Daughter Card Header Clocks par 3 5 in this User Manual 8 2 Daughter Card Header Pin Assignments The pin assignments of the daughter card header are designed to reduce cross talk to manageable levels while operating at full speed of the Virtex 6 LVDS standards The daughter card header 15 divided into five banks refer to Figure 36 Virtex 6 devices support source synchronous interfacing with LVDS signaling at up to 1 6Gbps The ground to signal ratio of the connector 15 1 1 refer to Figure 36 General purpose IO is arranged in a GSGS pattern to allow high speed single ended or differential use These DNMEG V6HXT User Manual www dinigroup com 105 HARDWARE DESCRIPTION signals ate routed as loosely coupled differential signals meaning when used differentially they benefit from the noise resistant properties of a differential pair but when used in a single ended configuration they do not interfere with each other excessively DNMEG_V6HXT User Manual www dinigroup com 106 HARDWARE DESCRIPTION i Clock outputs Q N Figure 36 Daughter Card Header Bank Pin Assignments DNMEG V6HXT User Manual www dinigroup com 107 HARDWARE DESCRIPTION 8 3 Special Pins on the Daughter Card Header 8 3 1 DCA_CLK_DN_IN_P N DCA UP OUT P N The daughter card pin out defines two bidirectional differential clock pins These
88. eristics for more information Symbol DC Parameter Min Typ Max Units VIDIFF Differential peak to peak input voltage 210 800 2000 mV Rin Differential input resistance 90 100 130 Q Cext Required external AC coupling capacitor 100 nF 4 3 1 SFP Pin Assignments The SFP pin assignments are listed in Table 26 Pin Number Symbol Table 26 SFP Pin Assignments Desctiption VeeT Transmitter Ground TX Fault Transmitter Fault Indication TX Disable Transmitter Disable MOD DEF2 Module Definition 2 SDA MOD DEF1 Module Definition 1 SCL MOD DEFO Module Definition 0 Module Present Rate Sel LOW or OPEN reduced bandwidth HIGH Full Bandwidth LOS Loss Of Signal VeeR Receiver Ground VeeR Receiver Ground VeeR Receiver Ground RD Inverse Received Data Out RD Received Data Out Receiver Ground Receiver Power Transmitter Power Transmitter Ground Transmitter Data In DNMEG_V6HXT User Manual Inverse Transmitter Data In www dinigroup com 71 HARDWARE DESCRIPTION Pin Description Number 20 Transmitter Ground 4 3 2 SFP Circuit Diagram SFP connectors 36 J37 on the DNMEG_HXT 2x2 medium height press fit cages with lightpipes not used see Molex P N 757145001
89. et MAC block Supports 1000BASE X PCS PMA and SGMII using GTX transceivers Supports and using SelectIO technology resources DNMEG_V6HXT User Manual www dinigroup com 27 HARDWARE DESCRIPTION o 2500Mb s support available 40 nm copper CMOS process technology 1 0V core voltage 1 2 3 speed grades only Lower power 0 9V core voltage option 1L speed grade only High signal integrity flip chip packaging available in standard or Pb free package options 1 3 FPGA Configuration Virtex 6 Virtex 6 FPGAs are configured by loading application specific configuration data the bitstream into internal memory Because the Xilinx FPGA configuration memory is volatile it must be configured each time it is powered up The bitstream is loaded into the device through special configuration pins These configuration pins serve as the interface for a number of different configuration modes The following configuration modes supported e Slave SelectMAP parallel configuration mode x8 JTAG Boundaty Scan configuration mode The configuration modes are explained in detail in Chapter 2 Configuration Interfaces of the 00360 Virtex 6 FPGA Configuration User Guide The specific configuration mode is selected by setting the appropriate level on the dedicated Mode input pins M 2 0 The M2 and MO mode pins should set at a constant DC voltage level either through pull up or pull down resisto
90. ference Clocks HCSL for clocking information 4 7 3 Connections between FPGA and the PCI Express Cable Connector Table 32 lists the connections between the high speed serial transceivers GTX on the FPGA and the PCI Express connector Note Tx Pairs are isolated by ceramic capacitors Table 32 Connections between FPGA and the PCI Express Cable Connector Signal Name PCI Express Cable FPGA PCIE1 RECLKP J4 A14 Multiple Schematic Sources see PCIE1 RECLKN J4 A15 Multiple Schematic Sources see 1_ J4 A2 U34 AE42 PCIE1_PETNO U34 AEA1 PCIE1 PERPO 4 2 U34 AD40 PCIE1_PERNO DNMEG_V6HXT User Manual 4 3 U34 AD39 www dinigroup com 88 HARDWARE DESCRIPTION Signal Name PCI Express Cable FPGA _ 1 J4 A5 U34 AD44 PCIE1_PETN1 J4 A6 U34 AD43 PCIE1_PERP1 J4 B5 U34 AC38 PCIE1_PERN1 J4 Bo U34 AC37 PCIE1_PETP2 J4 A8 U34 AC42 PCIE1 PETN2 J4 A9 U34 AC41 PCIE1 PERP2 J4 B8 U34 AB40 PCIE1 PERN2 J4 B9 U34 AB39 _ J4 A11 U34 AB44 PCIE1 PETN3 12 U34 AB43 PCIE1 PERP3 J4 B11 U34 AA38 PCIE1 PERN3 J4 B12 U34 AA37 PCIE1_FPGA_CPERSTN U7 6 S1 5 U34 A15 PCIE1_FPGA_CPWRON U7 7 S1 6 U34 B15 PCIE1_FPGA_CPRSNT U6 1 S1 1 U34 B17 PCIE1_FPGA_CWAKE U6 3 S1 2 U34 A17 Multiple Sources see
91. formation reference the SEE 8436 Specification for the 10Gbs 4X Pluggable Transceiver 4 2 1 QSFP Circuit The QSFP module and the host system are hot pluggable The module or the host system shall not be damaged by insertion or removal of the module The QSFP control signals are directly connected to the FPGA while the high speed signals are connected DNMEG_V6HXT User Manual www dinigroup com 67 HARDWARE DESCRIPTION directly to the GTH Transceivers Refer to par 3 2 GTX GTH Transceiver Clocks for clocking information P2 5VD P2 5VD o o R673 R678 R677 R674 J34 R676 R675 R672 4 7K 4 7K 4 7K 4 7K BOTTOM TOP 4 7K 4 7K 4 7K QSFP1_TX2n GND GND 28 QSFP1 TXin QSFPi 2 3 Den OSFPT_TXIp 3 1 He QSFP1_TX4n T ae 34 1_ QSFP1 D4j Q j SFP1_LPMODE 8 QSFP1_MODSELn lt lt GSEEt MODSELn 4 8 MODSELn Ha a OSFP1 LPMODE pg18 918 QSFP1_RESETn lt lt P3 3V_QSFPT_VOCRX 10 3 37 29 P3 3V_QSFP1_VCCTX SCL _ 11 3 3v 3 VCCTX H55 pgi8 SCL lt lt SDA Tz SCL OSEE Res 17 SDA lt lt 18 SDA MODPRSn 55 OSFP1 MODPRSn pg18 1 QSFP1_RX3p 14 25 QSFP1_RX4p QSFPi
92. ght click on the FPGA and select the Program option Click in the Device Programming Properties window A Configuration Operation Status box will appear indicating programming progress DNMEG V6HXT User Manual www dinigroup com 19 PROGRAMMING CONFIGURING THE HARDWARE ISE iMPACT 0 76xd Boundary Scan Operations Output Debug Window gt IMPACT Flows ensx 89 Boundary Scan E Systemace E Create PROM File File Formatter E WebTalk Data xeBvhx380t 2 384 bypass bypass IMPACT Processes Available Operations are Program eFUSE Registers gt Read eFUSE Registers gt Set eFUSE Control Register gt Read eFUSE Control Register gt Get Device Signature Usercode gt Read Device Status gt Read Device Boundary Scan Console 3 INFO iMPACT 501 1 Added Device xc2c384 successfully Manufacturer s ID Xilinx xc6vhx380t Version Reading C Xilinx 13 3 ISE_DS ISE virtex6 data xc6vhx380t bsd 32 INFO iMPACT 501 1 Added Device xc6vhx380t successfully Eras dy Warnings Configuration Platform Cable USB 6 MHz usb hs 8 Verify that the DONE blue LED 055 is enabled indicating successful configuration of the FPGA DNMEG V6HXT User Manual www dinigroup com 20 HARDWARE DESCRIPTION l Hardware Description
93. grammable FIFO logic Built in optional error correction circuitry o Optionally use each block as two independent 18 Kb blocks e High performance parallel SelectIO technology 1 2 to 2 5V I O operation DNMEG_V6HXT User Manual www dinigroup com 26 HARDWARE DESCRIPTION Source synchronous interfacing using o ChipSync technology Digitally controlled impedance DCI active termination Flexible fine grained I O banking High speed memory interface support with integrated write leveling capability e Advanced DSP48E1 slices 25 18 two s complement multiplier accumulator Optional pipelining New optional pre adder to assist filtering applications O Optional bitwise logic functionality o Dedicated cascade connections e Flexible configuration options SPI and Parallel Flash interface o Multi bitstream support with dedicated fallback reconfiguration logic o Automatic bus width detection e System Monitor capability on all devices o On chip off chip thermal and supply voltage monitoring access to all monitored quantities e Integrated interface blocks for PCI Express designs o Designed to the PCI Express Base Specification 2 0 o 2 5 Gb s and Gen2 5 Gb s support with GTX transceivers Endpoint and Root Port capable x1 x2 x4 ot x8 lane support per block e GTX transceivers 150 Mb s to 6 6 Gb s transceivers 2 488 Gb s to beyond 11 Gb s e Integrated 10 100 1000 Mb s Ethern
94. hat is connected to 10 lanes of GTH transceivers variety of MSA fiber optic transceiver modules not supplied are compatible to this connector and provide PHYS for 40Gb s and 100Gb s applications The user is required to provide the MAC IP for the 40GbE with QSFP The DNMEG V6HXT has two Quad Small Form Factor Pluggable QSFP connectors Each is attached to 4 lanes of GTH transceivers A variety of QSFP PHYS can be used here creating a single lane of 40GbE or 4 lanes of 1OGbE The user is required to provide the MAC IP for the FPGA 10GbE with SFP The DNMEG V6HXT has four Small Form Factor Pluggable SFP connectors each attached to single lane Again a variety of SFP PHYS be used here with the most popular being 10GbE 10 100 1000 BaseT with SFP Eight SFP connectors are attached to single GTX lane vatiety of SFP PHYS can be used here with the most popular being 1000BaseT Two Serial ATA Ports SATA IT The FPGA has dual SATA II Serial ATA ID connectors attached to GTX With SATA IP integrated into the FPGA logic SATA cables connected can provide additional high speed data paths to off board peripheral GTX Expansion Header Eight lanes of GTX are connected to our standard GTX expansion header purple thing in block diagram Daughter cards such as the DNSEAM_SFP can be used here to add 8 SFP sockets potentially adding 1x 2x 4x Fibre Channel 10 100 1000GbE Ethernet XAUL SA
95. ing specification establishes a standard method of using PCI Express technology over a cable by defining cable connectors copper cabling attributes and electrical characteristics connector retention identification and labeling The board conforms to the PCI Express External Cabling Specification Revision 1 0 enabling high data rates 2 5Gb s between PCI Express subsystems Standard cables and connectors have been defined for x1 x4 x8 and x16 link widths Sideband signaling is provided via the cable to attain compatibility with existing silicon and software this leverages existing software and infrastructure provides ease of use and helps accelerate adoption of the technology See PCI Express External Cabling Specification Rev 1 0 available from PCI SIG for more information The PCI Express Cable Connector supports the following Auxiliary signals CREFCLKp CREFCLEn required Low voltage differential cable reference clock e CPRSNTn required Cable present detect an active low signal provided by a Downstream Subsystem to indicate that it s both present and its power 15 good within tolerance e CPERSTn required Cable PERST an active low signal logically equivalent to system PERSTn platform reset driven by the Upstream Subsystem CPWRON required Cable Power On an active high signal provided Upstream Subsystem to notify slave type Downstream Subsystems to turn their main power on off used for
96. ins Active Cooler Dynatron P N K555 To avoid mechanical stress during shipment the part is not installed on the board please proceed as follows to install the fan heatsink combo 2 1 1 Tools required ESD Safe Assembly Environment e Phillips Screwdriver DNMEG V6HXT User Manual www dinigroup com 11 GETTING STARTED 2 1 2 Assembly Instructions For assembly instructions review the following video http youtu be XENSvaGmCdg 2 2 Before Powering Up the Board Before powering up the board prepare the board as follows 1 Ifthe kit contains Memory UDIMM module populate the UDIMM socket Insert UDIMM DDR3 SDRAM module into posiion 29 P N CT51272BA1339 Note Ensure the VOLT ADJ jumper JP4 is set to 1 5V JP4 pin 1 3 2 Attach an ATX Power Supply to the ATX PWR header J3 3 Connect the RS232 Cable to the RS232 FPGA header J17 2 3 Powering Up the Board 4 Opena Terminal Emulator and configure the session as follows Session Options Serial COM1 Category Connection Logon Actions Serial Terminal Baud rate amp Emulation Modes Data bits Emacs Mapped Keys Advanced Stop bits Appearance Window Log File Serial break length 10 milliseconds Printing Advanced Xi 2 Flow Control CIDIR DSR 5 CI XOn XOFF lt Port Parity lt 5 Power up the board by turning
97. iver Clock Circuit 32 2 Input Connections to the Clock Generator esee erre e ANTH RENS 50 3 2 3 Output Connections between the Clock Buffers and the 50 3 3 PCI Express Cable Reference Clocks HCSL 3 3 3 1 Selecting between Upstream or Downstream Auxiliary Signals 53 33 2 Connection between the PCI Express Jitter Attenuator and the FPGA 53 3 4 SATA IT Clock Oscillator LVDS essen 54 3 4 1 SATA II Clock 54 3 4 2 Connection between SATA II Clock Oscillator and the FPGA 54 3 5 Daughter Card Header Clocks MEG Array 499 3 5 1 Daughter Card Global Clock Input Output 95 3 5 2 Connection between MEG Array Daughter Card Clocks and the FPGA 56 3 5 3 Source Synchronous MEG Array Daughter Card Clocks 4597 3 5 4 Connection between Secondary Clocks and the FPGA 57 3 6 Mezzanine Card 1 a 2299 3 6 1 FMC Differential Reference Clock Requirements 60 3 6 2 Connection between FMC Mezzanine Card Clocks and the FPGA 63 4 HIGH SPEED INTERFACES 63 4 1 Interface T 4 1 1 CFP Circuit m 4 1 2 Connection between CFP Connector and the 65 4 2 O
98. l Name CFP Connector FPGA CFP_PRG_ALRM3 J25 35 34 AK30 CFP_PRG_CNTL1 J25 30 34 AR31 CFP_PRG_CNTL2 25 31 34 AT32 CFP_PRG_CNTL3 J25 32 34 AW31 CFP_MDC_12 J25 48 34 BD30 CFP_MDIO_12 J25 47 34 AM30 4 2 QSFP Interface InfiniBand uses copper CX4 cable for SDR and DDR rates also commonly used to connect SAS Serial Attached SCSI HBAs to external SAS disk arrays With SAS this is known as an SFF 8470 connector and is referred to as an Infiniband style Connector The latest connectors used with QDR capable solutions are QSFP Quad Only one channel shown for simplicity C Rej 15 Rx2 D 15 5 Rx Out rx3 OR E x p 2 55 ASIC SerDes 5 gt 8 Module 8 gt Tx s 4 16 gt E 2 2 2 Tx 1 Two 134 J35 interfaces are provided on the DNMEG HXT The electrical and optical specifications are compatible with those enumerated in the ITU T Recommendation G 957 STM 1 STM 4 and STM 16 Telcordia Technologies GR 253 CORE OC 3 OC 12 and OC 48 Ethernet IEEE 802 3 2005 Fast Ethernet and Gigabit Ethernet InfiniBand Architecture Specifications SDR and DDR or Fibre Channel PI 2 2GFC and 4GFC Electrical and optical specifications may be compatible with standards under development such as Fibre Channel PI 3 and Fibre Channel PI 4 For more in
99. le GEN1 GEN2 e Xilinx Virtex 6 FPGA FF1760 populated with any of the following options 80 3 2 1 fastest to slowest XC6VHX565T 2 1 e GTX Transceiver Interfaces up to 6 6Gbps o Dual PCI Express Cable x4 o Eight SFP x1 Dual SATA II x1 Host Device o x10 Daughter Card HPC DNMEGV6 HXT User Manual www dinigroup com 5 INTRODUCTION SEARAY x8 GTH Expansion Header e Transceiver Interfaces 2 488Gbps to 11Gbps o CFP x10 o Dual QSFP x4 Four SFP x1 SMA x2 Shares a CFP QUAD Tile e FPGA Configuration o Configuration Options USB PCI Express JTAG Stand alone configuration with USB Flash Drive Encryption Readback and Partial Reconfiguration e Flexible Clock Resources FPGA Clock Generator 15338 Clock Network CML Clock Network LVPECL SFP HS LS Clock Network LVPECL PCI Express Clock 100MHz o External Clock LVDS Input via SMA x2 o Multiple clocks from the Daughter Card Header Fixed Oscillator for SATA II 150MHz Clock Test Points x2 e Memory DDR3 SDRAM UDIMM 8GB 1G x 72 240 pin SODIMM PC3 8500 Serial EEPROM 64 8192 x 8 e Daughter Card Headers LVDS MEG Array 400 pin 96 LVDS unidirectional pairs clocks or 192 single ended 550 MHz all signals with source synchronous LVDS Signal voltage set by daughter card 1 2V to 2 5V 12 24W
100. m For technical questions email support dinigroup com DNMEG V6HXT User Manual www dinigroup com 122
101. max and 3 3V 10W max Supplied power rails fused e LCD Display 192 x 64 pixel e User LED s DNMEGV6_HXT User Manual www dinigroup com 6 INTRODUCTION 3 Onboard Distributed Power Supplies support for Embedded Logic Analyzers ChipScope Logic Analyzer Dual RS232 Port for Microcontroller and FPGA 10 pin Header Stand Alone operation requires an external 12V ATX power supply with a ATX Power Connector Package Contents Before using the kit or installing the software be sure to check the contents of the kit and inspect the board to verify that you received all of the items If any of these items are missing contact Dini Group before you proceed The DNMEG_V6HXT Logic Emulation Board kit includes the following USB Flash Drive 4GB USB007 P N UFDCR 4096 UDIMM DDR3 4GB PC3 10600 240 Pin Crucial P N CT51272BA1339 Active Cooler for 20 Server amp Up Dynatron P N 555 or Cable RS232 DB9 Female to DB9 Female 6ft Jameco P N 132346 Cable Straight IDC 10 Pin Socket DB9 Male 18 Cables P N 000 F903 N Customer Support Package on USB Flash Drive o Documentation Datasheets User Manual and Schematics DNMEGV6_HXT User Manual www dinigroup com 7 INTRODUCTION FPGA Reference Designs Verilog Host Software AETest Optional items that support development efforts not provided Xilinx ISE Software Xilinx Platform Cable USB LCD Displ
102. n Table 21 Table 21 Connections between MEG Atray Daughter Card Clocks and the FPGA Signal Name Daughter Card Header TOP Header P1 DCA_CLK_DN_INP_TOP 34 14 DCA_CLK_DN_INN_TOP 34 H13 DCA CLK UP OUTP TOP 34 P15 DCA CLK UP OUTN TOP 34 P14 BOTTOM Header P2 DCA_CLK_DN_INP_BOT 34 AV33 DCA_CLK_DN_INN_BOT 34 AW34 DCA CLK UP OUTP BOT 34 AK35 DCA UP OUTN BOT 34 AL35 DNMEG V6HXT User Manual www dinigroup com 56 HARDWARE DESCRIPTION 3 5 3 Source Synchronous MEG Array Daughter Card Clocks Each Daughter Card IO Bank contains a number of clock capable LVDS pairs _ nets connect to SRCC and MRCC pins on the FPGA while _GCC pins connect to global clock inputs on the FPGA and 15 capable of clocking all signals on the daughter card using synchronous zero hold time timing Note on Virtex 6 this means a GCC pin a SRCC or MRCC pin on banks 36 44 46 45 and 47 see Figure 24 These clocks need to comply with the IO requirements of the Virtex 6 FPGA IO bank they are connected too see schematic for more information 1 2 GCC DN DCA GCC DN B4 B0_P0_GCC_DN DCA P1 BO_NO_GCC_DN DCA B0 1 VREF Be B0_P1 2 B0_N1_VREF 2 0 2 P3 B0 N2 B10 80_ CC Aii 0_ 3 N4
103. ncreases Speed control is accomplished by tachometer feedback from the fan so that the speed of the fan is controlled not just the PWM duty cycle Accuracy of speed measurement is 4 The maximum recommended operating temperature of the FPGA is 85 degrees When the MCU measures the temperature above 80 degrees it will immediately RESET and clear the 2 3 4 Temperature Sensor Circuit Each FPGA is connected to the temperature sensor U24 This sensor measures the temperature of the FPGA silicon die see Figure 15 The maximum recommended operating temperature of the FPGA 15 85 degrees commercial rating When the configuration circuitry measures the temperature of any FPGA above 80 degrees it will immediately un configure the FPGA and prevent it from re configuting DNMEG V6HXT User Manual www dinigroup com 44 HARDWARE DESCRIPTION Paavo con coss Cooling Fan FPGA o uec 22uF 596 Liev tev m 10 10 1 DYNATRON FAN ASSY GER 7 CER zw 7 FAN_TAGH FPGA Rss 1 ale Paavo WM 470593000 Silkscreen R595 Paavo cso Cooling Fan Chassis EI 22uF R301 Liev tev at i 10 1 tebe Temperature Monitor Hono DYNATRON FAN a300 1k TACH CHASSIS
104. ne module starting with the lowest ordinal and used in ascending order when CLK_DIR is connected via a 10K pull up resistor to 3P3V by the mezzanine module Rule 5 24 CLK 0 3 shall use the LVDS signaling standard Rule 5 25 All CLK signals shall be connected to differential logical 0 By the driving source when not connected to a signal The signal shall connect to 0 and the N signal shall connect to 1 Rule 5 26 Clock traces shall provide a differential impedance of 100 10 Rule 5 27 The differential length mismatch on each differential clock pair shall be a maximum 11ps Rule 5 28 The maximum period jitter on CLK 0 3 shall be 115 Rule 5 29 The maximum cycle to cycle jitter on CLK 0 3 shall be 150ps Recommendation 5 5 CLK 0 1 M2C and CLK 2 3 BIDIR when carrier cards support the configuration of CLK_DIR connected to GND or unconnected signals should be connected to optimal pins on the FPGA device residing on the carrier card such as dedicated clock pins Recommendation 5 6 If a mezzanine module has a need for a particular clock performance then it should be generated locally on the mezzanine module Rule 5 30 CLK_DIR shall be implemented as a LVTTL signal Rule 5 31 The Carrier card shall provide a 100K pull down resister signals to GND Rule 5 32 The Mezzanine module shall connect CLK DIR to GND leave unconnected when it is driving a clock on either C
105. ng glue logic board digital signal monitoring and control system bus interface etc into a single integrated solution The Platform Manager provides 12 independent analog input channels to monitor 12 power supplies Up to six general purpose 5V tolerant digital inputs are also provided for miscellaneous control functions There are 16 open drain digital outputs that can be used for controlling DC DC converters low drop out regulators LDOs and opto couplers as well as for supervisory and general purpose logic interface functions 6 2 1 Power Sequencing The Virtex 6 FPGAs have power up requirements refer to the datasheet for the requirements Power sequencing is implemented by the Platform Manager 033 6 2 2 Reset Options A Logic 54 reset from the Platform Manager U33 is directly connected to the FPGA see Table 38 The System 55 reset powers down the power supplies and generates a power ON OFF teset to the board The Platform Manager holds the MCU U26 in RESET until the power supplies are up and stable Table 38 Logic Reset for the FPGA Signal Name Platform Manager FPGA MCU RST_CPLD_LOGN S4 U33 T11 U34 BC34 MCU_RSTN U33 R11 026 14 7 Mezzanine The also known VITA 57 standard was developed to provide an industry standard mezzanine form factor in support of a flexible modular IO interface to an FPGA located on a baseboard or cartier card It allows the physical IO in
106. ng standard used by the bank B data pins HBxx If the signaling standard on Bank does not require a reference voltage then this pin can be left unconnected Note This option is not supported B 2 This voltage is generated by the Mezzanine module and is used as the main voltage to power the IO banks on the FPGA that interface to the Bank B IO pins of the connector Note This option is not supported e PG_C2M Power Good Carrier Card This signal asserts high by the carrier when power supplies VADJ 12POV 3P3V are within tolerance Note This option is not supported pull up with resistor PG M2C Power Good Mezzanine This signal asserts high by the mezzanine module when power supplies VIO_B_M2C VREF_A_M2C VREF_B_M2C are within tolerance Note This option is not supported pull up with resistor 7 4 FMC to FPGA IO Connections Table 39 lists the input output interconnect between the Virtex 6 FPGA and the FMC Mezzanine Card Table 39 FMC to FPGA IO Connections e TN Signal Connector FPGA ANE MART ZEE IET DNMEG V6HXT User Manual www dinigroup com 98 HARDWARE DESCRIPTION ee Signal Name Connector FPGA AR SAT SAR HAS DNMEG_V6HXT User Manual www dinigroup com 99 HARDWARE DESCRIPTION ee Signal Name Connector FPGA HEARD MAI DNMEG_V6HXT User Man
107. ng the FPGA using JTAG Before configuring the FPGA ensure the following steps have been completed 1 Attach an ATX Power Supply to the ATX PWR header J3 2 Connect the Xilinx Platform Cable USB IP to the FPGA CPLD header J30 3 2 Powering Up the Board 3 Power up the board by turning ON the ATX power supply and verify the ATX PWR OK LED 0528 is ON indicating the presence of 12V located at the bottom left side of the board 3 3 Configuring the FPGA To configure the Xilinx perform the following steps 4 Open iMPACT and create a new default project Select Configure devices using Boundary Scan JT AG from the iMPACT welcome menu DNMEG V6HXT User Manual www dinigroup com 18 PROGRAMMING CONFIGURING THE HARDWARE 2 Welcome to iMPACT Please select an action from the list below Configure devices using Boundary Scan JTAG Automatically connect to a cable and identify Boundary Scan chain Prepare a PROM File Prepare a System ACE File Prepare a Boundary Scan File 5 A pop up window will display Device Programming Properties Device 1 Programming Properties Click to select default options 6 Right click on FPGA and select Assign New Configuration File Specify the location for the FPGA bit file based on the type of FPGA populated e g XC6VHX380T a pop up window will display Attach SPI or BPI PROM Click to proceed 7 Ri
108. ntation is provided for XLAUI OTL4 10 DNMEG_V6HXT User Manual www dinigroup com 63 HARDWARE DESCRIPTION OTL3 4 and STL256 4 electrical interface specifications The CFP module may be used to support single mode and multimode fiber optics CFP MSA is an acronym for 100G1 Form factor Pluggable Multi Source Agreement For more information reference the CFP MSA Hardware Specification 4 1 1 Circuit The CFP module and the host system are hot pluggable The module or the host system shall not be damaged by insertion or removal of the module The CFP control signals are routed through the Platform Manager U33 for level translation from 2 5V to 1 2V Refer to pat 3 2 GIX GTH Transceiver Clocks for clocking information PL2VD REFCLKp R573 DNI 49 9R 2 CLK REFCLKp E pg2 REFCLKn amp n ONI 49 9R P3 3VF_CFP o J25 BOTTOM TOP 4 GND GND 7 3 3V GND REFCLKn 3 3V GND REFCLKp 9 3V_GND GND CFP_S1_REFCLKn R582 NI 6 3 3 _ GND S1_REFCLKn CFP_S1_REFCLKp R583 NI 7323V 81 REFCLKp 3 3V GND
109. odule specific timing parameters configuration information and physical attributes User specific information can be 33 DNMEG V6HXT User Manual www dinigroup com HARDWARE DESCRIPTION written into the remaining 128 bytes of storage READ WRITE operations between the system master and the EEPROM slave device occur via a standard I2C bus using the DIMN s SCL clock and SDA data signals together with SA 2 0 which provide four unique DIMM EEPROM addresses Write protect WP is connected to Vss internal to the Temp Sensor EEPROM permanently disabling hardware write protection Please note that VDDSPD is connected to 3 3V Table 6 Serial Presence Detect EEPROM Connections Signal Name FPGA DDR3 UDIMM DIMM_SAO 129 117 pull down R604 DIMM_SA1 U34 G17 29 237 pull down R605 DIMM_SA2 129 119 pull down R175 DIMM_SCL U34 AT35 729 118 pull up R174 DIMM_SDA U34 AU35 729 238 pull up R172 1 4 7 Clocking Connections between FPGA and UDIMM The clocking connections between the FPGA and the UDIMM connector are shown in Table 7 Table 7 Clocking Connections between FPGA and the UDIMM Connector Signal Name FPGA UDIMM DIMM_CKOP U34 N22 J29 184 DIMM_CKON U34 N21 J29 185 DIMM CKIP U34 M24 J29 63 DIMM_CK1N U34 M25 J29 64 1 4 8 Connections between FPGA and UDIMM Table 8 shows the connections between the FPGA and the UDIMM connector pins Table 8 Connections between FPGA and the UDIMM Connect
110. or DNMEG_V6HXT User Manual www dinigroup com 34 HARDWARE DESCRIPTION CICI ala DNMEG_V6HXT User Manual www dinigroup com 35 HARDWARE DESCRIPTION DIMM_DM4 34 19 DIMM_DM5 34 D20 DIMM_DM6 34 18 CICI 34 29 34 27 MKT ee DNMEG_V6HXT User Manual www dinigroup com 36 HARDWARE DESCRIPTION DNMEG_V6HXT User Manual CICI ala 34 20 34 820 34 20 34 22 34 A22 34 G22 34 F22 34 C27 34 R23 34 R22 34 R21 34 P21 34 F20 34 E20 34 K21 34 20 34 C18 34 C17 34 28 34 H17 34 16 34 19 34 N19 34 F19 34 F18 34 J16 34 K18 34 17 34 117 34 N26 34 N16 34 M16 J J29 201 J29 206 J29 207 J29 122 J29 97 J29 209 J29 210 J29 215 J29 216 J29 99 29 100 J J29 123 J29 105 J29 106 J29 108 J29 109 J29 114 www dinigroup com 37 HARDWARE DESCRIPTION DNMEG_V6HXT User Manual CICI ala c CICI O Z O Z O U34 D18 U34 K16 www dinigroup com UDIMM 29 233 29 234 29 129 29 12 29 13 29 29 15 29 16 29 24 29 25 29 33 29 34 29 84 29 85 29 93 29 94 29 102 29 103 29 111 29 112 29 42 29 43 29 187 29 135 29 126 29 144 29 48 29 153 29 49 29 162
111. oup com 116 HARDWARE DESCRIPTION DNMEG V6HXT User Manual www dinigroup com 117 HARDWARE DESCRIPTION 8 7 MEG Array Specifications Manufacturer Part Number RoHS Lead Free Compatible Total Number Of Positions Contact Area Plating Mating Force Unmating Force Insulation Resistance Withstanding Voltage Current Rating Contact Resistance Temperature Range Trademark Approvals and Certification Product Specification Pick up Cap Housing Material Contact Material Durability Mating Cycles DNMEG_V6HXT User Manual FCI 74390 101LF Bottom Receptacle P2 84520102LF Top Plug P1 yes 400 0 76 um 30 uin gold over 0 76 um 30 pin nickel 30 grams per contact average 20 grams per contact average 1000 M ohms 200 VAC 0 45 amps 20 to 25 m ohms max initial 10 m ohms max increase after testing 40 C to 85 MEG Array UL and CSA approved GSe 12 100 from FCI websit yes LCP Copper Alloy 50 www dinigroup com 118 HARDWARE DESCRIPTION 9 Mechanical 9 1 Board Dimensions The DNMEG V6HXT Logic Emulation Board measures 334mm x 286 5mm The maximum component height is determined by the FPGA heatsink fan combo measured at 70mm Note A passive heatsink solution is available for rack mounted applications Two bus bats MP1 MP2 ate installed to prevent flexing of the PWB The mounting holes are connected to the ground plane and can be used to
112. own in Table 10 DNMEG_V6HXT User Manual www dinigroup com 39 HARDWARE DESCRIPTION Signal Name Table 10 Connections between FPGA and the EEPROM FPGA EEPROM PROM_SCL U34 AP35 U23 6 PROM_SDA U34 AR35 U23 5 PROM_AO R391 PROM A1 R392 PROM A2 R393 1 6 RS232 Port RS232 serial port 029 is provided for low speed communication with the Virtex 6 FPGA and the MCU The LTC2804 is a dual RS 232 transceiver in narrow SSOP and chip scale DEN package An integrated DC to DC converter generates power supplies for driving RS 232 levels A logic supply pin allows easy interfacing with different logic levels independent of the DC DC supply Part is compatible with the TIA EIA 232 F standatd 1 6 1 RS232 Circuit Diagram Figure 10 shows the implementation of the serial port RS232 MCU J22 1 2 363 42 27 5 029 2 1 Lg FPGA 14 3 RS232 DD1 9 10 MCU_TXDO HUN TOUT 4 89232 TXD2 bg d MCU TXDO lt lt T2OUT TSM 136 01 T DV FPGA RXD 16 1 RS232 RXD1 AYDO RIOUT 15 2 n 5 1 2 P2 5VD vee P2 5VD i 9 5 6 y R461 4 7K RS232 ON GEE ent RS232 SW d cap 10 BS232 CAP C168 022 10uH C176 x LOH2MCN100K02L 1uF 5 136 01 yoo
113. popular being 10GbE 10 100 1000 BaseT with SFP Eight SFP connectors are attached to single GTX lane vatiety of SFP PHYS can be used here with the most popular being 1000BaseT Two Serial ATA Ports SATA IT The FPGA has dual SATA II Serial ATA ID connectors attached to GTX With SATA IP integrated into the FPGA logic SATA cables connected can provide additional high speed data paths to off board peripheral GTX Expansion Header Eight lanes of GTX are connected to our standard GTX expansion header purple thing in block diagram Daughter cards such as the DNSEAM_SFP can be used here to add DNMEG_V6HXT User Manual www dinigroup com 23 HARDWARE DESCRIPTION 8 SFP sockets potentially adding 1x 2x 4x Fibre Channel 10 100 1000GbE Ethernet XAUL SATA ot Serial RapidI O to the mix All or any subset of the above interfaces high speed serial interfaces can be used simultaneously Two GTH channels are connected to high speed SMAs DDR3 Bulk Memory A single PC3 8500 DDR3 UDIMM socket enables up to 16GB plus ECC of memory for bulk storage and lookup With a 16GB UDIMM memory stick the configuration is 2048M x 72 Using a 2 or 3 speed grade FPGA this interface is tested at the maximum FPGA IO frequency 533 MHz 1066 Mb s with DDR You ate welcome to use this memory as 64 bits with 8 bits of error correction ECC or as 72 bit memory without correction This is the same UDIMM interface used in our blockbuster DNPCIe 106
114. r 5 aav P N pro 2 gu nop Silkscreen mp 1 2 FAN FGA silkscreen FAN FPGA DXN lt lt 1 FAN 02 ud 4 FAN TACH CHASSIS pg4 19 29 FPGA SD lt lt SOL ili DM 04 19 29 FPGA SCLKK SCLT 186 CC 14 e PQSVD Pasvp 5 z FANE H R549 R563 10 8 TEMP CF 200R UOGEGNCSOPIE x bat FAN ALERT 5 L MAXGGSSAEE T Lea pot FAN THERME P25VD P25VD Address 0101 111 0x5E 2 50 Address 0101 111 0x5E R564 5 R562 47K pos C FAN FAT pg4 FAN_FAILn lt lt ENEN Figure 15 FPGA Temperature Sensor 2 3 2 Connection between the MCU and the Temperature Sensor The connection between the MCU U26 and the Temperature Sensor U42 are shown in Table 15 Note that the temperature sensor can be read by the MCU U26 FPGA U34 or the Platform Manager U33 Table 15 Connection between MCU and the Temperature Sensor Signal Name Temp Sensor MCU FPGA PM FPGA_MCU_SD1 U42 15 U26 37 U34 AH32 U33 M2 FPGA_MCU_SCL1 U42 16 U26 38 U34 AH33 U33 N2 2 4 Emulation and Debugging Standard JTAG test debug interface as well as Serial Wire Debug and Serial Wire Trace Port options ar
115. r and the FPGA Table 5 Connection between JTAG Header and the FPGA Signal Name Header FPGA 30 6 gt 051 9 U34 AB12 JIAG_FPGA_TDI 730 10 U34 AF12 JTAG_FPGA_TDO 730 8 U34 Y12 JTAG_FPGA_TMS J30 4 gt 051 18 U34 AD12 Note The TMS and TCK signals are buffered before being distributed to the CPLD and FPGA 1 4 DDR3 Memory UDIMM A 240 pin UDIMM module connected to the Virtex 6 FPGA allows addressing for up to 16GB DDR3 SDRAM PC3 8500 modules The following transfer speed can be expected Speed Grade 3 1066Mb s Speed Grade 2 1066Mb s DNMEG V6HXT User Manual www dinigroup com 30 HARDWARE DESCRIPTION Speed Grade 1 800Mb s The UDIMM interface is connected to IO Banks on the Virtex 6 FPGAs and uses a 1 5V switching power supply for and Vecio and are powered from a separate linear power supply set at 0 75V DDR3 SDRAM modules ate available from Micron example part number for a 8GB 1Gb x 72 240 pin UDIMM SDRAM module is MT18KSP1G72AZ 1G4D1 141 DDR3 SDRAM Memory Interface Solution The Virtex 6 FPGA memory interface solutions core is a pre engineered controller and physical layer PHY for interfacing Virtex 6 FPGA user designs to DDR2 and DDR3 SDRAM devices Figure 6 shows a high level block diagram of the Virtex 6 FPGA memory interface solution connecting a user design to a DDR2 or DDR3 SDR
116. rated for 750W see Antec EarthWatts Series EA 750 P N N82E16817371051 DNMEG V6HXT User Manual www dinigroup com 93 HARDWARE DESCRIPTION Figure 32 Power Supply 6 1 1 External Power Connector Figure 33 indicates the connections to the external power connector J3 This header is fully polarized to prevent reverse connection and is rated for 600V AC at per contact Jumper J33 must be installed for the ATX Power Supply to turn ON TP6 1 P3 3V_ATX i ae Sexo P3 3V_ATX P5 0V ATX T 9 C503 C505 E 150uF 0 1 1 5 16V 16V TP 20 20 1 TANT TP7 PWR_OK 1 P12V 2 PS 0V_ATX Sexo 1 1 P5 0V_ATX C501 C506 3 C504 c21 150uF 0 10 150uF 0 1 16V 16V 16V 16V 20 20 20 20 TANT TANT 39 29 1248 533 PS ONn 1 22 23 2023 Note Install jumper to EG power on ATX Supply 90120 0122 Figure 33 External Power Connection Note Header J3 is not hot plug able Do not attach power while power supply is ON DNMEG V6HXT User Manual www dinigroup com 94 HARDWARE DESCRIPTION 6 2 Voltage Monitors and Reset The Lattice Platform Manager LPTM10 12107 integrates board power management hot swap sequencing monitoring reset generation trimming and margining and digital board management functions reset tree non volatile error loggi
117. rom Digi Key P N CR1220 1 7 1 Backup Battery Circuit The recommended battery voltage is specified at 1 0V to 2 5V The TPS782 low dropout regulator LDOs offers the benefits of ultra low power 10 see Figure 11 P3 3VD R55 DNI OR TP23 _ 1 BAS40 05 SOT23 P_VBATT P2 5V_VBATT bi U18 GND 3 P_VBATT 1 5 P2 5V VBATT c85 IN OUT 4 5585 2 2uF 3 2 2uF j VBATT 1 2 VBATT_EXT 20 2 4 20 ie p lt 17 T ER GND GND pi m 978225 50123 5 D3 BAS40 05 SOT23 TPS78225DDCR ra Bn Der 3001 90120 0122 Silkscreen VBATT EXT Accepts 3V Lithium CR1220 1 Figure 11 Backup Battery Supply 1 7 2 Backup Battery Loads The backup battery supplies the following loads see Table 12 Table 12 Backup Battery Load Signal Name Load Description P2 5V_VBATT U34 AA13 FPGA encryption supply 1 8 VCCINT Switching Power Supply A distributed point of load POL power supply topology is implemented utilizing the PTHO8T250W is a high performance 50 A rated non isolated power module operating DNMEG_V6HXT User Manual www dinigroup com 41 HARDWARE DESCRIPTION from an input voltage range of 4 5 V to 14 V The PTHO8T250W requires a single resistor R671 to set the output voltage to 1 0V see Figure 12 TLPLOVD Ri02 187K TP28 1 P12V P1 0V_VCCINT 21 0 VC
118. roup using this e mail address support dinigroup com Phone Support Call us at 858 454 3419 during the hours of 8 00am to 5 00pm Pacific Time FAQ The download section of the web page may contain a document called MEG_V6HXT Frequently Asked Questions FAQ This document is periodically updated with information that may not be in the User s Manual DNMEGV6_HXT User Manual www dinigroup com GETTING STARTED Getting Started Congratulations on your purchase of the DNMEG_V6HXT Logic Ezutaton Board The remainder of this chapter describes how to start using the DNMEG_V6HXT Lo Emulation Board 1 Before You Begin 1 1 Configuring the Programmable Components The DNMEG V6HXT has been factory tested and pre programmed to ensure correct operation The user does not need to alter any jumpers or program anything to see the board work 1 2 Warnings e Test Headers Over Voltage The test headers are NOT 3 3V tolerant These signals connect directly with the FPGA IO Take care when handling the board to avoid touching the components and daughter card connections due to ESD e Mechanical Stress Board stiffeners are provided to reduce mechanical stress however inserting and removing Daughter Cards may add additional stress that may cause boatd failures e ESD Warning The board is sensitive to static electricity so treat the PCB accordingly The target markets for this product are engineers that are familiar wi
119. rs or tied directly to ground or VCC CONFIG see Figure 4 The mode pins should not be toggled during and after configuration The mode pins can also be driven by the Microcontroller MCU in Slave SelectMAP mode The mode pins should not be toggled during and after configuration In Slave SelectMAP mode the FPGA is configured via the Microcontroller The mode pins can also be driven by the MCU see Figure 4 1 3 1 Mode Select Resistors M 2 0 The specific configuration mode is selected by setting the appropriate level on the dedicated Mode input pins M 2 0 configuration pins P2 5VD Figure 4 Mode Select Resistors M 2 0 default Slave DNMEG V6HXT User Manual www dinigroup com 28 HARDWARE DESCRIPTION Select the configuration scheme by driving the FPGA M 2 0 pins either HIGH or LOW as shown in Table 3 Table 3 FPGA Configuration Schemes Configuration Mode Configuration Resistors Slave SelectMAP R514 R524 R509 Installed JTAG R514 R532 R500 Installed 1 3 2 In System Programming using a Microcontroller MCU The NXP LPC1754 Microcontroller U26 is connected to the SelectMAP interface on FPGA U34 with a dedicated 8 bit bidirectional data bus This allows for faster data transfer during configuration or readback CCLK is an input in Slave SeleccMAP mode and is sourced from the MCU Table 4 shows the SelectMAP bus connection between the Microcontroller and the
120. rtex 6 HXT FPGAs from Xilinx The DNMEG V6HXT is configured with a Xilinx Virtex 6 HXT family FPGA in the FFG1923 package This package supports 720 IOs and all are utilized The HXT FPGAs contain high speed transceiver of two different types GTX transceivers ate capable of handling data rates of 150 MB s to 6 5 Gb s making these useful for lower speed Ethernet Serial ATA and GEN1 GEN2 PCI Express The transceivers are tuned higher 2 48 to 11 18 Gb s making them applicable to 10 gigabit Ethernet 10 GbE Two possible FPGAs be stuffed XC6VHX380T the DNMEG V6HXT User Manual www dinigroup com 1 INTRODUCTION XC6VHX565T The XC6VHX380T comes in three speeds grades with 3 being the fastest The larger XCOVHX565T is limited to the 2 speed grade This means the smaller device can be clocked at a higher frequency at the cost of slightly fewer FPGA logic resources The XC6VHX565T is capable of handling gt 4M ASIC gates of logic and is among the largest of the FPGAs shipping from any vendor in 2011 Features of the 6 HXT FPGAs include the efficient dual register 6 input look up table LUT logic 18 Kb 2 x 9 Kb block RAMs and second generation DSP48E1 slices includes 25 x 18 multipliers Floating point functions can be implemented using these DSP slices Network Prototyping with FPGAs at the High End 40GbE 100GbE with CFP Module The DNMEG V6HXT hosts a single C Form factor pluggable CFP module t
121. rvice provider transport applications SFP is defined as Small Form Factor Pluggable standard by the SFP MSA and is most commonly used for 10 Gigabit Ethernet or 10 Gigabit Fiber Channel applications The SFP modules are hot pluggable Hot pluggable refers to plugging in or unplugging a module while the host board is powered Due to routing losses in the printed circuit board utilizing 10GSFP Cu over copper is limited recommend SFP Direct Cable 10GbE Copper 1 6ft Amphenol P N SF SEPPZEPASS 000 5 Please note the limitation in operating frequency due to Xilinx Virtex 6 clocking limitations see DS152 6 FPGA Data Sheet DC and Switching Characteristics for more information y PLL Output Divider 1 11 182 10 32 Gb s rM put 11362 1082 Gb Output 1 9 92 9 02 9 92 Gb s MnimumGTHtanecovordem rae 002 os 052 65 PLL Output Divider 4 2 48 4 4 1 SFP Pin Assignments The SFP pin assignments are listed in Table 26 Table 28 SFP Pin Assignments Pin Description Number 1 Transmitter Ground 2 Transmitter Fault Indication DNMEG_V6HXT User Manual www dinigroup com 76 HARDWARE DESCRIPTION Pin Symbol Description Number Disable Transmitter Disable SDA 2 wire Serial Interface Data Line Same as MOD DEF2 in INF 80741 SCL 2 wire Serial Interface Clock Same as MOD DEF 1 in INF 80
122. s limited to the 2 speed grade This means the smaller device can be clocked at a higher frequency at the cost of slightly fewer logic resources The XC6VHX565T is capable of handling gt 4 gates of logic and is among the largest of the FPGAs shipping from any vendor in 2011 Features of the 6 HXT FPGAs include the efficient dual register 6 input look up table LUT logic 18 Kb 2 x 9 Kb block RAMs and second generation DSP48E1 slices includes 25 x 18 multipliers Floating point functions can be implemented using these DSP slices Network Prototyping with FPGAs at the High End 40GbE 100GbE with CFP Module The DNMEG V6HXT hosts a single C Form factor pluggable CFP module that is connected to 10 lanes of GTH transceivers A variety of CFP MSA fiber optic transceiver modules not supplied are compatible to this connector and provide PHYS for 40Gb s and 100Gb s applications The user is required to provide the MAC IP for the FPGA 40GbE with QSFP The DNMEG_V6HXT has two Quad Small Form Factor Pluggable QSFP connectors Each QSFP is attached to 4 lanes of GTH transceivers A variety of QSFP PHYS can be used here creating a single lane of 40GbE or 4 lanes of 1OGbE The user is required to provide the MAC IP for the FPGA 10GbE with SFP The DNMEG_V6HXT has four Small Form Factor Pluggable SFP connectors each attached to single lane Again a variety of SFP PHYS can be used here with the most
123. ss Channel 1 2 SATA II Oscillator 150MHz e External Clock LVDS Input via SMA x2 e Daughter Card Header Clocks MEG Array o DCA CLK DN IN P N TOP o DCA CLK UP OUT P N TOP o DCA CLK DN IN P N BOT o DCA CLK UP OUT P N BOT FMC Mezzanine Clocks o CLKO GBT M2C P N o M2C P N 3 2 GTX GTH Transceiver Clocks The 515338 is a high performance low jitter clock generator capable of synthesizing any frequency on each of the device s four output drivers This timing IC is capable of replacing up to four different frequency crystal oscillators or operating as a frequency translator Using its patented MulaSynth technology the 15338 allows generation of four independent clocks with 0 ppm precision Each output clock is independently configurable to support various signal formats and supply voltages The 515338 provides low jitter frequency synthesis in a space saving 4 x 4 mm package The device is programmable via an I2C SMBus compatible serial interface and supports operation from a 1 8 2 5 or 3 3 V core supply I2C device programming is made easy with the ClockBuilder Desktop software available at www silabs com ClockBuilder 3 2 1 GTX GTH Transceiver Clock Circuit Each one of the four clock outputs from the 515338 047 is connected to LVPECL buffer that in turn provides clock sources to the GIX GTH Transceivers CFP QSFP DNMEG_V6HXT User Manual www dinigroup com 49 HARDWA
124. t are assigned for clock signals which driven either by the IO Mezzanine Module the cartier card CLK_DIR Used to determine whether the mezzanine module or the cartier card is the driver for CLK 2 3 GBTCLK0_M2C_P N GBTCLK1 M2C P N A differential pair shall be used as reference clock for the DP data signals DNMEG_V6HXT User Manual www dinigroup com 59 HARDWARE DESCRIPTION 3 6 1 Differential Reference Clock Requirements There ate four reference clocks which have a bus between the carrier card and the IO mezzanine module The clocks can have two configurations 1 When CLK_DIR is connected to GND or unconnected on the mezzanine module then CLK 0 1 M2C P N CLK 2 3 BIDIR_P N are four differential pairs that are assigned for clock signals which are driven from the IO Mezzanine Module to the carrier card DNMEG HXT FMC Connector input FPGA input 2 When is connected to a 10K pull up resistor on the mezzanine module then CLK 0 1 M2C P N are two differential pairs that are assigned for clock signals which are driven from the IO Mezzanine Module to the cartier card and CLK 2 3 BIDIR P N two differential pairs that ate assigned for clock signals which are driven from the carrier card DNMEG_HXT to the IO Mezzanine Module DNMEG V6HXT User Manual www dinigroup com 60 HARDWARE DESCRIPTION FMC ea
125. ter Header IO Connectiohs aa ena enr en tio draps ana dracone tro rii cione tronc INTRODUCTION Introduction This User Manual accompanies the DNMEG_V6HXT Logic Board For speajtc information regarding the alie Virtex 6 parts please reference the datasheet on the Xilinx website 1 DNMEG V6HXT LOGIC Emulation Kit Overview The DNMEG V6HXT is a complete network interface solution featuring high speed serial IOs The DNMEG_V6HXT can be used stand alone without hosting contact factory for chassis options if required hosted by 8 lane PCIe cable GEN1 GEN2 plugged into ASIC Prototyping boards from the DINI product line as an expansion peripheral FPGA configuration and other miscellaneous board functions are controlled by the NXP LPC1754 ARM based microcontroller including the front panel LCD A single DNMEG V6HXT configured with the Xilinx Virtex 6 XCOVHXT565T FPGA can emulate up to 4 million gates of logic as measuted by a reasonable ASIC gate counting standard This gate count estimate number does not include embedded memories and multipliers resident in each FPGA One hundred percent 100 of the FPGA resources are available to the user application but the user s application must include all necessary MACs and the PCIe Bridge The DNMEG V6HXT achieves high gate density and allows for fast target clock frequencies by utilizing FPGAs from Xilinx s 40nm Virtex 6 HXT family Vi
126. terface to be decoupled from the FPGA design while maintaining a close coupling between a physical IO interface and an FPGA 7 1 Clocking A High Pin Count single width 69 mm x 76 5 mm connector 8 with 400 pins is provided on the board Refer to par 3 6 FMC Mezzanine Card Clocks for clocking information 7 2 FMC Pin Assignments Refer to the FMC Specification AV57DOT1 R2010 for more information pin assignments DNMEG_V6HXT User Manual www dinigroup com 95 HARDWARE DESCRIPTION JO OBUUOD Od 2d1 I 212 ejoa 212 QNO Nav devi __ S5 E Non No Nemi devi Now devi Now 4591 dev QNO ano Nozw dd d OCW 6 I Odd __ 2 J0199uu02 2d1 wow dem ono m mo omo mo aw zi f
127. th FPGAs and circuit boards However if needed the following web page has an excellent tutorial on the Fundamentals of ESD for those of you who are new to ESD sensitive products http en wikipedia org wiki Electrostatic_discharge 1 3 Exploring the Customer Support Package The USB Flash Drive contains the following items see Figure 2 DNMEG V6HXT User Manual www dinigroup com 10 GETTING STARTED Daughtercards Documentation SN FPGA Reference Designs Figure 2 USB Flash Drive Directory Structure A description of the USB Flash Drive directory contents is listed in Table 1 Please visit the Dini Group website for the most recent revision of these documents Table 1 USB Flash Drive Directory Contents USB Flash Drive Directory Contents Directory Name Description of Contents Daughtercards Contains the documentations for the DNMEG_OBS Test Daughter Card Documentation Contains the Datasheets User Manual and Schematics for the board FPGA Reference Designs Contains source and compiled programming files for the DNMEG V6HXT reference designs 2 Board Setup The instructions in this section explain how to install the DNV6 HXT Logic Emulation board For the purpose of this demonstration the DNV6 HXT will be configured in Stand Alone mode connected using the RS232 Interface 2 1 Installing the FPGA Cooler In order to provide cooling for the FPGA the kit conta
128. ual www dinigroup com 100 HARDWARE DESCRIPTION ee Signal Connector FPGA ma DNMEG_V6HXT User Manual www dinigroup com 101 HARDWARE DESCRIPTION a Sienal Name Connector FPGA EAN DNMEG_V6HXT User Manual www dinigroup com 102 HARDWARE DESCRIPTION ES ee Signal Name Connector FPGA SAKE A HARD SANDS ANAA BAA DNMEG_V6HXT User Manual www dinigroup com 103 HARDWARE DESCRIPTION ES e Signal Name Connector FPGA TENES ZEE AMAA SEANAD SCANS AST ARS MATH DNMEG V6HXT User Manual www dinigroup com 104 HARDWARE DESCRIPTION umama Signal Name Connector FPGA 8 MEG Array Daughter Header The 400 pin MEG Array connector P1 P2 is used to interface to Dini Group products e g DNMEG_AD DA The daughter card header provides a dedicated global LVDS input clock from daughter card connected capable pins on the FPGA and a dedicated global LVDS output clock input to daughter card In addition each IO bank provides a source synchronous LVDS clock that connects to the FPGA Other connections on the daughter card connector system includes two dedicated differential clock connections for global clocks power connections bank Veco power and a reset signal 8 1 Daughter Card clocking Ref
129. uestionable option Also the total DNMEGV6_HXT User Manual www dinigroup com 3 INTRODUCTION number of IOs in the specification is much too small But there are some good A D and D A cards that adhere enough to the specification to be useful Easy Configuration via PCIe USB or Ethernet Configuration of the FPGAs is under the control of an embedded CPU an ARM based LPC1754 from NXP Xilinx is not nice enough to supply a serial PROM large enough to configure the 565 so we need to use rather exotic methods to create enough onboard EEPROM storage for this function Status LEDs Debug As with all of our ASIC emulation boards DNMEG V6HXT is loaded with LEDs The LEDs are stuffed in several different colors red green blue orange et al Blinking these LEDs in a controlled fashion can confuse a trout While this is unlikely to be fatal to the little fish make sure an adult is present and wear eye protection when testing this feature These LEDs are user controllable from the FPGAs so can be used as visual feedback in addition to the task of distracting fish JTAG connector provides an interface to ChipScope Veridae and other third party debug tools DNMEGV6_HXT User Manual www dinigroup com 4 INTRODUCTION 2 DNMEG V6HXT Logic Emulation Board WB c PES 9 Figure 1 DNMEG_V6HXT Logic Emulation Board e Stand alone or hosted via PCI Express Cab
130. ution for addressing the needs of high performance logic designers high performance DSP designers and high performance embedded systems designers with unprecedented logic DSP connectivity and soft microprocessor capabilities For more information please reference the Xilinx Virtex 6 documentation DNMEG V6HXT User Manual www dinigroup com 25 HARDWARE DESCRIPTION 1 2 Summary of Virtex 6 FPGA Features e Three sub families o Virtex 6 LXT FPGAs High performance logic with advanced serial connectivity Virtex 6 SXT FPGAs Highest signal processing capability with advanced serial connectivity o Virtex 6 HXT FPGAs Highest bandwidth serial connectivity Compatibility across sub families o LXT and SXT devices are footprint compatible in the same package e Advanced high performance FPGA Logic o Real 6 input look up table LUT technology Dual LUT5 5 input LUT option LUT dual flip flop pair for applications requiring rich register mix o Improved routing efficiency 64 bit or 32 x 2 bit distributed LUT RAM option o SRL32 dual SRL16 with registered outputs option e Powerful mixed mode clock managers MMCM MMCM blocks provide zero delay buffering frequency synthesis clock phase shifting input jitter filtering and phase matched clock division e 36 Kb block RAM FIFOs Dual port RAM blocks Programmable o Dual port widths up to 36 bits o Simple dual port widths up to 72 bits o Enhanced pro
131. wer and Reset The 12V and 3 3V power rails can be supplied by the daughter card header if the fuses are installed refer to Figure 38 Each pin on the MEG Array connector is rated to tolerate 1A of current without thermal overload DNMEG_V6HXT User Manual www dinigroup com 108 HARDWARE DESCRIPTION DCA CLK DN INp TOP E1 918 DN INp TOP lt lt n F1 918 DCA DN INn TOP lt lt DCA UP OUTp TOP 8 DCA UP OUTp CIK UP OUT 918 UP OUTn TOP X amp 24 DCA lt lt K20 C27 2 2uF 6 3V UP 1 1 12 _ P12VFUSED 3 DN 25 lt 12V 12 _ pg24 P5 0V_ATX CLK UP 2 5 P RSVD 1 P REVO 3 UP 2 5 gt RSVD PWR P RSVD pg24 i P3 3VD VCCO_CAP P3 3VEUSED DC 3 3V 3 3V 42 5V LDO R16 10K DCA RSTn RSTn 3 8 TOLERANT CONN MEGAI 84520102LF RRAY 84520 102LF Figure 38 Daughter Card Header Power amp RESET 1 N j amp P3 3VFUSED pg24 0486005 RSTn signal is routed from the under voltage reset monitor U5 The signal is used to hold the Veco power supplies inactive until the 2 5V supply is sta
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