PowerDNA DIO-416 Solenoid Drive Output Layer User Manual
Contents
1. if DORdCfg devmod i printf Model Sx Option x n DQRdCfg gt devmod i DQRdCfg option i else break for 1 0 i lt 16 i if ret DqAdv416SetLimit hd0 DEVN i OVERCURRENTLIMIT lt 0 printf nError in DgqAdv416SetLimit error found 1 goto finish up for i 16 i lt 32 itt if ret DqAdv4l6SetLimit hd0 DEVN i UNDERCURRENTLIMIT lt 0 printf nError in DqAdv416SetLimit error found 1 goto finish up J en FOR PaO RR SR RRP Sg eae oa FBR ee ne are E OPTIONAL PART get all possible data from the 416 if ret DqAdv416GetAll hd0 DEVN amp data416 double float416 0 printf nError in DqAdv416GetAl1 error found 1 goto finish up printf cfg S08x n data416 cfg disconnection mode configuration printf port0out 08x n data416 port0out last value written to the output printf adcsts 08x n data416 adcsts ADC status and speed selected printf port0ocs 08x n data416 port0ocs Overcurrent status printf port0ucs 08x n data416 port0ucs Undercurrent status printf rdcent 08x n data416 rdcnt of successive reads before failure detected printf adcdata0 08x n data416 adcdata0 User selected ADC conversion result low side printf adcdatal 08x n data416 adcdatal User selected ADC conversion result high side printf disdiv S08x n data416 disdiv Divider fo2. Low Side sse em 10 Chapter 2 Programming with High Level API sseeeeeeeeeene 12 None Chapter 3 Programming with Low Level API 000 c eee e ee eee eee eee 14 None AppendbcA nr teas a e m Medea de had Ata eae erudire Rd 19 None Chapter 1 1 4 Organization of this manual 1 1 1 Introduction 1 1 2 The DIO 416 Layer 1 1 3 Programming with the High Level API 1 4 4 Programming with the Low Level API Appendix A Accessories Index DNA DIO 416 Layer Chapter 1 Introduction Introduction This document outlines the feature set and use of the DNA DIO 416 digital output layer when used with the PowerDNA I O Cube This PowerDNA DIO 416 User Manual is organized as follows This chapter provides an overview of PowerDNA DNA DIO 416 Solenoid Inductive Load Drive Output board features accessories and what you need to get started This chapter provides an overview of the device architecture connectivity and logic of the DNA DIO 416 layer This chapter provides a general description of the how to create a session configure the session for solenoid drive output and format relevant data This chapter describes Low level API commands for configuring and using the DNA DIO 416 layer and contains an example of code written for a typical application This appendix describes the accessories available for use with the DNA DIO 416 layer This is an alphabetical listin
3. WARNING DO NOT USE PRODUCTS SOLD BY UNITED ELECTRONIC INDUSTRIES INC AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS Products sold by United Electronic Industries Inc are not authorized for use as critical components in life support devices or systems A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness Any attempt to purchase any United Electronic Industries Inc product for that purpose is null and void and United Electronic Industries Inc accepts no liability whatsoever in contract tort or otherwise whether or not resulting from our or our employees negligence or failure to detect an improper purchase Table of Contents Chapter 1 Introduction s eiee a eel y bee RR RR ae ee es 1 1 1 Organization of this manual llle 1 1 1 1 INtrODUCHION Pc 1 1 1 2 The DIO 416 Layer lssssslsseslll s 1 1 1 3 Programming with the High Level API 0 000 eee eee eee 1 1 1 4 Programming with the Low Level API 00 0 c eee ee eee eee 1 1 2 The DIO 416 Layer 2 0 0 6c de ee eee eee 3 1 3 Features exten er ek ke eren erg ee Pe a ae qd a 5 1 4 Device Architecture coss Wee oS VERAT pa Qu EPAGMEUERETIUPERA diate 6 1 5 Layer Connectors and Wiring llsseeeee rn 7 1 6 QUTPUE CIFCUIIS fica ces este Bac PEORES
4. Block Diagram HIGH SIDE OUTPUTS Optoisolators 32 bit 66 MHz bus Digital 1 O Connector Optical Isolation Control Logic Optoisolators LOW SIDE OUTPUTS Optoisolator Figure 1 2 DNA DIO 416 Device Architecture Note that the I O part of the layer is isolated from the logic interface by isolation transformers and that overload protection is provided on all inputs and outputs E Copyright 2006 all rights reserved Tel 781 821 2890 Vers 1 0 D M EE ine Date 02 14 2007 File DNA DIO 416 Chap1 fm 1 5 Layer Connectors and Wiring Copyright 2006 all rights reserved United Electronic Industries Inc 19 DNA DIO 416 Layer Chapter 1 Introduction The pinout of the DB 37 37 pin female connector for the DNA DIO 416 Layer board is shown in Figure 1 3 DB 37 female 37 pin connector High Side DOUTO DOUT2 DOUTA oeno 36 8 vec DOUT6 DOUT8 DOUT10 vec Ba H6 vec DOUT12 DOUT14 Vcc 33 15 DGND x acer oe HE Low Side DOUT1 DOUT3 DOUT5 DOUTIS 30 2 RESERVED DOUT7 DOUT9 DOUT11 pour 28 10 pouT DOUT13 DOUT15 pout 27 9 DGND DOUT9 26 8 DOUTIO pouts SEE DOND Note Connect external power DOUTS 23 5 DGND source to VCC pins All VCC and DOUT3 22 4 DOUT4 s DOUT2 21 3 DGND DGND pins should be used to DOUTO 20 2 DOUTI 1 DGND supply external power 1 aaa RESTO CM
5. 1 5 0 022uF 0 0250 5 10KQ o Q 100KQ FET DOut High C gt Transistor 1A 60V DOutO User Load DGND Figure 1 7 Typical Output Circuit Diagram High Side 10 55V DC 1A 100V Reverse Current Protection User Load DOut Low FET Transistor 100KQ B 3 10KQ 5 0 022uF I 0 0250 o 3 2 10KQ q DGND Figure 1 8 Typical Output Circuit Diagram Low Side Referring to the circuit of Figure 1 6 the voltages from both high and low side current sensing resistors are fed to the two ADCs The ADC outputs are then processed in the logic to perform a virtual circuit breaker function The outputs are first compared to preset limits If they exceed the limits the FETs are turned OFF and the output circuit is shut down Depending on how the channel is configured the shutdown may either be immediate or delayed by a programmable time or by a cumulative number of detected faults Tel 781 821 2890 Vers 1 0 Date 02 14 2007 File DNA DIO 416 Chap1 fm 1 8 Configuring ADC Conversion Speed Measured Nominal channel ADC DNA DIO 416 Layer Chapter 1 Introduction The circuit breaker function can also be configured for either User Re enable default or for Auto Re enable The user re enable mode requires a write operation to re enable output on the disabled channel The auto re enable mode attempts to restore the channel after a 1 second default delay If an overcurr
6. 3 5W at max load 350Vrms 3 875 x 3 875 98 x 98 mm Tested 40 to 85 C 90 non condensing Noise Interrupts maskable Limit Override Power Requirements VCC Power Consumption Isolation Physical Dimensions Operating Temp Range Operating Humidity Copyright 2006 all rights reserved United Electronic Industries Inc Tel 781 821 2890 Date 02 14 2007 Vers 1 0 File DNA DIO 416 Chap1 fm DNA DIO 416 Layer Chapter1 4 Introduction Figure 1 1 is a photo of the DNA DIO 416 Layer board 120 pin DNA bus connector IRQ Jumpers Do not change Layer Position Jumpers see Figure 1 5 Power Connector DB 37 female 37 pin I O connector Figure 1 1 A DNA DIO 416 Digital I O Layer lC ee ee 9 Copyright 2006 all rights reserved Tel 781 821 2890 Vers 1 0 United Electronic Industries Ine Date 02 14 2007 File DNA DIO 416 Chap1 fm 1 3 Features DNA DIO 416 Layer Chapter 1 Introduction The main features of the PowerDNA DNA DIO 416 Solenoid Drive Output Layer are 16 digital outputs configured either as 8 high low pairs or 8 High side and 8 Low Side channels 500 mA per channel maximum current drive 125 Hz per channel maximum output rate Ideal for driving solenoids motors or other inductive loads FET transistors for high and low side outputs Inductive load kickback protection on every high low channel pair Resettable
7. 1 4 Physical Layout of DNA DIO 416 Layer Board Chapter 1 1 5 0 1 Jumper A diagram of the jumper block is shown in Figure 1 5 To set the layer Settings position jumpers place jumpers as shown in Figure 1 5 NOTE Since all layers are assembled in Cubes before shipment to a customer you should never have to change a jumper setting unless you change a layer from one position to another in the field Layer s Position as marked on the Faceplate 1 01 1 0 2 1 03 1 0 4 1 05 1 0 6 9 10 oo oo o o oo 11212 oo oo oo 13 14 oo oo 15 16 All I O Layers are sequentially enumerated from top to the bottom of the Cube 0 Open Closed Figure 1 5 Diagram of DNA DIO 416 Layer Position Jumper Settings Copyright 2006 all rights reserved Tel 781 821 2890 United Electronic Industries Inc Vers 1 0 Date 02 14 2007 File DNA DIO 416 Chap1 fm 8 DNA DIO 416 Layer Chapter 1 Introduction 1 6 Output Each output circuit is built as shown in Figure 1 6 Circuits 50VDC RHO HSCH1 C HSCH1 48 CAO To ADC 0 022uF RSHO Current E coo 0 025 Ohm WSLOBOSRO250FEA s u RAO Monitor HSCHo j SCHO T D OUTO 10K EDS4559 NC Q2 DOUTO User Ln 60 1A 60V Redundancy Load Support DFLS160 1A 60 Diodes Bw pos gt DOUT1 1 DFLS160 1A 60V FET ooa RF FDS4559 PC Q1 9 56K D_OUT1 To ADC Cu
8. 1152 00 2368 00 878 40 1171 20 544 3 242493 0 77307 1728 00 2304 00 256 1 525879 0 363798 3552 00 4736 00 200 1 192093 0 284217 6 76 0 84 Vin full scale mV 0 025 Shunt resistor Ohm LSB full scale 8388608 Full scale current uA 2000000 Note typical reaction of the circuit breaker is 50 longer then minimal mV LSB uV LSB 50 5 96046E 06 uA LSB 0 23841858 Maximum reaction time is 2x minimal nV LSB 1 9 Redundancy Copyright 2006 all rights reserved United Electronic Industries Inc 0 005960464 5 960464478 Increased system reliability is ensured by using the High Low Side Pair circuit for a given channel as illustrated in Figure 1 6 As shown in the figure a malfunction in one the FETs or side circuits will not prevent the other FET from disabling the circuit when needed The current sensing in the good side still functions and the circuit breaker function will still operate safely Note that this feature is not valid when High Side only Figure 1 7 or Low Side Figure 1 8 only circuits are configured Tel 781 821 2890 Date 02 14 2007 Vers 1 0 File DNA DIO 416 Chap1 fm 11 DNA DIO 416 Layer Chapter 2 12 Programming with the High Level API Chapter 2 Programming with the High Level API This section describes how to control the PowerDNA DIO 416 with UEIDAQ s high level API called Framework Framework is obj
9. Configuring the Circuit Breaker 10 Conventions 2 D Description 3 F Features 5 H High Level API 12 J Jumper Settings 8 L Layer Position Jumper Settings 8 O Organization 1 Output Circuit Diagram High Low Pair 9 Output Circuit Diagram Low Side 10 Output Circuit Diagram High Side 10 Index 20 Index P Photo of DIO 416 4 Physical Layout 8 Pinout 7 Programmin Low Level API 14 Programming Cleaning up 13 Configuring resource string 12 Configuring timing 13 Creating a session 12 Reading and Writing Data 13 Programming with high level API 12 R Redundancy 11 S Screw Terminal Panels 19 Specifications 3 Support ii Support email support ueidaq com ii Support FTP Site ftp ftp ueidaq com ii Support Web Site www ueidaq com ii Copyright 2006 all rights reserved Tel 781 821 2890 Vers 1 0 United Electronic Industries Inc Date 02 14 2007 File DNA DIO 4161X fm
10. IS qUdu NR Sheer Seeded NERIS 9 1 7 Configuring the Circuit Breaker Function 0 0000 eee eee eee 10 1 8 Configuring ADC Conversion Speed 0000s 11 1 9 hedundatncy uta bet ane eee Saat gant ie Ger beg Resend SBS teu ig 11 Chapter 2 Programming with the High Level API 000 cece eee eee eeee 12 2 1 Creating a Session 1 0 eee 12 2 2 Configuring the Resource String 0 ce eee 12 2 3 Configuring the Timing 0 ce RR en 13 2 4 Reading Data sis wcities eae hae hee ve AE ER oan Seda ets Dux ce d 13 2 5 Cleaning up the Session 0 ccc eh 13 Chapter 3 Programming with the Low Level API 0c cece eee eee eens 14 3 1 Code Examples 5 zo cA tcd hae Mak eh Nd Ria E PR prid 14 Appendix A Accessories esr ho mm a nm UR RR ee RUA RR 19 nr d DE 20 iii Table of Figures Chapter 1 Introduction n e a a ee 1 1 1 A DNA DIO 416 Digital O Layer ssse emere 4 1 2 DNA DIO 416 Device Architecture sssssseseene eene nennen 6 1 3 DB 37 I O Connector Pinout eenn n a eene eene enne nene 7 1 4 Physical Layout of DNA DIO 416 Layer Board sssssee e 8 1 5 Diagram of DNA DIO 416 Layer Position Jumper Settings seesse 8 1 6 Typical Output Circuit Diagram High Low Pair sm 9 1 7 Typical Output Circuit Diagram High Side ssse e 10 1 8 Typical Output Circuit Diagram
11. K A A kk kCk kc k kc k kc k kk kckckckck ckck ck ck ckck ck k ck ckckckckckck ck kk f BEGIN CUSTOM CONFIGURATION define IOM_IPADDRO NTO 168 1 0052 define DEVN 0 define TOTALSCANS 0 END CUSTOM CONFIGURATION define TIMEOUT DELAY 2000 milli seconds define RETRY ATTEMPTS 10 END Customizing defines define EVENT TIMEOUT 500 how long to wait for events to happen C SSS SS 8088588880880 000000000 NN ES a iiiOoOU O h LomcllLliLMLAAAs 2 c SSS SSS SSS See Copyright 2006 all rights reserved Tel 781 821 2890 Vers 1 0 PEU ere near een Date 02 14 2007 File DNA DIO 416 Chap3 fm a a t DNA DIO 416 Layer Chapter 3 15 Programming with the Low Level API define UPDATE PERIOD 50 int stop Handler for SIGINT void handler int sig stop 1 ff eree main routine define OVERCURRENTLIMIT 0 505 define UNDERCURRENTLIMIT 0 01 int main int argc char argv int error found 0 int hd0 0 int i ret pDOE pDge NULL pDOBCB pBcb NULL uint32 dataout datain DORDCFG DQRdCfg NULL int timeout EVENT TIMEOUT int datarcv 0 int packetlost int errorsallowed DQDIO416DATAIN data416 DQDIO416DATAOUT data416out 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 double float416 DQ DIO416 CHAN 0 RETRY ATTEMPTS m
12. a a ed teu 37 6o 6020 20 Figure 1 3 DB 37 I O Connector Pinout Note that the DIO 416 outputs are numbered from DOutO through DOut15 Also note the location of the nine VCC pins Power must be supplied to the layer by connecting an external 10 55V power source directly to the VCC pins or indirectly through the VCC pins on a DNA STP 37 terminal panel connected to the 37 pin I O connector on the board When power is provided to the layer the RDY LED on the PowerDNA Cube turns on When no power is supplied the RDY LED is off and the DNA DIO 416 layer cannot operate The only valid channel pairs are Channels 1and 2 2 and 3 4 and 5 6 and 7 8 and 9 10 and 11 12 and 13 14 and 15 Use of any other channel pair connections may cause severe damage to the equipment because kickback protection diodes will not be present Before plugging any I O connector into the Cube or Layer be sure to remove power from all field wiring Failure to do so may cause severe damage to the equipment The board does not have reverse polarity protection because of space constraints To prevent damage use extreme caution in connecting power to the layer Tel 781 821 2890 Vers 1 0 Date 02 14 2007 File DNA DIO 416 Chap1 fm DNA DIO 416 Layer Introduction DNA 120 pin Bus Connector 9 vi ci OL See Figure 1 5 for Fanor UseOnly jumper locations for setting layer position Power Connector External Circuits Figure
13. ansistors FETs that can be configured to provide output control for 8 channels on both high and low sides of the load or 8 channels each on just the high or low sides The board has redundant support FETs on every channel and also provides overvoltage kickback and overcurrent protection on every channel Output current monitors 0 5 accuracy can be configured to trigger automatic shutdown on overload detect short open output circuits and to confirm the state of every channel The maximum current drive is 500 mA per channel You can set the current and duration of an overload as short as 10 mS required to shut down each channel The DNA DIO 416 layer requires an external 10 55V power source The technical specifications for the DIO 416 layer are listed in Table 1 1 Table 1 1 DNA DIO 416 Technical Specifications Number of channels 16 digital outputs 8 high and 8 low side 500mA per channel continuous max 1A per channel max peak 1 sec max 125Hz per channel max 90V peak 2kV ESD Drive Capacity Output Rate Output Protection Circuit Breaker Current limit 50mA 1A user programmable Closing time 200 500ms autorestart Current Monitor Resolution 24 bit ADC ADC Speed 0 6 to 293 Hz Sense Resitor 0 0250 Over current Limit 0 2A Under current Limit 0 2A Accuracy 0 596 of full scale lt IMA 2 per channel over under current programmable per channel 10 55V external source 1 5W no load
14. aximum errors allowed at a time ifndef WIN32 DqInitDAQLib endif signal SIGINT handler open communication with IOM and receive IOM crucial identification data if ret DqOpenIOM IOM IPADDRO DQ UDP _ DAQ PORT TIMEOUT DELAY amp hd0 amp DQRdCfg lt 0 printf nError In Initializing Communication with IOM return 1 if DORdCfg NULL printf nError in receiving the response for Echo Command error found 1 goto finish up printf ipaddr d d d dWn DORdCfg ipaddr amp 0Oxff000000 224 DQRdCfg ipaddr amp 0x00ff0000 gt gt 16 SSS SS SS SSeS a Copyright 2006 all rights reserved Tel 781 821 2890 Vers 1 0 Ba eae ee Ng Date 02 14 2007 File DNA DIO 416 Chap3 fm DQ DQ printf model printf sernum printf mfgdate printf caldate DNA DIO 416 Layer Chapter 3 Programming with the Low Level API 16 RdCfg gt ipaddr amp 0x0000ff00 gt gt 8 RdCfg gt ipaddr amp 0x000000f 04x n DQRdCfg gt model 07dNn DQRdCfg gt sernum x x Sx n DQRdCfg gt mfgdate DORdCfg gt mfgdate DORdCfg gt mfgdate DORdCfg caldate DORdCfg caldate DORdCfg caldate Ox 000000 gt gt 24 Ox 0000 gt gt 16 Oxffff Ox 000000 gt gt 24 Ox 0000 gt gt 16 Oxffff Sx Sx Sx n RR m mm m for i 0 i DQ MAXDEVN i
15. directional ports you need to configure two sessions one for input and one for output n NS Copyright 2006 all rights reserved Tel 781 821 2890 Vers 1 0 Ba eae ee Ng Date 02 14 2007 File DNA DIO 416 Chap2 fm DNA DIO 416 Layer Chapter 2 13 Programming with the High Level API 2 3 Configuring You can configure the DIO 416 to run in simple mode point by point buffered the Timing mode ACB mode or Dmap mode In simple mode the delay between samples is determined by software on the host computer In buffered mode the delay between samples is determined by the DIO 416 on board clock The following sample shows how to configure the simple mode Please refer to the UeiDaq Framework User s Manual to learn how to use the other timing modes di session ConfigureTimingForSimpleIO 2 4 Reading Data Reading data from the DIO 416 is done by using a reader object The following sample code shows how to create a scaled reader object and use it to read samples Create a reader and link it to the session s stream CUeiDigitalReader reader di session GetDataStream read one scan the buffer must be big enough to contain one value per channel ulIntl16 data reader ReadSingleScan amp data 2 5 Cleaning up The session object cleans itself up when it goes out of scope or when it is the Session destroyed However you can manually clean up the session to reuse the object with a differe
16. ect oriented its objects can be manipulated in the same man ner from a wide range of development environments such as Visual C Visual Basic or LabVIEW The following section focuses on the C API but the concept is the same no matter what programming language you use Please refer to the UeiDaq Framework User Manual to get more information on using other programming languages 2 4 Creating a The Session object controls all operations on your PowerDNA device There Session fore the first task is to create a session object CUeiSession session 2 2 Configuring Framework uses resource strings to select which device subsystem and chan the Resource nels to use within a session The resource string syntax is similar to a web URL String lt device class gt lt IP address gt lt Device Id gt lt Subsystem gt lt Channel list gt For PowerDNA the device class is pdna As an example the following resource string selects digital output channels 0 1 2 3 on device 1 at IP address 192 168 100 2 pdna 192 168 100 2 Dev1 D0 3 NOTE In Framework a digital channel corresponds to a physical port on the device Note that you cannot configure a session only to access a subset of lines within a digital port Configure session to write to port 0 on device 1 do session CreateDOChannel pdna 192 168 100 2 Dev1 Do0 NOTE Sessions are unidirectional If your device has both input and output ports or has bi
17. ent is detected on restart the channel is disabled again and the re enable attempt is repeated The re enable time interval is user programmable The speed and resolution of the ADC are user programmable in the range from 0 6 to 293 Hz Refer to the section marked optional in the code example in Chapter 3 page 17 for more detail on setting ADC speed and resolution The default value for the ADC speed is 110 Hz which corresponds to 13 Hz per channel because of overhead Slower speed produces more accurate results but increases circuit breaker disconnect time as shown in the table below LL qesutminimum bresker reaction ms O o 2 3 Immediate consecutive consecutive consecutive noise decision samples samples Measured Measured Measured noise uV noise mA LSB p p Vin A in 1577 29 197 16 5 07 10 14 15 22 20 29 3857 22 98951 5 481127 7 30 14 59 1760 912 1096 49 137 06 880 1470 680 27 85 03 21 89 29 18 3584 21 3623 5 09317 35 28 47 04 2560 15 25879 3 637979 11 76 20 80 23 52 41 60 110 440 2600 384 62 48 08 220 4860 205 76 25 72 62 40 83 20 2048 12 20703 2 910383 116 64 155 52 896 5 340576 1 273293 38 88 75 20 77 76 150 40 9400 106 38 13 30 55 18300 54 64 6 83 146 40 292 80 292 80 585 60 225 60 300 80 768 4 577637 1 091394 439 20 585 60 592 3 528595 0 841283 6 875 148000 27 5 36600 27 32 3 42 13 75 72000 13 89 1 74 576 00 1184 00
18. g of the topics covered in this manual Copyright 2006 all rights reserved United Electronic Industries Inc Tel 781 821 2890 Vers 1 0 Date 02 14 2007 File DNA DIO 416 Chap1 fm DNA DIO 416 Layer Chapter 1 Introduction Manual Conventions To help you get the most out of this manual and our products please note that we use the following conventions Tips are designed to highlight quick ways to get the job done or reveal good ideas you might not discover on your own NOTE Notes alert you to important information CAUTION advises you of precautions to take to avoid injury data loss and damage to your boards or a system crash Text formatted in bold typeface generally represents text you should be entered verbatim For instance it can represent a command as in the following example You can instruct users how to run setup using a command such as setup exe Before plugging any I O connector into the Cube or Layer be sure to remove power from all field wiring Failure to do so may cause severe damage to the equipment Copyright 2006 all rights reserved Tel 781 821 2890 Vers 1 0 Peed Elen een ee Date 02 14 2007 File DNA DIO 416 Chap1 fm 1 2 The DIO 416 Layer DNA DIO 416 Layer Chapter 1 Introduction The DNA DIO 416 is an 8 channel Digital Output Layer designed for driving solenoids motors or other inductive loads attached to a PowerDNA Cube It has 8 digital outputs controlled by field effect tr
19. nt set of channels or parameters by entering do session CleanUp SSS SSS EE ee A Copyright 2006 all rights reserved Tel 781 821 2890 Vers 1 0 Palio a Eleeironieinausimese Ines Date 02 14 2007 File DNA DIO 416 Chap2 fm i 8 f DNA DIO 416 Layer Chapter 3 14 Programming with the Low Level API Chapter 3 Programming with the Low Level API 3 1 Code The following is an example of code used for a DNA DIO 416 Layer Example NAME Sample416 c DESCRIPTION Test DIO 416 specific commands NOTES This example utilizes a single DIO 416 layer Mr E RE igh Copyright C 2006 United Electronic Industries Inc All rights reserved United Electronic Industries Confidential Information include lt stdio h gt include signal h ifdef WIN32 include winsock2 h include conio h else include netinet in h include unistd h endif WIN32 include PDNA h RK RK KK KK kk kk kk KC KC KC KK ek ek ke kk ke IMPORTANT NOTE Ck ck ckckck ck ck kk ck ck ckck ck ckck kck kk k kk Before this example can be tested on your network you have to set up IP address of the cube IOM IPADDR and device number DEVN of the layer you intend to use ake sure that IP address of the cube lies within network mask defined in your Ethernet interface settings FER KK AK AK KC KC KC KC KC ICE KK KK KK KK KK K
20. overload circuit breaker function on every channel Output current monitoring 0 5 accuracy 24 bit resolution for short open circuit and output state detection Requires external 10 55Vpower source 1 5W no load 4 5W max load Power Good monitor indicates VCC gt 10V Programmable enable DC DC control emergency shutoff Redundancy support diodes on every channel Over and under current monitoring with programmable delay FET circuit breaking on every channel Auto enable option selectable per channel attempts to restore disabled channel Interrupt on over and under current conditions Current monitoring user programmable from 50mA 2A Default limit is 1000 mA default disconnect time is 10 15mS Layer survives output circuit shorts with impedances of 3 ohms or more SYNC interface support Clock output trigger input provided Guaranteed output OFF state on initial power up external power OFF internal power OFF and overload detected Tel 781 821 2890 Vers 1 0 Date 02 14 2007 File DNA DIO 416 Chap1 fm Copyright 2006 all rights reserved United Electronic Industries Inc 5 DNA DIO 416 Layer Chapter1 6 Introduction 1 4 Device The DNA DIO 416 Layer has 8 digital outputs 8 high low channels configured Architecture as current sources There are two sigma delta ADCs one for high side circuits and one for low side circuits that run independently A block diagram of the board is shown in Figure 1 2
21. pa United Electronic wy Industries The High Performance Alternative PowerDNA DIO 416 Solenoid Drive Output Layer User Manual 8 Channel 500 mA Solenoid Inductive Load Drive Output Layer Release 1 0 February 2007 Edition PN Man DNA DIO 416 0207 Copyright 1998 2007 United Electronic Industries Inc All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form by any means electronic mechanical by photocopying recording or otherwise without prior written permission Information furnished in this manual is believed to be accurate and reliable However no responsibility is assumed for its use or for any infringement of patents or other rights of third parties that may result from its use All product names listed are trademarks or trade names of their respective companies See the UEI website for complete terms and conditions of sale http www ueidaq com company terms aspx Contacting United Electronic Industries Mailing Address 611 Neponset Street Canton MA 02021 U S A For a list of our distributors and partners in the US and around the world please see http www ueidaq com partners Support Telephone 781 821 2890 Fax 781 821 2891 Also see the FAQs and online Live Help feature on our web site Internet Support Support support ueidag com Web Site www ueidaq com FTP Site ftp ftp ueidag com Product Disclaimer
22. printf DOUT status 0x 08x datain datarcv 16 0x001111 0x 04x dataout dataout printf dataout Write digital outputs if ret DqAdv40xWrite hd0 DEVN dataout lt 0 printf nError in DqAdv40xWrite error found 1 goto finish up Sleep 500 limit the number of loops if TOTALSCANS 0 if TOTALSCANS amp amp stop 1 datarcv gt TOTALSCANS printf Mn finish_up if hd0 DqCloseIlOM hd0 17 Copyright 2006 all rights reserved United Electronic Industries Inc Tel 781 821 2890 Date 02 14 2007 Vers 1 0 File DNA DIO 416 Chap3 fm DNA DIO 416 Layer Chapter 3 18 Programming with the Low Level API ifndef WIN32 DqCleanUpDAQLib endif if error found return 1 else return 0 Copyright 2006 all rights reserved Tel 781 821 2890 Vers 1 0 VARSHLEIPER Sec Ingusiriesing Date 02 14 2007 File DNA DIO 416 Chap3 fm DNA DIO 416 Layer Appendix A Accessories The following cables and STP boards are available for the DIO 416 layer DNA CBL 37 A 3ft 37 way flat ribbon cable that connects the layer to a terminal panel DNA STP 37 37 way screw terminal panel Copyright 2006 all rights reserved Tel 781 821 2890 Vers 1 0 VARSHLEIPER Sn Ingusiriesing Date 02 14 2007 File DNA DIO 416 Appx fm A ADC Conversion Speed 11 Architecture 6 B Block Diagram 6 C Cable s 19 Caution 7
23. r re enable circuitry printf dout 08x n data416 dout Actual values on the outputs low side inverted Copyright 2006 all rights reserved United Electronic Industries Inc Tel 781 821 2890 Date 02 14 2007 Vers 1 0 File DNA DIO 416 Chap3 fm DNA DIO 416 Layer Chapter 3 Programming with the Low Level API for i 0 i DQ DIO416 CHAN printf ocl 02d 08x i data416 ocl i Overcurrent limit printf ucl 02d 2 08x i data416 ucl i Undercurrent limit printf adc 02d 08x i data416 adc i Raw ADC Value printf cur 02d 6d uA n i data416 cur i uA ADC Value i JW eR Se a ae a ee ELO RICH Pn aaa OPTIONAL PART set additional configuration parameters on 416 set fastest speed possible keeping current settings on timing data4l6out adcspdset 1 data4l6out adcspd data416 adcsts amp OxFFF00000 change number of failed reads prior to break data4l6out rdcntset 1 data4l6out rdcnt 2 if ret DqAdv416SetAll hd0 DEVN amp data4l6out printf nError in DqAdv416GetAl1 error found 1 goto finish up DQ L416 ADCSPD 190 0 while stop datarcvtt printf nCycle d datarcv Get status of the disabled channels first because channels will be re enabled when updated if ret DqAdv40xRead hd0 DEVN amp datain lt 0 printf nError in DqAdv40xRead error found 1 goto finish up
24. rrent Monitor RSLO 0 025 Ohm WSLO805R0250FEA DGND Figure 1 6 Typical Output Circuit Diagram High Low Pair Because of inherent imbalances in components in the circuit of Figure 1 6 a small current is always flowing from VCC to ground through the 0 025 ohm sense resistors This produces a voltage that is monitored by the two current sensing ADCs If the current falls below a programmed minimum this indicates a possible fault such as an open circuit An interrupt is then enabled Similarly an overcurrent in the ON state indicates a short or overload condition which generates an interrupt and can cause the circuit to be shut down if so configured Figure 1 7 shows a typical High Side output circuit Its function is similar to that of Figure 1 6 except that it only uses the high side FET Figure 1 7 shows a typical Low Side output circuit using only the low side FET Copyright 2006 all rights reserved Tel 781 821 2890 Vers 1 0 TInitediElecironiendusiries Ines Date 02 14 2007 File DNA DIO 416 Chap1 fm Y Xi 1 7 Configuring the Circuit Breaker Function Copyright 2006 all rights reserved United Electronic Industries Inc DNA DIO 416 Layer Chapter 1 10 Introduction 5 10KQ o 10 55V DC T lt 1 o
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