1 Tutorial - Robotics and Embedded Systems
Contents
1. lt lt new node gt gt Figure 1 10 Pin Planner with locations assigned to pins ware design see section 1 1 4 programming the FPGA chip Now that you have created a hardware description for your FPGA and have successfully generated compiled it you can proceed to program your design Programming your hardware design onto the FPGA can be done from the console or by using the Programmer UL Programming the FPGA chip will keep the hardware description in the chip until the next programming or power loss This means that the chip has to be programmed again each time the development board is turned on To avoid reprogramming upon each power cycle the FPGA chip can be set to an automatic programming mode In this mode the FPGA will take the hardware description from a flash memory and program itself upon start But there is a restriction to this automatic programming mode It can only be used if all the components used in the current hardware design are properly licensed e g the tse ethernet MAC component is not licensed in Quartus II Web Edition See section 1 1 2 for a short summary of the differences between Quartus versions You can start the Programmer manually or even fire it up from your Quartus instance see figure 1 11 for a screenshot of the Programmer main window To do so open your hardware design project and select Tools Programmer from the menu bar If you start Programmer from Quartus the hardware design yo2. PIO Parallel I O to the system The parameter window appears Do not change any settings as the default value configures the PIO as an 8 bit output device As we referring to this component later in the software design process we give it a new name Right click on the pio_0 component select the Rename option and enter ed_pio as its new name Connect clk and reset to the clock source and connect s1 to the data_master port of the processor To export the external_connection port of the led_pio component double click in the Export column of the external_connection row The PIO component finishes the list of components that are needed for this basic NioslI system Now it is time to remove the errors from our Qsys system By just adding all the components to the system Qsys automatically assign base address 0x00000000 to all of them This creates conflicts as a memory address can only be used by one component Osys provides a function to automatically create a non conflicting memory assignment To run this function select System Assign Base Addresses from the menubar Finally the only warnings remaining apply to the Interrupts of the system Low interrupt numbers mean high priorities in NiosII systems We assign a low priority i e a high inter rupt number to the JTAG component You can assign an interrupt to the JTAG component by clicking on the semi transparent dot in the IRQ column of the jtag_uart_ O component Type
3. both options Reset vector memory and Exception vector memory to your onchip_memory2_0 s1 component The final NiosII settings in the pa rameter window should look like figure 1 6 To be able to flash and debug our applications later on we add a Joint Test Action Group JTAG component to our system Add the JTAG UART component from Interface Proto cols Serial JTAG UART in the Component Library Do not change any settings in the parameter window and add the component by selecting the Finish button Connect the clk port of the jtag_uart_O component to clk_0 of your clock source and reset to clk_reset Connect the JTAG s avalon_jtag_slave port to the data_master port of your CPU To be able to generate a BSP for our system later on we need to have an Interval Timer in our system Add Peripherals Microcontroller Peripherals Interval Timer to the system Choose Full features from the Presets setting and add the component through the Finish button Connect clk and reset to your clk 0 component and connect the s1 port to the data_master port of the NiosII CPU The system ID component can identify our generated system and thus protect it from ac cidentally flashing software which is not intended for this system The component can be found at Peripherals Debug and Performance System ID Peripheral When adding the System ID component add a randomly chosen 32bit
4. 1 Tutorial Contents 1 Tutorial 1 Glossary 1 1 Initial setup of the development environment 1 1 1 components cae se Cees eee we ee RR ew eRe we Iolye WSIAUQNON c s e see tase et ead ee bwe ew ch eRe eREAS 1 1 3 verification of successful installation 0 0 4 1 1 4 first steps with the xme software fornios 4 NPR RP ew Bibliography 19 Glossary BSP Board Support Package 14 CPU Central Processing Unit 14 HDL Hardware Description Language 8 IDE Integrated Development Environment 13 IP Intellectual Property 1 4 JTAG Joint Test Action Group 5 LED Light Emitting Diode 6 PIO Parallel I O 15 SVN Subversion 2 xme chromosome a modular middleware architecture for cyber physical systems 2 Glossary 1 1 Initial setup of the development environment 1 1 1 components Development means creation of a hardware description for the FPGA and writing soft ware for the created hardware Altera Corporation provides the necessary tools which are Quartus II and the Nios2SBT to achieve this 1 1 2 installation Please note that this installation description applies to installing the Altera Design Suite v12 on Windows7 64bit only To install all the required software Altera Corporation provides a Free Download package at its website called Altera Design Suite Altera In staller This is a installer package which downloads all selected installation components during the
5. 11 3 Terasic Technologies Inc DE2 115 User Manual Terasic 2010 4 terasIC My First Nios II for Altera DE2 115 Board Terasic Technologies Gongdao 5th Rd East Dist Hsinchu City 30070 Taiwan 19
6. ID into the 32 bit System ID field This value will identify your system but is not important for us in this example Glossary r ca On Chip Memory RAM or ROM onchip_memory2_0 2 e _ x Tk On Chip Memory RAM or ROM Megatore altera_avalon_onchip_memory2 Documentation Block Diagram l a Memory type ow signals 9 Type RAM Writable w onchip_memory2_0 Duetport ocene Single clock operation Read During Write Mode DONT_CARE Block type Auto Size Data width a Total memory size 20480 bytes in e memory block usage may impact fma Read latency Slave s1 Latency _ Slave s2 Latency 1 Memory initialization V Initialize memory content _ Enable non defautt initialization file User created initialization file ip_memory2_0 _ Enable In System Memory Content Editor feature Instance ID NONE Info onchip_memory2_0 Memory will be initialized from onchip_memory2_0 hex cance Figure 1 5 On Chip Memory parameters Connect the sysid_qsys_0 component to the clock source and the CPU s data_master port Our system cannot communicate with its surroundings yet We want it to be able to con trol Light Emitting Diodes LEDs to let us know if the program is working To control the LEDs we need a connection to the LEDs on the board Add Peripherals Microcontroller Peripherals
7. II New Project Wizard A NiosII system requires memory to store instructions and data To keep the design sim ple we are choosing On Chip memory for our design On the left of the Qsys window you have a Component Library which gives you a selection of all available components for your system Choose Memory and Memory Controllers On Chip On Chip Memory RAM or ROM from the Component Library and double click on it to add it to your system A new window opens which lets you choose the parameters for your new component Change the total memory size to 200480 bytes see figure 1 5 20 kiB should be enough for our small demonstration system Click Finish to add the On Chip Memory to the system It will appear in the System Contents list of Qsys Next add the NiosII processor core to the system by choosing Embedded Processors Nios II Processor from the Component Library The NiosII parameter window opens and you have to choose a NioslI core variant More complex cores give performance advantages and have useful functions For out tutorial we do not need any special functionality and can choose the smallest core version Nios II e Nios II e is the only core variant which does not need any IP and thus can be used without time limitation in the free Web Edition of Quartus In the bottom part of the NiosII parameter window you can see some error messages letting you know that the exce
8. Location us DE 23 LEDG 7 0 Output Group E ae 25 LEDG 7 Output PIN_G21 7 a OOO OOOCATMAGO OAOCOOACO out LEDG 6 Output PIN_G22 Fa oe T E a A out LEDGIS Output PIN_G20 7 z 0O00 OOOHOO OOCOOOOOOO OOOOH c J out LEDG 4 Output PIN_H21 7 2 HOO OOO ODOODOOOOOO OOO da out LEDG 3 Output PIN_E24 7 out LEDG 2 Output PIN_E25 7 a out LEDG 1 Output PIN_E22 7 i out LEDG O Output PIN_E21 Z E lt lt new group gt gt We Im t O00 ial n sex 3 _ O00 pan aman Y iP AV OO 3 QOCA m 00000 z 00000000000000 A OOS 0000000000 AOG SOK900 OG amp AOOO YOO S an 9 Pin i Named X k gt Edit x H Node Name Direction Location I O Bank VREF Group I O Standard Reserved Current Strength Slew Rate Differential Pair in CLOCK_50 Input PIN_Y2 B2_NO 2 5 V default 8mA default out LEDG 0 Output PIN_E21 i out LEDG 1 Output PIN_E22 i out LEDG 2 Output PIN_E25 out LEDG 3 Output PIN_E24 out LEDG 4 Output PIN_H21 out LEDG 5 Output PIN_G20 out LEDG 6 Output PIN_G22 Output PIN_G21 B7_NO 2 5 V default 8mA default 2 default B7_NO 2 5 V default 8mA default 2 default B7_N1 2 5 V default 8mA default 2 default rt 2 5 V default 8mA default 2 default B7_N2 2 5 V default 8mA default 2 default B7_N1 2 5 V default 8mA default 2 default B7_N2 2 5 V default 8mA default 2 default B7_N1 12 5 V default 8mA default 2 default NNN NNN NNN w N zZ _ All Pins pys S
9. _system Info irg_mapper qsys_nios_system instantiated altera_irq_mapper irg_mapper Info qsys_nios_system Done qsys_nios_system with 24 modules 74 files 1405111 byl Info ip generate succeeded Info Finished Create HDL design files for synthesis 4 UW Generate Completed 0 Errors 0 Warnings Figure 1 8 output of succesful generation an Pin hovering below your mouse pointer Place it next to your NiosII system block so that the clk_clk wire connects to your pin Press the menu of the Pin Tool again but this time select Output from the toolbar Place the output pin next to your NiosII block Select it by using the Selection Tool from the toolbar and rotate the output pin by 180 degrees You can do that by right clicking on the output pin and selecting Rotate by Degrees Rotate Left 180 connect the output pin to the led_pio_external_connection_export 7 0 wire You can easily distinguish input and output pins by their shape Double click on an empty space in the Block Diagram file again but this time add c altera 12 1 quartus libraries primitives other vcc Place the VCC pin next to your NiosII block and connect the VCC pin with the reset_reset_n wire using the Orthogonal Node Tool from the toolbar Take care to draw the Orthogo nal Node line precisely from the reset_reset_n wire to the connection of the VCC pin You should have a small square at the VCC pin and the NioslI block visualiz
10. ation project and select the BSP for your project the BSP that you created in section 1 1 4 Create the project by selecting the Finish button The project appears in the Project Explorer To add a new source file to the application project right click on the application project and select New Source File In the New Source File window see figure 1 16 enter a name for the Source File and click Finish to create your file Every project has to contain a main function which is the entry point to your application Start by creating this function and adding code to it Listing 1 1 shows how a basic main function could look like It demonstrates the output of text to the console by using 1 printf Hello from Nios II n and controls the LEDs that we connected via a Parallel I O PIO component by using 1 ITOWR_ALTERA_AVALON_PIO_DATA PIO_LED_BASE count amp 0x01 You created your first NiosII software application Glossary DEE Hew Source Fie Source File Create a new source file Source folder quartus_demo Source Tile main c Template Default source template Configure Figure 1 16 the BSP creation wizard include lt stdio h gt include lt system h gt include altera_avalon_pio_regs h int main printt Helle from Nios IT n int count 0 int delay while 1 TOWR_ALTERA AVALON PIO _DATA LED PIO BASE count amp 0x01 delay 0 while delay lt 2000000 delaytt I cou
11. contained in the lt quartusII_project_dir gt lt niosI_system_nan folder After adding all the files to the project the window should look like figure 1 9 close the window wuth the OK button Your Analysis amp Elaboration should finish without any Glossary a Settings quartus_nios_demo E Sto Category Device me Files Libraries Select the design files you want to indude in the project Click Add All to add all design files in the project directory to the 4 Operating Settings and Conditions Project Voltage EES Temperature File name cas de E sg rect r File Name Type Library Design Entry Synthesis To Add All Incremental Compilation qsys_nios_system synthesi Verilog HDL File lt None gt Physical Synthesis Optimizations qsys_nios_system synthesi Verilog HDL File lt None gt R 4 EDA Tool Settings qsys_nios_system synthesi SystemVerilog HDL File lt None gt Design Entry Synthesis qsys_nios_system synthesi SystemVerilog HDL File lt None gt Simulation qsys_nios_system synthesi SystemVerilog HDL File lt None gt Formal Verification qsys_nios_system synthesi Verilog HDL File lt None gt Board Level qsys_nios_system synthesi Verilog HDL File lt None gt 4 Analysis amp Synthesis Settings qsys_nios_system synthesi Verilog HDL File lt None gt VHDL Input qsys_nios_system synthesi Verilog HDL File lt None gt Verilog HDL Input qsys_nios_system synthesi Verilog HDL File l
12. e processor does not require a license the DDR RAM controller or the tse ethernet MAC component 1 1 3 verification of successful installation designing an FPGA To verify that your installation was successful this tutorial which is based on 4 and 1 will guide you through your first steps in the Quartus II environment You will create your first Nios II CPU on your FPGA Please note that Altera has removed the SOPC builder from Quartus II v12 on which means that for designing the CPU core 4 is no longer usable To verify that you have a working set up please follow the steps described in 2 Glossary Select products Select the software products you want to install Products Install Size Download Size 4 F Quartus II Subscription Edition includes Nios II EDS 4 4G E Quartus II software 64 bit 810 M gt E Device Families 4 Quartus II Web Edition Free includes Nios II EDS 4 56 4 Device Families 240 M E Arria II GX 472 M E Cyclone II 29M E Cyclone I II LS 213 M Cyclone IV E 240 M E Cyclone IV GX 179M E Cyclone V 541 M E Legacy Families 1 5 M E MAX II 3 8 M E MAX V 4 2M E ModelSim Altera Starter Edition Free 3 4 G E ModelSim Altera Edition 3 4G E DSP Builder 254 M Description gt Select Products Includes Cyclone IV E device support Install Download Space Required 4 56 1 3G Select Deselect All Space Available 88 G 88 G Figure 1 1 Compo
13. eption vector memory None Fast TLB Miss Exception vector offset 9x99000000 Fast TLB Miss Exception vector 0x00000000 Include MPU Figure 1 6 NiosII processor parameters Figure 1 7 gives an overview of all the components which are used in this Qsys system It also shows the connections between the components black dots and lines on the left vi sualize a connection Further the Interrupt numbers for the JTAG and Timer components are set compare column IRQ Base Addresses in this figure were automatically assigned The assignment can be checked in columns Base and End Once your Qsys system design is finished you can start generating it similar to compiling source code Open the Generation tab in Qsys leave all settings at their default values and click the Generate button Qsys will ask you if you want to save your system Answer Yes and save the system in your QuartuslIl project directory The Generate window will show the generation output Generation can last several minutes depending on the system de sign and your host computer s performance When the status bar in the Generate window turns green your system has been successfully generated Your Generate window should look like figure 1 8 Close the Generation window and exit Qsys to return to QuartusllI Congratulations you are finished with the processor system adding the NiosII system to the QuartusII project The newly generated process
14. es window for evaluation time details Figure 1 12 the time limitation warning of Programmer Programmer A message will appear which reminds you of that situation the message might look like figure 1 12 Now you need to set your USB Blaster connection to the FPGA chip Simply click the Hardware Setup button and window like 1 13 will show up If you are using USB Blaster for programming on DE2 115 boards you are using USB Blaster your USB Blaster will show up in the list of Available hardware items Select if from the Currently selected hard ware dropdown list close the Hardware Setup window and you sould be ready to start programming The Start button should be enabled if you have added a sof file if you have selected a FPGA device and if your USB Blaster is selected Start programming the clicking that button The progress bar should show Success after programming finished successfully This means that your hardware design was programmed onto the FPGA chip If you are using non licensed time limited components a popup window will ap pear after successful programming TODO link to screenshot here Leave this window open and keep the FPGA chip connected to your computer until you have finished using your hardware design 12 Glossary sip Hardware Setup Hardware Settings JTAG Settings Select a programming hardware setup to use when programming devices This programming hardware setup applies only to the current prog
15. evice ID Common Source B Name Architecture E C C Remote App Launch Group PAA Nios I Hardware P blah Nios I Har 1 1 USB Blaster on localhost USB Blaster on localhost bo Beez EP3C120 INios2 3 Nios2 3 nios2_1 nios2 0 4 Filter matched 32 of 32 items b P blinky_a_la_Kai Device Device ID Instance ID Name PAI blinky_dual_cpu USB Blaster on localhost zeare ious f A F taguart_1 E P blinky_dual_cpu USB Blaster on localhost EP3C120 1 _ i0 __ itaquart 0 1 zal Blinky manual Disable Nios II Console view P de2 115 Nios I i m P hello_sd_3july_r Quartus Project File name lt Using default sopcinfo amp jdi files extracted from ELF gt ca cae System ID checks 7 u i 4 ae eae N Ignore mismatched system ID PA hello_world_sdri Ignore mismatched system timestamp PA IwIP_NIOS_I Ex Pa IwIP_NIOS_I_Ex Download P P myfirst_niosll_ay Download ELF to selected target system pA RTOSDemo_nio Start processor pa RTOSDemo_SBT Reset the selected target system PA sdram_gang_10j Figure 1 18 choosing the target connection 18 Bibliography 1 Altera My First Nios II Software Tutorial Altera Corporation 101 Philip Drive Assinippi Park Norwell Massachusetts 02061 USA January 2010 2 Altera Nios II Hardware Development Tutorial Altera Corporation 101 Innovation Drive San Jose CA 95134 May 20
16. ge five will give you a summary of your project settings Finish the New Project Wizard with Finish designing the NiosII system First of all we have to create our Processor Block This can be either be accomplished by using SOPC Builder or Qsys Qsys is the newer of them so we are using Qsys in this introduction Qsys can be used to create a NiosII system including components such as timers or memory This is exactly what we are doing now Glossary i j New Project Wizard Family amp Device Settings page 3 of 5 Select the family and device you want to target for compilation Device family Show in Available devices list Family Cydone IV E z Package Any X D Pin count Any Target device Speed grade Any Auto device selected by the Fitter Name filter Specific device selected in Available devices list v Show advanced devices HardCopy compatible only amp Available devices a Mame _ _ Core Voltage hE ala _User I Os __ Memory Bits ___ Embedded multiplier 9 bit elements PLL a al EP4CE115F23I8L 1 0V 114480 281 3981312 e a e e r E EP4CE115F29C8 1 2V 114480 529 3981312 532 EP4CE115F29C8L 1 0V 114480 529 3981312 532 EP4CE115F29C9L 1 0V 114480 529 3981312 532 EP4CE115F2917 1 2V 114480 529 3981312 532 EP4CE115F2918L 1 0V 114480 529 3981312 532 r m j bpp DD 8 Companion device amp Figure 1 3 page 3 of the Quartus
17. igure 1 9 project file setup window for Quartus issues If Analysis amp Elaboration has indexed your hardware design you can proceed to assign hardware positions to the pins in your hardware design Open the Pin Planner by selecting Assignments Pin Planner from the menubar At the bottom of the Pin Planner win dow there is a list with all the pins in your design Assign a location on the FPGA chip for each of the pins Nodes in Pin Planner by clicking on the empty cells in the Location col umn According to 3 the pin locations can be looked up in table 1 1 After assigning the Locations the Pin Planner window should look like figure 1 10 You can close Pin Planner and your hardware design is finished To finally generate your hardware design choose Processing Start Compilation Wy from Table 1 1 pin assignments for the DE2 115 board the menubar This process might take several minutes depending on your machine and hardware design If your Compilation finishes without errors you just created your first FPGA hardware design You can proceed and program your FPGA chip with this hard 10 Glossary e y Pin Planner C Users martin Documents quartus_nios_demo quartus_nios_demo quartus_nios_demo o File Edit View Processing Tools Window Help 5 Search altera cor Groups Wax Top View Wire Bond Cyclone IV E EP4CE115F29C7 Named X E Node Name Direction
18. ing an electrical link the visualization appears only if you have selected the Orthogonal Node line Right click on the output pin and open the Properties window of the output pin Rename the output pin by typing LEDG 7 0 in the Pin name s field Rename the input pin which is connected to the clk_clk wire to CLOCK_50 in the same way Now that all the pins for the hardware design are known a mapping to the hardware pins of the FPGA chip has to be created QuartusII has to detect all the pins in our hardware design thus we have to start the first steps of a compilation run first To do so select Pro cessing Start Start Analysis amp Elaboration from the menubar A new Compilation Report tab opens If the compilation was successful a window labeled Analysis amp Elaboration was successful appears If you have encounter an error particularly the error Node instance jinstance_ name instantiates undefined entity lt entity name gt then QuartusII might not find your NioslI system synthesis files the compiled files or the NiosII system In this case you should add them manually by selecting Project Add Remove Files in Project from the menubar Press the button with written on it to select the files you want to add Add the main v file which describes your NiosII block from lt quartusII_project dir gt lt niosII_system_name gt synthesis lt nio and click the Add button also add all the files
19. installation process from the internet To start the installation execute the in staller package as an administrative user right click and select run as administrator This step is very important as your USB Blaster will not work if you installed the software as a low privileged user If the installer asks you to select the desired components deselect everything and only select e Quartus II Web Edition Free includes Nios2SBT e Cyclone IV E in the Device Families category If you are running Quartus II v12 0 on a 64bit machine you might still have difficulties finding the USB Blaster hardware in the Programmer tool Altera does not ship the 64bit JTAG Server with the QuartusII Web Edition To resolve this issue install the standalone Programmer Software from https www altera com download software prog software which contains a 64bit Programmer and JTAG Server update as of Quartus II v12 1 you do not need to separately install the standalone Programmer Altera offers a paid Quartus II Subscription Edition and a free Quartus II Web Edition version of its Quartus development suite The free version includes most of the features for beginners or even professionals One striking difference are the missing Intellectual Prop erty IP license files for several more complex components These components which are not fully licensed to free edition users include but are not limited to NiosII s or NiosII f processors the NiosII
20. mer Clock Input Reset Input Avalon Memory Mapped Slave E sysid_qsys_0 System ID Peripheral clk Clock Input 0x0001_1038 0x0001_103 Ox0001_1000 0x0001_101 reset Reset Input control_slave Avalon Memory Mapped Slave PIO Parallel VO Clock Input Reset Input Avalon Memory Mapped Slave Conduit Endpoint 0x0001_ 1030 0x0001_1037 Ox0001_1020 0x0001_102 external_connection led_pio_external_connecti Messages Description Path 3 info Messages Memory will be initialized from onchip_memory2_0 hex System onchip_memory2_0 System ID is not assigned automatically Edit the System ID parameter to provide a unique ID System sysid_qsys_0 Time stamp will be automatically updated when this component is generated System sysid_qsys_0 Figure 1 7 an overview of Qsys system textually by using VHDL or by using the Verilog language But QuartuslII also lets you de sign systems without having to use one of the Hardware Description Languages HDLs Instead you can design your system graphically This is what we are doing here to keep things simple Select File New from the menubar and select Block Diagram Schematic File in the New window Create the new Block Diagram file by clicking OK Save the new Block Diagram file with the File Save As command Use the same name for this entity as you used for your projec
21. nent selection in the Altera Installer It is of particular importance to use the correct names for the components as references to these names have to be consistent 1 1 4 first steps with the xme software for nios In this section all the steps to create a executable binary for the DE2 115 development board are described All steps in this tutorial are based on the Altera Software in version 12 0 sp1 If you have a different software version the same steps may apply but some screens or identifiers may differ drom this description First of all make sure that you have a copy of the xme chromosome Subversion SVN We will refer to the root of this SVN tree as jsun root designing your hardware This section gives you a quick introduction into the main QuartuslII features and on how to build a simple NiosII hardware design with Quartusll It is based on 2 This introduc tion uses Quartus v12 1 64 Bit on a Windows machine and creates a demo project for the DE2 115 development board For different Quartus versions or FPGAs please take care to change this description at the corresponding sections Glossary New Project Wizard xs Directory Name Top Level Entity page 1 of 5 What is the working directory for this project C Users martin Documents quartus_nios_demo What is the name of this project quartus_nios_demo What is the name of the top4evel design entity for this project This name is case sensitive and m
22. nt t return 0 Oo oo NOAUA MRA Q N e 10 Hi i a a a a a a o N A a RA WY N e Listing 1 1 example implementation of a main function 16 Glossary executing NiosII projects on the target hardware You can execute your NiosII project from the Nios25BT To execute the application right click on the application project in the Project Explorer and choose Run As Nios II Hard ware This will compile your application create a downloadable image download the software image and execute it on the target hardware Before executing please make sure that you programmed the target hardware with the correct Hardware Design see section 1 1 4 Another option is to debug your application To start debugging right click the project and select Debug As Nios II Hardware This will execute the same steps as running the software and additionally start Nios2SBT s debugger if a window similar to figure 1 17 appears your Target Connection setup may be incorrect g Debug Configurations Create manage and run configurations Target Connection No Nios I target connection paths were located Check connections and that a Nios I sof is downloaded re HB amp O v Name blah Nios I Hardware configuration type filter text E Project gt Qi Target Connection Debugger y Source Common E C C Application Proj E C C Attach to Aj cans biah i E C C Postmorterr Pr
23. oject ELF file name C Users martin plah piah elf z C C Remote Apr Launch Group Enable browse for file system ELF file 4 FRA Nios I Hardware P blah Nios II Hart File system ELF file name pin blinky_a_la_Kai l P blinky_dual_cpu z zal blinky_dual_cpu _Advanced PA Blinky manual PAY de2 115 Nios It P hello_sd_3july_ri PA hello_sd_july02 P hello_sd_july09_ M P hello_world_0 N zal hello_world_sdri PAA IwIP_NIOS_Il_Exe Pay IwIP_NIOS Tl Ex pin myfirst_niosIl_a PA RTOSDemo_nio P RTOSDemo_SBT P sdram_gang_10j 4 mW Filter matched 32 of 32 items Figure 1 17 the window indicating an error with the target connection path To setup the target connection open the Target Connection tab and click the Refresh Connec tions button Select a Processor to execute your target on and a Byte Stream Device through which text output will be transferred see 1 18 Confirm your selection with Apply and start Debugging your software with Debug This finishes the tutorial on how to run your first Nios II Application 17 Glossary r Debug Configurations Create manage and run configurations Select one of the available target connection paths Bi aw F7 Name blah Nios I Hardware configuration type filtertet E C C Application E C C Attach to Ay fe C C Postmorterr E Project fl Target Connection Debugger ly Cable Device D
24. or sys tem has to be integrated into QuartusII You can design FPGA hardware in QuartuslI either Glossary B File Edit System View Tools Help Component Library s E3 A W Project 1 New Component Library Bridges Clock and Reset Configuration amp Programming DSP Embedded Processors interface Protocols Memories and Memory Controllers System Contents Address Map Clock Settings Project Settings Instance Parameters System Inspector HDL Example Generation Connections E nios2_qsys_0 clk Description Clock Source Clock Input Reset Input Clock Output Reset Output On Chip Memory RAM or ROM Clock input Avalon Memory Mapped Slave Reset Input Nios Il Processor Clock Input Export clk reset ox0000 8000 0x0000_cfff IRQ Tags Opcode Name Merlin Components i reset_n Microcontroller Peripherals Peripherals data_master PLL instruction_master Reset Input Avalon Memory Mapped Master Avalon Memory Mapped Master jtag_debug_module_reset Reset Output jtag_debug_module Avalon Memory Mapped Slave custom_instruction_master Custom Instruction Master jtag_uart_0 JTAG UART clk Clock Input E e IRQ 0 IRQ 31 E3 Qsys Interconnect SLS University Program Verification 4 Window Bridge 0x0001_0800 0x0001_0fff G e reset Reset Input avalon_jtag_slave Avalon Memory Mapped Slave Interval Ti
25. ption and reset vector memory are not set Ignore these error messages for now and add the processor core by clicking the Finish button Figure 1 6 shows the parameter window ignore the Reset Vector and Exception Vector settings for now Now you should have three components in the System Components list e the clock source clk_0 this component was automatically generated for you Glossary Figure 1 4 label of the FPGA chip e the On Chip Memory onchip_memory2_0 e the NiosII CPU core nios2_qsys_0 To connect components to each other you can toggle the connection state between com ponents by clicking the semi transparent dots in the Connections column of the System Contents list Connect the clk port of the clk 0 component to the clk1 port of the On Chip Memory by clicking on the dot in the clk1 row Connect the clock source clk of the clk_0 component to the Clock Input of your NiosII processor in the same way Connect the clk_reset port from the clock source to the reset1 port of your memory and to the reset_n port of the processor Now connect the processor with the memory block by connecting the s1 port of the memory to both the data_master and instruction_master ports of the processor This finishes the first stage of wiring After connecting the memory to the CPU we can fix the processor errors we encountered before Double click on the processor component in the System Contents list to open the processor parameter window again set
26. rammer window Currently selected hardware USB Glaster USB 0 Available hardware items Server Port Local USB 0 Remove Hardware Figure 1 13 The hardware setup window of Programmer Sometimes you could have issues with your USB Blaster hardware detection If your USB Blaster is not selected from your previous programming try to select it again in the Hard ware Setup window If it does not show up in the list of Available hardware items check your physical connection to your development board Make sure the USB cable is con nected properly to your computer and the FPGA hardware Also make sure that your FPGA hardware is connected to a power source and the power switch is turned on If the USB programmer is still not shown in the list close the hardware selection window and open it again you may need to repeat this procedure several times In fact simply retrying the failed operation helps in many cases for the Programmer not only the issues which are listed here Another way to get the Programmer working is to select Auto Detect or turning your development board off and on again If your USB Blaster did never show up in the list of available hardware components there might be a driver issue on your sys tem This could be because you ran the installation process as a non privileged user Also make sure that your USB Blaster is enlisted in Device Manager on Windows machines setting up the BSP After finishing all hard
27. see figure 1 14 Choose a name for your BSP project and select the path to the sopcinfo file which has been generated for your NiosII system The sopcfile should be located in your QuartuslI project folder You can change the location of the BSP be default it is saved in a subfolder of your Quartusll project folder Select the CPU you want to create the BSP for in case you have more than one CPU in your NioslI system A BSP can only be generated for one CPU at once If you have more CPUs in one hardware design you have to create a BSP for each processor Confirm your selection by pressing the Finish button of the BSP creation wizard Your BSP project will appear in the Project Explorer of the Nios2SBT Now we are creating the actual NiosII application project which uses the BSP that we just created Choose File New Nios II Application to open the 14 Glossary Nios I Application Nios I Application Create a new Nios I Software Build Tools application project Project name quartus_demo BSP location C Users martin Documents quartus_nios_demo software quartus_de Use default location Location C Users martin Documents quartus_nios_demo software quartus Additional arguments Command nios2 app generate makefile app dir bsp dir quartus_dermo_bsp elf name Use relative path Figure 1 15 the application creation wizard Nios II Application wizard see figure 1 15 Enter a name for your applic
28. t see section 1 1 4 We want to create an instance of the NioslI system that we created in section 1 1 4 Double click on an empty space in the newly created Block File The Symbol window appears In the Libraries pane on the left of the window choose your NioslI system by selecting Project qsys_nios_system Create the NiosII instance by clicking OK Place the NiosII block in your Block Diagram file with your mouse pointer You can see three wires leaving the gsys_nios_system e clk_clk the clock input to the NiosII system e reset_reset_n the reset input to the NiosII system e led_pio_external_connection_export 7 0 the output of the led_pio component This is an 8 bit wide wire as can be seen by the 7 0 range Now we have to connect these wires with input and output pins in the toolbar of the Block Diagram file open the menu of the Pin Tool option and select Input Now you should have Glossary ca Generate Completed Info cmd_xbar_mux qsys_nios_ system instantiated altera_merlin_multiplexer cmd a Info rsp_xbar_demux_002 qsys_nios_ system instantiated altera_merlin_demultiple Info rsp_xbar_mux qsys_nios_ system instantiated altera_merlin_multiplexer Tsp Info Reusing Tile CUsers martin Documents quartus_nios_demofqsys_nios_system Info rsp_xbar_mux_001 qsys_nios_system instantiated altera_merlin_multiplexer r Info Reusing file CvUsers martin Documents quartus_nios_demo qsys_nios
29. t None gt Default Parameters qsys_nios_system synthesi Verilog HDL File lt None gt Fitter Settings qsys_nios_system synthesi Verilog HDL File lt None gt TimeQuest Timing Analyzer qsys_nios_system synthesi Verilog HDL File lt None gt Assembler qsys_nios_system synthesi Verilog HDL File lt None gt Design Assistant qsys_nios_system synthesi SystemVerilog HDL File lt None gt SignalTap II Logic Analyzer qsys_nios_system synthesi SystemVerilog HDL File lt None gt Logic Analyzer Interface qsys_nios_system synthesi SystemVerilog HDL File lt None gt PowerPlay Power Analyzer Settings gsys_nios_system synthesi SystemVerilog HDL File lt None gt SSN Analyzer qsys_nios_system synthesi SystemVerilog HDL File lt None gt qsys_nios_system synthesi SystemVerilog HDL File lt None gt qsys_nios_system synthesi SystemVerilog HDL File lt None gt qsys_nios_system synthesi SystemVerilog HDL File lt None gt qsys_nios_system synthesi Verilog HDL File lt None gt qsys_nios_system synthesi Verilog HDL File lt None gt qsys_nios_system synthesi SystemVerilog HDL File lt None gt qsys_nios_system synthesi SystemVerilog HDL File lt None gt qsys_nios_system synthesi SystemVerilog HDL File lt None gt qsys_nios_system synthesi SystemVerilog HDL File lt None gt nmm minan nutans les mthaci CummtamUacilan Ul al Manns w b W Buy Software ok Cancel apy Hep F
30. the number 16 into the connection point Set the interrupt number of the timer_0 com ponent to 1 by applying the same procedure to the timer_O component Glossary T Nios I Processor Tk Nios Il Processor Megatore altera_nios2_qsys Block Diagram if C Show signals nios2_qsys_0 data_master Core Nios lI Caches and Memory Interfaces Advanced Features MMU and MPU Settings JTAG Debug Module an Documentation Select a Nios Il Core Nios Il Core Nios We Nios Ws Vi Nios Wf jtag_debug_module_rese on custom_instruction_master Nios Il Selector Guide Instruction Cache Branch Prediction Hardware Multiply Hardware Divide Instruction Cache Branch Prediction Hardware Multiply j Dynamic Branch Prediction Two M9Ks cache Three M9Ks cache Memory Usage e g Stratix IV Two M9Ks or equiv Hardware Arithmetic Operation Hardware multiplication type Embedded Multipliers Hardware divide Reset Vector Reset vector memory onchip_memory2_0 s1 v Reset vector offset 0x00000000 Reset vector 0x00000000 Exception Vector Exception vector memory onchip_memory2_0 s1 X Exception vector offset 0x00000020 Exception vector 0x00000020 MMU and MPU Include MMU Only include the MMU using an operating system that explicitly supports an MMU Fast TLB Miss Exc
31. u want to program should already be preselected Otherwise you can use the Add File button to add your sof file If your FPGA chip is not selected yet you can use the Add Device button to select your FPGA chip Make sure to select the correct chip number otherwise you risk damaging your hard ware If you are using a non licensed component in your hardware design you can still use that component but can only use it while your FPGA is connected to your Computer running 11 Glossary r A q Programmer C Users martin Dropbox Dokumente Master_Thesis quartus_stuff web_server_improved_rest els Search altera com KY Hardware Setup USB Blaster USB 0 Mode JTAG v Progress Enable real time ISP to allow background programming for MAX II and MAX V devices mh File Device Checksum Usercode Program Verify Blank Bu Start Configure Check pae DE2_115_WEB_SERVER_ EP4CE115F29 011F0F5C FFFFFFFF m A Auto Detect Qy Add File t3 Change File 4 me p z Save File A ct tb Up 4 u Down P EP4CE115F29 Figure 1 11 the main window of Programmer C Users martin Dropbox Dokumente Master_Thesis quartus_stuff web_server_improved_restored DE2_115_ WEB_SERVER_time_limited sof contains one or more time limited megafunctions that support the OpenCore Plus feature that will not work after the hardware evaluation time expires Refer to the Messag
32. ust exactly match the entity name in the design file quartus_nios_demo Use Existing Project Settings Ge Ga Gad Ge Figure 1 2 page 1 of the QuartusII New Project Wizard basic QuartusII project setup We assume that you have started an instance of QuartuslII Begin by creating a new QuartuslI project by selecting File New from the menubar and choosing New Quartus II Project from the window which opens This starts the New Project Wizard Fill in your project name and the top level design entity name remember this name carefully and name your top component exactly like this Now you just have to choose the working directory for this project QuartusII will not create a folder within the working directory so choose an empty folder Your project settings should like like figure 1 2 now If you have checked your input you can continue by choosing the Next button You can skip the Add Files Wizard page by selecting Next again On page three you have to select your exact model of FPGA device Choosing your FPGA device with caution as a wrong device setting could cause damage to the hardware For the DE2 115 development board that was used for this introduction we had to choose the EP4CE115F29C7 device see figure 1 3 To be sure which device is used in your board check the label on the FPGA chip see figure 1 4 You can skip page four by selecting Next 3 Pa
33. ware related aspects of this introduction into the DE2 115 FPGA we are ready to start working on the software Typically NiosII applications are devel oped using the Nios2SBT NiosII Software Build Tools a modified version of the eclipse Integrated Development Environment IDE NiosII applications usually consist of two parts 13 Glossary e the NiosII Board Support Package BSP a software library and runtime environ ment which is customized to a Central Processing Unit CPU in a hardware design e the NiosII application which is the program implementing the functionality required by the user and relying on functions provided by the BSP Nios I Board Support Package Nios I Board Support Package Create a new Nios I Software Build Tools board support package project Project name quartus_demo_bsp SOPC Information File name C Users martin Documents quartus_nios_demo qsys_nios_system sopcinfo Use default location Location C Users martin Documents quartus_nios_demo software quartus_demo_bsp BSP type Altera HAL BSP type version default Additional arguments Command nios bsp hal qsys_nios_system sopcinto cpu name nios2_qsys_0 Use relative path r Figure 1 14 the BSP creation wizard Start the Nios2SBT and select your workspace if you have not done so yet To create a new NioslI BSP select File New Nios II Board Support Package which will open the BSP creation wizard
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