Hitachi Flash Cards User`s Manual
Contents
1. x 7H Status Register Command Register A10 to A4 are optional addresses a Task File Register Mapping in Contiguous I O Map E bit7 bit6 bit5 bit4 bit3 bit2 bit1 bito Feature Register Sector Count Register Sector count 01H Sector Number Register Sector No ZZH Cylinder Low Register Cylinder No lower byte XXH Y Cylinder High Register Cylinder No upper byte YYH Drive Head Register 1 Leao 1 av 0 Head number OH Command Register Command 20H Y b Command Format AO to A3 4H Y 5H Yen Y au Y 2H Y 7H 7H OH 7H cg LI LI LI LIL Le OWL LL ey CE2 iy UU FE IOWR U LI LI LI Lu K EAS OD o LU LULL PL LJ LJ DOtoD15 4kxH YVHYAoH 2zH o1H 20H MI HHH EHH HI J 80H 80H 58H DO D2 D510 80H 80H 50H Di D3 D511 REQ A T Hm d Timing Chart Figure 4 6 Read Sector s 32 HITACHI bit7 bit6 bit5 bit4 bit3 bit2 bit bitO Status Register BSY DRDY DWF DSC DRQ CORR IDX ERR BSY busy Set at 1 during internal card processing DRDY drive ready Set at 1 after internal card processing has been completed and the drive has become ready for receiving access from the host DWF drive write fault Set at 1 when a write fault occurs inside the card DSC drive seek complete Set at 1 afte2. Repeats 256 times 512 bytes Reads the status register Compares with 50H b Command Format c Flow Chart O jat tp at Lati at 4H X 5H X 6H X 3H X 2H X 7H OT LLILI LI Lili 1 mok H cae MIT LIT LFLI LI LI Uy Acie AT LI 80H 80H 58H DO d Timing Chart 50H Quum 34 Figure 4 8 Write Sector s HITACHI Section 5 Format 5 1 Cylinder Head and Sector Since the Hitachi flash cards have one or some built in flash memories no physical configuration is reguired for the hard disk cylinders headers and sectors Since it is controlled using the ATA commands like the hard disk the same concept as for the disk also applies to the card format Before explaining the format the concept of the cylinders heads and sectors and the logical block address LBA for specifying the sector address are explained The third generation 8 Mbyte Hitachi flash card has one built in 64 Mbit Hitachi flash memory The data in this flash memory is read and written in 512 byte units This unit is called a sector and one flash memory has 15 744 sectors for reading and writing In addition to these sectors the memory has an alternative sector to be replaced with the sector which has failed during operation The 15 Mbyte card has two flash memories and the 30 Mbyte type has four Figure 5 1
3. wo 99 IF o Figure 2 1 Overall Dimensions of PC ATA Card HITACHI Unit mm 26 pin 50 pin vo 0000000000000 y y 1 60 0 05 060090000000000900000000 9 1 00 0 05 41 27 1pin Top 15 pin Brad D 1 00 0 08 1 00 0 08 S 42 80 0 10 enum F et eme o I 5 C H S a 8 E m S lo 1 I 2 40 0 08 co o a o D I O S 2 8 o e a o H oo Y lt e To E S S Hop 18 Eee NS EEE as RAS it Y To ME pO q 41 66 0 13 010 08 Figure 2 2 Overall Dimensions of CompactFlash HITACHI Table 2 1 PC ATA Card Pin Assignment Memory card mode I O card mode True IDE mode Input I Input 1 Input I Pin No Signal Output O Signal Output O Signal Output O 1 GND GND GND 2 D3 VO D3 O D3 I O 3 D4 VO D4 VO D4 VO 4 D5 O D5 I O D5 I O 5 D6 I O D6 O D6 I O 6 D7 VO D7 VO D7 VO T CE1 CE1 CE1 I 8 A10 l A10 A10 9 OE OE ATASEL 10 11 A9 I A9 A9 l 12 A8 l A8 A8 13 14 15 WE l WE WE I 16 RDY BSY O IREQ O INTRQ O 17 VCC VCC VCC 18 19 20 21 22 A7 A7 A7 23 A6 l A6 A6 24 A5 A5 A5 l 25 A4
4. 1 1 Introduction 1 2 Hitachi PC ATA Card 1 3 Hitachi CompactFlash 1 4 JEIDA and PCMCIA Section 3 Internal Card Configuration and Card Mode 3 1 Configuration Registers Section 4 Power Up Seguence and ATA Commands 4 1 Power up Seguence Appendixes A Pin Connection in True IDE Mode HITACHI Section 1 Hitachi Flash Cards 1 1 Introduction Hitachi flash cards are designed to 1 replace hard disks and 2 be embedded to various eguipment This manual is intended for those using Hitachi flash cards for these applications for the first time For this reason each item is not described in detail Refer to the data sheet or other related documents for detailed information Internal card configuration operating mode data transfer protocol and formatting at shipment are explained in the following chapters 1 2 Hitachi PC ATA Card PC cards are used to extend the functions of memories modems LANs and various equipment like laptop and notebook type computers are equipped with sockets for PC cards Such PC card standards as the physical electrical and interface specifications have been developed in cooperation with JEIDA Japan Electronic Industry Development Association and PCMCIA Personal Computer Memory Card International Association Although both these organizations previously issued standards separately they were unified into the PC Card Standard in 1995 and issued jointly issui PC cards are classified into the followi
5. A4 A4 26 A3 A3 A3 I 27 A2 A2 A2 I 28 A1 I A1 Al l 29 A0 I AO A0 30 DO I O DO I O DO I O 8 HITACHI Table 2 1 PC ATA Card Pin Assignment cont Memory card mode I O card mode True IDE mode Input I Input I Input I Pin No Signal Output O Signal Output 0 Signal Output O Si gt pp os Di Ot Di go 32 D2 VO D2 IO D2 VO 33 WP O IOIS16 O IOIS16 O 34 GND GND GND 35 GND GND GND 36 CD1 O CD1 O CD1 O 37 D11 VO D11 IO D11 VO 38 D12 VO D12 IO D12 VO 39 D13 I O D13 I O D13 O 40 D14 VO D14 IO D14 VO 41 D15 VO D15 IO D15 VO 42 CE2 CE2 l CE2 43 VS1 O VS1 O VS1 O 44 IORD IORD l IORD 45 IOWR IOWR l IOWR 46 47 48 49 50 51 VCC VCC VCC 52 53 54 55 56 CSEL CSEL CSEL 57 VS2 O VS2 O VS2 O 58 RESET RESET RESET 59 WAIT O WAIT O IORDY O 60 INPACK O INPACK O INPACK O HITACHI Table 2 1 PC ATA Card Pin Assignment cont Memory card mode I O card mode True IDE mode Input I Input 1 Input I Pin No Signal Output O Signal Output O Signal Output O 61 REG REG REG l 62 BVD2 VO
6. SPKR VO DASP VO 63 BVD1 I O STSCHG I O PDIAG O 64 D8 I O D8 O D8 I O 65 D9 I O D9 y o D9 I O 66 D10 I O D10 O D10 O 67 CD2 O CD2 O CD2 O 68 GND GND GND Table 2 2 CompactFlash Pin Assignment Memory card mode I O card mode True IDE mode Input Input I Input Pin No Signal Output O Signal Output O Signal Output O 1 GND GND GND 2 D3 O D3 I O D3 I O 3 D4 VO D4 VO D4 VO 4 D5 VO D5 O D5 I O 5 D6 I O D6 O D6 I O 6 D7 VO D7 VO D7 VO 7 CE1 l CE1 CE1 l 8 A10 l A10 A10 9 OE OE ATASEL 10 A9 I A9 A9 l 11 A8 l A8 A8 12 A7 l A7 A7 l 13 VCC VCC VCC 14 A6 l A6 A6 l 15 A5 l A5 A5 l 16 A4 l A4 A4 l 17 A3 A3 A3 10 HITACHI Table 2 2 CompactFlash Pin Assignment cont Memory card mode I O card mode True IDE mode Input I Input 1 Input I Pin No Signal Output O Signal Output 0 Signal Output O 18 A2 A2 l A2 19 A1 A1 l A1 20 A0 A0 l A0 21 DO O DO O DO I O 22 D1 VO D1 I O D1 VO 23 D2 VO D2 IO D2 y o 24 WP O IOIS16 O IOIS16 O 25 CD2 O CD2 O CD2 O 26 CD1 O CD1 O CD1 O 27 D11 VO D11 O D11 VO 28 D12 VO D12 IO D12 VO 29 D13 O D13 O D13 I O 30 D14 VO D14 IO D14 VO 31 D15 O D15 O D15 I O 32 CE2 CE2 l CE2 33 VS1 O VS1 O VS1 O 34 IORD IORD l IORD 35 IOWR I
7. b shows the concept of the hard disk cylinders heads and sectors for a third generation 8 Mbyte card The size of one sector is determined by the flash memory built in the card as follows 1 sector 512 bytes Considering that tracks are arranged concentrically around the disk assume as follows 1 track 32 sectors Also assume that data is recorded on both surfaces of the disk and the front surface is accessed by head 0 and the back surface by head 1 Since the tracks located away from the center by the same distance are called a cylinder one cylinder contains the same number of tracks as that of heads 1 cylinder 2 heads x 1 track 2 heads x 32 sectors Assuming that the number of cylinders is 246 the total number of sectors is as follows Total number of sectors 246 cylinders x 2 heads x 32 sectors 15 744 This equals to the number of sectors built in one flash memory Assuming that a 15 Mbyte card has two disks or four heads the total number of sectors is as follows Total number of sectors 246 cylinders x 4 heads x 32 sectors 31 488 35 HITACHI Assuming that a 30 Mbyte card has four heads or 492 cylinders the total number of sectors is as follows Total number of sectors 492 cylinders x 4 heads x 32 sectors 62 976 The numbers of the bytes cylinders and heads per sector of each byte count card are described in the identify drive information which can be read using the ATA command Cylinder
8. I O card mode the status when it is assigned to the I O address space The I O card mode is further divided into three mapping modes contiguous I O primary I O and secondary I O mapping modes depending on which address the task file registers are assigned to True IDE specification only has I O address space to which the task file registers are assigned This card mode is called the True IDE mode which has only one mapping mode Table 2 3 summarizes the relationship between the above card modes and task file registers assignment Chapter 3 explains 1 configuration registers 2 card information structure CIS 3 task file registers and 4 card mode in detail Chapter 4 explains 5 power up sequence after inserting the card in the slot and 6 data transfer protocol and Chapter 5 explains 7 default format ATA commands Task file registers Data area Figure 2 6 Task File Registers 15 HITACHI Table 2 3 Card Mode Interface specification PC card ATA specification Card mode Memory card mode Task file registers space mapping mode Common memory area memory map I O card mode I O address space contiguous I O map primary I O map secondary I O map True IDE specification True IDE mode HITACHI I O address space True IDE mode I O map Section 3 Internal Card Configuration and Card Mode 3 1 Configuration Registers The host i
9. 245 Cylinder 2 Cylinder 1 Alternative sector Head 0 Ru Cylinder 0 Sector 15 743 Sector 1 HI e Sector 3 Sector 2 a Hitachi 64 Mbit Flash Memory Configuration b Hard Disk Cylinder Head and Sector Configuration Address signal Sector address decoder Head 1 Sector 31 Sector 32 Output data Sector 1 Figure 5 1 Memory Configuration of Third generation 8 Mbyte Flash Card 5 2 Logical Block Address LBA Mode Both cylinder head sector address CHS and logical block address LBA mode can be selected using ATA commands Figure 5 2 shows the correspondence between both modes The figure refers to a third generation 8 Mbyte card the same as in the previous section With the CHS mode each sector assigned to the front and back surfaces of the disk is selected using the cylinder head and sector numbers With the LBA mode the first sector address is set as block 0 and the following sectors are serially numbered A general conversion formula from CHS to LBA is as follows LBA Cylinder No x Number of heads Head No x Number of sectors Sector No 1 Since the number of heads 2 and that of sectors 32 for the 8 Mbyte card in figure 5 2 LBA Cylinder No x 2 Head No x 32 Sector No 1 36 HITACHI Front surface Head 0 u Cylinder 0 Sector 31 corresponds to LBA 30 Sector 32 corresponds to LBA 31 Sector 1 corresponds to LBA 0 S
10. ATA specification is regulated by the PC Card Standard Simply inserting the card in the socket enables information written onto it to be read by the host and the card to be recognized as a flash ATA card The host then writes data onto the card to set the card operating mode The True IDE specification does not follow the PC Card Standard They were specified by changing the IDE hard disk interface specifications for card application and for handling cards as hard disks While PC card ATA specification requires cards to be recognized and operating mode to be set the True IDE specification does not thereby reducing the load on the host 1 3 Hitachi CompactFlash Because PC cards are too large for small lightweight equipment like digital cameras and hand held PCs several types of small memory cards are available The CompactFlash small memory card standard was proposed by SanDisk Corporation of the U S on which Hitachi CompactFlash is based The host interface is compatible with PC card ATA or True IDE specification the same as Hitachi PC ATA card Hitachi flash cards refer to the above PC ATA card and CompactFlash 1 4 JEIDA and PCMCIA PC card related standard has been established by JEIDA Japan Electronic Industry Development Association and PCMCIA Personal Computer Memory Card International Association since JEIDA started establishing standard for memory cards like SRAMs in 1985 In 1989 PC manufacturers in the U S es
11. HITACHI Section 2 Hitachi Flash Cards Overview 2 1 Comparison of PC ATA Card and CompactFlash The sizes of PC cards are classified into three types by thickness Type I to Type III and PC ATA cards are classified as Type II overall dimensions 54 0 x 85 6 x 5 0 mm The size of the CompactFlash is approximately one third of PC cards overall dimensions 42 8 x 36 4 x 3 3 mm Figures 2 1 and 2 2 show their overall dimensions Tables 2 1 and 2 2 show the pin assignments for the PC ATA Card and CompactFlash Since the functions of some pins vary depending on the card mode refer to Chapter 3 the tables show the signal names in each mode While only 50 of the 68 pins of the PC ATA card slot are used all 50 pins are used for the CompactFlash Because the electrical and interface specifications of Hitachi PC ATA Card and CompactFlash are standardized refer to the data sheet for detailed specifications since differences exist between generations PC ATA Card and CompactFlash are not differentiated between in the descriptions below Note that CompactFlash can also be used in the PC ATA card slot by mounting them in a PC card adapter HITACHI Surface A 54 00 0 10 pat A 85 60 0 20 Y Y 1 27 0 1 x i 68 pin 35 pin eet 1 27401 41 91 at Reference value Unit mm 5 0 max gt e Surface A 10 0 min
12. Hitachi Flash Cards User s Manual HITACHI oh Hitacf 4 semiconductor Notice When using this document keep the following in mind 1 2 This document may wholly or partially be subject to change without notice All rights are reserved No one is permitted to reproduce or duplicate in any form the whole or part of this document without Hitachi s permission Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user s unit according to this document Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi s semiconductor products Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi Ltd MEDICAL APPLICATIONS Hitachi s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi s sales company Such use includes but is not limited to use in life support systems Buyers of Hitachi s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS Contents Section 1 Hitachi Flash Cards
13. O map map map A9 to AO A9 to AO A3 to AO Task file register 1FOH 170H OH Data register 1F1H 171H 1H Error feature register 1F2H 172H 2H Sector count register 1F3H 173H 3H Sector number register 1F4H 174H 4H Cylinder low register 1F5H 175H 5H Cylinder high register 1F6H 176H 6H Drive head register 1F7H 177H 7H Status command register 8H Duplicate even data register 9H Duplicate odd data register DH Duplicate error feature register 3F6H 376H EH Alternate status device control register 3F7H 377H FH Drive address register In the True IDE mode I O mapping mode only three address signals of A2 to A0 in the I O address space are decoded as shown in table 3 4 and the CE2 signal is used to select the alternate status device control or drive address register and the CE1 to select other task file registers Table 3 4 Task File Registers Mapping at True IDE Mode True IDE Mode CE2 CE1 I O map A2 to A0 Task file register 1 0 OH Data register 1 0 1H Error feature register 1 0 2H Sector count register 1 0 3H Sector number register 1 0 4H Cylinder low register 1 0 5H Cylinder high register 1 0 6H Drive head register 1 0 7H Status command register 0 1 6H Alternate status device control register 0 1 7H Drive address register 24 HITACHI 3 4 Card Mode Table 3 5 summarizes card modes In the memory card mode the host configures the card using CIS and the configuration registers and c
14. OWR l IOWR 36 WE WE l WE 37 RDY BSY O IREQ O INTRQ O 38 VCC VCC VCC 39 CSEL CSEL CSEL 40 VS2 O VS2 O VS2 O 41 RESET RESET l RESET 42 WAIT O WAIT O IORDY O 43 INPACK O INPACK O INPACK O 44 REG REG l REG 45 BVD2 O SPKR IO DASP VO 46 BVD1 O STSCHG I O PDIAG I O HITACHI 11 Table 2 2 CompactFlash Pin Assignment cont Memory card mode I O card mode True IDE mode Input I Input 1 Input I Pin No Signal Output O Signal Output O Signal Output O 47 D8 O D8 I O D8 I O 48 D9 O D9 I O D9 O 49 D10 VO D10 I O D10 VO 50 GND GND GND 2 2 Interface Specifications Hitachi flash cards are eguipped with Hitachi AND type flash memories which are controlled by built in controllers For the interface between the controller and the host you can select either PC card ATA or True IDE specifications When turning the power on set the OE ATASEL pin at level H to select the PC card ATA specification or at GND to select the True IDE specification see figure 2 3 E PC card ATA or True IDE specifications PC card ATA specifications selected when the OE ATASEL pin is set at H level at power on As specified by the PC Card Card Standard the host recognizes the card and sets the operating mode Controller True IDE specifications selected when the OE ATASEL pin is set at GND at power on The card is handled
15. ace specification determined PC card ATA or True IDE specification There are three types of the card pin lengths in order to support hot insertion in PC card ATA specification see table 4 1 After inserting the card in the slot the power source and the ground pin reconnected first and the card detection pins CD1 and CD2 last Since CD1 and CD2 are connected to the ground inside the card the host can detect card insertion When the card is set in PC card ATA specification the host reads CIS from the card At this time power source voltage information is supplied to the host by the voltage sense pins VS1 and VS2 In order to indicate that CIS can be read both at 5 V and 3 3 V VS1 is connected to the ground inside the card and VS2 kept open The host is designed to recognize and configure the card based on the CIS information read Recognizing the card means determining the type manufacturer system resource to be used I O address IRQ signal and memory window and the kind of card The host adjusts and assigns the system resource to be used so as not to compete with other devices and sets an appropriate value in the configuration registers card configuration The card mode is determined by the value to be set in INDEX of the configuration optional register In the True IDE specification two connections namely the master and slave drives are allowed The drive is identified using the card select CSEL pin level followed b
16. and 4 5 show the CHS and LBA method command formats The Hitachi flash card supports 30 ATA commands The read and write sector commands are explained in 4 4 and 4 5 as typical ATA commands 30 HITACHI Feature Register Sector Count Register Sector Number Register Cylinder Low Register Cylinder High Register Drive Head Register Command Register bit bite bits bit bits Features bit biti bito Sector count Sector No Cylinder No lower byte Cylinder No upper byte Head No 1 ga d 1 orv Command Feature register Used when the host sets a particular function to the card Available only for writing data and not for reading Sector count register The host sets the number of sectors to transfer in this register The default setting is 01H The number of sectors are 256 when 00H is set Sector number register Sets the number of the sector where transfer starts Cylinder low register Sets the lower 8 bits of the number of the cylinder where sector transfer starts Cylinder high register Sets the upper 8 bits of the number of the cylinder where sector transfer starts Drive head register Sets the LBA DRV and head number When LBA 0 the cylinder head sector CHS mode is selected The DRV bit is used for selecting the master or slave configuration The card can be accessed when the DRV bit of the socket and copy register is equal to this bit Bit3 to bitO are us
17. as a hard disk in accordance with modified IDE specification for card IDE specification is one of hard disk interface specification Hitachi AND type flash memories Figure 2 3 Interface Specifications 12 HITACHI 2 3 Address Space With the PC card ATA specification interface the memory and I O address spaces can be seen from the host as shown in figure 2 4 Writing and reading are controlled by the OE and WE signals in the memory address space and by the IORD and IOWR signals in the I O address space The memory address space is further divided into attribute and common memory areas The attribute memory area includes a configuration registers used for setting the card operating mode and card information structure CIS describing information for recognizing the card type The common memory area can contain a task file registers for communicating data with the host Use the REG signal to switch between the attribute and common memory areas Set this signal at level L to access the attribute memory area or at level H for the common memory area Task file registers can also be assigned to the I O address space Whether it is assigned to the I O address space or the common memory area is determined by the host The True ID specification only has an I O address space so no memory address space is available figure 2 5 The task file registers are assigned to the I O address space and the configuration reg
18. ector 2 corresponds to LBA 1 Sector 3 corresponds to LBA 3 Back surface Head 1 Lu Cylinder 0 Sector 31 corresponds to LBA 62 Sector 32 corresponds to LBA63 Sector 1 corresponds to LBA 32 Sector 2 corresponds to LBA 33 sector 3 corresponds to LBA 34 Front surface Head 0 umm Cylinder 1 Sector 31 corresponds to LBA 94 Sector 32 corresponds to LBA 95 Sector 1 corresponds to LBA 64 Sector 2 corresponds to LBA 65 Sector 3 corresponds to LBA 66 Correspondence Between CHS and LBA Address Specification with LBA mode Address specification with CHS mode Block No 15 742 Figure 5 2 Logical Block Address Mode for Third generation 8 Mbyte Flash Card HITACHI 37 5 3 Formatting The hard disk is formatted by the following three procedures 1 Low level formatting 2 Partition setting 3 Partition formatting Low level formatting refers to preparing tracks on the disk and dividing them into sectors partition setting to dividing the hard disk into areas called partitions and partition formatting to preparing operating system boot information and data areas The above three procedures can apply also to formatting of the Hitachi flash cards Since the card has a built in flash memory and the sector address and size has already been determined it can be assumed that low level formatting has already been completed and thus cannot be c
19. ed P 0H WP signal not used B OH BVD1 and BVD2 signals not used IF type OH Memory interface TPCE FS M 1H Other function information A1H remains MS 1H Memory address space mapping specified by 2 bytes IR OH Interrupt not used IO OH IO space not used T 0H No timing related setting P 1H Only information describing VCC conditions exists TPCE PD NV 1H Parameter selecting byte of 01H other O standard operating power supply voltage VCC normal value 55H Standard operating power supply voltage 5 V TPCE MS 0008H Memory space window size 2 Kbyte TPCE MI 20H X OH End of extension byte R 0H Reserved P 1H Supports power down mode RO OH No read only A OH Audio function not used T 2 0H Only one card can be set the HITACHI same 21 3 3 Task File Registers Data is transferred between the host and the card and the transfer controlled via the task file registers The task file registers refer to the following series of registers 1 Data register 2 Error register 3 Feature register 4 Sector count register 5 Sector number register 6 Cylinder low register 7 Cylinder high register 8 Drive head register 9 Status register 10 Alternate status register 11 Command register 12 Device control register 13 Drive address register These registers are divided into five mapping modes 1 memory mapping 2 primary I O mapping 3 secondary I O mappi
20. ed to set the number of the head where sector transfer starts Figure 4 4 CHS Mode Command Format Feature Register Sector Count Register Sector Number Register Cylinder Low Register Cylinder High Register Drive Head Register Command Register bit bite bits bit4 bits bito Features bit2 bit Sector count Logical block address A07 to A00 Logical block address A15 to A08 Logical block address A23 to A16 DRV Logical block address A27 to A24 Command Sector number register Sets the address of the logical block A07 to A00 where sector transfer starts Oylinder low register Sets the address of the logical block A15 to A08 where sector transfer starts Cylinder high register Sets the address of the logical block A23 to A16 where sector transfer starts Drive head register When LBA 1 the logical block address LBA mode is selected Bit3 to bitO are used to set the address of the logical block A27 to A24 where sector transfer starts Figure 4 5 LBA Mode Command Format 4 4 Read Sector s Command Procedure The read sectors s command is designed to transfer data of the 1 to 256 sectors set by the sector count register in the sector set by the sector number register from the card to the host Figure 4 6 summarizes the read sector s command procedure for the card set in the I O card mode contiguous I O map First set values in the upper and lower bytes of the cylinde
21. erating system controls the card via this driver The ATA commands used here are explained in the next section The operating system provides the application program with general file operating functions In the True IDE mode no software corresponding to the socket and card services is available since there is no card recognition or configuration figure 4 3 b The card is also controlled using ATA commands in this mode as in the memory or I O card mode 29 HITACHI Application program Application program Y Operating system Operating system Software NS EM Card service client L Software Device driver driver Card service Socket service AIS AS PCMCIA controller PCIC Hardware IDE controller Hardware Hitachi flash card Hitachi flash card a Memory or I O card mode b True IDE mode Figure 4 3 Host Configuration 4 3 ATA Commands The task file registers are used to execute such functions as reading and writing of the Hitachi flash card A command is executed by setting parameters relating to it in up to six task file registers and command codes in the command register in this order The modes for setting the card address are the cylinder head sector CHS and the logical block address LBA modes refer to section 5 for these modes Set bit6 LBA of the drive head register at O to select the CHS mode or 1 to select the LBA mode Figures 4 4
22. guration of the card when writing this value is described in the configuration entry tuple Table 3 2 shows a typical configuration entry tuple in the memory card mode at a power supply voltage of 5 V There are other tuples in the memory card mode at a power supply voltage of 3 3 V and in the I O card mode at a power supply voltage of 5 V or 3 3 V Table 3 2 Typical CISs Address Tuple Contents Description 000H to Device information TPL_CODE 01H Tuple ID 01H OOAH tuple TPL_LINK 04H Next tuple pointer O4H common memory Device ID Device type I O device CISTPL_DEVICE DFH DH WPS 1H Write disable switch function disabled Device speed Extension device speed enabled 7H Extended speed 4AH Extension device speed 400 ns Device size 01H 2 Kbyte address space List end marker FFH End of tuple 020H to Manufacture ID tuple TPL CODE 20H Tuple ID 20H 02AH CISTPL_MANFID TPL_LINK 04H Next tuple pointer 04H TPLMID_MANF 0007H Manufacture ID cord 0007H Hitachi TPLMID_CARD 0000H Manufacture information 0000H 19 HITACHI Table 3 2 Address 02CH to 058H Typical CISs cont Tuple Level 1 version product information tuple CISTRPL_VERS_1 Contents TPL_CODE 15H Description Tuple ID 15H TPL_LINK 15H Next tuple pointer 15H TPLLV1_MAJOR 04H TPLLV1_MINOR 01H Basic compatible layer layer 1 complies with the PCMCIA2 0 JEIDA4 1 standa
23. hanged For the Hitachi flash cards a partition is created before shipment followed by formatting When using the card partition setting and formatting can be changed Before explaining partition the FAT file system is simply explained 5 4 FAT File System The FAT file system is adopted by MS DOS and some other operating systems Although the sector is the minimum unit for reading from and writing to the hard disk this file system combinedly controls several sectors called a cluster The file area area for storing files is divided into clusters to secure entries which correspond to each cluster one by one All entries are located in the file allocation table FAT and data stored in each entry indicates cluster combination and usage conditions The 12 bit FAT refers to the case when these entries are 12 bits and the 16 bit FAT to the case when these entries are 16 bits The size of the root directory area where files and directory entries can be stored is determined at formatting Directory entries refer to 32 byte data which indicates such information as file name and attribute 5 5 Partition Setting Figure 5 3 shows the partition default settings of the third generation 8 Mbyte card Data called the master boot record MBR is written in the first sector LBA 0 of the card The partition entry which describes the partition type size and the kind is included in the MBR The type in figure 5 3 forms one partit
24. ical case where 512 byte data is transferred by 256 word writes The status register turns to 50H after data transfer is completed waiting for a next command 33 HITACHI A10 to A4 are optional addresses a Task File Register Mapping in Contiguous I O Map Feature Register Sector Count Register Sector Number Register Cylinder Low Register Cylinder High Register Drive Head Register Command Register AO to A3 CE1 CE2 IOWR IORD DO to D15 IREQ bit7 bit6 bit5 bit4 Address Read Write Ai0to A4 A3to AO ORD L IOWR L x 4H Cylinder Low Register Cylinder Low Register x 5H Cylinder High Register Cylinder High Register x 6H Drive Head Register Drive Head Register x 3H Sector Number Register Sector Number Register x 2H Sector Count Register Sector Count Register x 7H Status Register Command Register bit3 bit2 bitt Sector count 01H Sets XXH in the cylinder low register Sets YYH in the cylinder high register Sets AOH in the drive head register Sets ZZH in the sector number register Sets 01H in the sector count register Sets 30H in the command register TP Reads the status register Compares with 58H Writes the data register Sector No ZZH Cylinder No lower byte XXH Cylinder No upper byte YYH 1 B o 1 Pav d Head number 0H Command 30H
25. ing the Write Sector s command 6 What state will be assumed after writing to the card has been interrupted The state to wait for data will be assumed until 512 byte data is transferred 7 How does the Format Track ATA command function Although the Format Track command of the hard disk is designed to reformat a track and initialize a data field that of the Hitachi flash cards is a NOP command and thus conducts no operation 8 What is the difference between the Read Long Sector and Read Sector s ATA commands 512 byte data is transferred by the Read Sector s command and 516 byte data by the Read Long Sector command Since the latter command executes ECC in the host four more bytes of data are transferred Since the Hitachi flash cards internally execute ECC however no Read Long Sector command is required 43 HITACHI
26. ion of the specified size from LBA 32 to LBA 15 679 called MS DOS 12 bit BPB FAT The size and type differ depending on the card capacity 38 HITACHI MS DOS is resistered by Microsoft 32 sectors 15 648 sectors 64 sectors o o e O o O R N 1 19 i or oo Il ll ol ll Il Il lt lt q lt q lt lt q lt m a nm e ea e E ud eb cc Partition c erased Type MS DOS 12 bit BPB FAT Figure 5 3 Third generation 8 Mbyte Flash Card Partition 5 6 Partition Formatting The third generation 8 Mbyte card has one partition of the MS DOS 12 bit BPB FAT type After formatting this partition data called the partition boot record PBR is written in the first sector of the partition and information called the BIOS parameter block BPB is described in the PBR where the following information is described 1 Number of sectors per cluster 2 Number of sectors per FAT 3 Number of FATs 4 Number of directory entries storable in the root directory area FATs are written in the sectors following where PBRs are written and the root directory area is secured in the sectors following the above sectors The default settings of the 8 Mbyte card are as follows 1 number of sectors per cluster 8 2 number of sectors per FAT 6 3 number of FATs 2 and 4 number of directory entries storable in the root directory area 512 Following PBRs two FATs of 6 sectors each are w
27. isters and card information structure CIS cannot be seen from the host 13 HITACHI Host Address bus OE Control signals Memory address space attribute and common memory areas I O address space Attribute memory area Memory address space Configuration registers and Accessed by OE and WE signals card information structure CIS Address space Common memory area I O address space Task file registers Accessed by IORD and IOWR signals Task file registers Figure 2 4 PC card ATA Specification Address Space E Host Card Address bus Control signals I O address space Address space I O address space Accessed by IORD and IOWR signals Task file registers Figure 2 5 True IDE Specification Address Space 14 HITACHI 2 4 Card Mode Reading from or writing to the host is executed by transmitting ATA commands to the task file register see figure 2 6 The data in the data area is also transmitted via the task file register The host cannot directly communicate data with the card data area This method is common to both PC card ATA and True IDE specifications With the PC card ATA specification the task file registers are assigned to the common memory area or the I O address space The memory card mode refers to the status when it is assigned to the common memory area and the
28. ly one card is used as the master drive example Card IDE interface AO 2 D0 7 15 CE1 CE2 IORD IOWR RESET IORDY INTRO IOIS16 OPEN DASP OPEN PDIAG OPEN INPACK YYvvYvvv CSEL L Master Mode A3 10 ge OE ATASEL GND GND WE REG VCC VCC MPU For Card detection CD1 i CD2 VS1 VS2 Note In this case slave drive should not be accessed 41 HITACHI 2 Pin connection when two cards are used as the master and slave drives example IDE interface A0 2 D0 7 15 CS0 CS1 IORD IOWR RESET IORDY INTRQ IOIS16 VCC MPU For Card detection t a ml ru at Card in the master drive AO 2 DO 7 15 CE1 CE2 IORD IOWR RESET YYvYvv IORDY INTRQ IOIS16 DASP a GND PDIAG lt OPEN INPACK CSEL A3 10 OE ATASEL GND OPEN 4 OPEN 4 Card in the slave drive AO 2 D0 7 15 CE1 CE2 IORD IOWR RESET IORDY INTRO IOIS16 DASP PDIAG INPACK CSEL A3 10 OE ATASEL GND 42 HITACHI B Typical Ouestions and Answers 1 What will happen if power break occurs during writing Although no phy
29. memory 4H Cylinder Low Register 3H Sector Number Register KL ja gene 2H Sector Count Register Host memory address space 1H Error Feature Register Data Register Task File Registers Mapping Figure 3 3 Memory Mapping Mode In the primary or secondary I O mapping mode the register functions as the I O card to be accessed via 1 FOH to 1F7H and 3F6H to 3F7H primary or 170H to 177H and 376H to 377H secondary in the standard I O address space Address signals of A9 to AO are used for access and A10 neglected In the contiguous I O mapping mode only four address signals of A3 to AO in the I O address space are decoded Thanks to this function those other than A3 to AQ can be accessed via any address although host operation is required Table 3 3 shows task file registers mapping in the I O card mode The contiguous I O mapping mode has the data and error feature registers as well as the duplicate even data duplicate odd data and duplicate error feature registers The data register can be accessed as 16 bit data combining 8 bit data indicated by an even address and 8 bit data indicated by an odd address Since the data register overlaps the error feature register when handled as 16 bit data registers duplicating them are equipped 23 HITACHI Table 3 3 Task File Registers Mapping at I O Card Mode Primary I O Secondary I O Contiguous I
30. ng 4 contiguous I O mapping and 5 True IDE mode I O mapping according to the address spaces to which these registers are assigned The mapping mode is selected after the host writes a value in INDEX of the configuration optional register Each mapping mode is explained below In the memory mapping mode the task file registers are assigned to the common memory area see figure 3 3 below As described in CIS TPCE_FA and TPCE_MS of the configuration entry tuple the memory window size is set at 2 Kbyte and the card base address at OH This window can be mapped to any address in the memory address space of the host The position of the task file registers is determined by the offset address from the card base address The 1 Kbyte memory window from offset 400H to 7FFH is secured for the host to access the data register during block transfer from memory to memory Since this 1 Kbyte memory window accesses FIFO data cannot be accessed randomly 22 HITACHI Odd Data Register Even Data Register High address High address Drive Address Register Alternate Status Device Control Register DH Duplicate Error Feature Register ee 9H Duplicate Odd Data Register 2Kbyte Card base address 8H Duplicate Even Data Register Optional host address OH 7H Status Command Register ins E onades 6H Drive Head Register 5H Cylinder High Register Card common
31. ng two types 1 Memory cards Flash memory card SRAM card ROM card etc 2 I O cards Flash ATA card HDD card modem card LAN card etc Memory card is used as ordinary memories in order to extend memory capacity and I O cards as peripherals for extending functions Hitachi s PC ATA flash card is classified as an I O card The built in controller is designed to precisely control data writing into the flash memory achieving the same interface as a hard disk Thanks to this function the minimum data reading and writing unit is one sector 1 sector 512 bytes and not one byte 8 bits like memory Unlike hard disks this card has no driving system such as disks or heads and features 1 low power consumption 2 high speed operation and 3 vibration resistance The flash memory card mentioned here refers to one that is not designed to internally control data writing into the built in flash memory but to achieve an interface as the memory while the HDD card refers to one having a small rotating magnetic hard disk HITACHI The physical specifications of Hitachi PC ATA card e g card dimensions and connector shapes are in accordance with the PC Card Standard The device like notebook laptop type computer which controls the cards is called the host and the following is the two types of specifications for the interface between the host and the card 1 PC card ATA specification 2 True IDE specification PC card
32. ommunication between the host and the card are conducted by the task file registers mapped in the 2 Kbyte window in the memory address space In the I O card mode configuration is conducted in the same way as in the memory card mode and the task file registers are mapped to the I O address space The True IDE mode does not have configuration function and the task file registers are mapped in the I O address space selected by address signal A2 to AO CE2 and CE1 Table 3 5 Card Mode Card mode Configuration registers and CIS Task file registers Memory card mode Exists in the attribute area in the Exists in the common memory area memory address space in the memory address space I O card mode Exists in the attribute area in the Exists in the I O address space memory address space True IDE mode None Exists in the I O address space 25 HITACHI Section 4 Power Up Seguence and ATA Commands 4 1 Power up Sequence Figure 4 1 shows the flow overview from inserting the card to determining the card mode Since hot insertion is supported in the memory or I O card mode the card can be inserted after the host power is turned on In the True IDE mode the host power should be turned on after the card is inserted In either mode power on is reset by the reset signal first generated by the reset IC built into the card During card default processing after the above operation the ATA select OE ATASEL pin level is detected and interf
33. on indicated by bit5 to bitO is explained here Configuration refers to setting the operating environment for such modes as card and mapping Either mode is selected after the host writes a value in INDEX The card status corresponding to each INDEX value is described in the configuration entry tuple in CIS For this purpose the host needs to read CIS before configuration Table 3 1 shows card and mapping modes corresponding to INDEX values Refer to 3 3 Task File Registers for mapping mode For other configuration functions refer to the data sheet 17 HITACHI Table 3 1 Correspondence Between INDEX and Card Mode INDEX bit5 bit4 bit3 bit2 bit1 bitO Card mode Mapping mode 0 0 0 0 0 0 Memory card mode memory map 0 0 0 0 0 1 I O card mode contiguous I O map 0 0 0 0 1 0 I O card mode primary I O map 0 0 0 0 1 1 I O card mode seconday I O map 3 2 Card Information Structure CIS Card Information structure CIS is assigned at even addresses to the attribute memory area the same as for configuration register CIS forms information unit called a tuple and the first tuple starts from address OOOH Each tuple holds data indicating the position of the next tuple pointer to the next tuple and is configured in chains The last tuple is called the End of list tuple indicating that there are no more tuples to follow As shown in figure 3 2 each tuple starts from the tuple ID and next tuple pointer da
34. r drive seek has been completed DRQ data request Set at 1 after data transfer between the host and the data register has become ready CORR corrected data Set at 1 after an error occurring during internal card processing has been corrected IDX index Always set at 0 ERR error Set at 1 when an error occurs during processing according to the input command This bit is cleared after a next command is input Figure 4 7 Status Register 4 5 Write Sector s Command Procedure The write sector s command is designed to transfer data of the 1 to 256 sectors set by the sector number register in the sector set by the sector count register from the host to the card As in the previous section figure 4 8 summarizes the write sector s command procedure for the card set in the I O card mode contiguous I O map First set values in the upper and lower bytes of the cylinder number the sector count and number and the drive head register The host sets 30H in the command register to request command execution The card sets the BSY in the status register at 1 after receiving the command After internal processing has been completed BSY turns to 0 and DRDY DSC and DRQ to to enable data transfer indicating that access from the host becomes available After this the host writes data in the data register 256 times Each access of word byte or odd number byte is available for the data register Figure 4 8 shows a typ
35. r number the sector count and number and the drive head registers The feature register needs not to be set since it is not referred to The host sets 20H in the command register to request command execution The card sets the BSY in the status register at 1 after receiving the command See 31 HITACHI figure 4 7 for the status register When BSY 1 internal card processing is executed After the processing has been completed BSY turns to 0 and DRDY DSC and DRQ to 1 to enable data transfer indicating that access from the host becomes available In short the host waits until the status register value turns from 80H to 58H After this the host reads data in the data register 256 times Each access of word byte or odd number byte is available for the data register Figure 4 6 shows a typical case where 512 byte data is transferred by 256 word reads The status register turns to 50H after data transfer is completed waiting for a next command Address Read Write d A10 to A4 A3 to AO IORD L IOWR L Sets XXH in the cylinder low register x 4H Cylinder Low Register Cylinder Low Register Sets YYH in the cylinder high register Sets AOH in the drive head register x x Drive Head Register Drive Head Register x 3H Sector Number Register Sector Number Register Sets ZZH in the sector number register x 2H Sector Count Register Sector Count Register Sets 01H in the sector count register
36. rds Manufacturer name string HITACHI Product name string FLASH Additional info 3 0 Indicates the third generation Hitachi flash card List end marker FFH End of tuple O5AH to Function class TPL_CODE 21H Tuple ID 21H 060H ID tuple TPL LINK 02H Next tuple pointer 02H CISTPL FUNCID TPLFID FUNTION 04H PC card ATA System Reserve OH Reserved initialization R 0H No BIOS ROM byte 01H P 1H Configuration processed at power on self test 074Hto Configuration tuple TPL CODE 1AH Tuple ID 1AH 080H CISTPL CONF TPL LINK 05H Next tuple pointer 05H TPCC SZ TPCC RFSZ Reserved 01H 0H TPCC RMSZ This value 1 is equal to byte OH count of TPCC_RSVD field TPCC_RASZ This value 1 is egual to byte 1H count of TPCC_RADR field TPCC_LAST 03H Last index No 03H TPCC_RADR 0200H Configuration register base address 0200H TPCC_RMSK OFH 4 configuration registers exist 20 HITACHI Table 3 2 Address 082H to 094H Typical CISs cont Tuple Configuration entry tuple CISTPL_CFTABLE_ ENTRY Contents TPL_CODE 1BH Description Tuple ID 1BH TPL_LINK 08H Next tuple pointer 08H TPCE_INDX 1H Followed by interface description COH field D 1H Default setting INDEX 00H Memory card INDEX TPCE_IF W 0H WAIT signal not used COH R 1H Ready busy signal enabl
37. ritten Since the FAT is 12 bits each cluster in the file area is specified in 12 bit units For the root directory entry area 32 sectors are secured so as to store 512 32 bit root directory entries see figure 5 4 39 HITACHI 15 603 sectors 13 sectors 32 sectors 1 950 clusters 3 sectors O D ce N e oo o wr 10 om LO e m oo rw DD I Il ofl nu I nu dg Il aX lt lt lt q atc tic lt x a cd co c c n om co l eJ Root directory area File area Figure 5 4 Third generation 8 Mbyte Flash Card Partition Configuration 5 7 Memory Density After Formatting The Hitachi flash cards partition has already been formatted before shipment The file area as shown in figure 5 4 is displayed as the all disk area when checking the card memory space of this state using functions like the MS DOS CHKDSK command Since 8 sectors 1 cluster for the third generation 8 Mbyte card the file area is as follows File area 15 679 76 sectors 15 603 sectors 1 950 clusters 3 sectors And accordingly All disk area 1 950 clusters x 8 sectors x 512 bytes 7 987 200 bytes 40 HITACHI Appendixes A Pin Connection in True IDE Mode There are two ways of using the Hitachi flash cards in the True IDE mode namely using only one card as the master drive and using two cards as the master and slave drives Pin connection in each method is described below 1 Pin connection when on
38. s designed to set the PC card operatign environment according to its own configuration after the PC card is inserted Hitachi flash cards have the following four configuration registers 1 Configuration option register 2 Configuration status register 3 Pin replacement register 4 Socket copy register The sizes of these registers assigned at even addresses to the attr bute memory area are 1 byte These addresses are specified by the base address written in TPCC_RADR in CIS and each register is allocated starting from base address 200H to the next two added addresses 202H 204H Figure 3 1 shows the configuration registers assignment d bit5 bit4 bi bit2 biti 206H Socket copy register 0 0 0 0 Pin replacement bit7 bit5 bit4 bi bit bit register 0 CRDY BSY 0 1 1 RRDY BSY Displays the statuses of the pins whose use varies between the memory and I O card modes 16 33 62 and 63 pins Configuration status bit7 bit6 bit5 bit4 bi bit2 bit register CHGED SIGCHG IOIS8 0 0 PWD INTR Holds information relating to card statuses 204H 202H 200H Configuration option bit7 bite bit5 bit4 bit3 bit2 bit bito register JSRESET LevIREQ INDEX id bit7 conducts soft reset and bit6 selects either level or pulse interrupt Attribute memory area Figure 3 1 Configuration Registers The configuration option register has three independent functions The INDEX functi
39. sical damage is applied to the chip no chip or sector breakage a logical error occurs in the corresponding sector disabling written data If the failed sector belongs to a file the file may seem to break It can be reused after formatting it again 2 How does the reading or writing procedure differ between the cylinder head sector address CHS and logical block address LBA mode Set bit6 of the drive head register one of the task file registers at O to select the CHS mode or 1 to select the LBA mode The sector where transfer starts is specified as follows for each mode Task file register CHS mode LBA mode Sector number register Sector No Logical block address A07 to A00 Cylinder low register Cylinder No lower 8 bits Logical block address A15 to A08 Cylinder high register Cylinder No upper 8 bits Logical block address A23 to A16 Bit3 to bitO of drive head register Head No Logical block address A27 to A24 3 Can data be written starting from the middle of a sector No Writing is available only in 1 sector units 4 Data of more than 512 bytes can be written at one time As many number of sectors as specified by the sector count register can be written when executing the Write Sector s command 5 Is a sector required to be erased before writing data Since executing the Write Sector s command erases the sector before writing data no Erase Sector s command is required before execut
40. ta followed by unique data 1st tuple 2nd tuple i 3rd tuple y End of tuple chain Address Data Meaning Tuple ID CISTPL DEVICE Indicates a device information 000H 01H tuple common memory 002H 04H Next tuple pointer Indicates a 4 byte tuple link Unique data Disables I O device and write disable 004H DFH switch functions 006H 4AH Unique data Extension device speed 400 ns 008H 01H Unique data 2 Kbyte address space 00AH FFH Indicates the end of the tuple Tuple ID Indicates an additional device 00CH 1CH CISTPL DEVICE OC information tuple common memory 18 Figure 3 2 CIS Configuration and Tuple Format HITACHI CIS information is reguired when the host recognizes or configures card Table 3 2 shows the following typical tuples 1 Device information tuple Describes device speed type and capacity 2 Function class ID tuple Information relating to card manufacturer 3 Level 1 version product information tuple Contains information on manufacturer etc 4 Function class ID tuple Describes card function information 5 Configuration tuple Describes the position and contents of the configuration register 6 Configuration entry tuple Describes card configuration and its variation The INDEX value of TPCE_INDEX in the configuration entry tuple corresponds to the value to be written in INDEX of the configuration optional register The confi
41. tablished PCMCIA Although PCMCIA and JEIDA cooperated in establishing JEIDA Ver 4 0 PCMCIA 1 0 in 1990 to covered only memory cards Since I O card specifications were specified by PCMCIA 2 0 established in 1991 such cards as modem and LAN cards have been widely used to extend the memories and functions of notebook PCs JEIDA Ver 4 2 PCMCIA 2 1 established in 1993 specified software for using PC cards And in 1995 the standards were unified into the PC Card Standard to which several more standards have been and will continue to be added HITACHI JEIDA and PCMCIA can be contacted at Japan Electronic Industry Development Association Personal Computer Operation Committee and IC Memory Card Applied Technology Special Committee 3 5 8 Shiba koen Minato ku Tokyo Japan Tel 03 3433 1923 Personal Computer Memory Card International Association 2635 North First Street Suite 209 San Jose CA 95134 USA 15 CFA The CompactFlash small flash memory card standard was proposed by SanDisk Corporation of the U S which is promoted by CFA CompactFlash Association CompactFlash a trademark of SanDisk Corporation of the U S is licensed to CFA The size of the CompactFlash is approximately one third of that of a PC card Its electrical and interface specifications comply with PC card ATA and True IDE specifications CFA can be contacted at CompactFlash Association PO Box 51537 Palo Alto CA 94303 http www compactflash org
42. vel has to be set before supplying VCC until resetting is completed Setting the pin at level H sets the memory or I O card mode and at GND the True IDE mode In the True IDE mode the master and slave drives are identified by the CSEL pin which is pulled up inside the card The level of this pin must also be set before supplying VCC until resetting is completed the same as for the OE ATASEL pin Setting it at level L sets the master drive and opening it sets the slave drive 28 HITACHI Card insertion Resetting completed CD1 CD2 pin rat Power on after the host has detected the card Power supply VCC Power on reset lt gt Power on reset internal card signal Reset RESET pin pr i W r 4 Level set before W Level set until resetting power on is completed OE ATASEL pin SRY CSEL pin TEES True IDE mode Level set at Figure 4 2 Timing Chart at Power on 4 2 Host Configuration Figure 4 3 a shows the host configuration in the memory or I O card mode The card inserted in the slot is connected to the PCMCIA controller PCIC The socket service provides the card service with an interface which is not dependent on PCIC The card service has host system resource control functions and configures the card The card service client driver corresponds to the device driver After configuring the card the op
43. y default processing In this way the True IDE mode is determined only by the states of the OE ATASEL and CSEL pins 27 HITACHI The PC card ATA specification supports hot insertion Hot insertion PC card ATA specification PC card ATA specification Start Host power on Card insertion True IDE specification Start Card insertion Host power on OE ATASEL HA Y OE ATASEL GND The True IDE specification does not support hot insertion True IDE specification Configuration optional register INDEX value CSEL pin level JINDEX 00H INDEX 01H J INDEX 02H J INDEX 08H cse GND jo OPEN Y Memory card I O card VO card I O card True IDE True IDE mode mode mode mode mode mode Memory map Contiguous I O map Primary I O map Secondary I O map Master drive Slave drive Figure 4 1 Power up Seguence and Card Mode Table 4 1 Pin Length Pin type Pin length Power and ground pins VCC and GND 5 00 0 10 mm Card detection pins CD1 and CD2 3 50 0 10 mm Other signal pins 4 25 0 10 mm Figure 4 2 shows the timing chart at power on Card insertion is detected when the CD1 and CD2 pins are turned to level L starting power VCC supply If VCC has already been supplied before detected card there is possibility that mode setting is disabled In order to set the card mode the OE ATASEL pin le
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