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USP-2 Hardware Manual

1. GND 1 BRO 1 2 SELO 1 3 SINT1 4 DO 5 D2 6 D4 7 INT2 8 D6 9 D8 10 D10 11 INT3 12 D12 13 D14 14 D16 15 INT4 16 D19 17 D21 18 D23 19 INT5 20 D25 21 D27 22 D29 23 INT6 24 D31 25 SIZO 26 SIZ2 27 INT7 H 28 PA2 30 PA4 31 LERR 32 PA6 33 PA8 34 PATO 35 ACKO 36 A12 37 A14 38 A16 39 ACK 40 A18 41 A20 42 A22 43 ACK2 44 A24 45 A26 46 DP 47 12V 48 49 CLKO 1 50 BGO 1 51 AS 52 GND 53 D1 54 D3 55 D5 56 5V 57 D7 58 D9 59 D11 60 GND 61 D13 62 D15 63 D17 64 5V 65 D18 66 D20 67 D22 68 GND 69 D24 70 D26 71 D28 72 5V 73 D30 74 SIZ1 75 RD 76 GND 77 A1 78 A3 79 AS 80 5V 81 A7 82 A9 83 A11 84 GND 85 A13 86 A15 87 A17 88 5V 89 A19 90 A21 91 A23 92 GND 93 A25 94 A27 95 RST 96 12V Figure 8 4 SBus Connectors 1 and 2 Pinouts Themis Computer 8 13 USP 2 Hardware Manual 8 5 Paddle board connectors TTY C D SUN KEYBOARD MOUSE D89S J0602 yo N y 0 C0602 8 A S MIT E nnn pees SHE E ao FEE o 000 o coo EN coo ee 0 90 000 ga 000 ef ooo o 0 9 000 e coer 000 e 0 eya 000 000 7 0 ooo 7000 7
2. Power POWER OK DSC UPA XIR L Supply SYS RESET L Software P Error UPA RESET L lt 0 gt Processor s and pp BUTTON POR P_RESET_L Wakeup Push RIC Reset Button BUTTON_XIR X RESET L aa ee UPA Scan SCAN CONTROL ha gt Graphics Interface Device UPA RESET L lt 1 gt SLAVIO RESET L VSIC VME RESET IN L D L p U2S p SLA_RST_L SYSRESET SBUS_RESET_ VMEbus l i Y SBus SBus SLAVIO FEPS APC Slot 0 Slot 1 The assertion of UPA RESET_L lt 1 0 gt is asynchronous with the UPA clock while UPA_XIR_L is synchronous with the UPA clock The deassertion edge of the resets has to be synchronous with UPA clock The assertion of SBUS_RESET_ can be asynchronous with SBus clock SLA_RST_OUT_L Figure 5 1 Reset Block Diagram SBUS_RESET_ must be synchronous with SBus clock Hardware Reset Sources The five different resets that RIC detects are Power Supply POR Push button POR Push button XIR Scan POR and Scan XIR The RIC chip combines the five reset conditions into three signals to the System Controller Based on these signals from the RIC the System Controller will set the proper bit s in the USC Control Register to allow software to identify the reset source Themis Compu
3. FEPS 1 SCSI 2 Headphones Microphone Line in Line out VSIC MII 10Base T VMEbus Slot 0 FLASH SLAVIO NVRAM Floppy TTY A B Keyboard Mouse or TTY C D a Figure 5 2 Block Diagram Themis Computer USP 2 Hardware Manual 5 8 Themis Computer 6 1 6 2 6 Clocks Overview The USP2 uses a programmable clock generator based on the speed of the UltraSPARC II processor The clock generator consists of a PLL synthesizer a frequency divider and a few clock drivers A low frequency input clock 16 MHz should be used along with programmable counters in a Phase Locked Loop PLL design to generate necessarily higher system frequencies and SBus frequencies This is called PLL synthesization The frequencies generated through the synthesizer are further divided to generate CPU and UPA clocks or to generate U2S and SBus clocks The USP2 board will start up at a predetermined frequency 160 MHz based on a hardware resistor network This is done through loading a hardwired speed code from the resistor network to the parallel interface of the clock generator After bootup Open Boot PROM OBP will take the control of the operating frequency setup Since the processor complex sits on the module the CPU speed varies from module to module The OBP will take speed settings from all CPU modules and select the lowest one as the speed
4. Pin Row A Row B Row C 14 PP_SLCT FD_DIR NC SCSIB_DAT 1 15 PP_INIT_L FD_STEP NC SCSIB_DAT 2 16 PP_AFXN_L FD_WR_DAT NC SCSIB DAT 3 17 PP SLOT IN L ED WR GATE NC SCSIB_DAT 4 18 PP_DAT lt 0 gt FD_TRKO NC SCSIB_DAT 5 19 PP_DAT lt 1 gt FD_WR_PROT NC SCSIB_DAT 6 20 PP_DAT lt 2 gt FD_RD_DAT NC SCSIB DAT 7 21 PP DAT lt 3 gt FD HD SEL NC SCSIB_PARO_L 22 PP_DAT lt 4 gt FD_DEN_IN NC SCSIB DAT 8 23 PP DAT lt 5 gt FD_EJECT NC SCSIB DAT 9 24 PP DAT lt 6 gt FD DSK CHNG NC SCSIB DAT 10 25 PP DAT lt 7 gt NC NC SCSIB_DAT 11 26 5V NC SCSIB_DAT 12 27 5V NC SCSIB_DAT 13 28 5V NC SCSIB_DAT 14 29 GND NC SCSIB_DAT 15 30 GND NC SCSIB_PAR1_L 31 GND GND SCSIB_REAR_L 32 5V 5V 5V VMEbus P1 Connector I O Board Table 8 9 VMEbus P1 connector description I O board Pin Row A Row B Row C 1 Doo BBSY D08 2 D01 BCLR Dog 3 D02 ACFAIL D10 4 D03 BGOIN D11 5 D04 BGOOUT D12 6 D05 BG1IN D13 7 D06 BG10UT D14 8 D07 BG2IN D15 9 GND BG2OUT GND Themis Computer 8 Connectors and Pinouts Table 8 9 VMEbus P1 connector description I O board Continued Pin Row A Row B Row C 10 SYSCLK BG3IN SYSFAIL 11 GND BG30UT SYSFAIL 12 DS1 BRO SYSRESET 13 DSO BR1 LWORD 14 WRITE BR2 AM5 15 GND BR3 A23 16 DTACK AMO A22 17 GND AM1 A21 18 AS AM2 A19 19 GND AM3 A19 20 IACK GND A18 21 IAGKIN NC A17 22 IACKOUT NC A16 23 AM4 GND A15 2
5. VMEbus SYSFAIL is asserted Reflects status of the SYSFAIL signal This signal can be controlled by the SCV64 bit SYSFAIL in register MISC SYSFAIL is asserted on Reset and cleared by OBP once SCV64 initializa tion is complete LED is also set when another VME board is driving VMEbus SYSFAIL Red SHUT DOWN Over temperature shutdown Asserted when board reaches shutdown critical temperature See 4 9 Temperature Monitoring Red VME ACCESS Accessing VMEbus Asserted during access to a SBus address decoded by VMMU as a VME region Green ENET LINK A B Ethernet Port is connected This LED is connected to pin LED3 of the DP83840 Ethernet Physical Layer chips It is set in accordance with IEEE 802 3 Link loss timer Red SCSI TERM A B On board SCSI termination is on See 7 4 SCSI Interface Settings Red USR LED 0 3 User defined Controlled by EPLD LED register see USP 2 programmer s manual Red Temperature Monitoring Temperature monitoring is based on a thermistor placed on the CPU module under the CPU on the bottom side Thermistor signals from each module are routed to the system board circuitry Temperature cannot be read by software but is used to generate two hardwired temperature thresholds e Warning temperature A PowerFail interrupt is sent With Solaris the default behavior is to broadcast a warning message and shutdown r
6. Keyboard and Mouse Settings Serial Ports C D settings Table 7 3 Keyboard Mouse Ports C D Settings Combination Description JP301 and JP302 I O board 1 2 JP0601 and JP0602 paddle board any position Sun keyboard mouse port available at the front on J3 circular 8 pin DIN connector No serial port C D This is the default setting with no jumper installed on JP0601 0602 JP301 and JP302 I O board 2 3 JP0601 and JP0602 paddle board 2 3 Sun keyboard mouse port available on the paddle board on J0602 circular 8 pin DIN connector No serial port C D JP301 and JP302 1 0 board 2 3 JP0601 and JP0602 paddle board 1 2 No Sun keyboard mouse port Serial port C D TTY C D available on the paddle board on J0603 DB9 Themis Computer 7 Jumper and Solder Bead Configurations 7 6 Serial Port Settings RS232 RS422 Table 7 4 Serial Port A and B settings Reference Location pou Description setting BD2 I O Board Off Controls the serial port transceivers for port A On Serial port transceivers are disabled Off Serial port transceivers are enabled BDI for port B SW401 I O Board RS232 for port A see set RS232 RS422 selection These switches control ting serial ports A B transceivers mode thru pins TCE3 0 SW501 shown of the serial port drivers SP504 for port B Mode TCE3 TCE2 TCE1 TCEO Disable On On On On RS232 On On Off
7. Solder beads may not be altered by a user If solder beads require reconfiguration please contact customer service Caution Attempting to alter solder bead configuration could seriously damage the USP 2 Themis Computer 7 1 USP 2 Hardware Manual 7 2 7 2 Location of USP 2 Jumpers Figure 7 1 Base Board Jumpers oe e 18 EN ha JP 1701 elo ejn ex JP2501 TN o e0000000000000ne Themis Computer 7 Jumper and Solder Bead Configurations Figure 7 2 I O Board Jumpers o 7 SW2101 e 1 e 2 o 3 gt pa 123 JP1 ee Parked position O SW502 SW501 a par Page Timekeeper NVRAM JP302 D ci lef ej 1 123 el e 2 JP2001 elee ee 3 123 1e e jo 2 b o 3 e JP2102 JP1101 JP1 Jumper on pins 1 2 will cause a bypass of the VSIC module in the JTAG chain Themis Computer 7 3 USP 2 Hardware Manual Figure 7 3 VSIC Jumpers O O 3 JP0401 DO DO y Pene JP1001 7 4 Themis Computer 7 Jumper a
8. 4 3 4 3 1 UPA Interconnect Note Throughout the UPA documentation the term MID master ID is used At times this is confusing because it is really a UPA port ID For devices which are masters there is no difference between port ID and master ID however devices which are slaves only have a port ID Slave Devices can not have a Master ID Port IDs are unique UPA Interconnect Overview The UPA interconnect is a packet based cache coherent interconnect Non coherent operations are also provided for accesses to I O devices and other devices that do not support cache coherency The physical connection among devices can be a bus or point to point The USP 2 adopts multiple buses to achieve cost performance requirements The major components defined in the UPA Interconnects are UPA Ports System Controller Data Path and Memory Physical connections among these devices are provided by Address Bus Data Bus and Data Path Control and Snoop Bus A distributed arbitration algorithm is used to arbitrate among master ports sharing the same Address Bus It is described in Chapter 3 3 5 UPA Arbitration Each UPA port can support one or more of the following functions master slave interrupter and interrupt receiver A UPA master is a device capable of issuing UPA transactions to the interconnect A UPA slave receives and services transactions requested by a UPA master or the System Controller An interrupter is a device capable of generating in
9. RxD port D NC o CO NI O oy AJ O N Themis Computer 8 15 USP 2 Hardware Manual 8 5 2 Fast wide SCSI port A and B J0801 and J0802 Table 8 12 Paddle board SCSI A and B connectors Pin Signal Name Description Direction 1 GND Ground 2 GND Ground 3 GND Ground 4 GND Ground 5 GND Ground 6 GND Ground 7 GND Ground 8 GND Ground 9 GND Ground 10 GND Ground 11 GND Ground 12 GND Ground 13 GND Ground 14 GND Ground 15 GND Ground 16 GND Ground 17 SCSI TRMPWR SCSI termination sensing Input 18 SCSI TRMPWR SCSI termination sensing Input 19 SCSI FRONT L Ground Output 20 GND Ground 21 GND Ground 22 GND Ground 23 GND Ground 24 GND Ground 25 GND Ground 26 GND Ground 27 GND Ground 28 GND Ground 29 GND Ground 30 GND Ground 31 GND Ground 32 GND Ground 33 GND Ground 8 16 Themis Computer 8 Connectors and Pinouts Table 8 12 Paddle board SCSI A and B connectors Continued Pin Signal Name Description Direction 34 GND Ground 35 SCSI DAT 12 Data Input Output 36 SCSI DAT 13 Data Input Output 37 SCSI DAT 14 Data Input Output 38 SCSI DAT 15 Data Input Output 39 SCSI PAR1 L Parity Input Output 40 SCSI DAT 0 Data Input Output 41 SCSI DAT 1 Data Input
10. including the VMEbus System Controller capability the VMEbus isolation All other VMEbus interface related options are configured using extensions to the Sun OpenBoot PROM monitor program OBP stores system configuration parameters in non volatile storage NVRAM using a setenv mechanism familiar to UNIX shell users The default configuration upon delivery of the USP 2 or after restoring the factory default values by pressing L1 N is e VME slave accesses disabled e VME slave base address at 0x00 e Mailbox interrupts disabled e Mailbox interrupt at CPU level 9 The OBP command setenv must be used to set the values of the environment variables The printenv command will list all supported environment variables and can be used to verify proper setting You must be at the OpenBoot command prompt to enter and execute OpenBoot commands If autoboot is enabled interrupt the boot sequence by pressing L1 A STOP A on an serial terminal press BREAK If BOOTMON compatibility mode is enabled you will initially see the BOOTMON prompt Enter n to start OpenBoot Type b boot c continue or n new command mode gt n ok At the ok prompt you are now able to enter OBP commands Use setenv to modify the environment variables necessary to configure the USP 2 for your VMEbus configurations or execute the appropriate OBP commands listed above The following example moves the slave window for A32 accesses to 0x80000000 decimal
11. 2147483648 and enables slave accesses E setenv vme32 slave base 2147483648 ok The OBP automatically programs the SCV64 interface chip with the correct register values and retains your settings in NVRAM Please refer to the USP2 Programmer s manual for more information Themis Computer 2 Installation AN 2 4 1 2 5 2 6 Warning Unless you are familiar with the Forth Monitor and are experienced in interacting with your system PROM restrict yourself to the most basic Forth Monitor operations That is to syncing your disks ejecting floppies from the diskette drive booting your system and configuring the VME interface More advanced commands can do damage to your system s operation VMEbus Memory Allocation The U2S SBus address space contains seven 7 physical SBus slots with 256 MBytes assigned to each slot Refer to USP 2 Programmer s Guide for the USP 2 Memory Map Each slot is logically divided into sixteen 16 16 MByte segments Any unused 16 MByte segment may be mapped to the VMEbus address space through the VME MMU translation table located on the VSIC Any segment allocated to the VMEbus can be programmed to access anywhere in the 4GByte VMEbus address space using any data path option supported Attaching the USP 2 To A Network The USP 2 features both a 10Base T and AUI Ethernet interface connectors OBP determines the active interface upon power up After attaching the USP 2 to a network y
12. 5 4 SYSRESET If SYSRESET is asserted by another VMEbus board and the USP 2 is jumpered to receive it the U2S will assert an SBus reset SB_RESET_L to the system I O devices Software Reset Software POR Software can also generate a POR equivalent reset by setting the SOFT_POR bit in the USC Control Register This is different from SIR supported in UltraSPARC IL which is only observed by the initiating processor A Software POR has the same effect as POR except that the refresh is unchanged Software XIR Software can also issue an XIR to the processors by setting the SOFT MR bit in the USC Control Register A Software XIR has the same effect as other XIRs Once the bit is set it will remain set until software clears it This allow software to find out what triggers previous XIR Error Reset A fatal error in the system can also cause a system reset A reset will be initiated if a fatal system error is detected A fatal error reset has the same effect as other PORs If the reset is caused by a fatal error the FATAL bit in the USC Control Register will be set to indicate the reset source The Themis USP 2 system detects the following fatal error conditions e UPA Address Parity Error detected by the USC e Fatal Error conditions reported by UPA devices through a P FERR UPA reply e Master Request Queue Overflow in the USC Wake up Reset The UltraSPARC II processor and Themis USP 2 system provide power management support One of th
13. Bus The UPA data bus provides data path connections between both UPA ports and memory and among UPA ports themselves Three data busses the processor data bus the memory data bus and the UPA 64 bit data bus are implemented in USP 2 systems They are interconnected by the Buffer Crossbar chip XB1 The Processor data bus is 144 bits wide with 128 bits of data and 16 ECC check bits The Memory data bus connecting the memory modules and the XB1 chip is 288 bits wide with 256 bits of data and 32 ECC check bits The UPA 64 bit data bus provides connection between the U2S and the XB1 chip It is 72 bits wide with 64 bits of data and 8 ECC check bits UPA Arbitration The UPA Interconnect uses a distributed arbitration protocol to decide which master port has the ownership of the UPA address bus It allows a maximum of four UPA master ports and an System Controller port Every master interface has its own arbitration logic and uses the same algorithm The master interfaces run synchronously Each master port presents one request and that request is connected to all other master ports and the System Controller The System Controller also provides a request that is connected to all the UPA master ports System Controller requests have a higher priority than other ports in order to access the address bus if multiple requests are active at the same time Among other master ports the priority assignment is based on round robin according to the value of
14. NC 19 GND NC NC 20 NC GND NC 21 Connected to A22 NC NC IACKIN IACKOUT 8 8 Themis Computer 8 Connectors and Pinouts Table 8 7 VMEbus P1 connector description system board Continued Pin Row A Row B Row C 22 Connected to A21 NC NC IACKIN IACKOUT 23 NC GND NC 24 NC GND NC 25 NC NC NC 26 NC NC NC 27 NC NC NC 28 NC NC NC 29 NC NC NC 30 NC NC NC 31 NC NC 12V 32 5V 5V 5V 8 3 1 VMEbus P2 Connector System Board The VMEbus P2 Connector accommodates user defined signals on row A and C The optional paddleboard is one way of easily accessing the USP 2 VMEbus P2 Connector user defined signals Table 8 8 VMEbus P2 connector description system board Pin Row A Row B Row C 1 5V 5V 5V 2 GND GND GND 3 NC NC SCSIB_TRMPWR 4 GND NC SCSIB_ATN_L 5 5V NC SCSIB_BSY_L 6 5V NC SCSIB_ACK_L 7 5V NC SCSIB_RST_L 8 NC NC SCSIB_MSG_L Parallel Port Floppy Port 9 PP_STRB_L NC NC SCSIB_SEL_L 10 PP_ACK_L FD_DEN_SEL NC SCSIB_CD_L 11 PP_BUSY FD_INDEX NC SCSIB_REQ_L 12 PP_PE FD_MOT_EN GND SCSIB_IO_L 13 PP_ERROR_L FD_DRV_SEL 5V SCSIB_DAT 0 Themis Computer 8 9 USP 2 Hardware Manual 8 3 2 8 10 Table 8 8 VMEbus P2 connector description system board Continued
15. On RS422 On Off On On On i RS232 setting shown Off SW402 UO Board RS232 RS232 RS422 selection These switches control for port A see set serial port A B receivers mode thru pins RCE3 0 of ting the serial port driver SP504 SW502 shown for port B Mode RCE3 RCE2 RCEI RCEO Disable On On On On RS232 On On Off On RS422 On Off On On Wd ME RS232 setting shown Themis Computer 7 7 USP 2 Hardware Manual 7 7 Ethernet 100BaseT Settings Table 7 5 Ethernet 100 Base T Settings Reference Location DU Description setting BD3 I O Board OFF This solder bead may have three different settings for port A No connection Normal mode 1 2 to increase the transmit signal amplitude BD2 System 2 3 to decrease the transmit signal amplitude for port B Board It controls the RTX input of the DB 83840 of the main Ethernet interface BD4 I O Board OFF The setting shall be identical to BD2 for port A It controls the REQ input of the DP83840 of the main Ethernet interface BDI System for port B Board 7 8 VME jumpers settings Table 7 6 VME Settings Reference Location Perui Description setting JP1201 VSIC ON ON USP2 is the VME system controller board OFF USP2 is not the VME system controller JP2001 I O Board 2 38 Controls the action of the VME sysreset connection to the board 1 2 Board isolated from VME SYSRESET 2 3 Board connected to V
16. code Based on the speed code OBP will look up a table and adjust the operating frequency accordingly The clock generator has two different input ports parallel load and serial load Parallel load is used by the power up sequence to initialize the CPU and system After the initialization OBP will use serial load to adjust the CPU and system to operating frequency Note that power up frequency and operating frequency are different Their difference and usage will be further discussed in the following paragraphs General Description Clock generation for the major clocks is done through the use of a Motorola MC 12439 frequency PLL synthesizers It combines a VCO Voltage Controlled Oscillator and programmable divider to derive a high speed clock from a much lower speed crystal oscillator Its internal VCO will operate over a range of frequencies up to 800 MHz The differential PECL output can be configured to be the VCO frequency divided by 16 With the output configured to divide the VCO frequency by 1 and with a 16 000 MHz external quartz crystal used to provide the reference frequency the output frequency can be specified in 16 MHz steps See Figure 6 1 for a simplified diagram of the PLL synthesizer chip In the USP2 the parallel load port is used for power up frequency programming and the serial load port is used for frequency adjustment to set the correct operating frequency under control of OBP Themis Computer 6 1 USP 2 Hardware Ma
17. configured to use the printer interface Please check Jumpers 3401 Table 8 14 Paddle board floppy connector Pin Description Pin Description 1 FD_EJECT 18 FD_DIR 2 FD_DENSEL 19 GND 3 GND 20 FD_STEP 4 FD_DEN_IN 21 GND 5 GND 22 FD_WR_DAT 6 NC 23 GND 7 GND 24 FD_WR_GATE 8 FD_INDEX 25 GND 9 GND 26 FD_TRKO 10 FD_DRVSEL 27 GND 11 GND 28 FD_WR_PROT 8 18 Themis Computer 8 Connectors and Pinouts Table 8 14 Paddle board floppy connector Continued Pin Description Pin Description 12 NC 29 GND 13 GND 30 FD_RD_DAT 14 NC 31 GND 15 GND 32 FD_HDSEL 16 FD_MOT_EN 33 GND 17 GND 34 FD_DSK_CHNG Themis Computer 8 19 USP 2 Hardware Manual 8 20 Themis Computer Themis Computer 3185 Laurelview Court Fremont CA 94538 Attn Publications Department AAA THEMIS COMPUTER Place Stamp Here Reader Comment Card We welcome your comments and suggestions to help improve the USP 2 Hardware Manual Please take time to let us know what you think about these manuals e The information provided in the maunal was complete Agree___ Disagree___ Not Applicable___ e The information was well documented and easy to follow Agree___ Disagree___ Not Applicable___ e The information was easily accessible Agree___ Disagree___ Not Applicable___ The manuals were useful Agree___ Disagree___ Not Applic
18. eee 9 0 000 ooo 7m ove 7000 E E ooo Zeie ooo 000 000 eee 0601000 ote 000 eco Eh ege 000 eo 000 5 000 seo E 000 e e 000 20 0 ooo e e e 000 200 0 e e ee 000 AA EAS ene ete lass 070 ess Qe eege 0 cee 0 coo ooo eo ee ev 000o o 000 0 0 000 000000 ad 000 0 0 000 0 6 000 a eco e ocos po es EE EES sie osos me ef 0800 0 0 000 0 0 000 on 00 ef eee 000 0 0 000 0 0 000 e gt 000 sie sie OG pe ee Ze ooo OSS Sete hete Sete SSS oe Soe eg lees 7 lt gt eve o see 2 000 ee oe 0900 y 000 eee 000 000 oo 008 po 000 fe 000 000 00 eso 900 oe 000 fe 000 e ee oe eee oe 000 07 ooo eee 000 0 KIC 000 SCSI A SCSI B IDC 34 FLOPPY I F MICRO D68 FAST WIDE SCSI STANDARD CONNECTION Figure 8 5 Paddle Board Connectors 8 14 Themis Computer 8 Connectors and Pinouts 8 5 1 Serial Ports C D DB9 connector J0603 A certain combination of jumpers allows to use the Sun keyboard mouse ports as two general purpose RS232 serial ports ports C and D Please refer to 8 2 2 Keyboard Mouse Connector Female on page 8 4 for a description With that combination ports C and D are accessible on the paddle board J0603 connector as follows Table 8 11 Serial Ports C D DB9 connector Pin Signal GND RxD port C TxD port C NC NC NC TxD port D
19. xe cace Egide 1 3 Installation 2 1 ROSISENING iii aire iis 2 1 22 ETE UP eee 2 1 23 Installing the USP 2 and its Paddleboard in the VME chassis conoccconoccconoccninancnnnos 2 2 ZA Configuring The VME Interfaceiunuyumunonsgsunsssensmnrsvurisisuiteiveisse 2 3 2 4 1 VMEbus Memory Allocation s 2 c0tisnies Seege Ha a 2 5 2 5 Attaching the USP 2 To A Network 5 is c cc3ceesuecesssscsedacasnsseseratecentcceat andes ENEE AEN 2 5 2 6 Attaching a Keyboard and Mouse ccscccisssccasesscecatssosacescnsdenvanccsetedeas sesion dnde daa s dica 2 5 2 7 VME Bus Addressing Data Transfer Modes AAA 2 6 USP 2 Hardware Specifications 3 1 Hardware and Performance Specifications ooooonocccnnoccconocccnnnncnnonccnnnnc conc nccnnn conan nccnnos 3 1 3 2 Environmental Specifications Ls Te 3 3 Themis Computer v USP 2 Hardware Manual vi Hardware Overview 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 Reset 5 1 5 2 GL EEE EEE EE EE ENE 4 1 Themis USP2 Block D tan Luse SANS 4 1 UPA Interconectado di 4 3 4 3 1 UPA erreecht nd 4 3 4 3 2 UPA Data Trans tri 4 4 4 3 3 UPA COLE SS BUS Ls 4 5 4 3 4 UPA Data BUS visi ida il aida 4 6 4 3 5 UPA Arbitration pes 4 6 4 3 6 Processor Sub syst em sssrini aas 4 6 Memory SENT RS 4 6 4 4 1 System Controller DSC Luse 4 8 4 4 1 1 Port Interface Controller DIE 4 8 4 4 1 2 Data Path Scheduler DP 4 8 4 4 1 3 Memory Controller MC EE 4 8 BA WA BREE Gea 4 8 4 4 2 Buffered Crossbar Chip KB Lis
20. 0Base T Ethernet Connector Pinouts Table 8 3 100Base T Ethernet Connector Pinouts Pin Signal Name Description Direction 1 TWO Transmit Data Output 2 TWO Transmit Data Output 3 TWI Receive Data Input 4 NC Not Connected Themis Computer 8 Connectors and Pinouts Table 8 3 100Base T Ethernet Connector Pinouts Pin Signal Name Description Direction 5 NC Not Connected 6 TWI Receive Data Input 7 NC Not Connected 8 NC Not Connected 8 2 4 SCSI A and B Fast wide Connector Female High Density Table 8 4 Fast wide SCSI A and B Connector Pinout Pin Signal Name Description Direction 1 GND Ground 2 GND Ground 3 GND Ground 4 GND Ground 5 GND Ground 6 GND Ground 7 GND Ground 8 GND Ground 9 GND Ground 10 GND Ground 11 GND Ground 12 GND Ground 13 GND Ground 14 GND Ground 15 GND Ground 16 GND Ground 17 SCSI TRMPWR SCSI termination sensing Input 18 SCSI TRMPWR SCSI termination sensing Input 19 SCSI FRONT L Ground Output 20 GND Ground 21 GND Ground 22 GND Ground 23 GND Ground Themis Computer 8 5 USP 2 Hardware Manual Table 8 4 Fast wide SCSI A and B Connector Pinout Continued Pin Signal Name Description Direction 24 GND Ground 2
21. 1 USP 2 Hardware Manual 1 4 1 4 1 1 4 1 1 Features of the USP 2 are e Up to 2x64 bit V9 UltraSPARC II processors e Use of Themis proprietary memory modules Up to 2GB of memory e UPA coherent memory interconnect Thermal management The USP2 will shutdown if over temp detected 2 thresholds e 2 RS232 RS422 serial ports TTYA TTYB supporting both synchronous and asynchronous protocols Available on the front panel e 2 asynchronous mode serial ports for SUN Type 5 keyboard or mouse interface that can be configured as 2 RS232 serial ports TTYC TTYD on the P2 connector Note that the SUN keyboard can be plugged on front panel or on the P2 paddle board e Centronic compatible parallel port interface Available on the paddle board P2 e Built in audio interface Available on Front panel e 2 SBus expansion slots Only one is available in case of graphic configuration e DUAL Ethernet 10 100baseT e DUAL 20 Mbyte sec fast and wide SCSI e VME64 Interface Note Themis distinguishes between two types of options field options which the customer may set in the field and factory options which Themis sets before shipping the board or when the board is returned to Themis for re configuration Factory configurable options are not to be configured by the customer An example of a field option is a jumper An example of a factory option is a solder bead Not all factory options are re configurable and the customer should decid
22. 4 A07 IRQ7 A14 25 A06 IRQ6 A13 26 A05 IRQ5 A12 27 A04 IRQ4 A11 28 A03 IRQ3 A10 29 A02 IRQ2 A09 30 A01 IRQ1 A06 31 12V NC 12V 32 5V 5V 5V Themis Computer 8 11 USP 2 Hardware Manual 8 3 3 VMEbus P2 connector I O board Table 8 10 VMEbus P2 connector description I O board Pin Row A Row B Row C 1 MIIA_PWR 5V 5V 2 5V GND GND 3 MIIA_PWR RETRY SCSIA_TRMPWR 4 5V A24 SCSIA_ATN 5 GND A25 SCSIA_BBSY 6 KEYB_IN_P2 A26 SCSIA_ACK 7 KEYB_OUT_P2 A27 SCSIA_RST 8 MIIA_MDIO A28 SCSIA_MSG 9 MIIA MDG A29 SCSIA SEL 10 MIIA RXD 3 A30 SCSIA CD 11 MIIA RXD 2 A31 SCSIA REQ 12 MIIA RXD 1 GND SCSIA IO 13 MIIA RXD 0 5V SCSIA_DAT 0 14 MIIA_RX_DV D16 SCSIA_DAT 1 15 MIIA_RX_CLK D17 SCSIA_DAT 2 16 MIIA_RX_ER D18 SCSIA_DAT 3 17 MIIA_TX_ER D19 SCSIA_DAT 4 18 MIIA TX CLK D20 SCSIA_DAT 5 19 MIIA_TX_EN D21 SCSIA_DAT 6 20 MIIA_TXD 0 D22 SCSIA_DAT 7 21 MIIA_TXD 1 D23 SCSIA_PARO 22 MIIA_TXD 2 GND SCSIA_DAT 8 23 MIIA TXD 3 D24 SCSIA_DAT 9 24 MIIA_COL D25 SCSIA_DAT 10 25 MIIA_CRS D26 SCSIA_DAT 11 26 MOUSE_IN D27 SCSIA_DAT 12 27 MOUSE_OUT D28 SCSIA_DAT 13 28 5V D30 SCSIA_DAT 14 10 29 5V D31 SCSIA_DAT 15 30 GND GND SCSIA_PAR1 31 GND 5V SCSIA_REAR 32 5V 5V 5V 8 12 Themis Computer 8 Connectors and Pinouts 8 4 SBus Connectors 1 and 2
23. 5 GND Ground 26 GND Ground 27 GND Ground 28 GND Ground 29 GND Ground 30 GND Ground 31 GND Ground 32 GND Ground 33 GND Ground 34 GND Ground 35 SCSI_DAT 12 Data Input Output 36 SCSI_DAT 13 Data Input Output 37 SCSI_DAT 14 Data Input Output 38 SCSI_DAT 15 Data Input Output 39 SCSI_PAR1_L Parity Input Output 40 SCSI DAT 0 Data Input Output 41 SCSI DAT 1 Data Input Output 42 SCSI DAT 2 Data Input Output 43 SCSI DAT 3 Data Input Output 44 SCSI DAT 4 Data Input Output 45 SCSI DAT 5 Data Input Output 46 SCSI DAT 6 Data Input Output 47 SCSI DAT 7 Data Input Output 48 SCSI PARO L Parity Input Output 49 GND Ground 50 Non connected 51 SCSI TRMPWR SCSI termination Input 52 SCSI TRMPWR SCSI termination Input 53 Non connected 54 GND Ground 8 6 Themis Computer 8 Connectors and Pinouts Table 8 4 Fast wide SCSI A and B Connector Pinout Continued Pin Signal Name Description Direction 55 SCSI ATN L Attention Input Output 56 GND Ground 57 SCSI BSY L Busy Input Output 58 SCSI ACK L Acknowledge Input Output 59 SCSI RST L Reset Input Output 60 SCSI MSG L Message Input Output 61 SCSI SEL L Selection Input Output 62 SCSI CD L Input Output 63 SCSI REQ L Input Output 64 SCSI IO L 65 SCSI DAT 8 Data Input Output 66 SCSI DAT 9 Data Input Output 67 SCSI DAT 10 Data Input Output 68 SCSI DAT 11 Data Input Output 8 2 5 Audio Ports All Audio Port
24. 8 5 1 Serial Ports C D DB9 connector OUOoO 8 5 2 Fast wide SCSI port A and B JO801 and JON 8 5 3 Parallelt TU ke 8 5 4 Floppy connector JOT OL EE Reader Comment Card viii Themis Computer List of Figures Listof Figures Figure Za USP 2 Assen ya cece ee telus eget lar ee eege 2 3 Figure 3 1 USP 2 System Board Block Dageram 4 2 Figure 4 2 UPA Interface Block Duageram yicc i sccsscccisssccassceccdcceesnsccetececeassenesdcctensesdectnsasteasesnvetone 4 4 Figure 3 3 Memory System Block Diagram saus einen has td 4 7 Figure 4 4 gt WO System Block D sram 44444 e O 4 9 Figure 4 5 USP2 Flow Di gram nvuausnsnasselsnsannadnbntmaueuanusnldittee 4 13 Fipires l Reset Block Eerad ege ebe 5 2 Fj ure5 2 Block Ereegnes 5 7 Figure 6 1 Simplified Block Diagram of Clock Generator 6 2 Figure 6 2 USP2 CPU and System Clock Schematic ed iden ds 6 3 Figure 6 3 USP2 SBUS Clock NEE 6 4 Bigure 7 1 Base Board Jumpersyicisc ccacsccscssciadeadasscachansesdacapestad svauascedssuasaseacasdaccansseanteaassactsevtiacaaes 7 2 Figure se 10 Board Jumpers iz A Sakene 7 3 o VS IMP 7 4 Figure 1 USP2 Front panelistas aliadas 8 2 Figure 8 2 Keyboard Mouse Connector Pinout oooconnncnnococonnnoncnononcnnncconccnna nono nono ncnnnncnnnnrn cnn 8 4 Figure 8 3 100Base T Ethernet Connector Pnouts conan ron nncnnnnnn cross 8 4 Figure 8 4 SBus Connectors 1 and 2 Pinouts eenrnrnrrnonvnrnvnnnrnnrnnrnnnenvnnvnrnrrasenensnvnnn
25. Address Bus It then sends a transaction request to the UPA Address Bus together with UPA_Addr_Valid signal Examples of simplified data transfer operations are given here to help in understanding how the UPA works Non cacheable Read The System Controller decodes the request packet and makes a transaction request to arbitrate for the address bus where the selected device resides It then forwards the packet to the UPA slave The UPA slave services the request and returns a P_Reply to the System Controller when data is available or there is an error The UPA slave must respond to the transaction request which 1s directed to it Failing to do so may cause the system to hang Based on the P_Reply received the System Controller schedules the datapath and sends a separate S_Reply to both parties involved in the transaction The S_Reply tells the UPA slave to send data on the data bus and UPA master to receive data from the data bus Non cacheable Write The System Controller forwards the request packet to the UPA slave It then schedules the datapath and issues a separate S_Reply to both UPA master and UPA slave The S_Reply tells the master port to drive data to its data bus and slave port to receive data from its data bus Either the address packet or data can arrive to the slave port earlier than the other If the slave port needs to use the data to schedule internal operations it has to wait until data is received on its UPA port After the slave port d
26. Any combination of 512 MBytes and 1 GByte modules may be used NVRAM TOD Clock The module provides 8KB of NVRAM space implemented via a SGS Thomson M48T59 hybrid module The module contains an encapulated lithium cell for non volatility PROM The I O Board provides mounting sites for two Flash EPROM devices It is intended that two 2MB devices be used providing a total of 4MB of Flash space The devices are sector erasable and operate from a single 5V supply The flash space is accessible on the SBus through the Slave I O ASIC as 8 bit space A connector is provided on board which allows the Flash EPROM to be factory programmed on board The device can also be reprogrammed over the network or from CD ROM in the field to support upgrades to the OBP or Power Up Self Test SBus SBus Controller Chip Sun STP 2220BGA U2S ASIC SBus Connectors 2 Female SBus headers Only one in graphic configu ration Environmental Specifications Table 3 2 and Table 3 3 on page 3 4 contain the environmental specifications for the USP 2 under operating and non operating conditions When measuring the operating environment air temperature for the USP 2 measure the air temperature as close to the air intake port on the enclosure as possible For cooling purposes maximum air flow should be across the USP 2 board processor section including the UltraSPARC processor external cache SRAMS and UDBs Themis Co
27. Bus 0 The two devices on this bus are the processor s and the U2S The processor s and U2S tristate asynchronously upon detection of RESET UPA Processor Data Bus This bus is shared by the UDBs and the BMX The UDB chips tristate the data bus at reset The BMX has a POR circuit which causes tristate its buses at power up time Memory Data Bus This bus is driven by the DRAM and the BMX chip The RAS and CAS signals driven by the USC are asynchronously deasserted BMX tristates its data output pins at power up SBus All expansion slots U2S FEPS SLAVIO and APC share this bus The U2S asynchronously tristates this bus It also asynchronously de asserts the AS line EBus The PROM TOD NVRAM and the USC share this bus The RIC chip drives the PROM CS and the USC chip select All signals driven by the RIC asynchronously deassert Unfortunately SLAVIO does not asynchronously deassert its signals so it is possible to have READ and the chip selects to the TOD and the PROM active if the SBus clock is not operational Themis Computer 5 Reset FEPS 2 APC Up to 4 128 MByte Memory Modules UPA CPU1 A Creator UDB Graphic Cache USC XB1 RIC U2S ParallelPort 16 Bit 14 Digital Gate Audio
28. DDRO BUR RASO CASOWE0 Block 3 Block 3 ADDRI 9 DRAMs 9 DRAMs RASO CAS1 WEO Note Strobe assignments shown are for base memory board up to 512 MBytes it is slightly different configuration for 1 GByte Base memory board Themis Computer USP 2 Hardware Manual 4 4 1 4 4 1 1 4 4 1 2 4 4 1 3 4 4 1 4 4 4 2 System Controller DSC The System Controller contains several major blocks e Port Interface Controller PIF Data Path Scheduler DPS e Memory Controller MC e EBus Port Interface Controller PIF This block of logic considers all UPA transactions and determines the intended target of the transaction The PIF is responsible for the control flow for packets It also performs the function of the Coherence Controller CC Data Path Scheduler DPS The Data Path Scheduler DPS controls all of the data flow in the machine coordinating the activity of the XBI chips Memory Controller MC This block implements all of the memory control for the system All operations affecting DRAM are contained in this block These include sizing timing and refresh EBus Since pins are limited on the DSC a low pin count interface was chosen This block provides an interface to the generic bus Reset functionality is located in this block Buffered Crossbar Chip XB1 The Buffered Crossbar Chip XB1 is the hub of all data transfers in the system It coordinates activity among memory at 288 bits wi
29. ME SYSRESET JP401 VSIC ON ON Enable TRANSMIT RECEIVE of SYSRESET to VMEbus OFF Disable TRANSMIT RECEIVE of SYSRESET to VMEbus JP1 I O Board 1 2 Connects signal VSIC_TDO to SLAVIO_TDO Not user configurable JP1001 VSIC Both Determine the size of the VME slave window JP1002 Board jumpers JP1001 ON JP1002 ON Window is 128MB OFF JP1001 ON JP1002 OFF Window is 64MB JP1001 OFF JP1002 ON Window is 32MB JP1001 OFF JP1002 OFF Window is 8MB a Settings on both the JP2001 and JP401 must be the same JP2001 jumper is on 2 3 and JP401 jumper is ON Themis Computer 7 Jumper and Solder Bead Configurations 7 9 7 10 7 11 Flash Prom Settings Table 7 7 Flash Prom Settings Reference Location Dan Description setting JP2101 I O Board 1 2 Selects the boot device located at 1ff f000 0000 1 2 Flash 1 U201 is selected 2 3 Flash 0 Rombo connector is selected JP2102 I O Board 1 2 Control the write protect feature on Flash Prom Flash 1 and Flash 2 1 2 Flash devices are all write protected 2 3 Flash devices are writable General Purpose DIP switch Table 7 8 General Purpose DIP switch Reference Location B faull Description setting SW2101 I O Board n a These 4 switches are user configurable They are readable thru a register described in the USP2 Pro grammer s manual Printer Floppy available
30. Output 42 SCSI DAT 2 Data Input Output 43 SCSI DAT 3 Data Input Output 44 SCSI DAT 4 Data Input Output 45 SCSI DAT 5 Data Input Output 46 SCSI DAT 6 Data Input Output 47 SCSI DAT 7 Data Input Output 48 SCSI PARO L Parity Input Output 49 GND Ground 50 Non connected 51 SCSI TRMPWR SCSI termination Input 52 SCSI TRMPWR SCSI termination Input 53 Non connected 54 GND Ground 55 SCSI ATN L Attention Input Output 56 GND Ground 57 SCSI BSY L Busy Input Output 58 SCSI ACK L Acknowledge Input Output 59 SCSI RST L Reset Input Output 60 SCSI MSG L Message Input Output 61 SCSI SEL L Selection Input Output 62 SCSI CD L Input Output 63 SCSI REQ L Input Output 64 SCSI IO L 65 SCSI DAT 8 Data Input Output 66 SCSI DAT 9 Data Input Output 67 SCSI DAT 10 Data Input Output 68 SCSI DAT 11 Data Input Output Themis Computer 8 17 USP 2 Hardware Manual 8 5 3 Parallel port J0702 NOTE The parallel printer interface can t be used if the USP2 is configured to use the floppy interface Please check Jumpers 3401 Table 8 13 Paddle board parallel port Pin Description Pin Description 1 STROBE 14 AFXN 2 DATOO 15 ERR 3 DATO1 16 INIT 4 DATO2 17 SLCT_IN 5 DAT03 18 GND 6 DAT04 19 GND 7 DATO5 20 GND 8 DATO6 21 GND 9 DATO7 25 GND 10 ACK 11 BUSY 12 PE 13 SLCT 8 5 4 Floppy connector J0701 NOTE The floppy interface can t be used if the USP2 is
31. Remove the USP 2 and accessories from its shipping container and check the contents against the packing list The package should include e Themis USP 2 e USP 2 Warranty Information Integration Kit if ordered separately Paddleboard A B Serial Cable Front Panel SCSI Cable Flat Ribbon SCSI Cable e USP 2 User Manual if ordered separately Please report any discrepancies to the Themis Computer Customer Support department immediately In Case of Difficulties Our Customer Support department is committed to providing the best product support in the industry Customer support is available 8am Spm PST Monday through Friday via telephone fax e mail or our World Wide Web site Themis Customer Support Telephone 510 252 0870 Fax 510 490 5529 E mail support themis com Web Site http www themis com Themis Computer 1 3 USP 2 Hardware Manual 1 4 Themis Computer 2 Installation 2 1 Registering Please review the Themis Computer warranty and complete the product registration card delivered with your UPS 2 board s Return of the registration card is not required to activate your product warranty but by registering your USP 2 Themis Computer will be able to better provide you with timely updated information and product enhancement notifications At Themis Computer we value our customers comments and concerns We have a marketing department that is eager to know what you think of our products and
32. USP 2 Hardware Manual Version 1 4 March 8 2001 EE E AE et Themis Computer Americas and Pacific Rim Themis Computer Rest of World 3185 Laurelview Court 20 rue du Tour de I Eau Fremont CA 94538 USA 38400 St Martin d Heres Phone 510 252 0870 France Fax 510 490 5529 Phone 33 476 59 60 46 World Wide Web http www themis com Fax 33 476 59 60 49 Copyright 2001 Themis Computer Inc ALL RIGHTS RESERVED No part of this publication may be reproduced in any form by photocopy microfilm retrieval system or by any other means now known or hereafter invented without the prior written permission of Themis Computer The information in this publication has been carefully checked and is believed to be accurate However Themis Computer assumes no responsibility for inaccuracies Themis Computer retains the right to make changes to this publication at any time without prior notice Themis Computer does not assume any liability arising from the application or use of this publication or the product s described herein RESTRICTED RIGHTS LEGEND Use duplication or disclosure by the United States Government is subject to the restrictions set forth in DFARS 252 227 7013 c 1 11 and FAR 52 227 19 TRADEMARKS SOLARIS is a registered trademark of Sun Microsystems UltraSPARC is a registered trademark of SPARC International All other trademarks used in this publication are the property of their respective owners T
33. a customer support department that is committed to providing the best product support in the industry Customer support is available 8AM to 5PM PST Monday through Friday via telephone fax email or our web site Customer Support Phone 510 252 0870 Fax 510 490 5529 Email support O themis com Web site www themis com 2 2 Configuring the USP 2 Confirm the installation of all factory default jumpers The default configuration is as follows USP 2 as VME System Controller Keyboard Mouse ports connect to front panel Active SCSI termination enabled on base and I O boards Drive Receive SYSRESET Serial Port A B is EIA 232 E EIA 423A compatible Themis Computer USP 2 Hardware Manual 2 3 2 2 Boot from FLASH e FLASH programming disabled e Manual Ethernet port selection enabled e Use normal twisted pair squelch threshold for 1OBASE T e Bypass VMEbus interface in JTAG scan chain If the default jumper settings meet your requirements you are now ready to install the SPARC USP 2 in a standard VME chassis To check the default configurations or if reconfiguration is required refer to Chapter 4 Configurations and Options for information concerning board jumper settings solder bead and memory configurations Note If you are not installing the USP 2 as a system controller jumper J1201 must be removed In addition to the USP 2 hardware a standard VME chassis with P1 P2 backplane is required If you intend to u
34. able___ e Please write down any additional comments you may have about these manuals Name Title Company Address
35. cessor Module 2 Processor Module 1 a l Power Supply Mid Plane Board The paddle board is a daughter board that permits access to I O signals on the back of the USP 2 This is done through the user defined pins row A and row C available on the USP 2 VME P2 connectors of the System board and the I O board The paddle board has 5 VME P2 connectors that plug opposite to the 5 slots occupied by the USP 2 It provides industry standard connectors for Serial Ports C and D Ethernet SCSI and printer It contains no statically sensitive components but should be handled with care to avoid bending pins on the connectors Caution Always make sure the USP2 and the paddle board are properly aligned Refer to Chapter 8 Connectors and Pinouts for a description of all connectors Configuring The VME Interface Themis has implemented a variable and flexible VMEbus interface using both on board jumpers OpenBoot PROM OBP commands and environment variables specific to the USP 2 board Themis Computer 2 3 USP 2 Hardware Manual 2 4 The USP 2 is typically reconfigured when VMEbus boards are added removed or changed in the chassis Board configuration normally involves allocation of VMEbus master access address interrupts and slave base address of the USP 2 A small number of VME interface capabilities are configured using jumpers or solder beads
36. current master No matter which master port gets ownership of the bus the value of current master is incremented by I and wraps around to 0 after it reaches 3 The current master has to give up the bus when another request is asserted Processor Sub system The USP 2 is a next generation SPARC CPU incorporating on chip 16 KByte Instruction and 16 Kilobyte Data caches integrated Level 2 cache management a floating point unit fixed point units multi instruction issue logic and a 128 bit wide data bus The processor requires external synchronous SRAMs for the second level cache plus cache tags and two data bus interface chips UDBs The processor complex is soldered onto the CPU Module Subsystem Memory System The USP 2 memory system consists of three major components e the System Controller e DRAM Memory Modules e Buffered Crossbar Chips XB1 Themis Computer Figure 3 3 Memory System Block Diagram Memory Board Connector 288 a E El Z CBT z Switches lt y lt MEM_DAT 288 MEM DAT 288 ADDRO Memory Bank 0 Memory Bank 1 RASO CASO WEO m BUF Block 0 Block 0 ADDRI 9 DRAMs 9 DRAMs RASO CAS1 WEO c BUF gt ADDRO BUR _RASACASO WED Block 1 Block 1 ADDRI 9 DRAMs 9 DRAMs RASO CAS1 WE0 ADDRO BUR RAS CASOWED Block 2 Block 2 ADDRI 9 DRAMs 9 DRAMs RASO CAS1 WEO BUF __ A
37. d before issuing a S_Reply e Coherent Write Coherent write requests are handled in the same fashion as coherent reads The tag state is updated in the dual tags UPA Address Bus The UPA Address Bus is a 35 bit wide packet switched bus The address bus is protected by a parity bit UPA_Address_Parity Odd parity is generated by the UPA masters that is the total number of bits including parity is odd The UPA address bus carries transaction request packets generated by the master ports The packet includes information such as transaction type address class master ID MID and others Forty one bits of physical address are carried in the packet bits lt 40 4 gt come directly from the packet Bits lt 3 0 gt can be derived from the 16 bits of Byte Mask field in the packet The Master ID is a 5 bit field used to identify the master that initiated the transaction Each slot gets its port ID from hardwired inputs to the UPA connector from a software programmable register in the case of U2S or from its implicit location in the system Table 4 1 below shows the UPA Port ID assignments in the USP 2 system Table 4 1 UPA Port ID Assignments UPA Slot Number UPA Port ID lt 4 0 gt Processor slot 0 0x0 U2S Ox1F Processor slot 1 Ox1 The UPA interconnect allows multiple UPA address busses in the system UPA address bus 0 is shared by the processor port s and U2S The System Controller is the only master device o
38. ddle board distributes additional 5V power to the boards via auxiliary power pins An auxiliary power connector on the paddle board couples directly to the backplane power lugs in order to deliver the required 5V power Please contact factory for power requirement values Thermal Management Themis Computer 3 1 USP 2 Hardware Manual Table 3 1 USP 2 Hardware and Performance Specifications An on board thermal sensor circuitry ensures that the USP2 functions at an acceptable temperature The monitoring is done thru a thermistor placed on the CPU module In case of over temperature the system defines two thresholds Warning threshold The thermal circuitry sends an interrupt to Solaris which prints the following message WARNING Severe over temperature condition detected WARNING Powering down THE SYSTEM IS BEING SHUT DOWN NOW Log off now or risk your files being damaged Shutdown threshold The thermal circuitry will shutdown the DC TO DC converters that are powering the CPU modules The front panel SHUTDOWN LED will be ON Input Output SBus Slots Two physical slots One only if Creator graphic option SBus Standard SBus specifications IEEE 1496 1993 SBus Data Size 64 Bit Full Master Slave Sbus Clock Rate 25MHz SBus Write Sizes Maximum 64 byte burst Sbus Writes 64 32 16 8 byte burst mode supported SCSI Port 1 A 68 pin high density connector
39. de the processor UPA bus at 144 bits wide and the system UPA bus at 72 bits wide Transfers can take place among any of the ports To minimize the cost the chip is bit sliced such that 18 parts are required to implement a full connection to the system Themis Computer 4 Hardware Overview 4 5 4 5 1 UO System T O Board Paddle Board Connector A Front Panel 2 Ei E Y RST d 2 2 FLASH NVRAM O a a 4Mx8 8Kx8 RIC gt ASIC gn Sei Keybrd Mse DE rarer TTY C amp D ra gt I gt gt Serial Ports ra Dir ra gt Floppy Option VSIC CH Module pp L Line In lt lt APC GP Cod P2 p odec I ti ASIC gt Line Out CH a Hp 10 100BaseT E Xcvr a a gt gt MII 5 gt n FEPS CH 2 pe ASIC gt sai fa p e SCSI 2 CH KI Xevr at 10 100BaseT tp FEPS s Clk SBus Clocks ASIC gt SCSL3 Gen Sa SCSI 3 y CH S Parallel Port DJ Located on System Board Figure 4 4 I O System Block Diagram U2S The U2S is the bridge chip between the UPA and the SBus In addition to providing simple bridge functions it acts as the I O hub and provides such necessary features as the IOMMU and Streaming Buffers This is done to speed up sequential I O acc
40. e 6 2 General Description eiii ad diia ii 6 3 UPA Processor and SBus OClocks 6 4 Ober NSG Jumper and Solder Bead Configurations 7 1 12 1 3 7 4 7 5 7 6 7 1 7 8 7 9 7 10 7 11 E E A E E E sr Location Ot USP JUNE REST CPU Clock SSUES Vase SE ST ee SMS NSG Keyboard and Mouse Settings Serial Ports C D settings ooooconoccnoccnonccnonanannnnnnnnnno Serial Port Settings RS232 RS422 EE Ethernet 100BaseT Settings ee VME jumpers EE Flash Porn EH dese SEE General Purpose DIP Switch eege Printer Floppy available on the paddle board Configuration coooconnocnnonononnnannnnnnnnns Connectors and Pinouts 8 1 8 2 uge Tee LEE Front Panel On DerIER eege ebe gedeelt Eege Eege EEN 8 2 1 TTY A and TTYB Connectors bemale t Themis Computer 5 3 5 3 5 3 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 5 5 5 5 5 5 6 5 6 5 6 5 6 5 6 6 1 6 1 6 2 6 3 7 1 7 2 7 5 7 5 vii USP 2 Hardware Manual 8 3 8 4 8 5 8 2 2 Keyboard Mouse Connector Pemale 8 2 3 Ethernet 100BaseTX A and B RJ45 Connector ococcconoccncnononcnonnnonnnnnnnnos 8 2 4 SCSI A and B Fast wide Connector Female High Densttv 8 2 5 Ee OLS ras tee ees eget ee Sass tual tees ee WME CENT e 8 3 1 VMEbus P2 Connector System Board 8 3 2 VMEbus P1 Connector I O Board 8 3 3 VMEbus P2 connector I O board oooooococonncccnnononananononccncnnnannn nono nocnononnnns SB s C nn ctots FL d IA A Paddle board connectors 10000 i
41. e supported features is to allow the UltraSPARC II processor to enter a power down mode by executing a shutdown instruction A reset is the only method to wake up the processor after the UltraSPARC II Cache Tag UDB are in power down mode The wake up reset is generated by the USC when it detects an interrupt packet being directed to a port in power down mode This reset will only reset the processor s and UPA arbitration not other system resources such as memory I O devices The UPA graphics interface will not be reset The wake up reset generated to the processor has the same effect as a POR The WAKEUP status bit will be set in the USC Control Register to indicate the reset source UPA Arbitration Reset The UPA uses distributed arbitration for master devices to gain control of the address bus Each master device has its own arbiter to keep track of which master device owns the address bus and which master device should get the ownership of the bus if multiple requests are present Themis Computer 5 Reset 5 3 5 3 1 5 3 2 A UPA RESET L lt 1 0 gt will reset the devices connected to it During the wake up sequence a UPA_RESET_L lt 0 gt will be asserted to reset the processor and the U2S arbiter A UPA RESET L lt I gt will not be asserted This leaves the states of I O devices and UPA Graphics unchanged Effects of Resets All system resets are software visible and insure proper hardware operation For example all bus
42. e APC audio chip supports 16 bit digital audio along with an SBus interface It provides an interface to a 16 bit CODEC with DMA The specifications below assume use of the Audio Tool format setting CDROM or DAT has been selected The microphone input specifications are for the Sun Microphone II Table 4 2 Audio Specifications Stereo Specifications Line In 2V typical 4V max 5 50 ohm impedance Frequency Response 20 Hz 17 kHz 0 5 dB Internal CD Input Input Level 0 1 Vrms typical at 10 kohm 2Vpp max Distortion 0 01 typical at 1kHz S N Ratio 84 dB typical IEC 179 A weighted Frequency Response 20 Hz 17 kHz 0 5 dB Microphone Input 15mV typical 0 6 1 0 kohm impedance 5 VDC input bias via a 2 2 kohm resistor Headphones Output 1V typical 2 4V max 160hm 1 kohm impedance Line Out 1V typical 2 4V max 5 50 kohm impedance Themis Computer 4 11 USP 2 Hardware Manual 4 5 4 4 5 5 4 6 4 12 SLAVIO The SLAVIO is an I O chip implementing three slave devices on the SBus These are the serial ports a keyboard mouse and the floppy disk controller EBus Devices Auxiliary devices not conveniently fitting into an existing chip are implemented on the 8 bit expansion bus called the EBus Devices found on this interface include the Flash EPROM the NVRAM TOD chip the System Controller interface and the frequency marg
43. e SCV64 VMEbus U2S SBus slots FEPS SLAVIO APC CS4231 and other on board devices The RIC ASIC is independent of system interconnects It provides JTAG reset and clock control functions that are important to the system The RIC ASIC communicates with other chips through direct interfaces Themis USP 2 Block Diagram The CPU board at the block level is described below Processor a dual processor system with the processor subsystem on the CPU board e SBus Slots supports up to two external SBus slots e Memory Modules supports from one 512 MByte and up to two 1 GByte Memory Modules Themis Computer 4 1 Figure 3 1 USP 2 System Board Block Diagram CPU CPU Module Module Clock Mid Plane Riser ra Tag SRAM Generator A 16 3 sp Y Data 4 TT dare Cui gt UPA Clocks E E A UPA ADDRO 35 0 a L 144 Dual amp UPA ADDR1 28 0 System Y Bice Controller Le x lt 3 U gt DSC BMX MRB_CTRL MWB_CTRL Muxes UPA64S_DATA 63 0 J Si 3 2 A D D Y Y 288 A lt UPA to SBus E gt Interface La z m U2S a yl s 2 SI g 2 o ES A Y Y Y de Y Memory UPA64S I O Board Connectors Connector Connector Graphics connector is located on the I O Board but coupled directly to the System Board Themis Computer 4 2 4 Hardware Overview
44. e upon the desired configuration before shipment of the board Getting Started How to Start Quickly This document presents the Theory of Operation of the USP 2 It is intended to be a general purpose guide to the USP 2 for system architects programmers technicians and other users Technical discussions begin from an architectural perspective of a given topic and then proceed to those aspects of a general Sun architecture as it is implemented in the USP 2 board from a programmer s view The information presented here is also written for the technician In most cases all that will be needed in the laboratory is this document and the appropriate toolkit Finally the discussion retains a global view that is useful to a less technical user Product Warranty and Registration Please review the computer warranty information packaged with your USP 2 processor board Your USP 2 single board computer is automatically registered when it leaves the factory based on the information provided in the sales order All computers are tracked via the serial number The warranty service period is based on the original shipment date from the factory Themis Computer 1 Introduction 1 4 1 2 1 4 2 Unpacking the USP 2 Caution The USP 2 contains statically sensitive components Industry standard measures use of a grounded wrist strap must be observed when removing the USP 2 from it s shipping container and during any subsequent handling
45. eboot the system WARNING Powering down EEES Severe over temperature condition detected Themis Computer 4 Hardware Overview e Shutdown temperature The USP 2 DC DC converters are turned off to protect the CPU modules The front panel SHUT DOWN LED is turned on Solaris s action on Warning temperature is controlled by an entry in etc inittab p3 s1234 powerfail usr sbin shutdown y i5 g0 gt dev console 2 gt 41 This entry can be changed by the system administrator Table 4 4 Indicative Ambient Temperature Thresholds CPU type Warning temperature Shutdown temperature deg C deg C 300 MHz 59 73 400 MHz 55 60 Caution Although the USP 2 temperature monitoring system provides a reasonable way to protect the board against over temperature it is not an absolute protection or a substitute for a full monitoring of system temperature System integrators must take into account all operating conditions that will affect cooling efficiency like air velocity humidity etc Themis Computer 4 15 USP 2 Hardware Manual 4 16 Themis Computer 5 1 5 2 Reset Overview This chapter covers system generated resets Other types of resets generated and observed only by the local processor are not described in this chapter Examples of resets not covered in this chapter are Software Initiated Reset SIR and Watchdog Reset WDR Resets are used to force all or
46. ensnrasenee 8 13 Fipure 8 5 Paddle Board Cornectors 4 a sect id A ci 8 14 Themis Computer ix USP 2 Hardware Manual x Themis Computer List of Tables Listof Tables Table 2 1 VME Bus Addressing Data Transfer Modes AAA 2 6 Table 3 1 USP 2 Hardware and Performance Specifications ooococonocccnonnnnnocnnononannnncnonnnccnnnncnnnnno 3 1 Table 3 2 USP 2 Operating Environmental Specifications ooconnnccnnnnnnonononnnannconnnnoncnnnnnnnn cono nannno 3 4 Table 3 3 USP 2 Non operating Environmental Specifications 00 0 0 ee eeeeesseceeeeeneeenaeeeteeeneees 3 4 Table 4 1 UPA Port ID Assignme ntsuunnsadskusssadakridenemn aiii 4 5 Table 4 2 AUdIO IPECINCAMONAS ti iio 4 11 Table 4 3 LED Desenpton vestidas di donan tado anaconda ed ciaci n 4 14 Table 4 4 Indicative Ambient Temperature Thresholds bk 4 15 Table 5 1 A A A E 5 5 Table 6 1 CPU tO UBA SPEAR a da 6 2 Table 7 1 AAA AA A Stiaan 7 5 Table 7 2 SCSI Interface Setting merino aan EE E E EE E E a TS 7 5 Table 7 3 Keyboard Mouse Ports C D Settings sssssssesseesseesseeesseeesseessressessseeessseessresseesseesssees 7 6 Table 7 4 Serial Port A and NEE 7 7 Table 7 5 Ethernet 100 Basel Senin Lage ais 7 8 Table 7 6 A N 7 8 Table 7 7 Flash Prom Settings eiii lila riales 7 9 Table 7 8 General Purpose E erte dicas 7 9 Table 7 9 Printer floppy ComMeuratlons secccsigis scacdasvascanasovsndeassndeeds irene ninel cdi edi and 7 10 Table 8 1 Serial Ports A B Connect
47. es are tristated at power up Major System Activities as a Function of Reset Table 5 1 shows the effects of the various different resets in an Themis USP 2 system Table 5 1 System Reset Effects Reset Sources USC Memory Reset Reset Reset CPU UPA Register Refresh I O UPA UPA XIR Reset to Devices Graphics Arbiter the CPU Power Supply POR Reset Disable Yes Yes Yes No Yes Push button POR Reset NC Yes Yes Yes No Yes Push button XIR NC NC No No No Yes No Scan POR Reset NC Yes Yes Yes No Yes Scan XIR NC NC No No No Yes No Software POR Reset NC Yes Yes Yes No Yes Software XIR NC NC No No No Yes No Error Reset Reset NC Yes Yes Yes No Yes Wake up Reset NC NC No No Yes No Yes a NC No Change Bits in the DSC Control Register will be set to the proper value based on the type of reset received by the DSC Bus Conditions at Power up It is important to insure that all buses are tristated at power up This prevents drive fights To be completely safe these buses must tristate whether or not the device interfacing to them is being clocked Otherwise failure of a clock generator could cause permanent damage to a chip on the board Bused system signals are e UPA Address Bus 0 e UPA Processor Data Bus e UPA 64 bit Data Bus e Memory Data Bus e SBus EBus Themis Computer 5 5 USP 2 Hardware Manual 5 3 2 1 5 3 2 2 5 3 2 3 5 3 2 4 5 3 2 5 UPA Address
48. esses Themis Computer 4 9 USP 2 Hardware Manual 4 5 1 1 4 5 1 2 4 5 1 3 4 5 1 4 4 5 1 5 4 5 1 6 4 5 1 7 4 10 PIO Operation A processor which wishes to access the SBus makes a UPA request which is forwarded to the U2S The U2S processes the request and if it is intended for the SBus routes it down to that bus Write operations are buffered Errors are reported asynchronously Refer to Chapter 9 of the Programmer s Guide Error Handling for more details on the error behavior Note Hardware detection of synchronization between DVMA writes and PIO reads to the SBus is not provided DVMA Operation All DMA transactions from SBus are actually DVMA transactions This means that a virtual address is put on the SBus and the U2S chip performs translation of that virtual address into a physical address recognized by the system Translation is performed by the IOMMU Bypass is provided for when translation is not desired Interrupt Dispatching All interrupts on the UPA are performed as transactions packets The U2S works in conjunction with the RIC ASIC to translate level sensitive interrupts into packets which are delivered to the processor Registers are present to control the mapping between the physical interrupt wire and the corresponding code delivered in the interrupt packet Registers also control the target of the interrupt Interrupt transactions which go out on the UPA will never pass DVMA transaction
49. he U2S and SBus clock values are correct at power up They default to 50 MHz and 25 MHz respectively Both clocks are TTL levels Themis Computer 6 Clocks Figure 6 2 USP2 CPU and System Clock Schematic UltraSPARC CPU 0 MC100LVEL39 UltraSPARC CPU 1 USC U2S UDB 400 800Mhz MP Systems Only 6 4 Other Clocks In addition to the clocks listed above the following clocks or crystals are present in the system 10 MHz for Ethernet and U2S timers e 24 MHz for the Floppy Controller e 40 MHz for SCSI Themis Computer 6 3 USP 2 Hardware Manual xtal II 6 4 MC12439 Figure 6 3 USP2 SBUS Clock Schematic MC10H64 n 50 MHz to U2S freq generator and PLL Themis Computer 25 MHz to SBus Devices on the VSIC QS5917T 25 MHz to SBus Devices on the I O QS5917T 4 25 MHz to SBus Devices 25 MHz to SBus Devices on the CPU QS5917T Used to distribute the SBus clocks 7 1 7 Jumper and Solder Bead Configurations Overview This chapter provides a summary of the jumpers and solder beads configurations on the USP 2 Jumpers are considered to be field configurable and may be altered by a user on site Solder beads are considered to be factory configurable
50. hemis Customer Support North America South America and Pacific Rim Telephone 510 252 0870 Fax 510 490 5529 E mail support themis com Web Site http www themis com USP 2 Hardware Manual March 8 2001 Part Number 108084 Version Revision History Version 1 4 Miscellaneous typos and errors corrected Also e Added VME bus addressing data transfer mode Gbles page 2 6 e Modified audio p r meen vase pages 3 3 8 7 e Modified board jumper pin dagrams pages 7 2 7 3 e Divided Table 8 1 Signal Name column into Serial Port A and Port B page 8 3 e Modified System Board VME P2 connector pin descriptions pages 8 9 8 10 March 8 2001 Version 1 3 Reorganized sections Re created Reset chapter Added description of LED and Temperature monitoring in Chapter 4 Added paddle board diagram in Chapter 8 Fixed minor errors June 30 2000 Version 1 2 Misc typos and errors corrected Jumper 2001 Added jumper and front panel drawings May 18 1999 Version 1 1 Misc typos and errors corrected March 20 1999 Version 1 0 Rev X1 3 Preliminary May 30 1998 Themis Computer iii USP 2 Hardware Manual iv Themis Computer Table of Contents Table of Contents Introduction 1 1 INTO e EE 1 1 132 Id 1 1 1 3 SAS SENG 1 1 1 4 Gems Sala 1 2 1 4 1 How to SET Quickly EE 1 2 1 4 1 1 Product Warranty and Regtstraton 1 2 14125 Unpackme the Keesen 1 3 1 4 2 In Case of Dirt CO ies cases 5
51. ining registers RIC ASIC The RIC ASIC contains logic for dock generation reset control interrupt concentration and JTAG control Themis Computer 4 Hardware Overview 4 7 USP 2 Flow Diagram Cache CPU Module 0 UDB 144 CPU Module 1 Cross Bar Switch 12 data I O Memory Dual Processor message oriented G Controller System Controller bidirectional 28 UPA to Memory decoupled data A SEAN Interface DSC packet oriented Vo request UPA to reply SB s Controller VNE Interface STP2220 U2S VNE I F Memory Module SBus Slot 0 SBus SBus Slot 1 SCSI Serial FEPS 1 FEPS 2 Ethernet 3 APC GE Floppy Printer Prom Audio SCSI Ethernet Figure 4 5 USP 2 Flow Diagram Themis Computer 4 13 USP 2 Hardware Manual 4 8 4 9 4 14 User LEDs The following table contains a description of the LEDs located on the front panel of the USP 2 Table 4 3 LED Description LED Description Color SYSTEM Board is running Controlled by SLAVIO Aux1 register see USP 2 programmer s manual This LED is cleared on Reset and set by OBP initial code Green SYS CON Board is VMEbus System Controller Reflects status of jumper JP1201 Green SYS FAIL
52. lA232 ElA423 14 SER_TXDB_A SER_TXDB_B Transmit Data Input ElA232 ElA423 15 SER_TRXCB_A_L SER_TRXCB_B_L Transmit clock Input ElA232 ElA423 16 GND GND Ground Input ElA232 ElA423 17 SER DTRB AL SER_DTRB_B_L Data terminal ready Input ElA232 ElA423 18 SER_RTSBA L SER RTSB BL Request to send Input ElA232 ElA423 19 NC NC Non connected 20 SER_SYNCB_A_L SER SYNGB BL Output ElA232 ElA423 21 NC NC Non connected Output ElA232 ElA423 22 SER DCDB AL SER_DCDB BL Carrier detect Output ElA232 ElA423 23 SER CTSB AL SER CTSB BL Clear to send Output ElA232 ElA423 24 GND GND Ground 25 SER_RTXCB_A_L SER_RTXCB_B L Receive clock_B Output ElA232 ElA423 26 SER_RXDB_A SER_RXDB_B Receive data Output ElA232 ElA423 Themis Computer 8 3 USP 2 Hardware Manual 8 2 2 Keyboard Mouse Connector Female 5 KB_OUT 8 KBM_5VF 7 POWER ON 6 GND 2 MOUSE_IN KB_IN 3 KBM_5VE GND 1 Figure 8 2 Keyboard Mouse Connector Pinouts Table 8 2 Keyboard Mouse Connector Pinouts Pin Signal Name Description Direction 1 GND Ground ES 2 GND Ground 3 KBM_5VF 5 VDC Input 4 MOUSE_IN Mouse in Input 5 KB_OUT Keyboard Out Output 6 KB_IN Keyboard In Input 7 POWER_ON RTC Alarm or Frequency Test Output 8 KBM_5VF 5 VDC Ethernet 100BaseTX A and B RJ45 Connector H 1 Figure 8 3 10
53. le 2 1 VME Bus Addressing Data Transfer Modes Master DMA Slave A16 A24 A32 A16 A24 A32 A16 A24 A32 D08 Y Y Y D08 N N N D08 N Y Y D16 Y Y Y D16 N Y Y D16 N Y Y D32 N Y Y D32 N Y Y D32 N Y Y D32 BLT N N N D32 BLT N Y Y D32 BLT N Y Y MBLT D64 N N N MBLT N N Y MBLT N Y Y D16 BLT N Y Y Themis Computer 3 USP 2 Hardware Specifications This chapter describes these USP 2 specifications e Hardware and performance specifications e Electrical power specifications Environmental specifications 3 1 Hardware and Performance Specifications Table 3 1 USP 2 Hardware and Performance Specifications Physical Dimensions CPU Board Size 6U Number of VME slots taken 5 CPU Performance Number of Processors One or two UltraSparcll CPU Estimated SPECint95 Performance 12 10 est single 300MHZ Estimated SPECfp95 Performance 20 2 est single 300MHZ Estimated SPECint_rate95 219 est dual 300MHZ Power requirement The CPU modules utilizes a large amount of 3 3V power in addition to standard 5V Since 3 3V is not distributed on standard VME backplanes a pair of DC DC converters are provided on board to convert 5V to 3 3V The two converters generate 3 3V and 3 3V CORE respectively A five slot wide power and I O distribution paddle board is connected to the P2 connectors of both boards at the rear of the backplane This pa
54. located on the front panel AND on the Paddle Board via the P2 I O SCSI Port 2 A 68 pin high density connector located on the front panel AND on the Paddle Board via the P2 I O SCSI Standard ANSI X3 133 SCSI Types Dual FAST WIDE 20MB sec Ethernet 1 Connectors RJ 45 jack for 10Base T twisted pair Standard connector T bases 10 100 on the Front Panel Standard connector DB 15 on the Paddle Board via P2 I O Ethernet 42 Connectors 2 will be twisted pair Ethernet Standard IEEE 802 3 Printer Parallel DB 25 Connector on the Paddle Board via P2 I O Printer Standards IEEE 1284 Serial A B Ports One 26 pin D Sub Serial Standard EIA 232 E EIA 423 A Serial Types Synchronous Asynchronous Serial Configuration DTE Serial Performance 19 200 19 2 Kbit baud Hardware to 76 8 Kbaud Solaris to 38 4 Kbaud Keyboard Mouse Port 8 pin mini circular jack Floppy Diskette Drive Intel 82077 compatible 34 pin ribbon connector 3 2 Themis Computer 3 USP 2 Hardware Specifications 3 2 Table 3 1 USP 2 Hardware and Performance Specifications Audio Headphone Audio jack connector stereo EIA standard 3 5mm 0 125 jacks Audio Line In Audio Jack connector stereo EIA standard 3 5mm 0 125 jacks Audio Performance Voice standard 8 bit 8 Khz and CD quality 16 bit 48 Khz On board Main Memory Description of Memory Up to 2 Modules mounted on top of the System board
55. mputer 3 3 USP 2 Hardware Manual 3 4 Table 3 2 USP 2 Operating Environmental Specifications Description Minimum Value Maximum Value Temperature Range OG 50 C Humidity Range relative 5 95 non condensing at 104 F 40 C Wet Bulb Maximum Not applicable 77 F 25 Altitude Range 0 feet 0 meters 10 000 feet 3 408meters Air Flow 300 Ifm airfow at 50 C Table 3 3 USP 2 Non operating Environmental Specifications Description Minimum Value Maximum Value Temperature Range 40 C 85 C Humidity Range relative non con 5 95 densing at 104 F 40 C Wet Bulb Maximum Not applicable 115 F 46 C Altitude Range 0 feet 0 meters 38 370 feet 12000 meters Themis Computer 4 1 4 2 4 Hardware Overview Overview This chapter provides a brief hardware overview of the USP 2 Detailed information about each component can be found in the respective component specification Operations of individual peripheral devices will not be covered The UPA interconnect provides interconnection at the highest level Components interfacing through the UPA interconnect are processor subsystem System Controller Buffered Crossbar Chip memory and I O subsystem Processor subsystem includes the UltraSPARC II processor E cache Tag and Data RAM and the UDBs The System Controller provides overall control to the UPA interconnect and memory The I O subsystem consists of th
56. n the bus Arbitration among device in accessing the address bus 0 is described in a later section The USP 2 may implement a second address bus used for graphics I O Graphic option The UPA interconnect uses geographical addressing to select the target device Each port is assigned with an address range to respond to The System Controller hardwires the address range of each UPA slave port and routes UPA packets to the proper destination The UPA Address Valid signal is driven active to indicate a valid address on the address bus Associated with each address packet is a reply packet There are two sets of reply signals for each UPA port a UPA port reply and a System Controller reply Each port has to supply dedicated UPA port reply signals to the System Controller The System Controller also needs to supply each port with a dedicated System Controller reply signals UPA protocol requires that each UPA device respond to the access targeted to its slave port Failure to reply to a slave access may hang the system indefinitely The encoding of replies is such Themis Computer 4 5 USP 2 Hardware Manual 4 3 4 4 3 5 4 3 6 4 4 4 6 that connected ports indicate a P REPLY code representing idle immediately after reset Unconnected ports normally return a P REPLY code of UPA read time out if they are present Ports which are present must return idle after being reset Any other code is interpreted as device not present UPA Data
57. nd Solder Bead Configurations 7 3 7 4 CPU Clock Settings Table 7 1 CPU Clock Settings Reference Location peau Description setting JP1701 System 2 3 Cpu clock ratio mode Board The CPU clock ratio can be set automatically based on the logic level of the signal Cpu_Ratio generated by the RIC controller or can be forced to a specific value based on the setting of the jumper JP1702 Cpu clock ratio select In position 1 2 see jumper JP1702 setting description In position 2 3 Cpu ratio 0 then Raw clock Cpu clock 2 Cpu ratio I then Raw clock Cpu clock 4 JP1702 System 1 2 Clock clock ratio select Board When the JP1701 is set in position 1 2 manual mode this jumper becomes effective and defines the ratio between the raw clock generated by the PLL MC12349 and the Cpu clock provided to the Cpu modules In position 1 2 Raw clock Cpu clock 4 In position 2 3 Raw clock Cpu clock 2 SCSI Interface Settings Table 7 2 SCSI Interface Setting Reference Location ea Description setting JP1101 JP1101 2 3 1 2 Disable on board SCSI termination for port A on I O 2 3 On board termination is automatically disabled JP2501 Board when a SCSI device is plugged on front AND on the for port B JP250 on back P2 paddle board system In all other situations on board termination is board enabled Themis Computer 7 5 USP 2 Hardware Manual 7 5
58. nual 6 3 Phase OSC Four Divide M P Divide N S LOAD S DATA S_CLOCK pp Configuration Interface Logic 3 ee eg We M P LOAD N Figure 6 1 Simplified Block Diagram of Clock Generator UPA Processor and SBus Clocks Figure 6 2 shows the detail of the clock generator for the CPU and UPA UltraSPARC II modules start with hardwired frequency of 160MHz CPU clock This means that the ultraSPARC II is running at 160Mhz and 53 33MHz UPA clock After power up OBP will identify the type of module residing in the systems UltraSPARC II will be identified by the UPA CONFIG register This register will also identify the speed table to use in programming the frequency synthesizer UPA CONFIG register is read for the proper UPA module speed Both processors must have the same speed setup Different module speed values are allowed the slowest will be used by OBP to set final operating speed Depending on the determined CPU speed the UPA will run on a 3 1 or 4 1 ratio in accordance to Table 6 1 Table 6 1 CPU to UPA Speed ratio Module Speed UPA Speed 248 Mhz 82 67 Mhz 296 Mhz 98 67 Mhz 400 Mhz 100 Mhz 6 2 The U2S and SBus clock generator is very similar to the UPA and CPU clock It has a fixed 2 1 frequency ratio Figure 6 3 shows the SBus clock generator While software programmable t
59. on the paddle board Configuration NOTE The printer interface and the floppy interface use the same pins on P2 That means they cannot be used at the same time Table 7 9 Printer floppy Configuration Reference Location Pl Description setting JP3401 System Printer All jumpers on 1 2 Printer selected board All jumpers on 2 3 Floppy selected Themis Computer 7 9 USP 2 Hardware Manual 7 10 Themis Computer 8 1 Introduction 8 Connectors and Pinouts The USP 2 has various connectors located on the front panel the baseboard CPU Board the I O board and the optional paddle board Each of these connectors are listed below and described in a separate section with illustrations and or tables featuring a complete listing of the connector pinouts Front Panel Connectors e TTY A This is the console port e TIYB e Sun Keyboard Mouse e 100BaseTx Ethernet port A and B e Fast wide SCSI port A and B e Audio System Board VME Connectors VMEbus P1 Connector VMEbus P2 Connector I O Board VME Connectors VMEbus P1 Connector VMEbus P2 Connector I O Board SBus Connectors SBus Connectors 1 and 2 Paddle Board Connectors e B W SCSI 2 e TTY C D e MII Ethernet 2 e Parallel Port e Floppy Port Themis Computer USP 2 Hardware Manual 8 2 Front Panel Connectors Described below are the connectors located on the front panel of the USP 2 Included are illustrati
60. ons and or tables featuring a complete listing of the connector pinouts The views presented are taken while looking at the front panel Figure 8 1 USP2 Front panel AUDIO IN O AUDIO OUT Le SUN Keyboard Mouse SYSTEM SERIAL Port B SYSCON O ds SYSFAL SHUT DOWN 6 VME ACCESS SERIAL Port A RESET o ABORT 0 ENET LINK B A ETHERNET Port A SCSITERMBO A USR LEDO USR LED2 963 ETHERNET Be SCSI B SCSI A O 8 2 Themis Computer 8 Connectors and Pinouts 8 2 1 TTY Aand TTYB Connectors Female Table 8 1 Serial Ports A B Connector Pinouts Signal Name Description Direction Level ge Serial Port A Serial Port B 1 SER_TXDA_A SER_TXDA_B Transmit Data Input ElA232 ElA423 2 SER TRXCA A L SER TRXCGA B L Transmit clock Input ElA232 ElA423 3 GND GND Ground 4 SER DTRA AL SER DTRA BL Data terminal ready Input ElA232 ElA423 5 SER_RTSA_A_L GER RTSA B L Request to send Input EIA232 EIA423 6 NC NC Non connected 7 SER SYNGA A L SER SYNCA BL 8 NC NC Non connected 9 SER DCDA AL SER DCDA BL Carrier detect Output ElA232 ElA423 10 SER CTSA AL GER CTSA BL Clear to send Output ElA232 ElA423 11 GND GND Ground 12 SER_RTXCA_A_L SER RTXCA B L Receive clock Output ElA232 ElA423 13 SER_RXDA_A SER_RXDA_B Receive Data Output E
61. or PIU A Gael 8 3 Table 8 2 Keyboard Mouse Connector Pinouts e teste eegene eg 8 4 Table 8 3 100Base T Ethernet Connector et EEN 8 4 Table 8 4 Fast wide SCSI A and B Connector Pinout anernnnrnvnrnnvvnrenvnnnnenvvrnrevrnsnvnnnrnsvrasevsssnesenn 8 5 Table 8 5 Audio Port EE 8 7 Table 8 6 A e Mona a e aa a a aae es 8 7 Table 8 7 VMEbus P1 connector description system board esnrrrnnrrvnnnrrvernrrvennrnvennrnennrneenrreern 8 8 Table 8 8 VMEbus P2 connector description system board oooonnnocccnocccoooccnooncnonancconanacononacinncnos 8 9 Table 8 9 VMEbus P1 connector description I O board cee eeeceeeseeeeeeeeceeeeeceeeeeeseeeeneeesaeees 8 10 Themis Computer xi USP 2 Hardware Manual Table 8 10 VMEbus P2 connector description I O board ooooonccccnoccccnoncconancnnonncnnnnccnnnnccnnnnccnnn nos 8 12 Table 8 11 Serial Ports C D DB9 Comme Ctr sc 5 ccissecjssetasenecessavedansasuebaacsenscceds nogsantecusdendescbedantasusnencys 8 15 Table 8 12 Paddle board SCSI A and B connectors 0 e ce eeeceeeeeceestececeeececseeeeeeeecseeeesteeeeseeeesaes 8 16 Table 8 13 Paddle board parallel port sss 2v2v4 45 RPG 8 18 Table 8 14 Paddle board EE ai dd ee 8 18 xii Themis Computer 1 1 1 2 1 3 1 Introduction Introduction Thank you for purchasing the Themis USP 2 single board computer with VMEbus interface Themis Computer is a leading manufacturer of SPARC based processor boards for the VMEbus marke
62. ou can verify proper physical connection by executing the FORTH network selftest test net This test will indicate external loopback failure on each of the network interfaces when there is not a proper physical connection As only one interface can be active the inactive network interface will always return an external loopback error p ok test net Using AUI Ethernet Interfac Lance Register test succeeded Internal loopback test succeeded External loopback test Lost Carrier transceiver cable problem send failed Using TP Ethernet Interfac Lance Register test succeeded Internal loopback test succeeded External loopback test succeeded send ok net selftest succeeded o Bi Attaching a Keyboard and Mouse A standard SUN type 4 or type 5 keyboard mouse combination can be attached to the front panel keyboard connector or on the paddle board if you prefer to have it connected to the back of the board Themis Computer 2 5 USP 2 Hardware Manual 2 7 Note The POST power on self test displays the message Warning JO301 and J0302 on the I O board are not configured for the front panel mouse keyboard interface VME Bus Addressing Data Transfer Modes no keyboard detected if no keyboard is attached to the USP 2 This message may alternately indicate that configuration jumpers Table 2 1 describes the VME bus addressing data transfer modes supported by the USP 2 Tab
63. part of the system into a known state In the USP 2 resets are sourced from power supply push button scan interface software error conditions and power management logic They are converted into three types of resets in the system power on reset POR externally initiated reset XIR and UPA arbiter reset Their assertions have different level of effects on the system Information stored in the USC Control Register allows software to determine where the reset originated Reset Sources Resets come form various sources They are converted by the System Controller into two sets of signals UPA_RESET_L lt 1 0 gt and UPA_XIR_L Processor s receiving UPA_RESET_L lt 0 gt will treat the assertion of this signal as a POR The U2S receives both UPA RESET L lt 1 0 gt reset signals The UPA_RESET_L lt 0 gt signal is used by the U2S as an UPA Arbiter Reset UPA graphic devices receive an UPA_RESET_L lt 1 gt Separate UPA RESET L signals are needed for the processor and U2S Graphics for power management reasons The U2S will use the UPA RESET L lt 1 gt signal to derive an SBUS_RESET_ for on board I O devices and SBus slots The XIR reset is only observed by the processor The System Controller will assert UPA_XIR_L for one clock cycle when it detects an XIR condition The following block diagram in Figure 5 1 shows how resets are generated and distributed in the system Themis Computer 5 1 USP 2 Hardware Manual 5 2 1 5 2
64. rains the data out of its UPA port interface it can send a P_Reply to the System Controller The purpose of this P_Reply is to provide flow control of data It informs the System Controller that it has room for further incoming data Precise transfer errors cannot be reported by a P_Reply The error will be dropped or reported as an interrupt Themis Computer 4 Hardware Overview 4 3 3 e Coherent Read When the System Controller detects a coherent request it will perform a snoop operation to the external dual tag if DTAG is provided It also starts a memory request in parallel with snoop operation In the case of a snoop miss data will be provided by memory The System Controller schedules the datapath based on the availability of memory data and issues S_Reply to the requesting master In the case of a snoop hit the System Controller issues a copyback or copyback invalidate request to the UPA port that owns the block If the coherent read also requires invalidation of another cache invalidate requests will be issued to other UPA ports that also have this block in their cache When the UPA slave port is ready to send out copyback data it issues a P_Reply to the System Controller If no invalidation is involved the System Controller will schedule the datapath and issue a S_Reply to both the UPA slave port and the UPA master port to send receive data Otherwise the System Controller has to wait until all invalidate operations are complete
65. s use EIA standard 3 5mm 0125 inch jacks Table 8 5 Audio Port Signals Headphone Line in Tip Left Channel Left Channel Ring Center Right Channel Right Channel Shield Ground Ground Table 8 6 Audio Port Functions Port Function Headphones Connects stereophonic headphones for private listening of audio output Line In Connects external stereophonic audio sources such a compact disc player or cassette tape player to the system Themis Computer USP 2 Hardware Manual 8 3 VME Connectors Described below are the VME connectors located on the system board of the USP 2 VMEbus P1 Connector System Board The following table contains signal description for the VMEbus P1 system board connection Unused connections are specified as NC Non connected Table 8 7 VMEbus P1 connector description system board Pin Row A Row B Row C 1 NC NC NC 2 NC NC NC 3 NC NC NC 4 NC Connected to B5 NC BGOIN BGOOUT 5 NC Connected to B4 NC BGOIN BGOOUT 6 NC Connected to B7 NC BG1IN BG10UT 7 NC Connected to B6 NC BG1IN BG10UT 8 NC Connected to B9 NC BGO2N BG2OUT 9 GND Connected to B8 GND BG2IN BG20UT 10 NC Connected to B11 NC BG3IN BG30UT 11 GND Connected to B11 GND BG3IN BG30UT 12 NC NC NC 13 NC NC NC 14 NC NC NC 15 GND NC NC 16 NC NC NC 17 GND NC NC 18 NC NC
66. s which occurred prior to the interrupt DVMA transactions may pass an interrupt UPA Interface The U2S implements a 72 bit UPA interface ECC Checking Generation All packets to or from the UPA have ECC The U2S logic performs ECC generation and checking SBus Interface One of the major functions of the U2S is to bridge the UPA and SBus It implements an IEEE P1496 compliant SBus interface Streaming Buffer Streaming Buffers perform read ahead write behind transfers to speed up sequential I O activity The transfers act to buffer data on the way to or from memory Themis Computer 4 Hardware Overview 4 5 1 8 4 5 1 9 4 5 2 4 5 3 IOMMU As mentioned in 4 5 1 2 DVMA Operation the IOMMU performs translation between the virtual SBus address and a physical address In addition it supports bypass operation for devices not needing address translation and pass through when not enabled Timer Counter Two Timer Counters generate interrupts when the counter matches the programmed timer value and are useful for interrupting the system at specified intervals in the future Two Timer Counters are provided by the U2S FEPS 1 and 2 The FEPS chips implement the SBus interface to three master I O devices Ethernet SCSI and the parallel port It contains three DMA channels implemented in its DMA2 block one for each device supported Note On FEPS 2 the parallel port is not supported Audio APC Th
67. se the USP 2 in a workstation configuration instead of as an embedded controller you will also need a hard disk and graphics frame buffer or serial terminal Installing the USP 2 and its Paddleboard in the VME chassis The USP2 VME board takes 5 VME slots in width see Figure 2 1 The active VME slot of the USP2 is slot 4 This means that the USP2 VME controller drives the VME signal from slot 4 In case you don t have an automatic jumpering VME chassis this requires daisy chain signals to be jumpered on your VME chassis backplane Failure to do so may prevent proper interrupt and arbitration function in your VME chassis Note If you are only planning to have slave only VME boards along with the USP2 you don t need to jumper any of those daisy chain signals e VME slotftl IACKIN OUT e VME slot 2 IACKIN OUT VME slot 3 IACKIN OUT VME slot 4 Do not place any daisy chain jumpers here e VME slot 5 IACKIN OUT VME slot 5 BUS GRANTO IN OUT VME slot 5 BUS GRANT1 IN OUT VME slot 5 BUS GRANT2 IN OUT V ME slot 5 BUS GRANT3 IN OUT Themis Computer 2 Installation VME Slot 5 VME Slot 4 Active VME Slot 3 VME Slot 2 VME Slot 1 2 4 Figure 2 1 USP 2 Assembly SBus Graphics Board VSIC Board includes VME I F T O Board Memory Board System Board Memory Board Pro
68. t We value our customers comments and concerns Our Marketing department is eager to know what you think of our products A Reader Comment Card is located at the end of this manual for your use Caution Before you begin carefully read each of the procedures in this manual Improper handling can cause serious damage to the equipment Scope The purpose of this document is to provide a hardware overview of the USP 2 This manual is written for system integrators and programmers It contains all the necessary information to install and configure the USP 2 processor board It is assumed that the Sun Open Boot PROM OBP is installed If you intend to use another operating system or a real time kernel such as VxWorks please consult the appropriate documentation accompanying your OS or kernel software The reader is assumed to be familiar with and have a working knowledge of the UltraSPARC II processor architecture and current VMEbus SBus Ethernet and SCSI specifications Although all USP 2 specific hardware and software features are described in detail in this manual programmers wishing to code the USP 2 without the benefit of an operating system or real time kernel will require additional data sheets and documentation for the system components comprising the USP 2 design USP 2 Systems Overview The USP 2 is a high end dual processor desktop workstation based on Sun4u formerly known as Sun5 system architecture Themis Computer 1
69. ter The deassertion edge of 5 Reset 5 2 1 1 5 2 1 2 5 2 1 3 5 2 1 4 5 2 1 5 Power Supply POR After the system power supply is turned on and before the power supply output stabilizes the power supply will drive the POWER_OK signal inactive to put the system in a reset state When the supply voltage reaches a level to support a functional system the power supply will drive the POWER_OK active The RIC chip uses this signal to generate power on reset POR during the period POWER_OK is inactive to reset the entire system It extends the reset period for 12 8 ms after the POWER_OK signal becomes active The extra time is needed to allow the PLL circuitry to stabilize The RIC chip asserts SYS_RESET_L to the System Controller during the whole reset period Since the SBus clock is also derived from the synthesizer which has PLL circuitry in it the RIC chip cannot use it as the source for the internal counter The RIC chip will use a 10 MHz clock to count the extended reset time Push button POR An external push button is provided to allow the user to trigger a reset to the system Two types of push button resets are available Push button POR and Push button XIR A Push button POR has the same effect as a Power Supply POR The only difference between these two is the status bits in USC Control Register and the state of refresh unchanged with B POR The P_BUTTON bit will be set to indicate the reset is initiated by a push but
70. terrupts to the interconnect and handling interrupt flow control as defined by the interconnect An interrupt receiver is a device capable of handling interrupt and providing necessary flow control on interrupt packet across the interconnect The System Controller is the key element of the UPA interconnect The services it provides are coherence control memory control datapath control flow control transaction ordering and address routing A brief description of the System Controller will be provided in a later section Figure 4 2 shows the physical connections among UPA devices in the USP 2 system The following sections provide introductory information about the UPA For more detailed description of how the UPA works please refer to UPA Interconnect Architecture Themis Computer 4 3 USP 2 Hardware Manual 4 3 2 Processor UPA Address Bus 0 System 83 MH Controller z or DSC 100 MHz UPA Processor Data Bus UPA to UPA 64 bit Data Bus SBus 83 MHz U2S or 100 MHz Buffered Memory Data Bus Memory Crossbar Chip SU XB1 288 Modules SBus 25 MHz Figure 4 2 UPA Interface Block Diagram UPA Data Transfer Data transfers can happen between UPA devices or between a UPA device and memory Data transfer is initiated by the master interface of a UPA port The UPA port first asserts a request and waits for its turn to get the ownership of UPA
71. ton POR Push button XIR A push button XIR is provided to allow the user to reset part of the processor without resetting the whole system The System Controller will set the X_BUTTON bit in the USC Control Register when a Push button XIR is detected An XIR affects processors only It has no effect on the rest of the system such as the USC the U2S memory and any I O devices The effect of an XIR on the UltraSPARC II processor is different from POR Additional detailed information can be found in the USP 2 Programmer s Reference Manual Scan POR The scan controller can also assert reset to the system through the scan interface A Scan POR has the same effect as a POR from the power supply It shares the same status bit as the Push button POR The System Controller does not see the difference between Scan POR and Push button POR The same status bit P_BUTTON will be set in the USC Control Register Scan XIR The scan controller can scan in a command to the RIC to cause a Scan XIR This has the same effect as a Push button XIR The Scan XIR and Push button XIR share the same status information in the USC Control Register Note Do not assert a Push button POR or Push button XIR while coming out of a system reset power on condition This activates a special test mode in the USC chip which results in a shortened reset Themis Computer 5 3 USP 2 Hardware Manual 5 2 1 6 5 2 2 5 2 2 1 5 2 2 2 5 2 3 5 2 4 5 2 5
72. ts TREES 4 8 VO SEMA a E A E E A E A O ET 4 9 4 5 1 US eee o 4 9 51 PIO ea 4 10 45122 DVYMA Operas EN 4 10 4 5 1 3 Interrupt AA isse 4 10 45 14 AA arii ea s 4 10 4 5 1 5 ECC Checking Generation ssessseseseeesseesseessereseseesseessresseessee 4 10 AO SBS Interface senh E E E a E N 4 10 ASAT Streaming Buber ege ease aan 4 10 1508 A 4 11 45 19 Timer Comtat 4 11 4 5 2 PEPSI NTL mek AR EEN 4 11 4 5 3 Audio APO 4 11 4 5 4 SLAVIO ie A R E E E OEE R E E TAE ERE 4 12 4 5 5 EBUS DEE dee ee ee 4 12 RICAS CE A 4 12 USP2 Flow D r pva Sonate aat edge 4 13 Ver LED ass 4 14 Temperature Monitoring 0 ed det 4 14 ENE 5 1 Reset SOURCES ito 5 1 5 2 1 Hardware Reset Sources ensins asesi a a EaR E i Eia 5 2 SLA Power Supply EH 5 3 321142 Pobbu POR ARR 5 3 Themis Computer Table of Contents 5 213 Push button XIR iaa dai its IZ LA SAN TEE 21 57 SEM A ad A AA en STE lt SYSRESET E Ra ARR E 5 2 2 Soft ware Reset Luna Bees is so Ass breaks 221 Software POR conan susi das 52220 SoHw re XIR paaske eee 5 2 3 Error Reset ari a a ease Ea 5 2 4 Wake up Reset uusansmnunninundniemsnisenuiteeiissvihes 5 2 5 UPA Arbitration Res timida 5 3 BHEGSOERSSEN e EE 5 3 1 Major System Activities as a Function of Reset 532 Bus Conditions at Power UD Ai AEN 5 3 2 1 UPA Address Bus 0 5 3 2 2 UPA Processor Data Bus ssssoseneeesosssseeoeessressesereesesssseseees SE Memory EE SE GE EE A EE Clocks 6 1 COV OL VIC Weer re cers O Oe EE e

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