Home

the user manual for the HPDI32A-ASYNC

1. 5 12 DMA CHANNEL 1 COMMAND STATUS REGISTER 0 PCI OFFSET 8 A 5 13 DMA ARBITRATION REGISTER 1 5 14 DMA THRESHOLD REGISTER I A 6 MESSAGING QUEUE REGISTERS A 6 1 OUTBOUND POST LIST FIFO INTERRUPT STATUS REGISTER PCI OFFSET 0x30 A 6 2 OUTBOUND POST LIST FIFO INTERRUPT STATUS REGISTER PCI OFFSET 0X34 6 3 INBOUND QUEUE PORT REGISTER PCI OFFSET A 6 4 OUTBOUND QUEUE PORT REGISTER PCI OFFSET OX44 eese tette tenete tenete tette A 6 5 MESSAGING QUEUE CONFIGURATION REGISTER PCI OFFSET A 6 6 QUEUE BASE ADDRESS REGISTER PCI OFFSET 4 6 7 INBOUND FREE HEAD POINTER REGISTER PCI OFFSET A 6 8 INBOUND FREE HEAD TAIL REGISTER PCI OFFSET OXQO eese A 6 9 INBOUND POST HEAD POINTER REGISTER PCI OFFSET A 6 10 INBOUND POST TAIL POINTER REGISTER PCI OFFSET 0 4 A 6 11 OUTBOUND FREE HEAD POINTER REGISTER PCI OFFSET OXD6 A 6 12 OUTBOUND FREE TAIL POINTER REGISTER PCI OFFSET 0 A 6 13 OUTBOUND POST HEAD POINTER REGISTER PCI OFFSET A 6 14 OUTBOUND POSTTAIL POINTER REGISTER PCI OFFSET OXEA eese tenete nee A 6 15 QUEUE STATUS CONTROL REGISTER User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual R
2. a 0 will indicate that Rx Receive Busy has not occurred Enable Interrupt on Tx Transmitter Busy If this bit is enabled as an interrupt a 1 will indicate that an interrupt on Tx Transmitter Busy has occurred a 0 will indicate that an interrupt on Tx Transmitter Busy has not occurred If this bit is not enabled as an interrupt a 1 will indicate that Tx Transmitter Busy has occurred a 0 will indicate that Tx Transmitter Busy has not occurred D31 23 22 16 TX CLOCK DIVIDER Offset 0x38 RW The Transmit Clock Divider Register has been removed from the PC HPDI32A ASYNC This function can be accessed thru the upper 16 bits of the Tx Status Block Length Register NOTE This register cannot be accessed using the currently released Windows NT Device Driver 22 17 RESERVED Offset 0x3C RW This register is reserved for future use NOTE This register cannot be accessed using the currently released Windows NT Device Driver 2 2 18 TX FIFO SIZE Offset 0x40 RO Upon Power up or any time FPGA code is reloaded the logic will fill Tx FIFO and count the number of writes until the FIFO is full This value is saved as the FIFO size and the FIFOs are reset The Counter is only 20 bits wide the upper 12 bits are undefined NOTE This register cannot be accessed using the currently released Windows NT Device Driver 19 Tx FIFO Size Number of D32 Words that the Tx FIFO Holds D31 D20 Undefined 2 2 19 RX FIFO SIZ
3. 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 16 CREATED ON OCTOBER 16 2001 2 2 1 FIRMWARE REVISION Offset 0x00 RO This Register is used to determine the version of firmware that is programmed into the board If the logic is changed to accommodate a modification for any reason then the value in this register is incremented Revision 0x000F0200 Original version after debug and final release D7 D0 D15 D8 Board Revision Currently HPDI32A Revision A D23 D16 Board Identifier 0x000F Identifies the HPDI32A ASYNC D30 D24 D31 Firmware Features Identifier Indicates that this board does not contains the Firmware Features Re 2 2 2 BOARD CONTROL Offset 0x04 RW The Board Control Register is strictly under software control and provides the following functionality s Resets the board Resets the transmit FIFOs Resets the receive FIFOs Enables the receive logic Enables the transmit logic Starts the transmission of data Mode control for the transmitter Mode control for the receiver Board Reset Writing a to this bit will generate a self timed pulse that is used to reset the on board logic and the FIFOs There is no need for the software to clear this bit the bit will clear itself D Tx FIFO Reset Writing a to this bit will generate a self timed pulse that will be used to reset the Tx FIFOs After setting this bit there should be a minimum of 25 Rx clk periods or 1 millisecon
4. 1 will indicate that an interrupt on the Tx FIFO full has occurred a 0 will indicate that an interrupt on the Tx FIFO full has not occurred If this bit is not enabled as an interrupt 1 will indicate that the Tx FIFO is currently full a 0 will indicate that the Tx FIFO is not currently full User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 25 CREATED ON OCTOBER 16 2001 Rx FIFO Empty If this bit is enabled as an interrupt 1 will indicate that an interrupt on the Rx FIFO empty has occurred a 0 will indicate that an interrupt on the Rx FIFO empty has not occurred If this bit is not enabled as an interrupt 1 will indicate that the Rx FIFO is currently empty a 0 will indicate that the Rx FIFO is not currently empty Rx FIFO Almost Empty If this bit is enabled as an interrupt 1 will indicate that an interrupt on the Rx FIFO almost empty has occurred a 0 will indicate that an interrupt on the Rx FIFO almost empty has not occurred If this bit is not enabled as an interrupt 1 will indicate that the Rx FIFO is currently almost empty a 0 will indicate that the Rx FIFO is notcurrently almost empty Rx FIFO Almost Full If this bit is enabled as an interrupt 1 will indicate that an interrupt on the Rx FIFO almost full has occurred a 0 will indicate that an interrupt on the Rx FIFO almost full has n
5. AL 35802 Phone 256 880 8787 39 CREATED ON OCTOBER 16 2001 A 2 10 PCI Base Address Register for Memory Access to Runtime Registers PCI Configuration Offset 0x010 Memory space indicator A value of 0 indicates register maps into Memory space A value of 1 indicates the register maps into I O space Note Hardcoded to 0 Location of register 00 Locate anywhere in 32 bit memory address space 01 Locate below 1 Mbyte memory address space 10 Locate anywhere in 64 bit memory address space 11 Reserved Note Hardcoded to 0 Prefectchable A value of 1 indicates there are no side effects on reads This bit has no effect on the operation of the PCI 9080 Note Hardcoded to 0 Memory Base Address Memory base address for access to Local Runtime and DMA registers default is 256 bytes Note Hardcoded to 0 Memory Base Address Memory base address for access to Local Runtime and DMA registers A 2 11 PCI Base Address Register for I O Access to Runtime Registers PCI Configuration Offset 0x14 Memory space indicator A value of 0 indicates register maps into Memory space A value of 1 indicates the register maps into I O space Note Hardcoded to 1 Reserved I O Base Address Base Address for I O access to runtime registers Minimum Block Size 128 bytes Note Hardcoded to 0 D8 31 I O Base Address Base Address for I O access to Local Runtime and DMA Registers User Manual for the PCI HPD
6. CREATED ON OCTOBER 16 2001 A 6 13 Outbound Post Head Pointer Register PCI Offset 0xE0 Reserved Outbound Post Head Pointer Local Memory Offset for Outbound Post List FIFO This register is initialized as 2 FIFO Size by the local CPU software D20 31 A 6 14 Outbound Post Tail Pointer Register PCI Offset 0xE4 Reserved Outbound Post Tail Pointer Local Memory Offset for Outbound Post List FIFO This register is initialized as 2 FIFO Size and maintained by the MU hardware and is incremented modulo the FIFO size D20 31 6 15 Queue Status Control Register PCI Offset 0xE8 1 2 O Decode Enable When this bit is set Mailbox registers 0 and 1 are replaced by the Inbound and Outbound Queue Port Registers and redefines Space 1 as PCI Base Address 0 to be accessed by PCIBARO Former Space 1 registers FO F4 and F8 should be programmed to configure their shared I 2 O memory space defined as PCI Base Address 0 Queue Local Space Select When this bit is set to 0 use Local Address Space 0 bus region descriptor for queue accesses When this bit is set to 1 use Local Address Space 1 bus region descriptor for queue accesses Outbound Post List FIFO Prefetch Enable When this bit is set prefetching occurs from the Outbound Post List FIFO if not empty Inbound Free List FIFO Prefetch Enable When this bit is set prefetching occurs from the Inbound Free List FIFO if not empty When this bit is set interrupt is masked I
7. NOTE This register cannot be accessed using the currently released Windows NT Device Driver D19 D0 Rx FIFO Word Count Number of D32 Words currently in the Rx FIFO 2 2 22 INTERRUPT EDGE REGISTER Offset 0x50 RW Thirty two bit register to define interrupt source to individually define as edge or level sensitive Bits are the same order as the interrupt source Default is 0 Level Triggered Interrupts to maintain compatibility with existing devices NOTE This register cannot be accessed using the currently released Windows NT Device Driver Interrupt Edge Select Individual Interrupt level or edge trigger select 0 Level Triggered Interrupts 1 Edge Triggered Interrupts 2 2 23 INTERRUPT HI LO REGISTER Offset 0x54 RW Thirty two bit register to define interrupt source as active hi or active lo Bits are in same order as interrupt source Default is 1 Active High Interrupts to maintain compatibility with existing devices NOTE This register cannot be accessed using the currently released Windows NT Device Driver Interrupt Hi Lo Select Individual Interrupt Hi or Lo active level selection 0 Active Low Interrupt 1 Active Hi Interrupt User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 28 CREATED ON OCTOBER 16 2001 3 1 INITIALIZATION Initializing the PCI HPDI32A ASY
8. Phone 256 880 8787 18 CREATED ON OCTOBER 16 2001 Rx Even Parity Select Writing a 1 to this bit will command the receiver to check the received byte for even parity Writing a 0 to this bit will command the receiver to check the received byte for odd parity Default is 0 odd parit Rx Alternate Register Select Writing a 1 to this bit will enable reading and writing the Receive Clock Divider Register and will disable reading and writing the Receive Input Port Register Writing a 0 to this bit will disable reading and writing the Receive Clock Divider Register and will enable reading the Receive Input Port Register Default is 0 Read the Receive Input Port Register Rx Swap Receiver to Cable Command 1 Writing a 1 causes this board to receive from Cable Command 1 Writing a 0 causes this board to receive from Cable Command 2 Default is 0 receive from Cable Command 2 Rx 8 bit FIFO Writing a 1 causes this board to receive byte for each 032 FIFO Word The other 3 bytes are the word count and a Time Tag Writing a 0 causes this board to receive 4 bytes to form each 032 FIFO word Default is 0 receive 4 bytes to form each D32 FIFO word Rx Invert Cable Polarity Writing a 1 causes this board to invert the data from the cable before it is sent to the receiver Writing a 0 causes this board to receive data with no inversion Default is 0 do not Invert
9. RO e ide INTERRUPT EDGE REGISTER OFFSET OX50 26 INTERRUPT HI LO REGISTER OFFSET 0X54 26 PROGRAMMING 29 THE ON BOARD TRANSMIT anna ta tantae tenen 32 JUMPERS J5 eret eee eee enean CABLE CONNECTOR User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 CREATED ON OCTOBER 16 2001 Appendix PLX REGISTER PROGRAMMING wessssssssssssssssssssssssssssssssssssessssessessesessessssnssnssnsnssnssnsntsstsssnsssssssnssnsesess 35 CONFIGURATION EEPROM eo RE 2 PCI CONFIGURATION REGISTER BIT MAPS A 2 1 PCI CONFIGURATION ID REGISTER PCI CONFIGURATION OFFSET 0 4 2 2 PCI COMMAND REGISTER PCI CONFIGURATION OFFSET 0 04 2 3 PCI STATUS REGISTER PCI CONFIGURATION OFFSET 0 06 M IM 2 4 PCI REVISION ID REGISTER PCI CONFIGURATION OFFSET OXO6 essere nennen 4 2 5 PCI CLASS CODE REGISTER PCI CONFIGURATION OFFSET 0X09 0B mec 2 6 PCI CACHE LINE SIZE REGISTER PCI CONFIGURATION OFFSET 4 2 7 PCI LATENCY T
10. Software Selectable 1 or 2 stop bits Software Selectable Big Little Endian Software Selectable 8 bit Tx Rx FIFO size Software Programmable gap between bytes transmitted Software Programmable Message Length counters Separate Transmit Data and Receive Data Lines Software Selectable ability to Swap Transmit Data and Receive Data Software Selectable ability to connect Transmit Data to Receive Data for self test loop back without requiring an external loop back cable Typical 128K byte Transmit FIFO Typical 128K byte Receive FIFO 32 General Purpose I O Lines A Basic Serial Transfer is shown in Figure 1 2 1 below Figure 1 2 1 Basic Serial Transfer d d dod d d d 200ns 200ns 200ns 200ns 200ns 200ns PC HPDI32A ASYNC board also contains 32 programmable I O Lines that are under software control The lines are driven onto the cable on the Cable Data DO thru Cable Data D31 Lines Tri state control on a byte wide basis is available thru the Board Control Register The PCLHPDI32A ASYNC contains a ASYNC data Transmitter AS YNC data Receiver and 32 programmable I O lines When reset the PC HPDI32A ASYNC will tri state hi z the 32 programmable I O Lines and the Serial Data line out of the board The board will tri state on and drive the 2 lines that indicate if the Transmitter and Receiver are running They control signals are as follows e Transmit Data Line Reset to tri State h
11. The Transmitter is sending the Sync or data bits e Tx Transmit Done The Transmitter is sending a gap or has no data to send The Transmitter operates from an on board clock oscillator for 5 Mega bits per second operation the Transmitter will use a 40 Mhz clock Each bit transmitted will be 8 clock cycles long and with a 40 Mhz clock each bit transmitted will be 200 nsec long High end speeds will always be set by adjusting the clock frequency for the desired bit rate When a transmit is started by the Host processor the Transmitter will begin waiting for data to become available from the Transmit FIFO Once Data is available from the FIFO the transmitter will read the data and begin to send the Start Bit After the Start Bit the Transmitter will shift out the 8 Data Bits If the Parity bit is to be transmitted then the Parity bit will be shifted out after all 8 data bits have been shifted The Transmitter will then always include 1 stop bit following the other data There is a software selectable option to insert 2 stop bits after the final data bit There is also a counter that will insert additional clock cycles after the stop bit s are complete This counter will insert a gap that is X clock cycles wide using the Main Transmitter Clock Typically the Clock would be 40 Mhz 25 nSec So a count of 4 would yield an additional gap if 100 nSec 2 bit cell time Which would be 112 or 2 stop bits If data is available from the FIFO then t
12. User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 24 CREATED ON OCTOBER 16 2001 Cable Command 4 If this bit is enabled as an interrupt 1 will indicate that an interrupt on Cable Command 4 has occurred a 0 will indicate that an interrupt on Cable Co mmand 4 has not occurred If this bit is not enabled as an interrupt 1 will indicate that Cable Command 4 is currently a 1 0 will indicate that Cable Command 4 is not currently a Cable Command 5 Cable Transmitter Driving the Cable If this bit is enabled as an interrupt 1 will indicate that an interrupt on Cable Command 5 has occurred a 0 will indicate that an interrupt on Cable Command 5 has not occurred If this bit is not enabled as an interrupt 1 will indicate that Cable Command 5 is currently a 1 0 will indicate that Cable Command 5 is not currently a Cable Command 6 Cable Receiver Ready to Receive If this bit is enabled as an interrupt 1 will indicate that an interrupt on Cable Command 6 has occurred a 0 will indicate that an interrupt on Cable Command 6 has not occurred If this bit is not enabled as an interrupt 1 will indicate that Cable Command 6 is currently a 1 0 will indicate that Cable Command 6 is not currently a Tx Transmit Done If this bit is enabled as an interrupt a 1 will indicate
13. A 0 value indicates transfers from PCI bus to local bus D4 31 Next Descriptor Address Quad word aligned bits 3 0 20000 User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 61 CREATED ON OCTOBER 16 2001 A 5 11 DMA Command Status Register PCI Offset 0xA8 Channel 0 Enable A 1 value enables the channel to transfer data A 0 value disables the channel from starting a DMA transfer and if in the process of transferring data suspend transfer Pause D1 Channel 0 Start Writing a 1 to this bit causes the channel to start transferring data if the channel is enabled Channel 0 Abort Writing a to this bit causes the channel to abort the current transfer The channel enable bit must be cleared The channel complete bit is set when the abort has completed D3 Clear Interrupt Writing a to this bit clears channel 0 interrupts Channel 0 Done A 1 value indicates this channels transfer is complete A 0 value indicates the channel transfer is not complete 5 12 DMA Channel 1 Command Status Register 0 PCI Offset 0xA8 Channel 1 Enable A value enables the channel to transfer data A 0 value disables the channel from starting a DMA transfer and if in the process of transferring data suspend transfer Pause Di Channel 1 Start Writing a 1 to this bit causes the channel to start transferr
14. D16 31 Assigns a value to the bits which will be used to decode a Local to PCI memory access User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 48 CREATED ON OCTOBER 16 2001 A 3 10 Local Base Address for Direct Master to PCI IO CFG Register PCI Offset 0x24 DO 15 D16 31 Assigns a value to the bits to be used for decoding a Local to PCI I O or configuration access This base address is used for Direct Master I O and configuration accesses A 3 11 PCI Base Address Re map register for Direct Master to PCI Memory PCI Offset 0x28 Direct Memory Access Enable A value of 1 enables decode of Direct Master Memory accesses A value of 0 disables decode of Direct Master Memory accesses Direct Master I O Access Enable A value of lenables decode of Direct Master I O accesses A value of 0 disables decode of Direct Master I O accesses LOCK Input Enable A value enables LOCK input A value of 0 disables the LOCK input Direct Master Red Prefetch Size control 00 PCI 9080 continues to prefetch read data from the PCI bus until Direct Master access is finished This may result in an additional four unneeded Lwords being prefetched from the PCI bus 01 2 Prefetch up to four Lwords from the PCI bus 10 Prefetch up to eight Lwords from the PCI bus 11 Prefetch up to 16 Lwords from the PCI bus If PC
15. ROM A value of 0 specifies Little Endian ordering Big Endian Byte Lane Mode A vlaue of 1 specifies that in Big Endian mode use byte lanes 31 16 for a bit local bus and byte lanes 31 24 for an 8 bit local bus A value of 0 specifies that in Big Endian mode byte lanes 15 0 be used for a 16 bit local bus byte lanes 7 0 for an 8 bit local bus D5 Direct Slave Address Space 1 Big Endian Mode A value of 1 specifies use of Big Endian data ordering for Direct Slave accesses to loal Address Space 1 A value of 0 specifies Little Endian ordering DMA Channel 1 Big Endian Mode A value of 1 specifies use of Big Endian data ordering for DMA Channel 1 accesses to the local Address Space A value of 0 specifies Little Endian ordering DMA Channel 0 Big Endian Mode A value of 1 specifies use of Big Endian data ordering for DMA Channel 0 accesses to the local Address Space A value of 0 specifies Little Endian ordering D8 31 User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 46 CREATED ON OCTOBER 16 2001 A 3 5 Local Expansion ROM Range Register for PCI to Local Bus PCI Offset 0x10 DO 10 Specifies which PCI address bits will be used for decoding a PCI to local bus expansion ROM Each of the bits corresponds to an Address bit Bit 31 corresponds to Address bit 31 Write a value of 1 to all bits to be included i
16. address space 01 locate below 1 Meg in PCI address space 10 locate anywhere in 64 bit PCI address space 11 reserved If mapped into I O space bit 1 must be a 0 Bit 2 is included with bits 3 through 31 to indicate decoding range If mapped into memory space a value of indicates that reads are pre fetchable bit has no effect on the PCI9080 but it is used for system status If mapped into I O space bit is included with bits 31 2 to indicate decoding range If mapped into I O space bit is included with bits 2 through 31 to indicate decoding range Specifies which PCI address bits to use for decoding a PCI access to local bus space 0 Each bit corresponds to a PCI address bit Bit 31 corresponds to Address bit 31 Write a value of 1 to all others used in conjunction with PCI Configuration register 0x18 Default is 1 Meg A 3 2 Local Address Space 0 Local Base Address Re map Register for PCI to Local Bus PCI Offset 0x04 Space 0 Enable A 1 value enables decoding of PCI addresses for Direct Slave access to local space 0 A value of 0 disables Decode If this bit is set to 0 the PCI BIOS may not allocate assign the base address for Space 0 Note Must be set to 1 for any Direct Slave access to Space 0 Di If mapped into I O space bit is included with bits 4 through 31 for re mapping Re map of PCI Address to Local Address Space 0 into a Local Address Space The bits in this register re map replace the PCI Address
17. high User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 55 CREATED ON OCTOBER 16 2001 4 12 Serial EEPROM Control PCI Command Codes User I O Control Init Control Register PCI Offset 0x6C A Fis PC command is sent This PCI command is sent out during DMA read cycles PCI Write Command Code for DMA PM Tier commana s sentou taring D8 11 PCI Memory Read Command Code for Direct Master A Tiere se sent out during PCI Memory Write Command Code for Direct Master This PCI command is sent out during Direct Master write cycles D16 General Purpose Output A value of 1 will cause the USERO output to go high uM A value of 0 will cause the output to go low General Purpose Input A value of 1 indicates that USERI input pin is high A value of 0 indicates that USERI pin is low D Serial EEPROM clock for Local or PCI bus reads or writes to serial EEPROM Toggling this bit generates a serial EEPROM clock Refer to the manufacturer s data sheet for the particular EEPROM being used D Serial EEPROM chip select For Local or PCI bus reads or writes to serial EEPROM Setting this bit to a 1 provides the EEPROM chip select D Write bit to serial EEPROM For writes this output bit is the input to the serial EEPROM It is clocked into the
18. into the Transmit FIFO A read from this offset will read from the Receive FIFO User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 CREATED ON OCTOBER 16 2001 2 2 9 TX STATUS LENGTH REGISTER Offset 0x1C RO The Transmit Status Length Register has been replaced by a counter that will count the number of bytes that were transmitted in the current message Reset to Zero when the transmitter starts Useful for checking if the DMA was interrupted by bus loading D31 D0 Data 0 31 The number of Bytes transmitted in the current message Reset to Zero when the Transmitter Starts 2 2 10 TX ROW VALID LENGTH REGISTER Offset 0x20 RW This register counter controls the number of D8 Bytes transmitted For each byte that is transmitted the counter will be decremented When the Counter reaches Zero the transmitter will halt the current message and any partial D32 Words will be discarded If new data becomes available in the Transmit FIFO the counter will be reset and the transmitter will begin sending the new message This counter can be used to generate message sizes that are not multiples of D32 Words In normal operation this counter would not be used D31 D0 Data 0 31 The number of D8 Bytes to transmit per message 2 2 11 TX ROW INVALID LENGTH REGISTER Offset 0x24 RW This register counter is
19. lower 8 bits of the Rx Row Length Counter Rx Invert Cable Polarity BCR D29 When this bit is set to a 1 the Receiver will invert the incoming data from the cable When this bit is set to a 0 the Receiver will not invert the receive data Default is 0 Rx No Parity Bit BCR D30 This command bit will tell the Receiver that there is no parity bit in the incoming data When this bit is set to a 1 the Receiver will expect to receive only 1 start bit 8 data bits and 1 stop bit When this bit is set to a 0 the Receiver will expect to receive start bit 8 data bits 1 parity bit and 1 stop bit Default is 0 NOTE Do not use this command bit to try to ignore parity errors Incorrect receiver operation will result Rx Row Length Counter This counter will count the number of D8 bytes received in the current message It will be reset to zero ona board reset or every time the Receiver Starts up When in the middle of a message the Row Length Counter will have the Current count of the number of D8 bytes received in this message Rx Status Block Length Counter The Status Block Length counter has been removed from the ASYNC board When the Alternate Register Select bit BCR D26 is a 0 then this has been replaced by a 32 bit register that will allow the Host processor to read the current state of the 32 Cable Data lines The RS 485 Receivers used on the HPDI32A ASYNC project are guaranteed that a Floating Cable
20. searching for an Idle Cable The Receiver will also generate the following status that can be used to generate interrupts Rx Data Error The Receiver has detected a Data Error e Rx Parity Error The Receiver has detected a Parity Error Rx Fifo Big Endian Mode BCR D24 Normally the PCI HPDI32A ASYNC will receive cable bytes and assemble them into a D32 FIFO word with D7 DO being received first D15 D8 being received second D23 D16 being received third and D31 D24 being received fourth When this bit is set then data will be written into the FIFO in Big Endian Motorola style Using Big Endian D31 D24 being received first D23 D16 being received second D15 D8 being received third and D7 D0 being received fourth Default is 0 Rx Even Parity Select BCR D25 When this bit is set to a 1 the Receiver will expect the received byte of data to carry Even Parity When this bit is set to a 0 the Receiver will expect the received byte of data to carry Odd Parity Default is 0 Rx Alternate Register Select BCR D26 When this bit is set to a 1 the host can access the Receiver Clock Division Register thru the address assigned to the Rx Status Length Counter When this bit is set to a 0 reading the RX Status Length Register will allow the Host processor to read the current state of the 32 Cable Data lines Default is 0 User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Rev
21. serial EEPROM by the serial EEPROM clock D Read serial EEPROM data bit For reads this input bit is the output of the serial EEPROM It is clocked out of the serial EEPROM by the serial EEPROM clock D D D Serial EEPROM present A 1 in this bit indicates that an EEPROM is present Reload Configuration Registers When this bit is 0 writing a 1 causes the PCI9080 to reload the local configuration registers from the serial EEPROM PCI Adapter Software Reset A value of written to this bit will hold the local bus logic in the PCI9080 reset and LRESETO asserted The contents of the PCI configuration registers and Shared Run Time registers will not be reset Software Reset can only be cleared from the PCI bus Local bus remains reset until this bit is cleared D0 3 D4 7 17 24 25 26 27 28 29 30 31 D Local Init Status Value of lindicates local init done Responses to PCI accesses will be RETRYs until this bit is set While Input NB is asserted low this bit will be forced to 1 User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 56 CREATED ON OCTOBER 16 2001 4 13 PCI Permanent Configuration ID Register PCI Offset 0x70 D0 15 Permanent Vendor ID Identifies device manufacturer Note Hardcoded to the PCI SIG issued vendor ID of PLX 10B5 D16 31 Permanent Device ID Identifies
22. the data from the cable before it is sent to the receiver Rx No Parity bit Writing a 1 causes this board to receive data with no parity bit Writing a 0 causes this board to receive data with the parity bit Default is 0 Receive data with a parity bit 22 3 BOARD STATUS Offset 0x08 RO The Board Status Register is used to return information to the software about the most current status of the board at the time of the reading Listed below is the information that this register contains Rx Cable Command DO Rx Cable Command D1 Do Rx Cable Command D2 D6 Rx Cable Command D6 D7 Tx Transmit Done A 1 will indicate that a transmit is complete and the transmitter is waiting for the host processor to remove Start Tx or the transmitter is waiting for more data in the Transmit FIFO A 0 will indicate that the transmitter is Stopped or a transmit is in progress User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 19 CREATED ON OCTOBER 16 2001 Tx FIFO Empty L 1 will indicate the Tx FIFO is not empty 0 will indicate the Tx FIFO is empt Tx FIFO Almost Empty L 1 will indicate the Tx FIFO is not almost empty 0 will indicate the Tx FIFO is empty Tx HFO Almost Full L 1 will indicate the Tx FIFO is not almost full 0 will indicate the Tx FIFO is almost full Tx FIFO Ful
23. the particular device Note Hardcoded to the PLX part number for PCI interface chip PCI 9080 A 4 14 PCI Permanent Revision ID Register PCI Offset 0x74 D0 15 Permanent Revision ID Note Hardcoded to the silicon revision of the PCI 9080 User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 57 CREATED ON OCTOBER 16 2001 A 5 LOCAL DMA REGISTERS Table EDMA REGISTERS PCI Offset from base A Value after Reset Register Name ded Cx and Jx modes MA Ch 0 PCI Address MA Ch 0 Local Address MA Ch 0 Transfer Byte Count MA Ch 0 Descriptor Pointer MA Ch 1 Mode 0x00000003 Cx and Jx modes MA Ch 1 PCI Address MA Ch 1 Local Address MA Ch 1 Transfer Byte Count MA Ch 1 Descriptor Pointer 1 Reserved DMA Ch Command Status Register DMA Ch 0 0x00000010 ep Command Status D32 ye ode Arbitration Register 0x00000000 D32 ye j DMA Threshold Register 0x00000000 ep A 5 1 DMA Channel 0 Mode Register PCI Offset 0x80 95 WIN N J m 3 ddr 0x90 PE 95 gjg NJN lt 2 o o o o ajajaja m yes lt g 3 gg Oo m NIN N lo 5 RIM RIM RIM RIM Nn lt 5 Dn m 91819 S S wo wio w Local DMA Bus Width A value of 00 indicates a DMA bus w
24. the transmit clock while in test mode The oscillator is factory installed at 4OMHz This oscillator can be changed in the field by the end user The maximum frequency supported by this clock is 40Mhz Figure 4 1 1Oscillator Pinout User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 32 CREATED ON OCTOBER 16 2001 42 JUMPERS J5 J5 is a header consisting of four individual jumpers Figure 42 1 Jumper J5 7 1 514944 8 2 J5 1 to JS 2 EEPROM Configuration This jumper connects the PNP EEPROM to the PCI chipset for power up configuration This jumper is intended for factory use only and should always be installed Se o a OE J5 3 to JS 4 FPGA Reload This jumper connects the FPGA Reload to the local PCI Reset When this jumper is installed the FPGA will reload when the PCI is reset If the jumper is off the FPGA will reload only at power up This jumper is intended for factory use only and should always be installed J5 5 to JS 6 Board Jumper 0 This jumper is Readable thru the Board Status Register and can be used to identify a particular board if multiple boards are installed in a system J5 7 to J5 8 Board Jumper 1 This jumper is Readable thru the Board Status Register and can be used to identify a particular board if multiple boards are installed in a system User Manual f
25. transfer is in response to the DREQ input The DMA controller transfers Lwords 32bits of data This may result in multiple transfers for an 8 or 16 bit bus D13 Write and Invalidate mode for DMA transfers ul When set to 1 PCI 9080 performs Write and Invalidate cycles to the PCI bus PCI 9080 supports Write and Invalidate sizes of 8 or 16 Lwords The size is specified in the PCI Cache Line Size Register If a size other than 8 or 16 is specified PCI 9080 performs write transfers rather than Write and Invalidate transfers Transfers must start and end at the Cache Line Boundaries DMA EOT End Of Transfer Enable A Value of 1 enables input pin A Value of 0 disables EOT input pin D15 DMA Stop Data Transfer Mode ul A Value of 0 sends a BLAST to terminate DMA transfer A Value of 1 indicates an EOT asserted or DREQ negated during demand mode DMA terminates the DMA transfer D16 DMA Clear Count Mode ull When set to 1 the byte count in each chaining descriptor if it is in local memory is cleared when the corresponding DMA transfer is complete Note f chaining descriptor is in PCI memory the count is not cleared DMA Channel 0 Interrupt Select A Value of 1 routes the DMA Channel 0 interrupt to the PCI interrupt A Value of 0 routes the DMA Channel 0 interrupt to the local bus interrupt 5 2 DMA Channel 0 PCI Address Register PCI Offset 0x84 D0 31 PCI Address Register This indicates where in the PCI memory space the DMA tran
26. with bits 31 2 to indicate decoding range Specifies which PCI address bits to use for decoding a PCI access to local bus space 1 Each of the bits corresponds to a PCI address bit Bit 31 corresponds to Address bit 31 Write a value of 1 to all bits that must be included in decode and a 0 to all others Used in conjunction with PCI Configuration Register Default is 1 MB User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 50 CREATED ON OCTOBER 16 2001 A 3 14 Local Address Space 1 Local Base Address Remap Register PCI Offset 0 4 Space 1 Enable A value of 1 enables decoding of PCI addresses for Direct Slave access to local space 1 A value of 0 disables decoding If this bit is set to 0 the PCI BIOS may not allocate assign the base address for Space 1 Note Must be set to 1 for any Direct Slave access to Space 1 If local space 1 is mapped into memory space bits are not used If mapped I O space bit is included with bits 31 4 for remapping Remap of PCI Address to Local Address space 1 into a Local Address Space The bits in this register remap replace the PCI Address bits used in decode as the Local Address bits A 3 15 Local Address Space 1 Bus Region Descriptor Register PCI Offset 0xF8 D0 1 Memory Space 1 Local Bus Width ili A value of 00 indicates bus width of 8 bits A valu
27. Almost Empty 1 will allow an interrupt on Tx FIFO almost empty 0 will disallow an interrupt on Tx FIFO almost empty Enable Interrupt on Tx FIFO Almost Full 1 will allow an interrupt on Tx FIFO almost full 0 will disallow an interrupt on Tx FIFO almost full Enable Interrupt on TxFIFO Full 1 will allow an interrupt on Tx FIFO full 0 will disallow an interrupt on Tx FIFO full Enable Interrupt on Rx FIFO NOT Empty 1 will allow an interrupt on Rx FIFO NOT empty 0 will disallow an interrupt on Rx FIFO NOT empty Enable Interrupt on Rx FIFO NOT Almost Empty 1 will allow an interrupt on Rx FIFO NOT Almost empty 0 will disallow an interrupt on Rx FIFO NOT Almost empty Enable Interrupt on Rx FIFO Almost Full 1 will allow an interrupt on Rx FIFO almost full 0 will disallow an interrupt on Rx FIFO almost full Enable Interrupt on Rx FIFO Full 1 will allow an interrupt on Rx FIFO full 0 will disallow an interrupt on Rx FIFO full Enable Interrupt on Rx FIFO Underflow 1 will allow an interrupt on Rx FIFO Underflow 0 will disallow an interrupt on Rx FIFO Underflow User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 23 CREATED ON OCTOBER 16 2001 Enable Interrupt on Rx FIFO Overflow 1 will allow an interrupt on Rx FIFO Overflow 0 will disallow an interrupt on Rx FIFO Overflow Enable Interr
28. CREATED ON OCTOBER 16 2001 PCI HPDI32 ASYNC PMC HPDI32 ASYNC cPCI HPDI32 ASYNC PC104P HPDI32 ASYNC User Manual Preliminary General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 Fax 256 880 8788 URL WWW generalstandards com E mail Support generalstandards com User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 CREATED ON OCTOBER 16 2001 User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 CREATED ON OCTOBER 16 2001 PREFACE General Standards Corporation Preliminary Revised July 20 2000 Copyright C 2000 General Standards Corp Additional copies of this manual or other literature may be obtained from General Standards Corporation 8302A Whitesburg Dr Huntsville Alabama 35802 Tele 256 880 8787 FAX 256 880 8788 E mail support generalstandards com The information in this document is subject to change without notice General Standards Corp makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Although extensive editing and reviews are performed before release to ECO control General Stand
29. D ON OCTOBER 16 2001 Re map of Local to PCI space into a PCI address space The bits in this register re map replace the Local address bits used in decode as the PCI address bits This PCI Remap address is used for Direct Master memory and I O accesses A 3 12 PCI Configuration Address Register for Direct Master to PCI IO CFG PCI Offset 0x2C Configuration Type 00 2 Type 0 012 Type 1 D2 7 Register Number If different register read write is needed this register value must be programmed and a new PCI configuration cycle must be generated Configuration Enable A value of 1 allows Local to PCI I O accesses to be converted to a PCI configuration cycle The parameters in this table are used to generate the PCI configuration address Memory Space Indicator A value of 0 indicates Local Address Space 1 maps into PCI memory space A value of 1 indicates Local Address Space maps into PCI I O space Encoded for Memory Space If mapped into memory space encoding is as follows 00 Locate anywhere in 32 bit PCI address space 01 Locate below 1 MB in PCI address space 10 Locate anywhere in 64 bit PCI address space 11 Reserved If mapped into I O space bit 1 must be set to 0 Bit 2 is included with bits 31 3 to indicate decoding range If mapped into memory space a value of indicates reads are prefetchable bit has no effect on the operation of the PCI 9080 but is for system status If mapped into I O space bit is included
30. E Offset 0x44 RO Upon Power up or any time FPGA code is reloaded the logic will fill Rx FIFO and count the number of writes until the FIFO is full This value is saved as the FIFO size and the FIFOs are reset The Counter is only 20 bits wide the upper 12 bits are undefined NOTE This register cannot be accessed using the currently released Windows NT Device Driver 19 FIFO Size Number of D32 Words that the Rx FIFO Holds D31 D20 Undefined User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 27 CREATED ON OCTOBER 16 2001 2 2 20 TX FIFO WORD COUNT Offset 0x48 RO This counter tracks the number of D32 Words in the Tx FIFO Every time a word is written to the FIFO the count is incremented When a D32 Word is read the count is decremented The Counter is only 20 bits wide the upper 12 bits are undefined NOTE This register cannot be accessed using the currently released Windows NT Device Driver D19 D0 Tx FIFO Word Count Number of D32 Words currently in the Tx FIFO D31 D20 Undefined 2 2 21 RX FIFO WORD COUNT Offset 0x4C RO This counter tracks the number of D32 Words in the Rx FIFO Every time a word is written to the FIFO the count is incremented When a D32 Word is read the count is decremented The Counter is only 20 bits wide the upper 12 bits are undefined
31. General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 36 CREATED ON OCTOBER 16 2001 2 2 PCI Command Register PCI Configuration Offset 0x04 I O Space A value of 1 allows the device to respond to I O space accesses A value of 0 disables the device from responding to I O space accesses Memory Space A value of 1 allows the device to respond to memory space accesses A value of 0 disables the device from responding to memory space accesses Master Enable Controls a device s ability to act as a master on the PCI bus A value of 1 allows the device to behave as a bus master A value of 0 disables the device from generating bus master accesses This bit must be set for the PCI 9080 to perform Direct Master or DMA cycles Memory Write Invalidate A value of 1 enables memory write invalidate A value of 0 disables memory write invalidate Parity Error Response A value of 0 indicates that a parity error is ignored and operation continues A value of 1 indicates that parity checking is enabled Wait Cycle Control Controls whether the device does address data stepping A 0 value indicates the device never does stepping A value of 1 indicates that the device always does stepping Note Hardcoded to 0 SERR Enable A value of 1 enables the SERR driver A value of 0 disables the driver Fast Back to Back Enable Indicates what type of fast back to back transfers a Master can perf
32. I memory prefetch is not wanted performs a Direct Master single cycle The direct master burst reads must not exceed the programmed limit Direct Master PCI read mode A value of 0 indicates that the PCI9080 should release the PCI bus when the read FIFO becomes full A value of 1 indicates that the PCI9080 should keep the PCI bus and de assert IRDY when the read FIFO becomes full Programmable Almost Full flag When the number of entries in the 32 word direct master write FIFO exceed this value the output pin DMPAF is asserted low Write and Invalidate Mode When set to 1 PCI 9080 waits for 8 or 16 Lwords to be written from the local bus before starting PCI accesses When set all local Direct Master to PCI write accesses must be 8 or 16 Lwords bursts Use in conjunction with PCI 0x04 If set to 1 don t prefetch past 4K 4098 bytes boundaries I O Remap Select When set tol forces PCI address bits 31 16 to all zeros When set to 0 uses bits 31 16 of this register as PCI address bits 31 16 Direct Master Write Delay This register is used to delay the PCI bus request after direct master burst write cycle has started Values 00 delay start the cycle immediately 01 Delay 4 PCI clocks 10 Delay 8 PCI clocks 11 Delay 16 PCI clocks User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 49 CREATE
33. I32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 40 CREATED ON OCTOBER 16 2001 A 2 12 PCI Base Address Register for Memory Access to Local Address Space 0 PCI Configuration Offset 0x18 Memory space indicator A value of 0 indicates register maps into Memory space A value of 1 indicates the register maps into I O space Specified in Local Address Space 0 Range Register Location of register if memory space Location values 00 Locate anywhere in 32 bit memory address space 01 Locate below 1 Mbyte memory address space 10 Locate anywhere in 64 bit memory address space 11 Reserved Specified in Local Address Space 0 Range Register Prefetchable if memory space A value of indicates there are no side effects on reads This bit reflects the value of bit 3 in the LASORR register and provides only status to the system This bit has no effect on the operation of the PCI 9080 Prefetching features of this address s pace are controlled by the associated Bus Region Descriptor Register Specified in LASORR register If I O Space bit 3 is included in the base address Memory Base Address Memory base address for access to Local Address Space 0 A 2 13 PCI Base Address Register for Memory Access to Local Address Space 1 PCI Configuration Offset 0x1C Memory space indicator A value of 0 indicates register maps into Me
34. IFO becomes full during a Direct Slave read Direct slave LLOCKo Enable A value of 1 enables PCI Direct Slave locked sequences A value of 0 disables Direct Slave locked sequences PCI Request Mode A value of 1 causes PCI9080 to negate REQ when it asserts FRAME during a master cycle A value of 0 causes PCI 9080 to leave REQ asserted for the entire bus master cycle PCI Rev 2 1 Mode When set to 1 PCI 9080 operates in Delayed Transaction mode for Direct Slave Reads PCI 9080 issues a RETRY and prefetches the read data PCI Read No Write Mode A value of 1 forces a retry on writes if read is pending A value of 0 allows writes to occur while read is pending PCI Read with Write Flush Mode A value of 1 submits a request to flush a pending read cycle if a write cycle is detected A value of 0 submits a request to not effect pending reads when a write cycle occurs PCI v2 1 compatible Gate the Local Bus Latency Timer with BREQ If this bit is set to 0 PCI 9080 gives up the local bus during Direct Slave or DMA transfer after the current cycle if enabled and BREQ is sampled If this bitis set to 1 PCI 9080 gives up the local bus only if BREQ is sampled and the Local Bus Latency Timer is enabled and expires during Direct Slave or DMA transfer PCI Read No Flush Mode A value of 1 submits request to not flush the read FIFO if PCI read cycle completes Read Ahead mode A value of 0 submits request to flush read FIFO if PCI read cy
35. IMER REGISTER PCI CONFIGURATION OFFSET OXOD 4 2 8 PCI HEADER TYPE REGISTER PCI CONFIGURATION OFFSET OXQOE esee eene 4 2 9 PCI BUILT IN SELF TEST BIST REGISTER PCI CONFIGURATION OFFSET OXOF 2 10 PCI BASE ADDRESS REGISTER FOR MEMORY ACCESS TO RUNTIME REGISTERS PCI CONFIGURATION OFFSET 0x010 40 2 11 PCI BASE ADDRESS REGISTER FOR I O ACCESS TO RUNTIME REGISTERS PCI CONFIGURATION OFFSET 0x14 40 A 2 12 PCI BASE ADDRESS REGISTER FOR MEMORY ACCESS TO LOCAL ADDRESS SPACE 0 PCI CONFIGURATION OFFSET oie ml me M Su Md It EE EEEN Tto Af LEES ae M 41 4 2 13 PCI BASE ADDRESS REGISTER FOR MEMORY ACCESS TO LOCAL ADDRESS SPACE 1 PCI CONFIGURATION D de EXC San cet a A te ol hich eens leh A 2 14 PCI BASE ADDRESS REGISTER PCI CONFIGURATION OFFSET 0X20 4 2 15 PCI BASE ADDRESS REGISTER PCI CONFIGURATION OFFSET 0x24 2 16 PCI CARDBUS CIS POINTER REGISTER PCI CONFIGURATION OFFSET 0X28 4 2 17 PCI SUBSYSTEM VENDOR ID REGISTER PCI CONFIGURATION OFFSET O0X2O essere 4 2 18 PCI SUBSYSTEM ID REGISTER PCI CONFIGURATION OFFSET 2 4 2 19 PCI EXPANSION ROM BASE REGISTER PCI CONFIGURATION OFFSET 0 30 4 2 20 PCI INTERRUPT LINE REGISTER PCI CONFIGURATION OFFSET O0X3C 4 2 21 PCI INTERRUPT PIN REGISTER PCI CONFIGURATION esses eere 4 2 22 PCI MIN REGISTER PCI CO
36. NC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 35 CREATED ON OCTOBER 16 2001 The configuration registers are usually programmed by the system BIOS during system startup Table B Pci Configuration Register Mapping PCI Access CFG Value after register Size Register Name Reset address D32 yes Ep pp endor ID 0x9080 0x00 Ox10B5 eel 0x00010000 Class Code Revision ID 0x07800003 D32 yes Yes BIST Header Type Latency Timer Cache Line 0x00000000 0x0C 15 0 Size Runtime Registers Configuration Registers 32 yes No Reserved 0x00000000 0x34 D32_ yes Reserved 0 00000000 0x38 Max lat Min GnU lInterrupt Pin Interrupt Line 0x00010000 7 0 registers may be written to or read from in byte word Lword accesses A 2 1 PCI Configuration ID Register PCI Configuration Offset 0x00 Vendor ID Identifies the manufacturer of the device Defaults to the PCI SIG issued vendor ID of PLX 0x10B5 if no serial EEPROM is present and pin NB no local bus initialization is asserted low Device ID Identifies the particular device Defaults to the PLX part number for PCI interface chip 0x9080 if no serial EEPROM is present and pin NB no local bus initialization is asserted low User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR
37. NC Card will generally need to be done only once by the software unless the mode needs to change The software is responsible for tracking any changes for making all changes necessary to meet the needs of the application and for making all the adjustments when requirements change Most of the configuration status can be determined by reading the Board Control Register Upon system reset and also after a board reset is performed the board will be in a state where the following initialization will apply 1 all cable data transceivers will be in their default state Tri state off 2 allinterrupts will be disabled 3 the FIFOs will be empty 4 thereceive logic will be disabled 5 the transmit logic will be dis abled 6 the board will be driving Cable Command 5 and Cable Command 6 7 the board will be driving Cable Command 1 default transmit data line 8 all RW registers will be set to 0 Board Control Register bits are set to 0 on system reset 32 RESETS There are three 3 bits on this board that are used as resets to the local side three bits are located in the Board Control Register These bits perform a reset when the software writes a 1 to them After writing a 1 the software does not need to return to clear the bits the bits operate as self timed pulse that will return to 0 after they have been asserted long enough to perform the reset s For further details on the resets refer to the Regis
38. NFIGURATION OFFSET 4 2 23 PCI MAX LAT REGISTER PCI CONFIGURATION OFFSET OX3F A3 LOCAL CONFIGURATION REGISTERS occsscssssssssssssssssssssssssssssssssssssssessesssssssssnssnssnsssssssess 3 1 LOCAL ADDRESS SPACE 0 RANGE REGISTER FOR PCI TO LOCAL BUS PCI OFFSET 0X00 4 3 2 LOCAL ADDRESS SPACE 0 LOCAL BASE ADDRESS RE MAP REGISTER FOR PCI TO LOCAL BUS PCI OFFSET 0 04 44 3 3 MODE ARBITRATION REGISTER PCI OFFSET 0 08 45 4 3 4 BIG LITTLE ENDIAN DESCRIPTOR REGISTER PCI OFFSET OXOC essent enne nnne nnns 46 4 3 5 LOCAL EXPANSION ROM RANGE REGISTER FOR PCI TO LOCAL BUS PCI OFFSET OXIO sess 47 3 6 LOCAL EXPANSION ROM LOCAL BASE ADDRESS RE MAP REGISTER FOR PCI TO LOCAL BUS AND BREQO CONIROL PCI OERESET OX14 ICE I ea ie ds 47 4 3 7 LOCAL ADDRESS SPACE 0 EXPANSION ROM BUS REGION DESCRIPTOR REGISTER PCI OFFSET OX1 8 47 3 8 LOCAL RANGE REGISTER FOR DIRECT MASTER TO PCI PCI OFFSET OX1QO essere 4 3 9 LOCAL BUS BASE ADDRESS REGISTER FOR DIRECT MASTER TO PCI MEMORY PCI OFFSET 0 20 4 3 10 LOCAL BASE ADDRESS FOR DIRECT MASTER TO PCI IO CFG REGISTER PCI OFFSET 24 A 3 11 PCI BASE ADDRESS RE MAP REGISTER FOR DIRECT MASTER TO PCI MEMORY PCI OFFSET 0x28 49 3 12 PCI CONFIGURATION ADDRESS REGISTER FOR DIRECT MASTER TO PCI IO CFG PCI OFFSET 2 50 4 3 13 LOCAL ADDRESS
39. Offset PCI CFG from Register base Value after Reset Address Addr Size Register Name 0x70 D32 Device ID Vendor ID 0x9080 0x00 Ox10B5 007800003 000010000 Oc 000000000 OTe 0x00000000 0x00 OxFFFFFEOO 0x04 xo0000001 0x08 0 0000 Not Used 0x0C Big little Endian descriptor 0x0000 Le 0x10 0 0000 Not Use 0 14 0 0000 Not Used Bus region descriptors for PCI to Local Address Space 0 0x42000143 0 0000 Used NotUsed Local Base Address for direct Master to PCI IO CFG Not U NotUsed 0x2C D32 PCI Configuration Address Register for direct Master to 0x0000 Not Used PCI IO CFG Ox10B5 Ox0000 Nor Usa 0x0000 Not Used 0x0000 Not Used 2 PCI Base Address for Local Expansion ROM 0x0000 Not Used A 2 PCI CONFIGURATION REGISTER BIT MAPS n x x olojo gt lt gt lt gt S olo Z ja 1 0 104 ajajaja The PC HPDI32 CDC Card complies with the plug n play concept That is at the time of power up an attempt will be made by the CPU to set up the board to meet the configuration requirements of the system In doing this the CPU will map the amount of I O space requested by the PCI HPDI32 CDC Card and return the configuration base address into the PCI Configuration Register Offset 0x18 of this Board User Manual for the PCI HPDI32A ASY
40. On boards with 2 DMA channel capability this bit will enable use of both DMA channels Not supported at this time This bit must ALWAYS be set to 0 for proper board operation Reserved S Tx Data Port Output Enable D7 DO A I will enable the board to Drive Cable Data D7 DO A 0 will prevent the board from driving Cable Data 07 00 Default to 0 D13 Tx Data Port Output Enable D15 D8 A 47 will enable the board to Drive Cable Data D15 D8 A 0 will prevent the board from driving Cable Data D15 D8 Default to 0 Tx Data Port Output Enable D23 D16 A 1 will enable the board to Drive Cable Data D23 D16 A 0 will prevent the board from driving Cable Data D23 D16 Default to 0 Tx Data Port Output Enable D31 D24 A 417 will enable the board to Drive Cable Data D31 D24 A 0 will prevent the board from driving Cable Data D31 D24 Default to 0 Tx Big Endian Mode Writing a 1 to this bit will enable transmitting in Big Endian Mode Writing a 0 to this bit will enable transmitting in Little Endian Mode Default is 0 Little Endian Mode Tx Even Parity Writing a 1 to this bit will enable the transmitter to generate and send Even parity with each byte Writing a 0 to this bit will enable the transmitter to generate and send Odd parity with each byte Default is 0 Odd Parity Tx 2 Stop Bits Writing a 1 to this bit Place 2 stop bits on the end of each byte
41. PU will map the amount of I O space requested by the PCI HPDI32A ASYNC Card and return the configuration base address into the PCI Configuration Register Offset 0x18 of this Board PCI bus interface functions are handled by the PLX9080 3 PCI bus interface For more information regarding the PCI bus interface please refer to Appendix A PLX Register Programming User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 15 CREATED ON OCTOBER 16 2001 22 PCI HPDI32A ASYNC LOCAL REGISTERS BIT DESCRIPTIONS The PC HPDI32A AS YNC board contains the following registers Figure 2 2 1 Register Map Value Access Register Name after Reset 0x000F0200 Board Control 0x00000000 Offset 32 D32 D32 D32 16 m 0x0000CCXX Tx Programmable Almost 0x01000008 Rx Programmable Almost 0x01000008 gJ m it NIN AX 95 5 Tx Output Data Port Register 0x00000000 gt z Rx FIFO Word Count Removed WwW Interrupt Hi Lo Level Select RO read only RW read write capability RC read clear a write clears the specified bits 95 N m T NIN N z o zz gt gt o N m NIN User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation
42. RFACE FEROS pcc RUE REGISTERS r 15 PCFHPDI32A ASYNC REGISTER INFORMATION 15 PCFHPDI32A ASYNC LOCAL REGISTERS BIT DESCRIPTIONS reete tenens stets 16 FIRMWARE REVISION OFFSET 0X00 RO BOARD CONTROL OFFSET 0 04 RW sd ves BOARD STATUS OFFSET OX0S RO TX ALMOST OFFSET OXOC RW iret reete eerte ted e d dete DR Ee a veteres RX ALMOST OFFSETOXIO FIRMWARE FEATURES OFFSET 0X14 RW TX OUTPUT DATA PORT REGISTER OFFSET 0 14 RW Ses FIFO TO OFESEDOXIG RW ir tete P phe tbe ener ehe Rete er senses TX STATUS LENGTH REGISTER OFFSETOXIC TX ROW VALID LENGTH REGISTER OFFSET 0X20 RW Seve TX ROW INVALID LENGTH REGISTER OFFSET 0X24 22 RX STATUS BLOCK LENGTH COUNTER OFFSET 0X28 22 RX ROW LENGTH COUNTER OFFSETOX2C RO he INTERRUPT CONTROL OFFSET OX30 RW aae a ae sar aa taS CEEA eE AR asea EE REE INTERRUPT STATUS OFFSET 0X34 TX CLOCK DIVIDER OFFSET 0X38 RW RESERVED OFFSET OX3C TX FIFO SIZE OFFSET 0X40 m PM RX FIFO SIZE OFFSETOX44 RO eee Rete e HU ER RE Ren TX FIFO WORD COUNT OFFSETOX4S RX FIFO WORD COUNT OFFSET
43. Received Target Abort When set to a 1 this bit indicates the PCI9080 has signaled a target abort Writing a 1 to this bit clears the bit 0 Master Abort When set to a 1 this bit indicates the PCI9080 has generated a master abort signal Writing a 1 to this bit clears the bit 0 Signal System Error When set to a 1 this bit indicates the PCI9080 has reported a system error on the SERR signal Writing a 1 to this bit clears the bit 0 Detected Parity Error When set to a 1 this bit indicates the PCI9080 has detected a PCI bus parity error even if parity error handling is disabled the Parity Error Response bit in the Command Register is clear One of three conditions can cause this bit to be set 1 the PCI9080 detected a parity error during a PCI address phase 2 the PCI9080 detected a data parity error when it was the target of a write 3 the PCI9080 detected a data parity error when performing a master read operation Writing a 1 to this bit clears the bit 0 A 2 4 PCI Revision ID Register PCI Configuration Offset 0x08 0 7 User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 38 CREATED ON OCTOBER 16 2001 A 2 5 PCI Class Code Register PCI Configuration Offset 0x09 0B Register level programming interface 0x00 Queue Ports at 0x40 and 0x44 0x01 Queue Ports at 0x40 and 0x44 and Int Stat
44. SPACE 1 RANGE REGISTER FOR PCI TO LOCAL BUS PCI OFFSET OXFO 4 3 14 LOCAL ADDRESS SPACE 1 LOCAL BASE ADDRESS REMAP REGISTER PCI OFFSET OXF4 3 15 LOCAL ADDRESS SPACE 1 BUS REGION DESCRIPTOR REGISTER PCI OFFSET OXF8 AA RUNTIME REGISTERS cssssssssssssssssssssssssssssssscssosssssossossssoescessssssssesssscescssesseseeseesesseneenees 4 1 MAILBOX REGISTER 0 PCI OFFSET 0x40 eer saa ee Ede x dae a egeo vore betae eee tacente ee eee ced 4 4 2 MAILBOX REGISTER 1 PCI OFFSET 0x44 re does Cre xe Er ERE e de sues 4 4 3 MAILBOX REGISTER 2 PCI OFFSET 0x48 4 4 4 MAILBOX REGISTER 3 PCI OFFSET 0 4 i A 4 5 MAILBOX REGISTER 4 PCI OFFSET 0X50 A 4 6 MAILBOX REGISTER 5 PCI OFFSET 0x54 aee Rb EE RARE aves see s EE RAN TE xou 4 7 MAILBOX REGISTER 6 nno aane ie TOU c arae A 4 6 MAILBOX REGISTER 7 PCI OFFSET 0X3Q wsscsssssessesscsscescessessesseseesecseesecsscescesesseesesaesaeessesececeeseasessessessesecseeseeeeneees User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 CREATED ON OCTOBER 16 2001 A 4 9 PCI TO LOCAL DOORBELL REGISTER DESCRIPTION PCI OFFSET 0X60 etetene 53 A 4 10 LOCAL TO PCI DOORBELL REGISTER DESCRIPTION PCI OFFSET OX64 e
45. SYNC Data Lines rising edge Enable Interrupt on Cable Command 1 Data Falling Edge 1 will allow an interrupt on Cable ASYNC Data Falling Edge 0 will disallow an interrupt on Cable ASYNC Data Falling Edge Enable Interrupt on Cable Command 1 Data a logic 1 1 will allow an interrupt on Cable ASYNC Data a logic 1 0 will disallow an interrupt Cable ASYNC Data a logic 1 Enable Interrupt on Cable Command 2 a logic 1 1 will allo w an interrupt on Cable Command 2 a logic 1 0 will disallow an interrupt Cable Command 2 a logic 1 Enable Interrupt on Cable Command 4 a logic 1 1 will allow an interrupt on Cable Command 4 logic 1 will disallow an interrupt Cable Command 4 a logic 17 Enable Interrupt Cable Command 5 a logic 1 Cable Transmitter Driving the Cable 1 will allow an interrupt on Cable Command 5 a logic 1 0 will disallow an interrupt Cable Command 5 a logic 1 Enable Interrupt on Cable Command 6 a logic 1 Cable Receiver Ready to Receive 1 will allow an interrupt on Cable Command 6 a logic 1 will disallow an interrupt Cable Command 6 a logic 1 Enable Interrupt on Tx Transmit Done 1 will allow an interrupt on Tx Transmit Done 0 will disallow an interrupt on Tx Transmit Done Enable Interrupt Tx FIFO Empty 1 will allow an interrupt on Tx FIFO empty 0 will disallow an interrupt on Tx FIFO empty Enable Interrupt on TxFIFO
46. Size Outbound Trail Pointer If FIFO is empty a value of FFFFFFFh is returned A PCI interrupt is generated if Outbound Post List FIFO is not empty A 6 5 Messaging Queue Configuration Register PCI Offset 0xC0 Queue Enable Value of 1 allows accesses to the Inbound and Outbound Queue ports If cleared to 0 writes are accepted but ignored and reads return FFFFFFFF pointer initialization and frame allocation should be completed before enabling this bit 1 5 Circular FIFO Size Defines the size of one of the circular FIFOs Each of the four FIFOs are the same size Each FIFO entry is one 32 bit word FIFO Size Encoding emo se 5 1 per FIFO Size Memo D6 31 Reserved A 6 6 Queue Base Address Register PCI Offset 0xC4 D20 31 Queue Base Address Local Memory base address of the Inbound and Outbound Queues four contiguous and equal size FIFOs Queue base address must be aligned on a 1 MB boundary A 6 7 Inbound Free Head Pointer Register PCI Offset 0xC8 D0 1 User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 CREATED ON OCTOBER 16 2001 Inbound Free Head Pointer Local memory Offset for Inbound Free List FIFO This register is initialized as 0 FIFO Size and maintained by the local CPU software A 6 8 Inbound Free Head Tail Register PCI Offset 0xCC Inbound F
47. Standard for the RS 422A Interface EIA order number EIA RS 422A PCI Local Bus Specification Revision 2 1 June 1 1995 Questions regarding the PCI specification be forwarded to PCI Special Interest Group P O Box 14070 Portland OR 97214 800 433 5177 U S 503 797 4207 International 503 234 6762 FAX User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 CREATED ON OCTOBER 16 2001 PCI HPDI32A ASYNC Documentation History 1 October 16 2001 Initial Release User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 CREATED ON OCTOBER 16 2001 Table of Contents 11 1 2 1 1 2 2 1 4 2 1 2 2 2 2 1 2 2 2 2 2 3 2 2 4 2 2 5 2 2 6 2257 2 2 8 2 2 9 2 2 10 2 2 11 2 2 12 2 2 13 2 2 14 2 2 15 2 2 16 2 2 17 2 2 18 2 2 19 2 2 20 2 2 21 2 2 22 222 29 3 1 3 2 33 3 4 4 1 43 INTRODUCTION 5 FUNCTIONAL DESCRIPTION 5 THEORY OF 6 TRANSMIITER OPERATION 2 iet o RE ERR OT RH ERRAT EUN DENTES HIR 7 RECEIVER OPERATION CABLE INTE
48. al interrupt enable Clearing the DMA status bits also clears the interrupt Value of 1 indicates local doorbell interrupt is active Value of 1 indicates Ch 0 interrupt is active Value of 1 indicates Ch 1 interrupt is active Di D2 D4 7 D10 D11 D12 User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 54 CREATED ON OCTOBER 16 2001 Value of 1 indicates BIST interrupt is active BIST Built In Self Test interrupt is generated by writing 1 to bit 6 of the PCI Configuration BIST gister Clearing bit 6 clears the interrupt Refer to the BIST Register for a description of self test pe none e e E E until abort c occurs Hi until abort occurs D26 Value of 0 indicates a DMA CH 1 was the bus master during a master or Target abort Not valid pe dicun eee D27 Value of 0 indicates a Target Abort was generated by the PCI 9080 after 256 consecutive Master P esta Target NS Value of 1 41005 PCI wrote data to the Mailbox 0 Enabled only if MBOXINTENB is enabled bit 3 high Value of 1 indicates PCI wrote data to the Mailbox 1 Enabled only if MBOXINTENB is enabled PP cay Value of 1 indicates PCI wrote data to the Mailbox 2 Enabled only if MBOXINTENB is enabled Value of 1 indicates PCI wrote data to the Mailbox 3 Enabled only if MBOXINTENB is enabled bit 3
49. ar a doorbell bit by writing a 1 to that bit position 4 10 Local to PCI Doorbell Register Description PCI Offset 0x64 Doorbell register The local processor can write to this register and it will generate a PCI interrupt A PCI master can then read this register to determine which doorbell bit was asserted The local processor sets a doorbell by writing a 1 to a particular bit The PCI master can clear a doorbell bit by writing a 1 to that bit position User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 53 CREATED ON OCTOBER 16 2001 4 11 Interrupt Control Status PCI Offset 0x68 Enable Local Bus LSERR A value of 1 enables PCI 9080 to assert LSERR interrupt output when PCI bus Target Abort or Master Abort status bit is set in the PCI Status configuration register Enable Local Bus SERR when PCI parity error occurs during PCI 9080 Master Transfer or PCI p Generate PCI Bus SERR When this bit is set to 0 writing a 1 generates a PCI bus SERR D3 Mailbox Interrupt Enable A value of 1 enables a Local Interrupt to be generated when the PCI bus writes to Mailbox register 0 3 To clear the Local Interrupt the Local master must read the Mailbox Used in conjunction with Local interrupt enable PCI Interrupt Enable A value of 1 enables PCI interrupts D4 7 PCI Doo
50. ards Corp assumes no responsibility for any errors that may exist in this document No commitment is made to update or keep current the information contained in this document General Standards Corp does not assume any liability arising out of the application or use of any product or circuit described herein nor is any license conveyed under any patent rights or any rights of others General Standards Corp assumes no responsibility for any consequences resulting from omissions or errors in this manual or from the use of information contained herein General Standards Corp reserves the right to make any changes without notice to this product to improve reliability performance function or design rights reserved No part of this document may be copied or reproduced in any form or by any means without prior written consent of General Standards Corp This user s manual provides information on the specifications theory of operation register level programming installation of the board and information required for customized hardware software development User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 CREATED ON OCTOBER 16 2001 RELATED PUBLICATIONS The following manuals and specifications provide the necessary information for in depth understanding of the specialized parts used on this board EIA
51. be driven out onto the cable on the Cable Data Bits on a to 1 basis DO to DO thru D31 to D31 This register can be read or written When you read back this register you get the contents of the holding register NOT the contents of the Data Cable In order to access this register using the standard device driver you must include a define similar to what is shown below and access the register using this define in the routines as shown define SPL TX OUTPUT REG 3 Write the Test Data to the Output Port Register WriteLocal TxBoard SPL TX OUTPUT REG TestData Read Back the port register and verify it s contents ReadData ReadLocal TxBoard SPL TX OUTPUT REG User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 10 CREATED ON OCTOBER 16 2001 1 2 2 1 2 2 1 1 2 2 2 1 2 2 3 Receiver Operation The Receiver is very flexible with mode bits to control the following Software Selectable options Data rate of 5 0 megabits per second 8 Bits Receiver LSB First Software Selectable Big Little Endian Software Selectable Even or Odd Parity Software Selectable No Parity Option Software Selectable Cable Polarity Software Selectable 8 bit FIFO Software Selectable Swap Rx to Tx Data line Number of D8 Bytes Received Counter Software Programmable clock divider for slower data rates Register f
52. bits used in decode as the Local Address bits Note Remap Address value must be multiple of Range not the Range register ud If local space 0 is mapped into memory space bits are not used User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 44 CREATED ON OCTOBER 16 2001 A 3 3 Mode Arbitration Register PCI Offset 0x08 Local bus Latency Timer Number of local bus clock cycles before negating HOLD and releasing the local bus This timer is also used with bit 27 to delay BREQ input to give up the local bus only when this timer expires Local bus Pause Timer Number of local bus clock cycles before reasserting HOLD after releasing the local bus Note Applicable only to DMA operation A value of 1 enables latency timer A value of 1 enables pause timer Local bus BREQ Enable A value of 1 enables local bus BREQ input When the BREQ input is active PCI 9080 negates HOLD and releases the local bus DMA Channel Priority A value of 00 indicates a rotational priority scheme A value of 01 indicates Channel 0 has priority A value of 10 indicates Channel 1 has priority A value of 11 is reserved Local bus direct slave give up bus mode When set to 1 PCI 9080 negates HOLD and releases the local bus when the Direct Slave write FIFO becomes empty during a Direct Slave write or when the Direct Slave read F
53. cle completes User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 45 CREATED ON OCTOBER 16 2001 D29 Reads Device or Vendor ID If set to 0 reads from the PCI Configuration Register address 0x00 and returns the Device ID and Vendor ID If set to 1 reads from the PCI Configuration Register address 0x00 and returns Subsystem and Subsystem Vendor ID A 3 4 Big Little Endian Descriptor Register PCI Offset 0x0C Configuration Register Big Endian Mode A value of 1 specifies use of Big Endian data ordering for local accesses to the configuration registers A value of 0 specifies Little Endian ordering Big Endian mode can be specified for configuration register accesses by asserting the BIGEND pin during the address phase of the access D1 Direct Master Big Endian Mode A value of 1 specifies use of Big Endian data ordering for Direct Master accesses A value of 0 specifies Little Endian ordering Big BIGEND input pin during the address phase of the access D2 Direct Slave Address Space 0 Big Endian Mode A value of 1 specifies use of Big Endian data ordering for Direct Slave accesses to Local Address space 0 A value of 0 specifies Little Endian ordering D3 Direct Slave Address Expansion ROM 0 Big Endian Mode A value of 1 specifies use of Big Endian data ordering for Direct Slave accesses to Expansion
54. d a on the side of the differential pair Default to 0 Tx Data Port Output Enable D7 D0 BCR D12 This bit controls the output enable for the Data Port Bits D7 DO A 1 will enable the board to Drive Cable Data D7 DO A 0 will prevent the board from driving Cable Data D7 DO Default to 0 Tx Data Port Output Enable D15 D8 BCR D13 This bit controls the output enable for the Data Port Bits 015 08 1 will enable the board to Drive Cable Data D15 D8 A 0 will prevent the board from driving Cable Data D15 D8 Default to 0 1 2 1 10 Tx Data Port Output Enable D23 D16 BCR 014 This bit controls the output enable for the Data Port Bits D23 D16 A 1 will enable the board to Drive Cable Data D23 D16 A 0 will prevent the board from driving Cable Data D23 D16 Default to 0 1 2 1 11 Tx Data Port Output Enable D31 D24 015 This bit controls the output enable for the Data Port Bits D31 D24 A 1 will enable the board to Drive Cable Data D31 D24 A 0 will prevent the board from driving Cable Data D31 D24 Default to 0 User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 CREATED ON OCTOBER 16 2001 1 2 1 12 Tx Row Valid Length Counter The Transmit Row Valid Length Counter is the Number of D8 bytes that will be transmitted in a sin
55. d if the receivers are turned off before any local accesses are performed There is no need for the software to clear this bit the bit will clear itself D2 Rx FIFO Reset Writing a to this bit will generate a self timed pulse that will be used to reset the Rx FIFOs After setting this bit there should be a minimum of 25 Rx clk periods or 1 millisecond if the receivers are turned off before any local accesses are performed There is no need for the software to clear this bit the bit will clear itself D7 D3 D Enable Tx to Drive the cable Writing a to this bit will enable the transmit logic to drive the cable Writing a 0 to this bit will disable the transmit logic from driving the cable D Start Rx Writing a to this bit will start the receiver Writing a 0 to this bit will stop the receiver Rx Disable Output Status Lines When this bit is set to a 0 then this board will drive Cable Command D5 and D6 When this bit is set to a 1 this board will be prevented from driving Cable Command D5 and Default is 0 Reserved User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 17 CREATED ON OCTOBER 16 2001 Start Tx AME Writing a to this bit will start the transmitter Writing a 0 to this bit will stop the transmitter D9 Reserved Dual DMA Enable PCI ONLY
56. d mode the DMA controller transfers data when its DREQ input is asserted It asserts DACK to indicate that the current local bus transfer is in response to the DREQ input The DMA controller transfers Lwords 32bits of data This may result in multiple transfers for an 8 or 16 bit bus A 5 7 DMA Channel 1 PCI Data Address Register PCI Offset 0x98 PCI Data Address Register This indicates where in the PCI memory space the DMA transfers reads or writes will start from A 5 8 DMA Channel 1 Local Data Address Register PCI Offset 0x9C D0 31 Local data Address Register This indicates where in the local memory space the DMA transfers reads or writes will start from A 5 9 DMA Channel 1 Transfer Size bytes register PCI Offset 0xA Q0 0 22 DMA Transfer Size Bytes Indicates number of bytes to be transferred during operation 023 31 5 10 Channel 1 Descriptor Pointer Register PCI Offset 0xA4 Descriptor Location A 1 value indicates PCI address space A 0 value indicates Local address space D1 End of Chain 1 value indicates end of chain A 0 value indicates not end of chain descriptor Same as Nonchaining Mode D2 Interrupt after Terminal Count 1 value causes interrupt to be generated after the terminal count for this descriptor is reached A 0 value disables interrupts from being generated Direction of transfer A value indicates transfers from local bus to PCI bus
57. e of 01 indicates bus width of 16 bits A value of 10 indicates bus width of 32 bits Memory space 1 Ready Input Enable A value of 1 enables BTERM input A value of 0 disables Ready input D7 Memory space 1 BTERM Input Enable A value of 1 enables BTERM input E A value of 0 disables BTERM input If this bit is set to 0 PCI 9080 bursts four Lword maximum at a time Memory space 1 Burst Enable A value of 1 enables bursting ui A value of 0 disables bursting If burst is disabled the local bus performs continuous single cycle for burst PCI read write cycles Memory space 1 Prefetch Disable If mapped into memory space A value of 0 enables read prefetching A value of 1 disables read prefetching If prefetching is disabled PCI 9080 disconnects after each memory read D10 Read Prefetch Count Enable uli When set to 1 and memory prefetching is enabled PCI 9080 prefetches up to the number of Lwords specified in the prefetch count When set to 0 PCI 9080 ignores the count and continues prefetching until terminated by the PCI bus D11 14 Prefetch Counter Number of Lwords to prefetch during memory read cycles 0 15 D15 31 User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 CREATED ON OCTOBER 16 2001 A 4 RUNTIME REGISTERS Table D RUN TIME REGISTERS PCI Offset from Access base Value Addr i R W Re
58. e software acknowledges to the board that it has received the previous interrupt request and signals to the board that it may now generate any other interrupts that may occur This register will need some attention from the software after each interrupt has occurred Following the previous example when this interrupt has occurred the software will find that bit 13 of the ISR is now a 1 indicating that a FIFO Almost Empty interrupt has occurred This bit will remain a 1 and will not allow any additional interrupts to be generated until the software performs a write to this register To re enable the FIFO Almost Empty interrupt the software must write a 1 to bit 13 This will clear the occurrence of the interrupt The enabling latching and clearing of the FIFO Almost Empty status bit will not effect the other bits of the register This means that if the software receives the interrupt for FIFO Almost Empty the only interrupt currently enabled the software may very well find that the FIFO is now Empty indicated by bit 12 being a 1 Since this bit is not enabled as an interrupt it is acting as a status bit If it is enabled now it will immediately generate an interrupt User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 CREATED ON OCTOBER 16 2001 41 THE ON BOARD TRANSMIT CLOCK The on board oscillator U11 is used as
59. e that an interrupt on the Cable Command 1 Data Rising Edge has not occurred If this bit is not enabled as an interrupt 1 will indicate that the Cable Command 1 Data is a Rising Edge now a 0 will indicate that the Cable Command 1 Data is not a rising edge Cable Command 1 Data Falling Edge If this bit is enabled as an interrupt 1 will indicate that an interrupt on the Cable Command 1 Data Falling Edge has occurred a 0 will indicate that an interrupt on the Cable Command 1 Data Falling Edge has not occurred If this bit is not enabled as an interrupt 1 will indicate that the Cable Command 1 Data is a Falling Edge now a 0 will indicate that the Cable Command 1 Data is not a Falling edge Cable Command 1 Data If this bit is enabled as an interrupt 1 will indicate that an interrupt on Command 1 Data has occurred a 0 will indicate that an interrupt on Command 1 Data has not occurred If this bit is not enabled as an interrupt 1 will indicate that Cable Command 1 Data is currently a 1 0 will indicate that Cable Command 1 Data is not currently a 1 Cable Command 2 If this bit is enabled as an interrupt a 1 will indicate that an interrupt on Command 2 has occurred a 0 will indicate that an interrupt on Command 2 has not occurred If this bit is not enabled as an interrupt 1 will indicate that Cable Command 2 is currently a 1 0 will indicate that Cable Command 2 is not currently a
60. e the Receiver Clock Division Register The Receive Clock Division Register uses the lower 16 bits D15 DO The upper 16 bits D31 D16 are not used When these bits are all zero the receiver will operate at full speed 1 8 of the main transmit clock frequency The receive bit time is calculated the same as the transmit bit time as follows 1 count 8 clock period See Section 1 2 2 9 for a description of Bit Times VS Bits Per Second D15 D0 Cable Data D15 thru Cable Data DO or Rx Clock Division Register D31 D16 Cable Data D31 thru Cable Data D16 or not used 2 2 13 RX ROW LENGTH COUNTER Offset 0x2C RO This counter contains the number of D8 bytes received since the receiver was started It is reset to 0 when the receiver starts running The Host Processor can read it at any time D31 D0 Counter 0 31 User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 22 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 CREATED ON OCTOBER 16 2001 The number of D8 bytes received since the receiver was started 2 2 14 INTERRUPT CONTROL Offset 0x30 RW The Interrupt Control Register provides the software with a means of selecting what conditions will be allowed to generate an interrupt Enable Interrupt on Cable Command 1 Data Rising Edge 1 will allow an interrupt on the Cable ASYNC Data Lines rising edge 0 will disallow an interrupt on the Cable A
61. ee 53 A 4 11 INTERRUPT CONTROL STATUS PCI OFFSET OX668 ettet 54 A 4 12 SERIAL EEPROM CONTROL PCI COMMAND CODES USER I O CONTROL INIT CONTROL REGISTER PCI OEFESET DXOQ us indu eid DA Led 56 A 4 13 PCI PERMANENT CONFIGURATION ID REGISTER PCI OFFSET 0X70 cete 57 A 4 14 PCI PERMANENT REVISION ID REGISTER 4 57 5 LOCAL DMA REGISTERS 1 001 0 010 ntanonte nonton tonto tonto tontos istos tagen essen eaten esos eae 58 A 5 1 DMA CHANNEL 0 MODE REGISTER PCI OFFSET OX80 58 5 2 DMA CHANNEL 0 PCI ADDRESS REGISTER 59 5 3 DMA CHANNEL 0 LOCAL ADDRESS REGISTER PCI OFFSET 0 68 59 A 5 4 DMA CHANNEL 0 TRANSFER SIZE BYTES REGISTER PCI OFFSET 0X8C seen 60 5 5 DMA CHANNEL 0 DESCRIPTOR POINTER REGISTER PCI OFFSET 0X90 5 6 DMA CHANNEL 1 MODE REGISTER PCI 5 0 94 0 0 020004000000000000000000008444 0000 5 7 DMA CHANNEL I PCI DATA ADDRESS REGISTER PCI OFFSET 0 98 5 8 DMA CHANNEL I LOCAL DATA ADDRESS REGISTER PCI OFFSET 0 9 5 9 DMA CHANNEL I TRANSFER SIZE BYTES REGISTER PCI OFFSET 5 10 DMA CHANNEL I DESCRIPTOR POINTER REGISTER PCI OFFSET 4 5 11 DMA COMMAND STATUS REGISTER
62. enabled and expires during Direct Slave or DMA transfer PCI Read No Flush Mode A value of 1 submits request to not flush the read FIFO if PCI read cycle completes Read Ahead mode A value of 0 submits request to flush read FIFO if PCI read cycle completes User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 63 CREATED ON OCTOBER 16 2001 D29 Reads Device or Vendor ID If set to 0 reads from the PCI Configuration Register address 0x00 and returns the Device ID and Vendor ID If set to 1 reads from the PCI Configuration Register address 0x00 and returns Subsystem and Subsystem Vendor ID 5 14 DMA Threshold Register 1 PCI Offset 0 0 DMA Channel 0 PCI to Local Almost Full COPLAF of Full Entries minus 1 in FIFO before Requesting Local Bus for Writes COPLAF 1 COPLAE 1 should be lt FIFO Depth of 16 DMA Channel 0 Local to PCI Almost Empty COLPAE of Empty Entries minus 1 in FIFO before Requesting Local Bus for Reads COLPAF 1 COLPAE 1 should be lt FIFO Depth of 16 D8 11 DMA Channel 0 Local to PCI Almost Full COLPAF vein PCT bus of Empty Entries minus 1 FIFO before Requesting PCI Bus for Reads COPLAF 1 COPLAE 1 should be lt FIFO Depth of 16 D20 23 DMA Channel 1 Local to PCI Almost Empty of Empt
63. etching A value of 1 disables prefetching If prefetching is disabled the PCI9080 will disconnect after each memory read Expansion ROM Space Prefetch Disable A 0 enables read prefetching A 1 disables prefetching If prefetching is disabled the PCI9080 will disconnect after each memory read Read Prefetch Count Enable When set to a 1 and memory prefetching is enabled PCI 9080 prefetches up to the number of Lwords specified in the prefetch count When set to 0 PCI 9080 ignores the count and continues prefetching until terminated by the PCI bus D11 14 Prefetch Counter Number of Lwords to prefetch during memory read cycles 0 15 A count of zero selects a prefetch of 16 Lwords User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 47 CREATED ON OCTOBER 16 2001 Expansion ROM Space Local Bus Width A value of 00 indicates a bus width of 8 bits A value of 01 indicates a bus width of 16 bits A value of 10 or 11 indicates a bus width of 32 bits Expansion ROM Space Ready Input Enable A value enables Ready input A value of 0 disables the Ready input Expansion ROM Space BTERM Input Enable A value enables input A value of 0 disables the BTERMH input If this bit is set to 1 PCI 9080 bursts four Lword maximum at a time Memory Space 0 Burst Enable A value enables bur
64. evision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 CREATED ON OCTOBER 16 2001 Table of Figures Figure 1 1 1 Block oett tror ce cob De a EO Ser Ue EE nop e ee ehh Figure 1 221 Basic Serial Transfer eee eU DEB IO PR RUD P Ris Figure 1 2 2 Count Vs Bits Per Second Transmit Figure 1 2 3 Count Vs Bits Per Second Figure 2 2 1 Register Map eoa i eee de RR Figure 4 1 1Oscillator Pinout Figure 4 2 1 Jumper amet Re eS Mee s Figure 4 3 1 Cable Pinout Dei eU ete e a SN tees Table of Tables Table A Configuration EEPROM Contents essere tette tenente tente tenente tenen tente tete tenen 35 Table B Pci Configuration Register 36 Table C LOCAL CONFIGURATION REGISTERS 43 Table D RUN TIME REGISTERS DMA REGISTERS endete tret mee ee Penne Table F MESSAGING QUEUE REGISTERS User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 CREATED ON OCTOBER 16 2001 11 FUNCTIONAL DESCRIPTION PC HPDI32A ASYNC Board includes DMA Controller 64 128 256 512 Kbytes of FIFO buffering a cable Transmit controller cable Receive controller and cable transceivers RS 422 485 or d
65. gister Name after reset yes es es es 0565 yes 0x6C D32 yes Bit Dep EEPROM Control PCI Command Codes User I O 0x001767E Control Init Control un N e m lt m lt m lt m lt Z m lt jx 95 lt lt 95 92 95 lt J m lt E 95 5 A 4 1 Mailbox Register 0 PCI Offset 0x40 A 4 2 Mailbox Register 1 PCI Offset 0x44 A 4 3 Mailbox Register 2 PCI Offset 0x48 User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 52 CREATED ON OCTOBER 16 2001 A 4 4 Mailbox Register 3 PCI Offset 0x4C D0 31 32 bit mailbox register A 4 5 Mailbox Register 4 PCI Offset 0x50 32 bit mailbox register A 4 6 Mailbox Register 5 PCI Offset 0x54 32 bit mailbox register A 4 7 Mailbox Register 6 PCI Offset 0x58 32 bit mailbox register A 4 8 Mailbox Register 7 PCI Offset 0x5C 00 31 32 bit mailbox register A 4 9 PCI to Local Doorbell Register Description PCI Offset 0x60 Doorbell register A PCI master can write to this register and it will generate a local interrupt to the local processor The local processor can then read this register to determine which doorbell bit was asserted The PCI master sets a doorbell by writing a 1 to a particular bit The local processor can cle
66. gle message If this counter not used then the Transmitter will transmit data until the FIFO becomes empty This Counter MUST be used for any message that is not an even multiple of D32 FIFO word size bytes long If there is more data in the FIFO the transmitter will begin transmit of the new FIFO data For example with a Row Length of 5 Little Endian D32 FIFO and the following data in the FIFO First Load into FIFO 0x44332211 Second Load into FIFO 0x88776655 Third Load into FIFO Oxccbbaa99 Fourth Load into FIFO Ox00ffeedd Will result in the transmission of data in the following order Ox11 0x22 0x33 0x44 0x55 0x99 Oxbb Oxcc Oxdd The Upper 3 bytes of the Second and Fourth words will be read from the FIFO and Discarded If the FIFO becomes empty then the transmitter will end the message before the counter has decremented to zero 1 2 1 13 Tx Row Invalid Counter The lower 16 bits D15 D0 of the Row Invalid Counter Register will be used to extend the gap between the stop bit s of one byte and the Start Bit of the next byte in a transmission It can be set to zero for no additional gap between the stop bit s and the Start bit of the next byte The upper 16 bits D31 D16 of the Row Invalid Counter Register is used as the Transmit Clock Divider When these bits are all zero the transmitter will operate at full speed 1 8 of the main transmit clock frequency The transmit bit time is calculated as follows 1 co
67. has priority A value of 11 is reserved Local bus direct slave give up bus mode When set to 1 PCI 9080 negates HOLD and releases the local bus when the Direct Slave write FIFO becomes empty during a Direct Slave write or when the Direct Slave read FIFO becomes full during a Direct Slave read Direct slave LLOCKo Enable A value of 1 enables PCI Direct Slave locked sequences A value of 0 disables Direct Slave locked sequences PCI Request Mode A value of 1 causes PCI9080 to negate REQ when it asserts FRAME during a master cycle A value of 0 causes PCI 9080 to leave REQ asserted for the entire bus master cycle PCI Rev 2 1 Mode When set to 1 PCI 9080 operates in Delayed Transaction mode for Direct Slave Reads PCI 9080 issues a RETRY and prefetches the read data PCI Read No Write Mode A value of 1 forces a retry on writes if read is pending A value of 0 allows writes to occur while read is pending PCI Read with Write Flush Mode A value of 1 submits a request to flush a pending read cycle if a write cycle is detected A value of 0 submits a request to not effect pending reads when a write cycle occurs PCI v2 1 compatible Gate the Local Bus Latency Timer with BREQ If this bit is set to 0 PCI 9080 gives up the local bus during Direct Slave or transfer after the current cycle if enabled and BREQ is sampled If this bit is set to 1 PCI 9080 gives up the local bus only if BREQ is sampled and the Local Bus Latency Timer is
68. he Transmitter will begin sending the Start bit of the next byte to Transmit The Transmitter is capable of sending bytes back to back with no gap from the Stop bit of one byte to the Start bit of the next byte TX Big Endian Mode BCR D16 Normally the PCI HPDI32A ASYNC will transmit the D32 FIFO word as 4 D8 cable bytes with D7 DO being transmitted first D15 D8 being transmitted second D23 D16 being transmitted third and D31 D24 being transmitted fourth When this bit is set then the data will be taken out of the FIFO in Big Endian Motorola style Using Big Endian D31 D24 will be transmitted first D23 D16will be transmitted second D15 D8 will be transmitted third and D7 DO will be transmitted fourth Tx Even Parity BCR D17 This bit will control whether the Transmitter will generate Even or Odd Parity on the Transmitted byte When this bit is a 1 the Transmitter will generate Even Parity When this bit is a 0 the Transmitter will generate Odd Parity User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 CREATED ON OCTOBER 16 2001 1 2 1 3 1 2 1 4 1 2 1 5 1 2 1 6 1 2 1 7 1 2 1 8 1 2 1 9 Tx 2 Stop Bits BCR 018 When this bit is a 1 the Transmitter will send 2 stop at the end of the Byte being transmitted When this bit is a 0 the Transmitter will send only 1 St
69. hone 256 880 8787 65 CREATED ON OCTOBER 16 2001 A 6 3 Inbound Queue Port Register PCI Offset 0x40 Value written by PCI master is stored into the Inbound Post List FIFO which is located in local memory at the address pointed to by the Queue Base Address FIFO Size Inbound Post Head Pointer From the time of the PCI write until the local memory write and update of the Inbound Post Queue Head Pointer further accesses to this register result in a retry A local interrupt is generated when the Inbound Post List FIFO is not empty When the port is read by the PCI master the value is read from the Inbound Free List FIFO which is located in local memory at the address pointed the by The Queue Base Address Inbound Free Tail Pointer If FIFO is empty a value of FFFFFFFh is returned A 6 4 Outbound Queue Port Register PCI Offset 0x44 Value written by PCI master is stored into the Outbound Free List FIFO which is located in local memory at the address pointed to by the Queue Base Address 3 FIFO Size Outbound Free Head Pointer From the time of the PCI write until the local memory write and update of the Outbound Free Head Pointer further accesses to this register result in a retry If FIFO fills up a local LSERR interrupt is generated When the port Is read by the PCI master the value is read from the Outbound Post List FIFO which is located in local memory at the address pointed to by the Queue Base address 2 FIFO
70. idth of 8 bits A value of 01 indicates DMA bus width of 16 bits A value of 10 or 11 indicates a DMA bus width of 32 bits Internal Wait States data to data Ready Input Enable A value of 1 enables Ready input A value of 0 disables the Ready input Bterm Input Enable A value of 1 enables Bterm input A value of 0 disables Bterm input Local Burst Enable A value of 1 enables bursting A value of 0 disables bursting User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 58 CREATED ON OCTOBER 16 2001 Chaining A 1 value indicates non chaining mode is enabled For chaining mode the DMA source address destination address and byte count are loaded from memory in PCI or Local Address Spaces A 0 value indicates non chaining mode is enabled D10 Done Interrupt Enable value enables interrupt when done ull A 0 value disables interrupt when done If DMA clear count mode is enabled the interrupt won t occur until the byte count is cleared D11 Local Addressing Mode A 1 value indicates local addresses LA 31 2 to be held constant EN A 0 value indicates local address is incremented D12 Demand Mode A value of 1 causes the DMA controller to operate in demand mode In demand mode the DMA controller transfers data when it s DREQ input is asserted It asserts DACK to indicate that the current local bus
71. ifferential pseudo ECL The DMA on this board is intended for reading and writing the FIFOs After the DMA is initialized and started the host CPU will be free to proceed with other duties and need to respond only to interrupts The DMA controller is capable of transferring data to host memory using D32 transfers whereas the FIFO memory provides a means for continuous transmission of data without interrupting the DMA or requiring intervention from the host CPU The board also provides for DMA chaining interrupt generation for various states of the board including End Of Transfer TX FIFO Almost Empty RX FIFO Almost Full and more The Transmitter and Receiver are in FPGAs that provide a configurable interface that is highly flexible in data width and transfer protocol Figure 1 1 1 Block Diagram Tx peer o Done PLX BUS INTERFACE SNd 19 RX Done Read User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 CREATED ON OCTOBER 16 2001 12 Theory of Operation The transmitter and receiver of the standard HPDI32A board have been replaced by a ASYNC serial Data Transmitter and ASYNC serial data receiver with the following characteristics Data rate of 5 0 megabits per second 8 Bits transmitter LSB First e Software Selectable Even Odd Parity Software Selectable No Parity Bit Option
72. ille AL 35802 Phone 256 880 8787 42 CREATED ON OCTOBER 16 2001 LOCAL CONFIGURATION REGISTERS Table C LOCAL CONFIGURATION REGISTERS PCI Offset from Access base Value after Reset Addr Size R W Register Name Range for PCI to Local Address Space 0 OxFFFFEO0 Md ui ui Local Base Address Re map for PCI to Local Address 0x00000001 Space 0 0x08 D32 yes no Mode Arbitration 0x0C 032 yes Big Little Endian Descriptor Range for PCI to Local Expansion ROM 4 0x14 032 yes Local Base Address Re map for PCI to Local Expansion 0x00000000 s P Cx Mode Dep Dep Dep IO CFG Dep IO CFG Range for PCI to Local Address Space 1 0x00000000 Local Base Address Remap for PCI to Local Address Space 0x00000000 1 Local Bus Region Descriptor Space 1 for PCI to Local 0x00000000 Accesses User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 43 CREATED ON OCTOBER 16 2001 A 3 1 Local Address Space 0 Range Register for PCI to Local bus PCI Offset 0x00 Memory space indicator A value of 0 indicates Local address space 0 maps into PCI memory space A value of 1 indicates address space 0 maps into PCI I O space If mapped into memory space encoded as follows 1 being the LSB Meaning 00 locate anywhere in 32 bit PCI
73. ing data if the channel is enabled Channel 1 Abort Writing a 1 to this bit causes the channel to abort the current transfer The channel enable bit must be cleared The channel complete bit is set when the abort has completed D3 Clear Interrupt Writing a 1 to this bit clears channel 1 interrupts Channel 1 Done A value indicates this channel s transfer is complete A 0 value indicates the channel transfer is not complete Reserved User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 62 CREATED ON OCTOBER 16 2001 5 13 DMA Arbitration Register 1 PCI Offset 0xAC Local bus Latency Timer Number of local bus clock cycles before negating HOLD and releasing the local bus This timer is also used with bit 27 to delay BREQ input to give up the local bus only when this timer expires Local bus Pause Timer Nu mber of local bus clock cycles before reasserting HOLD after releasing the local bus Note Applicable only to DMA operation A value of 1 enables latency timer A value of 1 enables pause timer Local bus BREQ Enable A value of 1 enables local bus BREQ input When the BREQ input is active PCI 9080 negates HOLD and releases the local bus DMA Channel Priority A value of 00 indicates a rotational priority scheme A value of 01 indicates Channel 0 has priority A value of 10 indicates Channel 1
74. ision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 11 CREATED ON OCTOBER 16 2001 1 2 2 4 1 2 2 5 1 2 2 6 1 2 2 7 1 2 2 8 1 2 2 9 Rx Swap Receiver to Cable Command 1 BCR D27 When this bit is set to a 1 the Receiver will receive data on Cable Command 1 When this bit is set to a 0 the Receiver will receive on Cable Command 2 Setting either BCR D27 or BCR D19 will allow the board to send self test loop back messages without requiring an external loop back cable Setting both BCR D27 and BCR D19 will allow 2 boards to communicate back to back using a to 1 cable without requiring a crossover cable Default is 0 Rx 8 bit FIFO BCR D28 When this bit is set to a 1 the Receiver will only load a single byte of data into each D32 FIFO word When this bit is set to a 0 the Receiver will assemble 4 bytes into D32 word and then write D32 word into the Receive FIFO Default is 0 In Little Endian Mode the received byte will be in D7 DO D15 D8 will contain the lower 8 bits of the 16 bit time tag D23 D16 will contain the upper 8 bits of the 16 bit time tag and D31 D24 will contain the lower 8 bits of the Rx Row Length Counter In Big Endian Mode the received byte will be in D31 D24 D23 D16 will contain the lower 8 bits of the 16 bit time tag D15 D8 will contain the upper 8 bits of the 16 bit time tag and D7 DO will contain the
75. iz Receive Data Line Reset to tri State hiz Transmitter Running Reset to tri state and driven to logic low Receiver Running Reset to tri state on and driven to logic low 32 programmable I O Lines Reset to tri State hi z User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 CREATED ON OCTOBER 16 2001 1 2 1 1 2 1 1 1 2 1 2 Transmitter Operation The transmitter is very flexible with mode bits and software controlled counters to control the following Software Selectable options e Data rate of 5 0 megabits per second 8 Bit Transmitter LSB First Software Selectable Big Little Endian e Software Selectable Number of D8 bytes per Message Software Selectable 1 or 2 Stop Bits Software Selectable Even or Odd Parity Software Selectable No Parity Bit Option Software Selectable Swap Tx to Rx Data Line Software Selectable Clock Divider for slower Data Rates Software Selectable Cable Polarity Positive or Negative Software Selectable Programmable Gap between Bytes Software Selectable No Gap between Bytes e Software Selectable 8 bit FIFO The Transmitter will also generate the following Status that may be read thru the Board Status Register and may generate Interrupts thru the Interrupt Control and Interrupt Status Registers Tx Transmit Busy
76. l L 1 will indicate the Tx FIFO is not full 0 will indicate the Tx FIFO is full Rx FIFO Empty L red 1 will indicate the Rx FIFO is not empty 0 will indicate the Rx FIFO is empty Rx FIFO Almost Empty L 1 will indicate the Rx FIFO is not almost empty m 0 will indicate the Rx FIFO is empty p Rx FIFO Almost Full L 1 will indicate the Rx FIFO is not almost full 0 will indicate the Rx FIFO is almost full Rx FIFO Full L 1 will indicate the Rx FIFO is not full 0 will indicate the Rx FIFO is full Board Jumper 0 1 will indicate that Board Jumper 0 is present E will indicate that board jumper 0 is absent Board Jumper 1 1 will indicate that Board Jumper 1 is present 0 will indicate that board jumper 1 is absent D19 Rx FIFO Underflow 1 will indicate that a Receive FIFO underflow has occurred 0 will indicate that no Receive FIFO underflow has occurred Rx FIFO Overflow 1 will indicate that a Receive FIFO overflow has occurred 0 will indicate that no Receive FIFO overflow has occurred Tx FIFO Overflow 1 will indicate that a Transmit FIFO overflow has occurred 0 will indicate that no Transmit FIFO overflow has occurred Rx Receive Parity Error 1 will indicate that the Receiver has detected a Parity Error in the Receive Data 0 will indicate that the Receiver has not detected a Parity Error Reset to 0 when the Receiver is started Rx Data Error 1 will indicate that the Receiver has detected a Data Er
77. m Rx FIFO Underflow Read of the Rx FIFO while the Rx FIFO is Empty Rx FIFO Overflow Write to the Rx FIFO while the Rx FIFO is Full Tx FIFO Overflow Write to the Tx FIFO while the Tx FIFO is Full The Rx FIFO events are cleared by a Rx FIFO Reset The Tx FIFO Event flag is cleared by a Tx FIFO reset User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 30 CREATED ON OCTOBER 16 2001 3 4 INTERRUPTS In order for this board to generate interrupts to the PCI bus Bits 8 11 and 16 of the PLX Interrupt Control Status Register must be set to a 1 These bits must be set to a 1 in order for the interrupts to occur The next step in initializing the interrupt is to specify which interrupts are to be allowed The board allows the software to enable some interrupts and leave others disabled This is accomplished by writing a 1 to the appropriate bits in the Interrupt Control Register ICR For example to enable the interrupt for FIFO Almost Empty the software will need to write a 1 to bit 13 of the ICR This bit will not need to be changed again until the need to disable this specific interrupt This enable can be a one time process which will allow many interrupts to occur Multiple interrupts from the same cause are prevented via the Interrupt Status Register ISR Writing to the ISR is the method by which th
78. mory space A value of 1 indicates the register maps into I O space Specified in Local Address Space 1 Range Register Location of register if memory space Location values 00 Locate anywhere in 32 bit memory address space 01 Locate below 1 Mbyte memory address space 10 Locate anywhere in 64 bit memory address space 11 Reserved Specified in Local Address Space 1 Range Register Prefetchable if memory space A value of 1 indicates there are no side effects on reads This bit reflects the value of bit 3 in the LASIRR register and provides only status to the system This bit has no effect on the operation of the PCI 9080 Prefetching features of this address space are controlled by the associated Bus Region Descriptor Register Specified in LASIRR register If I O Space bit 3 is included in the base address Memory base address for access to Local Address Space 1 A 2 14 PCI Base Address Register PCI Configuration Offset 0x20 Reserved A 2 15 PCI Base Address Register PCI Configuration Offset 0x24 Reserved A 2 16 PCI Cardbus CIS Pointer Register PCI Configuration Offset 0x28 User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 41 CREATED ON OCTOBER 16 2001 A 2 17 PCI Subsystem Vendor ID Register PCI Configuration Offset 0x2C A 2 18 PCI Subsystem ID Register PCI Configurati
79. n decode and a 0 to all others Used in conjunction with PCI Configuration register 0x30 Default is 64 Kbytes A 3 6 Local Expansion ROM Local Base Address Re map register for PCI to Local Bus and BREQo Control PCI Offset 0x14 Direct Slave BREQo Backoff Requests Out Delay Clocks Number of local bus clocks in which a Direct Slave HOLD request is pending and a Local Direct Master access is in progress and not being granted the bus HOLDA before asserting BREQo Once asserted BREQo remains asserted until the PCI900 receives HOLDA LSB 8 or 64 clocks Local Bus BREQo Enable A 1 value enables the PCI9080 to assert the BREQo output Re map of PCI Expansion ROM space into a Local address space The bits in this register re map replace the PCI address bits used in decode as the Local address bits A 3 7 Local Address Space 0 Expansion ROM Bus Region Descriptor Register PCI Offset 0x18 Memory Space 0 Local Bus Width A value of 00 indicates a bus width of 8 bits A value of 01 indicates a bus width of 16 bits A value of 10 or 11 indicates a bus width of 32 bits The bus width is forced to 16 bits for the Sx mode Memory Space 0 Ready Input Enable 1 value enables Ready input A value of 0 disables the Ready input Memory Space 0 Input Enable A value enables input A value of 0 disables the BTERM input Memory Space 0 Prefetch Disable If mapped into memory space A 0 enables read pre f
80. nbound Post List FIFO Interrupt This bit is set when the Inbound Post List FIFO if not empty This bit is not affected by the Interrupt Mask bit When this bit is set interrupt is masked Outbound Free List FIFO Overflow Interrupt This bit is set when the Outbound Free List FIFO becomes full A local SERR NMJ interrupt is generated if enabled in the Interrupt Control Status Register Writing clears the interrupt 08 31 J D3 5 D User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 68
81. on Offset 0x2E D0 15 Subsystem ID unique add in board Device ID A 2 19 PCI Expansion ROM Base Register PCI Configuration Offset 0x30 Address Decode Enable A value of 1 indicates the device accepts accesses to the expansion ROM address A value of 0 indicates the device does not accept accesses to expansion ROM space Should be set to 1 by PCI host if expansion ROM is present D1 10 D11 31 Expansion ROM Base Address upper 21 bits A 2 20 PCI Interrupt Line Register PCI Configuration Offset 0x3C Interrupt Line Routing Value Indicates which input of the system interrupt controller s to which the interrupt line of the device is connected A 2 21 PCI Interrupt Pin Register PCI Configuration Offset 0x3D Interrupt Pin register Indicates which interrupt pin the device uses The following values are decoded 0 Interrupt Pin 1 INTA 2 INTB 3 INTC 4 INTD Note PCI 9080 su A 2 22 PCI Min_Gnt Register PCI Configuration Offset 0x3E Min Gnt Used to specify how long a burst period the device needs assuming a clock rate of 33 MHz Value is multiple of 1 4 use increments A 2 23 PCI Max Lat Register PCI Configuration Offset 0x3F Max Lat Specifies how often the device mu st gain access to the PCI bus Value is multiple of 4 user increments User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsv
82. op Bit Default to 0 Tx Swap Tx Data to CC2 BCR D19 Normally the PCI HPDI32A ASYNC will transmit data on Cable Command 1 lines When this bit is set to a 1 the Transmitter will send its data on Cable Command 2 lines Default to 0 Tx No Parity BCR D20 Normally the PCI HPDI32A ASYNC will transmit data and a parity bit of selectable polarity When this bit is set to a 1 the Transmitter will not send a parity bit When this bit is a 0 the Transmitter will send a parity bit as part of each byte send Default to 0 Tx 8 Bit FIFO BCR D21 Normally the PCI HPDI32A ASYNC will transmit all 32 bits of the FIFO data word When this bit is set to a 1 the transmitter will only send 1 byte from each 32 bit FIFO word the other 24 bits will be discarded For little Endian operation D7 DO is the Byte that is send For Big Endian operation D31 D24 is the byte that is send When this bit is set to a 0 the Transmitter will send the entire 32 bit FIFO word Default to 0 Tx Invert Cable Polarity BCR D22 Normally the PCI HPDI32A ASYNC will transmit data in positive polarity a 1 will generate a on the side of the differential pair and a LO on the side of the differential pair This bit will cause the Transmitter to invert the serial data before it is sent to the cable drivers so that a 1 will generate a LO on the side of the differential pair an
83. or the Cable D31 D0O Lines When the Receiver is started it will begin searching for an Idle Cable condition defined as no activity on the cable for 88 divided clock cycles Only after locating a period when the bus is completely idle can the Receiver be sure that the next Transition detected on the cable is the Start Bit of a new Byte After locating the Start Bit The Receiver will begin shifting in the 8 Data Bits and the optional Parity Bit During the Stop Bit the Receiver is checking Parity and loading the received byte into the FIFO The receiver does not check the Stop Bit but it does require that a stop bit be present The Receiver will flag Receive Parity Errors but will load the byte containing the error into the FIFO The Receiver will also check for data errors during the receive operation A Data error is defined as finding a transition during a bit cell time Transitions are only allowed at the boundaries between bit cells If a Data error occurs during a byte of data that byte is lost and the Receiver will stop collecting data until the cable 15 detected as being Idle again The Receiver will generate the following status in the Board Status Register that can be read by the Host Processor and can be used to generate Interrupts thru the Interrupt control register RxRunning The Receiver is enabled and is ready Rx Busy The Receiver is in the process of receiving a message e Error The Receiver is in Error recovery
84. or the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 33 CREATED ON OCTOBER 16 2001 4 3 CABLE CONNECTOR The 80 pin user connector reference designator 1 15 manufactured by Robinson Nugent the part number is 50 080 1 5 1 The part number for the mate is PSOE 080 S TG 50 mil cabling is suggested for twisted pair or 25 0805 25 mil cabling may be used for multidrop capability but with loss of twisted pair Figure 4 3 1 Cable Pinout 6 Cable ASYNC Tx Data 8 CibeASYNCRDaa 0 Cable Command 3 Not Used CABLEDM 66 CABLEDM fos T CABLED2S o CABLED3 s 39 CABLED3I O User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 34 Appendix A PLX REGISTER PROGRAMMING The following Appendix describes the registers of the PLX PCI Bus Interface that is used on the PMC HPDI32A CDC A l Configuration EEPROM During configuration the PLX will initialize itself from a EEPROM that is programmed at the factory The following values are loaded into the PLX and are used to configure the board for operation Table A Configuration EEPROM Contents PCI
85. orm on the bus A value of 1 indicates that fast back to back transfers can occur to any agent on the bus A value of 0 indicates fast back to back transfers can only occur to the same agent as the previous cycle D10 15 uii D10 15 User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 37 CREATED ON OCTOBER 16 2001 A 2 3 PCI Status Register PCI Configuration Offset 0x06 If high supports User definable features This bit can only be written from the local side It is read only from the PCI side Fast Back to Back Capable When this bit is set to a 1 it indicates the adapter can accept fast back to back transactions A 0 indicates the adapter cannot Master Data Parity Error Detected This bit is set to a 1 when three conditions are met 1 the PCI9080 asserted PERR itself or observed PERR asserted 2 the PCI9080 was the bus master for the operation in which the error occurred 3 the Parity Error Response bit in the Command Register is set Writing a to this bit clears the bit to a 0 DEVSEL Timing Indicates timing for DEVSEL assertion A value of 01 indicates a medium decode Note Hardcode to 01 Target Abort When this bit is set to a 1 this bit indicates the PCI9080 has signaled a target abort Writing a 1 to this bit clears the bit 0
86. ost Empt D15 D8 High byte Almost Empt D23 D16 Low byte Almost Full D31 D24 High byte Almost Full 2 2 6 FIRMWARE FEATURES Offset 0x14 RW Register to note new features present in FW This Register has been removed from the ASYNC It has been replaced by the Tx Output Data Port Register 2 2 7 TX OUTPUT DATA PORT REGISTER Offset 0x14 RW This is the holding register for data to be output on the 32 programmable I O Lines The outputs are enabled to drive the cable thru the Board Control Register Bits 15 thru 12 Reading this address will give the contents of the holding register NOT the contents of the Cable Data Lines To read the current state of the Cable Data Lines read the Rx Status Block Length register D31 D0 Tx Output Data Port Register 2 2 8 FIFO Offset 0x18 RW The 64 128 256 512 Kbytes FIFOs are used for buffering data This gives the software a means of buffering the data before it is transmitted to the cable or retrieved from the FIFOs The FIFOs are also used by the DMA for the same purpose This eliminates unnecessary PCI bus arbitration which provides for faster and more efficient bus cycles for transfers hence a faster and more efficient system Typical configuration is 256Kbytes which is 128Kbytes Transmit FIFO 32K by 32 bits and 128Kbytes Receive FIFO 32 K by 32 bits FIFO Data 0 31 This is the buffer that contains both the transmit and receive data A write to this offset will load
87. ot occurred If this bit is not enabled as an interrupt a 1 will indicate that the Rx FIFO is currently almost full a 0 will indicate that the Rx FIFO is not currently almost full Rx FIFO Full If this bit is enabled as an interrupt 1 will indicate that an interrupt on the Rx FIFO full has occurred a 0 will indicate that an interrupt on the Rx FIFO full has not occurred If this bit is not enabled as an interrupt 1 will indicate that the Rx FIFO is currently full a 0 will indicate that the Rx FIFO is not currently full Enable Interrupt on Rx FIFO Underflow If this bit is enabled as an interrupt 1 will indicate that an interrupt on Rx FIFO Underflow has occurred a 0 will indicate that an interrupt on Rx FIFO Underflow has not occurred If this bit is not enabled as an interrupt 1 will indicate that Rx FIFO Underflow has occurred a 0 will indicate that Rx FIFO Underflow is not occurred Enable Interrupt on Rx FIFO Overflow If this bit is enabled as an interrupt a 1 will indicate that an interrupt on Rx FIFO Overflow has occurred a 0 will indicate that an interrupt on Rx FIFO Overflow has not occurred If this bit is not enabled as an interrupt 1 will indicate that Rx FIFO Overflow has occurred a 0 will indicate that Rx FIFO Overflow has not occurred Enable Interrupt on Tx FIFO Overflow If this bit is enabled as an interrupt 1 will indicate that an interrupt on Tx FIFO Overflow has occurred a 0 will indicate that an inte
88. rbell Interrupt Enable EE A value of 1 enables doorbell interrupts Used in conjunction with PCI interrupt enable Clearing the doorbell interrupt bits that caused the interrupt also clears the interrupt PCI Abort Interrupt Enable HE A value of 1 enables a master abort or master detect of a target abort to generate a PCI interrupt Used in conjunction with PCI interrupt enable Clearing the abort status bits also clears the PCI interrupt PCI Local Interrupt Enable A value of 1 enables a local interrupt input to generate a PCI interrupt Use in conjunction with PCI Interrupt enable Clearing the local bus cause of the interrupt also clears the interrupt Retry Abort Enable A value of 1 enables PCI 9080 to treat 256 Master consecutive retries to a Target as a target abort A value of 0 enables PCI 9080 to attempt Master Retries indefinitely Note for diagnostic purposes only A value of 1 enables local interrupt output D17 Local Doorbell Interrupt Enable A value of 1 enables doorbell interrupts Used in conjunction with Local interrupt enable Clearing the local doorbell interrupt bits that caused the interrupt also clears the interrupt Local DMA Channel 0 Interrupt Enable A value of 1 enables DMA Channel 0 interrupts Used in conjunction with Local interrupt enable Clearing the DMA status bits also clears the interrupt Local DMA Channel 1 Interrupt Enable A value of 1 enables DMA Channel 1 interrupts Used in conjunction with Loc
89. ree Tail Pointer Local Memory Offset for Inbound Free List FIFO This register is initialized as 0 FIFO Size by the local CPU software It is maintained by the MU hardware and is incremented modulo the FIFO size Queue Base Address A 6 9 Inbound Post Head Pointer Register PCI Offset 0xD0 Inbound Post Head Pointer Local Memory Offset for Inbound Post List FIFO This register is initialized as 1 FIFO Size by the local CPU software It is maintained by the MU hardware and is incremented modulo the FIFO size A 6 10 Inbound Post Tail Pointer Register PCI Offset 0xD4 Inbound Post Tail Pointer Local Memory Offset for Inbound Post List FIFO This register is initialized as 1 FIFO Size by the local CPU software A 6 11 Outbound Free Head Pointer Register PCI Offset 0xD8 Outbound Free Head Pointer Local Memory Offset for Outbound Free List FIFO This register is initialized as 3 FIFO Size by the local CPU software It is maintained by the MU hardware and is incremented modulo the FIFO size A 6 12 Outbound Free Tail Pointer Register PCI Offset 0xDC Outbound Free Tail Pointer Local Memory Offset for Outbound Free List FIFO This register is initialized as 3 FIFO Size by the local CPU software D20 31 Queue Base Address User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 67
90. ror in the receive data 0 will indicate that the Receiver has not detected a Data Error in the receive data A Data Error is a Transition during a receive Bit Cell Time Transitions are only allowed at the boundaries between bit cells Reset to 0 when the Receiver is started Rx Busy 1 will indicate that the Receiver busy receiving a byte of data 0 will indicate that the Receiver is Idle in Error Recovery or not running Tx Transmit Busy 1 will indicate the Transmitter is busy Transmitting data 0 will indicate the Transmitter is either IDLE sending Gap or Waiting for FIFO data User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 20 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 D10 Dil D12 D13 D14 D15 D16 D17 D20 D21 D22 D23 D24 D25 CREATED ON OCTOBER 16 2001 2 2 4 TX ALMOST Offset 0x0C RW This register is contains the values that are used to program the Almost Flags of the transmit FIFOs Default is 0x01000008 Almost Empty 0x08 Almost Full 0x0100 from full D7 D0 Low byte Almost Empty D15 D8 High byte Almost Empty D23 D16 Low byte Almost Full D31 D24 High byte Almost Full 22 5 RX ALMOST Offset 0x10 RW This register is contains the values that are used to program the Almost Flags of the receive FIFOs Default is 0x01000008 Almost Empty 0x08 Almost Full 0x0100 from full 7 Low byte Alm
91. rrupt on Tx FIFO Overflow has not occurred If this bit is not enabled as an interrupt 1 will indicate that a Tx FIFO Overflow has occurred a 0 will indicate that a Tx FIFO Overflow has not occurred Enable Interrupt on Rx Parity Error If this bit is enabled as an interrupt a 1 will indicate that an interrupt Rx Parity Error has occurred a 0 will indicate that an interrupt Rx Parity Error has not occurred If this bit is not enabled as an interrupt a 1 will indicate that a Rx Parity Error has occurred a 0 will indicate that a Rx Parity Error has not occurred User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 26 CREATED ON OCTOBER 16 2001 Enable Interrupt on Rx Data Error If this bit is enabled as an interrupt a 1 will indicate that an interrupt on Rx Data Error has occurred a 0 will indicate that an interrupt on Rx Data Error has not occurred If this bit is not enabled as an interrupt 1 will indicate that Rx Data Error has occurred a 0 will indicate that Rx Data Error has not occurred D21 Enable Interrupt on Rx Receive Busy If this bit is enabled as an interrupt a 1 will indicate that an interrupt Rx Receive Busy has occurred a 0 will indicate that an interrupt on Rx Receive Busy has not occurred If this bit is not enabled as an interrupt a 1 will indicate that Rx Receive Busy has occurred
92. sent Writing a 0 to this bit Place stop bits on the end of each byte sent Default is 0 1 Stop bit Tx Transmit on Cable Command 2 Writing a 1 cause this board to transmit on Cable Command 2 Writing a 0 cause this board to transmit on Cable Command 1 Default is 0 transmit on Cable Command 1 Tx No Parity Bit Writing a 1 cause this board to not transmit a parity bit Writing a 0 cause this board to transmit a parity bit Default is 0 transmit a parity bit Tx 8 bit FIFO Writing a 1 cause this board to transmit 1 byte from each 032 FIFO Word The other 3 bytes are discarded Writing a 0 causes this board to transmit all 4 bytes from each D32 FIFO word Default is 0 transmit all 4 bytes from each D32 FIFO word Tx Invert Cable Polarity Writing a 1 cause this board to Invert its serial data before it is sent to the Cable Writing a 0 cause this board to transmit its serial data without inverting the data Default is 0 do not invert the transmit data P23 Resrved D24 Rx FIFO Big Endian Mode Writing a 1 to this bit will enable receiving data in Big Endian Mode Writing a 0 to this bit will enable receiving data in Little Endian Mode Default is 0 Little Endian Mode User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802
93. sfers reads or writes will start from 5 3 DMA Channel 0 Local Address Register PCI Offset 0x88 0 31 Local Address Register This indicates where in the local memory space transfers reads writes will start from User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 59 CREATED ON OCTOBER 16 2001 A 5 4 DMA Channel 0 Transfer Size Bytes Register PCI Offset 0x8C 0 22 DMA Transfer Size Bytes Indicates number of bytes to be transferred during operation 23 31 A 5 5 DMA Channel 0 Descriptor Pointer Register PCI Offset 0x90 Descriptor Location A Value of 1 indicates PCI address space A Value of 0 indicates Local Address Space End of Chain A 1 value indicates end of chain A 0 value indicates not end of chain descriptor Same as Nonchaining Mode Interrupt after Terminal Count A value causes an interrupt to be generated after the terminal count for this descriptor is reached A 0 value disables interrupts from being generated Direction of transfer A value indicates transfers from local bus to PCI bus A 0 value indicates transfers from PCI to local bus Next Descriptor Address Quad word aligned Bit 3 0 0000 A 5 6 DMA Channel 1 Mode Register PCI Offset 0x94 Local Bus Width A value of 00 indicates a bus width of 8 bits A
94. sting A value of 0 disables bursting If burst is disabled the local bus performs continuous single cycles for burst PCI read write cycles Extra Long serial EEPROM A value of 1 loads the Subsystem ID and Local Address Space 1 registers A value of 0 indicates not to load them Expansion ROM Space Burst Enable A value enables bursting A value of 0 disables bursting If burst is disabled the local bus performs continuous single cycles for burst PCI read write cycles Direct Slave PCI write mode A 0 indicates that the PCI9080 should disconnect when the Direct Slave write FIFO is full A indicates that the PCI9080 should de assert TRDY when the write FIFO is full PCI Target Retry Delay Clocks Contains the value multiplied by 8 of the of PCI bus clocks after receiving a PCI Local read or write access and not successfully completing a transfer Only pertains to Direct Slave writes when bit 27 is set to 1 A 3 8 Local Range register for Direct Master to PCI PCI Offset 0x1C D16 31 Specifies which local address bits to use for decoding a Local to PCI bus access Each of the bits corresponds to an address bit Bit 31 corresponds to Address bit 31 A value of 1 should be written to all bits that should be included in decode and a 0 to all others This range is used for Direct Master memory I O or configuration accesses A 3 9 Local Bus Base Address register for Direct Master to PCI Memory PCI Offset 0x20 DO 15
95. ter Map See Table 2 1 1 Board Reset will reset the local logic clear the FIFOs and place the appropriate registers into a known state Tx FIFO Reset will reset the Tx FIFOs Rx FIFO Reset will reset the Rx FIFOs The FIFOs are reset by either a hardware system reset of the board a software FIFO reset Board Control Register bit 1 or bit 2 or a software board reset Board Control Register bit 0 User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 29 CREATED ON OCTOBER 16 2001 33 FIFOs The FIFOs flags are used to indicate the current fill level of the FIFO There are four flags for Tx and four flags for Rx These flags are labeled and defined as follows Empty Almost Empty Almost Full Full There are 0 true signals The almost registers are used for programming the FIFOs states are Empty 0 Almost Empty programmable level Almost Full programmable level Full depth Use bits 1 and 2 of the BCR a board reset will not program the FIFOs The FIFO Almost Registers are used to program the Almost Empty and Almost Full flag levels The default is 0x01000008 which will give you levels of Almost Empty 0x0008 8 D32 words above empty Almost Full 0x0100 Almost Full is 256 D32 words below Full In addition there are 3 FIFO Event Flags that are part of the FIFO syste
96. that an interrupt on Tx Transmit Done has occurred a 0 will indicate that an interrupt on Tx Transmit Done has not occurred If this bit is not enabled as an interrupt 1 will indicate that Tx Transmit Done has occurred a 0 will indicate that Tx Transmit Done has not occurred Tx FIFO Empty If this bit is enabled as an interrupt 1 will indicate that an interrupt on the Tx FIFO empty has occurred a 0 will indicate that an interrupt on the Tx FIFO empty has not occurred If this bit is not enabled as an interrupt 1 will indicate that the Tx FIFO is currently empty a 0 will indicate that the Tx FIFO is not currently empty Tx FIFO Almost Empty If this bit is enabled as an interrupt 1 will indicate that an interrupt on the Tx FIFO almost empty has occurred a 0 will indicate that an interrupt on the Tx FIFO almost empty has not occurred If this bit is not enabled as an interrupt 1 will indicate that the Tx FIFO is currently almost empty a 0 will indicate that the Tx FIFO is not currently almost empty Tx FIFO Almost Full If this bit is enabled as an interrupt 1 will indicate that an interrupt on the Tx FIFO almost full has occurred a 0 will indicate that an interrupt on the Tx FIFO almost full has not occurred If this bit is not enabled as an interrupt 1 will indicate that the Tx FIFO is currently almost full a 0 will indicate that the Tx FIFO is not currently almost full Tx FIFO Full If this bit is enabled as an interrupt
97. tion which is 128Kbytes of Transmit FIFO and 128Kbytes of Receive FIFO Both FIFOs are organized as 32K deep by 32 bits wide The receive FIFOs are loaded by the cable receive control logic and read by either the CPU or the DMA The transmit FIFOs are loaded by either the CPU or the DMA and read by the cable transmit control logic The 4 status flags that accompany the FIFOs are all active low 0 being TRUE and are as follows Empty Almost Empty Almost Full Full The Almost Empty and the Almost Full status flags can be programmed by the software to become true at most desired levels In addition there are 3 FIFO Event Flags that are part of the FIFO system Rx FIFO Underflow Read of the Rx FIFO while the FIFO is Empty Rx FIFO Overflow Write to the Rx FIFO while the Rx FIFO is Full Tx FIFO Overflow Write to the Tx FIFO while the Tx FIFO is Full The Rx FIFO events are cleared by a Rx FIFO Reset The Tx FIFO Event flag is cleared by a Tx FIFO reset User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 14 CREATED ON OCTOBER 16 2001 2 1 PCI HPDI32A ASYNC REGISTER INFORMATION The PCLHPDI32A ASYNC Card complies with the plug n play concept That is at the time of power up an attempt will be made by the CPU to set up the board to meet the configuration requirements of the system In doing this the C
98. unt 8 clock period Typically the Transmit clock will be 40 Mhz 25 nsec period The Bit times and Bit Rates for several division count values are given in the following table Figure 1 2 2 Count Vs Bits Per Second Transmit 0 20 5Mbs 2 60 166 58 8 100 555555Kbps 1 2 1 14 Tx Status Block Length Counter The Transmit Status Block Length Counter has been replaced by a counter that will count the actual number of bytes transmitted If the Transmit FIFO becomes empty during a Transmit operation the User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 CREATED ON OCTOBER 16 2001 1 2 1 15 1 2 1 16 Transmitter will STOP This counter can be used to detect if the transmit DMA operation was interrupted by other PCI bus traffic Tx Clock Division Counter This Counter has been removed from the PC HPDI32A ASYNC The Device Driver will not allow access to this register as of this time The clock division Register counter is located in the upper 16 bits of the Tx Row Invalid Counter Tx Output Data Port Register The Firmware Features Register has been removed from the PC HPDI32A ASYNC It has been replaced by a 32 bit register that can is under software control When Enabled by the proper output enable bits in the Board Control Register the contents of this register will
99. upt on Tx FIFO Overflow 1 will allow an interrupt on Tx FIFO Overflow 0 will disallow an interrupt on Tx FIFO Overflow Enable Interrupt on Rx Parity Error 1 will allow an interrupt on Rx Parity Error 0 will disallow an interrupt on Rx Parity Error Enable Interrupt on Rx Data Error 1 will allow an interrupt on Rx Data Error 0 will disallow an interrupt on Rx Data Error Enable Interrupt on Rx Receive Busy 1 will allow an interrupt on Rx Receive Busy 0 will disallow an interrupt on Rx Receive Busy Enable Interrupt on Tx Transmitter Busy 1 will allow an interrupt on Tx Transmitter Busy 0 will disallow an interrupt on Tx Transmitter Busy 2 2 15 INTERRUPT STATUS Offset 0x34 RC The Interrupt Status Register serves as a dual purpose register Each bit in this register operates independently of each other If an interrupt condition is enabled in the Interrupt Control Register the appropriate bit in the Interrupt Status Register will indicate if an interrupt has occurred or not and it will continue to indicate this until the software resets that bit If an interrupt bit is not enabled in the Interrupt Control Register then the appropriate bit in the Interrupt Status Register will indicate whether or not the condition exists for an interrupt request Cable Command 1 Data Rising Edge If this bit is enabled as an interrupt 1 will indicate that an interrupt on the Cable Command 1 Data Rising Edge has occurred a 0 will indicat
100. us and Int Mask at 0x30 and 0x34 respectively 08 15 Sub class Code 0x80 Other Communications device D16 D23 Base Class Code 0x07 Communications Device A 2 6 PCI Cache Line Size Register PCI Configuration Offset 0x0C D0 7 A 2 7 PCI Latency Timer Register PCI Configuration Offset 0x0D PCI Latency Timer Units of PCI bus clocks the amount of time the PCI9080 as a bus master can burst data on the PCI bus 2 8 PCI Header Type Register PCI Configuration Offset 0x0E Configuration Layout Type Specifies the layout of bits Ox10 through Ox3F in configuration space Only one encoding 0 is defined other encodings are reserved Header Type A indicates multiple functions A 0 indicates a single function A 2 9 PCI Built In Self Test BIST Register PCI Configuration Offset 0x0F A value of 0 means the device has passed its test Non zero values mean the device failed Device specific failure codes can be encoded in the non zero value Reserved Device returns 0 D4 5 PCI writes a 1 to invoke BIST Generates an interrupt to local bus Local bus resets the bit when BIST is complete Software should fail device if BIST is not complete after 2 seconds Refer to Runtime registers for interrupt control status Return 0 if the device is not BIST compatible User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville
101. used to control 2 functions The lower 16 bits B15 D0 is used to control the Gap between the Stop Bit of one byte and the Start bit of the next byte transmitted In units of Main Clock Ticks Typically 40 Mhz Reset to 8 which will give an additional time of 200 nSec a single bit time Can be set to zero to give no gap between the Stop bit of one byte and the Start bit of the next byte 16 Bit counter The Upper 16 bits D31 D16 of the Row Invalid Register Counter is used to control the Transmit Clock Divider When these bits are all zero the transmitter will operate at full speed 1 8 of the main transmit clock frequency See Section 1 2 1 13 for a description of bit times VS Bits Per Second D15 D0 Data 0 15 Sets the size of the Gap between bytes in a message D31 D16 Transmit Clock Divider Sets the Bit cell time of transmit data See Section 1 2 1 13 2 2 12 RX STATUS BLOCK LENGTH COUNTER Offset 0x28 RO The Rx Status Block Length counter has been removed from the ASYNC board When the Alternate Register Select bit BCR D26 is a 0 then this Counter has been replaced by a 32 bit register that will allow the Host processor to read the current state of the 32 Cable Data lines The RS 485 Receivers used on the HPDI32A ASYNC project are guaranteed that a Floating Cable will be received as a logic 1 When the Alternate Register Select bit BCR D26 is a 1 then reading and writing this register will read and writ
102. value of 01 indicates bus width of 16 bits A value of 10 or 11 indicates a DMA bus width of 32 bits The bus width is forced to 16 bits for the Sx mode Ready Input Enable A value enables Ready input A 0 value disables the Ready input Bterm Input Enable A value enables Bterm input A value of 0 disables the Bterm input If this bit is set to 0 PCI 9080 bursts four Lword maximum at a time Local Burst Enable A value enables Local bursting input A value of 0 disables Local bursting If burst is disabled the local bus performs continuous single cycles for burst PCI read write cycles Chaining A value indicates chaining mode enabled For chaining mode the DMA source address destination address and byte count are loaded from memory in PCI or Local address spaces A 0 value indicates non chaining mode Done Interrupt Enable A value enables interrupt when done A 0 value disables the interrupt when done If DMA Clear Count Mode is enabled the interrupt won t occur until the byte count is cleared Local Addressing Mode A 1 value indicates local addresses LA 31 2 to be held constant A 0 value indicates local addresses is incremented User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 60 CREATED ON OCTOBER 16 2001 Demand Mode A value of 1 causes the DMA controller to operate in demand mode In deman
103. vented from driving Cable Command D5 and Cable Command D6 When this bit is set to a 0 then this board will drive Cable Command D5 and D6 This bit is included for testing 2 boards cabled back to back Default is 0 User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 13 CREATED ON OCTOBER 16 2001 13 CABLEINTERFACE The cable interface consists of 32 brdirectional Cable Data lines the ASYNC Transmit Data Line the ASYNC Receive Data line and 2 control Status output lines Transmitter Running and Receiver Running which can employ either differential 1 RS485 422 compatibility or differential pseudo ECL Refer to cable pin out in Figure 4 3 1 The Cable Command Lines are assigned as follows ASYNC Transmit Data Line Connected to Cable Command 1 ASYNC Receive Data Line Connected to Cable Command 2 e Transmitter Running Connected to Cable Command 5 Receiver Running Connected to Cable Command 6 32 I O Lines Connected to Cable Data 0 thru Cable Data 31 1 4 FIFOs The FIFOs on the PC HPDI32A ASYNC are used for buffering the transmit and receive data There a total of eight FIFOs on the board 1 set of 4 FIFOs for transmit and 1 set of 4 FIFOs for receive Each set consists of 32 bits of data and 4 status flags The typical configuration is the 256 board ordering op
104. will be received as a logic 1 When the Alternate Register Select bit BCR D26 is a 17 then reading and writing this register will read and write the Receiver Clock Division Register The Receive Clock Division Register uses the lower 16 bits D15 D0 The upper 16 bits D31 D16 are not used When these bits are all zero the receiver will operate at full speed 1 8 of the main transmit clock frequency The receive bit time is calculated the same as the transmit bit time as follows 1 count 8 clock period User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 12 CREATED ON OCTOBER 16 2001 The Receiver runs off of the same clock as the Transmitter Typically the Transmit clock will be 40 Mhz 25 nsec The Bit times and Bit Rates for several division count values are given in the following table Figure 1 2 3 Count Vs Bits Per Second Receive EL e 200 400 2 6 166 5 8 8 100 555555Kbps 1 2 2 10 Rx Disable Output Status Lines BCR D6 In normal operation the board will drive Cable Command D5 and Cable Command D6 all of the time Cable Command D5 will be driven to a logic high when the transmitter on this board is running Cable Command D6 will be driven to a logic high when the receiver on this board is running When this bit is set to a 1 this board will be pre
105. y Entries minus 1 in FIFO before Requesting Local Bus for Reads COLPAF 1 COLPAE 1 should be lt FIFO Depth of 16 D24 27 DMA Channel 1 Local to PCI Almost Full COLPAF of Full Entries minus 1 in FIFO before requesting PCI bus for Writes D28 31 DMA Channel 1 PCI to Local Almost Empty COPLAE of Empty Entries minus 1 in FIFO before Requesting PCI Bus for Reads D16 19 DMA Channel 1 PCI to Local Almost Full COPLAF of Full Entries minus 1 in FIFO before Requesting Local Bus for Writes User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 64 CREATED ON OCTOBER 16 2001 A 6 MESSAGING QUEUE REGISTERS Table F MESSAGING QUEUE REGISTERS PCI Offset from Access base Value Addr R W Register Name after reset yes A 6 1 Outbound Post List FIFO Interrupt Status Register PCI Offset 0x30 Outbound Post List FIFO Interrupt This bitis set when the Outbound Post List FIFO is not empty This bit is not affected by the interrupt mask bit A 6 2 Outbound Post List FIFO Interrupt Status Register PCI Offset 0x34 D3 Outbound Post List FIFO Interrupt Mask Interrupt is masked when this bit is set D4 31 User Manual for the PCI HPDI32A ASYNC Card Revision NR Manual Revision NR General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 P

the user manual for the HPDI32A-ASYNC

Contents

Download Pdf Manuals

Related Search

Related Contents