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DM6620HR User`s Manual

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1. tpe treten re e ENERO PEE pia ia 6 6 DMA Mask Register rrt ert n P ad 6 6 DMA Mode Registet i ed c D HR Dee HEU MR EE e HE HR ER ee a ER ARES 6 7 Programming DMA Controller iaioe iee E nne Ra a 6 7 Programming the DM6620 for DMA ununsssensesnennensesnennennnnnennennennensenensensensonsensonsorsonsensonsonnonsnnenennnonsonsonn 6 7 Monitoring for DMA Done biie tdt Debe t 6 7 Common DMA Problems uan lidad dederis 6 8 CHAPTER 7 8 7 1 Software Selectable Interrupt Sources nennen nennen 7 3 Software Selectable Interrupt Channel pp 7 4 Advanced Digital Interrupts erise aeo t Heim isn Bern 7 4 Event Mode tects ee A eot C eae gie 7 4 Match Modem ae ae re e tits 7 4 Sampling Digital Lines for Change of State Ne 7 4 Basic Programming For Interrupt Handling 4 7 5 What Is an HL dome eget ned ed neve it 7 5 Interrupt Request Eines es ie ae m in S pe f ee HER 7 5 8259 Programmable Interrupt Controller Ne 7 5 Interrupt Mask Register IMR cut anna kennen 7 5 End of Interrupt EOI Command pp 7 6 What Exactly Happens When an Interrupt Occurs Ne 7 6 Using Interrupts in Your Programs cnrs n E REE a E E E aA EEEE AE a ENEE t E EEEE haa 7 6 Writing an Interrupt Service Routine ISR 02 22 2 1 1 0 000000 000 0000000
2. 7 6 Saving the Startup Interrupt Mask Register IMR and Interrupt 7 7 Restoring the Startup IMR and Interrupt Vector Ne 7 8 Common Interrupt Mistakes eee EO UE REGE RE E DE RI EE Ce E 7 8 CHAPTER 8 TIMER COUNTERS s secures e unse ee kae soe Gaspar or auos 8 1 CHAPTER 9 DIGITAL TO e ecere epe enne ke enero Foro eu eerte eaa estre soo specu s o 9 1 Port 0 Bit Programmable Digital VO esses eene enne netten trennen nne trennen 9 3 Advanced Digital Interrupts Mask and Compare 9 3 Port 1 Port Programmable Digital VO iio 9 3 Resetting the Digital CitCultry ERBE e e 9 3 Strobirig Data into POrt D irre Ro CH ann 9 3 High Speed Digital Input 2 2 odia hg dt D EP RU ca ER LR RE Hee be Deo de 9 3 CHAPTER 10 EXAMPLE PROGRAMS eee eerte seen eerte eee sesto sesta asa 10 1 CELOS e M 10 3 Quick Basi Programs ueniet e OU re n desi 10 3 CHAPTER 11 14 2004000 seta netos conoce asses aea 11 1 Required Equipments zs coded a t D
3. Reserved IRQ1 Source Select 00000 DAC1 FIFO half full 00001 DAC2 FIFO half full 00010 DAC3 FIFO half full 00011 DAC4 FIFO half full 00100 Sample Counter 1 00101 Sample Counter 2 00110 Sample Counter 3 00111 DMA 5 done 01000 DMA 6 done 01001 DMA 7 done 01010 User TC Counter O out 01011 User TC Counter 1 out 01100 User TC Counter 1 out inverted 01101 User TC Counter 2 out 01110 digital interrupt 01111 external interrupt 10000 1111 Reserved DACI FIFO half full an interrupt is generated when the DACI FIFO goes below half full FIFO half full an interrupt is generated when the DAC2 FIFO goes below half full DAC3 FIFO half full an interrupt is generated when the DAC3 FIFO goes below half full DACA FIFO half full an interrupt is generated when the DAC4 FIFO goes below half full Sample Counter 1 an interrupt is generated when sample counter 1 reaches 0 Sample Counter 2 an interrupt is generated when sample counter 2 reaches 0 Sample Counter 3 an interrupt is generated when sample counter 3 reaches 0 DMA 5 done an interrupt is generated when DMA channel 5 is done DMA 6 done an interrupt is generated when DMA channel 6 is done DMA 7 done an interrupt is generated when DMA channel 7 is done User TC Counter 0 out an interrupt is generated when user TC Counter 0 s count reaches 0 User TC Counter 1 out an interrupt is generated when user TC Counter 1
4. Note that the DAC sample counter 8254 must be programmed for Mode 2 opera tion DAC Data Markers The DAC Data Markers are used to send out digital pulses synchronized to the D A output Since each DAC FIFO buffer is 16 bits wide and the D A only uses 12 bits there are 4 bits left over One of these bits is used for the Data Marker This bit location can be filled with data and this data is sent out on the appropriate pins synchro nized to the D A output This is useful for sending out a trigger pulse each time a waveform crosses zero or to send out pulses to trigger A D conversions at the proper time in the D A waveform Each DAC channel has 1 Data Marker bit These outputs can be accessed at the pins on connector CN3 5 8 CHAPTER 6 DATA TRANSFERS USING DMA This chapter explains how data transfers are accomplished using DMA 6 1 6 2 Direct Memory Access DMA transfers data between a peripheral device and PC memory without using the processor as an intermediate Bypassing the processor in this way allows very fast transfer rates All PCs contain the necessary hardware components for accomplishing DMA However software support for DMA is not included as part ofthe BIOS or DOS leaving you with the task of programming the DMA controller yourself With a little care such programming can be successfully and efficiently achieved The following discussion is based on using the DMA controller to get data from memory and write it to a
5. User TC Counter 2 out This option uses the OUT 2 signal from the User Timer Counter External clock CN3 39 This option uses an external signal connected to the board at CN3 39 External Interrupt CN3 19 This option uses an external signal connected to the board at CN3 19 DAC Cycle No Cycle In this mode data is read from the DAC FIFO until it is empty If the D A continues to read from the empty FIFO the data is undetermined Cycle In this mode data is read from the DAC FIFO until it is empty When the empty flag is encountered the FIFO automatically resets the internal pointer to the beginning of the data and repeats This is useful for loading the FIFO with a set of data and repeating it to generate a waveform 5 4 A write to the proper Base Address programs the DAC 12 bit output in the format shown below Output coding is two s complement for bipolar and straight binary for unipolar ranges After the data has been written to the DAC channel an update signal must occur to output the data to the D A If the update selection is software the program must now issue the update command If one of the hardware clocks is being used the program does not need to issue the update command A write also sets the DAC Data Marker outputs t Pi z 2 a ee Bit E El 11 10 u Rem us The following tables list the key digital codes and corresponding output voltages for the D A converters Ideal Output Voltage m
6. 3 m oin teen tete deett aede Ore LEGO IE te bee Ra E eni el cotes Ce eoe ERA 3 3 A 2 2222 E 3 4 Digital EO a Heu tee pq n aere dO AH 3 5 CHAPTER 4 VO MAPPING ice eenccss c eo ecu eo erue to ton to ete raro eL erae oo eee oo ero koe ee nee 4 1 Defining thet T O M3p fe e ti i pie ld af eio ec ir bec Lit of fe 4 3 BAO Board ID Register 2 2 2 22 e ea el eee RN 4 4 BA 2 Program IRQ Source and Channel ee 4 4 BA 4 Program DMA Channel and Source Ne 4 5 BA 6 Read Status Update DACS enisi ier nenese aaea a aa coronar etre rennen rennen enne 4 6 BA 8 Load Sample Counter 1 Select Sample Counter Source RN 4 7 BA 10 Load Sample Counter 2 Select DAC Output Range Ne 4 7 BA 12 Load Sample Counter 3 Select DAC Update Ne 4 8 BATTA Cle rsRegister reae tei niti 4 10 BA 16 Update DACI Output Load DACI FIFO Ne 4 11 BA 18 Update DAC2 Output Load DAC2 FIFO Ne 4 11 BA 20 Update DAC3 Output Load DAC3 FIFO sese nnt ener nnne 4 12 BA 22 Update Output Load FIFO Ne 4 12 BA 24 TC Counter Ol TER E e e pa eee id EIE ARCU 4 13 B 257 TC Counten iate ntt RO 4 13 BA 26 TC Co nter 2 re dre di 4 13 BA 27 Timer Counter Control Word e a ea ee aaa aripii 4 13 BA 28 Digital I O Port 0 Bit Programmable Port
7. 4 9 BA 14 Clear Register 16 bit operation Read A read clears selected circuits on the board depending on the value programmed at this same address as described below Write The value programmed in this register determines which clear enable and reset operations are carried out when a read at this address is executed Setting a bit high clears or enables the defined operation This register s bits are described below eese es o n v T o ouo Clear Board 0 no clear 1 clear Clear DAC1 FIFO 0 no clear Clear IRQ 2 1 clear 0 no clear 1 clear Clear DAC2 FIFO 0 no clear Clear IRQ 1 de clear 22 Clear DAC3 FIFO 0 no clear Clear DMA Done 7 1 clear 0 no clear Clear DAC4 FIFO 1 clear 0 no clear 1 clear Clear DMA Done 6 Reset DAC1 FIFO 0 no clear 1 clear 0 no clear 1 clear Clear DM Doe Reset DAC2 FIFO 0 no clear Al des 0 no clear mi 1 clear Reset DAC4 FIFO Reset DAC3 FIFO 0 no clear 0 no clear 1 clear 1 clear Clear Options Clear Board Clears all of the board registers and initializes the board for operation Clear DACI FIFO Clears all the data from the DACI FIFO setting the empty flag low Clear DAC2 FIFO Clears all the data from the DAC2 FIFO setting the empty flag low Clear DAC3 FIFO Clears all the data from the DAC3 FIFO setting the empty flag low Clear DAC4 FIFO Clears all the data from the DAC4 FI
8. A D FIKXA 9 SIA O JP1 Fig 1 2 User TC Clock Sources Jumpers JP1 TO DAC UPDATE SELECT CONNECTOR CN3 XTAL 8 MHz ER CLK PIN 39 EXT CLK 0 5 GATE PIN 41 4 EXT GATE 0 PIN 42 CLK OUT 0 TIMER COUNTER CLK 1 5 V GATE PIN 43 A EXT GATE 1 PIN 44 OUT 1 TIMER COUNTER 5 V PIN 45 EXT GATE 2 PIN 46 OUT 2 Fig 1 3 User TC Circuit Diagram 1 5 S1 Base Address Factory Setting 300 hex 768 decimal One of the most common causes of failure when you are first trying your module is address contention Some of your computer s I O space is already occupied by internal I O and other peripherals When the module attempts to use I O address locations already used by another device contention results and the board does not work To avoid this problem the DM6620 has an easily accessible DIP switch S1 which lets you select any one of 16 starting addresses in the computer s O Should the factory setting of 300 hex 768 decimal be unsuitable for your system you can select a different base address simply by setting the switches to any one of the values listed in Table 1 2 The table shows the switch settings and their corresponding decimal and hexadecimal in parenthe ses values Make sure that you verify the order of the switch numbers on the switch 1 through 4 before setting them When the switches are pulled forward they are OPEN
9. INTERRUPTS This chapter explains software selectable interrupts digital interrupts and basic interrupt programming techniques 7 1 7 2 The DM6620 has two completely independent interrupt circuits which can generate interrupts on IRQ channels 3 5 9 10 11 12 or 15 By using these two circuits complex data acquisition systems can be config ured Software Selectable Interrupt Sources Each interrupt circuit on the DM6620 has 16 software selectable interrupt sources which can be programmed in bits 0 through 4 and bits 8 through 12 of the Interrupt Register at BA 2 as described and shown below LO IRQ2 Channel IRQ2 Source Select IRQ1 Channel IRQ1 Source Select Select 00000 DAC1 FIFO half full Select 00000 DAC1 FIFO half full 000 disabled 00001 DAC2 FIFO half full 000 disabled 00001 DAC2 FIFO half full 001 IRQ3 00010 DAC3 FIFO half full 001 IRQ3 00010 DAC3 FIFO half full 010 IRQ5 00011 DAC4 FIFO half full 010 IRQ5 00011 DAC4 FIFO half full 011 IRQ9 00100 Sample Counter 1 011 IRQ9 00100 Sample Counter 1 100 IRQ10 00101 Sample Counter 2 100 IRQ10 00101 Sample Counter 2 101 IRQ11 00110 Sample Counter 3 101 IRQ11 00110 Sample Counter 3 110 IRQ12 00111 DMA 5 done 110 IRQ12 00111 DMA 5 done 111 IRQ15 01000 DMA 6 done 111 IRQ15 01000 DMA 6 done 01001 DMA 7 done 01001 DMA 7 done 01010 User TC Counter O out 01010 User TC Counter O out 01011 User TC Counter 1
10. O Status Set Digital Control Program digital control register amp Register Read digital status word digital interrupt enable BA 31 BA Base Address BA 0 Board ID Register 16 bit operation Read A read returns the board identifier Each time you read this address the value returned will be 6620 0 1 1 0 0 1 1 0 0 0 1 0 0 0 0 0 Write Reserved BA 2 Program IRQ Source and Channel 16 bit operation Read Reserved Write This register programs the software selectable interrupt source and channel The IRQ circuitry is driven by an open collector device which is turned off when the IRQ channel is set to disable The IRQ sources are described below er IRQ2 Channel Select 000 disabled 001 IRQ3 010 IRQ5 011 IRQ9 100 IRQ10 101 IRQ11 110 IRQ12 111 IRQ15 IRQ Sources IRQ2 Source Select 00000 DAC1 FIFO half full 00001 DAC2 FIFO half full 00010 DAC3 FIFO half full 00011 DACA FIFO half full 00100 Sample Counter 1 00101 Sample Counter 2 00110 Sample Counter 3 00111 DMA 5 done 01000 DMA 6 done 01001 DMA 7 done 01010 User TC Counter O out 01011 User TC Counter 1 out IRQ1 Channel Select 000 disabled 001 IRQ3 010 IRQ5 011 IRQ9 100 IRQ10 101 IRQ11 110 IRQ12 111 IRQ15 01100 User TC Counter 1 out inverted 01101 User TC Counter 2 out 01110 digital interrupt 01111 external interrupt 10000 1111
11. To program the DMA controller follow these steps Disable DMA on the channel you are using Write the DMA mode register to choose the DMA parameters Write the page offset bits D1 D16 of your buffer Write the number of samples to transfer Write the page register Enable DMA on the channel you are using Du bu No Programming the DM6620 for DMA Once you have set up the DMA controller you must program the DM6620 for DMA The following steps list this procedure 1 Program Conversion and Trigger mode 2 Program the DMA channel at BA 2 3 Issue the start trigger Monitoring for DMA Done There are two ways to monitor for DMA done The easiest is to poll the DMA done bits in the DM6620 status register BA 6 While DMA is in progress the bit is clear 0 When DMA is complete the bit is set 1 The second way to check is to use the DMA done signal to generate an interrupt An interrupt can immediately notify your program that DMA is done and any actions can be taken as needed Common DMA Problems Check to be sure that your buffer does not straddle a page boundary Remember that the value for the number of samples for the DMA controller to transfer is equal to the number of samples 1 If you terminate sampling before the DMA controller has transferred the number of bytes it was pro grammed for be sure to disable DMA by setting the mask bit in the mask register 6 7 6 8 CHAPTER 7
12. buffer data repeat Under normal operation without the cycle bit set data is written into the buffer and the update clock reads data out of the buffer When the buffer is empty the data will be undefined as explained above If you set the cycle bit high the data in the buffer will repeat If you load a data set into the buffer when the update clock reaches the end of the data it will automatically wrap around to the begin ning and start over This is useful for generating waveforms It is important to note that when you are operating in this mode you do not have to fill the complete FIFO buffer before using it You can load the FIFO with any number of samples between and 1024 The board will automatically repeat only the number of samples that are stored in the buffer DMA Transfer Each DAC buffer can be accessed through DMA This allows you to load D A data into a memory buffer and have the DMA controller in the CPU fill the FIFO buffer automatically This feature is useful if the amount of D A data is greater than the 1024 samples that the FIFO buffer will hold A detailed discussion about DMA transfers can be found in chapter 6 Two important things to remember when using DMA with the DAC are to program the DMA controller in the CPU for read operations since you are reading data from memory and sending it out the D A and be sure to issue a Clear DAC FIFO command at BA 14 right before you unmask the DMA channel bit This will ensure pro
13. called the page register The remaining bit for the page D16 is sent to the base address register of the DMA controller along with bits DI through D15 Since the buffer sits on a word boundary bit DO must be zero and is ignored The following diagram shows you to which registers the components of the 20 bit linear address are sent 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 To 8237 base address MSB is To 8237 base address LSB To page register 6 4 The following examples show you how to calculate the linear address and break it into components to be sent to the various registers In Pascal Segment SEG Buffer get segment of buffer Offset OFS Buffer get offset of buffer LinearAddress Segment 16 Offset calculate linear address PageBits LinearAddress DIV 65536 AND SOE determine page corresponding to this linear address and clear least significant bit OffsetBits LinearAddress SHR 2 MOD 65536 shift linear address to ignore DO then extract bits 1 16 In C segment FP_SEG amp Buffer get segment of buffer offset FP OFS amp Buffer get offset of buffer linear_address segment 16 offset calculate linear address pagebits linear address 65536 amp Ox0E determine page corresponding to this linear address and clear least significant bit offset_bits linear_address gt gt 2 65536 shift lin
14. esee enne 4 14 BA 29 Digital I O Port 1 Byte Programmable Port Ne 4 14 BA 30 Read Program Port 0 Direction Mask Compare Registers 4 14 BA 31 Read Digital IRQ Status Program Digital Mode Ne 4 15 Programming the DM Oia e 4 17 Clearing and Setting Bits in a Port nenessessensessesnensesnensensensensensonsensennonnnnsnnnonsonnensonsennnnnnenensensensonerorsonnn 4 17 CHAPTER 5 D A CONVERSIONS 00ss0000s00000000000000200002000020000000000 setas senos seen stesse SR 5 1 1024 Sample Buffer 222 A aci 5 7 DAG Update Enables 5 7 5 7 DMA sao e fielen 5 7 DAC Sample Comte o ld edat 5 7 DAG Data MAKES A epit tp a EA 5 8 CHAPTER 6 DATA TRANSFERS USING 0040 6 1 Choosing a DMA Channel ed eat e 6 3 Allocatins amp DM A eo eb e CEDERE etes te P d etd 6 3 Calculating the Page and Offset of a 6 4 Setting the DMA Page Register soie ERROR HERB OR RR TB ERR TO 6 5 Phe DMA Controller
15. example software to help you verify your module s operation You can also use this program to make sure that your current base address setting does not contend with another device 2 4 CHAPTER 3 HARDWARE DESCRIPTION This chapter describes the features of the DM6620 hardware The major circuits are the D A the timer counters and the digital lines 3 1 3 2 The DM6620 has three major circuits the D A the timer counters and the digital 1 O lines Figure 3 1 shows the block diagram of the module This chapter describes the hardware which makes up the major circuits FIFO 1024 X 16 DAC1 DATA MARKER DAC2 DATA MARKER DAC3 DATA MARKER PC BUS SELECT 1O CONNECTOR ADDRESS ADDRESS DECODE P0 0 PO 7 CONTROL DIGITAL vo 1 0 1 7 INTERRUPT AS VOLTS 215 VOLTS CONVERTER 12 VOLTS 5 VOLTS CONTROL Fig 3 1 DM6620 Block Diagram Digital to Analog Conversion The digital to analog D A circuitry features four independent 12 bit analog output channels with individu ally programmable output ranges of 5 to 5 volts 0 to 5 volts 10 to 10 volts or 0 to 10 volts Each channel has it s own 1024 sample buffer for data storage before being output Data can be continuously written to the buffer producing a non repetitive output waveform or a set of data can be written into the buffer and continuously cycled to p
16. its execution was interrupted Interrupts are very handy for dealing with asynchronous events events that occur at less than regular inter vals Keyboard activity is a good example your computer cannot predict when you might press a key and it would be a waste of processor time for it to do nothing while waiting for a keystroke to occur Thus the interrupt scheme is used and the processor proceeds with other tasks Then when a keystroke does occur the keyboard interrupts the processor and the processor gets the keyboard data places it in memory and then returns to what it was doing before it was interrupted Other common devices that use interrupts are modems disk drives and mice Your DM6620 board can interrupt the processor when a variety of conditions are met such as DMA done timer countdown finished sample counter and external trigger By using these interrupts you can write software that effectively deals with real world events Interrupt Request Lines To allow different peripheral devices to generate interrupts on the same computer the AT bus has 16 differ ent interrupt request IRQ lines A transition from low to high on one of these lines generates an interrupt request which is handled by one of the AT s two interrupt control chips One chip handles IRQO through IRQ7 and the other chip handles IRQ8 through 15 The controller which handles IRQ8 IRQIS is chained to the first controller through the IRQ2 line W
17. out 01011 User TC Counter 1 out 01100 User TC Counter 1 out inverted 01100 User TC Counter 1 out inverted 01101 User TC Counter 2 out 01101 User TC Counter 2 out 01110 digital interrupt 01110 digital interrupt 01111 external interrupt 01111 external interrupt 10000 1111 Reserved 10000 1111 Reserved IRQ Sources DACI FIFO half full an interrupt is generated when the DACI FIFO goes below half full DAC2 FIFO half full an interrupt is generated when the DAC2 FIFO goes below half full DAC3 FIFO half full an interrupt is generated when the DAC3 FIFO goes below half full DAC4 FIFO half full an interrupt is generated when the DAC4 FIFO goes below half full Sample Counter 1 an interrupt is generated when sample counter 1 reaches 0 Sample Counter 2 an interrupt is generated when sample counter 2 reaches 0 Sample Counter 3 an interrupt is generated when sample counter 3 reaches 0 DMA 5 done an interrupt is generated when DMA channel 5 is done DMA 6 done an interrupt is generated when DMA channel 6 is done DMA 7 done an interrupt is generated when DMA channel 7 is done User TC Counter 0 out an interrupt is generated when user TC Counter 0 s count reaches 0 User TC Counter out an interrupt is generated when user TC Counter 175 count reaches 0 User TC Counter 1 out inverted an interrupt is generated when user TC Counter 178 count reaches 0 useful for frequency counting User T
18. selecting match mode BEFORE writing the Compare Register value at this address In the event mode where an interrupt is generated when any Port 0 bit changes its current state the value which caused the interrupt is latched at this register and can be read from it Bits can be selectively masked using the Mask Register so a change of state is ignored on these lines in the event mode BA 31 Read Digital IRQ Status Program Digital Mode 8 bit Operation Read Write Digital IRQ Strobe Status A read shows you whether a digital interrupt has occurred bit 6 whether a strobe has occurred bit 7 when using the strobe input as described in Chapter 7 and lets you review the states of bits 0 through 5 in this register If bit 6 is high then a digital interrupt has taken place If bit 7 is high a strobe has been issued Strobe Status 0 no strobe BA 28 Port 0 1 strobe Register Select Digital IRQ Status Port 1 Direction 0 no digital interrupt 1 digital interrupt Digital IRQ Mode Digital IRQ Enable Digital Sample Clock Select Digital Mode Register Reserved BA 28 Port 0 Register Select Digital Sample Clock Select 00 clear mode 0 8 MHz system clock 01 Direction Register 1 programmable clock 10 Mask Register 11 Compare Register Digital IRQ Enable Port 1 Direction 0 disabled 0 input 1 enabled 1 output Digital IRQ Mode O event mode 1 match mode 4 15 Bits 0 and 1 Sele
19. sure that its location will not change while DMA is in progress The following code examples show how to allocate buffers for use with DMA In Pascal Var Buffer Array 1 10000 of Byte static allocation or Var Buffer Byte dynamic allocation Buffer GetMem 10000 In C char Buffer 100001 static allocation or char Buffer dynamic allocation Buffer calloc 10000 0 6 3 Calculating the Page and Offset of a Buffer Once you have a buffer into which to place your data you must inform the 8237 DMA controller of the location of this buffer This is a little more complex than it sounds because the DMA controller uses a page offset memory scheme while you are probably used to thinking about your computer s memory in terms of a segment offset scheme Paged memory is simply memory that occupies contiguous non overlapping blocks of memory with each block being 64K one page in length The first page page 0 starts at the first byte of memory the second page page 1 starts at byte 65536 the third page page 2 at byte 131072 and so on A computer with 640K of memory has 10 pages of memory The DMA controller can write to or read from only one page without being reprogrammed This means that the DMA controller has access to only 64K of memory at a time If you program it to use page 3 it cannot use any other page until you reprogram it to do so When DMA is started the DMA controller is pro
20. the DAC4 FIFO is not full 8254 Timer Select Sample counter Selects the first 8254 chip which contains the 3 sample counters User Timer Counter Selects the second 8254 which contains the 3 User Timer Counters 4 5 BA 6 Read Status Update All DACs 16 bit operation Read A read returns the status bits defined below eser en s T o DAC1 FIFO Empty Flag Digital IRQ 0 FIFO empty 0 no interrupt 1 FIFO not empty 1 interrupt DAC1 FIFO Half Full Flag DMA 7 Done 0 FIFO half full 0 DMA not done 1 FIFO not half full 1 DMA done DAC1 FIFO Full Flag DMA 6 Done 0 FIFO full 0 DMA not done 1 FIFO not full 1 DMA done DMA 5 Done DAC2 FIFO Empty Flag 0 FIFO empty 0 DMA not done 2 S Bile dong 1 FIFO not empty en Flag DAC2 FIFO Half Full Flag LEO u Cu 0 FIFO half full not Tu 1 FIFO not half full DAC4 FIFO Half Full Flag DAC2 FIFO Full Flag 0 FIFO half full 0 FIFO full 1 FIFO not half full 1 FIFO not full DACA FIFO Empty Flag 0 FIFO empty 1 FIFO not empty DAC3 FIFO Full Flag 0 FIFO full 1 FIFO not full DAC3 FIFO Half Full Flag 0 FIFO half full 1 FIFO not half full Bit 0 Goes high when the DACI FIFO is not empty Bit 1 Goes low when the DACI FIFO is more than half full Bit 2 Goes low when the DACI FIFO is full Bit 3 Goes high when the DAC2 FIFO is not empty Bit 4 Goes low when the DAC2 FI
21. 0 Send EOI command to 8259B if using IRQ8 Jos In Pascal Procedure ISR Interrupt begin Your code goes here Do not use any DOS functions Port 20 20 Send EOI command to 8259A for all IROs Port SAO 20 Send EOI command to 8259B if using IRQ8 T5 1 end Saving the Startup Interrupt Mask Register IMR and Interrupt Vector The next step after writing the ISR is to save the startup state of the interrupt mask register and the interrupt vector that you will be using The IMR for IRQO IRQ7 is located at I O port 21H the IMR for 8 15 is located at I O port AIH The interrupt vector you will be using is located in the interrupt vector table which is simply an array of 256 four byte pointers and is located in the first 1024 bytes of memory Segment 0 Offset 0 You can read this value directly but it is a better practice to use DOS function 35H get interrupt vector Most C and Pascal compilers provide a library routine for reading the value of a vector The vectors for IRQO IRQ7 are vectors 8 through 15 where IRQO uses vector 8 IRQ1 uses vector 9 and so on The vectors for IRQ8 IRQ15 are vectors 70H through 77H where IRQ8 uses vector 70H IRQ9 uses vector 71H and so on Thus if the DM6420 will be using IRQ15 you should save the value of interrupt vector 77H 7 7 Before you install your ISR temporarily mask out the IRQ you will be using This prevents the IRQ from requesti
22. 254 timer counters must be programmed in 8 bit operations High level languages such as Pascal C and C make it very easy to read write these ports The table below shows you how to read from and write to 1 O ports in Turbo C and Turbo Pascal Read 8 Bits Write 8 Bits Read 16 Bits Write16 Bits Turbo Pascal Data Port Address Port Address Data Data PortW Address PortW Address Data In addition to being able to read write the 1 O ports on the DM6620 you must be able to perform a variety of operations that you might not normally use in your programming The table below shows you some of the operators discussed in this section with an example of how each is used with Pascal and C C 96 amp a b c a b c a b amp c a b c Pascal MOD DIV AND OR a b MOD a b DIVc a b ANDC b ORC Many compilers have functions that can read write either 8 or 16 bits from to an I O port For example Turbo Pascal uses Port for 8 bit port operations and PortW for 16 bits Turbo C uses inportb for an 8 bit read of a port and inport for a 16 bit read Be sure to use the correct function for 8 and 16 bit operations with the 6620 Clearing and Setting Bits in a Port When you clear or set one or more bits in a port you must be careful that you do not change the status of the other bits You can preserve the status of all bits you do not wish to change by proper use of the AND and OR binary operators Using AND and OR single or multiple bit
23. 8 LI H 20010000 0000000 0000011000008 ad c rH Hina 010 08 r HI e LI e CAU Fig 1 1 Module Layout Showing Factory Configured Settings 1 3 JP1 User TC Clock Source Select Factory Settings Clk 0 XTAL Clk 1 0 Clk 2 OT1 This header connector shown in Figure 1 2 lets you select the clock sources for User TC Counters 0 1 and 2 the 16 bit timer counters available for user functions Figure 1 3 shows a block diagram of the User TC circuitry to help you in making these connections The clock source for Counter 0 is selected by placing a jumper on one of the two rightmost pairs of pins on the header OSC or ECK Osc is the on board 8 MHz clock and ECK is an external pacer clock which can be connected through I O connector CN3 pin 39 The next three pins 0 OSC and ECK set the clock source for timer counter Counter 1 OTO is the output of Counter 0 OSC is the on board 8 MHz clock and ECK is an external pacer clock which can be connected through I O connector CN3 pin 39 The last three pins OT1 OSC and ECK set the clock source for timer counter Counter 2 is the output of Counter 1 OSC is the on board 8 MHz clock and ECK is an external pacer clock which can be connected through I O connector CN3 pin 39 Counters 0 and 2 are factory set as a 48 bit cascaded counter clocked by the 8 MHz system clock mo o imoo m Qo O
24. C Counter 2 out an interrupt is generated when user TC Counter 2 s count reaches 0 Digital interrupt an interrupt is generated when an advanced digital interrupt occurs External interrupt an interrupt is generated when the external interrupt line is pulsed CN3 19 7 3 Software Selectable Interrupt Channel Each interrupt circuit on the DM6620 has 7 software selectable interrupt channels which can be programmed in bits 5 through 7 and bits 13 through 15 of the Interrupt Register at BA 2 The interrupt output is driven by an open collector device which is turned off when the IRQ channel is set to disable At power up or reset this register is set to all zero s Advanced Digital Interrupts The bit programmable digital I O circuitry supports two Advanced Digital Interrupt modes event mode or match mode These modes are used to monitor input lines for state changes The mode is selected at BA 31 bit 3 and enabled at BA 31 bit 4 Event Mode When enabled this mode samples the Port 0 input lines at a specified clock rate using the 8 MHz system clock or a programmable clock in User TC Counter 1 looking for a change in state in any one of the eight bits When a change of state occurs an interrupt is generated and the input pattern is latched into the Compare Regis ter You can read the contents of this register at BA 30 to see which bit caused the interrupt to occur Bits can be masked and their state changes ignored by pro
25. DIGITAL GND PIN 1 DIGITAL GND 02 DIGITAL GND 7 23 e 1 7 P0 6 25 P1 6 5 7 8 P1 5 P0 4 P1 4 P0 3 61 83 P1 3 2 83 Ga P1 2 P0 1 85 86 P1 1 P0 0 67 G8 P1 0 EXT CLK DIGITAL GND EXT GATE 0 CLK OUT 0 EXT GATE 1 CLK OUT 1 NOTE On the DM6620 12 volts at pin 47 and 12 volts at pin 49 are available only if supplied by the computer bus CN3 Mating Connector Part Numbers Manufacturer Part Number 1 746094 0 3425 7650 B 4 C 1 APPENDIX C COMPONENT DATA SHEETS Intel 82C54 Programmable Interval Timer Data Sheet Reprint APPENDIXD WARRANTY AND RETURN POLICY Return Policy If you wish to return a product to the factory for service please follow this procedure Read the Limited Warranty to familiarize yourself with our warranty policy Contact the factory for a Return Merchandise Authorization RMA number Please have the following available Complete board name Board serial number A detailed description ofthe board s behavior List the name of a contact person familiar with technical details of the problem or situation along with their phone and fax numbers address and e mail address if available Listyourshipping address Indicate the shipping method you would like used to return the product to you We will not ship by next day service without your pre approval Carefully package the product using proper anti static packaging Write the RMA number i
26. DM6620HR User s Manual TIGO RTD Embedded Technologies Inc Real Time Devices Accessing the Analog World amp BDM 610010008 Rev A DM6620HR User s Manual RTD Embedded Technologies INC 103 Innovation Blvd State College PA 16803 0906 Phone 1 814 234 8087 FAX 1 814 234 5218 E mail sales rtd com techsupport rtd com web site http www rtd com Revision History Rev A New manual naming method Published by RTD Embedded Technologies Inc 103 Innovation Blvd State College PA 16803 0906 Copyright 1999 2002 2003 by RTD Embedded Technologies Inc All rights reserved Printed in U S A The RTD Logo is a registered trademark of RTD Embedded Technologies cpuModule and utilityModule are trademarks ofRTD Embedded Technologies PhoenixPICO and PheonixPICO BIOS are trademarks of Phoenix Technologies Ltd PS 2 PC XT PC AT and IBM are trademarks of International Business Machines Inc MS DOS Windows Windows 95 Windows 98 and Windows NT are trademarks of Microsoft Corp PC 104 is a registered trademark of PC 104 Consortium All other trademarks appearing in this document are the property of their respective owners Table of Contents 2 940050 1 1 Digital to Analog Conversion esses nennen EES i 3 8254 Ditne
27. FO setting the empty flag low Reset DACI FIFO Resets the internal FIFO pointer to the first data location does not erase any data Reset DAC2 FIFO Resets the internal FIFO pointer to the first data location does not erase any data Reset DAC3 FIFO Resets the internal FIFO pointer to the first data location does not erase any data Reset DACA FIFO Resets the internal FIFO pointer to the first data location does not erase any data Clear DMA Done 5 Clears the DMA done flag for channel 5 Clear DMA Done 6 Clears the DMA done flag for channel 6 Clear DMA Done 7 Clears the DMA done flag for channel 7 Clear IRQ 1 Clears the interrupt 1 circuitry Clear IRQ 2 Clears the interrupt 2 circuitry 4 10 For example if you want to clear the DACI FIFO and the DAC3 FIFO you would write a 10 to this address to set bits 1 and 3 high followed by a read to carry out the clear operation Clear FIFO and DMA Done Flag value written 10 o o v 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 16 Update DACI Output Load DACI FIFO 16 bit operation Read A read provides a software trigger to update the DACI output This command will update only the DACI output as opposed to the update all command at BA 6 Write A write to this address is used to load data into the DAC1 FIFO The word sent to this address contains the DAC data in the upper 12 bits and the Data Marker in the lowest bit In unipol
28. FO is more than half full Bit 5 Goes low when the DAC2 FIFO is full Bit 6 Goes high when the DAC3 FIFO is not empty Bit 7 Goes low when the DAC3 FIFO is more than half full Bit 8 Goes low when the DAC3 FIFO is full Bit 9 Goes high when the DACA FIFO is not empty Bit 10 Goes low when the DACA FIFO is more than half full Bit 11 Goes low when the DAC4 FIFO is full Bit 12 Goes high when a DMA transfer is completed on channel 5 Bit 13 Goes high when a DMA transfer is completed on channel 6 Bit 14 Goes high when a DMA transfer is completed on channel 7 Bit 15 Goes high when an Advanced Digital Interrupt occurs from the digital I O chip DAC3 FIFO Empty Flag 0 FIFO empty 1 FIFO not empty Write A write to this address is used to update all of the D A outputs simultaneously with a software command The data written is irrelevant To use this update method it must be selected at BA 12 4 6 8 Load Sample Counter 1 Select Sample Counter Source 16 bit operation Read A read provides a software trigger so that sample counter 1 can be loaded with the correct value This software correction is used as an easy means to compensate for the operating structure of the 8254 Two pulses of the counter are required to actually load the desired count and prepare the counter to count down correctly this can be looked at as the initialization procedure for the sample counter A
29. IRQ you are using This enables interrupts on the IRQ Restoring the Startup IMR and Interrupt Vector Before exiting your program you must restore the interrupt mask register and interrupt vectors to the state they were in before your program started To restore the IMR write the value that was saved when your program started to I O port 21H for IRQO IRQ7 or I O port AIH for IRQ8 IRQ15 Restore the interrupt vector that was saved at startup with either DOS function 25H set interrupt vector or use the library routine supplied with your compiler Performing these two steps will guarantee that the interrupt status of your computer is the same after running your program as it was before your program started running Common Interrupt Mistakes Remember that hardware interrupts are numbered 8 through 15 for IRQO IRQ7 and 70H through 77H for IRQ8 IRQIS The most common mistake when writing an ISR is forgetting to issue the EOI command to the appropriate 8259 interrupt controller before exiting the ISR Remember to clear the appropriate IRQ circuit on the DM6620 at BA 14 7 8 CHAPTER 8 TIMER COUNTERS This chapter explains the two 8254 timer counter circuits on the DM6620 8 1 8 2 Two 8254 programmable interval timers provide six 16 bit 8 MHz timer counters to support a wide range of timing and counting functions The 8254 at U9 is the Sample Counter TC All three of these 16 bit timer counters Counter 0 Counter 1 a
30. R WARRANTIES AREEX PRESSED OR IMPLIED INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF MER CHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AND RTD Embedded Technologies EXPRESSLY DISCLAIMS ALL WARRANTIES NOT STATED HEREIN ALLIMPLIED WARRANTIES INCLUDING IMPLIED WARRANTIES FOR MECHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE LIMITED TO THE DURATION OF THIS WARRANTY IN THE EVENT THE PRODUCT IS NOTFREEFROM DEFECTS AS WARRANTED ABOVE THE PURCHASER S SOLE REMEDY SHALLBE REPAIROR REPLACEMENT AS PROVIDED ABOVE UNDERNO CIRCUMSTANCES WILL RTD Embed ded Technologies BELIABLE TO THE PURCHASER OR ANY USER FOR ANY DAMAGES INCLUDING ANY INCIDENTAL OR CONSEQUENTIAL DAMAGES EXPENSES LOST PROFITS LOST SAVINGS OR OTHER DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PRODUCT SOME STATES DO NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR CONSE QUENTIAL DAMAGES FOR CONSUMER PRODUCTS AND SOME STATES DO NOT ALLOW LIMITA TIONS ON HOW LONG AN IMPLIED WARRANTY LASTS SO THE ABOVE LIMITATIONS OR EXCLU SIONS MAY NOT APPLY TO YOU THIS WARRANTY GIVES YOU SPECIFIC LEGAL RIGHTS AND YOU MAY ALSOHAVE OTHER RIGHTS WHICH VARY FROM STATE TOSTATE D3 RTD Embedded Technologies Inc 103 Innovation Blvd State College PA 16803 0906 USA Our website www rtd com DM6620 User Settings
31. all the module follow the procedures described in the computer manual and the steps below 1 Turn OFF the power to your system 2 Touch a metal rack to discharge any static buildup and then remove the module from its antistatic bag 3 Select the appropriate standoffs for your application to secure the module when you install it in your system 4 Holding the module by its edges orient it so that the bus connector s pin 1 lines up with pin 1 of the expansion connector onto which you are installing the module 5 After carefully positioning the module so that the pins are lined up and resting on the expansion connector gently and evenly press down on the module until it is secured on the connector NOTE Do not force the module onto the connector If the module does not readily press into place remove it and try again Wiggling the module or exerting too much pressure can result in damage to the DM6420 or to the mating module 6 After the module is installed connect the cable to I O connector CN3 on the module When making this connection note that there is no keying to guide you in orientation You must make sure that pin 1 of the cable is connected to pin 1 of CN3 pin is marked on the module with a small square For twisted pair cables pin 1 is the dark brown wire for standard single wire cables pin 1 is the red wire 7 Make sure all connections are secure External I O Connections Figure 2 1 shows the DM6620 s CN3 I O co
32. ar modes the D A data is straight binary In bipolar modes the D A data is 2 s complement The bit pattern is described below p 2 p 2 a 2 p p E 1 ES i 11 ne LSB BA 18 Update DAC2 Output Load DAC2 FIFO 16 bit operation Read A read provides a software trigger to update the DAC2 output This command will update only the DAC2 output as opposed to the update all command at BA 6 Write A write to this address is used to load data into the DAC2 FIFO The word sent to this address contains the DAC2 data in the upper 12 bits and the Data Marker in the lowest bit In uni polar modes the D A data is straight binary In bi polar modes the D A data is 2 s complement The bit pattern is described below EIEIESEIENEHEIEIEIEIEIEIEIENEEN Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit al 11 7 6 5 4 3 e 20 Update DAC3 Output Load DAC3 FIFO 16 bit operation Read A read provides a software trigger to update the DAC3 output This command will update only the DAC3 output as opposed to the update all command at BA 6 Write A write to this address is used to load data into the DAC3 FIFO The word sent to this address contains the DAC3 data in the upper 12 bits and the Data Marker in the lowest bit In unipolar modes the D A data is straight binary In bipolar modes the D A data is 2 s complement The bit pattern is described below Bit p z T E 11 Data Marker S 22 Updat
33. at BA 6 Any samples that are written to the FIFO after it is full will be ignored You can write up to 1024 samples to the buffer before it is full Each update pulse either software or from one of the clocks will remove a sample from the buffer and send it out the D A Each read after the FIFO buffer is empty will send undetermined data out the D A At power up or reset the D A outputs are set to 0 volts Before loading data into the sample buffer it is best to clear the buffer by writing and reading the proper bits at BA 14 When you issue the Clear DAC FIFO command all data in the buffer is erased If you issue the Reset DAC FIFO command the data in the buffer is not erased however the address pointer is set back to the beginning of the buffer This is useful when you are generating waveforms and stop the updating in the middle of a cycle DAC Update Enables These enable bits located in the register at BA 10 are used to enable and disable updating of the D A outputs When these bits are low disabled the update signal will have no effect on the output This is useful when connecting external signals or using clocks to update the D A outputs Any clock pulses received by the board while the update is disabled will be ignored Updating will occur on the first clock pulse after the enable bit is set high NOTE You must enable the update bit even when the update signal is software DAC Cycle Bit The cycle bit is used to make the
34. be set do not have to be consecutive Example Set bits 3 5 and 7 in a port Read in the current value of the port OR it with 168 168 23 2 27 and then write the resulting value back to the port In assembly language this is programmed as mov dx PortAddress in al dx or al 168 out dx al Often assigning a range of bits is a mixture of setting and clearing operations You can set or clear each bit individually or use a faster method of first clearing all the bits in the range then setting only those bits that must be set using the method shown above for setting multiple bits in a port The following example shows how this two step operation is done Example Assign bits 3 4 and 5 in a port to 101 bits 3 and 5 set bit 4 cleared First read in the port and clear bits 3 4 and 5 by ANDing them with 199 Then set bits 3 and 5 by ORing them with 40 and finally write the resulting value back to the port In C this is programmed as v inportb port_address v v amp 199 40 outportb port_address A final note Don t be intimidated by the binary operators AND and OR and try to use operators for which you have a better intuition For instance if you are tempted to use addition and subtraction to set and clear bits in place ofthe methods shown above DON T Addition and subtraction may seem logical but they will not work if you try to clear a bit that is already clear or set a bit that is already
35. ck CN3 39 110 External Interrupt CN3 19 111 reserved DAC2 Update Select 000 Software 001 Software update all 010 User TC Counter O out 011 User TC Counter 1 out 100 User TC Counter 2 out 101 External clock CN3 39 110 External Interrupt CN3 19 111 reserved Software This option uses the individual software update commands for each DAC read at BA 16 to BA 22 Software update all This option uses the software update command to update all the DAC outputs simulta neously write at BA 6 User TC Counter 0 out This option uses the OUT 0 signal from the User Timer Counter User TC Counter 1 out This option uses the OUT 1 signal from the User Timer Counter User TC Counter 2 out This option uses the OUT 2 signal from the User Timer Counter External clock CN3 39 This option uses an external signal connected to the board at CN3 39 External Interrupt CN3 19 This option uses an external signal connected to the board at CN3 19 DAC Cycle No Cycle In this mode data is read from the DAC FIFO until it is empty If the D A continues to read from the empty FIFO the data is undetermined Cycle In this mode data is read from the DAC FIFO until it is empty When the empty flag is encountered the FIFO automatically resets the internal pointer to the beginning of the data and repeats This is useful for loading the FIFO with a set of data and repeating it to generate a waveform
36. ct the clear mode initiated by a read write operation at BA 28 or the Port 0 control register you talk to at BA 28 Direction Mask or Compare Register Bit 2 Sets the direction of the Port 1 digital lines Bit 3 Selects the digital interrupt mode event any Port 0 bit changes state or match Port 0 lines match the value programmed into the Compare Register at BA 28 Bit 4 Disables enables digital interrupts Bit 5 Sets the clock rate at which the digital lines are sampled when in a digital interrupt mode Available clock sources are the 8 MHz system clock and the output of User TC Counter 1 16 bit programmable clock When a digital input line changes state it must stay at the new state for two edges of the clock pulse 62 5 nanoseconds when using the 8 MHz clock before it is recognized and before an interrupt can be generated This feature eliminates noise glitches that can cause a false state change on an input line and generate an unwanted interrupt This feature is detailed in Chapter 7 Bit 6 Read only digital IRQ status Bit 7 Reserved 4 16 Programming the DM6620 This section gives you some general information about programming and the DM6620 board The DM6620 is programmed by writing to and reading from the correct I O port locations on the board These I O ports were defined in the previous section Because the DM6620 is AT bus compatible most operations are done in a 16 bit word format The 8
37. d as an easy means to compensate for the operating structure of the 8254 Two pulses of the counter are required to actually load the desired count and prepare the counter to count down correctly this can be looked at as the initialization procedure for the sample counter A pulse is sent to sample counter 2 Sample Counter Counter 1 each time you read this address Without this correction the initial count sequence will be off by two pulses Once the counter is properly loaded and starts any subsequent countdowns of this count will be accurate Note that sample counter 2 must be programmed for Mode 2 operation 4 7 Write A write to this address is used to select the output range for each of the D A converters The different output ranges are described below At power up or reset this register is reset and all of the outputs will go to zero volts EIGIEIEIGIEHEIEIEIEIEIEIEIEIEITN DAC4 Update DAC1 Update DAC3 Output DAC1 Output Enable Enable Range Range 0 disabled 0 disabled 00 0 to 5 volts 00 0 to 5 volts 1 enabled 1 enabled 01 0 to 10 volts 01 0 to 10 volts 10 5 volts 10 5 volts DAC2 Update 11 10 volts 11 10 volts Enable DAC4 Output DAC2 Output 0 disabled Range Range 1 enabled 0 to 5 volts 00 0 to 5 volts 01 to 10 volts 01 to 10 volts 10 5 volts 10 5 volts DAC3 Update 11 10 volts 11 10 volts Enable 0 disabled 1 enabled DAC Output Ranges 0
38. d the digital chip write When these bits are set to any other value one of the three Port 0 registers is addressed Direction Register BA 31 bits 1 and 0 01 For all bits 1 output P0 7 P0 6 P0 5 P0 4 P0 3 0 2 PO 1 PO 0 This register programs the direction input or output of each bit at Port 0 Mask Register BA 31 bits 1 and 0 10 For all bits 0 bit enabled D7 D5 D3 D1 1 bit masked P0 7 P0 6 P0 5 P0 4 P0 2 P0 1 PO 0 4 14 In the Advanced Digital Interrupt modes this register is used to mask out specific bits when monitoring the bit pattern present at Port 0 for interrupt generation In normal operation where the Advanced Digital Interrupt feature is not being used any bit which is masked by writing a 1 to that bit will not change state regardless of the digital data written to Port 0 For example if you set the state of bit 0 low and then mask this bit the state will remain low regardless of what you output at Port 0 an output of 1 will not change the bit s state until the bit is un masked Compare Register BA 31 bits 1 and 0 11 This register is used for the Advanced Digital Interrupt modes In the match mode where an interrupt is generated when the Port 0 bits match a loaded value this register is used to load the bit pattern to be matched at Port 0 Bits can be selectively masked so that they are ignored when making a match NOTE Make sure that bit 3 at BA 30 is set to 1
39. detailed in the 8254 Data Sheet reprinted from Intel in Appendix C The sample counters should be programmed for mode 2 operation I CLK SAMPLE COUNTER 1 SOURCE COUNTER GATE 5 V OUT SAMPLE COUNT 1 CLK SAMPLE COUNTER 2 SOURCE SOUNFER GATE 5 OUT SAMPLE COUNT 2 1 l 1 l 1 SAMPLE COUNTER 3 SOURCE COUNTER GATE 5 V OUT SAMPLE COUNT 3 Fig 3 2 Sample Counter TC Circuit Block Diagram 3 4 TIMER COUNTER TIMER COUNTER 1 TIMER COUNTER 2 Digital I O CLK GATE OUT CLK TO DAC UPDATE SELECT XTAL 8 MHz 5 V 45V 45V Fig 3 3 User TC Circuit Block Diagram CONNECTOR CN3 PIN 39 PIN 41 PIN 42 PIN 43 PIN 44 PIN 45 PIN 46 amp EXT CLK Y EXT GATE 0 CLK OUT 0 EXT GATE 1 CLK OUT 1 O y EXT GATE 2 y CLK OUT 2 The 16 digital I O lines can be used to transfer data between the computer and external devices Eight lines are bit programmable and eight lines are byte or port programmable Port 0 provides eight bit programmable lines which can be independently set for input or output Port 0 supports RTD s two Advanced Digital Interrupt modes An interrupt can be generated when the lines match a programmed value or when any bit changes its current state A Mask Register lets you monitor selected lines for interrupt genera
40. e 000 Software DAC2 Cycle 0 no cycle 1 cycle DAC3 Update Select 001 Software update all 010 User TC Counter O out DACA Update Select 011 User TC Counter 1 out 000 Software 001 Software update all 010 User TC Counter 0 out 011 User TC Counter 1 out 100 User TC Counter 2 out 101 External clock CN3 39 110 External Interrupt CN3 19 111 reserved 111 reserved DAC Update Signals 100 User TC Counter 2 out 101 External clock CN3 39 110 External Interrupt CN3 19 DAC1 Cycle 0 no cycle DAC1 Update Select 1 cycle 000 Software 001 Software update all 010 User TC Counter 0 out 011 User TC Counter 1 out 100 User TC Counter 2 out 101 External clock CN3 39 110 External Interrupt CN3 19 111 reserved DAC2 Update Select 000 Software 001 Software update all 010 User TC Counter 0 out 011 User TC Counter 1 out 100 User TC Counter 2 out 101 External clock CN3 39 110 External Interrupt CN3 19 111 reserved Software This option uses the individual software update commands for each DAC read at BA 16 to BA 22 Software update all This option uses the software update command to update all the DAC outputs simulta neously write at BA 6 User TC Counter 0 out This option uses the OUT 0 signal from the User Timer Counter User TC Counter 1 out This option uses the OUT 1 signal from the User Timer Counter
41. e The output is initially high When the initial count expires the output goes low for one clock pulse and then goes high again Counting is triggered by writing the initial count Mode 5 Hardware Triggered Strobe Retriggerable The output is initially high Counting is triggered by the rising edge of the gate input When the initial count has expired the output goes low for one clock pulse and then goes high again 8 4 CHAPTER 9 DIGITAL VO This chapter explains the bit programmable and port program mable digital I O circuitry on the DM6620 9 1 9 2 The DM6620 has 16 buffered TTL CMOS digital I O lines available for digital control applications These lines are grouped in two 8 bit ports The eight bits in Port 0 can be independently programmed as input or output Port 1 can be programmed as an 8 bit input or output port Port 0 Bit Programmable Digital I O The eight Port 0 digital lines are individually set for input or output by writing to the Port 0 Direction Register at BA 30 The input lines are read and the output lines are written at BA 28 Direction Register For all bits 1 output 7 P0 6 P0 5 P0 4 P0 3 PO 2 PO 1 Advanced Digital Interrupts Mask and Compare Registers The Port 0 bits support two Advanced Digital Interrupt modes An interrupt can be generated when the data read at the port matches the value loaded into the Compare Register This is called a match interrupt Or an int
42. e DAC4 Output Load DAC4 FIFO 16 bit operation Read A read provides a software trigger to update the DAC4 output This command will update only the DAC4 output as opposed to the update all command at BA 6 Write A write to this address is used to load data into the DAC4 FIFO The word sent to this address contains the DAC4 data in the upper 12 bits and the Data Marker in the lowest bit In unipolar modes the D A data is straight binary In bipolar modes the D A data is 2 s complement The bit pattern is described below 2 P N Bit Ji a p 2 an 11 am Data Marker MS 4 12 BA 24 TC Counter 0 8 bit Operation Read Write A write loads the first counter in one of the two timer counters on the board with a new 16 bit value in two 8 bit steps LSB followed by MSB The counter must be loaded in two 8 bit steps Counting begins as soon as the count is loaded The timer counter being loaded is selected by writing to BA 4 bit 15 A read shows the count in the counter BA 25 TC Counter 1 8 bit Operation Read Write A write loads the second counter in one of the two timer counters on the board with a new 16 bit value in two 8 bit steps LSB followed by MSB The counter must be loaded in two 8 bit steps Counting begins as soon as the count is loaded The timer counter being loaded is selected by writing to BA 4 bit 15 A read shows the count in the counter BA 26 TC Counter 2 8 bit Operation Read Wr
43. ear address to ignore DO then extract bits D1 D16 Beware There is one big catch when using page based addresses The 8237 DMA controller cannot read properly from a buffer that straddles a page boundary A buffer straddles a page boundary if one part of the buffer resides in one page of memory while another part resides in the following page The DMA controller cannot properly read from such a buffer because the DMA controller can only read from one page without reprogramming When it reaches the end of the current page it does not start reading from the next page Instead it starts reading back at the first byte of the current page This can be disastrous if the beginning of the page does not correspond to your buffer More often than not this location is being used by the code portion of your pro gram or the operating system and reading data from it will almost always causes erratic behavior You must check to see if your buffer straddles a page boundary and if it does take action to prevent the DMA controller from trying to read from the portion that continues on the next page You can reduce the size of the buffer or try to reposition the buffer However this can be difficult when using large static data structures and often the only solution is to use dynamically allocated memory Setting the DMA Page Register Oddly enough you do not inform the DMA controller directly of the page to be used Instead you put the page to be u
44. eiode fi 11 3 BAR A Iain enema 11 4 APPENDIX A DM6620 SPECIFICATIONS 00 200220000000000000000000220002200000000000000 se toss tasse tens sinus A 1 APPENDIX B CN3 CONNECTOR PIN ASSIGNMENTS 00 eese ette etant B 1 APPENDIX C COMPONENT DATA SHEETS 2200000000000000000000002200020000200000000000000 0000000000000 C 1 APPENDIX D WARRANTY 2200sssoossesnnsssnnssnonnssnnnssnnssssnnsnnnnnsnnnnssnnnssnnnssnnnsnsnnssnnsnsnnsnssnnnssnnnsnannne D 1 iii 1 1 1 2 1 3 1 5 2 1 3 1 3 2 3 3 7 1 8 1 8 2 11 1 List of Illustrations Module Layout Showing Factory Configured Settings Ne 1 3 User TC Clock Sources Jumpers JP1 r a e a E a araa 1 4 User TC Circuit DIAM 1 4 Base Address li 1 6 Ports 0 and 1 Pull up Pull down Resistor Connections pe 1 7 Connector Pin Assignments iii A ds 2 4 0 6620 4 22 eld s ebur 3 3 Sample Counter TC Circuit Block Diagram essere 3 4 User TC Circuit Block Diagram e ERR HENRI ERREUR Ee nn 3 5 Digital Interrupt Timing Diagram seseeeeeeeeeeeenennennennennenneneenne nennen eoar eit aaa RAEE Daae 7 4 Sample Counter TC Circi y ssiri eaa e aai a ER E a 8 3 User TC Circuitry ut abi 8 3 Module zs eot tonem eee glo e ne Re Meta dde seo dol A ct oe 11 3 INTRODUCTION The DM6620 analog o
45. errupt can be generated whenever any bit changes state This is an event interrupt For either interrupt bits can be masked by setting the corresponding bit in the Mask Register high In a digital interrupt mode this masks out selected bits when monitoring the bit pattern for a match or event In normal operation where the Advanced Digital Interrupt mode is not activated the Mask Register can be used to preserve a bit s state regardless of the digital data written to Port 0 When using event interrupts you can determine which bit caused an event interrupt to occur by reading the contents latched into the Compare Register Port 1 Port Programmable Digital I O The direction of the eight Port 1 digital lines is programmed at BA 31 bit 2 These lines are configured as all inputs or all outputs with their states read and written at BA 29 Resetting the Digital Circuitry When a digital chip clear BA 31 bits 1 and 0 00 followed by a write to BA 30 clear board BA 14 or reset command is issued all of the digital I O lines are set up as inputs Strobing Data into Port 0 When not in an Advanced Digital Interrupt mode external data can be strobed into Port 0 by connecting a trigger pulse through the STRB IN pin at CN3 39 This data can be read from the Compare Register at BA 30 9 3 9 4 CHAPTER 10 EXAMPLE PROGRAMS This chapter discusses the example programs included with the DM6620 10 1 10 2 Included w
46. grammed to read data at a specified offset into a specified page for example start reading at word 512 of page 3 Each time a word of data is read by the controller the offset is automatically incremented so the next word will be read from the next memory location The problem for you when programming these values is figuring out what the corresponding page and offset are for your buffer Most compilers contain macros or functions that allow you to directly determine the segment and offset of a data structure but not the page and offset Therefore you must calculate the page number and offset yourself Probably the most intuitive way of doing this is to convert the segment offset address of your buffer to a linear address and then convert that linear address to a page offset address The table below shows functions macros for determining the segment and offset of a buffer FP_SEG FP_OFF s FP_SEG amp Buffer o FP_OFF amp Buffer Pascal Seg S Seg Buffer O Ofs Buffer Once you ve determined the segment and offset multiply the segment by 16 and add the offset to give you the linear address Make sure you store this result as a long integer or DWORD or the results will be meaning less The linear address is a 20 bit value with the upper 4 bits representing the page and the lower 16 bits representing the offset into the page Even though the upper 4 bits are the page only the upper 3 bits D17 D18 and D19 are sent to what is
47. gramming the Mask Register with the mask at BA 30 Match Mode When enabled this mode samples the Port 0 input lines at a specified clock rate using the 8 MHz system clock or a programmable clock in User TC Counter 1 and compares all input states to the value programmed in the Compare Register at BA 30 When the states of all of the lines match the value in the Compare Register an interrupt is generated Bits can be masked and their states ignored by programming the Mask Register with the mask at BA 30 Sampling Digital Lines for Change of State In the Advanced Digital Interrupt modes the digital lines are sampled at a rate set by the 8 MHz system clock or the clock programmed in User TC Counter 1 With each clock pulse the digital circuitry looks at the state of the next Port 0 bits To provide noise rejection and prevent erroneous interrupt generation because of noise spikes on the digital lines a change in the state of any bit must be seen for two edges of a clock pulse to be recognized by the circuit Figure 7 1 shows a diagram of this circuit CLOCK DIGITAL INPUT IRQ OUT Fig 7 1 Digital Interrupt Timing Diagram 7 4 Basic Programming For Interrupt Handling e What Is an Interrupt An interrupt is an event that causes the processor in your computer to temporarily halt its current process and execute another routine Upon completion of the new routine control is returned to the original routine at the point where
48. hen an IRQ line is brought high the interrupt controllers check to see if interrupts are to be acknowledged from that IRQ and if another interrupt is already in progress they decide if the new request should supersede the one in progress or if it has to wait until the one in progress is done This prioritizing allows an interrupt to be interrupted if the second request has a higher priority The priority level is determined by the number of the IRQ Because of the configuration of the two controllers with one chained to the other through IRQ2 the priority scheme is a little unusual IRQO has the highest priority IRQ1 is second highest then priority jumps to IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 and IRQIS and then following 15 it jumps back to IRQ3 IRQ4 5 IRQ6 and finally the lowest priority IRQ7 This sequence makes sense if you consider that the controller that handles 8 15 is routed through IRQ2 8259 Programmable Interrupt Controllers The chips responsible for handling interrupt requests in the PC are the 8259 Programmable Interrupt Control lers The 8259 that handles IRQO IRQ7 is referred to as 8259A and the 8259 that handles IRQ8 IRQIS is referred to as 8259B To use interrupts you need to know how to read and set the 8259 interrupt mask registers IMR and how to send the end of interrupt EOI command to the 82595 Interrupt Mask Registers IMR Each bit in the interrupt mask register IMR c
49. illivolts Unipolar D A Bit Weight 0 to 5 Volts 0 to 10 Volts 4095 4998 78 9997 56 2048 2500 00 5000 00 1024 1250 00 2500 00 1625 00 125000 5 5 Ideal Output Voltage millivolts Bipolar D A Bit Weight 5 to 5 Volts 10 to 10 Volts 1250 00 2500 00 5000 00 10000 00 1024 Sample Buffer Each DAC channel has a 1024 sample buffer for storing data to be sent to the D A converter This means that you can fill the buffer with data and set up the D A to output this data automatically This is very useful for outputting high speed data or generating waveforms with precise timing requirements By setting the cycle bit at BA 12 you can fill the buffer with one cycle of a wave start the D A update clock and the buffer will continue to repeat until the clock is stopped Combining this feature with the variety of update sources you can build a flexible waveform generator If you are trying to generate a non repetitive waveform you can combine the sample buffer capability with the DAC sample counter To utilize this feature of the DM6620 properly you should load the buffer with data program the DAC sample counter for half the buffer size 512 samples and use the sample counter to generate an interrupt When an interrupt is received you should reload the buffer with 512 new samples By continuing this cycle you can generate a non repetitive waveform at high speeds Status of the FIFO buffers can be monitored
50. it programmable amp 8 port programmable AYO a TTL Input Output 1 0 to 5 volts ISOUNCE ater Mea tas 12 MA ne ea nee DUE 24 mA User Timer Counters pe CMOS 82C54 Three 16 bit down counters 6 programmable operating modes Counter input SOUFCE pp External clock 8 MHz max or on board 8 MHz clock Counter outputs Available externally used as PC interrupts Counter gate source External gate or always enabled Miscellaneous Inputs Outputs PC bus sourced 5 volts 12 volts ground Power Requirements DM6620 5 volts 420 ma 2 1 W typ CN3 Connector 50 pin right angle header Environmental Operating temperature 2 40 to 85 C Storage temperature 55 to 125 C Humidity ii are eoe ode ide Oto 90 non condensing Size 3 55 L x 3 775 W x 0 6 H 90mm x 96mm x 16mm Weight 3 oz 86 grams A 3 A 4 APPENDIX B CN3 CONNECTOR PIN ASSIGNMENTS B 2 EXT GATE 2 12 VOLTS 12 VOLTS CLK OUT 2 5 VOLTS DIGITAL GND AOUT1 OO ANALOG GND AOUT2 GO ANALOG GND AOUT3 GO ANALOG GND AOUT4 DO ANALOG GND DAC1 DATA MARKER 9 Go DIGITAL GND DAC2 DATA MARKER DIS DIGITAL GND DAC3 DATA MARKER 3 04 DIGITAL GND DAC4 DATA MARKER OH DIGITAL GND N C 248 DIGITAL GND EXT INT
51. ite A write loads the third counter in one of the two timer counters on the board with a new 16 bit value in two 8 bit steps LSB followed by MSB The counter must be loaded in two 8 bit steps Counting begins as soon as the count is loaded The timer counter being loaded is selected by writing to BA 4 bit 15 A read shows the count in the counter BA 27 Timer Counter Control Word 8 bit Operation Write only Accesses the selected timer counter s control register to directly control the three 16 bit counters 0 1 and 2 di BCD Binary Counter Select 00 Counter 0 0 binary 01 Counter 1 Read Load Counter Mode Select 1 BCD 10 Counter 2 00 latching operation 000 Mode 0 event count 11 read back setting 01 read load LSB only 001 Mode 1 programmable 1 shot 10 read load MSB only 010 Mode 2 rate generator 11 read load LSB then MSB 011 Mode square wave rate generator 100 Mode 4 software triggered strobe 101 Mode 5 hardware triggered strobe 4 13 BA 28 Digital I O Port 0 Bit Programmable Port 8 bit Operation Read Write Port 0 0 7 0 6 PO 5 PO 4 PO 3 PO 2 PO 1 PO 0 This port transfers the 8 bit Port 0 bit programmable digital input output data between the module and external devices The bits are individually programmed as input or output by writing to the Direction Register at BA 28 For all bits set as inputs a read reads the input
52. ith the DM6620 is a set of example programs that demonstrate the use of many of the module s features These examples are in written in C and BASIC Also included is an easy to use menu driven diagnostics program 6620DIAG which is especially helpful when you are first checking out your module after installation and when calibrating the module Chapter 12 Before using the software included with your module make a backup copy of the disk You may make as many backups as you need C Programs These programs are source code files so that you can easily develop your own custom software for your DM6620 All of the programs use the files DRVR6620 C DIO5812 C and PCUTILS C These files contain all of the routines for setting up the board and acquiring data DRVR6620 C contains all the functions needed to control the D A converter and the Timer Counters These functions are used to set up the D A outputs and the timer counter chips DIO5812 C contains all the functions needed to control the digital I O chip This chip is the same one used on the Real Time Devices DM5812 module providing two 8 bit ports Port 0 can have its lines set as input or output on a bit by bit basis This allows maximum flexibility when connecting your signals Port 1 is set to be input or output as a group In addition Port 0 supports RTD s two Advanced Digital Interrupt modes An interrupt can be generated when the lines match a programmed value or when any bit changes it
53. lly be executed each time an interrupt request occurs on the specified IRQ An ISR is different than standard routines that you write First on entrance the processor registers should be pushed onto the stack BEFORE you do anything else Second just before exiting your ISR you must write an end of interrupt command to the 8259 controller s Since 8259B generates a request on IRQ2 which is handled by 8259A an EOI must be sent to both 8259A and 8259B for IRQ8 IRQIS Finally when exiting the ISR in addition to popping all the registers you pushed on entrance you must use the IRET instruction and not a plain RET The IRET auto matically pops the flags CS and IP that were pushed when the interrupt was called If you find yourself intimidated by these requirements take heart Most Pascal and C compilers allow you to identify a procedure function as an interrupt type and will automatically add these instructions to your ISR with one important exception most compilers do not automatically add the end of interrupt command to the proce dure you must do this yourself Other than this and the few exceptions discussed below you can write your ISR just like any other routine It can call other functions and procedures in your program and it can access global data If you are writing your first ISR we recommend that you stick to the basics just something that will convince you that it works such as incrementing a global variable NOTE If you are wri
54. load Counter Set DAC Control sample counter 3 Program DAC Control BA 12 Clear Clears board circuits programmed Sets the board circuits to be Clear Mask Register by a write to this address cleared BA 14 Update DAC1 DAC1 FIFO Update DAC1 Load DAC1 FIFO 16 Update DAC2 DAC2 FIFO Update DAC2 Load DAC2 FIFO BA 18 Update DAC3 DAC3 FIFO Update DAC3 Load DAC3 FIFO BA 20 Update DAC4 DAC4 FIFO Update DAC4 Load DACA FIFO BA 22 8254 SC TC Counter 0 amp Read value in SC or User TC Load count in SC or User TC User TC Counter 0 Counter 0 dependent on BA 4 Counter 0 dependent on BA 4 BA 24 8254 SC TC Counter 1 amp Read value in SC or User TC Load count in SC or User TC User TC Counter 1 Counter 1 dependent on BA 4 Counter 1 dependent on BA 4 BA 25 8254 SC TC Counter 2 amp Read value in SC or User TC Load count in SC or User TC User TC Counter 2 Counter 2 dependent on BA 4 Counter 2 dependent on BA 4 BA 26 8254 Clock TC 8 User TC Program counter mode for SC or Control User TC dependent on BA 4 BA 27 Digital MO Port 0 Digital MO Port 1 Port Programmable Read Port 1 digital input lines Program Port 1 digital output lines BA 29 Clear digital IRQ status flag read Clear digital chip program Port 0 Port 0 Clear Port 0 direction mask or compare direction mask or compare register Direction Mask Compare register dependent on BA 31 dependent on BA 31 BA 30 Read Digital I
55. n all three pads as this will damage the board JS2 JS1 Fig 1 5 Ports O and 1 Pull up Pull down Resistor Connections CHAPTER 2 INSTALLATION The DM6620 is easy to install in your cpuModule or other PC 104 based system This chapter tells you step by step how to connect the module After you have made all of your connections you can turn your system on and run the 6620DIAG board diagnostics program included on your example software disk to verify that the module is working 2 1 2 2 Installation Keep the module in its antistatic bag until you are ready to install it in your cpuModule or other PC 104 based system When removing it from the bag hold the module at the edges and do not touch the components or connectors Before installing the module in your system check the jumper and switch settings Chapter 1 reviews the factory settings and how to change them If you need to change any settings refer to the appropriate instructions in Chapter 1 Note that incompatible jumper settings can result in unpredictable module operation and erratic response The DM6620 comes with stackthrough connectors for and CN2 These stackthrough connectors let you stack another module on top of your DM6620 Pins B10 and C19 are keying pins and will be plugged on the top ofthe board and removed from the bottom NOTE The DM6620 module will only work with an AT cpuModule Do not try to use it with an XT cpuModule To inst
56. n large 1 letters on the outside of the package Return the package to RTD Embedded Technologies Inc 103 Innovation Blvd State College PA 16803 0906 USA D 1 D2 LIMITED WARRANTY RTD Embedded Technologies Inc warrants the hardware and software products it manufactures and produces to be free from defects in materials and workmanship for one year following the date of shipment from RTD Embedded Technologies INC This warranty is limited to the original purchaser of product and is not transferable During the one year warranty period RTD Embedded Technologies will repair or replace at its option any defective products or parts at no additional charge provided that the product is returned shipping prepaid to RTD Embedded Technologies All replaced parts and products become the property of RTD Embedded Technologies Before returning any product for repair customers are required to contact the factory for an RMA number THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY PRODUCTS WHICH HAVE BEEN DAM AGED AS A RESULT OF ACCIDENT MISUSE ABUSE such as use of incorrect input voltages improper or insufficient ventilation failure to follow the operating instructions that are provided by RTD Embedded Technologies acts of God or other contingencies beyond the control of RTD Embedded Technologies ORAS A RESULT OF SERVICE OR MODIFICATION BY ANYONE OTHER THAN RTD Embedded Technologies EXCEPT AS EXPRESSLY SET FORTH ABOVE NO OTHE
57. nd Counter 2 can be programmed as sample counters and used to generate interrupts These are useful for signaling the CPU to load new data into the D A buffer SAMPLE COUNTER 1 SOURCE COUNTER 0 SAMPLE COUNT 1 SAMPLE COUNTER 2 SOURCE COUNTER 1 SAMPLE COUNT 2 SAMPLE COUNTER 3 SOURCE COUNTER 2 SAMPLE COUNT 3 Fig 8 1 Sample Counter TC Circuitry The 8254 at UlO is the User TC On the User TC Counters 0 Counter 1 and Counter 2 are available to the user These timer counters can also be used to generate clocks as update signals for the D A converters TO DAC UPDATE SELECT 1 0 CONNECTOR CN3 I XTAL 8 MHz I TIMER Pin 39 EXT CLK COUNTER CLK 9 0 5 V GATE PIN 41 EXT GATE 0 ST PIN 42 OUT 0 I TIMER COUNTER CLK 1 5 V GATE PIN 43 EXT GATE 1 PIN 44 LK OUT 1 OUT TIMER COUNTER CLK 2 5 V GATE PIN 45 EXT GATE 2 PIN 46 4 CLK OUT 2 Fig 8 2 User TC Circuitry 8 3 Each timer counter has two inputs CLK in and GATE in and one output timer counter OUT They can be programmed as binary or BCD down counters by writing the appropriate data to the command word as described in the I O map discussion in Chapter 4 The outputs from the User TC Counters are available at the CN3 1 O connector These outputs can also be selected through software to be used as the update clock for the D A converters The timers can be programmed t
58. nes Instructions for activating these pull up pull down resistors are given at the end of Chapter 1 Module Settings What Comes With Your Module You receive the following items in your module package DM6620 interface module with stackthrough bus header Mounting hardware Windows example programs in Visual Basic and C Example programs in BASIC and C with source code amp diagnostics software User s manual If any item is missing or damaged please call Real Time Devices USA Customer Service Department at 814 234 8087 If you require service outside the U S contact your local distributor Module Accessories In addition to the items included in your module package Real Time Devices offers a full line of software and hardware accessories Call your local distributor or our main office for more information about these accessories and for help in choosing the best items to support your module s application Hardware Accessories Hardware accessories for the DM6620 include the OP series optoisolated digital input boards the MR series mechanical relay output boards the OR16 optoisolated digital input mechanical relay output board the TB50 terminal board and XB50 prototype terminal board for easy signal access and prototype development the DM16 extender board for testing your module in a conventional desktop computer and XT50 twisted pair wire flat ribbon cable assembly for external interfacing Using This Manual Thi
59. ng an interrupt while you are installing and initializing your ISR To mask the IRQ read in the current IMR at I O port 21H for IRQO IRQ7 or at I O port AIH for IRQ8 IRQIS and set the bit that corresponds to your IRQ remember setting a bit disables interrupts on that IRQ while clearing a bit enables them The IMR on 8259A is arranged so that bit 0 is for IRQO bit 1 is for IRQ1 and so on The IMR on 8259B is arranged so that bit 0 is for IRQ8 bit 1 is for IRQ9 and so on See the paragraph entitled Interrupt Mask Register IMR earlier in this chapter for help in determining your IRQ s bit After setting the bit write the new value to I O port 21H IRQO IRQ7 or I O port AIH IRQ8 IRQ15 With the startup IMR saved and the interrupts on your IRQ temporarily disabled you can assign the interrupt vector to point to your ISR Again you can overwrite the appropriate entry in the vector table with a direct memory write but this is a bad practice Instead use either DOS function 25H set interrupt vector or if your compiler provides it the library routine for setting an interrupt vector Remember that vectors 8 15 are for IRQO IRQ7 and vectors 70H 77H for 8 15 If you need to program the source of your interrupts do that next For example if you are using the program mable interval timer to generate interrupts you must program it to run in the proper mode and at the proper rate Finally clear the bit in the IMR for the
60. ng solder connections on the bottom of the board at JS1 and JS2 you can configure each set of digital I O lines to be pulled up or pulled down This procedure is explained at the end of this chapter Factory Configured Switch and Jumper Settings Table 1 1 lists the factory settings of the user configurable jumpers and switch on the DM6620 module Figure 1 1 shows the module layout and the locations of the factory set jumpers The following paragraphs explain how to change the factory settings Pay special attention to the setting of 51 the base address switch to avoid address contention when you first use the module in your system Table 1 1 Factory Settings Switch Factory Settings Jumper Function Controlled Jumpers Installed Sets the clock source for User TC Counters 0 1 CIk 0 XTAL Clk 1 OTO Clk 2 JP1 2 OT1 timer counters cascaded Activates pull up pull down resistors on Port 0 All bits pulled up solder JS1 digital O lines connections between COM amp V Activates pull up pull down resistors on Port 1 All bits pulled up solder JS2 digital I O lines connections between COM amp V Sets the base address 300 hex 768 decimal TR1 TR2 TR3 TR4 wu 2 5 2 Ex es Re U24 CN3 n 885 026 m ui Bg us 25 immo o nnn Ill zx 22 me ma vo 1851 mm ae a un U29 27 nii inni 27 eu 3 2 US u
61. nnector pinout Refer to this diagram as you make your I O connections Note that 12 volts at pin 47 and 12 volts at pin 49 are available only if your computer bus supplies them these voltages are not provided by the module 2 3 AOUT1 AOUT2 AOUT3 AOUT4 DAC1 DATA MARKER ANALOG GND ANALOG GND ANALOG GND ANALOG GND DIGITAL GND DAC2 DATA MARKER DIGITAL GND DAC3 DATA MARKER DIGITAL GND DAC4 DATA MARKER DIGITAL GND N C DIGITAL GND EXT INT DIGITAL GND DIGITAL GND DIGITAL GND P0 7 P1 7 P0 6 P1 6 P0 5 P1 5 P0 4 P1 4 P0 3 P1 3 P0 2 P1 2 P0 1 P1 1 P0 0 P1 0 EXT CLK DIGITAL GND EXT GATE 0 CLK OUT 0 EXT GATE 1 CLK OUT 1 EXT GATE 2 CLK OUT 2 12 VOLTS 5 VOLTS 12 VOLTS DIGITAL GND Fig 2 1 CN3 I O Connector Pin Assignments Connecting the Analog Outputs For each of the four D A outputs connect the high side of the device receiving the output to the AOUT channel CN3 1 CN3 3 CN3 5 or CN3 7 and connect the low side of the device to an ANALOG GND CN3 2 4 6 8 Connecting the Timer Counters Digital I O and DataMarkers For all of these connections the high side of an external signal source or destination device is connected to the appropriate signal pin on the I O connector and the low side is connected to any DIGITAL GND Running the 6620DIAG Diagnostics Program Now that your module is ready to use you will want to try it out An easy to use menu driven diagnostics program 6620DIAG is included with your
62. o operate in one of six modes depending on your application The following paragraphs briefly describe each mode Mode 0 Event Counter Interrupt on Terminal Count This mode is typically used for event counting While the timer counter counts down the output is low and when the count is complete it goes high The output stays high until a new Mode 0 control word is written to the timer counter Mode 1 Hardware Retriggerable One Shot The output is initially high and goes low on the clock pulse following a trigger to begin the one shot pulse The output remains low until the count reaches 0 and then goes high and remains high until the clock pulse after the next trigger Mode 2 Rate Generator This mode functions like a divide by N counter and is typically used to generate a real time clock interrupt The output is initially high and when the count decrements to 1 the output goes low for one clock pulse The output then goes high again the timer counter reloads the initial count and the process is repeated This sequence continues indefinitely Mode 3 Square Wave Mode Similar to Mode 2 except for the duty cycle output this mode is typically used for baud rate generation The output is initially high and when the count decrements to one half its initial count the output goes low for the remainder of the count The timer counter reloads and the output goes high again This process repeats indefinitely Mode 4 Software Triggered Strob
63. oller After the DMA controller has been programmed and the DM6620 has been programmed to accept data you can enable DMA by clearing the mask bit for the DMA channel you are using You should manually disable DMA by setting the mask bit before exiting your program or if for some reason sampling is halted before the DMA controller has trans ferred all the data it was programmed to transfer Te Te o Channel Select Mask Bit 00 Channel 4 0 unmask 01 Channel 5 1 mask 10 6 11 Channel 7 6 6 DMA Mode Register The DMA mode register is used to set parameters for the DMA channel you will be using The read write bits are self explanatory the write mode cannot be used with the DM6620 Autoinitialization allows the DMA controller to automatically start over once it has transferred the requested number of words Decrement means the DMA controller should decrement its offset counter after each transfer the default is increment We recommend that you use either the demand or single transfer mode when transferring data Block mode transfer is not sup ported by this board D4 D2 DO Port D6H rl Transfer Mode Channel Select 00 demand Autoinitialization 00 Channel 4 01 single transfer 0 disable 01 Channel 5 10 block 1 enable 10 Channel 6 11 cascade 11 Channel 7 nn Read Write 1 01 write not used with DM6620 10 read Programming the DMA Controller
64. ontains the mask status of an IRQ line 8259A bit 0 is for IRQO bit 1 is for IRQ1 and so on while in 8259B bit 0 is for IRQ8 bit 1 is for IRQ9 and so on If a bit is set equal to 1 then the corresponding IRQ is masked and it will not generate an interrupt If a bit is clear equal to 0 then the corresponding IRQ is unmasked and can generate interrupts The IMR for IRQO IRQ7 is programmed through port 21H and the IMR for IRQ8 IRQI5 is programmed through port AIH wo wm we Jr nes man s Jr For all bits 0 IRQ unmasked enabled 1 IRQ masked disabled 7 5 End of Interrupt EOD Command After an interrupt service routine is complete the appropriate 8259 interrupt controller must be notified When using 0 7 this is done by writing the value 20H to I O port 20H only when using 8 15 you must write the value 20H to I O ports 20H and AOH What Exactly Happens When an Interrupt Occurs Understanding the sequence of events when an interrupt is triggered is necessary to properly write software interrupt handlers When an interrupt request line is driven high by a peripheral device such as the DM6620 the interrupt controllers check to see if interrupts are enabled for that IRQ and then checks to see if other interrupts are active or requested and determine which interrupt has priority The interrupt controllers then interrupt the processor The c
65. or set to logic 1 as labeled on the DIP switch package When you set the base address for your module record the value in the table inside the back cover Figure 1 7 shows the DIP switch set for a base address of 300 hex 768 decimal Table 1 2 Base Address Switch Settings S1 Base Address Base Address Decimal Hex 4 3 2 1 Decimal Hex 432 1 768 1 600 0 closed 1 open Fig 1 4 Base Address Switch S1 JS1 and JS2 Pull up Pull down Resistors on Digital I O Lines The DM6620 has 16 TTL CMOS compatible digital 1 O lines which can be interfaced with external devices These lines are divided into two groups Port 0 with eight individual bit programmable lines and Port 1 with eight port programmable lines Resistors are connected to these lines and can be configured as either pull up or pull down resistors 10 k ohm pull up pull down resistors are installed on the module and a solder connection must be made on the bottom of the board to configure their operation The solder connections are made at JS1 for Port 0 and JS2 for Port 1 The factory default is pull up for both ports This is done by placing a solder short between the middle common pad and V 5 volts To configure the resistors as pull down resistors remove the existing solder connection and make one between the middle common pad and G ground To disable the pull up pull down resistor remove the solder connection WARNING Do not install a connection betwee
66. per DMA operation DAC Sample Counter The DAC sample counters are useful when using clocks to output data to the D A These 16 bit counters will 5 7 count update pulses sent to the D A s and can be polled to read the current count or can be used to generate interrupts when the count reaches 0 These counters can be loaded to any starting value up to 65535 and count down When the count reaches 0 it will automatically be reloaded with the original starting value Using the sample counters to cause an interrupt is useful when generating non repeating waveforms The sample counter interrupt can be used to signal the CPU when to load new data into the FIFO buffer A read at BA 8 10 or 12 provides a software trigger so that the appropriate DAC sample counter can be loaded with the correct value This software correction is used as an easy means to compensate for the operating structure of the 8254 Two pulses of the counter are required to actually load the desired count and prepare the counter to count down correctly this can be looked at as the initialization procedure for the DAC sample counter A pulse is sent to the DAC sample counter each time you read this address Without this correction the initial count sequence will be off by two pulses Once the counter is properly loaded and starts any subsequent countdowns of this count will be accurate You must program the register at BA 8 to select the input source for each ofthe 3 sample counters
67. peripheral device The following steps are required when using DMA 1 Choose a DMA channel 2 Allocate a buffer 3 Calculate the page and offset of the buffer 4 Set the DMA page register 5 Program the 8237 DMA controller 6 DMA buffer with desired data 7 Program device accepting data DM6620 8 Enable DMA channel 9 Wait until DMA is complete 10 Disable DMA channel Each step is detailed in the following paragraphs Choosing a DMA Channel There are a number of DMA channels available on the PC for use by peripheral devices The DM6620 can use DMA channel 5 6 or 7 selected through software You can arbitrarily choose any of these in most cases your choice will be fine Occasionally though you will have another peripheral device for example a tape backup or Bernoulli drive that also uses the DMA channel you have selected This will certainly cause erratic results and can be hard to detect The best approach to pinpoint this problem is to read the documentation for the other peripheral devices in your system and try to determine which DMA channel each uses Allocating a DMA Buffer When using DMA you must have a location in memory where the 8237 DMA controller will read the data from to send out to the D A board This buffer can be either static or dynamically allocated The buffer must start on a word boundary i e even numbered address You should force your compiler to use word alignment for data Be
68. pulse is sent to sample counter 1 Sample Counter Counter 0 each time you read this address Without this correction the initial count sequence will be off by two pulses Once the counter is properly loaded and starts any subsequent countdowns of this count will be accurate Note that sample counter 1 must be programmed for Mode 2 operation Write A write to this address is used to select the input source for the different sample counters The sample counter sources are described below Sample Counter 3 Sample Counter 1 Source Select Source Select 00 DAC1 00 DAC1 01 DAC2 01 DAC2 10 DAC3 10 DAC3 11 DAC4 11 DAC4 Sample Counter 2 Source Select 00 DAC1 01 DAC2 10 DAC3 11 DAC4 Sample Counter Sources DACI The sample counter counts down one count for each sample that is read from the DACI FIFO and sent out the D A DAC2 The sample counter counts down one count for each sample that is read from the DAC2 FIFO and sent out the D A DAC3 The sample counter counts down one count for each sample that is read from the DAC3 FIFO and sent out the D A DAC4 The sample counter counts down one count for each sample that is read from the DAC4 FIFO and sent out the D A BA 10 Load Sample Counter 2 Select DAC Output Range 16 bit operation Read A read provides a software trigger so that sample counter 2 can be loaded with the correct value This software correction is use
69. roduce a repeating waveform Data can be written into the output buffers by 1 O instruction or by DMA transfer Updating of the analog outputs can be done through software or by several different clocks and triggers The outputs can be updated simultaneously or independently Timer Counters Two 8254 programmable interval timers provide six 16 bit 8 MHz timer counters to support wide range of timing and counting functions The 8254 at U9 is the Sample Counter TC All three of these 16 bit timer counters Counter 0 Counter 1 and Counter 2 can be programmed as sample counters and used to generate interrupts These are useful for signaling the CPU to load new data into the D A buffer The 8254 at U10 is the User TC On the User TC Counters 0 Counter 1 and Counter 2 are available to the user These timer counters can also be used to generate clocks as update signals for the D A converters Each 16 bit timer counter has two inputs CLK in and GATE in and one output timer counter OUT Each can be programmed as binary or BCD down counters by writing the appropriate data to the command word as described in Chapter 4 The command word also lets you set up the mode of operation The six programmable modes are Mode 0 Event Counter Interrupt on Terminal Count Mode 1 Hardware Retriggerable One Shot Mode 2 Rate Generator Mode 3 Square Wave Mode Mode 4 Software Triggered Strobe Mode 5 Hardware Triggered Strobe Retriggerable These modes are
70. s can be easily cleared in one operation To clear a single bit in a port AND the current value of the port with the value b where b 255 2 Example Clear bit 5 in a port Read in the current value of the port AND it with 223 223 255 25 and then write the resulting value to the port In BASIC this is programmed as V INP PortAddress V V AND 223 OUT PortAddress V To set a single bit in a port OR the current value of the port with the value b where b 20 Example Set bit 3 in a port Read in the current value of the port OR it with 8 8 2 and then write the resulting value to the port In Pascal this is programmed as V Port PortAddress V OR 8 Port PortAddress V 4 17 Setting or clearing more than one bit at a time is accomplished just as easily To clear multiple bits in a port AND the current value of the port with the value b where b 255 the sum of the values of the bits to be cleared Note that the bits do not have to be consecutive Example Clear bits 2 4 and 6 in a port Read in the current value of the port AND it with 171 171 255 2 2 2 and then write the resulting value to the port In this is pro grammed as v inportb port_address amp 171 outportb port_address v To set multiple bits in a port OR the current value of the port with the value b where b the sum of the individual bits to be set Note that the bits to
71. s count reaches 0 User TC Counter 1 out inverted an interrupt is generated when user TC Counter 1 s count reaches 0 useful for frequency counting 4 4 User TC Counter 2 out an interrupt is generated when user TC Counter 2 s count reaches 0 Digital interrupt an interrupt is generated when an advanced digital interrupt occurs External interrupt an interrupt is generated when the external interrupt line is pulsed CN3 19 BA 4 Program DMA Channel and Source 16 bit operation Read Reserved Write This register programs the source for each of the DMA channels It is also used to select which 8254 Timer Counter chip is being addressed at BA 24 to BA 27 The DMA sources and timer options are described 829 Timer Select DMA 7 Source Select DMA 6 Source Select DMA 5 Source Select 0 Sample counter ES 000 disabled 000 disabled 000 disabled 1 User Timer Counter 001 DAC1 001 DAC1 001 DAC1 010 DAC2 010 DAC2 010 DAC2 011 DAC3 011 DAC3 011 DAC3 100 DAC4 100 DAC4 100 DAC4 101 reserved 110 reserved 111 reserved 101 reserved 110 reserved 111 reserved 101 reserved 110 reserved 111 reserved DMA Sources DACI DMA transfers are requested when the DACI FIFO is not full DAC2 DMA transfers are requested when the DAC2 FIFO is not full DAC3 DMA transfers are requested when the DAC3 FIFO is not full DAC4 DMA transfers are requested when
72. s current state A Mask Register lets you monitor selected lines for interrupt generation PCUTILS C and DMAUTIL C contain functions to help program the CPU for interrupts and DMA Quick Basic Programs These programs are source code files so that you can easily develop your own custom software for your DM6620 All of the programs rely on the DRVR6620 LIB and the DRVR6620 QLB library files These library files contain all of functions needed to interface to the DM6620 Make sure the proper library is loaded when starting Quick Basic by typing QB L DRVR6620 These libraries were created using Borland C 3 1 and were generated from the files DRVR6620 C and DIO5812 C Should you need to recompile the libraries contact the factory for details on this procedure 10 3 10 4 CHAPTER 11 CALIBRATION This chapter tells you how to calibrate the DM6620 using the 6620DIAG diagnostic program included in the example software package and the trimpots on the module This chapter tells you how to calibrate the D A converter The D A converter is factory calibrated and any time you suspect inaccurate readings you can check the accuracy of your conversions using the procedure below and make adjusts as necessary Using the 6620DIAG diagnostics program is a convenient way to monitor conver sions while you calibrate the module Calibration is done with the module installed in your system You can access the trimpots at the edge of the module Power up the
73. s manual is intended to help you install your new module and get it running quickly while also providing enough detail about the module and its functions so that you can enjoy maximum use of its features even in the most complex applications We assume that you already have an understanding of data acquisition principles and that you can customize the example software or write your own application programs When You Need Help This manual and the example programs in the software package included with your board provide enough information to properly use all of the module s features If you have any problems installing or using this dataModule contact our Technical Support Department 814 234 8087 during regular business hours eastern standard time or eastern daylight time or send a FAX requesting assistance to 814 234 5218 When sending a FAX request please include your company s name and address your name your telephone number and a brief description of the problem You can also contact us through our E mail address techsupport rtdusa com CHAPTER 1 MODULE SETTINGS The DM6620 has jumper and switch settings you can change if necessary for your application The module is factory configured as listed in the table and shown on the layout diagram in the beginning of this chapter Should you need to change these set tings use these easy to follow instructions before you stack the module with your computer system Also note that by placi
74. sed into the DMA page register with the least significant bit set to zero The DMA page register is separate from the DMA controller as shown in the table below DMA Channel Location of Page Register 8B 139 89 137 8A 138 6 5 The DMA Controller The DMA controller is made up of two complex 8237 chips one for DMA channels 0 3 and one for channels 4 7 that occupy 32 contiguous bytes of the AT I O port space starting with port COH A complete discussion of how it operates is beyond the scope of this manual only relevant information is included here The DMA control ler is programmed by writing to the DMA registers in your AT The table below lists these registers DMA Registers Address hex decimal D8 216 Byte Pointer Flip Flop If you are using DMA channel 5 write your page offset bits to port CAH and the count to C6H for channel 6 write the offset to C8H and the count to CAH for channel 7 write the offset to CCH and the count to CEH The page offset bits are the bits you calculated as shown above Count indicates the number of samples that you want the DMA controller to transfer The value that you write to the DMA controller is number of samples 1 The mask register and mode register are described below DMA Mask Register The DMA mask register is used to enable or disable DMA on a specified DMA channel You should mask disable DMA on the DMA channel you will be using while programming the DMA contr
75. set For example you might think that to set bit 5 ofa port you simply need to read in the port add 32 2 to that value and then write the resulting value back to the port This works fine if bit 5 is not already set But what happens when bit 5 is already set Bits 0 to 4 will be unaffected and we can t say for sure what happens to bits 6 and 7 but we can say for sure that bit 5 ends up cleared instead of being set A similar problem happens when you use subtraction to clear a bit in place of the method shown above 4 18 CHAPTER 5 D A CONVERSIONS This chapter explains how to perform D A conversions on the DM6620 5 1 5 2 The analog outputs are generated by four 12 bit D A converters with independent software programmable output ranges of 5 10 0 to 5 or 0 to 10 volts All channels support DMA transfer DACI data is written to BA 16 DAC2 data is written to BA 18 DAC3 data is written to BA 20 and DAC4 data is written to BA 22 The DAC Output Range register at BA 10 and the DAC Update register at BA 12 are described below DAC Output Range Register BA 10 PEPER EEE Pl DAC4 Update Enable 0 disabled 1 enabled Enable DAC2 Update DAC1 Update 0 disabled 1 enabled DAC3 Output Range 00 0 to 5 volts 01 0 to 10 volts 10 5 volts 11 10 volts DAC1 Output Range 00 0 to 5 volts 01 0 to 10 volts 10 5 volts 11 10 vol
76. storage before being output Data can be continuously written to the buffer producing a non repetitive output waveform or a set of data can be written into the buffer and continuously cycled to produce a repeating waveform Data can be written into the output buffers by I O instruction or by DMA transfer Updating of the analog outputs can be done through software or by several different clocks and triggers The outputs can be updated simultaneously or independently 8254 Timer Counters Two 8254 programmable interval timers provide six three each 16 bit 8 MHz timer counters to support a wide range of board operations and user timing and counting functions The Sample Counter TC is used for board operations providing 3 independent 16 bit counters used to count output samples and generate interrupts The User TC has three 16 bit timer counters for user functions The outputs from these timer counters can be used to update the D A outputs Digital The DM6620 has 16 buffered TTL CMOS digital I O lines which are grouped as eight independent bit programmable lines at Port 0 and an 8 bit programmable port at Port 1 The bit programmable lines support RTD s two Advanced Digital Interrupt modes An interrupt can be generated when any bit changes value event interrupt or when the lines match a programmed value match interrupt For either mode masking can be used to monitor selected lines Pull up or pull down resistors are provided for all 16 li
77. system and let the board circuitry stabilize for 15 minutes before you start calibrating Required Equipment The following equipment is required for calibration Digital Voltmeter 5 1 2 digits Small Screwdriver for trimpot adjustment While not required the 6620DIAG diagnostics program included with example software is helpful when performing calibrations Figure 12 1 shows the module layout with the trimpots located along the top edge TR1 TR2 TRS TR4 pes EE gt num i als U26 y U2 1 72 029 nn mim U27 mm U9 O STO 2 oo 8000 oo DOOO 07 ZT TI mm p mm lt nu 00000000000000 2 2 CHA amp C nia rM 010 e unnmil Un E OOO000000000000000000000000809898 00000000000000000000000000000 D A Calibration The D A circuit requires no calibration for the 0 to 5 and 5 volts ranges The following paragraph describes the calibration procedure for the 0 to 10 and 10 volt ranges To calibrate for the 0 to 10 and 10 volt ranges program the DAC outputs for a 0 to 10 volt range at the DAC Range register BA 10 Now program the D A outputs with a digital value of 2048 The ideal DAC output for a code of 2048 is 5 000 volts Connect a vol
78. t COUhters 2 rate dd aep epe p A eee e etre teet etg ii i 3 Digital VO sisien e E i 3 What Comes With Your Module eedem dde ent da etie eoe tds i 3 Module Accessories iere eaten n ed eere la tete I Ode Pepe aeons i 4 Hardware Accessories ira ue oh Bat aia eal Bete e ae rete E Fr ate i 4 Using This Mania cutis ein i 4 When You Need 1 4 CHAPTER 1 MODULE SETTINGS ee 1 1 Factory Configured Switch and Jumper Settings Ne 1 3 JP1 User TC Clock Source Select Factory Settings Clk 0 XTAL Clk 1 Clk 2 OT 1 4 S1 Base Address Factory Setting 300 hex 768 4 1 6 JS1 and JS2 Pull up Pull down Resistors on Digital VO Lines oooconncnnonncnocnnonocnnccnanonananonncnn cnn 1 7 CHAPTER 2 INSTALLATION 2 1 Sa 2 3 External VO Connections a A ta E 2 3 Connecting the Analog Outputs e a a e es 2 4 Connecting the Timer Counters and Digital I O 2 4 Running the 6620DIAG Diagnostics Program pe 2 4 CHAPTER 3 HARDWARE DESCRIPTION 20020000000000000000000000000000000000000000 0000000000000 3 1 Digital to Analog Conyetsiol 31
79. this can be looked at as the initialization procedure for the sample counter A pulse is sent to sample counter 3 Sample Counter Counter 2 each time you read this address Without this correction the initial count sequence will be off by two pulses Once the counter is properly loaded and starts any subsequent countdowns of this count will be accurate Note that sample counter 3 must be programmed for Mode 2 operation 4 8 Write A write to this address is used to select the update signal and cycle mode for each D A output The different update signals and cycle modes are described below EIEICIEIEIEIEN 9 015 Ei D13 D11 DAC4 Cycle DAC3 Cycle 0 no cycle 0 no cycle 1 cycle 1 cycle 000 Software DAC2 Cycle 0 no cycle 1 cycle DAC3 Update Select 001 Software update all 010 User TC Counter 0 out DAC4 Update Select 011 User TC Counter 1 out 000 Software 001 Software update all 010 User TC Counter 0 out 011 User TC Counter 1 out 100 User TC Counter 2 out 101 External clock CN3 39 110 External Interrupt CN3 19 111 reserved 101 External c 111 reserved DAC Update Signals 100 User TC Counter 2 out lock CN3 39 110 External Interrupt CN3 19 DAC1 Cycle 0 no cycle DAC1 Update Select 1 cycle 000 Software 001 Software update all 010 User TC Counter O out 011 User TC Counter 1 out 100 User TC Counter 2 out 101 External clo
80. ting an ISR using assembly language you are responsible for pushing and popping registers and using IRET instead of RET There are a few cautions you must consider when writing your ISR The most important is do not use any DOS functions or routines that call DOS functions from within an ISR DOS is not reentrant that is a DOS function cannot call itself In typical programming this will not happen because of the way DOS is written But what about when using interrupts Then you could have a situation such as this in your program If DOS function X is being executed when an interrupt occurs and the interrupt routine makes a call to DOS function X then function X is essentially being called while it is already active Such a reentrancy attempt spells disaster because DOS functions are not written to support it This is a complex concept and you do not need to understand it Just make sure that you do not call any DOS functions from within your ISR The one wrinkle is that unfortunately it 7 6 is not obvious which library routines included with your compiler use DOS functions A rule of thumb is that routines which write to the screen or check the status of or read the keyboard and any disk I O routines use DOS and should be avoided in your ISR The same problem of reentrancy exists for many floating point emulators as well meaning you may have to avoid floating point real math in your ISR Note that the problem of reentrancy exists no ma
81. tion A 1024 sample buffer is also connected to Port O to provide buffering for high speed digital inputs Port 1 can be programmed as an 8 bit input or output port Chapter 10 details digital I O operations and Chapter 7 explains digital interrupts 3 5 3 6 CHAPTER 4 MAPPING This chapter provides a complete description of the I O map for the DM6620 general programming information and how to set and clear bits in a port 4 1 4 2 Defining the I O Map The I O map for the DM6620 is shown in Table 4 1 below As shown the board occupies 32 consecutive I O port locations The base address designated as BA can be selected using DIP switch S1 located on the edge of the board as described in Chapter 1 Board Settings This switch can be accessed without removing the module from the stack The following sections describe the register contents of each address used in the I O map Table 4 1 DM6620 I O Map Register Description Read Function Write Function Decimal Channel Reserved Program IRQ register BA 2 Channel Reserved Program DMA register BA 4 Update DACs Read Staus register Update All DACs BA 6 Initialize Sample Counter Set Sample Provides software trigger to load Counter Source sample counter 1 Program Sample Counter Source BA 8 Initialize Sample Counter Set DAC Output Provides software trigger to load Range sample counter 2 Program DAC Range BA 10 Initialize Sample Provides software trigger to
82. tmeter to the DAC outputs and adjust TR1 for DACI TR2 for DAC2 TR3 for DAC3 and TR4 for DAC4 until 5 000 volts is read on the meter The following tables show the ideal output voltage per bit weight for unipolar and bipolar ranges Ideal Output Voltage millivolts Unipolar D A Bit Weight O to 5 Volts 44998 78 2500 00 125000 1625 00 31250 1156 25 178 19 139 06 TT 19 7 14 88 Em 12 599 O Ideal Output Voltage millivolts Bipolar D A Bit Weight 5 to 5 Volts 10 to 10 Volts 625 00 312 50 15625 156 25 78 13 4 88 1250 00 2500 00 5000 00 10000 00 APPENDIX A DM6620HR SPECIFICATIONS A 2 DM6620HR Characteristics Typical 25 C Interface Switch selectable base address I O mapped Software programmable interrupts amp DMA channel D A Converter Analog sein 4 channels ReESOlUtON osos REI 12 bits Output ranges 2 0 O to 5 5 or O to 10 volts Relative accuracy co tabe ias t1 bit max Full Scale ACCURACY tato ecd ete etn De pn lan 5 bits max Nonclinearity 2 1 ee at css 1 bit max Full scale settling 5 usec typ Output current ors atari 5 ma typ D A Sample Buffer FIFO Size each 2 404040 0 1024 samples Digital I O Number of lines 8 b
83. to 5 volts The coding for this output range is straight binary where a code of 0 outputs 0 volts and a code of all 1 s 4095 outputs 4 99878 volts 0 to 10 volts The coding for this output range is straight binary where a code of 0 outputs 0 volts and a code of all 1 s 4095 outputs 9 99756 volts 5 volts The coding for this output range is 2 s complement where a code of 0 outputs O volts a code of 0111 1111 1111 2047 outputs 4 99756 volts a code of 1000 0000 0000 2048 outputs 5 000000 volts and a code of all I s 4095 outputs 00244 volts 10 volts The coding for this output range is 2 s complement where a code of 0 outputs 0 volts a code of 0111 1111 1111 2047 outputs 9 99512 volts a code of 1000 0000 0000 2048 outputs 10 000000 volts and a code of all 1 s 4095 outputs 00488 volts DAC Update enable disable This bit is used to enable and disable the DAC update signal This allows loading of the FIFO s and simultaneous enabling to ensure synchronous operation BA 12 Load Sample Counter 3 Select DAC Update 16 bit operation Read A read provides a software trigger so that sample counter 3 can be loaded with the correct value This software correction is used as an easy means to compensate for the operating structure of the 8254 Two pulses of the counter are required to actually load the desired count and prepare the counter to count down correctly
84. ts Enable DAC4 Output DAC2 Output 0 disabled Range Range 1 enabled 0 to 5 volts 00 0 to 5 volts 01 0 to 10 volts 01 to 10 volts 10 5 volts 10 5 volts DAC3 Update 11 10 volts 11 10 volts Enable O disabled 1 enabled DAC Output Ranges 0 to 5 volts The coding for this output range is straight binary where a code of 0 outputs 0 volts and a code of all 1 s 4095 outputs 4 99878 volts 0 to 10 volts The coding for this code of all I s 4095 outputs 9 99756 volts output range is straight binary where a code of 0 outputs 0 volts and a 5 volts The coding for this output range is 2 s complement where a code of 0 outputs 0 volts a code of 0111 1111 1111 2047 outputs 4 99756 volts a code of 1000 0000 0000 2048 outputs 5 000000 volts and a code of all 1 s 4095 outputs 00244 volts 10 volts The coding for this output range is 2 s complement where a code of 0 outputs 0 volts a code of 0111 1111 1111 2047 outputs 9 99512 volts a code of 1000 0000 0000 2048 outputs 10 000000 volts and a code of all 1 s 4095 outputs 00488 volts DAC Update enable disable This bit is used to enable and disable the DAC update signal This allows loading of the FIFO s and simultaneous enabling to ensure synchronous operation 5 3 DAC Update Register BA 12 DACA Cycle DAC3 Cycle 0 no cycle 0 no cycle 1 cycle 1 cycl
85. tter what programming language you are using Even if you are writing your ISR in assembly language DOS and many floating point emulators are not reentrant Of course there are ways around this problem such as those which involve checking to see if any DOS functions are currently active when your ISR is called but such solutions are well beyond the scope of this discussion The second major concern when writing your ISR is to make it as short as possible in terms of execution time Spending long periods of time in your ISR may mean that other important interrupts are being ignored Also if you spend too long in your ISR it may be called again before you have completed handling the first run This often leads to a hang that requires a reboot Your ISR should have this structure Push any processor registers used in your ISR Most C and Pascal interrupt routines automatically do this for you Put the body of your routine here Issue the EOI command to the 8259 interrupt controller by writing 20H to port 20H and port AOH if you are using 8 15 Pop all registers pushed on entrance Most C and Pascal interrupt routines automatically do this for you The following C and Pascal examples show what the shell of your ISR should be like In C void interrupt ISR void Your code goes here Do not use any DOS functions outportb 0x20 0x20 Send EOI command to 8259A for all IROs outportb 0x20 0
86. urrent code segment CS instruction pointer IP and flags are pushed on the stack for storage and a new CS and IP are loaded from a table that exists in the lowest 1024 bytes of memory This table is referred to as the interrupt vector table and each entry is called an interrupt vector Once the new CS and IP are loaded from the interrupt vector table the processor begins executing the code located at CS IP When the interrupt routine is completed the CS IP and flags that were pushed on the stack when the interrupt occurred are now popped from the stack and execution resumes from the point where it was interrupted Using Interrupts in Your Programs Adding interrupts to your software is not as difficult as it may seem and what they add in terms of perfor mance is often worth the effort Note however that although it is not that hard to use interrupts the smallest mistake will often lead to a system hang that requires a reboot This can be both frustrating and time consuming But after a few tries you ll get the bugs worked out and enjoy the benefits of properly executed interrupts In addition to reading the following paragraphs study the example programs included on your DM6620 program disk for a better understanding of interrupt program development Writing an Interrupt Service Routine ISR The first step in adding interrupts to your software is to write the interrupt service routine ISR This is the routine that will automatica
87. utput dataModule turns your IBM AT compatible cpuModule or other PC 104 computer into a high speed high performance waveform generator and control system Ultra compact for embedded and portable applications the DM6620 module features Four fast settling 12 bit analog output channels 5 10 0 to 5 or 0 to 10 volt software programmable analog output range Four 1024 sample D A buffers for gap free high speed output under WindowsTM and DOS Simultaneous updating of all output channels Cycle mode for waveform generation DMA transfer 3 independent sample counters 4 bit analog output data trigger marker 8 bit programmable digital I O lines with Advanced Digital Interrupt modes 8 port programmable digital I O lines Six 16 bit timer counters three available to user and on board 8 MHz clock 5 volt only operation 2 1W power consumption Windows example programs in Visual Basic and C DOS example programs with source code in BASIC and C Diagnostics software The following paragraphs briefly describe the major functions of the module A detailed discussion of module functions is included in subsequent chapters Digital to Analog Conversion The digital to analog D A circuitry features four independent 12 bit analog output channels with individu ally programmable output ranges of 5 to 5 volts 0 to 5 volts 10 to 10 volts or 0 to 10 volts Each channel has it s own 1024 sample buffer for data
88. values and a write is ignored For all bits set as outputs a read reads the last value sent out on the line and a write writes the current loaded value out to the line Note that when any reset of the digital circuitry is performed clear chip or computer reset all digital lines are reset to inputs and their corresponding output registers are cleared BA 29 Digital I O Port 1 Byte Programmable Port 8 bit Operation Read Write Port 1 P1 7 P1 6 P1 5 P1 4 P1 3 P1 2 P1 1 P1 1 This port transfers the 8 bit Port 1 digital input or digital output byte between the module and an external device When Port 1 is set as inputs a read reads the input values and a write is ignored When Port 1 is set as outputs a read reads the last value sent out of the port and a write writes the current loaded value out of the port Note that when any reset of the digital circuitry is performed clear chip or computer reset all digital lines are reset to inputs and their corresponding output registers are cleared BA 30 Read Program Port 0 Direction Mask Compare Registers 8 bit Operation Read Write A read clears the IRQ status flag or provides the contents of one of digital 1 O Port 0 s three control registers and a write clears the digital chip or programs one of the three control registers depending on the setting of bits 0 and 1 at BA 30 When bits 1 and 0 at BA 30 are 00 the read write operations clear the digital IRQ status flag read an

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