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1. 44 4 1 3 WO Port Data Direction 44 4 1 4 VO Port Data Registers 44 4 1 5 Safe I O State Switching 45 42 TIMER eee RUE PU LSU a anyone 47 4 2 1 Timer Operating 48 422 Gated e e E YES 48 4 2 3 Clock Input AB 4 2 4 Qutp t Mode s zer a ae ee e EI PE FEET SE iS 48 4 2 5 Timer Interr pt sic wr eIS Sa ace 48 4 2 6 Application NOES er oam Eee MAE er Eu A ERA E Yr Co Ae 4 2 7 Timer Registers sco osa a wi d GAD 4 3 A D CONVERTER ADC a 6 ione Rem Each Rom PER EE Re ere 50 4 3 1 Application 50 5 an We 52 5 1 ST6 ARGHITECTURE 2 55 55 5 a an betwee ae Wola a vi a ayin 52 5 2 ADDRESSING MODES i ocenenie ns Kee ki Se EE 52 5 3 INSTRUCTION SET eub nua gk edP 53 6 ELECTRICAL 8 5
2. 58 6 1 ABSOLUTE MAXIMUM 5 58 6 2 RECOMMENDED OPERATING 6 59 6 3 DC TELECTRICAL CHARACTERISTICS 60 6 4 AC TELECTRICAL CHARACTERISTICS 61 6 5 READOUT PROTECTION 63 7 GENERAL 64 7 1 PACKAGE MECHANICAL 64 7 2 ORDERING INFORMATION 67 7 2 1 Transfer of Customer 1 67 7 2 2 Listing Generation and Verification 67 4 68 7424237 008015b 797 Mi 1 GENERAL DESCRIPTION 1 1 INTRODUCTION The ST62T10 T15 20 and T25 devices are low cost members of the 8 bit ST62xx family of microcontrollers which is targeted at low to me dium complexity applications All 5 62 devices are based on a building block approach a com mon core is surrounded by a number of on chip peripherals The 5 62 20 device is an erasable EPROM ver sion of the ST62T20 device which may be used to emulate the T10 and T20 devices as well as the respective ST6210B and 20B ROM devices The ST62E25 device is an erasable EPROM ve
3. 9 431 l OPORIS sie Sine Fae ee eS ee eal Beate dee ole BENING Re 9 4 2 TIMER Saute n ec HW ote hie OW 9 4 3 A D CONVERTER 9 5 2 52245 5 8 ete Bin eee ole RR KASS RU RR RR eee ae ee EUR 8 n 9 5 1 STe ARCHITECTURE err wees De ead 2 9 5 2 ADDRESSING 9 5 3 INSTRUCTION Rn pU RR Ea bonbe gon e DOE zo eA E 9 6 ELECTRICAL 5 5 10 6 1 ABSOLUTE MAXIMUM RATINGS EHE 10 6 2 RECOMMENDED OPERATING 5 11 7 GENERAL 12 7 1 PACKAGE MECHANICAL 12 7 2 ORDERING 15 2 68 STA EN 7929237 0080154 914 MH Table of Contents ST6210B 15B 20B 25 417 1 GENERAL DESCRIPTION aa aw de a aaa Y ma a E S ood 14 INTRODUCTION 5 essa e ER ev E a 18 1 2 PIN DESCRIPTION 5 eed eee es Bon AD t3 MEMORY rer rater De ee Ve
4. 60 to 150 1 Within these limits clamping diodes are non conducting Voltages outside these limits are authorised provided injection current is kept within the specification 2 The total current through ports A and B combined may not exceed 50mA The total current through port C combined may not exceed 50mA If the application is designed with care and observing the limits stated above total current may reach 100mA THERMAL CHARACTERISTIC PDIP20 PDIP28 10 68 4 7424237 0080152 730 5762710 T15 T20 T25 ST62E20 E25 6 2 RECOMMENDED OPERATING CONDITIONS Value Symbol Parameter Test Conditions 220 MN tin pie 6 Suffix Version se Dx essen 1 7 Pin Injection Current positive Digital Input Vpp 4 5 to 5 5V Analog Inputs Pin Injection Current negative Digital Input Vop 4 5 to 5 5V Analog Inputs Notes If a total current of 1mA is flowing into a single analog channel or if the total current flowing into all the analog inputsis 1mA all resulting A D conversions will be shifted by 1 LSB If a total positive current is flowing into a single analog channel or if the total current flowing into all analog inputs is 5mA all the resulting conversions are shifted by 2 LSB Figure 6 MAXIMUM OPERATING FREQUENCY VERSUS SUPPLY VOLTAGE Maximum FREQUENCY MHz 4 5 5 Supply Voltage Vo VRO1807H Note The
5. Indirect Indirect AN Direct SN DEC X Short Direct gt gt gt gt gt gt gt gt gt gt gt gt gt gt DEC Y Short Direct DEC V Short Direct DEC W Short Direct DEC A Direct DEC Direct DEC X Indirect DEC Y Indirect INC X Short Direct 4 INC Y Short Direct 4 INC V Short Direct 4 INC W Short Direct 4 4 INC rr 4 Indirect 4 INC Y Indirect 1 4 mea 7 mem 4 4 SLA A Inherent 2 4 A A SUB A Indirect 1 4 A A SUB A Y Indirect 1 4 A A SUB A rr Direct 2 4 A A sunam immedate Notes X Y Indirect Register Pointers V amp W Short Direct RegistersD Affected Immediate data stored in ROM memory Not Affected rr Data space register 54 68 4 7929237 0080206 042 Mi ST6210B 15 20 25 INSTRUCTION SET Cont d Conditional Branch The branch instructions Control Instructions The control instructions achieve a branch in the program when the select control the MCU operations during program exe ed condition is met cution Bit Manipulation Instructions These instruc Jump and Call These two instructions are used tions can handle any bit in data space memory to perform long 12 bit jumps or subroutines call One group either sets or clears The other group inside the whole program s
6. c a Q c c c DIS zm 2 Nis N N So 8 ols JRC 4 per pre Legend Indicates Instructions e 5 Bit Displacement A b 3 Bit Address aide Mnemonic 1byte dataspace address Operand nn 1 byte immediate data abc 12 bit address Bytes ee 8 bit Displacement Addressing Mode 57 68 7421047 0080209 851 AM ST6210B 15 20 25 6 ELECTRICAL CHARACTERISTICS 6 1 ABSOLUTE MAXIMUM RATINGS This product contains devices to protect the inputs Power ConsiderationsThe average chip junc against damage due to high static voltages how tion temperature Tj in Celsius be obtained ever it is advisable to take normal precaution to from avoid application of any voltage higher than the PD x RthJA specified maximum rated voltages Where TA ient T For proper operation it is recommended that Temperature and Vo be higher than Veg and lower than RthJA Package thermal resistance junc Reliability is enhanced if unused inputs are con tion to ambient nected to an appropriate logic voltage level PD z Pint Pport or Vss Pint IDD x VDD chip internal power Ppor Port power dissipation determined by the user Drain per Pin Fin Injection curent negative Al VO VD 45V 5 _ Wa Total Current out of VBS A Notes Stresses above those listed as absolute ma
7. see Table 10 the clock input of the timer counter register is multiplexed to different sources For di vision factor 1 the clock input of the prescaler is also that of timer counter for factor 2 bit 0 of the prescaler register is connected to the clock input of TCR This bit changes its state at half the fre quency of the prescaler input clock For factor 4 bit 1 of the PSC is connected to the clock input of TCR and so forth The prescaler initialize bit PSI in the TSCR register must be set to 1 to allow the prescaler and hence the counter to start If it is cleared to 0 all the prescaler bits are set to 1 and the counter is inhibited from counting The prescaler can be loaded with any value between 0 and 7Fh if bit PSI is set to 1 The prescaler tap is selected by means of the PS2 PS1 PSO bits in the control register Figure 27 illustrates the Timer s working principle DATABUS 8 8 BIT 56 b5 ba 63 b2 bi COUNTER LOGIC p 792923 0080199 STATUS CONTROL REGISTER VA00009 47 68 ST6210B 15 20 25 Cont d 4 2 1 Operating Modes There are three operating modes which are se lected by the TOUT and DOUT bits see TSCR register These three modes correspond to the two clocks which can be connected to the 7 bit prescaler fnr 12 TIMER pin signal and to the output mode 4 2 2 Gated Mode TOUT 0
8. DOUT 1 In this mode the prescaler is decremented by the Timer clock input fyr 12 but ONLY when the signal on the TIM pin is held high allowing pulse width measurement This mode is selected by clearing the TOUT bit in the TSCR register to 0 i e as input and setting the DOUT bit to 1 4 2 3 Clock Input Mode TOUT 0 DOUT 0 this mode the pin is an input and the prescaler is decremented on the rising edge 4 2 4 Output Mode TOUT 1 DOUT data out The TIMER pin is connected to the DOUT latch hence the Timer prescaler is clocked by the pres caler clock input inr 12 Figure 27 Timer Working Principle 48 68 7129237 0080200 b24 EN The user select the desired prescaler division ratio through the PS2 PS1 PSO bits When the TCR count reaches 0 it sets the TMZ bit in the TSCR The TMZ bit can be tested under program control to perform a timer function whenever it goes high The low to high TMZ bit transition is used to latch the DOUT bit of the TSCR and trans fer itto the TIMER pin This operating mode allows external signal generation on the TIMER pin Table 9 Timer Operating Modes TOUT DOUT 0 Input Event Counter input Gated Input Output Output 0 Output Output 1 4 2 5 Timer Interrupt When the counter register decrements to zero with the ETI Enable Timer Interrupt bit set to one an interrupt req
9. ST62E20 E25 lowest power consumption by stopping all CPU activity For a complete description refer topage 41 4 PERIPHERALS 4 1 VO PORTS Input Output lines may be individually pro grammed as one of a number of different configu rations For further details refer topage 43 4 2 TIMER The on chip Timer peripheral consists of an 8 bit counter with a 7 bit programmable prescaler giv ing a maximum count of 2 For a complete de scription refer to page 47 4 3 A D CONVERTER ADC The 8 bit on chip ADC features multiplexed ana log inputs as alternate functions Conversion is by successive approximations with a typical conversion time of 70 5 at 8MHz oscillator fre quency For a complete description refer topage 50 5 SOFTWARE 5 1 ST6 ARCHITECTURE The ST6 architecture has been designed to exploit the hardware in the most efficient way possible while keeping byte usage to a minimum For fur ther details refer topage 52 5 2 ADDRESSING MODES The ST6 core offers nine addressing modes Im mediate Direct Short Direct Extended Program Counter Relative Bit Direct Bit Test amp Branch In direct and Inherent For a complete description of the available addressing modes refer topage 52 5 3 INSTRUCTION SET The ST6 core offers a set of 40 basic instructions which when combined with nine addressing modes yield 244 usable opcodes these may be subdivided into six types load store
10. an asynchronous event the user cannot know the context and the time at which it occurred As a sult the user should save all Data space registers which may be used within the interrupt routines There are separate sets of processor flags for nor mal interrupt and non maskable interrupt modes which are automatically switched and so do not need to be saved The following list summarizes the interrupt proce dure MCU The interrupt is detected and Z flags are replaced by the interrupt flags or by the NMI flags The PC contents are stored in the first level of the stack The normal interrupt lines are inhibited still active The first internal latch is cleared The associated interrupt vector is loaded in the PC User User selected registers are saved within the in terrupt service routine normally on a software stack The source of the interrupt is found by polling the interrupt flags if more than one source is asso ciated with the same vector The interrupt is serviced Return from interrupt RETI ST6210B 15B 20 25 MCU Automatically the MCU switches back to the nor mal flag set or the interrupt flag set and pops the previous PC value from the stack The interrupt routine usually begins by the identi fying the device which generated the interrupt re quest by polling The user should save the regis ters which are used wit
11. arithme tic logic conditional branch control jump call and bit manipulation For further details refer to page 53 9 68 EN 732323 00580151 054 NE ST62T10 T15 T20 T25 ST62E20 E25 6 ELECTRICAL CHARACTERISTICS 6 1 ABSOLUTE MAXIMUM RATINGS This product contains devices designed to protect the inputs against damage due to high static volt ages however it is advisable to take normal pre cautions to avoid applying voltages higher than the specified maximum ratings For proper operation it is recommended that V and Vo be higher than Vss and lower than Reliability is enhanced if unused inputs are con nected to an appropriate logic voltage level Or Power Considerations The average chip junc tion temperature in degrees Celsius can be ob tained from T TA x RinJA Where Ambient Temperature Rinja Package thermal resistance junction to ambient Pp Pint Pport Pint lpp Vpp chip internal power Poort Port power dissipation to be determined by the user Notes Stresses above those listed as Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only 6 and functional operation of the device under these conditions is not implied Exposure to maximum rating conditions for extended perio may affect device reliability Value 0 3 to 7 0 Vss 0 310 Vpp 0 30 Vss 0 3 to Vpp 0 3 13 0 5 500 50
12. tine cannot save and then restore its previous con tent If it is impossible to avoid the writing of this register in the interrupt service routine an image of this register must be saved in a RAM location and each time the program writes to the DWR it must write also to the image register The image register must be written first so if an interrupt oc curs between the two instructions the DWR is not affected 0 PROGRAM SPACE ADDRESS ol READ 5 4 3 2 1 0 DATA SPACE ADDRESS Example DWR 28h ZZ PUPPI 2 40h 7Fh IN INSTRUCTION DATA SPACE ADDRESS 59h aporess aton ZAZA o o o 110 of 4 5 7929237 0080175 649 VRO1573C 23 68 ST6210B 15B 20 25 2 CENTRAL PROCESSING UNIT 2 1 INTRODUCTION The CPU Core of ST6 devices is independent of the or Memory configuration As such it may be thought of as an independent central processor communicating with on chip Memory and Pe ripherals via internal address data and control buses In core communication is arranged as shown in Figure 9 the controller being externally linked to both the Reset and Oscillator circuits while the core is linked to the dedicated on chip pe ripherals via the serial data bus and indirectly for interrupt purposes through the control registers 2 2 CPU REGISTERS The ST6 Family CPU core features six registers and three pairs of flags available to the programmer These
13. 0 TO 70 C ST62E25F1 HWD Hardware Watchdog ST62E25F1 SWD Software Watchdog Software Watchdog EN 7125237 0080167 5226275 5762710 T15 T20 T25 ST62E20 E25 M M Notes A NN 7929237 0080168 409 NM sO SGS THOMSON YA MICROELECTRONICS ST6210B 15B 20B 25B 12 20 VO pins fully programmable as 8 bit A D Converter with 8 ST6210B ST6220B a Power on Reset a One external Non Maskable Interrupt a ST626x EMU2 Emulation and Development DEVICE SUMMARY DEVICE ST6210B ST6220B ST6215B ST6225B 8 BIT HCMOS MCU WITH A D CONVERTER 3 0 to 6 0V Supply Operating Range 8 MHz Maximum Clock Frequency 40 to 85 C Operating Temperature Range Run Wait and Stop Modes 5 Interrupt Vectors Look up Table capability in ROM Data ROM User selectable size in program ROM Data RAM 64 bytes PDIP28 ROM read out Protection Input with pull up resistor Input without pull up resistor Input with interrupt generation Open drain or push pull output Analog Input 4 I O lines can sink up to 20mA to drive LEDs or TRIACS directly 8 bit Timer Counter with 7 bit programmable PDIP20 prescaler Digital Watchdog Oscillator Safe Guard and 16 ST6215B ST6225B analog inputs On chip Clock oscillator can be driven by Quartz crystal Ceramic resonator or RC network System connects to an MS D
14. 1 to the Start bit STA in the ADC control register This auto matically clears resets to 0 the End Of Conver sion Bit EOC When a conversion is complete the EOC bit is automatically set to 1 in order to flag that conversion is complete and that the data in the ADC data conversion register is valid Each conversion has to be separately initiated by writing to the STA bit The STA bit is continuously scanned so that if the user sets it to 1 while a previous conversion is in progress a new conversion is started before com pleting the previous one The start bit STA is a wile only bit any attempt to read it will show a log ical 0 The A D converter features a maskable interrupt associated with the end of conversion This inter rupt is associated with interrupt vector 4 and oc curs when the EOC bit is set i e when a conver sion is completed The interrupt is masked using the EAI interrupt mask bit in the control register The power consumption of the device can be re duced by turning off the ADC peripheral This is done by setting the PDS bit in the ADC control register to 0 If PDS 1 the A D is powered and enabled for conversion This bit must be set at least one instruction before the beginning of the conversion to allow stabilisation of the A D con 50 68 verter This action is also needed before entering WAIT mode since the A D comparator is not auto matically disable
15. 20 25B 3 3 2 Application Notes The Watchdog plays an important supporting role in the high noise immunity of ST62xx devices and should be used wherever possible Watchdog re lated options should be selected on the basis of a trade off between application security and STOP mode availability When STOP mode is not required hardware acti vation without EXTERNAL STOP MODE CON TROL should be preferred as it provides maxi mum security especially during power on When STOP mode is required hardware activa tion and EXTERNAL STOP MODE CONTROL should be chosen NMI should be high by default to allow STOP mode to be entered when the MCU is idle The NMI pin can be connected to PBO seeFigure 20 to allow its state to be controlled by software PBO can then be used to keep NMI low while Watchdog protection is required or to avoid noise or key bounce When no more processing is re quired PBO is released and the device placed in STOP mode for lowest power consumption When software activation is selected and the Watchdog is not activated the downcounter may be used as a simple 7 bit timer remember that the bits are in reverse order The software activation option should be chosen only when the Watchdog counter is to be used as a timer To ensure the Watchdog has not been un expectedly activated the following instructions should be executed within the first 27 instructions jrr 0 WD 3 141 WD OFDH 35 68 ST621
16. 44 68 With pull up no interrupt Reset state No pull up no interrupt With pull up and with interrupt ee l e pio Ss Te 1 1 No pull up no interrupt PAO PA3 pins pa pe Analog input PA4 PA7 PBO PB7 PC4 PC7 pins 20mA sink open drain output PAO PAS pins Standard open drain output PA4 PA7 PBO PB7 PC4 PC7 pins Output 20mA sink push pull output PAO PAS pins should be programmed as an analog input at any time since by selecting more than one input si multaneously their pins will be effectively shorted 4 1 2 Port Option Registers ORA B C CDh PB Read Write 7 0 EE ed Bit 7 0 Px7 0 Port A B and C Option Reg ister bits 4 1 3 Port Data Direction Registers DDRA B C C4h PA C5h PB C6h PC Read Write 7 0 es po Bit 7 0 Px7 Px0 Port A B and Data Direction Registers bits 4 1 4 I O Port Data Registers DRA B C PA C1h PB C2h Read Write 7 0 per ne re m re m nn Bit 7 0 Px7 Px0 Port A B and C Data Regis ters bits 4 7524237 0080196 373 VO PORTS 4 1 5 Safe State Switching Sequence Switching the I O ports from one state to another should be done in a sequ
17. 7 0 jor fos fos oe os KA Bit 7 0 07 00 Counter Bits Prescaler Register PSC Address OD2h Read Write 7 0 Bit 7 D7 Always read as 0 Bit 6 0 D6 DO Prescaler Bits 49 68 7424237 0080201 560 Mi ST6210B 15B 20B 25B 4 3 A D CONVERTER ADC The A D converter peripheral is an 8 bit analog to digital converter with analog inputs as alternate functions the number of which is device de pendent offering 8 bit resolution with a typical conversion time of 70us at an oscillator clock fre quency of 8 2 The ADC converts the input voltage by a process of successive approximations using a clock fre quency derived from the oscillator with a division factor of twelve With an oscillator clock frequency less than 1 2MHz conversion accuracy is de creased Selection of the input pin is done by configuring the related I O line as an analog input via the Op tion and Data registers refer to ports descrip tion for additional information Only one I O line must be configured as an analog input at any time The user must avoid any situation in which more than one I O pin is selected as an analog input si multaneously to avoid device malfunction The ADC uses two registers in the data space the ADC data conversion register ADR which stores the conversion result and the ADC control regis ter ADCR used to program the ADC functions A conversion is started by writing a
18. Normal operation another pair is used dur ing Interrupt mode 71 and a third pair is used ne Non Maskable Interrupt mode CNMI ZN The ST6 CPU uses the pair of flags associated with the current mode as soon as an interrupt or a Non Maskable Interrupt is generated the ST6 CPU uses the Interrupt flags resp the NMI flags instead of the Normal flags When the RETI in struction is executed the previously used set of flags is restored It should be noted that each flag set can only be addressed in its own context Non Maskable Interrupt Normal Interrupt or Main rou tine The flags are not cleared during context switching and thus retain their status The Carry flag is set when a carry or a borrow oc curs during arithmetic operations otherwise it is cleared The Carry flag is also set to the value of the bit tested in a bit test instruction it also partic ipates in the rotate left instruction The Zero flag is set if the result of the last arithme tic or logical operation was equal to zero other wise it is cleared Switching between the three sets of flags is per formed automatically when an NMI an interrupt or a RETI instructions occurs As the NMI mode is 7124237 008017 u11 AM ST6210B 15B 20B 25B automatically selected after the reset of the MCU the ST6 core uses at first the NMI flags Stack The ST6 CPU includes a true LIFO hard ware stack which eliminates the need for a stack pointer
19. T15 T20 T25 ST62E20 25 11 1 GENERAL DESCRIPTION uh sew whe n ape 5 Ist INTRODUCTION erexit RE cede ice eee a Ee RE Re 5 1 2 PIN DESCRIPTION 2s errore ER x ER X E RA ER Rer Reo de 6 1 3 MEMORY MAPS o 9 ENDE qe e UU KR ba ee is 7 1 3 1 Program Memory Maps 7 1 32 Data Spaces sud ee ea ET aaa eh RR RE RUP Y RR Ron a 7 1 4 PARTICULARITIES OF OTP AND EPROM 8 1 4 1 OTP EPROM Programming B 1 4 2 Eprom Erasure secede oe v RR Ue eeu Ta eU bie wee LES DN E 8 2 CENTRAL PROCESSING 9 9 23 52 334 ees ai er p mes e RP RR EET RAE 9 22 CPU REGISTERS ccrte ERR EA Uer ES KR RUE Sale wee hae RUE 9 3 CLOCKS RESET INTERRUPTS AND POWER SAVING MODES 9 3 3 CLOCK SYSTEM ry Aet boo de rd b RE e aie 9 3 2 RESETS pp 9 3 3 DIGITAL 9 3 4 INTERRUPTS e Gilden eda hd TQ 9 3 5 POWER SAVING 5 9 4 ON CHIP 5
20. be accepted 1 3 3 Data Space Data Space accommodates all the data necessary for processing the user program This space com prises the RAM resource the processor core and peripheral registers as well as data such as constants and look up tables in ROM Figure 7 ST6220B 25B Program Memory Map RESERVED USER PROGRAM MEMORY ROM 3872 BYTES RESERVED INTERRUPT VECTORS RESERVED NMI VECTOR USER RESET VECTOR 21 68 ST6210B 15 20 25B MEMORY MAP Cont d 1 3 3 1 Data ROM All read only data is priysicaly stored in ROM memory which also accommodates the Program Space The ROM memory consequently contains the program code to be executed as well as the constants and look up tables required by the ap plication The Data Space locations in which the different constants and look up tables are addressed by the processor core may be thought of as a 64 byte window through which it is possible to access the read only data stored in ROM 1 3 3 2 Data RAM ST6210B 576215 ST6220B and ST6225B devices the data space includes 60 bytes of RAM the accumulator A the indirect registers X Y the short direct registers W the port reg isters the peripheral data and control registers the interrupt option register and the Data ROM Window register DRW register 1 3 4 Stack Space Stack space consists of six 12 bit registers which are used to stack subro
21. changes to 0 This offers the user a choice of 64 timed periods ranging from 3 072 to 196 608 clock cycles with an oscillator frequency of 8MHz this is equivalent to timer pe riods ranging from 384 to 24 576ms WATCHDOG COUNTER o T s Q W Q a I lt 34 68 7574 ee 7525037 424 DIGITAL WATCHDOG Cont d 3 3 1 Digital Watchdog Register DWDR Address OD8h Read Write Reset status 1111 1110b 7 0 Bit 0 C Watchdog Control bit If the hardware option is selected this bit is forced high and the user cannot change it the Watchdog is always active When the software option is se lected the Watchdog function is activated by set ting bit C to 1 and cannot then be disabled save by resetting the MCU When C is kept low the counter can be used as a 7 bit timer This bit is cleared to 0 on Reset Bit 1 SR Software Reset bit This bit triggers a Reset when cleared When C 0 Watchdog disabled itis the MSB of the 7 bit timer This bit is set to 1 on Reset Bits 2 7 5 0 Downcounter bits It should be noted that the register bits are re versed and shifted with respect to the physical counter bit 7 TO is the LSB of the Watchdog downcounter and bit 2 T5 is the MSB These bits are set to 1 on Reset 7929237 01080187 350 ST6210B 15B
22. chip and peripherals For further details refer to page 18 2 2 CPU REGISTERS The CPU Core features six registers and three pairs of flags available to the programmer For a detailed description refer topage 24 3 CLOCKS RESET INTERRUPTS AND POWER SAVING MODES 3 1 CLOCK SYSTEM The Oscillator may be driven by an external clock ar by a crystal or ceramic resonator ROM devices also offer RC oscillator and Oscillator Safeguard features For a complete description refer topage 26 3 2 RESETS The MCU can be reset in three ways by the exter nal Reset input being pulled low by the Power on Reset circuit or by the Digital Watchdog timing out For further details refer topage 30 3 3 DIGITAL WATCHDOG The Digital Watchdog can be used to provide con trolled recovery from software upsets Software and Hardware enabled Watchdog options are available in order to achieve optimum trade off be tween power consumption and noise immunity For a complete description and a selection guide refer to page 33 3 4 INTERRUPTS The CPU can manage four Maskable and one Non Maskable Interrupt source Each source is associated with a specific Interrupt Vector An in ternal pullup option on the NMI pin is available on ROM devices For a complete description refer to page 37 3 5 POWER SAVING MODES WAIT mode reduces electrical consumption dur ing idle periods while STOP mode achieves the ST62T10 15 T20 T25
23. chip as the micro processor the user should not switch heavily loaded output signals during conversion if high precision is required Such switching will affect the supply voltages used as analog references The accuracy of the conversion depends on the quality of the power supplies and Vss user must take special care to ensure a well regu lated reference voltage is present on the and Vss pins power supply voltage variations must be less than 5V ms This implies in particular that a suitable decoupling capacitor is used at the V5p pin The converter resolution is given by Voo Vss 256 The input voltage Ain which is to be converted must be constant for ius before conversion remain constant during conversion Conversion resolution can be improved if the pow er supply voltage Vpp to the microcontroller is lowered In order to optimise conversion resolution the user can configure the microcontroller in WAIT mode because this mode minimises noise distur bances and power supply variations due to output switching Nevertheless the WAIT instruction should be executed as soon as possible after the beginning of the conversion because execution of the WAIT instruction may cause a small variation of the Vpp voltage The negative effect of this var lation is minimized at the beginning of the conver sion when the converter is less sensitive rather than at the end of conversion when the less s
24. gm 792923 00801388 lib MM e kr 4 2 The MCU features an on chip Timer peripheral consisting of an 8 bit counter with a 7 bit program mable prescaler giving a maximum count of 25 peripheral may be configured three differ ent operating modes Figure 26 shows the Timer Block Diagram The external TIMER pin is available to the user The content of the 8 bit counter can be read written in the Timer Counter register TCR which can be addressed in Data space as a RAM location at ad dress OD3h The state of the 7 bit prescaler can be read in the PSC register at address OD2h control logic device is managed in the TSCR reg ister as described in the following paragraphs The 8 bit counter is decrement by the output ris ing edge coming from the 7 bit prescaler and can be loaded and read under program control When it decrements to zero then the TMZ Timer Zero bit in the TSCR is set to 1 Ifthe ETI Enable Tim er Interrupt bit in the TSCR is also set to 1 an interrupt request associated with interrupt vector 3 is generated The Timer interrupt can be used to exit the MCU from WAIT mode Figure 26 Timer Block Diagram ST6210B 15B 20B 25B The prescaler input can be the internal frequency divided by 12 or an external clock applied to the TIMER pin The prescaler decrements on the rising edge Depending on the division factor pro grammed by PS2 PS1 and PSO bits in the TSCR
25. input HARDWARE WATCHDOG 33 68 5 6210 15 20 25 DIGITAL WATCHDOG Cont d The Watchdog is associated with a Data space Figure 19 Watchdog Counter Control register Digital WatchDog Register DWDR loca tion OD8h which is described in greater detail in Section 3 3 1 This register is set to OFEh on Re set bit C is cleared to 0 which disables the Watchdog the timer downcounter bits TO to T5 and the SR bit are all set to 1 thus selecting the longest Watchdog timer period This time period can be set to the user s requirements by setting the appropriate value for bits TO to T5 in the DWDR register The SR bit must be set to 1 since it is this bit which generates the Reset signal when it changes to 0 clearing this bit would gen erate an immediate Reset It should be noted that the order of the bits in the DWDR register is inverted with respect to the as sociated bits in the down counter bit 7 of the DWDR register corresponds in fact to TO and bit 2 to T5 The user should bear in mind the fact that these bits are inverted and shifted with respect to the physical counter bits when writing to this regis ter The relationship between the DWDR register bits and the physical implementation of the Watch dog timer downcounter is illustrated inFigure 19 Only the 6 most significant bits may be used to de fine the time period since it is bit 6 which triggers the Reset when it
26. level is seen by the OSG as spikes it therefore filters out some cycles in order that the internal clock fre quency of the device is kept within the range the particular device can stand depending on V5p and below 9 the maximum authorised fre quency with 55 enabled Note The OSG should be used wherever possi ble as it provides maximum safety Care must be taken however as it can increase power con sumption and reduce the maximum operating fre quency to fose NH 792923 0040179 294 2788 ST6210B 15B 20 25 CLOCK SYSTEM Cont d Figure 12 OSG Filtering 1 Maximum Frequency for the device to work correctly 2 Actual Quartz Crystal Frequency at OSCin pin 3 Noise from OSCin 4 Resulting Internal Frequency VROO1932 13 OSG Emergency Oscillator Principle Main Oscillator Emergency Oscillator Internal Frequency VR001933 8 68 Mi 792923 0080160 TOL EN ST6210B 15 20 25 CLOCK SYSTEM Cont d Figure 14 Clock Circuit Block Diagram Core TIMER 1 MAIN Watchdog OSCILLATOR Main Oscillator off Figure 15 Maximum Operating Frequency fmax versus Supply Voltage Maximum FREQUENCY MHz NCTIONALITY IS NOT GUARANTEED IN THIS AREA SUPPLY VOLTAGE Vpp Notes 1 Inthis area operation is guaranteed at the quartz crystal frequency 2 When the OSG is disabled operation in this area is guaranteed at the cry
27. o c Do 2 gt b2 rr ee per JRNC 2 2 JRC e b6 rr ee per prc JRNC JRS 2 JRC e b6 rr ee per pre JRNC JRZ JRC e per prc JRNC JRC e par pre JRNC JRC e per per pre JRNG JRC e per per pre JRNC prc JRNC JRS JRZ JRC e b3 rr ee par pre JRNC JRR 2 2 e b7 rree JRNC 2 JRC e b7 rr ee per bt pre Abbreviations for Addressing Modes Legend dir Direct Indicates Illegal Instructions Short Direct it Displacement Immediate b 3 Bi hanes n Cycle Mnemonig inh Inherent rr 1byte dataspace address Operand ext Extended nn 1 byte immediate data bd Bit Direct abc 12bit anle Bytes bt Bit Test ee 8 bit Displacement per Program Counter Relative Rddressing Mods ind Indirect 56 68 ka 7525237 0080208 915 Opcode Map Summary Continued Abbreviations for Addressing Modes dir sd imm inh ext b d bt per ind per Direct Short Direct Immediate Inherent Extended Bit Direct Bit Test Program Counter Relative Indirect c 7 c o VA oo VA ajo ajo cio Bx c cio v Us UIA cim c 79 ejo Us Clo to J S ST6210B 15B 20B 25B JRZ per JRZ c 2 O per JRZ c 2 gt JAZ JRZ m pcr JRZ pcr JRZ per JRZ per JAZ pre JRC pre JRC pre JRC per JRZ e plo oja per c 2 N c D Oja 215 5
28. show a logical zero Bit 4 PDS Power Down Selection This bit acti vates the A D converter if set to 1 Writing a O to this bit will put the ADC in power down mode idle mode Bit 3 0 D3 DO Not used A D Converter Data Register ADR Address ODOh Read only 7 0 Bit 7 0 07 00 8 Bit A D Conversion Result 51 58 7425237 0080203 333 mi ST6210B 15 20 25B 5 SOFTWARE 5 1 ST6 ARCHITECTURE The ST6 software has been designed to fully use the hardware in the most efficient way possible while keeping byte usage to a minimum in short to provide byte efficient programming capability The ST6 core has the ability to set or clear any register or RAM location bit of the Data space with a single instruction Furthermore the program may branch to a selected address depending on the status of any bit of the Data space The bit is stored with the value of the bit when the SE or RES instruction is processed 5 2 ADDRESSING MODES The ST6 core offers nine addressing modes which are described in the following pare Three different address spaces are available Pro gram space Data space and Stack space Pro gram space contains the instructions which are to be executed plus the data for immediate mode in structions Data space contains the Accumulator the X Y V and W registers peripheral and In put Output registers the RAM locations and Data ROM locations for storage of tables and
29. the address of an operand The 12 bit xd jih allows the direct addressing of 4096 bytes rogram space 0 01 TO 8MHz MENN FLAG OPCODE VALUES 7 PROGRAM ROM EPROM A DATA B DATA 24 68 7121237 0040176 585 CON SIGNALS INTERRUPTS DATA SPACE DATA ADDRESS READ LINE RAM EEPROM DATA ADDRESS DECODER 259 ROM EPROM DEDICATIONS ACCUMULATOR RESULTS TO DATA SPACE WRITE LINE CPU REGISTERS Cont d However if the program space contains more than 4096 bytes the additional memory in pro gram space can be addressed by using the Pro gram Bank Switch register The PC value is incremented after reading the ad dress of the current instruction To execute rela tive jumps the PC and the offset are shifted through the ALU where they are added the result is then shifted back into the PC The program counter can be changed in the following ways JP Jump instructiorPC Jump address CALL instructionPC Call address Relative Branch InstructionPC PC offset Interrupt PC Interrupt vector ResetPC Reset vector RET amp RETI instructionsPC Pop stack Normal instructionPC PC 1 Flags C Z The ST6 CPU includes three pairs of flags Carry and Zero each pair being associated with one of the three normal modes of operation Normal mode Interrupt mode and Non Maskable Interrupt mode Each pair consists of a CARRY flag and a ZERO flag One pair CN ZN is used during
30. 0B 15 20 25B DIGITAL WATCHDOG Cont d These instructions test the C bit and Reset the MCU i e disable the Watchdog if the bit is set i e if the Watchdog is active thus disabling the Watchdog In all modes a minimum of 28 instructions are ex ecuted after activation before the Watchdog can generate a Reset Consequently user software should load the watchdog counter within the first 27 instructions following Watchdog activation software mode or within the first 27 instructions executed following a Reset hardware activation It should be noted that when the GEN bit is low in terrupts disabled the NMI interrupt is active but cannot cause a wake up from STOP WAIT modes Figure 21 Digital Watchdog Block Diagram DB 36 68 7125237 0080188 277 MM Figure 20 A typical circuit making use of the EXERNAL STOP MODE CONTROL feature SWITCH VRO2002 127 28 1 7 LOAD SET SET a OSCILLATOR CLOCK DATA BUS 00010 3 4 INTERRUPTS The CPU can manage four Maskable Interrupt sources in addition to a Non Maskable Interrupt source top priority interrupt Each source is as sociated with a specific Interrupt Vector which contains a Jump instruction to the associated in terrupt service routine These vectors are located in Program space see Table 4 When an interrupt source generates an interrupt request and interrupt processing is enabled the PC register is loaded with t
31. 1 3 2 5 MCU Initialization Sequence 31 3 8 DIGITAL 33 3 3 1 Digital Watchdog Register 35 3 3 2 Application 6 35 34 INTERRUPTS 2 a eo ene m Rumes dela Re a RC as 37 3 4 1 Interrupt Vectors hn 37 3 4 2 Interrupt 37 3 4 3 Interrupt Option Register 38 3 4 4 External Interrupt Operating 38 3 4 5 Interrupt Procedure 4 39 3 5 POWER SAVING 0 00 vl ne e eh e e n n n n 3 5 1 WAIT t me xa Ute acra aod oss deb rumen e 41 3 52 STOP Mode 2 224 cole e gee eee ee we dee cs ap 3 5 3 Exit from WAIT and STOP 42 ST 3 68 EN 7929237 008055 850 EN Table of Contents 4 PERIPHERALS 22 22 22 55 444 e maa Ra RR Rr nans 43 EE vet eeu eye e ERU S ORIS 43 AA Operating Modes eT Ra ne AR EU or got 4 1 2 I O Port Option
32. 125237 0080217 928 MEM ST6210B 15B 20 25 ST6210B ST6215B ST6220B and ST6225B MICROCONTROLLER OPTION LIST Customer Address Contact Phone No Reference SGS THOMSON Microelectronics references Device ST6210B ST6215B ST6220B ST6225B Package Dual in Line Plastic Small Outline Plastic In this case select conditioning Standard Stick Tape amp Reel Temperature Range 10 to 70 40 C to 85 C Special Marking No Authorized characters are letters digits and spaces only Maximum character count DIP20 DIP28 10 SO20 5028 8 Oscillator Source Selection Crystal Quartz Ceramic resonator Default RC Network Watchdog Selection Software Activation STOP mode available Hardware Activation no STOP mode OSG 1 Enabled Disabled Default Input pull up selection on NMI Yes No Input pull up selection on TIMER pin Yes No ROM Readout Protection Standard Fuse cannot be blown 1 Enabled Fuse can be blown by the customer Note No part is delivered with protected ROM The fuse must be blown for protection to be effective External STOP Mode Contro Enabled Disabled Default Comments Supply Operating Range in the application Oscillator Fequency in the application Notes Signature Date 868 99092357 0080218 aby M 4 571 7 2 ORDERING INFORMATION The following section deals wi
33. 20 E25 PACKAGE MECHANICAL DATA Cont d Figure 10 20 Pin Ceramic Dual In Line Package 300 mil Width mm P a pu en 2225 0 50 1 78 020 ___ 6 070 04 0 55 0016 16 022 0 22 0 31 fes Fe 229 27s poo for Lo es es paer rs VROC1725 Figure 11 28 Ceramic Dual In Line Package 600 mil Width For cse 2905 ES Per pisos pesepse pss Pi feof poral T Fer 229 ers poo fen Fe Jess 2 humer of Pins i 14 68 ga 7525237 b3b NN 1 M 5162110 T15 T20 T25 ST62E20 E25 7 2 ORDERING INFORMATION Table 1 OTP Device Sales 6 Sales Temperature range Package pee option Temperature rango Package ST62T 1 ST62T10B6 HWD Hardware Hardware Watchdog Hardware Watchdog 0B6 SWD Software Watchdog PDIP20 ST62T20B6 HWD m Hardware Watchdog ST62T20B6 SWD Software Watchdog ST6ZT10M6SWD Software Watchdog 40 C 85 C Software Watchdog e m Hardware Watchdog isis Hardware Watchdog Software Watchdog 65254 Hardware Watchdog Hardware Watchdog Software Watchdog Table 2 EPROM Device Sales Types EPROM Sales Type Temperature range Package Bytes ST62E20F1 HWD Hardware Watchdog CDIP20W a Software Watchdog 3884
34. FTWARE and EXTERNAL STOP MODE CONTROL see Table 3 In the SOFTWARE mask option the Watchdog is disabled until bit C of the DWDR register has been set When the Watchdog is disabled low power Stop mode is available Once activated the Watchdog cannot be disabled save by resetting the MCU Table 3 Recommended Mask Option Choices Stop Mode amp Watchdog 7929237 0020185 558 Mi ST6210B 15B 20 25B In the HARDWARE mask option the Watchdog is permanently enabled Since the oscillator will run continuously low power mode is not available The STOP instruction is interpreted as a WAIT in struction and the Watchdog continues to count down However when the EXTERNAL STOP MODE CONTROL mask option available in ROM ver sions only has been selected low power con sumption may be achieved in Stop Mode Execution of the STOP instruction is then gov erned by a secondary function associated with the NMI pin If a STOP instruction is encountered when the NMI pin is low it is interpreted as WAIT as described above however the STOP in struction is encountered when the NMI pin is high the Watchdog counter is frozen and the CPU en ters STOP mode When the MCU exits STOP mode i e when terrupt is generated the Watchdog resumes its activity Note when the EXTERNAL STOP MODE CON TROL mask option has been selected port PBO must be defined as an open drain output and PA2 as an
35. Guard OSG affords drasti cally increased operational integrity in ST62xx de vices The OSG circuit provides three basic func tions it filters spikes from the oscillator lines which would result in over frequency to the ST62 CPU it gives access to the Low Frequency Auxiliary Os cillator LFAO used to ensure minimum process ing in case of main oscillator failure to offer re duced power consumption or to provide a fixed frequency low cost oscillator finally it automati cally limits the internal clock frequency as func tion of supply voltage in order to ensure correct operation even if the power supply should drop The OSG is enabled or disabled by choosing the relevant OSG mask option It may be viewed as a filter whose cross over frequency is device de pendent Spikes on the oscillator lines result in an effective ly increased internal clock frequency the ab sence of an OSG circuit this may lead to an over frequency for a given power supply voltage The OSG filters out such spikes as illustrated inFig ure 12 In all cases when the OSG is active the maximum internal clock frequency fnr is limited to fosa which is supply voltage dependent This relationship is illustrated inFigure 15 When the OSG is enabled the Low Frequency Auxiliary Oscillator may be accessed This oscilla tor starts operating after the first missing edge of the main oscillator seeFigure 13 Over frequency at a given power supply
36. MICROELECTRONICS SI SGS THOMSON 5762710 T15 T20 T25 5 62 20 E25 8 BIT OTP EPROM MCUs WITH A D CONVERTER 3 0 to 6 0V Supply Operating Range 8 MHz Maximum Clock Frequency 40 to 85 C Operating Temperature Range Run Wait and Stop Modes 5 Interrupt Vectors Look up Table capability in OTP EPROM Data OTP EPROM User selectable size in program EPROM Data RAM 64 bytes 12 20 I O pins fully programmable as Input with pull up resistor Input without pull up resistor Input with interrupt generation Open drain or push pull output Analog Input a 41 0 lines can sink up to 20mA to drive LEDs or TRIACs directly a 8 bit Timer with 7 bit programmable prescaler and external input m Digital Watchdog 8 bit A D Converter with 8 ST62T10 T20 E20 or 16 ST62T15 T25 E25 analog inputs On chip Clock oscillator can be driven by Quartz crystal or Ceramic resonator Power on Reset m One external Non Maskable Interrupt m ST626x EMU2 Emulation and Development System connects to an MS DOS PC via a parallel port DEVICE SUMMARY De Emme Bytes Bytes 8 Cm DR smms m E 1996 PACKAGES me PDIP20 PDIP28 PSO20 PSO28 EPROM PACKAGES CDIP20W CDIP28W See end of Datasheet for Ordering Information 1 68 745234237 00850153 Table of Contents ST62T10
37. OS PC via a parallel port See end of Datasheet for Ordering Information October 1996 17 68 7121237 0080159 345 ST6210B 15 20 25 1 GENERAL DESCRIPTION 1 1 INTRODUCTION The ST6210B ST6215B ST6220B and ST6225B microcontrollers are members of the 8 bit HCMOS ST62xx family of devices which is targeted at low to medium complexity applications All ST62xx de vices are based on a building block approach a common core is surrounded by a number of on chip peripherals The ST6210B ST6215B ST6220B and ST6225B devices feature the following peripherals a Timer comprising an 8 bit counter equipped with a 7 bit software programmable prescaler an 8 bit A D Converter with up to 16 analog inputs as I O pin alternate functions and a Digital Watchdog timer Figure 2 Block Diagram 8 BIT A D CONVERTER TEST INTERRUPT ROM Memory Size 1836 Bytes 5762108 158 3884 Bytes ST6220B 25B DATA ROM USER SELECTABLE DATA RAM 64 Bytes STACK LEVEL 1 STACKLEVEL 2 STACKLEVEL 3 STACK LEVEL 4 STACKLEVEL 5 STACKLEVEL 6 POWER EULER OSCILLATOR RESET 4 RESET 8 BIT CORE Vpp Vss OSCin OSCout 18 68 7125237 0080 70 Mi ST6210B ST6215B ST6220B and 5 6225 devices feature various options such as a choice of Quartz Ceramic or RC oscillators an Oscillator Safe Guard circuit Read out Protection against unauthorised copying of program code and an Extern
38. The processor core generates a delay af ter occurrence of the interrupt request in order to wait for complete stabilisation of the oscillator be fore executing the first instruction 41 68 7525237 0080133 Mi ST6210B 15 20 25 POWER SAVING MODE Cont d 3 5 3 Exit from WAIT and STOP Modes The following paragraphs describe how the MCU exits from WAIT and STOP modes when an inter rupt occurs not a Reset It should be noted that the restart sequence depends on the original state of the MCU normal interrupt or non maskable in terrupt mode prior to entering WAIT or STOP mode as well as on the interrupt type Interrupts do not affect the oscillator selection consequently when the LFAO is used the user program must manage oscillator selection as soon as normal RUN mode is resumed 3 5 3 1 Normal Mode If the MCU was in the main routine when the WAIT or STOP instruction was executed exit from Stop or Wait mode will occur as soon as an interrupt oc curs the related interrupt routine is executed and on completion the instruction which follows the STOP or WAIT instruction is then executed pro viding no other interrupts are pending 3 5 3 2 Non Maskable Interrupt Mode If the STOP or WAIT instruction has been execut ed during execution of the non maskable interrupt routine the MCU exits from the Stop or Wait mode as soon as an interrupt occurs the instruction which follows the STOP or WAIT ins
39. The stack consists of six separate 12 bit RAM locations that do not belong to the data space RAM area When a subroutine call or inter rupt request occurs the contents of each level are shifted into the next higher level while the content of the PC is shifted into the first level the original contents of the sixth stack level are lost When a subroutine or interrupt return occurs RET or RETI instructions the first level register is shift ed back into the PC and the value of each level is popped back into the previous level Since the ac cumulator in common with all other data space registers is not stored in this stack management of these registers should be performed within the subroutine The stack will remain in its deepest position if more than 6 nested calls or interrupts are executed and consequently the last return ad dress will be lost It will also remain in its highest position if the stack is empty and a RET or RETI is executed In this case the next instruction will be executed Figure 10 ST6 CPU Programming Mode 07 XREG POINTER b INDEX SHORT b7 YREG POINTER 50 DIRECT ADDRESSING bo MODE 0 57 ACCUMULATOR b0 REGISTER V REGISTER W REGISTER b11 PROGRAM COUNTER b SIX LEVELS STACK REGISTER NORMAL FLAGS INTERRUPT FLAGS FLAGS VA000423 25 68 5 6210 15 20 25 3 CLOCKS RESET INTERRUPTS AND POWER SAVING MODES 3 1 CLOCK SYSTEM The MCU featur
40. al STOP Mode Control to offer optimum tradeoff between power consumption and noise immunity depending on the application These devices are well suited for automotive ap pliance and industrial applications The user pro grammable parts for program development are the ST62E20 and E25 which are pin compatible devices with 4Kbytes of EPROM PAO PA3 20mA Sink PORTA pas Paz Ain ai PORT lt Lo PBO PB7 Ain PORT C Kl PC4 PC7 Ain NOT AVAILABLE ON 5762108 208 TIMER DIGITAL WATCHDOG o gt 1 2 PIN DESCRIPTION Vpp and Vss Power is supplied to the MCU via these two pins Vpp is the power connection and Vgg is the ground connection OSCin and OSCout These pins are internally connected to the on chip oscillator circuit When the QUARTZ CERAMIC RESONATOR Mask Op tion is selected a quartz crystal a ceramic reso nator or an external clock signal can be connected between these two pins When the RC OSCILLA TOR Mask Option is selected a resistor must be connected between the OSCout pin and ground The OSCin pin is the input pin the OSCout pin is the output pin RESET The active low RESET pin is used to re start the microcontroller TEST The TEST pin must be held at Veg for nor mal operation an internal 100 pull down resis tor selects normal operating mode if the TEST pin is not connected externally NMI The NMI pin provides the capability for asyn chronous interrup
41. are described in the following paragraphs Accumulator A The accumulator is an 8 bit general purpose register used in all arithmetic cal culations logical operations and data manipula tions The accumulator can be addressed in Data space as a RAM location at address FFh Thus the ST6 can manipulate the accumulator just like any other register in Data space Figure 9 ST6 Core Block Diagram Indirect Registers X Y These two indirect reg isters are used as pointers to memory locations in Data space They are used in the register indirect addressing mode These ede can be ad dressed in the data space as RAM locations at ad dresses 80h X and 81h Y They can also be ac cessed with the direct short direct or bit direct ad dressing modes Accordingly the ST6 instruction set can use the indirect registers as any other reg ister of the data space Short Direct Registers V W These two regis ters are used to save a byte in short direct ad dressing mode They can be addressed in Data space as RAM locations at addresses 82h V and 83h W They can also be accessed using the di rect and bit direct addressing modes Thus the ST6 instruction set can use the short direct regis ters as any other register of the data space Program Counter PC The program counter is a 12 bit register which contains the address of the next ROM location to be processed by the core This ROM location may be an opcode an oper and or
42. atus Control OD4h X Y V W Register 080h Accumulator OFFh Data RAM 0840 to OBFh Data ROM Window Register oc9h A D Result Register ODOh Timer Counter Register Timer Prescaler Register Watchdog Counter Register A D Control Register 001 A D in Stand by main oscillator on are Inputs with pull up I Os are Inputs with pull up Interrupts disabled Timer disabled to 083 Undefined Maximum count loaded 32 68 a 7929237 0080164 551 EM 3 3 DIGITAL WATCHDOG The digital Watchdog consists of a reloadable downcounter timer which can be used to provide controlled recovery from software upsets The Watchdog circuit generates a Reset when the downcounter reaches zero User software can prevent this reset by reloading the counter and should therefore be written so that the counter is regularly reloaded while the user program runs correctly In the event of a software mishap usu ally caused by externally generated interference the user program will no longer behave in its usual fashion and the timer register will thus not be re loaded periodically Consequently the timer will decrement down to 00h and reset the MCU In or der to maximise the effectiveness of the Watch dog function user software must be written with this concept in mind Watchdog behaviour is governed by two mask op tions known as WATCHDOG ACTIVATION i e HARDWARE or SO
43. byte read only data window from address 40h to address 7Fh of the Data space up and down the ROM memory of the MCU in steps of 64 bytes The effective address of the byte to be read as data in ROM memory is ob tained by concatenating the 6 least significant bits of the register address given in the instruction as least significant bits and the content of the DWR register as most significant bits seeFigure 8 So when addressing location 0040h of the Data Space with 0 loaded in the DWR register the physical location addressed ROM is 00h The DWR register is not cleared on reset therefore it must be written to prior to the first access to the Data ROM window area Figure 8 Data ROM Window Memory Addressing DATA ROM WINDOW REGISTER 7 6 CONTENTS DWR 5 4 3 2 1 13 12 11 10 9 8 7 615 4 3 2 1 ST6210B 15B 20 25 Data Window Register DWR Address 0C9h Write Only 7 0 DWR5 DWR4 DWR3 DWR2 DWRO Bit 7 This bit is not used Bit 6 0 DWR6 DWRO Data ROM Window Reg ister Bits These are the Data ROM Window bits that correspond to the upper bits of the data ROM space Caution This register is undefined on reset Nei ther read nor single bit instructions may be used to address this register Note Care is required when handling the DWR register as it is write only For this reason it is not allowed to change the DWR contents while exe cuting interrupt service routine as the service rou
44. con stants Stack space contains six 12 bit RAM cells used to stack the return addresses for subroutines and interrupts Immediate In the immediate addressing mode the operand of the instruction follows the opcode location As the operand is a ROM byte the imme diate addressing mode is used to access con stants which do not change during program exe cution e g a constant used to initialize a loop counter Direct In the direct addressing mode the address of the byte which is processed by the instruction is stored in the location which follows the opcode Direct addressing allows the user to directly ad dress the 256 bytes in Data Space memory with a single two byte instruction Short Direct The core can address the four RAM registers X Y V W locations 80h 81h 82h 83h in the short direct addressing mode In this case the instruction is only one byte and the selection of the location to be processed is contained in the opcode Short direct addressing is a subset of the direct addressing mode Note that 80h and 81h are also indirect registers Extended the extended addressing mode the 12 bit address needed to define the instruction is obtained by concatenating the four less significant 52 68 7929237 0080204 277 bits of the opcode with the byte following the op code The instructions JP CALL which use the extended addressing mode are able to branch to any address of the 4K bytes Program spac
45. d in WAIT mode During Reset any conversion in progress is stopped the control register is reset to 40h and the ADC interrupt is masked EAI 0 Figure 28 ADC Block Diagram INTERRUPT CLOCK RESET AVss CONVERTER CONTROL REGISTER RESULT REGISTER CORE CONTROL SIGNALS 4 3 1 Application Notes The A D converter does not feature a sample and hold circuit The analog voltage to be measured should therefore be stable during the entire con version cycle Voltage variation should not exceed 1 2 LSB for the optimum conversion accuracy A low pass filter may be used at the analog input pins to reduce input voltage variation during con version When selected as an analog channel the input pin is internally connected to a capacitor of typi cally 12pF For maximum accuracy this capacitor must be fully charged at the beginning of conver sion In the worst case conversion starts one in struction 6 5 us after the channel has been se lected In worst case conditions the impedance ASI of the analog voltage source is calculated us ing the following formula 6 5us 9 x C4 x ASI capacitor charged to over 99 9 i e 30 in cluding a 5096 guardband ASI can be higher if has been charged for a longer period by add ing instructions before the start of conversion adding more than 26 CPU cycles is pointless 7424237 0050200 AID CONVERTER Cont d Since the ADC is on the same
46. e An extended addressing mode instruction is two byte long Program Counter Relative The relative ad dressing mode is only used in conditional branch instructions The instruction is used to perform a test and if the condition is true a branch with a span of 15 to 16 locations around the address of the relative instruction If the condition is not true the instruction which follows the relative instruc tion is executed The relative addressing mode in struction is one byte long The opcode is obtained in adding the three most significant bits which characterize the kind of the test one bit which de termines whether the branch is a forward when it is 0 or backward when it is 1 branch and the four less significant bits which give the span of the branch to Fh which must be added or sub tracted to the address of the relative instruction to obtain the address of the branch Bit Direct In the bit direct addressing mode the bit to be set or cleared is part of the opcode and the byte following the opcode points to the ad dress of the byte in which the specified bit must be set or cleared Thus any bit in the 256 locations of Data space memory can be set or cleared Bit Test amp Branch The bit test and branch ad dressing mode is a combination of direct address ing and relative addressing The bit test and branch instruction is three byte long The bit iden tification and the tested condition are included in the opc
47. e instructions use one two or three bytes in relation with the addressing mode One operand is the Accumulator for LOAD and the other operand is obtained from data memory us ing one of the addressing modes For Load Immediate one operand can be any ot the 256 data space bytes while the other is always immediate data FI epe pen A A n A A HA HP A HPA HL A LOT N Immediate LDI rr N Immediate Notes XY Indirect Register Pointers V amp W Short Direct Registers Immediate data stored in ROM memory rr Data space register A Affected Not Affected 7424237 0080205 10b EM 53 68 ST6210B 15 20B 25B INSTRUCTION SET Cont d Arithmetic and Logic These instructions are tent or an immediate value in relation with the ad used to perform the arithmetic calculations and dressing mode In DEC INC instructions the logic operations In AND ADD CP SUB instruc operand can be any of the 256 data space ad tions one operand is always the accumulator while dresses In COM RLC SLA the operand is al the other can be either a data space memory con ways the accumulator Table 12 Arithmetic amp Logic Instructions ADD A X Indirect Bytes ADD A Y Indirect ADD A rr Direct ADDI A AND A X Indirect AND A Y Indirect AND A rr Direct ANDI A N Immediate EZ CLR A Short Direct CLRr Direct COMA Inherent 1
48. e rou tine A Schmitt trigger is present on the NMI pin The user can choose to have an on chip pull up on the NMI pin by specifying the appropriate ROM mask option see Option List at the end of the Da tasheet The two interrupt sources associated with the fall ing rising edge mode of the external interrupt pins Port A vector 1 Port B amp C vector 2 are con nected to two internal latches Each latch is set when a falling rising edge occurs during the processing of the previous one will be processed as soon as the first one has been serviced unless a higher priority interrupt request is present If more than one interrupt occurs while processing the first one the subsequent ones will be lost Storage of interrupt requests is not available in level sensitive detection mode To be taken into account the low level must be present on the in terrupt pin when the MCU samples the line after instruction execution At the end of every instruction the MCU tests the interrupt lines if there is an interrupt request the next instruction is not executed and the appropri ate interrupt service routine is executed instead When the GEN bit is low the NMI interrupt is ac tive but cannot cause a wake up from STOP WAIT modes 4 3 4 5 Interrupt Procedure The interrupt procedure is very similar to a call procedure indeed the user can consider the inter rupt as an asynchronous call procedure As this is
49. e that the reset signal is not released before the Vpp level is sufficient to allow MCU operation at the chosen frequency see Recommended Op erating Conditions A proper reset signal for a slow rising supply can generally be provided by an external RC net work connected to the pin Figure 16 Reset and Interrupt Processing NMI MASK SET INT LATCH CLEARED IF PRESENT SELECT NMI MODE FLAGS PUT FFEH ON ADDRESS BUS IS RESET STILL PRESENT NO LOAD PC FROM RESET LOCATIONS FFE FFF FETCH INSTRUCTION RESETS Cont d 3 2 3 Watchdog Reset The MCU provides a Watchdog timer function in order to ensure graceful recovery from software upsets If the Watchdog register is not refreshed before an end of count condition is reached the internal reset will be activated This amongst oth er things resets the watchdog counter The MCU restarts just as though the Reset had been generated by the RESET pin including the built in stabilisation delay period 3 2 4 Application Notes No external resistor is required between the Reset pin thanks to the built in pull up device The POR circuit operates dynamically in that it triggers MCU initialization on detecting the rising edge of Vpp The typical threshold is in the region of 2 volts but the actual value of the detected threshold depends on the way in which V5p rises The POR circuit is NOT designed to supervise static or slowly rising or falli
50. e to a Reset either by activating the external pin or generated by the Watchdog the MCU enters a normal reset proce dure If an interrupt is generated during WAIT mode the MCU s behaviour depends on the state of the processor core prior to the WAIT instruction but also on the kind of interrupt request which is generated This is described in the following para graphs The processor core does not generate a delay following the occurrence of the interrupt be cause the oscillator clock is still available and no stabilisation period is necessary 3 5 2 STOP Mode If the Watchdog is disabled STOP mode is avail able When in STOP mode the MCU is placed in the lowest power consumption mode In this oper ating mode the microcontroller can be considered as being frozen no instruction is executed the oscillator is stopped the RAM contents and pe ripheral registers are preserved as long as the power supply voltage is higher than the RAM re tention voltage and the ST62xx core waits for the occurrence of an external interrupt request or a Reset to exit the STOP state If the STOP state is exited due to a Reset by ac tivating the external pin the MCU will enter a nor mal reset procedure Behaviour in response to in terrupts depends on the state of the processor core prior to issuing the STOP instruction and also on the kind of interrupt request that is gener ated This case will be described in the following para graphs
51. ence which ensures that no unwanted side effects can occur The recom mended safe transitions are illustrated in Figure 25 All other transitions are potentially risky and should be avoided when changing the operat ing mode as it is most likely that undesirable side effects will be experienced such as spurious inter rupt generation or two pins shorted together by the analog multiplexer Single bit instructions SET RES INC and DEC should be used with great caution on Ports A and B Data registers since these instructions make an implicit read and write back of the entire register In port input mode however the data register reads from the input pins directly and not from the data register latches Since data register informa tion in input mode is used to set the characteristics of the input pin interrupt pull up analog input these may be unintentionally reprogrammed de pending on the state of the input pins As a gener al rule it is better to limit the use of single bit in structions on data registers to when the whole port ST6210B 15B 20B 25B is in output mode In the case of inputs or of mixed inputs and outputs it is advisable to keep a of the data register RAM Single bit instructions may then be used on the RAM copy after which the whole copy register can be written to the port data register SET bit LD a datacopy LD DRA a datacopy Care must also be taken to not use INC or DEC
52. es a Main Oscillator which can be Figure 11 Oscillator Configurations driven by an extemal clock or used in conjunction with an AT cut parallel resonant crystal or suita ble ceramic resonator or with an external resistor MATO SAL A 46 agi ption In addition a Low Frequency Auxiliary Os cillator LFAO can be switched in for security rea sons to reduce power consumption or to offer the benefits of a back up clock system The Oscillator Safeguard OSG option filters spikes from the oscillator lines provides access to the LFAO to provide a backup oscillator in the event of main oscillator failure and also automati cally limits the internal clock frequency fnr as a function of Vpp in order to guarantee correct op eration These functions are illustrated in Figure Chin 12 Figure 13 Figure 14 and Figure 15 E T Figure 11 illustrates various possible oscillator con figurations using an external crystal or ceramic res EXTERNAL CLOCK onator an external clock input an external resistor CRYSTAL RES ONATOR mask option or the lowest cost solution using only the L Can 2 should have a capacitance in the range 12 to 22 4 8 MHz range The internal MCU clock frequency is divided by 12 to drive the Timer the A D converter and the Watchdog timer and by 13 to drive the CPU core as may be seen in Figure 14 With an 8MHz oscillator frequency the fastest machine cycle is the
53. escribed in the following paragraphs routine and interrupt service routine nesting Figure 5 Memory Addressing Diagram PROGRAM SPACE DATA SPACE RAM EEPROM BANKING AREA DATA ROM WINDOW DATA ROM WINDOW SELECT INTERRUPT amp BANK SELECT RESET VECTORS io ACCUMULATOR 20 68 477 z EE 7929237 0080172 937 MM MEMORY 1 3 2 Program Space Program Space is physically implemented in ROM It comprises the instructions to be execut ed the data required for immediate addressing mode instructions the reserved factory test area and the user vectors Program Space is addressed via the 12 bit Program Counter register PC register 1 3 2 1 ROM Protection The ST6210B ST6215B ST6220B and ST6225B Program Space can be protected against external read out of ROM contents when the READOUT PROTECTION mask option is chosen This option allows the user to blow a dedicated fuse on the sil icon by applying a high voltage at see de tailed information in the Electrical Specification Figure 6 ST6210B 15B Program Memory Map NOT IMPLEMENTED RESERVED USER PROGRAM MEMORY ROM 1824 BYTES 71424237 0080173 ST6210B 15 20 25B Note Once the Read out Protection fuse is blown it is no longer possible even for SGS THOMSON to gain access to the ROM contents Returned parts with a blown fuse can therefore not
54. frequency than the main oscillator When the hardware activated Watchdog is select ed or when the software Watchdog is enabled the STOP instruction is disabled and a WAIT in struction will be executed in its place If all interrupt sources are disabled GEN low the MCU can only be restarted by a Reset Although setting GEN low does not mask the NMI as an in terrupt it will stop it generating a wake up signal The WAIT and STOP instructions are not execut ed if an enabled interrupt request is pending 4 PERIPHERALS 4 1 VO PORTS The 20 pin devices feature 12 Input Output lines and the 28 pin devices feature 20 Input Output lines refer to the Block Diagram in Figure 2 which may be individually programmed as any of the following input or output configurations Input without pull up or interrupt Input with pull up and interrupt Input with pull up but without interrupt Analog input only on certain pins seeFigure 2 Push pull output Standard Open drain output 20mA Open drain output PAO PA3 only e lines are organized as three Ports A B and Each port is associated with 3 registers in Data space Each bit of these registers is associated with a particular line for instance bits O of Port A Data Direction and Option registers are associat ed with the PAO line of Port A The three DATA registers DRA DRB and DRC are used to read the voltage level values of the l
55. g channel or if the total current flowing into all analog inputs is 5 all the resulting conversions are shifted by 2 LSB Figure 29 Maximum Operating FREQUENCY Fmax Versus SUPPLY VOLTAGE V Maximum FREQUENCY MHz 3 5 4 4 5 SUPPLY VOLTAGE V VR01807C Note The shaded area is outside the ST6210B ST6215B ST6220B and ST6225B recommended operating range functionality is not guaranteed under these conditions 4 7125237 0080211 4OT ST6210B 15B 20B 25 6 3 DC TELECTRICAL CHARACTERISTICS Ta 40 to 85 C unless otherwise specified Test Conditions Input Low Level Voltage TIMER NMI RE SET pins Input High Level Voltage TIMER NMI RE SET pins Hysteresis Volt All Inputs Low Level Output Voltage TIMER pin lol 5 0mA High Level Output Voltage TIMER pin Input Leakage Current TIMER NMI pins Input Leakage Current RESET Vin Vpp Watchdog Res Vin Vpp No Watch Res VIN Vss External Res Supply Current in VRESET Vss 35 mA RESET Mode fosc 8MHz Vpp 5 0V finr 8MHz 5 0V Iint fiFao Vpp 3 0V fint 2MHz Supply Current in RUN Mode 2 Vop 5 0V fint 8MHz Vpp 5 0Vfint fLFao Vpp 3 0V finr 2MHz Supply Current in 1 OMA STOP Mode 9 Vpp 5 0V 10 Notes 1 No watchdog reset activated 2 All peripherals running 3 A D Co
56. he address of the inter rupt vector i e of the Jump instruction which then causes a Jump to the relevant interrupt serv ice routine thus servicing the interrupt Table 4 Interrupt Vector Map Interrupt Source Associated Vector Vector Address Interrupt vector 0 a NMI FFCh FFDh FORA Port B amp Cpins FF4h FFSh TIMER peripheral Interrupt vector 3 ADC peripheral Interrupt vector 4 3 4 1 Interrupt Vectors Interrupt vectors are Jump addresses to the asso ciated service routine which reside in specific ar eas of Program space The following vectors are present The interrupt vector associated with the non maskable interrupt source is referred to as Inter rupt Vector 0 It is located at addresses OFFCh and OFFDh in Program space This vector is as sociated with the falling edge sensitive Non Maskable Interrupt pin NMI EN 7424237 0080189 133 ST6210B 15B 20B 25B The interrupt vector associated with Port A pins is referred to as interrupt vector 1 It is located at addresses OFF6h OFF7h is named It can be programmed either as falling edge sensitive or as low level sensitive by setting the Interrupt Op tion Register IOR accordingly The interrupt vector associated with Port B and C pins is referred to as interrupt vector 2 It is lo cated at addresses OFF4h OFF5h is named It can be programmed either as falling edge sensi tive or as rising edge sensi
57. hin the interrupt routine ina software stack After the RETI instruction is exe cuted the MCU returns to the main routine Figure 22 Interrupt Processing Flow Chart INSTRUCTION FETCH INSTRUCTION EXECUTE INSTRUCTION WAS N THE INSTRUCTIO A RETI YES IS THE CORE SET 2 INTERRUPT MASK LOAD PC FROM INTERRUPT VECTOR FFC FFD PUSH THE PC INTO THE STACK NO CLEAR INTERRUPT MASK SELECT SELECT PROGRAM FLAGS INTERNAL MODE FLAG POP THE STACKED PC CHECK IF THERE IS AN INTERRUPT REQUEST AND INTERRUPT MASK VAQ0001 4 EN 732323 0060191 89 NH 95 6 ST6210B 15 20 25 INTERRUPTS Cont d Table 6 interrupt Requests and Mask Bits EZITE Mantecintrnntsource Neco on cm excluaing NM 23 Interrupt Block Diagram FF ME LM INT 0 NMI FFC D NEL D l Start FF 0 CLR FROM REGISTER PORT A B C INT 1 FF6 7 SINGLE BIT ENABLE MUX ons bo 1 RESTART FR IOR REG bit 6 22 STOP WAIT i PORTAL FF D D INT 2 FF4 5 Tt CLR bit 5 la Start E INT 3 FF2 3 INT 4 FFO 1 El VAOH426 40 68 EE 7929237 0080192 728 ag AWA 3 5 POWER SAVING MODES The WAIT and STOP modes have been imple mented in the ST62xx family of MCUs in order to reduce the product s electrical consumption dur ing idle periods These two power saving mode
58. ht Both OTP and EPROM parts may be programmed using programming equipment approved by SGS THOMSON 1 4 1 OTP EPROM Programming Programming mode is selected by applying a 12 5V voltage to the Vpp TEST pin during reset Programming of OTP and EPROM parts is fully described in the EPROM Programming Board User Manual 1 4 2 Eprom Erasure Thanks to the transparent window present in the EPROM package its memory contents may be erased by exposure to UV light 8 68 7429237 0080150 110 AM Erasure begins when the device is exposed to light with wavelength shorter than 4000 It should be noted that sunlight as well as some types of artificial light includes wavelengths in the 3000 4000 range which on prolonged exposure can cause erasure of memory contents It is thus recommended that EPROM devices be fitted with an opaque label over the window area in order to prevent unintentional erasure The recommended erasure procedure for EPROM devices consists of exposure to short wave UV light having a wavelength of 2537 The minimum recommended integrated dose intensity x expo sure time for complete erasure is 15Wsec cnf This is equivalent to an erasure time of 15 20 min utes using a UV source having an intensity of 12mW cm at a distance of 25mm 1 inch from the device window 2 CENTRAL PROCESSING UNIT 2 1 INTRODUCTION The CPU Core may be thought of as an independ ent central processor communicating with on
59. ig nificant bits are determined The best configuration from an accuracy stand point is WAIT mode with the Timer stopped In deed only the ADC peripheral and the oscillator are then still working The MCU must be woken up from WAIT mode by the ADC interrupt at the end of the conversion It should be noted that waking ST6210B 15B 20B 25 up the microcontroller could also be done using the Timer interrupt but in this case the Timer will be working and the resulting noise could affect conversion accuracy A D Converter Control Register ADCR Address ODih Read Write 7 0 Bit 7 EAI Enable A D Interrupt If this bitis set to 1 the A D interrupt vector 4 is enabled when EAI 0 the interrupt is disabled Bit 6 EOC End of conversion Read Only This read only bit indicates when a conversion has been completed This bit is automatically reset to 0 when the STA bit is written If the user is using the interrupt option then this bit can be used as an interrupt pending bit Data in the data conversion register are valid only when this bit is set to 1 Bit 5 STA Start of Conversion Write Only Writ ing a 1 to this bit will start conversion on the se lected channel and automatically reset to 0 the EOC bit If the bit is set again when a conversion is in progress the present conversion is stopped and new will take place This bit is write on ly any attempt to read it will
60. in structions on a port register when the 8 bits are not available on the devices The WAIT and STOP instructions allow the ST62xx to be used in situations where low power consumption is needed The lowest power con sumption is achieved a configuring 1 in input mode with well defined logic levels The user must take care not to switch outputs with heavy loads during the conversion of one of the analog inputs in order to avoid any disturbance to the conversion Figure 25 Diagram showing Safe I O State Transitions Interrupt pull up Reset state Output Open Drain Output Push pull Note DDR OR DR Bits respectively 752523 0080197 Output Push pull 45 68 ST6210B 15B 20B 25B PORTS Cont d Table 8 Port Option Selections AVAILABLE Device Dependent SCHEMATIC PAO PA7 PBO PB7 PC4 PC7 Data in 0 Input PBO PB7 with pull up PC4 PC7 Data in Input PAO PA7 with pull up PBO PB7 Data in with interrupt PC4 PC7 Interrupt PA4 PA7 PBO PB7 PC4 PC7 Analog Input Device Dependent Open drain output PA4 PA7 SmA PBO PB7 PC4 PC7 H Data out Open drain output 20 Push pull output PA4 PA7 5mA PBO PB7 PC4 PC7 Data out Push pull output 20 Note 1 Provided the correct configuration has been selected 46 68
61. ines which have been configured as inputs or to write the logic value of the signal to be output on Figure 24 Port Block Diagram 5 7124237 0020195 437 Mi ST6210B 15 20B 25B the lines configured as outputs The port data reg isters can be read to get the effective logic levels of the pins but they can be also written by user software in conjunction with the related option registers to select the different input mode op tions Single bit operations on registers are possible but care is necessary because reading in input mode is done from pins while writing will direct ly affect the Port data register causing an unde sired change of the input configuration The three Data Direction registers DDRA DDRB and DDRC allow the data direction input or out put ofeach pin to be set The three Option registers ORA ORB and ORC are used to select the different port options availa ble both in input and in output mode All registers can be read or written to just as any other RAM location in Data space so no extra RAM celis are needed for port data storage and manipulation During MCU initialization all registers are cleared and the input mode with pull ups and no interrupt generation is selected for all the pins thus avoiding pin conflicts 000413 43 68 ST6210B 15B 20 25B PORTS Cont d 4 1 1 Operating Modes Each pin may be individually programmed as i
62. ing of the user program is stopped RUN mode only the Inputs and Outputs are con figured as inputs with pull up resistors and the main Oscillator is restarted When the level on the RESET pin then goes high the initialization se quence is executed following expiry of the internal delay period IF RESET pin activation occurs in the STOP mode the oscillator starts up and all Inputs and Outputs are configured as inputs with pull up resistors When the level of the pin then goes high the initialization sequence is executed following expiry of the internal delay period 3 2 2 Power on Reset The function of the POR circuit consists in waking up the MCU at an appropriate stage during the power on sequence At the beginning of this se quence the MCU is configured in the Reset state all I O ports are configured as inputs with pull up resistors and no instruction is executed When the power supply voltage rises to a sufficient level the oscillator starts to operate whereupon an internal delay is initiated in order to allow the oscillator to fully stabilize before executing the first instruction The initialization sequence is executed immedi ately following the internal delay 30 68 7424237 00501828 889 EN internal delay is generated on chip coun ter The internal reset line is released 2048 internal clock cycles after release of the external reset Notes To ensure correct D the user should take car
63. ion VDD Vss TIMER PAO OSCin OSCout PA2 NMI PA3 Ain PC7 PA4 Ain Ain PC6 PAS Ain PA7 Ain PBO Ain PB1 Ain PB2 Ain PB3 Ain PB4 Ain Ain PC5 Ain PC4 Vpp TEST RESET Ain PB7 Ain PB6 Ain PB5 1 3 5 1 3 1 Program Figure 4 65762710 T15 Program Memory IMPLEMENTED RESERVED USER PROGRAM MEMORY OTP 1824 BYTES RESERVED INTERRUPT VECTORS RESERVED NMI VECTOR USER RESET VECTOR Reserved areas should be filled with OFFh 1 3 2 Data Space Data Space accommodates all the data necessary for processing the user program This space com prises the RAM resource the processor core and peripheral registers as well as read only data such as constants and look up tables in OTP EPROM The Data Space is fully described and illustrated on page 21 r ST62T10 T15 T20 T25 ST62E20 E25 Figure 5 ST62T20 T25 E20 E25 Program Memory Map RESERVED USER PROGRAM MEMORY OTP EPROM 3872 BYTES RESERVED INTERRUPT VECTORS RESERVED NM VECTOR USER RESET VECTOR 9 Reserved areas should be filled witn OFFh 7 68 7929237 0080159 5762710 T15 T20 T25 ST62E20 E25 1 4 PARTICULARITIES OTP AND EPROM DEVICES OTP and EPROM devices are identical save for the package which in the EPROM device is fitted with a transparent window to allow erasure of memory contents by exposure to UV lig
64. ng 3 2 5 MCU Initialization Sequence When a reset occurs the stack is reset the PC is loaded with the address of the Reset Vector lo cated in program ROM starting at address OFFEh A jump to the beginning of the user pro gram must be coded at this address Following a Reset the Interrupt flag is automatically set so Figure 18 Reset Block Diagram 2 8kQ POWER ON RESET WATCHDOG RESET 7323237 0050183 715 NE ST6210B 15B 20B 25B that the CPU is in Non Maskable Interrupt mode this prevents the initialisation routine from being interrupted The initialisation routine should there fore be terminated by a RETI instruction in order to revert to normal mode and enable interrupts If no pending interrupt is present atthe end of the in itialisation routine the MCU will continue by processing the instruction immediately following the RETI instruction If however a pending inter rupt is present it will be serviced Figure 17 Reset and Interrupt Processing RESET JP 2 BYTES 4 CYCLES RESET VECTOR INITIALIZATION ROUTINE RETI 1 BYTE 2 CYCLES VA00181 ST6 INTERNAL RESET COUNTER 31 68 ST6210B 15 20 25B RESETS Cont d Table 2 Register Reset Status Suus Port Data Registers PA PB PC OCOh to 0C2h Port Direction Register PA PB PC OC4h to OC6h Port Option Register PA PB PC OCCh to OCEh Interrupt Option Register 9 8 Timer St
65. nput or output with various configurations except for PBO and PC7 on devices with the EXTERNAL STOP MODE CONTROL option This is achieved by writing the relevant bit in the Data DR Data Direction DDR and Option reg isters OR Table 7 illustrates the various port configurations which can be selected by user soft ware 4 1 1 1 Input Options Pull up High Impedance Option All input lines can be individually programmed with or without an internal pull up by programming the OR and DR registers accordingly If the pull up option is not selected the input pin will be in the high imped ance state 4 1 1 2 Interrupt Options All input lines can be individually connected by software to the interrupt system by programming the OR and DR registers accordingly The pins of Port A are AND connected to the interrupt associ ated with Vector 1 The pins of Port B and C are AND connected to the interrupt associated with Vector 2 The interrupt trigger modes falling edge rising edge and low level can be selected by software for each port by programming the IOR register accordingly 4 1 1 3 Analog Input Options Some pins refer to the Block Diagram Figure 2 can be configured as analog inputs by program ming the OR and DR registers accordingly These analog inputs are connected to the on chip 8 bit Analog to Digital Converter ONLY ONE pin Table 7 I O Port Option Selection Note X Don t care Device dependert
66. nverter in Stand by 4 Hysteresis voltage between switching levels Supply Current in WAIT Mode sues 2429237 0080212 We A ST6210B 15B 20 25 6 4 TELECTRICAL CHARACTERISTICS 40 85 unless otherwise specified Value Symbol Parameter Test Conditions ENGL NAE Min V pp 3 0V OSG disabled i Maximum internal frequency VDD 3 0V 2 MHz OSG with OSG enabled Vpp 4 5V 4 t Low Frequency Auxiliary Oscillator t Oscillator Start up Time Ceramic Resonator 5 100 M SU at Power 2 22pF 8MHz Ceramic Resonator i Oscillator STOP mode CL1 C 2 22pF SUS Recovery Time 2 8MHz Quartz CL1 C 2 22pF Supply Recovery Time Minimum Pulse Width Vpp 5V Twa RESET pin Notes NMI pin 1 Period for which Vpp has to be connected at to allow internal Reset function at next power up 2 This value is highly dependent on the Ceramic Resonator or Quartz Crystal used in the application Figure 30 Power on Reset ket os 1 2048 cycles 1 INTERNAL RESET t VAO295B 4 252523 0080213 282 M 6 8 ST6210B 15B 20B 25B M Figure 31 RC Oscillator Fy versus RNET Indicative Values The shaded area is outside the ST6210B ST6215B ST6220B and ST6225B recommended operating range device functionality i
67. ode byte The address of the byte to be tested follows immediately the opcode in the Pro gram space The third byte is the jump displace ment which is in the range of 126 to 129 This displacement can be determined using a label which is converted by the assembler Indirect n the indirect addressing mode the byte processed by the register indirect instruction is at the address pointed by the content of one of the indirect registers X or Y 80h 81h The indirect register is selected by the bit 4 of the opcode A register indirect instruction is one byte long Inherent In the inherent addressing mode all the information necessary to execute the instruction is contained in the opcode These instructions are one byte long 5 3 INSTRUCTION SET The ST6 core offers a set of 40 basic instructions which when combined with nine addressing modes yield 244 usable opcodes They can be di vided into six different types load store arithme tic logic conditional branch control instructions jump call and bit manipulation The following par agraphs describe the different types All the instructions belonging to a given type are presented in individual tables Table 11 Load amp Store Instructions Addressing Mode Short Direct Short Direct Short Direct Short Direct Short Direct Short Direct Short Direct Short Direct Direct Direct Indirect Indirect Indirect Indirect ST6210B 15B 20B 25B Load 8 Store Thes
68. ons Address 0C8h Write Only Reset status 00h 7 0 Bit 7 Bits 3 0 Unused Bit 6 LES Level Edge Selection bit When this bit is set to one the interrupt 1 Port A is low level sensitive when cleared to zero the negative edge sensitive interrupt is selected Bit 5 ESB Edge Selection bit When this bit is set to one the interrupt 2 Port B and C is positive edge sensitive when cleared to zero the negative edge sensitive interrupt is se lected Bit 4 GEN Global Enable Interrupt When this bit is set to one all interrupts are enabled When this bit is cleared to zero all the interrupts exclud ing NMI are disabled When the GEN bit is low the NMI interrupt is active but cannot cause a wake up from STOP WAIT modes This register is cleared on reset 38 68 7124237 080140 955 Table 5 Interrupt Options GEN Enables all interrupts CLEARED Disables all interrupts SET Rising edge mode on Interrupt Ports B and C 5 Falli dge mod int t alling mode on Interrupi CLEARED Ports B and C Level sensitive mode on Interrupt LES Falling edge sensitive mode on In alling CLEARED terrupt mode Port A 3 4 4 External Interrupt Operating Modes The NMI interrupt is associated with the external interrupt pin This pin is falling edge sensitive and the interrupt pin signal is latched by a flip flop which is automatically reset by the core at the be ginning of the non maskable interrupt servic
69. pace see Conditional Branch performs the bit test branch operations Table 13 Conditional Branch Instructions 2 2 2 2 JRR b rr ee 5 JRS b rr ee 5 Notes b 3 bit address rr Data space register e 5 bit signed displacement in the range 15 to 16 F128M Affected The tested bit is shifted into carry ee 8 bitsigned displacement in the range 126 to 129 Not Affected Table 14 Bit Manipulation Instructions Addressing Mode Bytes Cycles SET b rr Bit Direct RES b rr Bit Direct Notes b 3 04 address Wot M Affected rm Data space register Table 15 Control Instructions EE geal libi 2 Fe Inherent 1 2 1 2 RETI Inherent 1 2 STOP 1 Inherent 1 2 WAIT Inherent 1 2 Notes 1 This instruction is deactivated lt N gt and WAIT is automatically executed instead of a STOP if the watchdog function is selected Affected Not Affected Table 16 Jump amp Call Instructions Addressing Mode Cycles BS CALL abc Extended JP abe Extended Notes 12 bit address Not Affected r EN 7525237 0050207 T69 sues ST6210B 15B 20B 25B Opcode Summary The following table contains an opcode map for the instructions used by the ST6 JRR b0 rr ee c Ao bO rr ee o A JRR b4 rr ee uc 3 b4 rr ee 75 A
70. r sion ofthe ST62T25 device which may be used to emulate the T15 and T25 devices as well as the respective ST6215B and 25B ROM devices OTP and EPROM devices are functionally identi cal The ROM based versions offer the following additional features RC Oscillator Oscillator Safe Figure 1 Block Diagram 8 BIT A A D CONVERTER OTP EPROM Memory Size 1836 Bytes ST62T10 T15 3884 Bytes ST62T20 T25 DATA ROM USER SELECTABLE DATA RAM 64 Bytes STACK LEVEL 1 STACK LEVEL 2 STACKLEVEL 3 8 BIT CORE STACKLEVEL 4 STACKLEVEL 5 STACKLEVEL 6 POWER BOWER OSCILLATOR RESET HJ 1 40 a VopVss OSCin OSCout RESET Krey ST62T10 T15 T20 25 ST62E20 E25 guard external Stop mode control program code readout protection and the possibility of having an internal pullup on the NMI and TIMER pins OTP devices offer ali the advantages of user pro grammability at low cost which make them the ideal choice in a wide range of applications where frequent code changes multiple code versions last minute programmability are required EPROM devices thanks to their ease of erasure and reprogrammability are best suited for pro gram development and evaluation These compact low cost devices feature a Timer comprising an 8 bit counter and a 7 bit program mable prescaler an 8 bit A D Converter with 8 16 analog inputs and a Digital Watchdog timer mak ing them well suited for a wide range of automo
71. refore 1 625ps RC NETWORK A machine cycle is the smallest unit of time needed RC NETWORK mask option to execute any operation forinstance to increment the Program Counter An instruction may require two four or five machine cycles for execution 3 1 1 Main Oscillator The oscillator configuration may be specified by se lecting the appropriate mask option When the CRYSTAL RESONATOR option is selected it must be used with a quartz crystal a ceramic resonator or an external signal provided on the OSCin pin WhentheRC NETWORK optionisselected thesys tem clock is generated by an external resistor The main oscillator can be turned off when the INTEGRATE D CLOCK OSG ENABLED mask option is selected by set CRYSTAURES ONATOR mask option ting the OSCOFF bit of the ADC Control Register OSG ENABLE The Low Frequency Auxiliary Oscillator is auto matically started for an oscillator frequency in the ST6xxx OSC 26 68 792923 0080178 358 F CLOCK SYSTEM Cont d Turning on the main oscillator is achieved by re setting the OSCOFF bit of the A D Converter Con trol Register or by resetting the MCU Restarting the main oscillator implies a delay comprising the oscillator start up delay period plus the duration of the software instruction at Fao clock frequency 3 1 2 Low Frequency Auxiliary Oscillator LFAO The Low Frequency Auxiliary Oscillator has three main purpose
72. registers can be read accurately at any time 4 2 7 Timer Registers Timer Status Control Register TSCR Address OD4h Read Write 7 0 Bit 7 TMZ Timer Zero bit A low to high transition indicates that the timer count register has decrement to zero This bit must be cleared by user software before starting a new count Bit 6 Enable Timer Interrupt When set enables the timer interrupt request vector 3 If ETI O the timer interrupt is disabled If ETI 1 and TMZ 1 an interrupt request is gener ated Bit 5 TOUT Timers Output Control ST6210B 15B 20B 25B When low this bit selects the input mode for the TIMER pin When high the output mode is select ed Bit 4 DOUT Data Output Data sent to the timer output when TMZ is set high output mode only Input mode selection input mode only Bit 3 PSI Prescaler Initialize Bit Used to initialize the prescaler and inhibit its counting When PSI O the prescaler is set to 7Fh and the counter is inhibited When PSI 1 the prescaler is enabled to count downwards As long as PSI O both counter and prescaler are not running Bit 2 1 0 PS2 PS1 PSO Prescaler Mux Se lect These bits select the division ratio of the pres caler register Table 10 Prescaler Division Factors 2 25 Divided by 1 m ma sa e a O70 0 Timer Counter Register TCR Address OD3h Read Write
73. rved User ROM Reserved Interrupt Vectors Reserved NMI Interrupt Vector Reset Vector OFFOh OFF7h OFF8h OFFBh OFFCh OFFDh OFFEh OFFFh Table 18 Program Memory Map for ST6220B amp ST6225B 3884 Bytes ROM Device Address 0000h 007Fh Reserved 0080h 0F9Fh User ROM OFAOh OFEFh Reserved Interrupt Vectors Reserved NMI Interrupt Vector Reset Vector OFFOh OFF7h OFF8h OFFBh OFFCh OFFDh OFFEh 0FFFh Note 1 Reserved Areas should be filled with FFh 0 to 70 40 to 85 C 0 to 70 C 40 to 85 C 0 to 70 C 40 to 85 C 0 to 70 C 40 to 85 C 0 to 70 C 40 to 85 C 0 to 70 C 40 to 85 C Oto 70 C 40 to 85 C 0 to 70 C 40 to 85 C PDIP20 PDIP28 PSO28 Note XXX is a 2 3 alphanumeric character code added to the generic sales type on receipt of a ROM code and valid options 7424237 0020219 770 67 68
74. s Firstly it can be used to reduce power consumption in non timing critical routines Secondly it offers a fully integrated system clock without any external components Lastly it acts as a safety oscillator in case of main oscillator failure This oscillator is available when the OSG ENA BLED mask option is selected In this case it au tomatically starts one of its periods after the first missing edge from the main oscillator whatever the reason main oscillator defective no clock cir cuitry provided main oscillator switched off User code normal interrupts WAIT and STOP in structions are processed as normal at the re duced f frequency A D converter accu racy is decreased since the internal frequency is below 1MHz At power on the Low Frequency Auxiliary Oscilla tor starts faster than the Main Oscillator It there fore feeds the on chip counter generating the POR delay until the Main Oscillator runs The Low Frequency Auxiliary Oscillator is auto matically switched off as soon as the main oscilla tor starts ADCR Address OD1h Read Write 7 0 ADCR ADCR ADCR ADCR ADCR OSC ADCR Bit 7 3 1 0 ADCR7 ADCR3 ADCR1 ADCRQ ADC Control Register These bits are not used Bit 2 OSCOFF When low this bit enables main oscillator to run The main oscillator is switched off when OSCOFF is high ST6210B 15B 20 25B 3 1 3 Oscillator Safe Guard The Oscillator Safe
75. s are described in the following paragraphs In addition the Low Frequency Auxiliary Oscillator LFAO be used instead of the main oscillator to reduce power consumption in RUN and WAIT modes 3 5 1 WAIT Mode The MCU goes into WAIT mode as soon as the WAIT instruction is executed The microcontroller can be considered as being in a software frozen state where the core stops processing the pro gram instructions the RAM contents and periph eral registers are preserved as long as the power supply voltage is higher than the RAM retention voltage In this mode the peripherals are still ac tive WAIT mode can be used when the user wants to reduce the MCU power consumption during idle periods while not losing track of time or the capa bility of monitoring external events The active os cillator main oscillator or LFAO is not stopped in order to provide a clock signal to the peripherals Timer counting may be enabled as well as the Timer interrupt before entering the WAIT mode this allows the WAIT mode to be exited when a Timer interrupt occurs The same applies to other peripherals which use the clock signal If the power consumption has to be further re duced the Low Frequency Auxiliary Oscillator LFAO can be used in place of the main oscillator if its operating frequency is lower If required the LFAO must be switched on before entering the WAIT mode ST6210B 15B 20B 25B If the WAIT mode is exited du
76. s not gu ar anteed under these conditions Figure 32 RC Oscillator versus RNET Indicative Values Note The shaded area is outside the ST6210B ST6215B ST6220B and ST6225B recommended operating range device functionality is not guaranteed under these conditions NH 7525237 0080210 115 137 322 6 5 READOUT PROTECTION FUSE the ROM READOUT PROTECTION option is selected the waveform illustrated below must be applied to the TEST pin in order to blow the fuse Figure 33 Programming wave form t 02001 Note ZPD15 is used for overvoltage protection 7929237 0080215 055 Mi ST6210B 15B 20B 25B The following circuit can be used for this purpose Figure 34 Programming Circuit 5V 47mF PROTECT to 14y ZPDIS 15V VRO2003 _ 63 68 ST6210B 15B 20 25 7 GENERAL INFORMATION 7 1 PACKAGE MECHANICAL DATA Figure 35 20 Pin Plastic Dual In Line Package 300 mil Width 0 1725 Number of Pins Figure 36 28 Pin Plastic Dual In Line Package 600 mil Width See Lead Detail N w VR01725F 48 242923 0080216 TA MN AWA 1571 ST6210B 15B 20 25B PACKAGE MECHANICAL DATA Cont d Figure 37 20 Pin Plastic Small Outline Package 300 mil Width mm inches Min Typ Min Typ njo All b E Figure 38 28 Pin Plastic Small Outline Package 300 mil Width 65 68 7
77. shaded area is outside the recommended operating range device functionality is not guaranteed under these conditions 11 68 7929237 0080153 927 5762710 T15 T20 T25 ST62E20 E25 7 GENERAL INFORMATION 7 1 PACKAGE MECHANICAL DATA Figure 1 20 Pin Plastic Dual In Line Package 300 mil Width Max 0 065 me 0 28 0 100 0335 IEEE PER eT VROA1725 Ey Number of Pins eee eee Figure 7 28 Pin Plastic Dual In Line Package 600 mil Width g w gt N u w o gt 5 gt EN a o i gt a See Lead Detail Q e o b o io w EX ret T ee vers 7 330 04130 a 2 54 o in N a 12 68 LIT 168 mo 2329233 b3 ST62T10 T15 T20 T25 ST62E20 E25 PACKAGE MECHANICAL DATA Cont d Figure 8 20 Pin Plastic Small Outline Package 300 mil Width Fw joo frar Figure 9 28 Plastic Small Outline Package 300 mil Width Fer 740 T e Fw foes Cc oso poss fe tel vROO1726 ia Number of Pins EN 7125257 0080 65 7TT 1398 ST62T10 T15 T20 25 ST62E
78. stal frequency When the OSG is enabled operation in this area is guaranteed at a frequency of at least fosa Min 3 When the OSG is disabled operation in this area is guaranteed at the quartz crystal frequency When the OSG is enabled access to this area is prevented The internal frequency is kept a fosg 4 When the OSG is disabled operation in this area is not guaranteed When the OSG is enabled access to this area is prevented The internal frequency is kept at fose 4 EH 7929237 0080181 quo 29 68 5 6210 15 20 25 3 2 RESETS The MCU can be reset in three ways by the external Reset input being pulled low by Power on Reset by the digital Watchdog peripheral timing out 3 2 1 RESET Input The RESET pin may be connected to a device of the application board in order to reset the MCU if required The RESET pin may be pulled low in RUN WAIT or STOP mode This input can be used to reset the MCU internal state and ensure correct start up procedure The pin is active low and features a Schmitt trigger input The internal Reset signal is generated by adding a delay to the external signal Therefore even short pulses on the RESET pin are acceptable provided has completed its rising phase and that the oscillator is running correctly normal RUN or WAIT modes The MCU is kept in the Reset state as long as the RESET pin is held low If RESET activation occurs in the RUN or WAIT modes process
79. t Ente oe e a Si Rew 20 1 3 1 Introduction sos ee Reese Oct ee RES rS Ep Ves Y 20 1 3 2 Program Space ie ww S he ra Rake ARES kek Ri 21 1 3 3 Data Space vus hoc C RU X Eu E SR E LBS RR aie 21 1 3 4 Stack Space cus cx a eve v EGIT RARUS ARA OE RUP ROS VOLU 22 1 3 5 Data Window Register 23 2 CENTRAL PROCESSING 24 24 INTRODUCTION em a ye dap Saki ek iE GAUL EUR MIR og 24 22 CPU REGISTERS cR E REESE ihe Se 24 3 CLOCKS RESET INTERRUPTS AND POWER SAVING 26 S4A GLOGK SYSTEM ord eeu aae ENS 26 3 1 1 Main Oscillator kr ER I n rt 455 ee RR a RA 26 3 1 2 Low Frequency Auxiliary Oscillator 27 3 1 3 Oscillator Safe 1 27 3 2 RESETS meae e o 30 3 2 1 RESET Inp t SMe TG 30 3 2 2 Power on 30 3 2 3 Watchdog Reset W sd odit fai elas ea a pa ar poo E 31 3 2 4 Application 3
80. t occurs A pull up device must be provided externally on OTP and EPROM devices Figure 2 ST62T10 T20 E20 Pin Configuration Vpp Vss TIMER PAO OSCin PA1 OSCout PA2 NMI PA3 Vpp TEST PBO Ain PB1 Ain PB2 Ain PB3 Ain PB4 Ain RESET Ain PB7 Ain PB6 Ain PB5 6 68 7929237 0080158 567 PAO PA3 PA4 PAT These 8 lines are organized as one I O port A Each line may be configured under software control as inputs with or without in ternal pull up resistors interrupt generating inputs with pull up resistors open drain or push pull out puts can also sink 20mA for direct LED driving while PA4 PA7 can be programmed as an alog inputs for the A D converter Note PA4 PA7 are not available on ST62T10 T20 or E20 PBO PB7 These 8 lines are organized as one I O port B Each line may be configured under soft ware control as inputs with or without internal pull up resistors interrupt generating inputs with pull up resistors open drain or push pull outputs or as analog inputs for the A D converter PC4 PC7 These 4 lines are organized as I O port C Each line may be configured under soft ware control as inputs with or without internal pull up resistors interrupt generating inputs with pull up resistors open drain or push puli outputs or as analog inputs for the A D converter Note PC4 PC7 are not available on ST62T10 T20 or E20 Figure 3 ST62T15 T25 E25 Pin Configurat
81. th the procedure for transfer of customer codes to SGS THOMSON 7 2 1 Transfer of Customer Code Customer code is made up of the ROM contents and the list of the selected mask options The ROM contents are to be sent on diskette or by electronic means with the hexadecimal file gener ated by the development tool All unused bytes must be set to FFh The selected mask options are communicated to SGS THOMSON using the correctly filled OP TION LIST appended 7 2 2 Listing Generation and Verification When SGS THOMSON receives the users ROM contents a computer listing is generated from it This listing refers exactly to the mask which will be used to produce the specified MCU The listing is then returned to the customer who must thorough ly check complete sign and return it to SGS THOMSON The signed listing forms a part of the contractual agreement for the creation of the spe cific customer mask The SGS THOMSON Sales Organization will be pleased to provide detailed information on con tractual points Table 19 Ordering Information Sales Type ST6210BB1 XXX ST6210BB6 XXX 5 6220 1 ST6220BB6 XXX ST6210BM1 XXX ST6210BM6 XXX STGZ2OBMGNOX 1836 Bytes 3884 Bytes ROM Additional Features Temperature Range A D CONVERTER ST6210B 15B 20 25B Table 17 Program Memory Map for ST6210B amp ST6215B 1836 Bytes ROM 0000h 087Fh 0880h OF9Fh OFAOh OFEFh Rese
82. tion by applying an external non maskable interrupt to the MCU The NMI is falling edge sensitive A ROM mask option makes avail able an on chip pull up on the NMI pin TIMER This is the timer I O pin In input mode it is connected to the prescaler and acts as external timer clock input or as control gate input for the in ternal timer clock In output mode the timer pin outputs the data bit when a time out occurs A ROM mask option makes available an on chip pull up on the TIMER pin Figure 3 ST6210B ST6220B Pin Configuration Vpp TIMER OSCin OSCout NMI TEST RESET Ain PB7 Ain PB6 Ain PB5 PBO Ain PB1 Ain PB2 Ain PB3 Ain PBA AIn 1 2 3 4 5 6 7 8 9 732323 0080171 TT3 ST6210B 15B 20B 25B PAO PA3 PA4 PA7 These 8 lines are organized as one port A Each line may be configured under software control as inputs with or without in ternal pull up resistors interrupt generating inputs with pull up resistors open drain or push pull out puts PAO PA3 can also sink 20mA for direct LED driving while PA4 PA7 can be programmed as an alog inputs forthe A D converter Note PA4 PA7 are not available on ST6210B ST6220B PBO PB7 These 8 lines are organized as one port B When the External STOP Mode Control option is disabled each line may be configured under software control as inputs with or without in ternal pull up resistors interrupt generating inputs with pull
83. tive appliance and industrial applications PAO PA3 20mA Sink lt PORTA pag PAT Ain PORT B Cl EPBO PB7 Ain a gt PORT C Kol E2PC4 PC Ain NOT AVAILABLE ON ST62T10 T20 E20 TIMER DIGITAL WATCHDOG 5 68 7929237 0080157 b23 Mi 5762710 T15 T20 T25 ST62E20 E25 1 2 DESCRIPTION Vpp and Ves Power is supplied to the MCU via these two pins Vpp is the power connection and is the ground connection OSCin and OSCout These pins are internally connected to the on chip oscillator circuit A quartz crystal a ceramic resonator or an external clock signal can be connected between these two pins The OSCin pin is the input pin the OSCout pin is the output pin RESET The active low RESET pin is used to re start the microcontroller TEST Vpp The TEST must be held at for nor mal operation If TEST pin is connected to 12 5V level during the reset phase the EPROM programming Mode is entered NMI The NMI pin provides the capability for asyn chronous interruption by applying an extemal non maskable interrupt to the MCU The NMI input is falling edge sensitive A pull up device must be provided externally on OTP and EPROM devices TIMER This is the timer pin In input mode it is connected to the prescaler and acts as external timer clock input or as control gate input for the in ternal timer clock In output mode the timer pin outputs the data bit when a time ou
84. tive by setting the In terrupt Option Register IOR accordingly The two interrupt vectors located respectively at addresses OFF2h OFF3h and addresses OFFOh OFF1h are respectively known as Interrupt Vec tors 3 and 4 Vector 3 is associated with the TIMER peripheral and vector 4 with the A D Converter peripheral Each on chip peripheral has an associated inter rupt request flag TMZ for the Timer EOC for the A D Converter which is set to 1 when the pe ripheral generates an interrupt request Each on chip peripheral also has an associated mask bit ETI for the Timer EAI for the A D Converter which must be set to 1 to enable the associated interrupt request 3 4 2 Interrupt Priorities The Non Maskable Interrupt request has the high est priority and can interrupt any interrupt routine at any time the other four interrupts cannot inter rupt each other If more than one interrupt request is pending these are processed by the processor core according to their priority level vector 1 has the higher priority while vector 4 the lower The priority of each interrupt source is fixed 37 68 ST6210B 15B 20B 25B IINTERRUPTS Cont d 3 4 3 Interrupt Option Register IOR The Interrupt Option Register IOR is used to en able disable the individual interrupt sources and to select the operating mode of the external interrupt inputs This register is write only and cannot be accessed by single bit operati
85. truction is ex ecuted and the MCU remains in non maskable in terrupt mode even if another interrupt has been generated 3 5 3 3 Normal Interrupt Mode If the MCU was in interrupt mode before the STOP or WAIT instruction was executed it exits from STOP or WAIT mode as soon as an interrupt oc curs Nevertheless two cases must be consid ered If the interrupt is a normal one the interrupt rou tine in which the WAIT or STOP mode was en 42 68 7125237 0080194 STO NN tered will be completed starting with the execution of the instruction which follows the STOP or the WAIT instruction and the MCU is still in the interrupt mode At the end of this rou tine pending interrupts will be serviced in accord ance with their priority In the event of a non maskable interrupt the non maskable interrupt service routine is proc essed first then the routine in which the WAIT or STOP mode was entered will be completed by executing the instruction following the STOP or WAIT instruction The MCU remains in normal interrupt mode Notes To achieve the lowest power consumption during RUN a WAIT modes the user program must take care of configuring unused I Os as inputs without pull up these should be externally tied to well defined logic levels placing all peripherals in their power down modes before entering STOP mode selecting the Low Frequency Auxiliary Oscillator provided this runs at a lower
86. uest associated with Interrupt Vec tor 43 is generated When the counter decrements to zero the TMZ bit in the TSCR register is set to one VA00186 Cont d 4 2 6 Application Notes The user can select the presence of an on chip pull up on the pin as ROM mask option see Option List at the end of the Datasheet TMZ is set when the counter reaches zero how ever it may also be set by writing 00h in the TCR register or by setting bit 7 of the TSCR register The TMZ bit must be cleared by user software when servicing the timer interrupt to avoid unde sired interrupts when leaving the interrupt service routine After reset the 8 bit counter register is loaded with OFFh while the 7 bit prescaler is load ed with 07Fh and the TSCR register is cleared This means that the Timer is stopped PSI 0 and the timer interrupt is disabled If the Timer is programmed in output mode the DOUT bit is transferred to the TIMER pin when TMZ is set to one by software or due to counter decrement When TMZ is high the latch is trans parent and DOUT is copied to the timer pin When TMZ goes low DOUT is latched A write to the TCR register will predominate over the 8 bit counter decrement to function i e if a write and a TCR register decrement to 00h occur simultaneously the write will take precedence and the TMZ bit is not set until the 8 bit counter reaches 00h again The values of the TCR and the PSC
87. up resistors open drain or push pull out puts and as analog inputs for the A D converter When the External STOP Mode Control option is enabled PBO output Mode is forced as open drain push pull output is not possible The other lines are unchanged PC4 PC7 These 4 lines are organized as one I O port C When the External STOP Mode Control option is disabled each line may be configured under software control as inputs with or without in ternal pull up resistors interrupt generating inputs with pull up resistors open drain or push pull out puts and as analog inputs for the A D converter When the External STOP Mode Control is enabled PC7 output Mode is forced as open drain push pull output is not possible The other lines are un changed Note PC4 PC7 are not available on ST6210B ST6220B Figure 4 ST6215B ST6225B Pin Configuration Vpp Vss TIMER PAO OSCin PA1 OSCout PA2 NMI PA3 Ain PC7 PA4 Ain Ain PC6 PAS Ain PA7 Ain PBO Ain PB1 Ain PB2 Ain PB3 Ain PB4 Ain Ain PCS Ain PC4 TEST RESET Ain PB7 Ain PB6 Ain PB5 19 68 5 6210 15B 20 25B 1 3 1 3 1 Introduction a Risen tease oun user program The MCU operates in three separate memo soc and user vectors Data space con spaces Prodam space Data Suc and tains user data RAM and and Stack space Operation in these three memory spaces is accommodates six levels of stack for sub d
88. utine and interrupt return addresses as well as the current program counter contents 22 68 Table 1 ST6210B ST6215B ST6220B and ST6225B Data Memory Space NOT IMPLEMENTED DATA ROM WINDOW 64 BYTES X REGISTER Y REGISTER V REGISTER W REGISTER DATA RAM 60 BYTES RESERVED RESERVED WATCHDOG REGISTER RESERVED ACCUMULATOR WRITE ONLY REGISTER 7125237 0080174 702 Mi 000h O3Fh 040h 07Fh 0808 081h 082h 083h 084h OBFh ocoh OCth 0C2h O0C3h 0C5h 0 6 OC7h oC8h oCgh OCAh OCBh OCCh OCDh OCEh OCFh OD1h oD2h OD3h OD4h 0051 0078 oD8h OD9h OFEh OFFh MEMORY MAP Cont d 1 3 5 Data Window Register DWR The Data ROM window is located address 0040h to address 007Fh in Data space It allows di rect reading of 64 consecutive bytes located any where in ROM memory between address 0000h and 1FFFh top memory address depends on the specific device All the ROM memory can there fore be used to store either instructions or read only data Indeed the window can be moved in steps of 64 bytes along the ROM memory by writing the appropriate code in the Write only Data Win dow register DWR register location O0C9h The DWR register can be addressed like any RAM location in the Data Space at address 00 it is however a write only register and cannot be ac cessed using single bit operations This register is used to move the 64
89. ximum ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability 1 Within these limits clamping diodes are guarantee to be not conductive Voltages outside these limits are authorised as long as injection current is kept within the specification 2 The total current through ports A and B combined may not exceed 50mA The total current through port C may not exceed 50mA If the application is designed with care and observing the limits stated above total current may reach 100mA THERMAL CHARACTERISTIC 20 8 mso Thermal Resistance 58 68 4 792923 0080210 573 ST6210B 15B 20B 25 6 2 RECOMMENDED OPERATING CONDITIONS e MUST 6 Suffix Version 40 5 Operating Temperature 1 Suffix Version 0 me 70 IT ev Programming Voas Pin Injection Current positive Digital Input Analog Inputs Pin Injection Current negative Digital Input Analog Inputs Notes If a total current of 1maA is flowing into a single analog channel or if the total current flowing into all the analog inputs is 1mA all resulting A D conversions will be shifted by 1 LSB If a total positive current is flowing into a single analo

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