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DIMEtalk 3.1 User Guide

1. 44 Figure 53 Make Component Tab Invisible 45 Figure 54 Make Individual Components Invisible 45 Figure 55 Edit Block RAM Comwponent eee ee eese eese entente tete eene tnter ener nent 46 Figure 56 Editor D 46 Figure 57 Signals Tab in Component Editor 46 Figure 58 Support Files Tab in Component Edictor 47 Figure 59 Parameters Tab in Component Edictor 47 Figure 60 Edit constraints for pci host interface 47 Figure 6l Component Constraints tab in Component Editctor 48 viii www nallatech com NT 107 0305 Issue 3 November 24 2006 List of Tables Table I FUSE Naming Conventions xiii Table 2 DIMEtalk Components
2. 28 Manip lating Componentes u ire 29 Using the Component Editor 29 PUP TEC GC uu 30 Vyliar are D gt c IO 30 Assigning Components to a Device 30 the Device L i OP ocean ipn ec IIO LINEAE UDIN EDIT M DII 3l Connectivity and Constraints 33 Adding Signal BPedaleOUES sena ceri netta prr SERIE 33 Creating d BusSGOn neGlIoBu uU a pan iua 33 Creating Subsystems 33 Add Bor unu esa seers aun ete 34 Using Clocks within DIMEtalk 35 INTI07 0305 Issue 3 November 24 2006 www nallatech com vi Code Generation ou cccccccccccccscsssccsseccccscsscscscsscscsssscscssssescssssesessssessssssesscacscssssesssscscsesscsesesscaeseees 36 STIS MCU a eR SS u AA 36 Files Created during VHDL Generation 37 Creating a Xilinx Project Navigator File
3. 5 Table 3 DIME talk MENUS EE E DELETE 24 Table 4 DIMEtalk File Descriptions 37 NT107 0305 Issue 3 November 24 2006 www nallatech com ix This bage intentionally blank www nallatech com NT107 0305 Issue 3 November 24 2006 DIMEtalk 3 1 User Guide About this User Guide Using this manual This User Guide provides information on using DIMEtalk The manual is designed to provide information for users of DIMEtalk to become acquainted with the tool its features and the functionality it provides After reading the introduction you should proceed with the getting started section which describes how to install DIMEtalk and how to build a simple network The implementation section describes in detail how to use the DIMEtalk interface and contains information on components devices connectivity and code generation Several example tutorials are also detailed For information on individual DIMEtalk components and data packet structure see the DIMEtalk Reference Guide For additional application notes please visit www nallatech com applicationnotes For information on using the DIMEtalk Application Program Interface see the FUSE C C API Developer s Guide Symbols Used Throughout this manual there are symbols to draw attention to important inform
4. 38 DIMEtalk Tutorials ananassa 39 Connecting Signals to External Pins a tutorial sss 40 Using the DIMEtalk Library Manager a tutorial 44 www nallatech com INTI07 0305 Issue 3 November 24 2006 List of Figures Figure I DIMEtalk in FPGA System 4 Figure 2 Example Multiple FPGA Network 6 Figure 3 DIMEtalk System Design 6 Figure DIMEtalk ary m 10 Figure 5 Initial DIMEtalk Network Projected onto Hardware 10 FU roO CIO Figure Router Component 12 Figure 8 Block RAM Component 12 Figure 9 Edit Block RAM Memory Address Width 3 Figure 10 Wired NetworkK
5. 36 clock frequencies 36 DIMEtalk clock 36 DIMEtalk network reset 36 host clock u m 36 iser CIO Ce aaa qan 36 external view 35 internal 35 using DIMEtalk 21 www nallatech com NT107 0305 Issue 3 November 24 2006 Remarks Form We welcome any comments you may have on our product and its documentation Your remarks will be examined thoroughly and taken into account for future versions of this product DIMEtalk 3 1 User Guide 107 0305 Issue 24 11 06 Errors Detected Suggested Improvement Please send this completed form to Nallatech Boolean House One Napier Park Cumbernauld Glasgow G68 0BH United Kingdom If you prefer you may send your remarks via E mail to support nallatech com or by fax to 44 0 1236 789599 If you want Nallatech to reply to your comments please include your name address and telephone number This bage intentionally blank
6. hat LRA Once L anno ono 0 Es Figure 5 Initial DIMEtalk Network Projected onto Hardware 10 www nallatech com NT 107 0305 Issue 3 November 24 2006 DIMEtalk 3 1 User Guide v To build a new DIMEtalk network use the following procedures l In the task bar select Start gt Programs gt Nallatech gt DIMEtalk Design Tools and DIMEtalk System Design which brings up the DIMEtalk System Design tool The first step is to choose a component This enables a user to connect a network to the available host In this case it is assumed that the motherboard is connected to a PCI bus Therefore select the PCI component in the Edges tab Once the button is depressed click in the window area below to insert this component When a component is placed down the user is prompted to enter a name for it Enter a name and click OK as shown in Figure 6 DIME Syst Darign Dega 9 eo a Hedges Bariz iniemal modes TBT Moder Bridger Synem SORAM DIME Legacy ockFUAM Hodes AB 0 Enter name ef component Figure 6 PCI Edge INTI07 0305 Issue 3 November 24 2006 www nallatech com Getting Started 2 At the heart of DIMEtalk networks are the routers which allow packets to move between various components in the network Go to the Routers tab to select the Router component and place it down in the network as shown in Figure 7 Syxtnma Design
7. 519 Edges Basic iriemal FPGA nodes ZET Moder Bridger Ponten Synem SORAM DIME Legacy RAM Nodes 2 28 088 p HEL Gemnceralion Gereested Filer Generation Leg Currus e Pc LE cap tc rrr skal 121 TEL 5 Lr a EE and tel Lis rome TC rete pakar Prog Lamp eed modus Fel airian od rues TEL bonpia nat ceda dede ian Propecti E imple ate E ample usce i C fle dhovang DIME hal Cidre dede uan Proech WE kamples D implet later T sarapa links pies dev Project use rath Dey C dmt E samples aor lyra ki hu iie Coria meted dencnplon Ernesti uite nian samples imple oshswork ounce kak na k bo List of pounce and core tier bo bud T op Propecia E source Ueska TL commands for spa yoni H ode Cohiba Pope SE es WHOL dence ene lor Tope V idera Bee tn Poe SE arp Seek Ibin EE P peopel he ubera d ftc Frog t comple aki ounce Fem T Y ir WHOL urea Gram Bend YO Lern lh ier FP op SE scmper kecam Ae Oo TEL bo bude Ben YO dris al V mpl kanpa mban an PIE Lih f exce asd cone L heal Ian LR 0 Usenet ab tian Prec AE ipii paek cue De
8. 27 connect components to netvwolk 28 connectivity and constraints 33 create a bus connection 33 create a subsystem 33 D DIMEtalk devices 30 assigning components to a device 30 device editor 3l L 3l device overview 30 DIMEtalk System Design 22 component editor 29 general 5665 29 30 TT 30 SHDDOPE MES 30 library manager a 26 manipulating components 29 OVE E 22 start DIMEtalk System Design 22 toolbars and 23 24 www nallatech com DIMEtalk 3 1 User Guide Index DS 23 foro or NM 23 39 F FUS
9. IE HMM 13 PUSS WN CALS SVC Seca 14 Figure 12 Device Selection 14 rs ure Device ia i i 5 Figure 4 Resize BenNUEY PCI Device 5 Figure 15 Clock amp Reset Component l6 Figure Siye aus UE l6 Figure Compia BR dora u epidemia dei 7 Figure M 7 Figure 19 Warnings and Error u 18 Figure 20 DIMEtalk System Design Editor 22 Figure 21 DIMEtalk System Design Toolbar 23 Figure 22 DIMEtalk System Design Tabs 23 Paure 25 LOC i a Dod u S S 25 Figure 24 DIMEtalk System Design Workspace 26 Figure 25 DIMEtalk C
10. Fle Cat Yew Utilities Generation Helo Heb Sse UH FAD Eger Bane itema FPGA nodes ZET Moder Bridger outer Sunem SORAM DIHET Legacy Boci RAH pun 0 Figure 7 Router Component 3 A functional node in this case a block RAM component should be placed down to ensure the network can be implemented properly Go to the Basic internal FPGA internal nodes tab and select the block RAM node as shown in Figure 8 DIME talk Symtama Design amp 4 XDA l e 8 2 9 FPG0 nadar Node Bridger outers System SORAM DIHET Legacy Boci RAH Wadea pxi hest Di Ada 0 Figure 8 Block Component 4 Once the block RAM node has been placed down there are certain parameters associated with the node which can be changed For example the memory address width can be altered which changes the size of the memory created by the network To do this right click on the block RAM component in the 12 www nallatech com NT 107 0305 Issue 3 November 24 2006 DIMEtalk 3 1 User Guide network and select Edit In the component editor go to the Parameters tab and change the address width from 12 to 9 as shown in Figure 9 Changing this width from 12 to 9 creates a 512 word memory DIME talle Synta Benign s e j eo 8 9 Edger iniemal nodar Moder Bridger System SOR
11. Toolbar The DIMEtalk System Design toolbar provides quick access to frequently used operations and commands The toolbars used in DIMEtalk System Design are shown in Figure 21 with their functions listed Load Design i Refresh Open Library Manager New Design Save Design Route Goupa Generate Help Network Level in VHDL Connections Network Figure 21 DIMEtalk System Design Toolbar Tabs The tabs used in DIMEtalk System Design are shown in Figure 22 EStG SES Figure 22 DIMEtalk System Design Tabs INTI07 0305 Issue 3 November 24 2006 www nallatech com 23 Using DIMEtalk 24 Menus The menus available in DIMEtalk System Design provide the same functions as the standard tool bar with additional features such as the ability to save a design as an HTML file as well as other specific functions such as packaging up a design and zooming in on the navigator using the Navigator Zoom menu The menu contents are shown and explained in Table 3 Menu Description Allows user to File menu DIMEtalk Systems De Edit wiew Utilities New Ctrl M Open Cro d Save Ctrl 5 save s CtrtAlk s Close gt Reopen k Print Document in HTML l Exit Edit menu undo last action E e redo last undone action mE View Utilities Gene cut an item lt Undo Ctrl z copy an item Redo CteAkez paste an item M cut Ctrl BY Ctrl C delete an item 1 Faste select all items in DIMEtalk S
12. 35 Figure 40 Clock Driver Module Component Internal 35 Figure 4l Tcl File to Build Application 36 INTI07 0305 Issue 3 November 24 2006 www nallatech com Figure 2 Warnings and Re 37 Figure 43 Files Created During VHDL Generation 37 Figure Lock signal orientiert DRM 40 Figure 45 DIMEtalk Device Editor 41 Ligure 46 Constraint Editor uu suu au baa ia a emen MEI e NE 41 Figure 47 lock signal dragged to led l pin 42 Figure 49 lock connected e 42 Figure 49 Constraints File created for BenNUEY_0 43 Figure 50 UCF Showing Constrained Signal 43 Figure SI Library Manager BUCOM eee tore eher ebat cero See bon S echtes Sonn asian 44 Figure 52 Moving Components within Library Manager
13. DIMEtalk Signals user data in std logic vector 31 downto 0 Reset user data out out std logic vector 31 downto 0 Raw Reset B Doorbells CO ES E CLKA CLKAx2 CLKBx2 Raw CLKB CLKC CLKCx2 Raw CLKC Raw CLKA Cancel 46 Figure 57 Signals Tab in Component Editor www nallatech com INTI07 0305 Issue 3 November 24 2006 DIMEtalk 3 1 User Guide 9 The Support Files tab shown in Figure 58 displays all the files that are required for any design using this component Click on OK Component Editor block ram dtc General Signals Support Files Parameters Component Constraints C dimetalk dtdesign Components BlockRAM Nodes lt All bloc Design file All devices C dimetalk dtdesignNComponentsscommon dtnode slave co Design file All devices C dimetalk dtdesign Components common bretime vhd Design file All devices E dimetalk dtdesignsComponentsscommon retime vhd Design file All devices E dimetalk dtdesignNComponentsXBlockRAM Nodes All xst_ Design file All devices C dimetalk dtdesign Components common pkg_dimetalk_glo Design file All devices Figure 58 Support Files Tab in Component Editor 10 The Parameters tab shown Figure 59 displays parameters which can alter a components behavior Click on OK Component Editor block ram dtc General Signals Support Files Parameters Component Constraints Description Node Identifier std l
14. Faults incurred by abuse of the product as defined by the company are not covered by the warranty Attempted repair or alteration of the goods as supplied by the company by another party immediately invalidates the warranty offered The said warranty is contingent upon the proper use of the goods by the customer and does not cover any part of the goods which has been modified without Nallatech s prior written consent or which has been subjected to unusual physical or electrical stress or on which the original identification marks have been removed or altered Nor will such warranty apply if repair or parts required as a result of causes other than ordinary authorized use including without limitation accident air conditioning humidity control or other environmental conditions Under no circumstances will the company be liable for any incidental or consequential damage or expense of any kind including but not limited to personal injuries and loss of profits arising in connection with any contract or with the use abuse unsafe use or inability to use the companies goods The www nallatech com company s maximum liability shall not exceed and the customers remedy is limited to either i repair or replacement of the defective part or product or at the companies option ii return of the product and refund of the purchase price and such remedy shall be the customer s entire and exclusive remedy Warranty of the software written
15. In the Library Manager window drag a component folder in this case Basic internal FPGA nodes to the top of the tree as shown in Figure 52 Close the Library Manager and in the DIMEtalk design window this tab now appears as the first tab Basic internal FPGA nodes folder Tab moved in DTDesign Tool dragged to top of tree x DIMEtalk Systems Design Component Library Manager Sel fle Ld eb Library Addtalibrary Design Tools About Heb 8 e x 5d aag Bonc mtemal FPGA noder Edges ZBT Nodes Bridges Routers System SORAM DIME Legacy lockFUAM Nodes User Component Components Library Log s lt e Bp 3 Basic internal FPGA nodes Edges ZET Nodes Bridges Routers Spaten SDRAM DIME C Legacy BlockRAM Nodes User Components Figure 52 Moving Components within Library Manager 3 Entire tabs can also be made invisible using the Library Manager For example right click on the Basic internal FPGA nodes in the Library Manager and select Make Invisible from the menu which appears as shown in Figure 53 Close the Library Manager and in DIMEtalk System Design the Basic internal FPGA nodes tab is no longer visible To change this open the Library Manager again and click on the 44 www nallatech com NT 107 0305 Issue 3 November 24 2006 DIMEtalk 3 1 User Guide Basic internal FPGA nodes folder and select Make Visible from the
16. Nallatech reserves the right without prejudice to any other remedy to cancel any uncompleted order or to suspend delivery in the event of any of the customer s commitment with Nallatech not being met DELIVERY All delivery times offered by the company are to be treated as best estimates and no penalty can be accepted for non compliance with them Delivery shall be made by the company using a courier service of its choice The cost of the delivery plus a nominal fee for administration will be added to the invoice issued Payment of all inward customs duties and fees are the sole responsibility of the buyer If multiple shipments are requested by the buyer multiple delivery charges will be made In the case of multiple deliveries separate invoices will be raised If requested at the time of ordering an alternative delivery service can be used but only if account details are supplied to the company so that the delivery can be invoiced directly to the buyer by the delivery service The buyer accepts that any to be advised scheduled orders not completed within twelve months from the date of acceptance of the original order or orders held up by the buyers lack of action regarding delivery can be shipped and invoiced by the company and paid in full by the buyer immediately after completion of that twelve month period INSURANCE All shipments from the company are insured by them If any goods received by the buyer are in an unsatisf
17. Powerful tool for designing and deploying embedded communications networks within FPGA systems Networks provide integrated communication between user algorithm blocks in multiple FPGAs and the host system VME cPCI etc Intuitive GUI software interface for network design Drag and Drop User Constraints UCF editing for Nallatech hardware Automatic synthesizeable VHDL code generation Supports Xilinx Virtex ll Virtex Il Pro Virtex E and Virtex 4 Low FPGA resource requirements Directly supports all Nallatech DIME II hardware products Dedicated DIMEtalk FUSE API functions C C Tcl These functions can be found in the FUSE C C API Developer s Guide NT 107 0305 Issue 3 November 24 2006 www nallatech com 3 DIMEtalk Overview 1 1 2 How DIMEtalk Works Within a Nallatech FPGA Computing System Figure shows how DIMEtalk abstracts the features of the hardware platform to provide an easy to use development environment for implementing applications on multi FPGA systems Standard VHDL design flows are complemented with support for third party compiler tools alongside an integrated C to VHDL Function Generator DIME C enabling developers to select the design flow most appropriate to their application Communications networks between algorithm blocks memory and I O interfaces can be rapidly created across multiple FPGAs through the GUl based application development environment This functi
18. 2 Routers System 2 SDRAM gt DIME C Legacy BlockRAM Nodes User Components Package component Move EIER Figure 54 Make Individual Components Invisible 5 In DIMEtalk System Design go to the Basic internal FPGA nodes tab where the block RAM node is no longer visible To change this open the Library Manager again open the Basic internal FPGA nodes folder and right click on block RAM to select Make Visible from the menu which appears Close the Library Manager and this component is now visible again in the Basic internal FPGA nodes tab in DIMEtalk System Design 6 In the Library Manager open the Basic internal FPGA nodes folder and select the block RAM component shown in Figure 55 Note that the location of the definition and the date on which it was saved are INTI07 0305 Issue 3 November 24 2006 www nallatech com 45 DIMEtalk Tutorials shown under the component Double click on the block RAM component to open the Component Editor Component Library Manager Sele Library Add to Library Design Tools About Components Library Log amp Basic internal FPGA nodes block_ram xw read fifo xw write fifo x K fifo loopback xw master x memory map x memorymap test amp Edges 2 ZBT Nodes Bridges 2 Routers amp System 2 SDRAM C DIME C Legacy BlockRAM Nodes User Components Fh ET RET RED ET ETE 7 Figure 55 Edit Block RAM Component The Co
19. C Ves eee 11152 5 ee b 1 Figure 13 Device Type 9 Once the BenNUEY PCI device is placed down on the network it should be resized by dragging the resize handle in the bottom right hand corner to cover all the components as shown in Figure 4 This informs DIMEtalk that all these components are to be assigned to this device ega se 2B eo FAs Edges HarnciriemalFPGA noder T Nodes Bridger Routers Syrtem SORAM DIHET Legacy Medes B fin fin D Xo pg 0 enh UE PCI t vine Thes Biot HME mothercoard irm 1 Be hast intedace 0 Adar D router CL Figure 14 Resize BenNUEY PCI Device INTI07 0305 Issue 3 November 24 2006 www nallatech com 15 Getting Started 10 All FPGA devices need a component to handle clocking and resets Go to the System tab to select the Clock amp Reset component and place it down on the device then click on OK as shown in Figure 15 DIME talk Pie Cat Yew Utis aeneo Pelo Heb amp e xR Le an AS Edper iriemal FPGA nodes ZET Hodet Aouters Sytem SCAM DIHET Legacy isch Hodes BenNUEY 0 Ben UD PCI k Vinesctz Thes Hot HME motherboard iam Qo 1 0 pe U rky 0 hauler U Fifi e Y firan Herne Figure 15 Clock amp Reset Component l Before continuing further the network should b
20. Flash Player in order to view them Please visit http www macromedia com go getflashplayer to download the latest Flash Player For information on other DIMEtalk features and applications please visit www nallatech com applicationnotes INTI07 0305 Issue 3 November 24 2006 www nallatech com 39 DIMEtalk Tutorials 4 1 Connecting Signals to External Pins a tutorial This tutorial shows how to assign specific signals to external physical pins through a DIMEtalk network Signals that need to go to external pins are identified by DIMEtalk and largely routed automatically to appropriate pins Occasionally however users may wish to route a non essential signal to an external pin for example the lock signal of the Clock amp Reset component v To connect a signal to an external pin through DIMEtalk use the following procedures l Load the network created in Building a DIMEtalk Network 2 The Clock amp Reset component has a lock signal shown in Figure 44 which indicates that all the clocks are operating correctly For this tutorial the signal is brought out to an LED Systama Design deren re jacta UE samples impleMp Pee i3 Pie Cat Yew Uter Genention Hel s e eo 2 Edges Basic riemal FPGA nodes ZET Moder Bridger Routers System SORAM DIHET Legacy Boci RAH BerH LES PCI t vriet Thre
21. by the company shall be limited to 90 days warranty that the media is free from defects and no warranty express or implied is given that the computer software will be free from error or will meet the specification requirements of the buyer The terms of any warranty offered by a third party whose software is supplied by the company will be honoured by the company exactly No other warranty is offered by the company on these products Return of faulty equipment after the warranty period has expired the company may at its discretion make a quotation for repair of the equipment or declare that the equipment is beyond repair PASSING OF RISK AND TITLE The passing of risk for any supply made by the company shall occur at the time of delivery The title however shall not pass to the buyer until payment has been received in full by the company And no other sums whatever shall be due from the customer to Nallatech If the customer who shall in such case act on his own account and not as agent for Nallatech shall sell the goods prior to making payment in full for them the beneficial entitlement of Nallatech therein shall attach to the proceeds of such sale or to the claim for such proceeds The customer shall store any goods owned by Nallatech in such a way that they are clearly identifiable as Nallatech s property and shall maintain records of them identifying them as Nallatech s property The customer will allow Nallatech to inspect thes
22. file Load and test network Wish script Table 4 DIMEtalk File Descriptions www nallatech com 37 Using DIMEtalk File Created sysdesc tcl example c examplec dev make buildinput txt simutils tcl top vhd ucf dimebuild tcl build tcl buildinput txt buildopt txt Description Tcl file C file dev file make file Text file Tcl file VHDL file User Constraints File VHDL file Tcl file Tcl file Text file Text file Function Definition of network for Tcl scripts not executable code Example C code showing DIMEtalk network access Project file for Dev C IDE www bloodshed net Allows the user to build the example c using gcc compiler in Linux List of source and core files to build Top Useful Tcl commands for simulation ModelSIM VHDL source code for Top Constraints for device VHDL source code for device Top level build script which calls each devices build tcl Tcl script to build device This script takes all the files needed to generate the bitfile and copies them into a tmpcore and tmpsource folder within the device s output directory Then it calls the various Xilinx ISE processes and generates a bitfile from the files in tmpcore and tmpsource Before bitfile generation it also generates an ISE project navigator project file List of source and core files to build device Build options for device Table 4 DIMEtalk File Descriptions 3 5 3 During the build process DIME
23. lower black terminal block RAM doorbell port and select Wire up a level Then right click on the device and select Edit to open the Device Editor as shown in Figure 31 Right click on block RAM doorbell port and select Wire upa Right click on device and select Edit to open Device Editor Level Figure 31 Assigning Signals to Pins NT 107 0305 Issue 3 November 24 2006 www nallatech com 3l Using DIMEtalk 32 With the Device Editor open go to the right hand Device Information pane and double click on blockram 1024 0 as shown in Figure 32 Device Editor Double click to open the Constraint Editor BenNUEY D Device ptions Virtex2 xc2v3000 ff1 152 4 C Virtex2 xc2v3000 ff1 152 5 DOO fF1 152 5 Virtex2 xc2v6000 ff1 1523 C Virtex2 xc2v6D000 ff 152 5 Virtex2 xc2vBODO ff1152 5 C Mirtex2 xc2v8000 f1152 4 Mirtex2 xc2v8000 ff1 152 5 Mirtex2 xc2v8000 ff1152 5 C Virtex2 xc2v40D0 ff1152 4 Virtex2 xc2v4D00 ff 152 5 Virtex2 xe2v4000 f1152 6 Motherboard Onboard device On board FPGA System View Edit Devices Log Device Information Double click component names to edit local constraints Global Variables Resolved Constraints Unused Pins pci host interface D router 0 Local variables Component class constraints Specific instance constraints Unconstrained signals Constrained signals Resolved constraints clocks_0 Cancel OK Figure 32 Open th
24. menu which appears The tab is now visible again in the DIMEtalk design window Basic internal FPGA nodes Tab now invisible DTDesign Tool folder made invisible Component Library Manager Seles UEM aa Library Add to Library Design Tools About amp g a 3 x FR L e Sa amp 3 Edga ET SOHAM DIMES Laga Block AM Hirax Loe Components Library Log a des DB ASIC intera Edge FET Delete Bridg Component Group 2 Rout 7 2 Syste iis c z SDR Make Invisible gt DIME Package component Lega pave gt Userhoomporens EIE SII S dee ee S RP ES Figure 53 Make Component Tab Invisible 4 Individual components can also be made invisible In the Library Manager open the Basic internal FPGA nodes folder right click on block RAM and select Make Invisible as shown in Figure 54 Individual component made Component now invisible in Basic internal FPGA nodes tab invisible DME talk Syst Component Library EBR ee Library Add to Library Design Tools About Des amp s e X HR ee a s rh Basic intemal FPGA nodes E doer ZT Noser Broer Poden Sorte SORAM DIME Legacy friockfLAM Hodes Uter Components omponents Library Log Basic internal FPGA nodes xw rm Edit w Delete fil Component Group xo om Make Visible cw rZ amp Edge amp zBTI Brida
25. 24 2006 www nallatech com 9 Getting Started CD_ Drive V autorun exe In the DIMEtalk menu which appears click on Install DIMEtalk Design Tools 2 The DIMEtalk setup wizard appears Work through the series of dialog boxes until the Finish box is reached 3 Click Finish to install the software 2 2 Building a DIMEtalk Network This section describes how to create an initial DIMEtalk network and provides an introduction to the tool and its various components This initial example can be used to explore the various options in the DIMEtalk System Design toolbar and menus and to become familiar with the network creation process Figure 4 shows a simple network in the DIMEtalk System Design tool containing a node a router and an edge Note that the exact order of the component tabs are configurable so they may not look the same between different systems DIMEtalk Synim Desipn File Cat Yew Utities Genenstion lebo Heb Grae xR Let an ASG Eapen Boric temal moder SET Moder Bridgen Powter Sytem SERAM DIHET Legaey Eck FAM Redes BenNUEY 0 Den Lat PCI k Thes Shot DHE motherboard im U Ada 1 amp bzks pei host U rky 0 hauler U femen Figure 4 Initial DIMEtalk Network Figure 5 shows how these components node router edge relate to the physical hardware used in this case a BenNUEY PCI motherboard dou al T D
26. AM DIHET Legacy Redes PlotoD PHD Comporant Ldiior block ram General Suppi Fie Parameters ratare Conatan Hee Lender others wy 10 wich 12 AERIS vend B iam 1 Best 0 Add 0 Figure 9 Edit Block RAM Memory Address Width 5 The components must now be wired together using the red terminals at the side of each component Press the left mouse button when the cursor is over the red terminal on the right of the block RAM node While holding the mouse button down move the cursor over one of the red terminals on the right of the Router When the cross cursor is directly over a red terminal release the mouse button A wire should appear connecting the two red terminals together Repeat this step to wire the red terminal on the PCI Edge component to the Router The network is now wired together as shown in Figure 10 Systema Design fie DE Ver Uike Genertion ek HR Eager intemal FPOA nodar Z amp T Node Bridger Routers System SORAM DIHET Legacy Pinch RAH B fin fin IA Bisch im U Ada 1 Be hast nterace U Ad D router CD Figure 10 Wired Network INTI07 0305 Issue 3 November 24 2006 www nallatech com 13 Getting Started 6 The device on which this network will reside must be defined Right click in free space and select Create gt Device f
27. DIMEtalk 3 1 User Guide NT 107 0305 Issue 3 Contacting Nallatech Support WWW Go to www nallatech com and click support Email support nallatech com Phone Fax Europe and Asia Pacific Phone 44 0 1236 789500 WWW www nallatech com NALLATECH The High Performance FPGA Solutions Company North America Phone 877 44 NALLA www nallatech com NT 107 0305 Issue 3 November 24 2006 Document Name DIMEtalk 3 1 User Guide Document Number NT107 0305 Issue Number Issue 3 Date of Issue 24 11 06 Revision History Date Issue Number Revision 06 04 2006 2 Initial Release of 3 1 New to 3 1 User Guide Creating a Bus Connection Updates to Figure 22 Updates to Figure 34 New section Creating a Xilinx Project Navigator File Template updates Note added under Host System Requirements to show minimum ISE require ments for HIOI series components 24 11 2006 Intellectual Property The contents of this document are the copyright of Nallatech Limited Nallatech Limited 2006 All rights reserved The product name Nallatech the Nallatech logo The High Performance FPGA Solutions Company DIMEtalk DIMEscript DIME DIME II and FUSE are all trade marks of Nallatech Limited All names images and logos identifying Nallatech Limited or third parties and their products and services are subject to copyright design rights and trade marks of Nallatech Limited and or third part
28. E naming conventions xiii G getting started 9 implementatiO 2 19 hee 9 interactive tutorials xii Mro duU uuu au unamasa masaqa ee eee tee errr Key MC 3 placer effort level LRS 25 R related documentation xii I SISI M router effort level 25 S saving a DIMEtalk network 28 Scope of user xi system requirements 9 T Uer 39 using the DIMEtalk Library Manager 44 writing to an external pin 40 U undo redo commard 28 user guide symbols xi using clocks and resets 35 default u u au 36 53 igh Performance FPGA Solutions Company changing the default wirings
29. Editor 48 www nallatech com NT 107 0305 Issue 3 November 24 2006 INTI07 0305 Issue 3 November 24 2006 Standard Terms and Conditions GENERAL These Terms and Conditions shall apply to all contracts for goods sold or work done by Nallatech Limited hereinafter referred to as the company or Nallatech and purchased by any customer hereinafter referred to as the customer Nallatech Limited trading in the style Nallatech the company submits all quotations and price lists and accepts all orders subject to the following conditions of contract which apply to all contracts for goods supplied or work done by them or their employees to the exclusion of all other representations conditions or warranties express or implied The buyer agrees to execute and return any license agreements as may be required by the company in order to authorize the use of those licensable items If the licensable item is to be resold this condition shall be enforced by the re seller on the end customer Each order received by the company will be deemed to form a separate contract to which these conditions apply and any waiver or any act of non enforcement or variation of these terms or part thereof shall not bind or prejudice the company in relation to any other contract The company reserves the right to re issue its price list at any time and to refuse to accept orders at a price other than at the price stated on the price list in force at the time of
30. These override any default constraints Alternatively select the pins to use and drag these onto the first signal to be routed onto these pins Off chip signals Available Pins user doorbell in user doorbell inl user doorbell in2 user doorbell in3 user doorbell out connected to led 1 user doorbell out1 connected to led 2 user doorbell out2 connected to led 3 user doorbell out3 connected to led 4 Non default constrain l i e NET doorbell out LOC led 1 NET user doorbell out1 LOC led 2 NET doorbell out2 LOC led 3 ET user doorbell out3 LOC led 4 Figure 33 Drag Signals onto Pins Automapping DIMEtalk automatically maps some signals to pins Auto mapping is done on 4 bit bridges all edges clock amp reset components and ZBT components when wired up to the top level www nallatech com NT107 0305 Issue 3 November 24 2006 DIMEtalk 3 1 User Guide 3 4 Connectivity and Constraints 3 4 1 Adding Signal Breakouts This feature allows a user to breakout the signals within a connection group v To add a signal breakout use the following procedures l Right click on a component s red terminal port 2 Select Create Breakout from the menu which appears 3 The signal breakout is now placed down in the DIMEtalk System Design tool as shown by the red arrow in Figure 34 Block Ram Made node 1 block ram 0 Figure 34 Signal Breakout 3 4 2 Creating a Bus Co
31. a FIFO Test Loopback and a Memory Loopback User components can be added into a DIMEtalk network These components include the externally generated VHDL component and previously created DIMEtalk components Testbench components allow users to simulate devices in order to test networks in simulation tools i e ModelSim 3 2 2 Adding Components The first stage in generating a DIMEtalk network is to add and connect the various communications components for the design This is done in the DIMEtalk System Design tool v To add a component to a DIMEtalk network use the following procedures l In the DIMEtalk System Design tool select a component from one of the component tabs 2 Click in the design space to place the component down The component is then displayed shown in Figure 26 DIMEtalk Systems Design File Edit View Utilities Generation Help Figure 26 Add a Component INTI07 0305 Issue 3 November 24 2006 www nallatech com 27 Using DIMEtalk 3 2 3 Connecting Components v To connect components in a DIMEtalk network use the following procedures l In the DIMEtalk System Design tool move the cursor to the terminal of the first component 2 When the cursor turns into a cross press the left hand mouse button 3 Move the cursor to the terminal of the other component keeping the mouse button pressed when joining components 4 When the cursor turns into a cross and the name of the component appe
32. actory condition the following courses of action shall be taken If the outer packaging is visibly damaged then the goods should not be accepted from the courier or they should be signed for only after noting that the packaging has sustained damage If the goods are found to be damaged after unpacking the company must be informed immediately Under no circumstances should the damaged goods be returned unless expressly authorized by the company If the damage is not reported within 48 hours of receipt the insurers of the company shall bear no liability Any returns made to the company for any reason at any time shall be packaged in the original packaging or its direct equivalent and must be adequately insured by the buyer Any equipment sent to the company for any purpose including but not limited to equipment originally supplied by the company must be adequately insured by the buyer while on the premises of the company PAYMENT Nallatech Ltd terms of payment are 30 days net Any charges incurred in making the payment either currency conversion or otherwise shall be paid by the buyer www nallatech com 49 Standard Terms and Conditions 50 The company reserves the right to charge interest at a rate of 2 above the base rate of the Bank of Scotland PLC on any overdue accounts The interest will be charged on any outstanding amount from said due date of payment until payment is made in full such interest wil
33. ajects sE samples Simple Network E ample e amplec dey C dimetalk dtdesign PrajecEssE amples Simple Network sseuree sbulldinput bt C dimetalk dtdesign Prajects E amples Simple Matwork sseuree simutils tcl C dimetalk dtdesign Projects E amp amples sSimple Network source T C sdimetalk dtdesign Frajects E samples Simple M twark source sBenMNuewv D sBen C dimetalkdtdesign Prajects E xamples Simple M epweork source BenMuewv O Ben C dimetalk sdtdesign Prajects E amples sSimple Nehworksource B end uey_O Ben E dimetalk sdtdesignsPrajectssE amplessSimple Nate ark sseureesB enMN uev m us C dimetalk sdtdesign Prajects E samples Simple Metwisrk souree B sb C dimetalk dtdesign Prajects E samples Simple Metworkssource B enMueuy sb iA Beles N Comment Load and test network TCL Script Definition of network for TCL scripts not executable code Example C code showing DIMEtalk network access Project fle for Dey C IDE w bloodshed net List of source and core files to build Top Useful TCL commands for simulation MadelSIM VHDL source code for Top slins SE Project for BenMuey 0 Constraints for device BenNuey_O VHDL source code for BenNuey 0 TCL Script to build BenNuew 0 List of source and core files to build BenNuey_O Build options for Benue 0 Figure 43 Files Created During VHDL Generation File Created Description dimetest wish Function Wish
34. ars release the mouse button to join the two components To put an elbow in a wire click on one of the dots on the wire and drag the wire to the appropriate place as shown in Figure 27 DIMEtalk Systems Design File Edit View Utilities Generation Help DEAE LA 2 4 Four way non blocking s PCI Host IF OlMEtalk Router i OlMEtalk edge 0 router 0 A pci host interface 0 Figure 27 Connect Components At any point during the creation of a DIMEtalk network changes can be made using the Edit gt Undo Edit gt Redo menu commands Also note that a network can be saved using the File gt Save menu command If a design is closed without being saved DIMEtalk prompts the user to save the network 28 www nallatech com INTI07 0305 Issue 3 November 24 2006 DIMEtalk 3 1 User Guide 3 2 4 Manipulating Components DIMEtalk components can be manipulated using the right click menu shown in Figure 28 which is displayed when a network component is right clicked in the DIMEtalk System Design tool The function of each menu item is also listed in the following figure Opens the component Set the address of a node Renames a component editor Cuts a component from Edit the network to the clipboard component to Rename the clipboard Cut Ctrl Copy Paste Ctrl Delete Del Pastes a component to a new location Deletes a component Flips a componen
35. ation The red arrow symbol indicates a set of procedures to follow such as installing software or setting up hardware The blue i symbol indicates useful or important information The red symbol indicates a warning which requires special attention User Guide Format The User Guide is divided into Sections which are grouped into Parts The parts divide the document as follows Introduction Provides an overview of DIMEtalk and its key components plus a getting started section which details how to build an example network INTI07 0305 Issue 3 November 24 2006 www nallatech com xi About this User Guide DIMEtalk Implementation How to start using DIMEtalk System Design including a description of DIMEtalk components devices connectivity and code generation Example tutorials are also detailed Related Nallatech Documentation Nallatech DIMEtalk Reference Guide Nallatech FUSE C C API Developer s Guide Nallatech FUSE System Software User Guide Nallatech Tcl Plug In for FUSE Developer s Guide Abbreviations API Application Program Interface DAC Digital to Analog Converter DIME DSP and Image Processing Modules for Enhanced FPGAs FIFO First In First Out stack memory FIR Finite Impulse Response FPGA Field Programmable Gate Array FUSE Field Upgradeable System Environment IDE Integrated Development Environment e HO Input Output PCI Peripheral Compon
36. c i1 Dega amp se YOR Lee a a Eagen Barrie iniemal FPGA redes FET Nodes Bridger Posters Sytem SDRAM DIHE Legacy Fick LAM Nodes HEL Gemneralkon C uber ak ujar Prog th E Soap tva rmn tel Dern li aski TOL Senai tel ats romae TCL Ly chai old rues TCL bordada run tock cade ceda C fle hirang hk ui ase Project fle fia rath Bicod hed Dev C Header ide conbaining nete danonmbon Lint of pounce and core fier In baki Top TCL camarada for span eni Hodelt WHOL dence cw lor Tope Ta he Contras Pos dence Een Liz WHOL ionica Lo Beni TEL ta buki Bem EE Y 0 List oF bounce cote 15 bald ae LN YI lor Deci E 0 Figure 18 Build Network Fora complete listing of these files and their functions please see Table 4 INTI07 0305 Issue 3 November 24 2006 www nallatech com I7 Getting Started 14 When the script completes report of how many warnings and errors have been produced is displayed as shown in Figure 19 The DIMEtalk network is now built DIMILI Lali Syriam Dosign C Vdimatalkidt dazign Vra acia M nerwe rk dt3 Dega a ep xm ue oad Edger intemal FPGA nodes ZOT Nodes Bridges outer System SAMI DIME C Legacy Block PAM Node Running TEL s
37. ck of this User Guide you will find a remarks form We welcome any comments you may have on our product or its documentation Your remarks will be examined thoroughly and taken into account for future versions of Nallatech products INTI07 0305 Issue 3 November 24 2006 www nallatech com xiii About this User Guide This bage intentionally blank xiv www nallatech com NT 107 0305 Issue 3 November 24 2006 NALLATECH The High Performance FPGA Solutions Company Part l introduction This part of the User Guide provides an overview of DIMEtalk and describes how to install the software and build a simple network INTI07 0305 Issue 3 November 24 2006 www nallatech com This bage intentionally blank 2 www nallatech com NT107 0305 Issue 3 November 24 2006 DIMEtalk 3 1 User Guide Section DIMEtalk Overview In this section DIMEtalk Key Features 1 1 DIMEtalk Key Features 1 1 1 Introduction DIMEtalk enables developers to design packet based communications networks across multiple FPGAs These networks are then provided to the user through an automatic code generation mechanism for deployment within their application design DIMEtalk extends the capability of Nallatech cPCI VME PCI PCI X and 104 COTS FPGA computing systems This functionality offers a proven COTS solution designed for ease of use low risk system integration in field deployment Some of DIMEtalk s key features include
38. cript dimabulld tcl nre nnina level fer device is 1 Addicional information on Stepping jievel in available mupporr wil nw enm Opened conarrmincs file BenHUEY mncf Tum Sep 06 17 20 15 2005 Warning Running DRC DRC dececeed 0 errors and varni Cremrting hir map Soving hit stream in bennuey 0 Biratreamm generation is complete BITGEH af BenHUEY 0 complete Tu Figure 19 Warnings and Error This page intentionally blank 18 www nallatech com NT107 0305 Issue 3 November 24 2006 NALLATECH The High Performance FPGA Solutions Company Part ll DIMEtalk Implementation This part of the User Guide provides detailed information on how to use DIMEtalk and its key component DIMEtalk System Design Two example tutorials are also provided here INTI07 0305 Issue 3 November 24 2006 www nallatech com 19 This bage intentionally blank 20 www nallatech com NT107 0305 Issue 3 November 24 2006 Using DIMEtalk In this section Designing a DIMEtalk Network DIMEtalk Components DIMEtalk Devices Connectivity and Constraints Code Generation Xilinx Project File NT107 0305 Issue 3 November 24 2006 www nallatech com DIMEtalk 3 1 User Guide Section 3 21 Using DIMEtalk 22 3 1 DIMEtalk System Design Designing a DIMEtalk Network 3 1 1 Overview In order to create a DIMEtalk network the required nodes must be specified on the various
39. e Constraint Editor This opens the Constraint Editor where the LED signals should be dragged from the Off chip signals pane onto the correct pins in the Available Pins pane as shown in the left hand image in Figure 33 The signals are now assigned to the relevant pins and the constraints appear in the lower pane under Non default constraints The right hand image in the Figure 33 shows these constraints Drag LED signals onto correct pins Constraint Editor blockram_1024 0 Instructions Select the signals to be routed to specific pins Drag the selected signals onto the first pin Instance specific constraints will be created to form these routes These override any default constraints Alternatively select the pins to use and drag these onto the first signal to be routed onto these pins Off chip signals Available Pins user doorbell in user doorbell inl user doorbell in2 AS user_doorbell_out0 user_doorbell_out1 user_doorbell_out2 user doorbell out3 pci bp Ika 0 pci bp Ika 1 pci bp Ika 2 pci bp Ika 3 pci bp Ika 4 pci bp Ika 5 pci bp Ika 5 pci bp Ika 7 pci bp Ika 8 pci bp Ika S Non default constraints Signals now added to Non default constraints Constraint Editor blockram 1024 0 BAR Instructions Select the signals to be routed to specific pins Drag the selected signals onto the first pin Instance specific constraints will be created to form these routes
40. e Skor HHE motherboard ig D Aka 1 clocks j hoe mera U Ande Figure 44 Lock Signal 3 In order to make the lock signal available for external wiring right click the black terminal at the side of the Clock and Reset component and select Wire up a level from the menu Right click anywhere in the device to open the Device Editor In the Device Editor go to the Edit Devices tab and double click on the clocks 0 component as shown in Figure 45 40 www nallatech com INTI07 0305 Issue 3 November 24 2006 DIMEtalk 3 1 User Guide DIME talis System Janiga 2 ede trn jactr ME are ple pore i planner i13 ag Log B NUEY_D Device Denes Information D poble chol component names lo tdi local combent F Vite eR YS Guba Vanables Ves ez OO T1 152 5 Dornha OD TT Labs eo fin ete Yoon ick 0 c AORN TSS Vate 1524 F vrabia Vite sev OOITISA CO amp Valsx2 ede OQ HIT VES E Corsbsied tirak Ves sez DOO S Alecotved oomini acct TE E Hotherboad Unisa device Figure 45 DIMEtalk Device Editor 4 Double click on the clocks 0 component to bring up the Constraint Editor Figure 46 which shows five signals coming from the component to external pins Four
41. e records and the goods themselves upon request In the event of failure by the customer to pay any part of the price of the goods in addition to any other remedies available to Nallatech under these terms and conditions or otherwise Nallatech shall be entitled to repossess the goods The customer will assist and allow Nallatech to repossess the goods as aforesaid and for this purpose admit or procure the admission of Nallatech or its employees and agents to the premises in which the goods are situated INTELLECTUAL PROPERTY The buyer agrees to preserve the Intellectual Property Rights IPR of the company at all times and that no contract for supply of goods involves loss of IPR by the company unless expressly offered as part of the contract by the company GOVERNING LAW This agreement and performance of both parties shall be governed by Scottish law INTI07 0305 Issue 3 November 24 2006 INTI07 0305 Issue 3 November 24 2006 Any disputes under any contract entered into by the company shall be settled in a court if the company s choice operating under Scottish law and the buyer agrees to attend any such proceedings No action can be brought arising out of any contract more than 2 months after the completion of the contract INDEMNITY The buyer shall indemnify the company against all claims made against the company by a third party in respect of the goods supplied by the company SEVERABILITY If any part of these ter
42. e right click menu www nallatech com NT 107 0305 Issue 3 November 24 2006 DIMEtalk 3 1 User Guide 3 In the dialog box shown in Figure 30 select the device required for the design Click OK on the relevant motherboard or module which displays a build option menu showing the FPGA speed grades and package types available for the hardware Select a device for the network BenERA BenMLEYT 48 BenMLIEY 48 BenMLUE PC BenhLIE r motherboard v2pro p20 v2pra 50 Motherboard Cancel Figure 30 Assign Components 4 The device should now appear in the design tool as a green box which can be dragged over the components in the network as shown in Building a DIMEtalk Network This places all the components into that device 3 3 3 Using the Device Editor The Device Editor allows a user to map the nets in a design onto physical pins by dragging the unassigned nets onto the appropriate pins The list of nets comes from the connections that were wired to the top level in the design The Device Editor is accessed by right clicking on a device and selecting Edit from the menu Assigning Signals The principle function of the Device Editor is to assign signals to pins this is done using the Constraint Editor function within the Device Editor The following example shows how to assign LED signals to the pins of a block RAM node Firstly the user should select the block RAM node right click on the
43. e saved Click on the disk button right in the toolbar menu and save the network to an appropriate location as shown in Figure 16 ii DIME Dega ase stenet 3 9 Edges Banie piemal FPGA nodes ZET Nodes Briger outers Sytem SORAM DIMEC Legacy Beck AH Kodea Save EE das ia irm f uka 1 0 2 Hor V Sava 3 Fages I Cave pci D hauler U Figure 16 Save Network 16 www nallatech com NT107 0305 Issue 3 November 24 2006 DIMEtalk 3 1 User Guide 12 The final stage is to compile the VHDL for the network First press the Generate VHDL _ _ button right then click on Save in the dialog box to create all the appropriate VHDL files as shown in Figure 17 DME Rabe Systima asian C udimatadkldr desig n Urn jacte i pioblatwarrk aden rsatwork 11 Dee e Let FAG Eger Blai iniemal FPGA nodes ZET Moder Bridges Sim SDRAM DiHE Legacy Beck RAM Hodes Chasan top level direrclary Tar nebwerk iaa Arka 1 aloski 0 pe host intesa D Ande rondes CI Figure 17 Compilation Button 13 A list of all the files created appears In order to build the network simply click on Build to start the build process this calls the Xilinx ISE tools Lac Syst C udimatadkldr desk nU rn acte VE scarpe ss im pef Pee rum pla nus e r
44. elect the Generate Network code button right or choose Generation gt Generate Network Code from the drop down menu This prompts the user to selecta amp top level directory where the network will be stored A list of all the files created then appears as shown in Figure 41 which contains a Tcl file to build the application Double click on this or click Build to start the build process yaa F n V PR amp se j B a Eigen ariz eternal modes TET Moder Bridger Pipas Sytem SDRAM Legacy BEiyek AM Hodes bees oni busted TCL Sent Lis feet petra TCL Sera Thra od reve TEL bordada run ascecubu Chee AME ta Project fle ot use rath Dev C List of pounce and core fier bo beak Top Ussa TOL commands for och WHOL cade lor Tog 1 FE f peopel hie fle teeing D brote Pipette carr B enuE _ rrt ah utc n Pc E cries arb tak ounce HIE D VHDL Gram ra irre utc tn FP pt EE cipe ar t cours Dd TOL Seed no buld Biens IE Y reset di ttg Prog Vm pad Lave mban ase PIE Dhabi Lih of exce asd oaia Het L bald Ian LR 0 dededian Praec SE pate ounce M en UE Y bald Dude epsens lor Denis Dy 0 Figure 41 Tcl File to Build Application 36 www nallatech co
45. ent Interconnect SRAM Static Random Access Memory TCP IP Transmission Control Protocol Internet Protocol UCF User Constraints File USB Universal Serial Bus VHDL VHSIC Hardware Description Language Typographical Conventions The following typographical conventions are used in this manual Red text indicates a cross reference to information within the document set you are currently reading Click the red text to go to the referenced item To return to the original page right click anywhere on the current page and select Go To Previous View Blue underlined text indicates a link to a Web page Click blue underlined text to browse the specified Web site Italics denotes the following items References to other documents See the FUSE System Software User Guide for more information Emphasis in text Enable Loopback should not be enabled until all other registers have been set up xii www nallatech com INTI07 0305 Issue 3 November 24 2006 DIMEtalk 3 1 User Guide FUSE Naming Conventions Please note that the DIMEtalk clocks are named differently in the FUSE System Software compared to this User Guide The clock naming conventions are shown in Table l Clock Names in FUSE Clock Names in Documentation System Clock SYSCLK Clock CLK DSP Clock DSPCLK Clock B CLK B Pixel Clock PIXCLK Clock C CLK C Table 1 FUSE Naming Conventions Comments and Suggestions At the ba
46. erms and Conditions This bage intentionally blank 52 www nallatech com NT107 0305 Issue 3 November 24 2006 INTI07 0305 Issue 3 November 24 2006 igh Performance FPGA Solutions Company A aDBEOVIACIODS uen nates rore tuto ciii iota etre xii add components to network 27 add notes to network 34 add signal breakouts 33 B building a new network 10 building and managing DIMEtalk networks 6 C code generation 36 create network using Xilinx Project Navigator tool 38 files created during VHDL generation 37 generating VHDL files 36 component overview 27 3 7 27 COS E 27 lG 27 S 27 t st COImpO ents 27 testbench components 27 user components 27 Utility components 27 gt IST
47. estrictions This software contains trade secrets in its human perceivable form and to protect them except as permitted by applicable law you may not reverse engineer disassemble or otherwise reduce the software to any human perceivable form You may not modify translate rent lease loan or create derivative works based upon the software or part thereof with out a specific run time licence from Nallatech Ltd 3 Copyright The Licensed Materials are Copyrighted Accordingly you may either make one copy of the Licensed Materials for backup and or archival purposes or copy the Licensed Materials to another medium and DIMEtalk 3 1 User Guide keep the original Licensed Materials for backup and or archival purposes Additionally if the package contains multiple versions of the Licensed Materials then you may only use the Licensed Materials in one version on a single computer In no event may you use two copies of the Licensed Materials at the same time 4 Warranty Nallatech Ltd warrants the media to be free from defects in material and workmanship and that the software will substantially conform to the related documentation for a period of ninety 90 days after the date of your purchase Nallatech Ltd does not war rant that the Licensed Materials will be free from error or will meet your specific requirements 5 Limitations Nallatech Ltd makes no warranty or condition either expressed or implied including but not limited
48. ieeeeeeeeeeeeeeeeeeeeeeeeeeeeeeteenen 3 DIMEtalk Key Features NR 3 eec M 3 How DIMEtalk Works Within a Nallatech FPGA Computing System 4 PIME CANS COLIN OSIM ten ERT 4 Building and Managing DIMEtalk Networks 6 Getting Started 9 list o 9 Host System Requirements 9 Building a DIMEtalk Network 10 Part I DIMEtalk Implementation 19 Using DIMEtalk anasu 2 DIMEtalk System Design Designing a DIMEtalk Network 22 Q7 22 Starting DIMEtalk System Design 22 Toolbars Tabsand Monus NOn SM PPP 23 DIMEtalk System Design Tocol 26 DIMEtalk Component Library Manager 26 COMPONEN uuu u e uuu 27 What are Componehts 27 Addine Compost Ss 27 Connecting Components
49. ies Nothing contained in these terms shall be construed as conferring by implication estoppel or otherwise any licence or right to use any trademark patent design right or copyright of Nallatech Limited or any other third party Microsoft and Windows are either registered trade marks or trade marks of Microsoft Corporation in the United States and or other countries Disclaimer This document is for general information purposes only and is not tailored for any specific situations or circumstances Although Nallatech Limited believes the contents to be true and accurate as at the date of writing Nallatech Limited makes no assurances or warranty regarding the accuracy currency or applicability of any contents in relation to specific situations and particular circumstances As such the content should not be relied upon and readers should not act on this information without further consultation with Nallatech Limited Nallatech Limited accepts no responsibility for loss which may arise as a result of relying on the information in this document alone Copyright 1993 2006 Nallatech Limited All Rights Reserved NT 107 0305 Issue 3 November 24 2006 www nallatech com iii This bage intentionally blank www nallatech com 107 0305 Issue 3 November 24 2006 Contents About this User Guide x Part l Introduction e DIME talk Overview i
50. k 3 1 User Guide This bage intentionally blank INTI07 0305 Issue 3 November 24 2006 www nallatech com 7 DIMEtalk Overview This bage intentionally blank 8 www nallatech com NT107 0305 Issue 3 November 24 2006 DIMEtalk 3 1 User Guide Section 2 Getting Started In this section 2 1 2 1 1 Installation Building a DIMEtalk Network Installation Host System Requirements The following minimum system requirements are recommended for the DIMEtalk host PC Pentium 111 800 MHz or equivalent 128MB RAM 200MB Hard Disk Windows 2000 XP operating system 024 x 768 pixels screen resolution 16 bit color Display setting 96dpi Xilinx ISE 7 1 service pack 4 Foundation tools for bitstream generation FUSE for Windows v2 18 2 Macromedia Flash Player for interactive tutorials Web Browser Administrator privileges on the system System language set to English DIMEtalk may also operate under Linux using the WINE application interface layer Please note however that this option is not supported by Nallatech To install DIMEtalk on Windows 2000 XP use the following procedures Insert the supplied DIMEtalk installation CD into the system s CD ROM drive and wait for the CD to autorun lf autorun does not start click Start gt Run from the taskbar and run the following program For the HIOI series components ISE 8 2 or above is the only supported ISE release INTI07 0305 Issue 3 November
51. l accrue on a daily basis TECHNICAL SUPPORT The company offers a dedicated technical support via telephone and an E mail address It will also accept faxed support queries Technical support will be given free of charge for 90 days from the date of invoice for queries regarding the use of the products in the system configuration for which they were sold Features not documented in the user manual or a written offer of the company will not be supported Interfacing with other products other than those that are pre approved by the company as compatible will not be supported If the development tools and system hardware is demonstrably working no support can be given with application level problems WARRANTY The company offers as part of a purchase contract 12 months warranty against parts and defective workmanship of hardware elements of a system The basis of this warranty is that the fault be discussed with the companies technical support staff before any return is made If it is agreed that a return for repair is necessary then the faulty item and any other component of the system as requested by those staff shall be returned carriage paid to the company Insurance terms as discussed in the INSURANCE Section will apply Returned goods will not be accepted by the company unless this has been expressly authorized After warranty repair goods will be returned to the buyer carriage paid by the company using their preferred method
52. les Tab The Support Files tab shows all the files that are required for any design using this component These include the firmware parts of the component additional software and documentation Double click on any file to open it using the default filetype handler on the development machine Parameters Tab This tab contains the generics defined by the component Some of these are editable for example the size of new FIFO components can be set here Component Constraints Tab This tab shows the various constraints which are placed on a component Instance Constraints Tab This tab shows the constraints which are placed on a particular instance of a component Note that any values the user enters for the instance constraints override the component constraints 3 3 DIMEtalk Devices 3 3 1 What are Devices Devices represent the physical hardware deployed within a DIMEtalk network and are linked together by components This hardware includes BenONE BenONE PCI 104 BenERA BenNUEY PCI BenNUEY PCI 104 BenNUEY 4E BenNUEY PCI X and BenNUEY VME motherboards BenADDA BenBLUE ll BenBLUE Ill BenBLUE V4 BenDATA ll BenDATA V4 BenDATA DD BenDATA WS BenHOTLINK and BenPRO modules XtremeDSP Development Kit 3 3 2 Assigning Components to a Device v To assign a component to a device use the following procedures l Right click on a component or in the design space to open the menu 2 Select Create Device from th
53. lk 3 1 User Guide Generic Description DIMEtalk System Design Symbol Symbol Routers direct data around the network and interconnect all other component types within a physical device Bridges move data between physical devices across a defined physical media i e between FPGAs Nodes are the user interface to the network and can be connected to User FPGA designs via node interfaces Block RAM SRAM DDR SDRAM JT 4 I ZBT FIFO Memory Map re Tee DATA 4 D A i gn P Edges interface the network to from another data transfer standard such as PCI PCI X VME Ethernet or USB on Nallatech cards Table 2 DIMEtalk Components Figure 2 shows how these components can be used in an example multiple FPGA network on Nallatech hardware BenNUEY motherboard BenDATA and BenADDA modules The role of each network component is explained below l The Edge component allows the network to interface with the PCI FPGA 2 The Router receives data from its edge component Routers pass data around the network and connect all the component types within the device 3 The Router passes data to Nodes which are the user interface to the network INTI07 0305 Issue 3 November 24 2006 www nallatech com 5 DIMEtalk Overview 4 Bridges move the data between devices Figure 2 Example Multiple FPGA Network 1 1 4 Building and Managing DIMEtalk Networks Once the components which comprise a DIMEtalk netw
54. ll components are then placed into the subsystem Adding Notes An additional function in the DIMEtalk System Design tool is the ability to add notes to a network These can serve a variety of purposes for example users designing large complex networks can deploy them as reference points in the network or reminders to complete a task at a certain point in the network v To add a note to a network use the following procedures Right click on a component Select Create gt Note from the menu which appears In the box shown in Figure 37 enter the name for the note and click on OK Text to display This is a DIMEtalk note Figure 37 Add a Note The note can now be seen in the DIMEtalk System Design tool shown in Figure 38 gc PCI Host j DIMEtalk edge 0 LAE pci host_interface_O This is a DIMEtalk nate Figure 38 Note added in DIMEtalk System Design www nallatech com INTI07 0305 Issue 3 November 24 2006 DIMEtalk 3 1 User Guide 3 4 5 Using Clocks within DIMEtalk In the System tab when a user clicks on the Clock Driver Module shown right a module is created in A DIMEtalk to handle the clocking of the other components within the module Figure 39 shows how this ae component looks externally d clk clk1_ zx clk Trav ekz clkz 2H elzraw clk zx cl raw src clk1 src ckz src clk3 reset n reset resek am lock Figure 39 Clock Driver Module Component E
55. m INTI07 0305 Issue 3 November 24 2006 DIMEtalk 3 1 User Guide gt Dee S e 8 Edges Bare miena FPGA noces SET Nodes Bridger Aoten niem SDBAM DIHET Legacy INTI07 0305 Issue 3 November 24 2006 stepping bevel for this device im i level is available ar supporr wilinw com Opened eaonskraings file EcsNWIUEY D pcf Tue Jep i 20 16 200S Warning Running detected D errors mns D weenie Creating bit map Crore 0 faving bir stress im heanuey Db Bitstream generation i3 complete BLITGEN fim F O EOmnpletfe Tis Ch Kum Give Compan A dirional informariogn on m tepping Pirai TEL dirabi vele anpli Warnines 753 Cu Figure 42 Warnings Errors 3 5 2 Files Created during VHDL Generation Following VHDL Generation a number of files are created which have different functions within the DIMEtalk network These files are highlighted in Figure 43 which shows how they appear in the software The files created are also listed with their functions in Table 4 VHDL Generation Generated Files Generation Log C dimetalkdtdesign Prajects E samples Simple Networ C dimetalk dtdesign PrajectssE samples Simple C dimetalk sdtdesign sPrajectssE amp amples sS imple M etwark sE sampleC example c C dimetalk dtdesign Pr
56. ment in HTML INTI07 0305 Issue 3 November 24 2006 www nallatech com 25 Using DIMEtalk 3 1 4 DIMEtalk System Design Figure 24 shows the DIMEtalk System Design tool which displays the various components used to construct a DIMEtalk network These include a block RAM node a router a PCI edge and a Clock amp Reset component which are wired together to form a basic DIMEtalk network Also highlighted are the tree view and navigation windows which provide alternative views of the created network Clock amp Reset Component Device BlockRAM Node Navigation Window Tree View Systems Design Fm ER Yew Lee Generation Help Bere HR ue E Edoet asic intemal FPGA nades Hodes Bridges System Legacy Block Y UH UN 0 PerAMUCy PCI amp Three Ska DIEI blockiam 1024 0 Adar Dur WW non bici locks U 1 feu per hoii Add D iia LI Toner p 7 Chek S nint 5 Corine D CPP pei hest inerta Router PCI Host Interface Edge Figure 24 DIMEtalk System Design Workspace 3 1 5 DIMEtalk Component Library Manager The Library Manager enables the user to customize the layout and appearance of the DIMEtalk design window To open the Library Manager shown in Figure 25 click on the Library Manager button right in 6 the toolbar or select View Library Manager from the menu brary kita libra
57. mponent Editor window shown in Figure 56 provides some basic information about the component such as a full description short description and the type of component Note that it is not possible to edit the identifier as this has to be unique within DIMEtalk Component Editor block ram dtc General Signals Support Files Parameters Component Constraints Identifier Block ram Full Description BlockRamNode Am K Short Description BlockRamNode Type DIMEtalk Compatible Node Icon Color File Location C dimetalk dtdesign Components BlockRAM Nodes AINbloc Cancel i Figure 56 Component Editor The Signals tab shows the external interface to the component This tab can be used to alter the default connection for signals and resets For example right click on user_clk connected to CLKA and choose Set Group Type gt Clock gt CLKB from the menus as shown in Figure 57 This connects the DIMEtalk signal to Clock B Component Editor block_ram dtc General Signals Support Files Parameters Component Constraints data in in std logic vector 31 downto 0 data out out std logic vector 31 downto 0 data in ack out std logic data out ack in std logic user connected to Cla user clk in std logic Make group physical wires B Userlnterface Add Signal Group user addr instd loc Delete Signal Group user en in std logic Besse User Signals user we in std logic
58. ms and conditions is found to be illegal void or unenforceable for any reason then such clause or Section shall be severable from the remaining clauses and Sections of these terms and conditions which shall remain in force NOTICES Any notice to be given hereunder shall be in writing and shall be deemed to have been duly given if sent or delivered to the party concerned at its address specified on the invoice or such other addresses as that party may from time to time notify in writing and shall be deemed to have been served if sent by post 48 hours after posting SOFTWARE LICENSING AGREEMENT Nallatech Ltd software is licensed for use by end users under the following conditions By installing the software you agree to be bound by the terms of this license If you do not agree with the terms of this license do not install the Software and promptly return it to the place where you obtained it l License Nallatech Ltd grants you a licence to use the software programs and documentation in this pack age Licensed materials If you have a single license on only one computer at a time or by only one user at a time if you have acquired multiple licenses the Software may be used on either stand alone computers or on com puter networks by a number of simultaneous users equal to or less than the number of licenses that you have acquired and if you maintain the confidentiality of the Software and documentation at all times 2 R
59. n UE Ubud Duki oponi lor 0 Figure 49 Constraints File created for BenNUEY 0 10 This opens User Constraints File shown in Figure 50 which now displays the lock signal constrained to the physical pin E3 DIME habe Syanie asian C i lmatana dt design Utrnjactr V xarmples i13 pri U host AJ bet pe hast interface 0 host dataciks LocwkclT pci interface D host dabacz Locskcl pci hosr interface D host daracz7 LOCeABMII pei hast interface D host LOCSAL11 nci hast incr Deuce D heat datacczn Labia pei interface D hast dabaedUs LOCRALT7 pci hosr interface D host darac31 LOCMATIT pri host interface 0 hest datai OFFSET IN Sns BEFODE clecks D see phi hast inter face D host dated OFFSET OUT 12 569 AFTER arc c pci interface D hast LOC E116 pci _ hosr busy OFFSET IN Sns DEFORE clocks D sec EI pei hose inverface Q host empty LOCPAMI pci hast inter facr D host empty OFFSET IM Jna BEFORE clock 0 src cINZ I pci hast interface D heat ru Lene kml 3 pri hosc inrerface hnsr rw our OFFSET OUT iins fh clocks D src 1 pei bose interface D hese amis LOC AJ19 pci hast interfacr E heat asia OFFSET IN na BEFORE O cike pci bose interface D hist ruan aur Loc
60. nnection This option appears on the right click Create submenu if the terminal contains only output signals Unlike the signal breakout which gives one terminal per signal all the terminals on a bus have the same signals as the initial terminal Bus connections provide a way of connecting one terminal to multiple locations v To create a bus connection use the following procedures l Right click on a components terminal 2 Select Create Bus from the menu which appears 3 The bus is now placed down in the DIMEtalk System Design tool as shown by the red arrow in Figure 35 gt E PCI X Clocks a Reset Figure 35 Creating a Bus Connection 3 4 3 Creating Subsystems When using the software it may be necessary to create larger more complex networks The Create Subsystem option allows a user to compartmentalize a design and make it more manageable INTI07 0305 Issue 3 November 24 2006 www nallatech com 33 Using DIMEtalk 34 To create a subsystem use the following procedures Select one or more components Select Create gt Subsystem from the menu which appears The subsystem shown in Figure 36 is placed down in the tool and the component is now held within the subsystem rl Component Subsyste T Subsystem E Subsystem 0 4 3 4 4 Figure 36 Subsystem Alternatively a subsystem can be created by dragging a selection box over a number of components then right clicking on one A
61. of these three clocks and a reset are already assigned to appropriate physical pins whilst the locl signal is unassigned DIE Sayana Design design Urn ears ple Gi iim lame rers rh m Lormtnsim dilat clocks U signals to be rated bo pinu eran r iyide corri bank vul e ctir to kar the pins In and drag Eylem View EAE Devices oy chap signat HUEY 0 EK connected in Cha Device O phon mr ore in Rb uc ek esras bs eios rebel n h need Figure 46 Constraint Editor 5 Scroll down the list of available pins on the right hand side until the set of LEDs appears Drag the lock signal onto the led 1 pin as shown in Figure 47 INTI07 0305 Issue 3 November 24 2006 www nallatech com 4 DIMEtalk Tutorials dria fc Ded Pa signals ba be routed to specific pins Drag the selected signals onto the Prat pin teste Gorka bay eene ka Lor Dura cg hrs Thear cette any del oll Graoaframda select the pins bo ups and drag thesa onto the agal ka be routed onto hace pra r chip tigna SET cae nged i dis uc RI corria h gen bh rebel n Darahli h renal Figure 47 lock signal dragged to led l pin 6 This creates a non default constraint constraining the lock signal to a location known a
62. ogic vector 8 1 downto Value others gt D Editable Yes Pass to VHDL Yes mem awidth Description Address width 12 4096 words Type natural Value 12 Editable Yes Pass to VHDL Yes use sunplify Figure 59 Parameters Tab in Component Editor l The final tab shows Component Constraints in the case of the block RAM component there are none For an example of constraints go back to the Library Manager and open the Edges folder and double click on pci host interface as shown in Figure 60 Lampenani Library Manager E Comparat Libes Log amp Banc edema FETA nodes w bkxk ian E Lanian CBC ceo C1 E Died T XH 14 16 15 Bed fiu wan ia Ha loopback E Legacy Companants Figure 60 Edit constraints for pci host interface INTI07 0305 Issue 3 November 24 2006 www nallatech com 47 DIMEtalk Tutorials 12 This brings up the Component Editor again and Figure 61 shows the various signals constrained to the appropriate pins within a device These constraints also include timing constraints against global clock resources tempenent Editor pci host interface dtc Signals Support Fiss Component fhor di MET fait 1 LOL S SPCICONIAE T HET Punt dataczs LOCREPCIDUMMSI2E Figure 61 Component Constraints tab in Component
63. omponent Library Manager 26 Figure 25 Adda COMPONEN 27 Figure 2 Connect Componentrts 28 Figure 28 Component Manipulation 29 Figure 29 Component Editor 29 Figure 30 Assien COMPONENTS ul u unu 3l Figure 3l Assigning Signals to Pins eese esee u tn entente tenete 3l Figure 32 Open the Constraint Editor 32 Mgure 33 Dras Signals onto Ping au u l 32 Figure 34 Sis nal BreakOut u ans sunak bte etui Mn UII EE 33 35 Cresti e a Bus COMMS GEI ORE EE 33 ligure titm pt PU PUR 34 34 Figure 38 Note added in DIMEtalk System Desizgn 34 Figure 39 Clock Driver Module Component External
64. onality enables users to develop complex high performance FPGA Computing applications more easily reducing risk cost and shortening time to market Point to Point links across DIME II Interconnect Fabric Algorithm Algorithm Algorithm Algorithm Algorithm Algorithm Algorithm Algorithm DIMEtalk network fabric W C i Z FUSE firmware DIME II FPGA Computing Hardware FUSE FPGA Computing Runtime Software Figure 1 DIMEtalk in FPGA System 1 3 DIMEtalk Components Once a user is familiar with how DIMEtalk works within an FPGA system it is important to consider the components which make up a DIMEtalk network Data networks are a well established way of communicating data around systems yet many existing networking standards are overly cumbersome and overhead heavy for use in FPGA systems The simple network design and low overhead of DIMEtalk has been developed specifically for communications within FPGAs and between FPGAs in close proximity Interfaces to longer distance and backplane interfaces mean that DIMEtalk can be used in conjunction with these standards DIMEtalk networks are composed of four categories of underlying network components which the user can build together as required to form the network on an application specific basis The components are FPGA IP blocks available through the software tool DIMEtalk System Design and are shown in Table 2 4 www nallatech com INTI07 0305 Issue 3 November 24 2006 DIMEta
65. order The company reserves the right to vary the specification or withdraw from the offer any of its products without prior warning The company reserves the right to refuse to accept any contract that is deemed to be contrary to the companies policies in force at the time PRICING All prices shown on the company s price list or on quotations offered by them are based upon the acceptance of these conditions Any variation of these conditions requested by the buyer could result in changes in the offered pricing or refusal to supply All quoted pricing is in Pounds Sterling and is exclusive of Value Added Tax VAT and delivery In addition to the invoiced value the buyer is liable for all import duty as may be applicable in the buyer s location If there is any documentation required for import formalities whether or not for the purposes of duty assessment the buyer shall make this clear at the time of order Quotations are made by Nallatech upon the customer s request but there is no obligation for either party until Nallatech accepts the customer s order Nallatech reserves the right to increase the price of goods agreed to be sold in proportion to any increase of costs to Nallatech between the date of acceptance of the order and the date of delivery or where the increase is due to any act or default of the customer including the cancellation or rescheduling by the customer of part of any order DIMEtalk 3 1 User Guide
66. ork are understood the next stage is to start building a network using the software The DIMEtalk System Design tool allows a user to manage and configure the basic blocks to form complex and useful networks with little input required Network component type quantity and location are defined within each FPGA to meet the requirements of the end application This tool can be accessed through the windows start menu by selecting Start gt Programs gt Nallatech gt DIMEtalk Design Tools and DIMEtalk System Design which brings up the DIMEtalk System Design tool as shown in Figure 3 Full instructions on how to use the tool are provided later in this manual Hea 219 4 ag Edger Barrie temal FPGA nodes TET Nodes Bridger Pienter Eyetem SDRAM DIHET Legacy RAM Nodes Figure 3 DIMEtalk System Design Having defined the network user blocks of design VHDL or VHDL wrapped source can be imported and interconnected to the network in the DIMEtalk System Design tool FPGA I O ports for the whole design can be mapped to the device pins using the high level drag and drop Device Editor VHDL code and user constraints files for the network are then automatically generated by DIMEtalk System Design This code can then be added with additional user designs and code if necessary before being compiled using standard synthesis and implementation tools 6 www nallatech com NT 107 0305 Issue 3 November 24 2006 DIMEtal
67. process in the Xilinx ISE software The Standard Medium or High setting relates to how long an algorithm spends looking for a correct solution the higher the setting the longer the time spent look ing for a correct solution and the higher the possibility of finding one b The Router Effort option is passed through to the Place and Route process in the Xilinx ISE software The Standard Medium or High setting relates to how long an algorithm spends looking for a correct solution the higher the setting the longer the time spent look ing for a correct solution and the higher the possibility of finding one Document a DIMEtalk Network in HTML As mentioned in the previous table DIMEtalk System Design enables the user to generate an interactive HTML document that describes their system This shows all connections and components allowing the user to share design information with others For example the DIMEtalk network which was created earlier produces the HTML files which are created and stored by default on C Program Files Nallatech DIMEtalk projects Examples Simple Network Figure 23 shows these HTML files For an overall view of the network click on the file named Top html then click on the various network components as shown below to bring up the parameters connections and support files for each component in the network in this example the components include a block RAM node PCI Edge Router and Clock amp Reset Figure 23 Docu
68. programmable logic devices in the system and connected to each other and the wider system The tool provided for this process is DIMEtalk System Design which enables the user to specify the location and type of all nodes bridges routers and interfaces used in the system Once the network has been planned DIMEtalk System Design can be used to autogenerate all the required VHDL files to create the design 3 1 2 Starting DIMEtalk System Design DIMEtalk System Design requires minimal memory and disk resources and runs under all Microsoft 32 bit Windows versions DIMEtalk System Design can be started in two ways Double click on the DIMEtalk System Design desktop shortcut or Choose Start gt DIMEtalk Design Tools gt DIMEtalk System Design from the Windows start menu When the DIMEtalk System Design tool appears as shown in Figure 20 a previous design can be p s loaded using the Open File button left or by choosing File gt Open from the menu A new L xm network design can be created by clicking on the New Design button right or by selecting File gt New from the menu Systems esigi Fie Ede Wes Unites Gmer Help Dee S se a Esos Base niemal nodes ZRT Nodes Einiges Routers Spain Logacy BiockRAM Figure 20 DIMEtalk System Design Editor www nallatech com NT107 0305 Issue 3 November 24 2006 DIMEtalk 3 1 User Guide 3 1 3 Toolbars Tabs and Menus
69. rom the menu which appears as shown in Figure Dee Let FAT Edges Diiic mema FPGA nodar 7T Nodes Bridger Routers System SDRAM DIHET Legacy Beck RAM B fin fin IA iara Q uka 1 heat mesiaca 0 Ad 01 router CU Figure 11 Create a Device 7 In the device selection window shown in Figure 12 select the BenNUEY PCI motherboard and press OK DIME tale Syning asian Dega ae xOR a a Edger iniemal FPGA nodar ET Modes Bridger System SORAM DIHET Legacy Redes B fin fin D Xo Select a device for the nebeork Muluseh Methasani Halsiech Modues ina iremeDSP Kits Haliseck ReGen de Ge method vipera vee pila im i duki 1 Ba has D Ad D router 5 Figure 12 Device Selection 14 www nallatech com NT 107 0305 Issue 3 November 24 2006 DIMEtalk 3 1 User Guide 8 Choose the device option from the list of supported options to insert a device into the design window as shown in Figure 13 DIME tae Sylar Design Dega ae xm ue aa Edger intemal FPGA rder ET Moder Bridger ismi Saten SORAM DIHE Legacy EicckFUAM AERLE Selecta device for ihe naramrik Vipi eed OQ 11152 r Mies cz 000 1152 5 black irm Aika 1 C Mies iai 3000 1152 6 pei heat nsedace 01 C xc Pe iN 1152 4
70. ry Dok Compenenit Liban Log Ga intemal FPGA noder r Bleck Re Meeks Figure 25 DIMEtalk Component Library Manager www nallatech com NT 107 0305 Issue 3 November 24 2006 26 DIMEtalk 3 1 User Guide For an example of using the Library Manager please see Using the DIMEtalk Library Manager a tutorial 3 2 DIMEtalk Components This section provides an introduction to the components of DIMEtalk and how they can be used to create and manipulate networks For more detailed descriptions of the specific components please see the DIMEtalk Reference Guide 3 2 1 What are Components Components are the building blocks which are combined to make up a DIMEtalk network They consist of routers nodes bridges and edges Utility components are used to support the other components on hardware managing clocking grounding and resets Routers direct data around the network Nodes are the user interface to the network and can be connected to user application designs Bridges move data between physical devices across a defined physical media for example between FPGAs Edges are a special type of node that indicate data entering leaving the network from another data transfer standard such as PCI Ethernet USB on Nallatech systems Test components allow users to check that nodes are functioning properly These components consist of
71. s OUT ilna AFTER clocks src cli pei host inrerface D host imr pri baat inher hace heat f 1 pei host interface D h reserved nut 74 clocks Q lach cur LOGER eLacks sre ciki L B clacksa D are elki clocks 0 arc cik 10 11 miucks 0 src cikz PERIOD Zins clacka o sre elk LOC J168 elacka n0 are elk PEHTOD i1 0na clocks 0 reset n Locers Figure 50 UCF Showing Constrained Signal l When this network is built LEDI on the BenNUEY PCI motherboard will switch off as the active high lock signal is asserted on locking all of the clocks for the network 12 The signal has now been connected to a physical pin through DIMEtalk INTI07 0305 Issue 3 November 24 2006 www nallatech com 43 DIMEtalk Tutorials 4 2 Using the DIMEtalk Library Manager a tutorial This tutorial shows how to use the DIMEtalk Library Manager The Library Manager is the part of DIMEtalk System Design that allows users to decide which components are available in the component tabs for use within networks v To open the DIMEtalk Library Manager use the following procedures l In DIMEtalk System Design click on the Library Manager button in the toolbar as shown in Figure 51 DIME talk Systama Design file dk Ves Uter Generation elo 5G e Let a a 9 Edges Bane mema FPGA nodes JBT Node Bridger outers System SORAR DIHE Legacy Bak RAM Kades U Components Figure 51 Library Manager Button 2
72. s led l 7 Return to the Device Editor s main window and in the System View tab double click on Constrained Signals under the BenNUEY_0 node This opens the list of signals and displays the last entry as lock connected to led IT Click OK to return to DIMEtalk System Design DIME Stans Dann C Vlimatadstdt dein rn jacta UE amples simple Perm rhum p la na orm ri 81 3 xo es System View EdrDevices Log Dana pi hast connected o pote 35 pei ann ahis Foil Saa chaq Vs 17 pci Fact nierface hort connechsd to pocomma pei eet hal aca Fani connected Ip peiorem T3 Cx dir dk connected t cha ikki C uz ck connected h c kh clock 0 nc ck3 connected ckc mensi n coneected bo renes chaki Gunster Es lea t Lanier ard Interconneciaty Figure 48 lock connected to led I 8 In DIMEtalk System Design click on the Generate VHDL button then click on Save in the dialog box to create all the appropriate VHDL files 9 In Figure 49 the constraints file which has been created for the BenNUEY 0 is highlighted Double click on this to open it 42 www nallatech com NT 107 0305 Issue 3 November 24 2006 DIMEtalk 3 1 User Guide DIME Sper Daniam Urn jactr mampi simpleH n nere 8121
73. t so the user terminals are facing Creates a device in the opposite direction Create subsystem note VHDL Routes the wires in a Route Network component network Route Component wires Flip Ctrl F Export Attributes Routes a component s Saves a component as an wires attr file View a component s datasheet Figure 28 Component Manipulation 3 2 5 Using the Component Editor The component editor shown in Figure 29 gives complete details of the DIMEtalk component and allows a user to alter the clocks and resets It is accessed by right clicking on a component in DIMEtalk The component editor is split into five tabs which provide different information about the component Component Editar black ran General Signs Support Files Parameters Instance Constar CK liria Bock ram She Dscnplon Node Figure 29 Component Editor General Tab This tab shows details of the selected component and identifies it through a short and full description its type and its location NT 107 0305 Issue 3 November 24 2006 www nallatech com 29 Using DIMEtalk 30 Signals Tab The Signals tab shows the external interface to the component This tab can be used to alter the default connection for signals and resets For example right click on dt clk connected to CLKA and choose Set Group Type gt Clock gt Clock B from the menus Support Fi
74. talk creates a ise project file This enables the DIMEtalk network to be built using the Xilinx Project Navigator tool It is possible to create this file without invoking the full build process by using a DOS command prompt as described below Creating a Xilinx Project Navigator File v To create the ise file without invoking the full build process use the following procedures l In the task bar select Start gt Accessories gt Command Prompt gt 2 In the command prompt change directory into the top level directory where the network has been output and run the following command line cd source lt Device name gt 3 Followed by Lelsh build tel se 4 The ise project should now be created in the device folder on the user s hard disk 38 www nallatech com NT107 0305 Issue 3 November 24 2006 DIMEtalk 3 1 User Guide Section 4 DIMEtalk Tutorials In this section Connecting Signals to External Pins tutorial Using the Library Manager tutorial The tutorials described in this section are also available as interactive demonstrations which walk through each example and show the most appropriate methods for configuring and using DIMEtalk The tutorials are installed on a system s hard disk from the DIMEtalk installer to the location C Program Files Nallatech dimetalkdesigntools DIMEtalk help tutorials gt or from the menu in DIMEtalk System Design under Help gt Tutorials The tutorials require
75. to any implied warranties of merchantability and fitness for a particular purpose regarding the Licensed Materials Neither Nallatech Ltd nor any applicable Licenser will be liable for any incidental or consequential damages including but not limited to lost profits 6 Export Control The Software is subject to the export control laws of the United States and of the United Kingdom The Software may not be shipped transferred or re exported directly or indirectly into any country prohibited by the United States Export Administration Act 1969 as amended and the regula tions there under or be used for any purpose prohib ited by the Act USER GUIDE CONDITIONS Information in this User Guide is subject to change without notice Any changes will be included in future versions of this document Information within this manual may include technical typing or printing inaccuracies or errors and no liability will arise therefrom This User Guide is supplied without warranty or condition either expressed or implied including but not limited to any implied warranties of merchantability and fitness for a particular purpose regarding the information provided herein Under no circumstances will Nallatech Limited be liable for any incidental or consequential damage or expense of any kind including but not limited to loss of profits arising in connection with the use of the information provided herein www nallatech com 5 Standard T
76. xternal Figure 40 shows an internal view of the component reset_n resetraw clk1 Digital Clock clk1x2 Manager clk lraw clk2 src_clk2 x Digital Clock clk2x2 Manager clk2raw clk3 Digital Clock clk3x2 Manager clk3raw lock P reset Figure 40 Clock Driver Module Component Internal INTI07 0305 Issue 3 November 24 2006 www nallatech com 35 Using DIMEtalk There are no strict rules as to how the various clocks and resets can be used However by default DIMEtalk clock on all components is wired to be clkl 2 DIMEtalk network reset on all components is wired to reset 3 Host clock on relevant components e g PCI Edge is wired to clk2 4 User clock on all components is wired to clkl 5 is assumed to be 100MHz clk2 is assumed to be 40MHz clk3 is assumed to be OOMHz These default wirings can be altered by opening a component and changing the connection Note that DIMEtalk will not prevent potentially invalid connections e g half a DIMEtalk network on clk and half on clk2 In addition the three clocks must be constrained to appropriate pins in the module via the Device Editor The general assumption is that clk will be wired to CLKA clk2 to CLKB and clk3 to CLKC Again this is a suggested method which can be altered on the proviso that no checks are made as to the validity of any variation 3 5 Code Generation 3 5 1 Generating VHDL Files Once a network is created s
77. ystem 8 select All View menu view Library Manager refresh Library Manager alk Systems Design y ilities Generation Hi zoom in or out on the Navigator a Library Manager X Ckrl M panel E Refresh FS J OF Navigator Zoom d Utilities menu package a design into one folder which stores all the components stems Design and XML files for the design this create a new design open an existing design close a design saveadesign reopen a design list recently open files in submenu print the current view e document in HTML see Document a DIMEtalk Network in HTML on page 25 exit DIMEtalk Generation Help allows user to move projects from B Package Design one PC to another or archive them l for later use Table 3 DIMEtalk Menus www nallatech com INTI07 0305 Issue 3 November 24 2006 DIMEtalk 3 1 User Guide Description Allows user to Generation menu generate network code set Placer effort level DEUS set Router effort level eh Generate Network Code Placer Effort iE Router EfForE Help menu view Help contents view information about DIMEtalk view range of interactive tutorials E ET 2 Help Contents view Nallatech s website 77 About m Tutorials nallatech corn Table 3 DIMEtalk Menus a The Placer Effort option is passed through to the Place and Route

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