Video Platform User Manual - SiPS - INESC-ID
Contents
1. Veo 129 DG7 MSB 177 a ne a l o us DBO LSB L ve s ew 127 f voo Ne GND 2 NC 7e G23 108 DB 18s cos Lew 7 ex ws ew m c 26 NC 78 Ga 130 f DB2 1822 co 27 33 se e ef 137 DB7 MSB 86 c5 C07 L3 wc 87 O16 89 Vocaux 90 G13 39 42 ne 96 co 14 Nc LM C16 45 ne v cor e G30 98 voo Lx eno 4 GND 99 enp 15 GND 293 C2 50 car 12 co 200 GND 51 NC 10 DONE 155 Bm1 20 PROGB 52 co 208 TD GCLK input V2 0 Rev 1 1 5 25 2005 Jipf Page 8 of 8 inesc id2. timing diagram 5 Oscillator A 50MHz oscillator with a 3 3V maximum amplitude is used This HCMOS SMD device presents an accuracy of 50ppm The oscillator is connected to one GCLK FPGA pin P181 and is located close to the FPGA Oscillators for different frequencies can be employed by request Using the DCMs Digital Clock Managers available in the Startan 3 FPGA other frequencies can also be synthesized 6 Power Supply This board requires a power supply with an output voltage within the range of 5V to 6V DC The input voltage is monitored using a MAX4841 which provides overvoltage protection up to 28V If the unregulated input voltage is above 5 8V the MAX4841 disables a FET transistor isolating the remaining circuit The PWR Fail led indicates overvoltage condition The DC power socket must be connected to a 2 1mm female center positive plug and the supply must be capable of delivering at least 1A The board generates a total of four voltage levels 1 2V 2 5V 3 3V and 5V In order to save power all the supply voltages except the 5V are generated using a MAX1830 MAX1831 a low voltage PWM Pulse Width Modulation step down regulator which delivers a current of up to 3A with a peak efficiency of 94 Some of these voltages as well as the unregulated input are available through the expansion connectors To achieve a more efficient PDS Power Distribution System this board uses a four layer PCB with the inner layers dedicated to groun
3. 843 http sips inesc id pt videodevkit Document VPv20r11 01 Video Platform User Manual The board has been designed to be compatible with several expansion modules like the provided by Digilent The employed expansion connectors use standard 100mil spacing and can easily be found in common distributors These connectors make available I O pins one or more supply voltages and a reference ground signal Furthermore as currently CMOS sensors are capable of relatively good image quality the board was equipped with a connector capable of receiving several development camera modules from Omnivision Since the development modules can be equipped with different image sensors the voltage level applied to Camera Connector can be configured With this platform it is provided a simple VHDL description of an image capture module with the corresponding camera register configuration module Table 1 presents a summary of all the signals routed on the Video Board A more detailed description of these circuits can be found in the following sections Figure 2 presents a simplified layout of the components in the Video Board which has been implemented with a four layers the two internal corresponding to power ground planes 9 BINA BI
4. Lips inescid Oa PRELIMINARY Video Platform User Manual V2 0 Rev 1 1 5 25 2005 1 Overview This datasheet describes a compact configurable platform capable of real time video processing based on a board equipped with a FPGA The board has been designed to meet the high demanding characteristics of real time video processing This inexpensive and cost effective platform can be easily used and configured for different types of algorithms and applications It provides interfaces with a digital camera and with an output video peripheral for video display It is also equipped with a standard bus connector to allow debug or stream data input output or to attach expansion modules In fig 1 is presented the block diagram of the platform Processed Image Standard ge 6 Video DACs Monitor gt Q D 06 1 Data O D Q gt Packets 3 3 Debug Input z FPGA a eo Camera Image 9 Processing 8 3 Core Module 3 9 o a Configurable Platform Figure 1 Block diagram of the platform 2 Features The developed board presents the following main features e Xilinx Spartan3 XC3S400 FPGA as the processing core with o 400K system gates 288Kb of RAM in 16 blocks Sixteen 18 bit multipliers Fast carry look ahead logic JTAG configuration or through Serial PROM O O O O e Xilinx XCFO2S serial configuration flash PROM On
5. NS p T OIL Taw 8 j 8 bit 8 bit 8 bit Referee E pac l pac Il pac o e dli dii dl Good S od S e ercer smem E m BA JTAG pe g PROM M C XILINX nr SPARTAN 8 d XC3S400 3 2qB 8 m Oo J p E LED7 X amp luus i LED6 c B LEDS f 7 JE LEDA 1 2V de pac Power ae Am Lep4 Regulator E q im L 4 2 5V Power Power JP1 i Jack VTO 3 3V Power Regulator E n L Regulator J L N G9 at Figure 2 Simplified layout of the Video Board V2 0 Rev 1 1 5 25 2005 Power Supplies e Vcc Unregulated power supply voltage Veco 3 3V routed on a PCB plane employs a 3A PWM regulator I O supply voltage for the FPGA Vccaux 2 5V auxiliary supply required for the FPGA and for the camera expansion connector also uses a 3A PWM regulator e Vccint 1 2V core supply provides the supply voltage to the FPGA e Vcc 5V provides power to the DACs or for the Camera Connector maximum of 1 5A e GND System ground to all devices except the analog ground of the DACs Video Port e DRO DR7 Digital red data signal bus that connect to a DAC e DGO DG 7 Digital green data signal bus that connect to a DAC e DBO DB Digital blue data signal bus that connect to a DAC e CLK dac Clock signal for the DACs e HS Horizontal VGA synchronization e VS Vertical VGA synchronization e RGB Analog VGA color channe
6. at provides gt the analog output video signal if the TAG employed module provides this output Na Table 7 shows the FPGA pins for the Generic I O Connector expansion slot Q PROM 2 z XILINX g All the available I O signals from the FPGA G zt REA 2 3 25 37 S can be seen in fig 7 and the mapping of all 2 2 the pins is shown in table 10 x L J LEDs Control Z Z Switches Figure 7 FPGA available I O signals V2 0 Rev 1 1 5 25 2005 ipf Page 6 of 8 inesc id Video Platform User Manual Table 8 FPGA pins for camera connector Table 9 FPGA pins for the generic expansion expansion slot slot Number GND GCLK pin Configured through JP1 GCLK pin V2 0 Rev 1 1 5 25 2005 Jipf Page 7 of 8 inesc id Video Platform User Manual Table 10 Video Board FPGA pin assignment FPGA PIN Number FPGAPIN Number FPGAPIN Number FPGAPIN Number 2 co 5 GND 3 cz GND DR2 160 uev cau o oe 168 nc Lu pum e es ss forros 1er we 12 tps ea em me peotsp 19 Mc 5 ue s es 39 oe 39 nc 4 9 f e f enb f 1s f GND 1m f GND 15 171 Ne e uem ee Gar 120 oe i2 nc 17 Vecax 69 Vecaux 121 Vecaux 173 Vocaux 18 ED 70 Vcn 122 DG4 174 Voont 19 teo rt Ge 123 L 9 Ne z c 14 pee f me qm 21 NC 73
7. board FPGA boot e Two 100 mil spaced right angle DIP expansion connectors o Camera Connector 32 pin header providing 25 I O pins including two Global Clock inputs supports several camera modules from Omnivision o Generic I O Connector 40 pin socket providing 37 I O pins including four GCLK inputs supports several expansion modules provided by Diligent e VGA true color display port with three 20MHz conversion rate video DACs e On board user interface eight LEDs one 4 way slide switch two push buttons e 50MHz HCMOS 3 3V oscillator e Three 3A power regulators 1 2 V 2 5V and 3 3V and one 1 5A 5V power regulator 3 Platform Description The employed FPGA has sixteen embedded 18 bit multipliers fast carry look ahead logic and a total of 400K system gates This gives the developer enough resources to perform video processing The development can be performed by designing the circuits in VHDL using the free ISE WebPACK software tool from Xilinx To provide the interface with a standard VGA monitor this design employs three high speed video DACs capable of a conversion rate up to 30MHz These devices generate the red R green G blue B analog color signals require for the VGA interface Impedance adaptation is ensured using a triple video buffer Contact INESC I amp D Signal Processing Systems Group SiPS Rua Alves Redol 9 1000 029 Lisboa Portugal 351 21 3100378 351 21 3145
8. d and power Most of the power plane is at 3 3V but is divided into several islands one for each DAC and more two for the other supply voltages required for the FPGA The ground plane is also divided but in a more simple manner All the digital circuitry shares the same plane only the analog part of the DACs has a separate ground All the I O pin operate with 3 3V but some of the FPGA banks can be connected to other voltage levels by request V2 0 Rev 1 1 5 25 2005 lipf Page 4 of 8 inesc id Video Platform User Manual 7 FPGA Configuration The FPGA can be configured using a six pin JTAG header fig 5 shows the function of each pin in the connector The header can be connected to a standard JTAG programming cable Digilent JTAG3 the Vcc pin is connected to the 3 3V supply voltage It also employs the XCFO2S serial configuration flash PROM to store FPGA configuration data Using this design the FPGA can automatically boot from the on board PROM whenever the power is applied The configuration of the PROM is also done through the JTAG header RGB Control Switches T TDO r T T v Camera Connector Figure 5 JTAG connector pin order 8 On board User Interface The slide switches can be used to connect either Vcc or GND to the FPGA pins The slide switch in the OFF position pulls the FPGA pin to ground and in the ON will go high The output of the
9. f video DACs is lower than 20MHz The three analog voltage level generated by these DACs RGB together with the Horizontal Sync HS and the Vertical Sync HS are connected to a PCB mounted 15 pin sub HD socket standard VGA Figure 3 describes the mapping of these pins in socket and table 3 summarizes the function of each pin prs Table 3 VGA socket pin mapping FPGA PIN Number VGA e f n analog Red EE ee a a B E Hoot Sync s o 15 DDC Clock 1 Red Video 2 Green Video 3 Blue Video 4 No Connect 5 Ground Ground N C 10 Figure 3 VGA socket pin description V2 0 Rev 1 1 5 25 2005 ipf Page 3 of 8 inesc id Video Platform User Manual To implement this video out interface a VHDL module is provided with the board to generate the synchronization signals necessary for a standard VGA monitor The adopted configuration uses a resolution of 640 x 480 and a refresh rate of 60Hz The provided implementation uses a simple stage machine to generate the signals necessary to control the image display The image to be visualized can be stored into a frame memory block or be provided directly by the processing modules Figure 4 shows the temporal diagram of the VGA signals and Table 4 the necessary timings for the signals R G B KON wis um Table 4 VGA Timings idi Parameter wm aa KE 3 Sync front porch 320 us Figure 4 VGA
10. l moreover the camera also provides the pixel clock PCLK signal Figure 6 shows the temporal diagrams of those signals Tow v T disp Au P Tsw x Thine Tes 7 AN VSYN HREF AN Lo HREF PCLK Md Figure 6 Camera module sync signals The pixels information is updated every falling edge of the PCLK signal which means that pixel information can be read on the rising edge of PCLK the VHDL description of this module is provided 10 Expansion Connectors This board provides two expansion connectors both can provide supply power to an expansion module The pin arrangement is not equal for the two connectors As the Camera Connector must receive data from a digital camera the pin arrangement must be the same than for the camera module The power pins of this connector can be configured through JP1 to be 5V or 2 5V depending on the camera module Both connectors are close to the FPGA thus these connectors will exhibit a small signal delay and high data transfer rates Table 6 shows the pin mapping between the FPGA I O and the Camera Connector lt iis 8 bit DACs There is also a two pin header th
11. ls On board Devices e LEDO LED User controllable LEDs e BTNO BTN3 User controllable slide switch inputs BIN4 BTN5 User controllable push button inputs Power Fail Overvoltage condition LED Power Good Normal supply status LED CLK HCMOS oscillator connected to GCLK5 Expansion Connectors e C01 C32 Signals that connect the Camera Connector to the FPGA and to the power supplies e G04 G40 Signal bus that connects the FPGA to the Generic I O Connector e VTO Analog Video signal output Table 1 Video Board signal definitions Page 2 of 8 Video Platform User Manual 4 VGA Display Port The display port is based in three separate 8 bit DAC converters TLC5602C one per RGB channel This DAC presents low power consumption and a maximum conversion rate of 20MHz The signal conditioning for VGA port is performed using high speed video buffers with a 750 resistance in series with the output The voltage level required for powering the DAC is generated using a TPS78601 an ultra low noise low dropout linear regulator with a maximum output current of 1 5A The FPGA pin assignments for the tree converters are presented in table 2 the clock signal for the all DACs is provided by the FPGA pin 140 Table 2 FPGA pins for the video DACs Data Red Data Blue DRO LSB DGO LSB DBO LSB DR7 MSB DG7 MSB DB7 MSB Note when using this video port please ensure that the clock input o
12. push button is normally pulled to Vcco when pressed is pulled to ground No active debounce circuit was employed in either interface The board also provides 8 LEDs as output circuits and those LEDs are driven directly from the FPGA pins The LEDs are accessible through the pins presented in table 7 and are active high Table 6 FPGA pins for the slide switches Table 7 FPGA pins for the leds and the push buttons Function LEDO FPGA PIN Function PIN num 196 BINO AED 150 BINMM 149 BTN5 LEDS V2 0 Rev 1 1 5 25 2005 ipf Page 5 of 8 inesc id Video Platform User Manual 9 Image Capture The board is pin compatible several digital camera modules from Omnivision like the camera module based on the OV7620 CMOS image sensor or other modules with more recent sensors like the OV9650 All camera functions can be configured using a serial data transmission protocol SCCB which is a simplified version of the Philips I2C protocol A VHDL implementation of this protocol is supplied the desired register values are provided by a simple VHDL ROM like description Considering a camera module with the OV9650 sensor it can be programmed to capture frames in SXGA VGA QVGA and other specific formats or other programmed format Frame synchronization is performed by detecting a high pulse in the vertical sync VSYN signal and a new line occurs with a low pulse on the horizontal reference HREF signa
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