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TM87P18M 4-Bit Microcontroller with LCD Driver User Manual

1. BLOCK DIAGRAM 1 8 00 sEG1 3040 41 T M vDD3 B PORT A PORT C PORT D PORT LCD DRIVER ALARM RFC KEY IN FIXED SEGMENT PLA 34 1 4 BITS DATA BUS il it ir FREQUENCY INDEX ROM ALU DATA RAM GENERATOR 256 16 N X 8 BITS 512 X 4 BITS zx px p x ee RO 6 BITS PRESET p gt 8LEVELS INSTRUCTION PRE DIVIDER 1 82 STACK DECODER 1 e CONTROL 12815 PROGRAM ROM OSCILLATOR CIRCUIT PROGRAM Y 2048 128 X 16 BITS COUNTER CUP1 2 XIN OUT CFINOUT RESET INT N 0 gt 16 TM87P18M BLOCK DIAGRAM 9 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information PAD COORDINATE Name UM TM87P18M_E 4 Bit Microcontroller with LCD Driver Name BAK XIN XOUT CFIN CFOUT GND VDDI VDD2 VDD3 CUPI CUP2 COMI 2 COM3 COM4 B Z 16 N e N DC9 OD9 SEGI K1 SEG2 K2 SEG3 K3 SEG4 K4 SEGS K5 SEG6 K6 SEG7 K7 SEG8 K8 SEG9 K9 SEG10 K10 SEGI1 K11 SEG12 12 b2 NN OO OQ L COMS DCS5 OD5 COM6 DC6 OD6 COM7 DC7 OD7 8 8 8 SEG13 K13 SEG14 14 8 15 15 SEG16 16 SEGI7 DC17 OD17 SEG18 DC18 OD18 SEG19 DC19 OD19 S
2. 33 11 HEXADECIMAL CONVERT TO DECIMAL HCD 33 12 TIMER 1 TMR 34 12 1 NORMAL OPERATION 35 12 2 RELOAD OPERA HON MED TT N n 36 13 TIMER 2 TMR32 38 13 1 NORMAL OPERATION 38 13 2 RE LOAD OPERATION 39 13 3 TIMER 2 TMR2 IN RESISTOR TO FREQUENCY CONVERTER 40 14 STATUS REGISTER STS 42 14 1 STATUS REGISTER 1 S TS L 42 14 2 STATUS REGISTER 2 5152 43 14 3 STATUS REGISTER 3 STS3 44 14 4 STATUS REGISTER STS3 X nenei a a oneal excess 44 14 5 STATUS REGISTER 4 STS4 45 14 6 START CONDITION FLAG 11 SCF11 bea
3. Name Symb Condition For Min Typ Max Unit 1 2 Bias Display Mode Voh3f 1 uA 3 22 V TR WA e D 3 8 V Output L Velas WOl3E__ lol 1 uA a 0 2 V B Voldf 4 0 2 V m Voh3g 10 uA 43 22 V H Volge onde iUd M rii 3 8 V Vane 1 0 14 V m uA 3 Output M Voltage Vomde 1011 44 10 om 4g uA 4 COM n 22 Vol3g 01 10 uA 43 0 2 V Mb M lone 0 2 V 1 3 Bias display Mode Voh3i loh 1 3 3 4 V 5 8 V Voml3i Bor 1 0 14 V Output 1 Voltage 10113 710 Voml4i mis 1 8 2 2 uA JA Iol h24 10 BED Vom23i 9 1 29 2 6 V uA 3 Output M2 Voltage Tol h 10 Vom24i 4 3 8 42 V Vol i 01 1 3 0 2 V NOES INC d 0 2 V Wasi Voh3j loh 10 uA 3 3 4 V Output TU Voltage eed uA M 5 8 V Vou 1 0 14 uA 3 Output M1 Voltage lol h 10 Voml4j 1 8 2 2 uA JA Iol h24 10 SON VomQ3j 22 2 6 uA 3 Output M2 Voltage Tol h 10 Vom24j 4 3 8 42 V Vol3j 01 10 uA 43 0 2 V tput L lt LU Voltage 0 2 V 14 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information TYPICAL APPLICATION CIRCUIT 87 18 This application circuit is simply an example and is not guaranteed to work
4. old 16384 or 2048 clocks for internal reset cycle je toa Normal operation gt Internal reset cycle time is PH15 2 MASK OPTION table Mask Option name Selected item RESET TIME 1 15 2 In this option the reset cycle time will be extended 16384 clocks Internal reset cycle time is PH12 2 MASK OPTION table Mask Option name Selected item RESET TIME 2 PH12 2 In this option the reset cycle time will be extended 2048 clocks 2 1 POWER ON RESET TM87P18M provides a power on reset function If the power VDD is turned on or the power supply drops below 0 6V it will generate a power on reset signal Note It is recommended to connect a capacitor between VDD and GND in order to get the better performance of power on reset function 2 2 RESET PIN RESET When H level is applied to the reset pin a reset signal will be generated There is a built in pull down resistor on this pin There are two types of reset mode can be set for the RESET pin in mask option One is level reset and the other is pulse reset Preliminary tenx technology inc Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver It is recommended to connect a capacitor 0 1 uf between the RESET pin and the VDD This connection can prevent signal bounce on the RESET pin 2 2 1 Leve
5. 22 22 01 02111 0 222222 aa anata tha at om E 23 S n S eee 25 2 3 System COCK Generat u an Meu 26 PROGRAM COUNTER ccassoscassousssasesuseussuasescssesnvecees 26 PROGRAM TABLE MEMORY 27 4 1 INSTRUCTION ROM PROM 29 4 2 TABLE ROM TROM uuu uq aa u a u uama 29 5 INDEX ADDRESS REGISTER HL 30 3 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 6 STACK REGISTER STACNK 31 7 DATA MEMORY 32 8 WORKING REGISTER WR 32 9 ACCUMULATOR AC 33 10 ALD Arithmetic and Logic Unit
6. 4 2 REMOTE CONTROLLER APPLICATION If the buzzer output is combined with the timer and the frequency generator the output signals on the BZ pin may produce the waveform for the IR remote controller For the usage of remote controller the preset scaling data N of the frequency generator must be greater than or equal to 3 and the ALM instruction must be executed immediately after the FRQ related instructions in order to deliver the FREQ signal to the BZ pin Example SHE 1 Enable timer 1 halt release enable flag TMSX 3Fh Set initial value of Timer 1 to 3Fh and the clock source to PH9 SCC 40h Set the clock source of the frequency generator to BCLK FRQX 2 3 FREQ BCLK 4 2 preset scaling data of the frequency generator to 3 and duty cycle to 1 2 ALM 1COh FREQ signal is output This instruction must be executed after the FRQ related instructions HALT Waiting for the halt release Timer 1 underflows Halt released ALM 0 Stop the buzzer output 68 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 5 INPUT OUTPUT PORTS Four I O ports are available in TM87P18M IOA IOB IOC and IOD Each I O port has the same basic function and consists of 4 bits When the I O pins are defined as non IO functions in mask option the input output function of the pins will be disabled 5 1 OA PORT
7. 81 7 3 Enable 7 Disable the Counter by Timer 2 nana 83 7 4 Enable Disable the Counter by CX 84 8 Key Matrix Scanninsg 85 CHAPTER 4 LCD LED DRIVER OUTPUII A 90 1 LCD LIGHTING SYSTEM IN TM87P18M 90 2 OLOA DIAM ur 92 3 SEGMENT CIRCUIT FOR LCD DISPLA Y 93 3 1 PRINCIPLE OF OPERATION OF LCD DRIVER SECTION 93 3 2 Relative INITIATE 96 3 1 THE CONFIGURATION of LCD RAM Area a 97 4 LED DRIVER OUTPUT 98 Chapter 5 Detail Explanation of TM87P18M Instructions 104 1 INPUT OUTPUT INSTRUCTION S 104 5 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 2 ACCUMULATOR MANIPULATION INSTRUCTI
8. 87 18 4 Bit Microcontroller with LCD Driver The Resistor to Frequency Converter RFC converts a specified resistance to a corresponding frequency SRF 18h enable CNT CLKIN SRF 28h to data memory and FREQ output from frequency generator _ SRF 8h Controlled by Timer 2 SRF 18h SRF 28h CX pin signal interrupt request SCF9 16 bit counter 4 bit data bus counter over flow flag HRF6 This figure shows the block diagram of RFC Figure shows the block diagram of RFC RFC contains four external pins CX the oscillation Schmitt trigger input pin RR the reference resistor output pin RT the temperature sensor output pin RH the humidity sensor output pin this pin can also be used with another temperature sensor or left floating These CX RR RT and RH pins are MUXed with IOA1 SEG37 to IOAA SEGAO respectively and selected in mask option MASK OPTION table Mask Option name Selected item SEG2A IOA1 CX 3 CX SEG25 IOA2 RR 3 RR SEG26 IOA3 RT 3 RT 79 Preliminary tenx technology inc Rev 1 0 2012 10 05 Advance Information UM TM87P18M_E 4 Bit Microcontroller with LCD Driver SEG27 IOA4 RH 3 RH Preliminary 80 tenx technology inc Rev 1 0 2012 10 05 Advance Information 87 18 7 1 7 2 4 Bit Microco
9. Key Scanning latch circuit cw YS pu anb Key Scanning latch droit cona 5 m Key Scanning latch circuit Preliminary tenx technology inc Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 2 2 4 WATCHDOG RESET The watchdog timer is used to detect unexpected execution sequences caused by run away software The watchdog timer consists of a 9 bit binary counter The clock source of watchdog timer comes from the 10th stage output of the pre divider When the watchdog timer overflows it will generate a reset signal to reset TM87P18M Most of the functions in TM87P18M will be re initiated except for the watchdog timer itself which is still active the WDF flag will not be affected and PHO PH10 of the pre divider will not be reset The following figure shows the watchdog timer diagram Edge detector WDRST to reset TM87P18M POR Reset pin SF 10H Reset pin POR RF 10H During initial reset power on reset POR or reset pin reset the timer is inactive and the watchdog flag WDF is reset The Instruction SF 10h will enable the watchdog timer and set the watchdog flag WDF to 1 At the same time the content of the watchdog timer will be cleared Once the watchdog timer is enabled the watchdog timer
10. 55 1 1 RUPT REQUEST AND SERVICE ADDRESS u a 57 1 1 1 External Interr pt Factor 57 1 1 2 Internal Interrupt 37 PRIORITY E S uu Dun NU DEM SEE 58 1 3 INTERRUPT SERVICING 59 2 RESET FUNCTION mme 60 4 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 2 1 POWER RESE 60 2 2 RESET PIN dolo 60 2251 Level Reset 61 2 2 2 Pulse RESC RHET 61 2 2 3 IOC Por Rey Matrix RESET ose 62 2 2 4 WATCHDOG CHO RETE RYAN 63 3 OCK GENERA 64 3 1 RBOUENCY GENERATOR 64 3 2 Melody APPLICATION 65 3 3 Halver Doubl r EHpDIBE 66
11. 18 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 2 SYSTEM CLOCK XT clock slow clock oscillator and CF clock fast clock oscillator compose the clock oscillation circuitry and the block diagram is shown below Stop Halt Fast instruction Slow instruction Clock switch XT Clock circuit Clock switch CF Geek circuit Single clock option Dual clock option BCLK 1 2 T4 Sclk System clock generator Predivider The system clock generator provides the necessary clock signals for the execution of instructions The divider generates various clock signals of different frequencies for the LCD driver frequency generator etc The following table shows the clock sources of system clock generator and the pre divider under different conditions PHO BCLK Slow clock only option XT clock XT clock fast clock only option CF clock CF clock 2 1 CONNECTION DIAGRAM OF SLOW CLOCK OSCILLATOR XT CLOCK This oscillator provides the lower speed clock signals to the system clock generator the pre divider the timer the chattering prevention of the IO port and the LCD circuitry This oscillator is disabled when the fast clock only option is selected in mask option otherwise it is active all the time after the initial reset cycle In stop mode the oscillator will be stopped 15pf
12. 4 Bit Microcontroller with LCD Driver e LCD Panel 3 58MHz Ceramic COM1 8 SEG1 23 SEG40 41 15P H XN 9 9 32 768 2 2 Crystal A Pd cuP CUP2 SARS 7 VDD3 RR VPP CX VDD 2 1 O 1u 0 10 VDD1 L ale 0 1u TM87P18M BAK 0 tu 3 GND RESET External INT INT Port 10B IOC IOD Choke Buzzer SEG1 16 K1 K4 BZ BZB Key Scaning Key Matrix 1 3 Bias 1 8Duty Preliminary 15 tenx technology inc Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver Chapter 2 TM87P18M Internal System Architecture 1 Power Supply TM87P18M can operate at Li all of these operating types are defined by mask option The power supply circuitry is also generated by the necessary voltage level to drive the LCD panel with different bias Shown below are the connection diagrams for 1 2 bias 1 3 bias application LI BATTERY POWER SUPPLY Operating voltage range 2 4V 5 25V For different LCD bias application the connection diagrams are shown below 1 1 NO BIAS USING A Li BATTERY POWER SUPPLY Application circuit D 9 2 0 H i Z gt en x a x A AR 8 lt Z P B
13. Note When External R oscillator mode is operating the current consumption will depend on the frequency of oscillation 3 ALLOWABLE OPERATING CONDITIONS At Ta 40 C to 80 C GND 0V Name Symb Condition Min Max Unit VDD2 2 4 5 25 V Supply Voltage VDD3 2 4 8 0 V VPP 2 4 12 5 V Oscillator Start Up 32 768 KHz Crystal Mode 1 4 V Voltage ud 3 58 ceramic resonator Mode 1 8 V Oscillator Sustain VDD 32 768 KHz Crystal Mode 1 3 V Voltage 3 58 ceramic resonator Mode 1 55 Supply Voltage VDD2 Li Mode 24 3 6 V Input Voltage Vihl VDD2 0 7 VDD2 0 7 V Input L Voltage Vill pe Bane Mode 07 07 V Input Voltage Vih2 0 8 2 VDD2 Input L Voltage Vil2 AN 0 0 2 2 V Input Voltage Vih3 0 8x VDD2 VDD2 Input L Voltage Vil3 0 02xVDD2 V Fie Fopgl 32 768 KHz Crystal Mode 32 KHz perenne tied Fopg2 External R mode 10 1000 KHz Preliminary 12 tenx technology inc Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 4 ALLOWABLE OPERATING FREQUENCY At Ta 40 C to 80 C GND 0V Condition Max Operating Frequency BAK 3V 4 MHz 5 INTERNAL RC FREQUENCY RANGE Option Mode BAK Min Typ Max 250 KH
14. 5pf 32768Hz Crystal 1 19 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 2 2 4 Bit Microcontroller with LCD Driver When the backup flag is set to 1 the oscillator operates with a higher driving ability in order to reduce the start up time of the oscillator However it increases the power consumption Therefore the backup flag should be reset unless otherwise required The following table shows the power consumption of Crystal oscillator in different conditions Li power option 1 BCF 0 Initial reset After reset Normal CONNECTION DIAGRAM OF THE FAST CLOCK OSCILLATOR CF CLOCK The CF clock consists of 3 types of oscillators selectable in mask option which provide a faster clock source to the system In single clock operation fast only this oscillator provides the clock signals to the system clock generator pre divider timer I O port chattering prevention clock and the LCD circuitry In dual clock operation CF clock provides the clock signals to the system clock generator only When the dual clock option is selected in mask option this oscillator is inactive most of the time except when the FAST instruction is executed After the FAST instruction is executed the clock source BCLK of the system clock generator will be switched to CF clock but the clock source for other functions will still come in from the XT clock T
15. Multiplexer to select 1 2 duty 1 3 duty 1 4 duty 1 5 duty 1 6 duty 1 7 duty and 1 8 duty LCD driver circuitry Segment LRAM circuit connected between data decoder LO to L5 decoder and latch circuit 93 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver The data decoder is used for decoding the contents of the working registers as specified in LCD related instructions They are decoded as 7 segment patterns on the LCD panel The decoding table is shown below Content of Output of data decoder data memory Lg T Note The DBUSF of decoded output be selected as 0 1 by mask option The LCD pattern of this option is shown below DH HP DH F DH F mm T mm 2 DH x M lt gt lt gt H DBUSF 0 DBUSF 1 The following table shows the options table for displaying the digit 7 pattern MASK OPTION table Mask Option name Selected item F SEGMENT FOR DISPLAY 7 1 ON F SEGMENT FOR DISPLAY 7 2 OFF Both the LCT and LCB instructions use the data decoder table to decode the content of the specified data memory location When the content of the data memory location that is specified by the LCB instruction is 0 the output of DBUSA DBUSH
16. 15 TMS Rx 1110 0000 OXXX AC3 2 01 Ctm PH3 AC3 2 00 Ctm 9 AC1 0 PB3 0 Set Timer Value TD7 6 11 Ctm FREQ TD7 6 10 Ctm 15 TMS HL 1110 0001 0000 0000 TD7 6 01 Ctm PH3 TD7 6 00 Ctm PH9 TD5 0 Set Timer Value X8 7 6 111 Ctm PHI3 X8 7 6 110 Ctm PH11 X8 7 6 101 Ctm PH7 X8 7 6 100X8 Ctm PH5 TMSX 1110 001X 7 6 011 Ctm FREQ X8 7 6 010 Ctm 15 X8 7 6 001 Ctm PH3 X8 7 6 000 Ctm 9 X5 0 Set Timer Value TM2 Rx 11100100 0XXX Timer2 Rx amp AC TM2 HL 1110 0101 0000 0000 Timer2 lt T HL X8 7 6 111 Ctm PHI3 X8 7 6 110 Ctm X8 7 6 101 Ctm PH7 TM2X X 1110011IX XXXX XXXX 8 7 6 100 Ctm 5 X8 7 6 011 Ctm FREQ X8 7 6 010 Ctm 15 X8 7 6 001 Ctm PH3 138 tenx technology inc Rev 1 0 2012 10 05 Advance Information UM TM87P18M_E 4 Bit Microcontroller with LCD Driver Preliminary X8 7 6 000 Ctm PH9 X5 0 Set Timer2 Value X6 Enable HEF6 RFC 5 Enable 5 5 4 Enable HEF4 TMR2 SHE 1110 1000 Enable HEF3 PDV X2 Enable HEF2 INT XI Enable HEFI TMRI X6 Enable IEF6 RFC X5 Enable IEF5 KEY S X4 Enable IEF4 TMR2 SIE X 11101001 OXXX XXXX Enable IEF3 PDV X2 Enable IEF2 INT XI Enable IEFI TMRI Enable IEFO C DPT X8 Reset 15 11 PL
17. 4 1 SOUND EFFECT APPLICATION The buzzer output pins BZ BZB are suitable for driving the buzzer through a transistor with one output pin or driving the buzzer with both BZ and BZB pins directly It is capable of outputting a modulation waveform of any combination of the frequency generator s output signal PH3 1024 Hz PH4 2048 Hz 5 1024 Hz as the carrier and with the envelope waveform of any combination of the following frequencies 32 Hz PH10 16 Hz PH11 8 Hz PH12 4 Hz PH13 2 Hz PH14 1 Hz PH15 Execute the ALM instruction to specify the frequency combination for the output waveform Note 1 The higher frequency clock source should be only one of PH3 PH4 PH5 or FREQ and the lower frequency may be any all of the combinations from any all of PH10 15 2 The frequency in parentheses corresponding to the input clock of the pre divider PHO is 32768 Hz 3 The BZ and BZB pins will output DCO after the initial reset cycle Example Buzzer output generates a waveform with 1 KHz carrier and PH15 PH14 envelope LDS 20h OAh ALM 70h Output the waveform 67 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 E 4 Bit Microcontroller with LCD Driver In this example the BZ and BZB pins will generate the waveform as shown in the following figure le 1 P 1 FRE 1 7 2 7 e 7
18. gt gt gt ea o 87 18 MASK OPTION TABLE Mask Option name Selected item POWER SOURCE 2 BATTERY OR HIGHER BIAS 1 NO BIAS Note 1 The input output ports operate between GND and VDD2 16 tenx technology inc Rev 1 0 2012 10 05 Preliminary Advance Information 87 18 4 Bit Microcontroller with LCD Driver 1 2 1 2 BIAS USING A Li BATTERY POWER SUPPLY The backup flag BCF must be reset after the operation of the halver circuit is fully stabilized and a voltage of approximately 1 2 VDD2 appears on the VDD1 pin Backup BCF 0 BCF I CUP1 0 1u zz CUP2 VDD3 VDD2 34 sw2 VDD1 swi BAK 30v i 0 1u Internal logic GND MASK OPTION TABLE Mask Option name Selected item POWER SOURCE 2 BATTERY OR HIGHER BIAS 2 1 2 BIAS Note 1 The input output ports operate between GND and VDD2 Note 2 The backup flag is set to the initial cycle When the backup flag is set to 1 the internal logic signal operated on VDD2 and the driving power of the oscillator circuit increases and the operating current also increases Therefore unless it is required otherwise the backup flag must be reset to 0 after the initial cycle For the backup flag plea
19. in High active Su eMe GND LE VDD 5 in High active ET eee GND segnments on COM4 2 8 4 8 s cn VDD with unlighted sides GND segnments on COM1 with nny LT FED lighted sides _ LL J ac L Jj GND segnments on COM with 41 c L eo lighted sides x Jj L jJ Lo GND segnments on with Lf M EN LS lighted Sides Jj LJ GND segnments on 4 with j J C Lb e ES EE lighted sides 1 J GND segnments on COMB with Eb EMO lighted Sides LJ GND segnments on 1 2 with cea TEM lighted sides Y 0 L GND segnments on COM1 3 with J LJ LILI Ls 22 VED lighted sides ee GND segnments on COM1 4 with _ Lf LJ LILI baka VBD lighted sides SZ So GOCH L Jj OCA L j 2 GND segnments on COM1 5 with LO TS L lighted sides ge 22 GND segnments on COM2 3 with LO P L 22 22 VDD lighted sides GND segnments on COM2 4 with LILI LILI L 2 2 YD lighted sides CJA L jJ L J Y L GND segnments on 2 5 with uw LUIL 2 VDD lighted sides ee j 1L jJ L jJ L J L GND segnments on 4 with LP e TM lighted sides 1 1 2 1 L l f woe GND segnments 5 with LE LILT e 222 VDD lighted sides
20. lt STS3 SCFS TM1 B0 SCFA INT SCF9 RFC B2 unused MCX Rx 0100 1101 XXXX lt STS3X Bl SCF6 TM2 SCF8 SKI No use 2 FROVF MSD Rx 0100 1110 XXXX lt STS4 Bl WDE BO CSF ACn Rxn lt Rx n 1 SRO Rx 0101 0000 Rx3 n ACn Rxn lt Rx n 1 SRI Rx 0101 0001 OXXX XXXX AC3 Rx3 il ACn Rxn lt Rx n 1 SLO Rx 0101 00100XXX XXXX ACO RxO 4 0 ACn Rxn lt Rx n 1 511 0101 0011 ACO ei DAA 0101 0100 0000 0000 AC lt BCD AC CF DAA 01010101 OXXX lt BCD AC CF DAA HL 0101 0101 1000 0000 lt BCD AC lt BCD AC DAA HL 0101 0101 1100 0000 HL HLH CF DAS 0101 0110 0000 0000 AC lt BCD AC CF DAS Rx 01010111 OXXX XXXX lt BCD AC CF DAS HL 0101 0111 1000 0000 HL lt BCD AC CF lt BCD AC DAS 0101 0111 1100 0000 HL HLH CF LDS Rx D 0101 IDDD XXXX AC Rx D LDH Rx HL 011000000 XXXX lt H T HL LDH Rx HL 01100001 XXXX AC Rx lt 1 LDL 011000100XXX XXXX AC Rx lt L T HL LDL Rx HL 01100011 OXXX XXXX AC Rx Tent HL HL 1 MRFI Rx 01100100 OXXX XXXX lt RFC3 0 MRF2 Rx 01100101 XXXX lt RFC7 4 Rx 011001100XXX XXXX lt RFC11 8 137 tenx technology inc Rev 1 0
21. 1 Start Condition Flag 8 SCF8 SCFS is set to 1 when any one of KI1 4 1 0 4 1 in LED mode KI1 4 0 in LCD mode causes the halt release request flag 5 HRF5 to be output and the halt release enable flag 5 HEF5 is set beforehand To reset the Start Condition Flag 8 SCF8 the PLC instruction must be used to reset the halt release request flag 5 HRF5 or the SHE instruction must be used to reset the halt release enable flag 5 HEF5 Start Condition Flag 6 SCF6 SCF6 is set to 1 when an underflow signal from timer 2 TMR2 causes the halt release request flag 4 HRF4 to be output and the halt release enable flag 4 HEF4 is set beforehand To reset the Start Condition Flag 6 SCF6 the PLC instruction must be used to reset the halt release request flag 4 HRF4 or the SHE instruction must be used to reset the halt release enable flag 4 HEF4 Start Condition Flag 9 SCF9 SCF9 is set when a finish signal from mode 3 of RFC function causes the halt release request flag 6 HRF6 to be output and the halt release enable flag 9 HEF9 is set beforehand In this case the 16 counter of RFC function must be controlled by CX pin please refer to 2 16 9 To reset the Start Condition Flag 9 SCF9 the PLC instruction must be used to reset the halt release request flag 6 HRF6 or the SHE instruction must be used to reset the halt release enable flag 6 HEF6 The MCX instruction can be used to transfer the contents of status register
22. 117 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 EOR Rx Function Description EOR HL Function Description EOR HL Function Description EOR Rx Function Description EOR HL Function Description EOR HL Function Description OR Rx Function Description OR HL Function Description OR HL Function Description 4 Bit Microcontroller with LCD Driver lt Rx AC Exclusive Ors the contents of Rx and AC the result is loaded to AC HL AC Exclusive Ors the contents of HL and AC the result is loaded to AC HL indicates an index address of data memory AC lt HL AC HL HL 1 Exclusive Ors the contents of HL and AC the result is loaded to AC The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory lt AC Exclusive Ors the contents of Rx and AC the result is loaded to AC the data memory Rx AC HL lt HL Exclusive Ors the contents of HL and AC the result is loaded to AC and data memory HL HL indicates an index address of data memory lt HL 1 Exclusive Ors the contents of HL AC the result is loaded to AC and data memory HL The content of the index register HL will be incremented automatically after executi
23. 2 2 IOC2 IOC3 KD 2 IOC3 IOC4 KH 2 IOC4 The default setting of IOC port is input mode in the initial reset cycle each bit of the port can be defined as input mode or output mode respectively by executing a SPC instruction Executing an OPC instruction can output the content of specified data memory to the pins which has been defined as output mode Executing an IPC instruction can store the IO pins signals into the specified data memory When the IO pins are defined as output mode executing an IPC instruction will store the content that is stored in the output latch into the specified data memory Before changing the I O pins to output mode the OPC instruction must be executed first to output the data to those output latches It will prevent the chattering signal on the I O pin when changing the I O mode IOC port has a built in pull low resistor which can be selected in mask option and can be enabled disabled by executing a SPC instruction The IOC port can select the pull low device or low level hold device for each pin in mask option and can be enabled disabled by the software program When the pull low device and the low level hold device are both enabled in mask option a reset will enable the pull low device and disable the low level hold 73 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver device Executing the SPC 10h instr
24. 2012 10 05 Advance Information UM TM87P18M_E 4 Bit Microcontroller with LCD Driver Preliminary MRF4 Rx 01100111 XXXX RFCI5 12 STA Rx 011010000XXX XXXX Rx AC STA HL 0110 1000 1000 0000 HL lt AC HL AC STA HL 0110 1000 1100 0000 HL HLH LDA Rx 0110 1100 0XXX XXXX Rx LDA HL 0110 1100 1000 0000 AC HL AC HL LDA HL 0110 1100 1100 0000 HL HL 1 MRA Rx 011011010XXX CF lt Rx3 MRW HL Rx 011011100 AC HL Rx AC HL Rx MRW HL Rx 01101110 IXXX XXXX HL MWR Rx HL 01101111 OXXX XXXX lt HL MWR Rx GHL 01101111 XXXX AC Rx CHL HL HL 1 MRW Ry Rx 0111 OYYY YXXX XXXX Rx MWR Rx Ry 0111 YXXX XXXX lt Ry JBO X 1000 XXXX if ACO 1 JB1 1000 1 1 JB2 1001 if AC2 1 JB3 1001 if AC3 1 JNZ x 1010 XXXX if AC 0 JNC 1010 if CF 0 17 1011 XXXX XXXX 0 1 1011 IXXX XXXX XXXX if CF 1 CALL X 1100 PXXX STACK pres PC X JMP X 1101 PXXX XXXX XXXX X AC3 2 11 Ctm FREQ AC3 2 10 Ctm
25. 3 4 Alter atin e Frequency for EC D e rtv VPE Tbe hi oi PC e poe s E DM CC ERE 66 4 BUZZER OUTPUT PINS iicet eise o io VIE Hir Ie HN SUE ep Rte EHE 66 4 1 SOUND EFFECT APPLICATION 67 4 2 REMOTE CONTROLLER APPLICATION taro VERE ctv 68 5 INPUT OUTPUT PORTS 69 NP gu 69 5 1 1 Pseudo Serial iinis 70 5 2 LIN 61 72 PORT uuu A aioe oases 73 5 3 1 Chattering Prevention Function and Halt Release 75 5 4 TOD PL 76 5 4 1 Chattering Prevention Function and Halt 76 6 EXTERNAL INT PIN 78 7 Resistor to Frequency Converter RFO 79 Tel RC Oscillation Sty Oi dti embed E Rr 81 7 2 Brable Disable the Counter by Software
26. For slow clock oscillator only Mask Option name Selected item CLOCK SOURCE 2 SLOW ONLY The operation of the single clock option is shown in the following figure Either XT or CF clock may be selected by mask option in this mode The FAST and SLOW instructions will perform as the NOP instruction in this option 23 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information UM TM87P18M_E 4 Bit Microcontroller with LCD Driver The backup flag BCF will be set to 1 automatically before the program enters the stop mode This can ensure the Crystal oscillator will start up in a better condition Halt Normal mode Halt Halt mode OSC active released OSC active Stop Reset Reset release Stop Release Reset mode Power on reset OSC active Reset Reset pin reset Watchdog timer reset Key reset Stop mode OSC stop This figure shows the State Diagram of Single Clock Option Preliminary 24 tenx technology inc Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 2 4 PREDIVIDER The pre divider is a 15 stage counter that receives the clock signals from the output of the clock switch circuitry PHO as input When PHO changes from level to L level the content of this counter changes accordingly The PH11 to PHI5 of the pre divider are reset to 0 when the PLC 100H instruction
27. Reset mode WDF 0 XT clock slow speed clock in Clock source BCLK 2d m P Notes 1 PH3 the 3rd output of the predivider 2 PH10 the 10th output of predivider Resistor frequency converter RFC Inactive RR RT RH output 0 LCD driver output All lighted mask option 3 All the LCD segment pins can be set to output all ON or all OFF signals during reset cycle in mask option 61 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 2 2 3 IOC Port Key Matrix RESET UM TM87P18M_E 4 Bit Microcontroller with LCD Driver The key reset function can be selected in mask option When the IOC port or the key matrix scanning input KI1 4 is activated and the the 0 signal is applied to all the input pins a reset signal is delivered The key matrix scanning function will not deliver the reset signal until the scanning clock signal arrives MASK OPTION table IOC or KI pins are used as key reset Mask Option name Selected item IOCI KI1 FOR KEY RESET 1 USE IOC2 KD FOR KEY RESET 1 USE IOC3 KI3 FOR KEY RESET 1 USE IOCA KI4 FOR KEY RESET 1 USE IOC or KI pins are not used as key reset Mask Option name Selected item IOCI KI1 FOR KEY RESET 2 NO USE IOC2 KD FOR KEY RESET 2 NO USE IOC3 KI3 FOR KEY RESET 2 NO USE FOR KEY RESET 2 NO USE The following figure shows the key reset diagram b man
28. TABLE ROM D N 12 3584 1024 INSTRUCTION ROM lt gt TABLE ROM N 13 3712 768 INSTRUCTION ROM lt gt TABLE ROM F N 14 3840 512 INSTRUCTION ROM lt gt TABLE ROM N 15 3968 256 INSTRUCTION ROM lt gt TABLE ROM N 16 4096 0 28 tenx technology inc Preliminary Rev 1 0 2012 10 05 87 15 4 Bit Microcontroller with LCD Driver Advance Information 4 1 INSTRUCTION ROM PROM There are some special locations that serve as interrupt service routines such as reset address 000 interrupt 0 address 014H interrupt 1 address 018H interrupt 2 address 010H interrupt 3 address 01 interrupt 4 address 020H interrupt 5 address 024H and interrupt 6 address 028H in the program memory When the valid address range of PROM exceeds 2048 addresses 800h the memory space of PROM will automatically be defined as 2 pages Refer to section 2 3 This figure shows the Organization of ROM address 000h Initial reset 000H 010h Interrupt 2 014h Interrupt 0 018h Interrupt 1 zo 01Ch Interrupt 3 9 High Low 5 o Nibble Nibble 020h Interrupt 4 02411 Interrupt 5 028h Interrupt 6 XFFH 8 Bits X 15 N N 1 gt 15 N 0 16 lt 16 bits Instruction ROM PROM organization Table ROM TROM organization 4 2 TABLE ROM TROM The table ROM is organized into 256 16 N x 8 bi
29. by Lz through the data decoder Refer to Table 5 2 Lz 00 LCB Lz HL Function LCD latch Lz data decoder HL Description The contents of index RAM specified by HL are loaded to the LCD latch specified by Lz through the data decoder Refer to Table 5 2 If the content of HL is 0 the output of the data decoder will consist entirely of 0 Lz 00 1FH LCP Lz HL Function LCD latch Lz HL AC Description The content of index RAM specified by HL and the contents of AC are loaded to the LCD latch specified by Lz Refer to Table 5 2 Lz 00 SPA X Function Defines the input output mode of each pin for the IOA port and enables or disables the pull low device Description Sets the I O mode and turns the pull low device on or off The meaning of each bit of X X4 X3 X2 X1 X0 is shown below 4 1 Enable the pull low device on X4 0 Disable the pull low device on IOA1 IOA4 simultaneously IOA1 IOA4 simultaneously X3 1 IOA4 as output mode IOA4 as input mode IOA3 as output mode IOA3 as input mode IOA2 as output mode IOA2 as input mode IOA1 as output mode as input mode 105 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 OPA Rx Function Description OPAS Rx Function Description IPA Rx Function Description SPB Function Description 4 Bit Microcontroller with LCD Drive
30. lt Ry D ANDI Ry D 00111010 DDDD YYYY Ry ANDD ANDI RyD 0011 1011 DDDD YYYY Ry ANDD EORI RyD 00111100 DDDD YYYY Ry EORD EORI RyD 0011 1101 DDDD YYYY Ry EORD ORI RyD 00111110 DDDD YYYY lt Ry ORD ORI Ry D 0011 DDDD YYYY Ry ORD INC Rx 0100 0000 XXXX AC Rx lt 1 INC HL 0100 0000 1000 0000 AC HL lt HL 1 CF INC HL 0100 0000 1100 0000 AC HL HL 1 CF Preliminary 136 tenx technology inc Rev 1 0 2012 10 05 Advance Information UM TM87P18M_E 4 Bit Microcontroller with LCD Driver Preliminary HL lt HL 1 DEC Rx 0100 0001 lt Rx 1 CF DEC HL 0100 0001 1000 0000 HL lt HL 1 CF lt HL 1 4 DEC HL 0100 0001 1100 0000 HL HL 1 CF IPA Rx 0100 0010 XXXX lt Port A Rx 0100 0100 XXXX lt Port B IPC Rx 0100 0111 OXXX XXXX lt Port C IPD Rx 0100 1000 XXXX Port D CF MAF Rx 0100 1010 XXXX lt STSI ZERO No use No use B3 SCF3 DPT B2 SCF2 HRx MSB Rx 0100 1011 XXXX lt STS2 SCFI CPT B0 B3 SCF7 PDV 2 15 5 Rx 0100 1100 XXXX
31. 1 bit register 1 itch Enable Flag 4 SEF4 It stores the status of the input signal change on IOC pins which have been defined as input mode that causes the halt mode or the stop mode to be released 2 Switch Enable Flag 3 SEF3 It stores the status of the input signal change on IOD pins which have been defined as input mode that causes the halt mode or the stop mode to be released Executing the SCA instruction can set or reset these flags The following table shows Bit Pattern of Control Register 1 CTL 1 Bit4 Bit3 Switch Enable Flag 4 SEF4 Switch Enable Flag 3 SEF3 Enables the halt release caused by the signal change on Enables the halt release caused by the signal IOC port change on IOD port 47 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver The following figure shows the organization of control register 1 CTL1 Ed HALT IOC ge Released detector R SEF4 equest SCA 10h Interrupt 0 request Edge IOD detector SCF3 PLC 1 SCA 8h Interrupt accept 15 1 1 The Setting for Halt Mode If SEF4 SEF3 is set to 1 a signal change on the IOC IOD port will cause the halt mode to be released and SCF1 SCF3 will be set to 1 Because the signal change on the IOC IOD port is an ORed output of IOC1 4 it is necessary to keep the rest of input pins in 0 state when one of the input signal o
32. 3X STS3X to the accumulator AC and the data memory RAM The following table shows the Bit Pattern of Status Register 3X STS3X Bit 3 Bit 2 Bit 0 Start condition flag 9 NA Start condition flag 6 Start condition flag 8 SCF9 SCF6 SCF8 Halt release caused by NA Halt release caused by Halt release caused by RFC counter finish TMR2 underflow SKI underflow Read only Read only Read only Read only 14 5 STATUS REGISTER 4 STS4 The Status register 4 STS4 consists of 3 flags 1 The System Clock Selection Flag CSF The system Clock Selection Flag CSF shows which clock source of the system clock generator SCG is in use Executing the SLOW instruction will change the clock source BCLK of the system clock generator to the slow speed oscillator XT clock and the system clock selection flag CSF will be reset to 0 Executing the FAST instruction will change the clock source BCLK of the system clock generator to the fast speed oscillator CF clock and the system Clock Selection Flag CSF will be set to 1 For the operation of the system clock generator refer to section 2 2 3 The Watchdog Timer Enable Flag WTEF The Watchdog Timer Enable Flag WDF shows the operating status of the watchdog timer 3 The Overflow flag of the 16 bit counter of RFC RFOVF 45 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver The
33. 4 pins port IOC and INT pin will cause the stop mode to be released STOP Enter the stop mode STOP release MSC 10h Check the signal change on INT pin that causes the stop mode to be released MSB 11h Check the signal change on port IOC that causes the stop mode to be released MCX 12h Checks the signal change on KI1 4 pins that causes the stop mode to be released 50 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 16 HALT FUNCTION The halt function is provided to minimize the current dissipation of the TM87P18M when the LCD is still operating During halt mode the program memory ROM is not in operation only the oscillator circuit pre divider circuit sound circuit I O port chattering prevention circuit and LCD driver output circuit are in operation If the timer has started operating the timer counter still operates in the halt mode After executing the HALT instruction and no halt release signals SCF1 SCF3 6 are delivered the CPU enters halt mode The following 3 conditions are available to release halt mode 1 An interrupt is accepted When an interrupt is accepted the halt mode is released automatically and the program will enter the halt mode again by executing the RTS instruction after the completion of the interrupt service When halt mode is released and an interr
34. BCF This flag can be set reset by executing the SF 2h RF 2h instruction 43 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 14 3 STATUS REGISTER 3 5153 When the halt mode is released by the start condition flag 2 SCF2 the status register 3 STS3 will update the corresponding status flag wherein the cause for the release of the halt mode Status register 3 STS3 consists of 4 flags 1 The Start Condition Flag 4 SCF4 If the halt release enable flag 2 HEF2 is set the Start Condition Flag 4 SCF4 will be set to 1 when the signal change on the INT pin causes the halt release request flag 2 HRF2 to be output There are two methods to reset the Start Condition Flag 4 SCF4 one is to execute the PLC instruction to reset the halt release request flag 2 HRF2 and the other is to execute the SHE instruction to reset the halt release enable flag 2 HEF2 The Start Condition Flag 5 SCF5 If the halt release enable flag 1 HEF1 is set the Start Condition Flag 5 SCF5 will be set when an underflow signal from Timer 1 TMR1 causes halt release request flag 1 HRFI to be output There are two methods to reset the Start Condition Flag 5 SCF5 one is to execute the PLC instruction to reset the halt release request flag 1 HRF1 and the other is to execute the SHE instruction to reset the halt release enable flag 1 HEF1
35. Connect for Serial Program Read Mode ove for Connected VDD2 to VPP or floating for Normal Mode Serial Program Read Connect Pins VPP VDD2 VDD3 GND RESET INT BAK 11 tenx technology inc Preliminary Rev 1 0 2012 10 05 87 15 4 Bit Microcontroller with LCD Driver Advance Information CHARACTERIZATION 1 ABSOLUTE MAXIMUM RATINGS GND Name Symbol Range Unit VDDI 0 3 to 5 5 V VDD2 0 3 to 5 5 V Maximum Supply Voltage VDD3 03 to 8 5 V VPP 0 3 to 13 5 V Maximum Input Voltage Vin 0 3 to VDDI VDD2 0 3 V Maximum Output Voltage Voutl 0 3 to VDD1 VDD2 0 3 V p 5 2 0 3 to VDD3 0 3 V Maximum Operating Temperature Topg 40 to 80 Maximum Storage Temperature Tstg 25 to 125 2 POWER CONSUMPTION At VDD2 3 0V Ta 40 C to 80 C GND Name Sym Condition Min Typ Max Unit Only 32 768 KHz Crystal oscillator operating IHALT without loading BCF 0 1 4 duty phO BCLK D nu STOP mode ISTOP 1 uA Only 32 768 KHz Crystal oscillator operating Normal Mode Lok without loading BCE 0 1 4 duty phO BCLK i us 150 oscillator operating without loading Etpa de 0 1 4 duty phO BCLK 3e a 3 58 MHz ceramic I Only 3 58 MHz ceramic resonator operating without 480 J resonator 338 loading BCF 0 1 4 duty phO BCLK
36. D D represents the immediate data Binary ANDs the contents of Ry and D the result is loaded to AC AC Ry Ry amp D D represents the immediate data Binary ANDs the contents of Ry and D the result is loaded to AC and the working register Ry AC Ry EOR D D represents the immediate data Exlusive Ors the contents of Ry and D the result is loaded to AC AC Ry lt Ry D D represents the immediate data Exclusive Ors the contents of Ry and D the result is loaded to AC and the working register Ry AC lt Ry D D represents the immediate data Binary Ors the contents of Ry and D the result is loaded to AC AC Ry Ry D D represents the immediate data Binary Ors the contents of Ry and D the result is loaded to AC and the working register Ry 4 LOAD STORE INSTRUCTIONS STA Rx Function Description STA Function Rx AC The content of AC is loaded to data memory specified by Rx R HL AC Preliminary 121 tenx technology inc Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver Description The content of AC is loaded to data memory specified by HL STA HL Function lt HL HL 1 Description The content of AC is loaded to the data memory specified by HL The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index
37. FAST ONLY 3 PHO BCLK 8 PHO lt gt BCLK FOR FAST ONLY 4 PHO BCLK 16 25 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 2 5 System Clock Generator The system clock generator provides the necessary clocks to control the execution of instructions The FAST and SLOW instructions can also be used to switch the clock input of the system clock generator The basic system clock is as shown below SCLK T1 T2 T3 T4 Machine gt Instruction gt Cycle 3 PROGRAM COUNTER PC The program counter is a 12 bit counter which addresses the program memory ROM up to 4096 addresses The MSB of program counter PC11 is a page register Only CALL and JMP instructions can be used to address the whole address range 0001 FFFh the rest of relative jump instructions can address either page 0 000h 7ffh or page 1 800h FFFh The program counter PC is normally incremented by one 1 for every instruction execution PC 1 When executing JMP instructions subroutine call instructions CALL interrupt service routine or when reset occurs the program counter PC will be loaded with the corresponding address in table 2 1 PC corresponding address shown in Table 2 1 When e
38. For more detail information about Buzzer output function refer to section 3 4 3 3 Halver Doubler Tripler The halver doubler tripler circuitry generates the necessary bias voltage for LCD driver this circuitry consists of a combination of PH2 PH3 PH4 and PH5 When using Li battery power supply halver circuitry generates a 1 2 VDD voltage for suppling the MCU s functoins which is not related to the input output operation 3 4 Alternating Frequency for LCD The alternating clock is the basic clock for LCD driver Both COM and SEG pins shall change their output waveforms according to the alternating clock 4 BUZZER OUTPUT PINS TM87P18M provides a pair of buzzer output pins known as BZB and BZ which are pin shared with I O pins IOB3 and IOB4 and can be configured in mask option respectively BZB and BZ pins are versatile output pins with complementary output polarity When the buzzer output function combined with the clock source comes from the frequency generator it can generate a melody a sound effect or the carrier output for the remote controller MASK OPTION table Mask Option name Selected item SEG30 IOB3 BZB 3 BZB DC31 IOB4 BZ 3 BZ 66 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 05 MUX m s ALM 5 XD pco This figure shows the organization of the buzzer output
39. IOA1 IOA4 pins are MUX with CX SEG24 RR SEG25 SEG26 and RH SEG27 pins respectively by mask option MASK OPTION table Mask Option name Selected item SEG24 IOA 2 SEG25 IOA2 RR 2 IOA2 SEG26 IOA3 RT 2 IOA3 SEG27 IOA4 RH 2 IOA4 The default setting of IOA port is input mode in initial reset cycle each bit of the port can be defined as input mode or output mode respectively by executing a SPA instruction Executing an OPA instruction can output the content of the specified data memory to the pins which have been defined as output mode Executing an IPA instruction can store the I O pins signal into the specified data memory locations When the IO pins are defined as output mode executing an IPA instruction will store the content of the latch of the output pin into the specified data memory location Before executing the SPA instruction to set the I O pins to output mode the OPA instruction must be executed to output the data to those output latches beforehand This will prevent the chattering signal on the I O pin when the I O mode changes The IOA port has a built in pull low resistor which can be selected in mask option and be enabled disabled by executing a SPA instruction Pull low function option Mask Option name Selected item IOA PULL LOW RESISTOR 1 USE IOA PULL LOW RESISTOR 2 NO USE 69 tenx technology inc Preliminary Rev 1 0 201
40. LCD Driver MRF1 Rx Function Rx AC RFC 3 0 Description Loads the lowest nibble data of 16 bit counter of RFC to AC and data memory specified by Rx Bit3 3 Bit2 RFC 2 Bit Bit0 0 MRF2 Rx Function Rx AC RFC 7 4 Description Loads the 2nd nibble data of 16 bit counter of RFC to AC and data memory specified by Rx Bit3 RFC 7 Bit2 RFC 6 Bitl RFC 5 0 RFC 4 MRF3 Rx Function Rx lt RFC 11 8 Description Loads the 3rd nibble data of 16 bit counter of to AC and data memory specified by Rx RFC 11 Bit2 RFC 10 Bit RFC 9 Bit0 8 MRF4 Rx Function Rx AC RFC 15 12 Description Loads the highest nibble data of 16 bit counter of RFC to and data memory specified by Rx Bit3 RFC 15 Bit2 RFC 14 Bit 13 Bit0 RFC 12 5 CPU CONTROL INSTRUCTIONS NOP Function no operation Description operation HALT Function Enters halt mode Description The following 3 conditions cause the halt mode to be released 1 An interrupt is accepted Preliminary 123 tenx technology inc Rev 1 0 2012 10 05 Advance Information 87 18 E 4 Bit Microcontroller with LCD Driver 2 The signal change specified by the SCA instruction is applied to IOC 3 The halt release condition specified by SHE instruction is met When an interrupt is accepted to release the halt mode the hal
41. Lz HL 0000 100Z ZZZZ 7001 Lz lt 7SEG HL LCB Lz HL 10000 100Z ZZZZ Z010 Lz E OE fM Blank Zero LCP Lz HL 0000 100Z ZZZZ Z011 Lz lt HL amp OPA Rx 0000 1010 XXXX Rx OPAS Rx D 0000 1011 XXXX 1 2 3 4 lt Rx0 Rx1 D Pulse OPB Rx 0000 1100 XXXX Rx OPC Rx 0000 1101 XXXX Port C Rx OPD Rx 000011100XXX XXXX Rx FREQ lt Rx amp AC 00 1 4 Duty FRQ D Rx 0001 0000 D 01 1 3 Duty D 10 1 2 Duty D 11 1 1 Duty FRQ D HL 0001 01DD 0000 0000 FREQ TGHL FRQX DX 0001 1ODD XXXX XXXX FREQ lt Rx 0001 1100 OXXX XXXX UOIIDBF0 3 Rx MVH Rx 0001 1101 XXXX IDBF4 7 Rx MVU Rx 0001 1110 XXXX IDBF8 11 Rx ADC Rx 001000000XXX XXXX AC Rx HL 0010 0000 1000 0000 AC lt HL AC CF CF AC lt HL AC CF ADC HL 0010 0000 1100 0000 HL HL 1 CF ADC Rx 0010 0001 XXXX Rx ADC HL 0010 0001 1000 0000 HL lt HL AC CF CF AC HL lt HL ADC HL 0010 0001 1100 0000 HL HL 1 CF SBC Rx 0010 0010 XXXX lt Rx ACB CF SBC HL 0010 0010 1000 0000 AC lt HL ACB CF AC lt HL SBC HL 0010 0010 1100 0000 HL HL 1 CF SBC Rx 0010 0011 XXXX AC Rx lt Rx ACB CF CF SBC HL 0010 0011 1000 0000 HL lt HL CF A
42. PH3 The 3rd stage output of the predivider PH5 5th stage output of the predivider 7 7th stage output of the predivider PH9 9th stage output of the predivider 11 The 11th stage output of the predivider PH13 The 13th stage output of the predivider 15 The 15th stage output of the predivider 8 When the TMRI clock is FREQ set time Set value error 1 FREQ KHz ms FREQ refer to section 3 3 4 12 2 RE LOAD OPERATION TMRI provides a re load function which can last for a time interval longer than 3Fh The SF 80h instruction enables the re load function and RF 80h instruction disables it When the re load function is enabled the TMR1 will count down with a 3Fh initial data automatically if TMRI s underflow occurs Once the re load function has been disabled TMR1 s underflow will stop immediately During this operation the program must use halt release request flag or interrupt to calculate the desired counting value It is necessary to execute either the TMS or the TMSX instructions to initiate the count down value before the re load function is enabled otherwise TMRI will automatically count down with an unknown value Do not disable the re load function before the last expected halt release or interrupt occurs If the TMS related instructions are not executed after each halt release or an interrupt occurs TMRI will stop operating immediately after th
43. Rees eto kn 46 15 CONTROL REGISTER CTL 47 S L CONTROL REGISTER 1 C LL E 47 15 1 1 The Setting for Halt Mode 48 15 1 2 The Setting for Stop 48 134153 Interrupt for CTEL u uuu uu u uM vU M MM aaa eee 48 15 2 CONTROL REGISTER 2 E TLD2Z1 uu anan Da Rd neat 49 15 2 CONTROL aA IQ ax MEN uten 49 15 4 CONTROL REGISTER 4 o peux EE 50 I6 HALT FUNCTION 51 17 BACK UP FUNCTION NUN SEEN SNR ERN SERERE NN HRS CK NOSE 52 18 STOP FUNCTION STOP icsssubuedsnizentes tkctuscus ek eo FR o Rd 53 Chapter 3 Control Function 55 1
44. The signal change from the INT pin causes the halt release flag 2 HRF2 to output the stop release enable flag 5 SRF5 has to be set beforehand The following figure shows the organization of Start Condition Flag 11 SCF 11 HRF2 KI1 11 Stop release SRF7 request IOC1 IOC2 IOC3 IOC4 SRF4 SRF3 46 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver The stop release flags SKI CSR DSR HRF2 are specified by the stop release enable flags SRFx These flags should be cleared before the chip enters stop mode All of the pins in the IOA and IOC ports have to be set in input mode and keep in 0 state before the chip enters the STOP mode otherwise the program can not enter STOP mode Instruction SRE is used to set or reset stop release enable flags SRF4 5 7 The following table shows the stop release request flags The OR ed latched signals The OR ed input mode pins The rising or falling edge X 4 of IOC IOD port on INT pin Stop release requestflag Stop release requestflag request flag la s CSR DSR HRF2 Stop release enable flag SRF7 SRFA SRF3 15 CONTROL REGISTER CTL The control register CTL comes in 4 types control register 1 to control register 4 CTL 4 15 1 CONTROL REGISTER 1 CTL1 The control register 1 is a
45. activates K2 column X Xo 1110 activates K15 column X Xo activates K16 column X7X5X4 001 in this setting all of the matrix columns K16 will be checked simultaneously in each scanning cycle X Xgare not a factor X7X5X4 010 in this setting the key matrix scanning function will be disabled X Xp are not a factor X5X5X4 10X in this setting each scanning cycle checks 8 specified columns on the key matrix The specified column is defined by the setting of X3 X 0 activates K8 columns simultaneously 1 activates K16 columns simultaneously X Xo don t care 110 in this setting each scanning cycle checks four specified columns on key matrix The specified columns are defined by the setting of X and 00 activates K4 columns simultaneously 01 activates K5 K8 columns simultaneously 10 activates K12 columns simultaneously 11 activates K16 columns simultaneously Xo don t care 86 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 111 in this setting each scanning cycle checks two specified columns on key matrix The specified columns are defined by the setting of X5 X and X3X5X 000 activates K2 columns simultaneously X3X5X 001 activates K4 columns simultaneously X3X5
46. combining the data DBUSA to DBUSH with the address PSTB Oh to PSTB 1Fh any one of 256 signals corresponding to the number of latch circuits incorporated in the hardware can be selected by programming the aforementioned segment LRAM Table 4 3 3 shows the selectable PSTB Oh to PSTB 1Fh in mask option Table 4 3 3 Strobe Signal for LCD Latch in Segment LRAM and Strobe in the LCT Instruction Strobe signal for Strobe in LCT LCB LCP LCD instructions E Note The values of Q are the addresses of the working register in the data memory RAM In the LCD instruction Q is the index address in the table ROM The LCD pattern pixels can be turned off without changing the DBUS data The execution of the SF2 4h instruction can turn off all the patterns on the LCD panel simultaneously The execution of the RF2 4h instruction can turn on the panel These two instructions will not affect the content stored in the latch circuitry When executing the RF2 4h instruction to turn off the LCD the program can still execute LCT LCB LCP and LCD instructions to update the content in the latch circuitry The new data will be displayed on the LCD panel while the panel is turned on again In the stop mode all COM and SEG outputs of LCD driver will automatically switch to the GND state to eliminate the DC bias on the LCD panel 95 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller wit
47. data before DAA AC data after DAA CF data after DAA execution execution execution execution 0 lt lt 9 lt lt 6 lt lt 3 6 Example 1 LDS 10h 9 Load immediate data 9 to data memory address 10H LDS 11h 1 Load immediate data 1 data memory address 11H and AC RF lh Reset CF to 0 ADD 10h Contents of the data memory address 10H and AC are binary added the result loads to AC amp data memory address 10H RIO AC AH 0 33 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver DAA 10h Convert the content of AC to decimal format The result in the data memory address 10H is 0 and in the CF is 1 This represents the decimal number 10 Instructions DAS DAS DAS can convert the data from hexadecimal format to decimal format after any subtraction operation The conversion rules are shown in the following table and illustrated in Example 2 AC data before DAS CF data before DAS AC data after DAS CF data after DAS execution execution execution execution 0s AC x9 6S ACXF Example 2 LDS 106 1 Load immediate the data memory address 10H LDS 11h 2 Load immediate data 2 to data memory address and SF lh Set CF to 1 which means no borrowing has occurred SUB 10h Content of data memory addres
48. eee J gt L J ll jJ GND segnments on COM4 5 with bL TP e 20 VOD lighted JL 1 GND segnments on 1 2 3 4 5 with lighted sides GND 102 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver iii Display Turned Off VDD COM1 2 3 4 5 in low active GND VDD COM1 2 3 4 5 in high active GND VDD All LED driver outputs GND iv Stop mode VDD 1 2 3 4 5 in low active GND VDD COM1 2 3 4 5 in high active GND VDD All LED driver outputs GND Figure 4 4 5 1 5 duty LED Waveform 103 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver Chapter 5 Detail Explanation of TM87P18M Instructions It is recommended to initialize the content of the data memory after the initial reset because the initial values of them are unknown The working registers are part of the data memory RAM and the relationship between them is shown as follows The absolute address of working register Rx Ry 70H Address of working registers specified by Ry Absolute address of data memory Rx 70H represents the address of the LCD pixel latch which is configured in the segment LRAM the address range specified by Lz is from 00H to 1FH 1 INPUT OUTPUT INSTRUCTIONS LCT Lz Ry Func
49. figure shows the timing of the counter controlled by the CX pin Example SCC Oh Select the base clock of the frequency generator that comes from PHO XT clock FRQX 1 5 Set the frequency generator to FREQ PH0 3 5 the count value of the frequency generator is 5 and CK FREQ is 1 3 duty waveform The setting value of the frequency generator is 5 and FREQ 84 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information SHE SRF HALT PLC MRF1 MRF2 MRF3 MRF4 UM TM87P18M_E 4 Bit Microcontroller with LCD Driver has a 1 3 duty waveform 40h Enable the halt release caused by 16 bit counter 28h Enable the counter controlled by the CX signal 40h A halt release request is caused by the 2 rising edge on CX pin and then clear the halt release request flag 10h Read the content of the counter 11h 12h 13h 8 Key Matrix Scanning The key matrix scanning function is made up of the four input pins KI4 16 output pins shared with the LCD output pins SEG1 SEGI6 For ease of explanation these will be referred to as KO1 KO106 in the rest of the document and the external matrix keyboard The input port of the key matrix circuitry is composed of pins these pins are muxed with IOCI IOC4 pins and selected in mask option MASK OPTION table Mask Option name Selected item IOC1 KI1 3 IOC2 KD 3 KD 3
50. incremented automatically after executing this instruction The result will not affect the Carry Flag CF HL indicates an index address of data memory AND Rx Function AC Rx amp AC Description Binary ANDs the contents of Rx and AC the result is loaded to AC AND HL Function lt HL amp AC Description Binary ANDs the contents of 9 HL and AC the result is loaded to AC HL indicates an index address of data memory AND HL Function HL amp HL 1 Description Binary ANDs the contents of HL and AC the result is loaded to AC The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory AND Rx Function AC Rx Rx amp AC Description Binary ANDs the contents of Rx and AC the result is loaded to AC and the data memory Rx AND HL Function HL lt HL amp AC Description Binary ANDs the contents of HL AC the result is loaded to AC and the data memory HL HL indicates an index address of data memory AND HL Function AC HL HL amp HL HL 1 Description Binary ANDs the contents of HL and AC the result is loaded to AC and the data memory HL The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory
51. instruction In this case if the interrupt enable flag 0 IEFO is set to 1 interrupt 0 is accepted and the instruction at address 14H will be executed automatically Key matrix Scanning interrupt request An interrupt request signal HRF5 will be generated when an input signal is generated in the scanning interval If the Interrupt Enable Flag 5 IEF5 is set to 1 and interrupt 5 is accepted the instruction at address 24H will be executed automatically 1 1 2 Internal Interrupt Factor The internal interrupts are generated by Timer 1 TMR1 Timer 2 TMR2 RFC counter and the pre divider 1 2 3 Timer1 2 1 2 interrupt request An interrupt request signal HRF1 4 is generated when Timer1 2 1 2 underflows In this case if the interrupt enable flag 1 4 1 1 4 is set beforehand and interrupt 1 4 is accepted the instruction at address 18H 20H will be executed automatically Pre divider interrupt request An interrupt request signal HRF3 is generated when the pre divider overflows In this case if the Interrupt Enable Flag3 IEF3 is set beforehand and interrupt 3 is accepted the instruction at address 1 will be executed automatically The 16 bit counter of RFC CX pin control mode interrupt request An interrupt request signal HRF6 is generated when the control signal applied on the CX pin is inactive and the 16 bit counter stops to operate In this case if the Interrupt Enable Flag6
52. lt REE Be 1D ES PRA y tenx technology inc TM87P18M 4 Bit Microcontroller with LCD Driver User Manual tenx reserves the right to change or discontinue the manual and online documentation to this product herein to improve reliability function or design without further notice tenx does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others tenx products are not designed intended or authorized for use in life support appliances devices or systems If Buyer purchases or uses tenx products for any such unintended or unauthorized application Buyer shall indemnify and hold tenx and its officers employees subsidiaries affiliates and distributors harmless against all claims cost damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that tenx was negligent regarding the design or manufacture of the part tenx technology inc Rev 1 0 2012 10 05 Advance Information UM TM87P18M_E 4 Bit Microcontroller with LCD Driver AMENDMENT HISTORY Version Date Description V1 0 Jul 2012 New release Preliminary tenx technology inc Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller w
53. of HL the result is loaded to the data memory HL and AC The content of the index register HL will be incremented automatically after executing this instruction The Carry Flag CF will be affected HL indicates an index address of data memory AC Rx AC CF The contents of Rx AC and CF are binary added the result is loaded to AC The Carry Flag CF will be affected Preliminary 112 tenx technology inc Rev 1 0 2012 10 05 Advance Information 87 18 ADC HL Function Description ADC HL Function Description ADC Rx Function Description ADC HL Function Description ADC HL Function Description SBC Rx Function Description 4 Bit Microcontroller with LCD Driver AC R HL AC CF The contents of data memory specified by 9 HL AC and CF are binary added the result is loaded to AC The Carry Flag CF will be affected AC HL AC CF HL HL 1 Binary adds the contents of HL AC and CF the result is loaded to AC The content of the index register 9 HL will be incremented automatically after executing this instruction The Carry Flag CF will be affected HL indicates an index address of data memory AC Rx Rx AC CF The contents of Rx AC and CF are binary added the result is loaded to AC and data memory Rx The carry flag CF will be affected AC R HL R HL AC CF The contents of data memory speci
54. of the table ROM and data memory index addressing DATA RAM TABLE ROM index HL addressing This figure shows the diagram of the index address register The index address register is a write only register CPHL X instruction can specify 8 bit immediate data to compare with the content of H and L If the result of the comparison is equivalent the instruction behind CPHL X will be skipped NOP if it is not equivalent the instruction behind CPHL X will be executed normally Note During the process of the comparison of the index address all the interrupt enable flags IEF must be cleared to avoid malfunction The comparison bit pattern is shown below CPHL X 7 6 5 4 X3 X2 0 HL IDBF7 IDBF6 IDBF5 IDBF4 IDBF3 IDBF2 IDBFI IDBFO Example HL 30h CPHL 30h SIE Oh disable IEF 30 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver JMP lablel this instruction will not be executed NOP JMP 1 2 this instruction will be executed and than jump to lable2 lablel lable2 6 STACK REGISTER STACK Stack is a special design register following the first in last out rule It is used to save the contents of the program counter sequentially during subroutine call or execution of the interrupt service routine The contents of stac
55. on the clock source of TMR2 When the TMR2 underflow occurs the 16 bit counter will stop counting immediately TMR2 can produce an accurate time period to control the counting of the 16 bit counter For a detail description of the operation of TMR2 please refer to 2 13 Each time the 16 bit counter is enabled the content of the counter will be cleared automatically SFE s Brod 06 Thee Xm mX my 3m Crier teare o KrK ec EAT Li 111111111 11111111111 Fit cia eget arer dats Cariri s kort bythe Tne 22 This figure shows the timing of the RFC counter controlled by timer 2 Example In this example the RT network is used to generate the clock source SRF 1Ah Build up the RT network and enables the counter controlled by TM2 SHE 10h Enable the halt release caused by TM2 TM2X 20h Set the 9 as the clock signals for TM2 and the count down value is 20h HALT PLC 10h Clear the halt release request flag of TM2 MRF1 10h Read the content of the counter MRF2 11h MRF3 12h MRF4 13h 83 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 7 4 Enable Disable the Counter by CX Signal This is another usage for the 16 bit counter but it is not related to the RFC function In the applications described in th
56. released IOD3 chattering Q 1004 R PAE chattering EHE prevention clcok PLC 1 Interrupt accept SCC intruction SCA intruction This figure shows the organization of chattering prevention circuitry Note The default prevention clock is PH10 The chattering prevention function will be invoked when the signal on the applicable pin e g IOD1 changes from L level to H level or from H level to L level and the remaining pins e g 1002 to IOD4 are held at level When the signal changes on the IOD port pins in input mode specified by the SCA instruction and stays in the state for at least two chattering clock PH6 PH8 and PH10 cycles the control circuit that operates upon the input pins will transmit the halt release request signal SCF3 At that time the chattering prevention clock will stop due to the transmission of SCF3 The SCF3 can be reset to 0 by executing a SCA instruction and the chattering prevention clock will be enabled at the same time If the SCF3 has been set to 1 the halt release request flag 0 HRFO will be generated In this case if the interrupt enable mode IEFO of the port IOD 18 set the interrupt will be accepted Since no flip flop is available to hold the information of the signal on the input pins of IOD1 to IOD4 the input data on the port IOD should be stored into the RAM immediately after the halt mode is released 77 tenx technology inc Preliminary Rev 1 0
57. the TM87P18M will enter the halt mode immediately and will process the halt release procedure If signal on the IOC IOD port does not hold long enough to set the SCF1 SCF3 once the signal on the IOC port returns to L the TM87P18M will enter stop mode The backup flag BCF will be set to 1 automatically after the MCU enters stop mode The following diagram shows the stop release procedure Figure The stop release state machine Before the STOP instruction is executed the following operations must be completed Set the stop release conditions by the execution of the SRE instruction Set the halt release conditions corresponding to the stop release conditions if needed Set the interrupt conditions corresponding to stop release conditions if needed When stop mode is released by an interrupt request TM87P18M will enter the halt mode immediately Once the interrupt is accepted the halt mode will be released and then enters the interrupt service routine The MCU will return to the stop mode again by executing the RTS instruction after the interrupt service is completed 53 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver Once the MCU is released from the stop release the execution of the MSB MSC or the MCX instruction can test the halt release signals and the execution of the PLC instruction can reset the halt release
58. when changing the I O mode IOD port has a built in pull low resistor for each pin which can be selected in mask option and can be enabled or disabled this resistor by executing a SPD instruction When the IOD pin is set to the output mode the pull low device will be disabled MASK OPTION table Pull low function option Mask Option name Selected item IOC PULL LOW RESISTOR 1 USE IOC PULL LOW RESISTOR 2 NO USE This figure shows the organization of IOD port Note If the input level is in the floating state a large current straight through current will flow to the input buffer when both the pull low and L level hold devices are disabled Therefore the input level must not be in the floating state 5 4 1 Chattering Prevention Function and Halt Release The port IOD is capable of preventing the chattering signals bounce applied on the IOD1 to IOD4 pins The de bounce time can be selected as PH10 32 ms PH8 8 ms or PH6 2 ms by executing a SCC instruction The default selection is PH10 after the reset cycle The following figure shows the organization of chattering prevention circuitry 76 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver SPD 2 IERO Interrur SPD 4 HRF0 Edge reques SPD 8 detect R 1001 oo edge dectect amp Is aL SCF3 HALT
59. will pause when the program enters the halt or the stop mode When the TM87P18M wakes up from the halt or the stop mode the timer operates continuously It is recommended to execute a SF 10h instruction before the program enters the halt or the stop mode This will keep the MCU away from the unexpected reset when it is released from halt or stop mode Once the watchdog timer is enabled the program must execute the SF 10h instruction to clear the watchdog timer periodically it will prevent the watchdog timer from overflow The overflow time interval of the watchdog timer is selected in mask option MASK OPTION table Mask Option name Selected item WATCHDOG TIMER OVERFLOW TIME INTERVAL 1 8 x PHIO WATCHDOG TIMER OVERFLOW TIME INTERVAL 2 64 x PH10 WATCHDOG TIMER OVERFLOW TIME INTERVAL 3 512 x PHIO Note timer overflow time interval is about 16 seconds when PHO 32 768 KHz 63 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 3 OCK GENERATOR 3 1 REQUENCY GENERATOR The Frequency Generator is a versatile programmable divider that is capable of delivering a clock with wide frequency range and different duty cycles The output of the frequency generator may be the clock source for the alarm function timer1 timer2 and RFC counter The following shows the organization of the frequency generator 8 bit Programmable Duty Cycl
60. 00 0000 AC lt HL AND AC AC HLAND AC AND HL 0010 1010 1100 0000 HL HLH AND Rx 0010 1011 XXXX Rx AND AC AND 0010 1011 1000 0000 AC HL HL AND AC AC HL HLAND AC AND HL 0010 1011 1100 0000 HL HLH EOR Rx 0010 1100 Rx EOR AC EOR HL 0010 1100 1000 0000 AC lt HL EOR AC HL EOR EOR HL 0010 1100 1100 0000 HL HLH Rx 0010 1101 OXXX XXXX lt Rx EOR AC EOR HL 0010 1101 1000 0000 AC HL lt HL EOR AC HL GHL EOR EOR HL 0010 1101 1100 0000 HL HLH OR Rx 0010 1110 lt Rx OR AC OR HL 0010 1110 1000 0000 AC lt HL OR AC AC GHL OR AC OR HL 0010 1110 1100 0000 HL HLH Rx 00101111 XXXX lt Rx OR AC OR HL 0010 1111 1000 0000 AC HL lt HL OR AC AC HL lt HL AC OR HL 0010 1111 1100 0000 HL HL 1 ADCI Ry D 0011 0000 DDDD YYYY lt ADCI 0011 0001 DDDD YYYY lt 5 00110010 DDDD YYYY lt Ry DB SBCI 0011 0011 DDDD YYYY lt Ry DB ADDI Ry D 00110100 DDDD YYYY lt Ry D ADDI RyD 0011 0101 DDDD YYYY lt Ry D SUBI Ry D 0011 0110 DDDD YYYY lt Ry x 1 SUBI 00110111 DDDD YYYY lt 1 ADNI Ry D 0011 1000 DDDD YYYY lt ADNI 0011 1001 DDDD YYYY
61. 1 SLOW 32 Hz LCD frame frequency 2 TYPICAL 64 Hz LCD frame frequency 2 FAST 128 Hz LCD frame frequency 2 0 Hz LCD is not used The following table shows the relationship between the LCD lighting system and the maximum number of driving LCD segments LCD Lighting System The Maximum Number of Driving LCD Segments Remarks Duplex 1 2 bias 1 2 duty 82s Connect VDD3 to VDD2 1 2 bias 1 3 duty Connect VDD3 to VDD2 1 2 bias 1 4 duty Connect VDD3 to VDD2 1 2 bias 1 5 duty 1 2 bias 1 6 duty 1 2 bias 1 7 duty 1 3 bias 1 3 duty 1 3 bias 1 4 duty 1 3 bias 1 5 duty 287 82 22087 f 05 46 Connect VDD3 to VDD2 Connect VDD3 to VDD2 Connect VDD3 to VDD2 1 2 bias 1 8 duty Connect VDD3 to VDD2 1 3 bias 1 6 duty 1 3 bias 1 7 duty 1 3 bias 1 8 duty It is recommended to choose the frame frequency higher than 24 Hz If the frame frequency is lower than 24 Hz the pattern on the LCD panel will start to flicker 2 DC OUTPUT TM87P18M allows the LCD driver output pins COM5 8 and SEG17 SEG23 40 41 to be defined as CMOS type DC output or P open drain DC output ports in mask option It is also possible to use some LCD driver output pins as DC output and the rest of the LCD driver output pins as LCD drivers Refer to 4 3 4 for details The configurations of CMOS output type and P open drain type are shown below When the LCD driver output pins SEG are defined as DC output ports the out
62. 1 7 duty 1 3 bias 1 8 duty these options for the lighting systems are combined into 2 kinds in mask options the LCD DUTY CYCLE and the BIAS MASK OPTION table LCD duty cycle option Mask Option Name Selected Item LCD DUTY CYCLE 1 O P LCD DUTY CYCLE 2 DUPLEX note 1 2 duty LCD DUTY CYCLE 3 1 3 DUTY LCD DUTY CYCLE 4 1 4 DUTY LCD DUTY CYCLE 5 1 5 DUTY LCD DUTY CYCLE 6 1 6 DUTY LCD DUTY CYCLE 7 1 7 DUTY LCD DUTY CYCLE 8 1 8 DUTY 90 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information LCD bias option 87 18 Mask Option name Selected item BIAS 1 NO BIAS BIAS 2 1 2 BIAS BIAS 3 1 3 BIAS The LCD frame frequency in duplex 1 2 duty type 4 Bit Microcontroller with LCD Driver The frame frequency for each lighting system is shown below These frequencies can be selected in mask option The entire LCD frame frequencies in the following tables are based on the slow clock source is Mask Option name Selected item Frequency LCD frame frequency 1 SLOW 16 Hz LCD frame frequency 2 TYPICAL 32 Hz LCD frame frequency 2 FAST 64 Hz LCD frame frequency 2 0 Hz LCD is not used The LCD frame frequency in 1 3 duty type Mask Option name Selected item Frequency LCD frame frequency 1 SLOW 21 Hz LCD frame frequency 2 TYPICAL 42 Hz LCD fr
63. 2 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver Initial clear SPA 1 Initial clear SPA 4 a Initial clear IOA Pull low option This figure shows the organization of IOA port Note If the input level is in the floating state a large current straight through current flows to the input buffer The input level must not be in the floating state 5 1 1 Pseudo Serial Output The IOA port may operate as a pseudo serial output port by executing an OPAS instruction The IOA port must be defined as output mode before executing an OPAS instruction 1 BITO and 1 of the port deliver RAM data 2 BIT2 of the port delivers the constant data D in operand 3 BIT3 of the port delivers a pulse Shown below is a sample program using the OPAS instruction to perform a serial output function 1 LDS 0 2 70 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver LDS 1 5 3 OPAS 1 1 Bit 0 output enable the serial output function 4 SRO 1 Shift bit 1 to bit 0 5 OPAS 1 1 Bit 1 output 6 SRO 1 Shift bit2 to bit 0 7 OPAS 1 1 Bit 2 output 8 SRO 1 Shift bit 3 to bit O 9 OPAS 1 1 Bit 3 output 10 OPAS 1 1 Output the Last bit data 11 OPAS 1 0 Inactive the serial output function The above program is i
64. 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 6 EXTERNAL INT PIN There are three kinds of input type can be selected in mask option for the INT pin pull up pull down and high impedance A signal change either rising edge or falling edge in mask option will set the halt release request flag 2 HRF2 In this case if the halt release enable flag HEF2 is set the start condition flag 2 will be set and a corresponding signal is delivered If the INT pin Interrupt Enable Flag IEF2 is set the interrupt will be accepted MASK OPTION table For internal resistor type Mask Option name Selected item INT PIN INTERNAL RESISTOR 1 PULL HIGH INT PIN INTERNAL RESISTOR 2 PULL LOW INT PIN INTERNAL RESISTOR 3 OPEN TYPE For input triggered type Mask Option name Selected item INT PIN TRIGGER MODE 1 RISING EDGE INT PIN TRIGGER MODE 2 FALLING EDGE IEF2 Interrupt request HEF2 SCF2 Halt release request Mask option PLC 4h Initial clear pulse Interrupt 2 receive signal Mask option Open type This figure shows the INT Pin Configuration Note For Ag battery power supply positive power is connected to VDD1 for anything other than Ag battery power supply it is connected to VDD2 78 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 7 Resistor to Frequency Converter RFC
65. 3 1 The is set so that the halt mode is released by predivider overflow 4 1 The is set so that the halt mode is released by TMR2 underflow X6 1 The HEF6 is set so that the halt mode is released by RFC counter overflow X7 is reserved 124 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 E 4 Bit Microcontroller with LCD Driver SRE X Function Set Reset stop release enable flag Description 4 1 The SRF4 is set so that the stop mode is released by the signal change on IOC port X5 1 The 5 5 is set so that the stop mode is released by the signal change on INT pin X6 X3 0 is reserved FAST Function Switches the system clock to CFOSC clock Description Starts up the CFOSC high speed osc and then switches the system clock to high speed clock SLOW Function Switches the system clock to XTOSC clock low speed osc Description Switches the system clock to low speed clock and then stops the CFOSC MSB Rx Function AC Rx lt SCF3 SCF1 SCF2 Description The SCF1 SCF2 and flag contents are loaded to AC and the data memory specified by Rx The content of AC and meaning of bit after execution of this instruction are as follows Bit 3 Bit 2 Bit 1 Bit 0 Start Condition Flag 3 Start Condition Flag 2 Start Condition Flag 1 Backup flag SCF 3 SCF2 5 1 Halt release caused by Halt release caused by Ha
66. 3 1 111 gt KO15 16 lt STACK RTS 1111 0100 0000 0000 PC CALL Return X6 1 Cfq BCLK X6 0 Cfq PHO 4 1 Set 5 X 11110100 1X0X XXXX 3 1 Set P D Cch X2 1 0 001 Cch PH10 X2 1 0 010 Cch PH8 X2 1 0 100 6 4 Enable SEF4 C1 4 SCA X 1111 0101 000X X000 xa Enable SEF3 D1 4 X4 Set A4 1 Pull Low 1 Pull low 3 0 Set A4 1 1 Output 0 Input 4 Set B4 1 Pull Low 1 Pull low P 5 X3 0 Set B4 1 I O 1 Output 0 Input 4 Set C4 1 Pull Low 1 Pull low 0 LLH SPC 11110101 110 Low Level Hold X3 0 Set C4 1 1 Output 0 Input 4 Set 4 1 Pull Low 1 Pull low SED DH X3 0 Set D4 1 1 Output 0 Input 7 Reload 1 Set 4 WDT Enable SF 1111 0110 Xi Set 7 Reload 1 Reset 4 Reset RF X 11110111 X00X 00XX Xi Reset X0 CF Reset 8 7 6 111 FREQ X8 7 6 100 DCI X8 7 6 011 PH3 ALM X 1111 110X XXXX X8 7 6 010 PHA X8 7 6 001 PHS X8 7 6 000 DCO X5 0 lt PH15 10 X3 Enable INT powerful Pull low SF2 X 1111 1110 0000 XXXX X2 Close all Segments X1 Dis ENX Set Reload 2 Set X3 Disable INT powerful Pull low RF2 1111 1110 1000 2 Release Segments Dis ENX Reset Reload 2 Reset HALT 1111 1111 0000 0000 Halt Operation STOP 1111 1111 1000 0000 Stop Operation Preliminary 140 tenx techn
67. 4 4 3 The typical application circuit of the key matrix scanning is shown below Executing the SPKX X SPK Rx and SPK HL instructions can set the scanning type of the key matrix The bit patterns of these 3 instructions are shown below KES RGSS KEM KO 6 HRS Fe KM LT TE ES 3208 Preliminary 85 tenx technology inc Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver This figure shows the key matrix Instruction Bit7 Bit6 5 Bit4 Bit3 Bit2 Bitl SPKX X X7 X6 X5 X4 X3 X2 X1 5 2 1 Rx3 Rx2 Rx0 SPK HL T HL7 T HL6 T HL5 T HL4 T HL3 T HL2 T HLI T HLO The following description shows the bit definition of the operand in the SPKX instruction Xs 0 when HEFS is set to 1 the HALT release request 5 will be set to 1 after the key is depressed on the key matrix and then SCF8 will be set to 1 1 when is set to 1 the HALT released request HRF5 will be set to 1 after each scanning cycle regardless of key is depressed and then SCF8 will be set to 1 X5X5X4 000 in this setting each scanning cycle only checks one specified column K16 on the key matrix The specified column is defined by the setting of X3 Xo X5 Xo 0000 activates column X Xo 0001
68. C 1110 101 X6 0 Reset HRF6 0 X5 Enable Cx Control 4 Enable TM2 Control X3 Enable Counter ENX BRE 2 Enable RH Output EHM Enable RT Output ETP Enable RR Output ERR 7 Enable 5 7 5 ma 1110 1101 000 5 Enable SRES INT 4 Enable SRF4 C port X3 Enable SRE3 D port FAST 1110 1110 0000 0000 SCLK High Speed Clock SLOW 1110 1110 1000 0000 SCLK Low Speed Clock lt force NOP if CPHL 1110 XXXX 1 X7 0 IDBF7 0 SPK Rx 1111 0000 XXXX KOI 16 lt Rx amp AC SPK HL 1111 0001 0000 0000 16 lt T HL KEY S is released by scanning cycle 6 1 KEY_S is released by normal key scanning X6 0 Set one of KO1 16 l by X3 0 X7 5 4 000 Set all 1 Set all Hi z X7 5 4 001 Set eight of KO1 16 1 by X7 5 4 010 X3 X7 5 4 10X X3 0 gt 1 8 5 1111 0010 XXXX XXXX 1 gt KO9 16 Set four of KO1 16 1 by X3 2 7 5 4 110 2 00 4 2 01 gt 5 8 X3 2 10 gt KO9 12 X3 2 11 gt KO13 16 Set two of KO1 16 1 by X3 2 1 X7 5 4 111 X3 1 000 gt KO1 2 X3 1 001 gt KO3 4 3 1 010 gt 5 6 X3 1 011 gt KO7 8 139 tenx technology inc Rev 1 0 2012 10 05 Advance Information UM TM87P18M_E 4 Bit Microcontroller with LCD Driver X3 1 100 gt KO9 10 X3 1 101 gt KO11 12 X3 1 110 gt KO13 14 X
69. C HL lt HL ACB SBC HL 0010 0011 1100 0000 HL HL 1 CF ADD Rx 0010 0100 XXXX lt Rx HL 0010 0100 1000 0000 AC lt HL AC CF AC HL AC ADD GHL 0010 0100 1100 0000 HL HL 1 CF ADD Rx 0010 0101 OXXX XXXX lt Rx AC CF ADD GHL 0010 0101 1000 0000 AC HL lt HL AC CF HL HL AC ADD GHL 0010 0101 1100 0000 HL HL 1 CF SUB Rx 0010 0110 Rx 1 SUB HL 0010 0110 1000 0000 AC lt HL ACB 1 SUB HL 0010 0110 1100 0000 AC lt HL ACB 1 CF Preliminary 135 tenx technology inc Rev 1 0 2012 10 05 Advance Information UM TM87P18M_E 4 Bit Microcontroller with LCD Driver HL lt HL 1 SUB Rx 0010 0111 OXXX XXXX AC Rx lt Rx ACB 1 CF SUB HL 0010 0111 1000 0000 AC HL lt HL ACB 1 CF AC HL lt HL ACB 1 SUB HL 0010 0111 1100 0000 HL HLH CF ADN Rx 001010000XXX XXXX AC lt Rx AC ADN HL 0010 1000 1000 0000 AC lt HL AC AC HL AC ADN HL 0010 1000 1100 0000 HL HLH ADN Rx 0010 1001 OXXX XXXX lt Rx AC ADN HL 0010 1001 1000 0000 AC HL HL AC AC HL lt HL AC ADN HL 0010 1001 1100 0000 HL HLH AND Rx 0010 1010 lt Rx AND AC AND HL 0010 1010 10
70. EG20 DC20 0D20 SEG21 DC21 0D21 SEG22 DC22 0D22 SEG23 DC23 0D23 SEG24 IOAI CX SEG25 IOA2 RR SEG26 IOA3 RT SEG27 IOA4 RH SEG28 IOB1 SEG29 IOB2 SEG30 IOB3 BZB DC31 OD31 IOB4 BZ IOCI KII 2 12 IOC3 KI3 IOC4 KI4 IODI IOD2 IOD3 1004 SEG40 DC40 0D40 SEG41 DC41 OD41 RESET INT VPP Preliminary tenx technology inc Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver PIN DESCRIPTION Positive Back up voltage connect a 0 1u capacitor to GND Positive voltage is needed to BAK pin for Serial Program Read Mode Positive supply voltage Connect 3 0V battery positive pin to VDD2 Positive voltage is needed to VDD2 for Serial Program Read Mode LCD supply voltage and positive supply voltage Positive voltage is needed to VDD3 for Serial Program Read Mode Input pin from LSI reset request signal with internal pull down resistor Instruction Reset Time can select 15 2 PH12 2 by option Reset Type can select Level or Pulse by option Signal for Serial Program Read Mode Input pin for external INT request signal Falling edge or rising edge triggered by option Internal pull down or pull up resistor is selected by option Signal for Serial Program Read Mode Switching pins for supply the LCD driving voltage to the VDD1 VDD2 VDD3 pins Connect the and CUP2 pins with non polarized electrolytic capacitor if 1 2 or 1 3 bias mode has b
71. F4 occurs thus the TENX flag will be reset to 0 when the last HRF4 flag delivery After the last underflow HRF4 of TMR2 occurs disable the re load function by executing 2 1h instruction For example if the target set value is 500 it will be divided as 52 7 64 1 Set the initiate value of TMR2 to 52 and start counting 2 Enable the TMR2 halt release or interrupt function Before the first underflow occurs enable the re load function and set the DED flag The TMR2 will continue counting even if TMR2 underflows 4 When halt release or interrupt occurs clear the HRF4 flag by PLC instruction and increase counting value to count the underflow times When halt release or interrupt occurs for the 7 time reset the DED flag 6 When halt release or interrupt occurs for the 8 time disable the re load function and the counting is completed In the following example S W enters the halt mode to wait for the underflow of TM2 LDS 0 0 5 Initiate the underflow counting register PLC 10h 40 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver SHE 10h Enable the halt release caused by TM2 SRF 19h Enable RFC and controlled by TM2 TM2X 34h Initiate the TM value 52 and clock source is 9 SF2 3h Enable the re load function and set DED flag to 1 RE LOAD HALT INC 0 Increase the underflow counter PLC 10h Clear 4 LD
72. FREQ refer to section 3 3 4 13 2 RE LOAD OPERATION TMR2 also provides the re load function is the same as The instruction SF2 1 enables the re load function the instruction RF2 1 disables it 39 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 13 3 TIMER 2 TMR2 IN RESISTOR TO FREQUENCY CONVERTER RFC TMR2 also controls the operation of the RFC function TMR2 will set TENX flag to 1 to enable the RFC counter Once TMR2 underflows the TENX flag will be reset to 0 automatically In behaving this way Timer 2 can set an accurate time period without setting a value error like the other operations of TMR1 and TMR2 Refer to section 3 8 for more detail information on controlling the RFC counter The following figure shows the operating timing of TMR 2 in RFC mode Clock source of Timer 2 7 TM2X X 7 Content of 3Fh N 1 N 2 1 0 Timer2 LM LLL LLL WY HRF4 _ _ _ _ _ _ TMR2 also provides the re load function when controlls the RFC function The SF2 1h instruction enables the re load function and the DED flag should be set to 1 by SF2 2h instruction Once DED flag has been set to 1 TENX flag will not be cleared to 0 while TMR2 underflows but HRF4 will be set tol The DED flag must be cleared to 0 by executing RF2 2h instruction before the last HR
73. H 5 2 4h Turns off the LCD display RF2 4h Turns on the LCD display 96 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 3 3 THE CONFIGURATION of LCD RAM Area E Fs 12 cows DBUSC DBUSD DBUSG DBUSH m DBUSC DBUSD DBUSG DBUSH DBUSD SEG6 DBUSG DBUSH DBUSC DBUSD DBUSG DBUSH SEG9 DBUSC DBUSD 03H UM TM87P18M_E 4 Bit Microcontroller with LCD Driver 1 8 Duty gt E DBUSD DBUSH 2 DBUSD DBUSH DBUSD DBUSE DBUSF DBUSG DBUSH DBUSA DBUSB DBUSD SEG12 DBUSG DBUSH DBUSD SEG14 DBUSG DBUSH DBUSC DBUSD DBUSG DBUSH DBUSD SEGIS DBUSG DBUSH DBUSC DBUSD DBUSG DBUSH SEG19 skGI9 SEG22 DBUSG DBUSH DBUSC DBUSD DBUSG DBUSH DBUSD SEG26 DBUSG DBUSH DBUSC DBUSD DBUSG DBUSH DBUSC DBUSD SEG30 DBUSG DBUSH DBUSC DBUSD DBUSG DBUSH z 5 17 5 18 5 19 20 DBUSC SEG21 SEG22 SEG23 DBUSG X Duty 1 2 COM1 COM2 Duty 1 3 1 DBUSE DBUSF DBUSG DBUSH DBUSH DBUSD DBUSH DBUSD DBUSH DBUSD DBUSH DBUSD DBUSH DBUSD DBUSH DBUSD DBUSH DBUSD DBUSH DBUSD DBUSH DBUSD DBUSH DBUSD COM7 COMS DC7 OD7 DC8 OD8 5 DC5 OD5 COM6 DC6 OD6 DC9 OD9 SEG40 SEG41 Duty 1 8 8 97 Prelimina
74. Hz LJ 1 4 duty carrier out 1 3 duty carrier out 1 2 duty carrier out 1 1 duty carrier out 3 2 Melody APPLICATION The frequency generator may generate specified frequencies to compose melody music and the note table for those specified frequencies is shown below 1 The clock source is PHO 1 6 32 768 Hz 2 The duty cycle is 1 2 Duty D 2 3 FREQ is the output frequency 4 ideal is the ideal tone frequency 5 90 is the frequency deviation The following table shows the note table for melody application FREQ C2 249 655360 654064 019 C4 62 260 063 261 626 060 C2 D2 D4 198 82 3317 824069 0 09 F4 49 327 680 329628 050 0 18 2 F4 0 64 G 0 48 G2 1 16 0 64 A2 0 42 B 0 53 C3 1 01 C3 1 48 D3 0 37 D3 D5 1 27 E3 98 165 495 164 814 041 BS 24 655 360 659 255 0 59 F 1 99 F3 0 64 0 48 G3 1 37 2 01 69 234057 233082 042 A5 2 37 65 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver Note 1 The above variation does not include X tal variation 2 If PHO 65536 Hz C3 B5 may have more accurate frequency For the melody application the output signal of frequency generator has to be conveyed to the buzzer output BZB BZ in order to accomplish the whole function
75. IEF6 is set beforehand and interrupt 6 is accepted the instruction at address 28H will be executed automatically 57 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 1 2 INTERRUPT PRIORITY If all interrupts are requested simultaneously during a state when all interrupts are enabled the pre divider interrupt is given the first priority and other interrupts are held When the interrupt service routine is initiated all of the Interrupt Enable Flags IEFO IEF6 are cleared and should be set with the next execution of the SIE instruction Refer to Table 3 1 Example Assuming all interrupts are requested simultaneously and all interrupts are enabled beforehand all the IOC port pins are been defined as input mode PLC 7Fh Clear all of the HRF flags SCA 10h Enable the interrupt request of IOC SIE 7Fh Enable all interrupt requests All interrupts are requested simultaneously An interrupt caused by the predivider overflow occurs and the interrupt service is concluded SIE 77h Enable the interrupt request except the predivider An interrupt caused by TM1 underflow occurs and interrupt service 1s concluded SIE 75h Enable the interrupt request except the predivider and TMR1 An interrupt caused by TM2 underflow occurs and interrupt service 1s concluded SIE 65h Enable the interrupt request ex
76. IOD port Priority control circuit Timer TM underflow Interrupt Specified signal request change at INT pin signal Interrupt vector address generator Predivider overflow Interrupt 4 TM2 underflow Specified signal interrupt 5 enable at Key matrix Scanning RFC counter Interrupt 6 overflow Interrupt accept signal SIE instruction Initial clear tenx technology inc Rev 1 0 2012 10 05 56 Preliminary Advance Information 87 18 4 Bit Microcontroller with LCD Driver 1 1 RUPT REQUEST AND SERVICE ADDRESS 1 1 1 External Interrupt Factor The external interrupts are generated by the INT pin the IOC or IOD ports or Key matrix scanning function 1 2 3 External INT pin interrupt request In the mask option a rising edge or falling edge of the signal on the INT pin can be selected for generating an interrupt If the interrupt enable flag 2 IEF2 is set beforehand and a signal change on the INT pin matches the mask option it will generate a HRF2 the interrupt 2 Once the interrupt request is accepted and the instruction at address 10H will be executed automatically It is necessary to hold the signal level for at least 1 machine cycle after the signal edge changes port IOC IOD interrupt request An interrupt request signal HRFO will be generated when an input signal changes on the I O port IOC IOD matches what is specified by the SCA
77. NT pin can cause the stop mode to be released When the stop release enable flag 7 SRF7 and the 5 are set the H signal from OR ed output of K1 4 latch signals can cause the stop mode to be released 15 3 CONTROL REGISTER 3 CTL3 The Control register 3 CTL3 is composed of 7 bits of interrupt enable flags IEF to enable disable interrupts The interrupt enable flag IEF is set reset by the SIE instruction The bit pattern of control register 3 CTL3 is as shown below Interrupt enable flag TEF6 5 IEFA Enable the interrupt request Enable the interrupt request Enable the interrupt request Interrupt request flag caused by RFC function caused by Key Scanning caused by TMR2 underflow HRF6 HRF5 HRF4 Interrupt flag Interrupt enable flag IEF2 1 Enable the interrupt request Enable the interrupt request a Enable the interrupt request Interrupt request flag caused by predivider caused by INT pin HRF2 caused by underflow overflow HRF3 TENSE HRF1 Interrupt flag Interrupt enable flag Enable the interrupt request caused by IOC or IOD port ae HRFO Interrupt flag Interrupt 49 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver When any of the interrupts are accepted the corresponding HRFx and the interrupt enable flag IEF will be reset to 0 automat
78. ONS AND MEMORY MANIPULATION INSTRUCTION 110 3 OPERATION INSTRUCTIONS 112 4 LOAD STORE INSTRUCTION S 121 5 CPU CONTROL INSTRUCTION S 123 6 INDEX ADDRESS INSTRUCTION 126 7 DECIMAL ARITHMETIC INSTRUCTION S 127 S JUMP INSTRUCTIONS ERR usses tas 6 sosse ossessi sessies 128 9 MISCELLANEOUS INSTRUCTION S 130 Appendix TM87P18M Instruction Table 135 6 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver Chapter 1 General Description GENERAL DESCRIPTION The TM87P18M is a One Time PROM embedded high performance 4 bit microcontroller with LCD driver It contains all the following functions on a single chip 4 bit parallel processing ALU ROM RAM I O ports t
79. OR FOR 500 KHz CFOUT NC CFIN N C Internal RC FREQUENCY RANGE OF INTERNAL RC OSCILLATOR Option Mode BAK Min Typ Max 250 KHz 3 0V 200 KHz 250 KHz 300 KHz 500 KHz 3 0V 400 KHz 500 KHz 600 KHz 21 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information UM TM87P18M_E 4 Bit Microcontroller with LCD Driver 2 3 THE COMBINATION OF THE CLOCK SOURCES There are three types of combination of the clock sources that can be selected by mask option 2 3 1 Dual Clock MASK OPTION TABLE Mask Option name Selected Item CLOCK SOURCE 3 DUAL The operation of the dual clock mode is shown in the following figure When this mode is selected in mask option the clock source BCLK of the system clock generator will switch between the XT clock and the CF clock according to the user s program When the HALT and STOP instructions are executed the clock source BCLK will switch to the XT clock automatically The XT clock provides the clock signals to the pre divider the timer the I O port chattering prevention and the LCD circuitry in this mode Halt Halt mode lt XTOSC active CFOSC stop HALT released Stop released Power on reset Reset pin reset Watchdog timer reset Key reset Slow mode XTOSC active CFOSC stop 411 release Reset Reset state XTOSC active CFOSC stop Halt Slow Fast mod
80. P mode or the LED turn off mode is active During the initial reset cycle all the LED pixels will be turned off as defined in the default setting because turning on all the LED pixels will cause large current consumption the LED output data will keep their initial settings until LED related instructions are executed to change their settings in the program The waveform on the COM output and LED driver output for each LED lighting system are shown below 100 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver Example 1 5 DUTY LIGHTING SYSTEM FOR LED DRIVER i Initial reset cycle lighting VDD COM1 2 3 4 5 in low active GND VDD COM1 2 3 4 5 in high active GND VDD All LED driver outputs GND 101 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver ii Normal operation mode frame period eMe VDD COMI in Low active eee GND eMe VDD in Low active pm eee GND idus VDD COMS in Low active m eMe GND ee VDD in Low active ee GND eee VDD COMS5 Low active gun GND uis VDD COM in High active pawie eee GND VDD in High active GND VDD in High active Logis eee GND TE VDD
81. S 20h 7 SUB 0 When halt is released for the 7 time reset DED flag JNZ NOT RESET DED RF2 2 Reset DED flag NOT RESET DED LDA 0 Store underflow counter to AC JB3 END TMI If the TM2 underflow counter is equal to 8 exit this subroutine JMP RE LOAD END TMI RF2 1 Disable the re load function ad en Zh an TN HFA s T Filed LHO This figure shows the operating timing of TMR2 re load function for 41 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 14 STATUS REGISTER STS The status register STS is organized with 4 bits and comes in 4 types status register 1 STS1 to status register 4 STS4 The following figure shows the configuration of the start condition flags for TM87P18M IEFO PLC SIE 1h Chatterng prevention output of IOC SCF 1 HRFO J Interrupt 0 SEF4 SCA 10h Initial reset Halt cher Interrupt accep lease output of IOD request SEF3 SCF3 IEF1 SCA 8h SIE 20 1 underflow 1 SCF5 Interrupt 1 HEF1 SHE 2h IEF2 Signal m Interrupt 2 changed HRE2 r onIN
82. S sivcchuciieines iienaa oaiae a eiaa nae Rie 13 1 DC Output Character ie RT EY 13 5 Segment Driver Output Characteristics n a 14 TYPICAL APPLICATION CIRCUIT 15 Chapter 2 TM87P18M Internal System Architecture 16 1 POW GT SOUP MT 16 1 1 NO BIAS USING A Li BATTERY POWER SUPPLY 16 1 2 1 2 BIAS USING A Li BATTERY POWER 50 17 1 5 BIAS AT ti BATTERY POWER SUPPLY 18 2 SYSTEM COCA 19 2 1 CONNECTION DIAGRAM SLOW CLOCK OSCILLATOR XT CLOCK 19 2 2 CONNECTION DIAGRAM OF THE FAST CLOCK OSCILLATOR CF 20 2 2 1 RC oscillator with External Resistor connection diagram is shown below 20 2 2 2 External 3 58 MHz Ceramic Resonator Oscillator 21 2 2 3 Internal SB Att T C 21 2 3 THE COMBINATION OF THE CLOCK SOURCES 22 2 3 1 Dual
83. SISTOR 2 NO USE The low level hold device can not be selected individually in mask option without the pull low resistor The Low level hold function option Mask Option name Selected item C PORT LOW LEVEL HOLD 1 USE C PORT LOW LEVEL HOLD 2 NO USE 5 3 1 Chattering Prevention Function and Halt Release The port IOC is capable of preventing the chattering signals bounce applied on to IOC4 pins The de bounce time can be selected as PH10 32 ms PH8 8 ms or PH6 2 ms by executing a SCC instruction The default selection is PHIO after the reset cycle The following figure shows organization of chattering prevention circuitry Note The default prevention clock is PH10 The chattering prevention function will be invoked when the signal on the applicable pin e g IOC1 changes from L level to H level or from level to L level and the remaining pins e g IOC2 to IOC4 are held at L level When the signal changes on the IOC port pins in input mode specified by the SCA instruction and stays in that state for at least two chattering clock PH6 8 10 cycles the control circuit that operates upon the input pins will transmit a halt release request signal 5 At that time the chattering prevention clock will stop due to the
84. Selects timer 1 clock source and preset timer 1 Description The data specified by X X8 is loaded to timer 1 to start the timer The following table shows the bit pattern for this instruction The clock source setting for timer 1 TM2 Rx Function Selects timer 2 clock source and preset timer 2 Description The content of data memory specified by Rx and AC is loaded to timer 2 to start the timer The following table shows the bit pattern for this instruction OPCODE Select clock TM2 Rx AC ACO The clock source setting for timer 2 132 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 2 HL Function Selects timer 2 clock source and preset timer 2 Description The content of Table ROM specified by HL is loaded to timer 2 to start the timer The following table shows the bit pattern for this instruction OPCODE Select clock The clock source setting for timer 2 0 D PD 0 1 _ PH U 1 0 PHS TM2X X Function Selects timer 2 clock source and preset timer 2 Description The data specified by X X8 is loaded to timer 2 to start the timer The following table shows the bit pattern for this instruction The clock source setting for timer 2 SFX Function Sets flag Description Description of each flag 1 The CF is set to 1 X1 1 The chip enters backup mode and BCF
85. T pin N SCF4 HEF2 SHE 4h Interrupt 3 Predivid N SCF7 SHE 8h IEF4 SIE 10h Interrupt 4 underflow SCF6 HEF 4 SHE 10h IEF5 T nterr Key SIE 20h up Scanning HRF 5 d SCF7 overflow HEF5 SHE 20h 6 SIE 40h FRC counter HRF6 Interrupt 6 overflow DUM S EI SCF9 HEF6 SHE 40h 14 1 STATUS REGISTER 1 STS1 Status register 1 STS1 consists of 2 flags 1 Carry flag CF The carry flag is used to save the results of the carry or borrow during the arithmetic operation 2 Zero flag Z 42 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver Indicate the accumulator AC status When the content of the accumulator is 0 the Zero flag is set to 1 If the content of the accumulator is not 0 the zero flag is reset to 0 3 The MAF instruction transfers the data of the status register 1 STS1 to the accumulator AC and the data memory RAM 4 The MRA instruction transfers the data of the data memory RAM to the status register 1 STS1 The bit pattern of status register 1 STS1 is shown below Bit 3 Bit 2 BitO fag A Zote Read only Read only Read only 14 2 STATUS REGISTER 2 STS2 Status register 2 STS2 consists of start condition flag 1 2 3 SCF1 SCF2 SCF3 and the backup flag The MSB instruction transfers the data of the status r
86. The Start Condition Flag 7 SCF7 If the halt release enable flag 3 HEF3 is set beforehand the Start Condition Flag 7 SCF7 will be set when an overflow signal from the pre divider causes the halt release request flag 3 HRF3 to be output There are two methods to reset the Start Condition Flag 7 SCF7 one is to execute the PLC instruction to reset the halt release request flag 3 HRF3 and the other is to execute the SHE instruction to reset the halt release enable flag 3 HEF3 Contents of the pre divider on the 15th stage The MSC instruction is used to transfer the contents of the status register 3 STS3 to the accumulator AC and the data memory RAM The following table shows the Bit Pattern of Status Register 3 STS3 Bit 3 Bit 2 Bit 0 Start condition flag 7 15th stage of the Start condition flag 5 Start condition flag 4 SCF7 pre divider SCF5 SCF4 Halt release caused by Halt release caused by Halt release caused by pre divider overflow underflow INT Read only Read only Read only Read only 14 4 STATUS REGISTER STS3X When the halt mode is released with Start Condition Flag 2 SCF2 status register 3X STS3X will store the status of the factor in the release of the halt mode 44 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver The status register 3X STS3X consists of 3 flags
87. Use 111 tenx technology inc Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 3 OPERATION INSTRUCTIONS INC Rx Function Description INC HL Function Description INC HL Function Description DEC Rx Function Description DEC HL Function Description DEC HL Function Description ADC Rx Function Description Rx AC Rx 1 Adds 1 to the content of Rx the result is loaded to data memory Rx and AC The carry flag CF will be affected R HL AC R HL 1 Adds 1 to the content of data memory specified by 9 HL the result is loaded to data memory specified by HL and AC The carry flag CF will be affected HL AC lt R HL 1 HL HL 1 Adds 1 to the content of 9 HL the result is loaded to the data memory HL and The content of the index register HL will be incremented automatically after executing this instruction The Carry Flag CF will be affected HL indicates an index address of data memory Rx AC Rx 1 Substrates 1 from the content of Rx the result is loaded to data memory Rx and AC The Carry Flag CF will be affected R HL AC R HL 1 Substrates 1 from the content of data memory specified by HL the result is loaded to data memory specified by 9 HL and The Carry flag CF will be affected lt R HL 1 HL HL 1 Substrates 1 from the content
88. WR Rx HL Function SRO Rx Function Description SRI Rx Function SLO Rx Function 511 Function MRA Rx Function Description MAF Rx Function Preliminary AC Rx R HL HL 1 Description The content of the data memory specified HL is loaded to AC and the data memory specified by Rx The content of the index register HL will be incremented automatically after executing this instruction Rxn ACn Rx n 1 AC n 1 Rx3 0 The Rx content is shifted right and 0 is loaded to the MSB The result is loaded to the AC 0 Rx3 Rx2 Rx 50 Rxn ACn Rx n 1 AC n 1 Rx3 AC3 Description The Rx content is shifted right and 1 is loaded to MSB The result is loaded to the AC 1 Rx3 Rx2 Rxl 50 Rxn ACn lt Rx n 1 AC n 1 Rx0 ACO 0 Description The Rx content is shifted left and 0 is loaded to the LSB The results are loaded to the AC Rx3 Rx2 Rxl Rx0 0 Rxn ACn lt Rx n 1 AC n 1 Rx0 1 Description The Rx content is shifted left and 1 is loaded to the LSB The results are loaded to the AC Rx3 Rx2 Rxl Rx0 CF Rx 3 Bit3 of the content of Rx is loaded to Carry Flag CF AC Rx CF Description The content of CF is loaded to AC and Rx The content of AC and meaning of bit after execution of this instruction are as follows Bit 3 CF Bit 2 AC 0 zero flag Bit 1 Use Bit 0 No
89. X 110 activates K14 columns simultaneously X3X5X 111 activates K15 K16 columns simultaneously Xo is not a factor When 4 are selected as the Key matrix scanning input in mask option it is necessary to execute a SPC instruction to set the unused IOC port to output mode before the key matrix scanning function is activated Fig 2 27 shows the organization of the Key matrix scanning input port Once one of the KI1 4 pins detects the signal changes from Hi z to 1 TM87P18M will set HRF5 to 1 If HEF5 has been set to 1 beforehand it will cause SCF7 to be set and release the HALT mode After the key scanning cycle finishes the states of SKII 4 pins will be stored into the output latch of the IOC port Executing an IPC instruction can store these states into data RAM Executing a PLC 20h instruction can clear the HRF5 flag Since the key matrix scanning function steals a part of the LCD driving waveforms as the scanning output signal the scanning frequency is the same as the alternating clock frequency of the LCD The formula for the key matrix scanning frequency is shown below The key matrix scanning frequency Hz LCD frame frequency x LCD duty cycle x 2 Note 2 is a factor For example if the LCD frame frequency is 32 Hz and the duty cycle is 1 5 duty the scanning frequency for the key matrix will be 320 Hz 32 x 5 x 2 87 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance In
90. a memory The Carry Flag CF will be affected AC lt Rx AC Binary adds the contents of Rx and AC the result is loaded to AC The result will not affect the Carry Flag CF AC lt HL AC Binary adds the contents of 9 HL and AC the result is loaded to AC The result will not affect the Carry Flag CF HL indicates an index address of data memory AC HL AC HL HL 1 Binary adds the contents of HL and AC the result is loaded to AC The content of the index register HL will be incremented automatically after executing this instruction The result will not affect the Carry Flag CF HL indicates an index address of data memory AC Rx Rx AC Binary adds the contents of Rx and AC the result is loaded to AC and data memory Rx The result will not affect the Carry Flag CF Preliminary 116 tenx technology inc Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver ADN HL Function AC HL lt HL AC Description Binary adds the contents of HL and AC the result is loaded to AC and the data memory HL The result will not affect the Carry Flag CF HL indicates an index address of data memory ADN HL Function AC lt HL AC HL 1 Description Binary adds the contents of HL and AC the result is loaded to AC and the data memory HL The content of the index register HL will be
91. address of data memory LDS Rx D Function AC Rx D Description Immediate data D is loaded to the AC and data memory specified by Rx D 0H FH LDA Rx Function AC lt Rx Description The content of Rx is loaded to AC LDA HL Function AC lt R HL Description The content of data memory specified by HL is loaded to AC LDA HL Function HL HL HL 1 Description The content specified by HL is loaded to AC The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory LDH Rx HL Function Rx AC H T HL Description The higher nibble data of Table ROM specified by HL is loaded to data memory specified by Rx LDH Rx HL Function Rx lt H T HL 0HL HL 1 Description The higher nibble data of Table ROM specified by HL is loaded to data memory specified by Rx and then is increased in 9 HL LDL Rx HL Function Rx AC L T HL Description The lower nibble data of Table ROM specified by HL is loaded to the data memory specified by Rx LDL Rx HL Function AC lt L TQHL HL HL 1 Description The lower nibble data of Table ROM specified by HL is loaded to the data memory specified by Rx and then incremented the content of HL 123 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information UM TM87P18M_E 4 Bit Microcontroller with
92. ame frequency 2 FAST 85 Hz LCD frame frequency 2 0 Hz LCD is not used The LCD frame frequency in 1 4 duty type Mask Option name Selected item Frequency LCD frame frequency 1 SLOW 16 Hz LCD frame frequency 2 TYPICAL 32 Hz LCD frame frequency 2 FAST 64 Hz LCD frame frequency 2 0 Hz LCD is not used The LCD frame frequency in 1 5 duty type Mask Option name Selected item Frequency LCD frame frequency 1 SLOW 25 Hz LCD frame frequency 2 TYPICAL 51 Hz LCD frame frequency 2 FAST 102 Hz LCD frame frequency 2 0 Hz LCD is not used The LCD frame frequency in 1 6 duty type Mask Option name Selected item Frequency LCD frame frequency 1 SLOW 21 Hz LCD frame frequency 2 TYPICAL 42 Hz LCD frame frequency 2 FAST 85 Hz LCD frame frequency 2 O P 0 Hz LCD is not used 91 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver The LCD frame frequency in 1 7 duty type Mask Option name Selected item Frequency LCD frame frequency 1 SLOW 18 Hz LCD frame frequency 2 TYPICAL 36 Hz LCD frame frequency 2 FAST 73 Hz LCD frame frequency 2 O P 0 Hz LCD is not used The LCD frame frequency in 1 8 duty type Mask Option name Selected item Frequency LCD frame frequency
93. be affected lt HL HL HL 1 Binary subtracts the content of AC from the content of HL the result is loaded to AC The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory The Carry Flag CF will be affected Preliminary 115 tenx technology inc Rev 1 0 2012 10 05 Advance Information 87 18 SUB Rx Function Description SUB HL Function Description SUB HL Function Description ADN Rx Function Description ADN HL Function Description ADN HL Function Description ADN Rx Function Description 4 Bit Microcontroller with LCD Driver AC Rx lt Rx AC B 1 Binary subtracts the content of AC from the content of Rx the result is loaded to AC and Rx The Carry Flag CF will be affected HL HL AC B 1 Binary subtracts the content of AC from the content of the result is loaded to AC and the data memory HL HL indicates an index address of data memory The Carry Flag CF will be affected AC HL lt HL AC B 1 HL HL 1 Binary subtracts the content of AC from the content of 9 HL the result is loaded to AC and the data memory HL The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of dat
94. cept the predivider TMR1 and TMR2 An interrupt caused by RFC counter overflow occurs and interrupt service is concluded SIE 25h Enable the interrupt request except the predivider 2 and the RFC counter An interrupt is caused by IOC port and interrupt service is concluded SIE 24h Enable the interrupt request except the predivider TMR1 TMR2 RFC counter and IOC port An interrupt is caused by the INT pin and interrupt service is concluded SIE 20h Enable the interrupt request except the predivider TMR1 TMR2 RFC counter IOC port and INT An interrupt is caused by Key matrix Scanning and interrupt service is concluded All interrupt requests have been processed 58 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 1 3 INTERRUPT SERVICING When an interrupt is enabled the program in execution is suspended and the instruction at the interrupt service address is executed automatically Refer to Table 3 1 1 In this case the CPU performs the following services automatically 1 The value of the program counter PC right before the interrupt service begins is saved on the stack register STACK 2 The corresponding interrupt service routine address is loaded in the program counter PC The interrupt request flag corresponding to the accepted interrupt is reset and a
95. ch can be checked a by MSD instruction the 16 bit counter will stop counting when overflow occurs Mask Option name Selected item RFC OVERFLOW DISABLE COUNTER 1 USE RFC OVERFLOW DISABLE COUNTER 2 NO USE If NO USE is selected the RFOVF flag is only used as the 17th bit of the counter There are 3 operation modes for the 16 bit counter Each mode is described in the following sections Enable Disable the Counter by Software In this mode the clock source of the 16 bit counter is received from the CX pin and the counter is enabled disabled by the S W When the SRF 8h instruction is executed the counter will be enabled and will start to count the clocks from the CX pin The counter will be disabled when the SRF 0 instruction is executed Executing MRF1 4 instructions will load the content of the 16 bit counter into the specified data memory and AC Each time the 16 bit counter is enabled the content of the counter will be cleared automatically Example If you intend to count the number of clock from the CX pin for a time period you can enable the 16 bit counter by executing a SRF 8 instruction and setting the timerl to control the time period The overflow flag RFOVF of the 16 bit counter will be checked during the time period If the overflow flag is not set to 1 read the content of the counter directly if the overflow flag has been 81 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance I
96. ck source of TMR2 is PH7 If a watchdog reset occurs the clock source of TMR2 will remain the same The following table shows the definition of each bit in TMR2 instructions TM2R o AC3 AC ACT ACO rwzeHL o wu i Bi bio wio 38 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver The following table shows the clock source setting for TMR2 Notes n the TMR2 clock is PH3 TMR2 set time Set value error 8 1 fosc KHz ms When the TMR2 clock is PH9 TMR2 set time Set value error 512 1 fosc KHz ms When the TMR2 clock is PH15 TMR2 set time Set value error 32768 1 fosc KHz ms When TMR2 clock is PH5 TMR2 set time Set value error 32 1 fosc KHz ms When the timer clock is PH7 TMR2 set time Set value error 128 1 fosc KHz ms When the TMR2 clock is PH11 TMR2 set time Set value error 2048 1 fosc KHz ms When the TMR2 clock is PH13 TMR2 set time Set value error 8192 1 fosc KHz ms Set value Decimal number of timer set value error the tolerance of set value 0 lt error lt 1 fosc Input of the predivider PH3 3rd stage output of the predivider PHn nth stage output of the predivider n 5 7 9 11 13 When the TMR2 clock is FREQ TMR2 set time Set value error 1 FREQ KHz ms
97. data memory HL The content of the index register HL will be incremented automatically after executing this instruction When this instruction is executed the AC must be the result of any subtracted instruction The Carry Flag CF will be affected AC data before DAS CF data before DAS AC data after DAS CF data after DAS execution execution execution execution 0 AC 6 9 F 8 JUMP INSTRUCTIONS JBO X Function Description JB1X Function Description JB2X Function Description Program counter jumps to X if ACO 1 If bitO of AC is 1 jump occurs If 0 the PC is increased by 1 The range of X is from 000H to 7FFH or 800H to FFFH Program counter jumps to X if AC1 1 If bit of AC is 1 jump occurs If 0 the PC is increased by 1 The range of X is from 000H to 7FFH or 800H to FFFH Program counter jumps to X if AC2 1 If bit2 of AC is 1 jump occurs If 0 the PC is increased by 1 Preliminary 128 tenx technology inc Rev 1 0 2012 10 05 Advance Information JB3 X Function Description JNZ X Function Description JNCX Function Description JZ X Function Description JC X Function Description JMP X Function Description CALL X Function Description RTS Function Description Preliminary 87 15 E 4 Bit Microcontroller with LCD Driver The range of X is from 000H to 7FFH or 800H to FFFH Program c
98. e Frequency output Divider Generator FREQ SCC AC1 ACO FRQ DRX Rx3 Rx0 BCLK PHO Executing the SCC instruction can select the clock source for the frequency generator Executing the FRQ related instructions can set the output frequency and duty cycle of frequency generator The FRQ related instructions preset a scaling data N for the programming divider and a data D for setting the duty cycle and then the frequency generator starts to output the clock signals with the following formula FREQ clock source N 1 X Hz X 1 2 3 4 for 1 1 1 2 1 3 1 4 duty The scaling data N is preset by the content of data memory and the accumulator AC the table ROM data or the operand data specified in the FRQX instruction The following table shows the bit pattern of the combination The following table shows the bit pattern of the preset scaling data N The bit pattern of preset letter Programming divider Notes 1 T7 represents data of table ROM 2 X0 X7 represents the data specified in operand X The following table shows the bit pattern of the preset letter D Lo e meon 0 1 Bay 1 0 64 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver The following diagram shows the output waveform for different duty cycles clock source N 1
99. e XTOSC active fast CFOSC active Stop Reset Stop mode M XTOSC stop CFOSC stop The state diagram of the dual clock mode is shown the above figure After the execution of the FAST instructions the system clock generator will hold for 12 CF clock cycles after the CF clock oscillator starts up and then BCLK will switch to the CF clock It prevents the delivery of incorrect clock signals to the system clock in the start up duration of the fast clock oscillator Preliminary 22 tenx technology inc Rev 1 0 2012 10 05 87 18 Advance Information 4 Bit Microcontroller with LCD Driver e opr acrs This figure shows the System Clock Switching from Slow to Fast After executing SLOW instruction the system clock generator will hold for 2 XT clock cycles and then BCLK will switch to the XT clock Feet darkkaiqss quaerdirg EE This figure shows the System Clock Switching from Fast to Slow 2 3 2 Single Clock MASK OPTION TABLE For Fast clock oscillator only Mask Option name Selected item CLOCK SOURCE 1 FAST ONLY
100. e Information 87 18 10 11 12 13 14 15 16 17 4 Bit Microcontroller with LCD Driver Two 6 bit programmable timers with programmable clock source Watch dog timer LCD driver output 8 common outputs and 32 segment outputs drive up to 256 LCD segments 1 2 1 8 Duty for LCD LED 1 2 Bias or 1 3 Bias for LCD LED selected by option Single instruction to turn off all segments 5 8 DC9 OD9 SEG17 SEG23 DC31 OD31 5 40 SEG41 can be defined as CMOS P_open drain output type output in mask option 32 LCD address Built in Voltage doubler halve charge pump circuit Dual clock operation Slow clock oscillation can be defined as X tal or external RC type oscillator in mask option Fast clock oscillation can be defined as 3 58 MHz ceramic resonator internal in external type oscillator by mask option HALT function STOP function ROM code protect fuse 8 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver
101. e affected D 0H FH SUBI Ry Function AC Ry D 1 Description D represents the immediate data Binary subtracts the immediate data D from the working register Ry the result is loaded to AC The Carry Flag CF will be affected D 0H FH SUBI Ry D Function AC Ry Ry Y 1 Description D represents the immediate data Binary subtracts the immediate data D from the working register Ry the result is loaded to AC and the working register Ry The Carry Flag CF will be affected D 0H FH ADNI Function AC Ry D Description D represents the immediate data Binary ADDs the contents of Ry and D the result is loaded to AC The result will not affect the Carry Flag CF D 0H FH ADNI Ry D Function AC Ry Ry D Description D represents the immediate data Binary ADDs the contents of Ry and D the result is loaded to AC and the working register Ry The result will not affect the Carry Flag CF D 0H FH 120 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 ANDI D Function Description D 0H FH ANDI Ry D Function Description D 0H FH EORI Ry D Function Description D 0H FH EORI Ry D Function Description D 0H FH ORI Ry D Function Description D 0H FH ORI Ry D Function Description D 0H FH 4 Bit Microcontroller with LCD Driver AC Ry amp
102. e previous section the CX clock is used as the clock source for the 16 bit counter using the S W or TMR2 to produce a time period to control the counter In this mode however the 16 bit counter operates differently The clock signal on the CX pin turns into the controlled signal to enable disable the 16 bit counter and the clock source of the 16 bit counter coming from the output of the frequency generator FREQ When the 16 bit counter is enabled it will count the clock FREQ after the first rising edge signal applies to the CX pin Once the second rising edge applies to the CX pin after the counter is enabled a halt release request HRF6 will be delivered and the 16 bit counter stops counting In this case if the Interrupt Enable Flag 6 IEF6 is set the interrupt will be accepted and if the halt release enable flag 6 HEF6 is set the halt release request signal will be delivered to set the start condition flag 9 SCF9 in the status register 4 STS4 Each time the 16 bit counter is enabled the content of the counter will be cleared automatically SRF SRF T SRF control Enable counter CX Content of the counter 0 X 1X 2X3 NI XNX NH FREQ HALT released request Counter starts to count Counter stops caused by the 2nd falling edge This
103. e re load function is disabled For example if the expected count down value is 500 it may be divided as 52 7 64 First set the initial count down value of TMRI to 52 and start counting then enable the halt release or interrupt function Before the first underflow occurs enable the re load function TMR1 will continue operating even though TMR1 underflow occurs When a halt release or an interrupt occurs clear the 1 flag by executing PLC instruction After a halt release or an interrupt occurs 8 times disable the re load function and then the counting is completed 36 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information UM TM87P18M_E 4 Bit Microcontroller with LCD Driver p ad ad ah ah 7th art cart cart curt cart cart cut HA In the following example S W enters the halt mode to wait for the underflow of TMR1 RE_LOAD END TMI 105 0 0 PLC 2 SHE 2 TMSX 34h SF 80h HALT INC 0 PLC 2 JB3 END TMI JMP LOAD RF 80h Initiate the underflow counting register Enable the HALT release caused by TMR1 Initiate the TMRI value 52 and clock source is 9 Enable the re load function Increase the underflow counter Clear HRF1 If the TMR1 underflo
104. een selected In no BIAS mode these pins should be open Low speed oscillator generates clock for time base functions clock specified LCD alternating frequency Alarm signal frequency or system clock oscillation 32KHz Crystal oscillator for Slow Clock High speed oscillator system clock oscillation for FAST clock only or DUAL clock operation The usage of 3 58 MHz ceramic resonator oscillator or external R type oscillator is defined by mask option Output pins for driving the common pins of the LCD or LED panel 5 8 is muxed with DC Open Drain and set mask option DC Open Drain SEGI 30 40 41 O Output pins for driving the LCD or LED panel segment This port is muxed with SEG24 27 and set by option Input Output port B can use software to define internal pull low Resistor This port is muxed with SEG28 30 DC31 BZB BZ and set by option Input Output port C can use software to define internal pull low low level hold Resistor 10 1 4 and Chattering clock to reduce input bounce This port is muxed with KI1 4 and set by option wass IOD1 4 clock to reduce input bounce 1 input pin and 3 output pins for RFC application RR RT RH O This port is muxed with SEG24 27 IOA1 4 and set by option ALM Output port for alarm frequency or melody generator BZB BZ This port is muxed with SEG 30 DC 31 IOB3 4 and set by option This port is muxed with IOC1 4 and set by option OOOO i
105. egister 2 STS2 to the accumulator AC and the data memory RAM and the status register 2 STS2 is read only The following table shows the bit pattern of each flag in status register 2 STS2 Bit 3 Bit 2 Bit 0 Start condition flag 3 Start condition flag 2 Start condition flag 1 Backup flag SCF3 5 2 5 1 Halt release caused the Halt release caused by Halt release caused by The backup mode IOD port SCF4 5 6 7 9 the IOC port status Read only Read only Read only Read only Start Condition Flag 3 5 When a signal change occurs on port IOC due to the execution of SCA instruction to and the halt mode is released as a result SCF3 will be set Executing the SCA instruction will cause SCF3 to be reset to 0 Start Condition Flag 1 SCF1 When a signal change occurs on port IOC due to that the execution of SCA instruction and the halt mode is released as a result SCF1 will be set Executing the SCA instruction will cause SCF1 to be reset to 0 Start Condition Flag 2 SCF2 When factors other than port IOA and IOC cause the halt mode to be released SCF2 will be set to 1 Also if one or more start condition flags in SCF4 5 6 7 9 are set to 1 SCF2 will be set to 1 synchronously When all of the flags in SCF4 5 6 7 9 are cleared the start condition flag 2 5 2 18 reset to 0 Note If the start condition flag is set to 1 the program will not be able to enter the halt mode Backup Flag
106. er with LCD Driver Advance Information The meaning of each bit of X X4 X3 X2 X1 X0 is shown below Bit pattern Setting Bit pattern Setting Enables all of the pull low and Disables all of the pull low and X4 1 disables the low level hold X4 0 enables the low level hold devices devices OPC Rx Function Rx Description The content of Rx is output to I OC port IPC Rx Function Rx AC IOC Description The data of I OC port is loaded to AC and data memory Rx SPD X Function Defines the input output mode of each pin for IOD port and enables or disables the pull low device Description Sets the I O mode and turns the pull low device on or off The meaning of each bit of X X4 X3 X2 X1 X0 1s shown below Bit pattern Setting Bit pattern Setting 4 1 Enable the pull low device on X4 0 Disable the pull low device on IOD1 IOD4 simultaneously IOD1 IOD4 simultaneously OPD Rx Function I OD Rx Description The content of Rx is output to I OD port IPD Rx Function Rx AC I OD Description The data of the I OD port is loaded to AC and data memory Rx SPKX X Function Sets the Key matrix scanning output state Description When 5 1 16 is are used for LCD driver pin s set X X7 0 to specify the key matrix Preliminary scanning output state for each SEGn pin in the scanning interval X 0 when HEFS is set to 1 the HALT released request HRF5 will be set to 1 af
107. executing this instruction When this instruction is executed the AC must be the result of any added instruction The Carry Flag CF will be affected AC data before DAA CF data before DAA AC data after DAA CF data after DAA execution execution execution execution 0 9 6 0 3 6 DAS Function AC BCD AC 127 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 Description DAS Rx Function Description DAS HL Function Description DAS HL Function Description 4 Bit Microcontroller with LCD Driver Converts the content of AC to binary format and then restores to AC When this instruction is executed the AC must be the result of any subtracted instruction The Carry Flag CF will be affected AC Rx BCD AC Converts the content of AC to decimal format and then restores to AC and data memory specified by Rx When this instruction is executed the AC must be the result of any subtracted instruction The Carry Flag CF will be affected HL BCD AC Converts the content of AC to binary format and then restores to AC and the data memory HL When this instruction is executed the AC must be the result of any subtracted instruction The Carry Flag CF will be affected HL BCD AC HL HL 1 Converts the content of AC to binary format and then restores to AC and the
108. fied by HL AC and CF are binary added the result is loaded to AC and data memory specified by HL The Carry Flag CF will be affected AC HL lt HL AC CF HL HL 1 Binary adds the contents of HL AC and CF the result is loaded to AC and the data memory HL The content of the index register HL will be incremented automatically after executing this instruction The Carry Flag CF will be affected HL indicates an index address of data memory AC lt Rx The contents of AC and CF are binary subtracted from content of Rx the result is loaded to AC The Carry Flag CF will be affected Preliminary 113 tenx technology inc Rev 1 0 2012 10 05 Advance Information SBC HL Function Description SBC HL Function Description SBC Rx Function Description SBC HL Function Description SBC HL Function Description ADD Rx Function Description ADD HL Function Description Preliminary UM TM87P18M_E 4 Bit Microcontroller with LCD Driver AC R HL AC B CF The contents of AC and CF are binary subtracted from content of data memory specified by HL the result is loaded to AC The carry flag CF will be affected HL AC B CF HL HL 1 Binary subtracts the contents of AC and CF from the content of HL the result is loaded to AC The content of the index register HL will be incremented automatically after executi
109. formation 87 18 4 Bit Microcontroller with LCD Driver KH C key scanning SKI1 input amp latch Ign gt bit0 key scanning SKI2 input amp latch gt biti KSI N SKI Data Bus key scanning 5 13 x bit2 Rising edge strobe key scanning 5 ad input amp latch 2 5 R gt J bit3 PLC 20h L key scanning Initial Reset enable signal IPC Interrupt 5 request This figure shows the organization of Key matrix scanning input Example SPC Ofh Disable all the pull down devices on the internal IOC port Set all the IOC pins as the output mode SPKX 10h Generate a HALT release request when key is depressed Scan every column simultaneously in each cycle PLC 20h Clear Flag HRF5 SHE 20h Set HEFS HALT Wait for the halt release caused by the key matrix MCX 10h Check SCF8 5 1 JBO ski_release 88 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information ski_release IPC 10h JBO kil_release JB1 ki2_release JB2 ki3_release JB3 ki4_release kil_release SPKX 40h PLC 20h CALL wait_scan_again IPC 10h kil segl SPK 4fh PLC 20h CALL wait_scan_again IPC 10h JBO kil_seg16 wait_scan_again HALT PLC 20h RTS UM TM87P18M_E 4 Bit Microcontroller with LCD Driver Read the KI1 4 input latch state Check if the key depressed on K1 colu
110. h LCD Driver 3 2 Relative Instructions 1 Lz Ry Decodes the content specified in Ry with the data decoder and transfers the DBUSA H to the LCD latch specified by Lz LCB Lz Ry Decodes the content specified in Ry with the data decoder and transfers the DBUSA H to the LCD latch specified by Lz DBUSA to DBUSH are all set to 0 when the input data of the data decoder is 0 LCD Lz HL Transfers the table ROM data specified by HL directly to DBUSA through DBUSH without passing through the data decoder The mapping table is shown in table 4 3 4 LCP Lz The data in the RAM and accumulator AC are transferred directly to DBUS and stores the DBUS data into the latch circuit specified by Lz The mapping table is shown in table 4 3 4 LCT Lz HL Decodes the index RAM data specified in HL with the data decoder and transfers DBUSA H to the LCD latch specified by Lz LCB Lz HL Decodes the content specified in index RAM HL and stores the DBUS data into the LCD latch circuit specified by Lz All the DBUS data will be 0 when the input data of the data decoder is 0 LCP Lz HL The content of the index RAM HL and accumulator AC are transferred directly to DBUS and stores the DBUS data into the latch circuit specified by Lz The mapping table is shown below Table 4 3 4 The mapping table of LCP and LCD instructions DBUSA DBUSB DBUSC DBUSD DBUSE DBUSF DBUSG DBUS
111. h to 7FFh and page 1 covers 800h to FFFh 27 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver Both instruction ROM PROM and table ROM TROM share this memory space together The partition formula for PROM and TROM is as shown below Instruction ROM memory space 2048 128 N words Table ROM memory space 256 16 N bytes N 0 16 Note The data width of the table ROM is 8 bit The partition of memory space is defined by mask option the table is shown below MASK OPTION table Instruction ROM Table ROM memory Mask Option name Selected item memory space space Words Bytes INSTRUCTION ROM TABLE ROM 1 N20 2048 4096 INSTRUCTION ROM TABLE ROM 2 1 2176 3840 INSTRUCTION ROM lt gt TABLE ROM 3 N 2 2304 3584 INSTRUCTION ROM lt gt TABLE ROM 4 N 3 2432 3328 INSTRUCTION ROM lt gt TABLE ROM 5 N24 2560 3072 INSTRUCTION ROM TABLE ROM 6 N25 2688 2816 INSTRUCTION ROM TABLE ROM 7 6 2816 2560 INSTRUCTION ROM lt gt TABLE ROM 8 N 7 2944 2304 INSTRUCTION ROM lt gt TABLE ROM 9 N 8 3072 2048 INSTRUCTION ROM lt gt TABLE ROM A N 9 3200 1792 INSTRUCTION ROM lt gt TABLE ROM N 10 3328 1536 INSTRUCTION ROM lt gt TABLE ROM C N 11 3456 1280 INSTRUCTION ROM lt gt
112. he Halt mode the stop mode and the execution of the SLOW instruction will stop this oscillator and the system clock BCLK will be switched to the XT clock There are 3 types of oscillators that can be used as the fast clock oscillator which can be selected in mask option 2 2 1 RC oscillator with External Resistor connection diagram is shown below MASK OPTION TABLE Mask Option name Selected item FAST CLOCK TYPE FOR FAST ONLY OR DUAL 3 EXTERNAL RESISTOR CFOUT R CFIN External Resistor 20 tenx technology inc Preliminary Rev 1 0 2012 10 05 87 18 Advance Information 4 Bit Microcontroller with LCD Driver 2 2 2 External 3 58 MHz Ceramic Resonator Oscillator MASK OPTION TABLE Mask Option name Selected item FAST CLOCK TYPE FOR FAST ONLY OR DUAL 4 3 58 MHz Ceramic Resonator CFOUT C CFIN JE 3 58MHz Ceramic Resonator Notes 1 If it is required to reset to 0 in Li battery power mode do not use 3 58 MHz Ceramic Resonator as the oscillator 2 2 3 Internal RC Oscillator MASK OPTION TABLE For 250 KHz output frequency Mask Option name Selected item FAST CLOCK TYPE FOR FAST ONLY OR DUAL 1 INTERNAL RESISTOR FOR 250 KHz For 250 KHz output frequency Mask Option name Selected item FAST CLOCK TYPE FOR FAST ONLY OR DUAL 2 INTERNAL RESIST
113. hen set the start condition flag 5 SCF5 to 1 in the status register 3 STS3 After power on reset the default clock source of TMR1 is PH3 If watchdog reset occurs the clock source of TMR1 will still keep the previous selection The following table shows the definition of each bit in TMRI instructions TMSRx o acz ACI ACO Rxl o bi bw bis Bia bio bii bio The following table shows the clock source setting for TMR1 Notes 1 nthe TMRI clock is PH3 set time Set value error 8 1 fosc KHz ms 2 When TMR clock is PH set time Set value error 512 1 fosc KHz ms 3 When the TMRI clock is PH15 set time Set value error 32768 1 fosc KHz ms 4 When TMRI clock is PH5 TMRI set time Set value error 32 1 fosc KHz ms 5 When the TMRI clock is PH7 35 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 1 set time Set value error 128 1 fosc KHz ms 6 When the TMRI clock is PH11 TMRI set time Set value error 2048 1 fosc KHz ms 7 When the TMRI clock is PH13 1 set time Set value error 8192 1 fosc KHz ms Set value Decimal number of timer set value error the tolerance of set value 0 lt error 1 fosc Input of the predivider
114. ibition Refer to section 2 16 1 1 48 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 15 2 CONTROL REGISTER 2 CTL2 The Control register 2 CTL2 consists of halt release enable flags 1 2 3 4 5 6 2 3 4 5 6 and is set by the SHE instruction The bit pattern of the control register CTL2 is shown below Halt release enable flag HEF6 HEF5 HEF4 Enable the halt release Enable the halt release Enable the halt release Halt release condition caused by RFC counter to caused by Key caused by TMR2 underflow be finished HRF6 Scanning HRF5 HRF4 Halt release enable flag HEF3 HEF2 HEFI Enable the halt release Enable the halt release i n Enable the halt release Halt release condition caused by pre divider caused by INT pin HRF2 caused by TM1 underflow overflow HRF3 SENAP 1 When the halt release enable flag 6 HEF6 is set the stop signal from the 16 bit counter of RFC causes the halt mode to be released In the same manner when HEF to HEF4 are set to 1 the following conditions will cause the halt mode to be released respectively an underflow signal from TMRI the signal change at the INT pin an overflow signal from the pre divider and an underflow signal from TMR2 and a H signal from OR ed output of KI1 4 latch signals When stop release enable flag 5 SRF5 and the are set a signal change on the I
115. ically Therefore the desirable interrupt enable flag IEFx must be set again before exiting from the interrupt routine 15 4 CONTROL REGISTER 4 CTL4 The Control register 4 CTL4 is a 3 bit register It is set reset by the SRE instruction The following table shows the Bit Pattern of the Control Register 4 CTL4 Stop release enable flag SRF7 SRF5 SRF4 SRF3 Enable the stop release Enable the stop release Enable the stop release Stop release request flag request caused by signal request caused by signal request caused by signal change on KI1 4 SKI change on INT pin HRF2 change on IOC IOD When the stop release enable flag 7 SRF7 is set to 1 an input signal change on the pin KI1 4 will cause the stop mode to be released In the same manner when SRF4 SRF3 and SRF5 are set to 1 an input signal will change on the IOC IOD port pin in input mode and a signal change on the INT pin will cause the stop mode to be released as well Example This example illustrates the stop mode released by the port IOC 4 and INT pins Assuming all the IOD and IOC pins have been defined as input mode PLC 25h Reset the HRF2 and 5 SHE 24h Set HEF2 and HEFS the signal change on INT or KI1 4 pin will cause the start condition flag 4 or 8 to be set SCA 10h Set SEFA the signal change on port IOC will cause the start conditions 5 1 to be set SRE ObOh SRF7 5 4 are set so that the signal changes on KI1
116. icrocontroller with LCD Driver 4 LCT LCB LCP 9 ACCUMULATOR AC The accumulator AC is a register that plays the most important role in operations and controls By using it in conjunction with the ALU Arithmetic and Logic Unit data transfer between the accumulator and other registers or data memory can be performed 10 ALU Arithmetic and Logic Unit This is a circuitry that performs arithmetic and logic operation The ALU provides the following functions Binary addition subtraction INC DEC ADC SBC ADD SUB ADN ADCI SBUI ADNI Logic operation AND EOR OR ANDI EORI ORI Shift SRO SR1 SLO SL1 Decision JBO JB1 JB2 JB3 JC INC JZ and JNZ BCD operation DAA DAS 11 HEXADECIMAL CONVERT TO DECIMAL HCD Decimal format is another number format for TM87P18M When the content of the data memory has been assigned as decimal format it is necessary to convert the results to decimal format after the execution of ALU instructions When the decimal converting operation is processing all of the operand data including the contents of the data memory RAM accumulator AC immediate data and look up table should be in the decimal format or the results of conversion will be incorrect Instructions DAA DAA DAA HL can convert the data from hexadecimal to decimal format after any addition operation The conversion rules are shown in the following table and illustrated in example 1 AC data before DAA CF
117. imer clock generator dual clock operation Resistance to Frequency Converter RFC LCD driver look up table watchdog timer and key matrix scanning circuitry FEATURES 1 Powerful instruction set 173 instructions Binary addition subtraction BCD adjusts logical operation in direct and index addressing mode Single bit manipulation set reset decision for branch Various conditional branches 16 working registers and manipulation Table look up LCD driver data transfer 2 Memory capacity Program ROM capacity 4096 16 bits Data RAM capacity 512 x 4 bits 3 Input output ports Port IOA 4 pins with internal pull low muxed with SEG24 SEG27 Port IOB 4 pins with internal pull low muxed with SEG28 SEG30 DC31 Port IOC 4 pins with internal pull low low level hold chattering prevention clock Port IOD 4 pins with internal pull low chattering prevention clock 4 8 1 1 subroutine nesting Interrupt function External factor 4 INT pin Port IOC IOD amp KI input Internal factor 4 Pre Divider Timerl Timer2 Built in Alarm Frequency or Melody generator BZB BZ Muxed with IOB3 SE30 IOB4 DC31 Built in R to F Converter circuit CX RR RT RH Muxed with IOA1 IOA4 SEG24 SEG27 9 Built in KEY BOARD scanning function K1 K16 Share with SEGI SEGI6 KII KIA Muxed with IOC1 IOC4 7 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advanc
118. ing output state Description When SEG1 16 is are used for LCD driver pin s sets the content of table ROM HL to specify the key matrix scanning output state for each SEGn pin in the scanning interval The bit setting is the same as the SPKX instruction The bit pattern of the table ROM corresponding to SPKX is shown below Instruction Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bitl 0 SPK HL T HL 7 T HL 6 T HL 5 T HL 4 T HL 3 T HL 2 TeHL 1 TeHL O SPKX X 7 6 5 4 X3 X2 X1 Function Sets buzzer output frequency Description The waveform specified by X X8 is delivered to the BZ and BZB pins The output Preliminary frequency could be any combination in the following table The bit pattern of X for higher frequency clock source Clock Source Higher Frequency FREQ Lo 1 o o DI Pp 1 1 ePHGKH O 1 0 49 PHQOKH O 0 1 PHS KH 0 0 DC The bit pattern of X for lower frequency clock source 12 8 Hz 16 Hz PH10 32 Hz Notes 1 FREQ is the output of the frequency generator 2 When the buzzer output does not need the envelope waveform X5 should be set to 0 3 The frequency inside is based on the is 32768 Hz 109 tenx technology inc Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Drive
119. is executed or in the initial reset cycle The pre divider delivers the signals to the halver tripler circuit LCD driver sound generator and the I O port chattering prevention function Frequency Interrupt reque e HEF3 Halt mode BCLK 7 Initial FAST instruction T1 T2 T3 T4 Sclk PLC 8H FAST instruction Interrupt HALT release Clock Fall edge Oars request flag switch detector XTOSC circul MSC instructit em C Data bus 2 OC CFOSC Wawa To timer circuit circuit PLC 100H initial R TR Single clock option Dual clock option o I jt ir PH1 PH13 PH14 LM To sound circuit tribler circuit This figure shows the Pre divider and its Peripherals The falling edge of PH14 will set the halt mode release request signal flag HRF3 in this case if the pre divider interrupt enable mode IEF3 is set in advance the interrupt coming from predivider is accepted and if the halt release enable mode HEF3 is set in advance then the halt release request signal will be delivered and the start condition flag 7 SCF7 in status register 3 STS3 will be set The clock source of the pre divider is PHO there are 4 kinds of frequencies of PHO that can be selected in mask option MASK OPTION TABLE Mask Option name Selected item BCLK FOR FAST ONLY 1 PHO BCLK BCLK FOR FAST ONLY 2 PHO BCLK 4 PHO lt gt BCLK FOR
120. is set to 1 X4 1 The watchdog timer is initiated and active XT 1 Enables the re load function of timer 1 X6 5 is reserved RF X Machine code 1111 0100 X700X4 00 1 Function Resets flag Description Description of each flag 1 The CF is reset to 0 X1 I The chip is out of backup mode and is reset to 0 X4 1 The watchdog timer is inactive XT 1 Disables the re load function of timer 1 X6 5 3 is reserved 133 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 SF2 X Function Description RF2 X Function Description PLC Function 4 Bit Microcontroller with LCD Driver Sets flag Description of each flag X4 1 Enables low battery detected function X3 1 Enables INT powerful pull low X2 1 Disables the LCD segment output X1 1 Sets the DED flag Refer to 2 12 3 for detail 1 Enables the re load function of timer 2 X7 6 is reserved Resets flag Description of each flag X4 1 Disables low battery detected function X3 1 Disables INT powerful pull low X2 1 Enables the LCD segment output X1 I Resets the DED flag Refer to 2 12 3 for detail X0 1 Disables the re load function of timer 2 X7 6 is reserved Pulse control Description The pulse corresponding to the data specified by X is generated X0 1 Halt release request flag HRFO caused by the signal at I O port C is
121. ith LCD Driver CONTENTS AMENDMENT HISTORY u sccsceoscaswedsnennesasenssnasesscoeshoncdansdes 2 Chapter 1 General Description 7 GENERAL DESCRIPTION 7 FEATURES siseses iecit siuos user eies 7 BLOCK DIAGRAM bassas ssis osons 9 10 PIN DESCRIPTION PUER PEOR UHR DIR SARUM NOE 11 CHARACTERIZATION 12 1 obi ies tree e edm 12 2 POW ER CONSUMPTION Ex GR pow ave ds 12 3 ALLOWABLE OPERATING CONDITIONS i rsscrnsstuckontecen penguin Fere s planus 12 4 ALLOWABLE OPERATING FREQUENCY 13 5 INTERNAL RC FREQUENCY RANGE 13 6 ELECTRICAL CHAR AC TER U5 CIC
122. k register are returned sequentially to the program counter PC while executing return instructions RTS The stack register is organized using 11 bits by 8 levels but with no overflow flag hence only 8 levels of subroutine call or interrupt are allowed If the stacks are full and either interrupt occurs or subroutine call executes the first level will be overwritten Once the subroutine call or interrupt causes the stack register STACK overflow the stack pointer will return to 0 and the content of the level 0 stack will be overwritten by the PC value The contents of the stack register STACK are returned sequentially to the program counter PC during execution of the RTS instruction Once the RTS instruction causes the stack register STACK underflow the stack pointer will return to level 7 and the content of the level 7 stack will be restored to the program counter The following figure shows the diagram of the stack Stack pointer CALL instruction Interrupt gccepted RTS instruction STACK ring with first in last out function 31 tenx technology inc Preliminary Rev 1 0 2012 10 05 87 18 Advance Information 4 Bit Microcontroller with LCD Driver 7 DATA MEMORY RAM The static RAM is organized with 512 addresses x 4 bits and is used to store data The data memory may be accessed using two methods 1 Direct addressing mode The address of the data memory is specified by the instructi
123. l Reset Once an H signal is applied on the RESET pin TM87P18M will not enter the initial reset cycle until the signal on the RESET pin is return to 0 Once the signal applied on the reset pin returns to 0 TM87P18M launches the initial reset cycle immediately MASK OPTION table Mask Option name Selected item RESET PIN TYPE 1 LEVEL 2 2 2 Pulse Reset Once a 1 signal is applied on the RESET pin TM87P18M will escape from reset state and begin the normal operation after internal reset cycle automatically no matter whether the signal on RESET pin returns to O or not MASK OPTION table Mask Option name Selected item RESET PIN TYPE 2 PULSE The following table shows the initial condition of TM87P18M in reset cycle Program counter PC Address 000H Start condition flags 1 to 7 8 1 7 0 Backup flag BCP Stop release enable flags 4 5 7 SRF3 4 5 7 lO Switch enable flags 4 SEF3 4 Halt release request flag HRF 0 6 Halt release enable flags 1 to 3 HEF 1 6 lO Interrupt enable flags 0 to 3 IEF0 6 Alarm output ALARM DCO Pull down flags in I OD port 1 with pull down resistor Input output ports PORT I OB Input mode I OD I OD I OD port chattering clock Cch PH10 Frequency generator clock source and Cf PHO duty cycle is 1 4 output is duty cycle q inactive Timer 1 2 Watchdog timer WDT
124. lag CSF Clock Source Flag Ctm 1 Source of Timer Program Page Pre Divider RFOVF Overflow Flag STACK Content of stack RFC Resistor to Frequency counter Timer 1 RFC n Bit data of Resistor to Frequency counter TM2 Timer2 Preliminary 141 tenx technology inc Rev 1 0 2012 10 05
125. ll other interrupt enable flags are also cleared When an interrupt occurs the TM87P18M will follow the procedure below Instruction 1 An interrupt is accepted by the MCU NOP Store the address of Instruction 1 into the STACK the current program is suspended and insert a NOP instruction cycle Instruction A The program jumps to the interrupt service routine Instruction B Instruction C RTS Finish the interrupt service routine Instruction 15 Re execute the instruction 1 which is interrupted Instruction 2 Note If instruction 1 is the halt instruction the MCU will return to halt mode after interrupt When an interrupt is accepted all interrupt enable flags are reset to 0 and the corresponding flag will be cleared the Interrupt Enable Flags IEF can be set again in the interrupt service routine if required 59 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 2 RESET FUNCTION UM TM87P18M_E 4 Bit Microcontroller with LCD Driver TM87P18M contains four reset sources power on reset RESET pin reset IOC port reset and watchdog timer reset When reset signal is accepted TM87P18M will generate a time period for internal reset cycle and there are two types of internal reset cycle time could be selected by mask option the one is PH15 2 and the other is PH12 2 Reset signal System clock
126. llustrated by the timing chart below wale ale el eal eRe em L L 101 1 gt lt t EdL bc If the 1 pin is defined as the CX pin for the function and the other pins IOA2 IOA3 are used as normal IO pins in mask option the IOA1 function must be set as output mode in the begining of program to prevent the signal change on the CX pin getting into the IOAT function within input mode On the other hand the function cannot change the output signal within output mode because the output signal of IOA1 function will affect the counting of RFC counter through the CX pin when the RFC function is enabled 71 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 5 2 IOB PORT pins are MUXed with SEG28 SEG29 BZB SEG30 and BZ DC31 pins respectively mask option MASK OPTION table Mask Option name Selected item SEG28 IOB 1 2 IOB1 SEG29 IOB2 2 IOB2 SEG30 IOB3 BZB 2 IOB3 DC31 IOBA BZ 2 IOB4 The following figure shows the organization of IOB port Initial clear SPB 1 Initial clear SPB 2 Initial clear SPB 8 SPB IOA Pull low option Note The pins in the input mode should not be in floating or a large current straight through curren
127. lt release caused by The Backup mode status the IOD port SCF4 5 6 7 8 9 the IOC port in TM87P18M MSC Rx Function AC lt SCFA 7 Description SCF4 to SCF7 contents are loaded to AC and the data memory specified by Rx The content of AC and meaning of bit after execution of this instruction are as follows Bit 3 Bit 2 Bit 0 Start Condition Flag 7 The content of 15th stage Start Condition Flag 5 Start Condition Flag 4 SCF7 of the predivider SCF5 SCF4 Halt release caused by Halt release caused Halt release caused by INT predivider overflow TM1 underflow pin MCX Rx Function AC Rx SCF8 SCF6 SCF9 Description The SCF8 SCF6 SCF9 contents are loaded to AC and the data memory specified by Rx 125 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver The content of AC and meaning of bit after execution of this instruction are as follows Bit 3 Bit 2 Bit 0 Start Condition Flag 9 NA Start Condition Flag 6 Start Condition Flag 8 SCF9 SCF6 SCF8 Halt release caused by Halt release caused by Halt release caused by the signal change to L RFC counter overflow 2 underflow applied on KI1 4 in scanning interval MSD Rx Function Rx AC WDF CSF RFOVF Description The watchdog flag system clock status overflow flag of RFC counter and low battery detected flag are loaded to da
128. ltage on BAK pin VDDI VDD2 Internal operating voltage VDDI VDD2 Note For power saving reasons it is recommended to reset the BCF flag to 0 when back up mode is not used 52 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 18 STOP FUNCTION STOP The stop function is another way to minimize the current dissipation for TM87P18M In stop mode all the functions in TM87P18M are put into hold state including oscillators All of the LCD corresponding signals COM and Segment will output L level In this mode TM87P18M will not dissipate any power Because the stop mode will set the BCF flag to 1 automatically it is recommended to reset the BCF flag after releasing the stop mode in order to reduce power consumption Before the stop instruction is executed all of the signals on the IOD and IOC port pins which are defined as input mode must be in the L state and no stop release signals SRFn will be delivered The CPU will then enter stop mode by executing STOP instruction The following conditions will cause stop mode to be released One of the signals on IOD or the IOC port pin in input mode is in state and holds long enough to cause the CPU to be released from the halt mode A signal is changed on the INT pin The stop release condition specified by the SRE instruction is met When TM87P18M is released from stop mode
129. mn Clear Flag HRF5 to avoid the false HALT release Wait for the next key matrix scanning cycle The waiting period must be longer than the key matrix scanning cycle Read the input latch state Only enable SEG16 scanning output Clear HRF5 to avoid the false HALT released Wait for the time longer than the halt LCD clock cycle to ensure scan again Read the input latch state Preliminary 89 tenx technology inc Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver CHAPTER 4 LCD LED DRIVER OUTPUT TM87P18M provides 32 segment output pins and 8 common output pins to drive LCD 5 SEG17 23 SEG40 SEG41 can also be used as DC output ports the mask option MASK OPTION table Mask Option name Selected item 5 5 5 1 5 COM6 DC6 OD6 1 COM6 COM7 DC7 OD7 1 COM7 8 8 8 1 8 MASK OPTION table Mask Option name Selected item SEG17 23 40 41 DC OD 1 SEG17 23 40 41 1 LCD LIGHTING SYSTEM IN 87 18 There are several settings for the LCD lighting systems that can be selected in mask option in TM87P18M they are 1 2 bias 1 2 duty 1 2 bias 1 3 duty 1 2 bias 1 4 duty 1 2 bias 1 5 duty 1 2 bias 1 6 duty 1 2 bias 1 7 duty 1 2 bias 1 8 duty 1 3 bias 1 3 duty 1 3 bias 1 4 duty 1 3 bias 1 5 duty 1 3 bias 1 6 duty 1 3 bias
130. n the IOC IOD port pin is changing 15 1 2 The Setting for Stop Mode If SRF4 SRF3 and SEF4 SEF3 are set the stop mode will be released and set the SCF1 SCF3 when a high level signal is applied to one of the input mode pins of IOC IOD port and other pins stay in 0 state It is applied to one of the IOC IOD port pins in input mode After the stop mode is released TM87P18M enters the halt mode The high level signal must hold for a period long enough to allow the chattering prevention circuitry of the IOC GOD port to detect this signal and then set SCF1 SCF3 to release halt mode otherwise the chip will return to stop mode again 15 1 3 Interrupt for CTL1 The control register 1 CTL1 performs the following functions by the execution of the SIE instruction to enable the interrupt function An input signal changes on the input pins of IOC IOD port will cause MCU to deliver the SCFI SCF3 when SEF4 SEF3 has been set to 1 by executing the SCA instruction After delivering the status of SCF1 SCF3 flag the halt release request flag HRFO will be set to 1 In this case if the interrupt enable flag 0 IEFO is set to 1 by executing the SIE instruction beforehand it will also deliver the interrupt request flag 0 interrupt 0 to interrupt the program Once the interrupt 0 is accepted by MCU the later interrupt requests come from interrupt 0 will be inhibited until executing the SCA instruction to release this inh
131. nformation 87 18 4 Bit Microcontroller with LCD Driver set to 1 the program is required to reduce the time period and repeat the previous procedure again In the following example the RR network generates the clock source on CX pin Timer 1 is used to enable disable the counter LDS 0 0 Set the TMRI clock source 9 LDS 1 3 Initiate 1 setting value to LDS 2 OFh SHE 2 Enable halt release by TMR1 RE_CNT LDA 0 OR 1 Combine the TMRI setting value TMS 2 Enable the TMRI SRF 9 Build up the RR network and enable the counter HALT SRF 1 Stop the counter when 1 underflows MRFI 10h Read the content of the counter MRF2 11h MRF3 12h MRF4 13h MSD 20h JB2 CNTI OF Check the overflow flag of counter JMP DATA ACCEPT CNTI1 OF DEC 2 Decrement the TMI value LDS 20h 0 SBC 1 JZ RANGE Change the clock source of TMRI PLC 1 Clear the halt release request flag of TMR1 JMP RE CNT 82 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 7 3 Enable Disable the Counter by Timer 2 In this mode the clock source of the 16 bit counter is received from the CX pin and the 16 bit counter is activated by the operation of TMR2 When the counter is enabled by a SRF 18 instruction the 16 bit counter will not start counting until TMR2 is enabled and the first falling edge of the clock has applied
132. ng this instruction HL indicates an index address of data memory The Carry Flag CF will be affected AC Rx Rx AC B CF The contents of AC and CF are binary subtracted from content of Rx the result is loaded to AC and data memory Rx The Carry Flag CF will be affected AC R HL R HL AC B CF The contents of AC and CF are binary subtracted from content of data memory specified by HL the result is loaded to AC and data memory specified by HL The Carry Flag CF will be affected AC HL lt HL HL HL 1 Binary subtracts the contents of AC and CF from the content of HL the result is loaded to AC and data memory G HL The content of the index register G HL will be incremented automatically after executing this instruction HL indicates an index address of data memory The Carry Flag CF will be affected lt Rx AC Binary adds the contents of Rx and AC the result is loaded to The Carry Flag CF will be affected AC lt HL AC Binary adds the contents of 9 HL and AC the result is loaded to AC HL indicates an index address of data memory The Carry Flag CF will be affected 114 tenx technology inc Rev 1 0 2012 10 05 Advance Information 87 18 ADD HL Function Description ADD Rx Function Description ADD HL Function Description ADD HL Function Description SUB Rx Func
133. ng this instruction HL indicates an index address of data memory AC lt Rx AC Binary Ors the contents of Rx and AC the result is loaded to AC AC lt HL AC Binary Ors the contents of HL and AC the result is loaded to AC HL indicates an index address of data memory lt HL AC HL HL 1 Binary Ors the contents of HL and AC the result is loaded to AC The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory Preliminary 118 tenx technology inc Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver Rx Function AC lt Rx AC Description the contents of Rx and AC the result is loaded to AC and the data memory Rx HL Function AC HL lt HL AC Description the contents of HL and AC the result is loaded to AC and the data memory HL HL indicates an index address of data memory OR HL Function AC QHL lt QHL AC HL 1 Description the contents of 9 HL and AC the result is loaded to AC and the data memory HL The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory ADCI Ry D Function AC Ry D CF Description D represent
134. ntroller with LCD Driver RC Oscillation Network The RFC circuitry can build up to 3 RC oscillation networks by connecting sensors or resistors between CX and one of RR RT or RH and CX pins Only one RC oscillation network can be active at a time When the oscillation network is built up by executing SRF 1h SRF 2h and SRF 4h instructions to enable RR RT and RH networks respectively a clock signal with specified frequency corresponding to the resistance will be generated and counted by the 16 bit counter through the CX pin as the clock source How to build up the RC oscillation network 1 Connect the resistor and capacitor on the RR RT RH and CX pins Fig 2 24 illustrates the connection of these networks 2 Execute SRF 1h SRF 2h or SRF 4h instructions to activate the output pins RR RT RH for the RC networks respectively The inactive pins will become tri state output pins 3 Execute SRF 8 SRF 18h or SRF 28h instructions to enable the RC oscillation network and the 16 bit counter The RC oscillation network will not active until these instructions are executed The output pin of RC oscillation network one of the RR RT and RH pins will output an state before this network is activated To get a better oscillation clock from the CX pin activate the output pin for each RC network before the counter is enabled There is an extended bit the 175 bit for the 16 bit counter This bit is the overflow flag RFOVF whi
135. ology inc Rev 1 0 2012 10 05 Advance Information UM TM87P18M_E 4 Bit Microcontroller with LCD Driver Symbol Description Symbol Description Symbol Description Content of Register D Immediate Data AC Accumulator D B Complement of Immediate Data AC n Content of Accumulator bit n PC Program Counter AC B Complement of content of Accumulator CF Carry Flag X Address of program or control data ZERO Zero Flag Rx Address X of data RAM Watch Dog Timer Enable Flag content of Rx 7SEG 7 segment decoder for LCD Ry Address Y of working register BCLK System clock for instruction Address of data RAM specified HL IEFn Interrupt Enable Flag Backup flag HRFn Release Flag HL Generic Index address register HEFn HALT Release Enable Flag HL Content of generic Index address register Lz Address of LCD PLA Latch GL Content of lowest nibble Index register 5 STOP Release Enable Flag H Content of middle nibble Index register 5 Start Condition Flag GU Content of highest nibble Index register Cch Clock Source of Chattering prevention ckt T HL Address of Table ROM Clock Source of Frequency Generator H TGHL High Nibble content of Table ROM SEFn Switch Enable Flag L T HL Low Nibble content of Table ROM FREQ Generator setting Value TMR Timer Overflow Release F
136. on and the addressing range is from to 7FH 2 Index addressing mode The index address register HL specifies the address of the data memory and all address space from 00H to 1FFH can be accessed The 16 specified addresses 70H to 7FH in the direct addressing memory are also used as 16 working registers The function of working register will be described in detail in section 2 8 1 e 2 DATA o s lt o e 5 70H Working Register 389 x lt 7FH 5 80H 1 Y 4 Bits gt This figure shows the Data Memory RAM and Working Register Organization 8 WORKING REGISTER WR The locations 70H to 7FH of the data memory RAM are not only used as general purpose data memory but also as the working register WR The following will introduce the general usage of working registers 1 To perform the arithmetic and logic operations on the contents of a working register and immediate data Such as ADCI ADCI SBCI SBCI ADDI ADDI SUBI SUBI ADNI ADNI ANDI ANDI EORI EORI ORI ORI 2 To transfer data between a working register and any address in the direct addressing data memory RAM Such as MWR Rx Ry MRW Ry Rx 3 To decode or directly transfer the contents of a working register and then output to the LCD PLA circuit Such as 32 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit M
137. operates with a normal driving ability and the internal power BAK pin switches from VDD2 to VDD1 when BCF flag is cleared In this condition only peripheral circuitry operates under VDD2 voltage level the other functions will operate under voltage level It is necessary to connect a 0 1 uf capacitor between BAK and GND pins to regulate the internal power voltage Exit the back up mode anytime if it is not needed and reset the BCF flag to 0 in order to reduce the current consumption for low power applications The back up flag indicates the status of the back up function When setting the flag to 1 the MCU will enter backup mode The BCF flag can be set or reset by executing the SF or RF instructions respectively In order to shorten the start up time of the 32 768 KHz Crystal oscillator TM87P18M sets the BCF to 1 during the initial reset cycle and reset BCF to 0 by executing the RF 2 instruction in Li power mode options The back up function performs differently with different power mode options as shown in the following table 3V battery or higher mode TM87P18M status BCF flag status Initial reset cycle 1 hardware controlled After initial reset cycle 1 hardware controlled Executing SF 2h instruction 1 Executing RF 2h instruction 0 HALT mode Previous state STOP mode 1 hardware controlled 32 768 KHz Crystal Oscillator Small driver Large driver Vo
138. ounter jumps to X if AC3 1 If bit3 of AC is 1 jump occurs If 0 the PC is increased by 1 The range of X is from 000H to 7FFH or 800H to FFFH Program counter jumps to X if AC 0 If the content of AC is not 0 jump occurs If 0 the PC is increased by 1 The range of X is from 000H to 7FFH or 800H to FFFH Program counter jumps to X if CF 0 If the content of CF is 0 jump occurs If 1 the PC is increased by 1 The range of X is from 000H to 7FFH or 800H to FFFH Program counter jumps to X if AC 0 If the content of AC is 0 jump occurs If 1 the PC is increased by 1 The range of X is from 000H to 7FFH or 800H to FFFH Program counter jumps to X if CF 1 If the content of CF is 1 jump occurs If 0 the PC is increased by 1 The range of X is from 000H to 7FFH or 800H to FFFH Program counter jumps to X Unconditional jump The range of X is from 000H to FFFH STACK PC 1 Program counter jumps to X A subroutine is called The range of X is from 000H to FFFH PC STACK A return from a subroutine occurs 129 tenx technology inc Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 9 MISCELLANEOUS INSTRUCTIONS SCC X Function Setting the clock source for IOC IOD chattering prevention PWM output and frequency generator Description The following table shows the meaning of each bit for this instruction Bit pattern Clock sou
139. overflow flag of the 16 bit counter of RFC RFOVF is set to 1 when the overflow of the 16 bit counter of RFC occurs The flag will be reset to 0 when this counter is initiated by executing the SRF instruction The MSD instruction can be used to transfer the contents of status register 4 STS4 to the accumulator AC and the data memory RAM The following table shows the Bit Pattern of Status Register 4 STS4 Bit 3 Bit 2 Bit 1 Bit 0 NA The overflow flag of 16 bit Watchdog timer System clock counter of RFC RFVOF Enable flag WDF selection flag CSF Read only Read only Read only Read only 14 6 START CONDITION FLAG 11 SCF11 The Start Condition Flag 11 5 11 will be set to 1 in STOP mode when the following conditions are met A high level signal received from the OR ed output via the pins defined as input mode in the IOC port it causes the stop release flag of the IOC port CSR to output the stop release enable flag 4 SRF4 has to be set beforehand A high level signal received from the OR ed output via the pins defined as input mode in the port it causes the stop release flag of the IOD port DSR to output the stop release enable flag 3 SRF3 has to be set beforehand A high level signal received from the OR ed output of the signals latch buffer on KI1 4 pins it causes the stop release flag of the Key Scanning SKI to output the stop release enable flag 4 SRF7 has to be set beforehand
140. put data on the ports will not be affected even the program enters the stop mode or the LCD turn off mode Preliminary 92 tenx technology inc Rev 1 0 2012 10 05 UM TMS7P18M Advance Information 4 Bit Microcontroller with LCD Driver Figure 4 1 CMOS Output Type Figure 4 2 P Open Drain Output Type Only those unused COM and SEG pads can be defined as DC output pins The COM pad sequence for LCD drivers can not be interrupted when the COM pads are defined as DC output ports For example when the LCD lighting system is specified as 1 5 duty the COM pad used for LCD driver must be 5 Only COM6 8 pads can be defined as DC output ports 3 SEGMENT CIRCUIT FOR LCD DISPLAY 3 1 PRINCIPLE OF OPERATION OF LCD DRIVER SECTION Fig 4 3 1 below illustrates how the LCD driver module operates when the LCD related instructions are AC amp RAM data executed gt Data Data Multiplexe memor decode RRP LCD output i Bata bus circuit Strobe data of LCD Don related strobe LO to L4 instructio n Figure 4 3 1 Principal Drawing of LCD Driver Section The LCD driver section consists of the following units Data decoder to decode data supplied from RAM or table ROM Latch circuit to store LCD lighting information LO to L4 decoder to decode the Lz specified data in LCD related instructions which specifies the strobe of the latch circuit
141. r Rx The content of Rx is output to I OA port 1 2 Rx IOA3 D IOA4 pulse Content of Rx is output to IOA port D is output to IOA3 pulse is output to IOA4 D 0or 1 Rx AC IOA The data of I OA port is loaded to AC and data memory Rx Defines the input output mode of each pin for IOB port and enables or disables the pull low device Sets the I O mode and turns the pull low device on or off The meaning of each bit of X X4 X3 X2 X1 X0 is shown below Bit pattern Setting Bit pattern Setting 4 1 Enable the pull low device on X4 0 Disable the pull low device on IOB1 IOB4 simultaneously 2 IOB1 IOB4 simultaneously IOB4 as output mode IOB4 as input mode IOB3 as output mode IOB3 as input mode IOB2 as output mode IOB2 as input mode IOB 1 as output mode as input mode OPB Rx Function Description IPB Rx Function Description SPC Function Description VOB Rx The contents of Rx are output to I OB port Rx AC IOB The data of I OB port is loaded to AC and data memory Rx Defines the input output mode of each pin for IOC port and enables disables the pull low device low level hold device Sets the I O mode and turns on off the pull low device The input pull low device will be enabled when the I O pin is set as input mode Preliminary 106 tenx technology inc Rev 1 0 2012 10 05 87 15 E 4 Bit Microcontroll
142. r SRF X Function The operation control for RFC Description The meaning of each control bit X5 X0 is shown below X4 1 controls the counter must be X4 0 Disables timer 2 to control the 16 bit counter set to 1 when this bit is set to 1 X5 0 Disables the CX pin to control the 16 bit counter Note X4 and X5 can not be set to 1 at the same time 2 ACCUMULATOR MANIPULATION INSTRUCTIONS AND MEMORY MANIPULATION INSTRUCTIONS MRW Ry Rx Function AC Rx Rx Description The content of Rx is loaded to AC and the working register specified by Ry MRW HL Rx Function AC R HL Rx Description The content of data memory specified by Rx is loaded to AC and data memory specified by HL MRW HL Rx Function AC R HL lt Rx HL HL 1 Description The content of data memory specified by Rx is loaded to AC and the data memory specified by HL The content of the index register HL will be incremented automatically after executing this instruction MWR Rx Ry Function AC Rx Ry Description The content of working register specified by Ry is loaded to AC and data memory specified by Rx MWR Rx HL Function AC Rx lt R HL Description The content of data memory specified by HL is loaded to AC and data memory specified by Rx 110 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information UM TM87P18M_E 4 Bit Microcontroller with LCD Driver M
143. r The comparison bit pattern is shown below CPHL X X7 X6 X5 4 X3 X2 HL IDBF7 IDBF6 IDBF5 IDBF4 IDBF3 IDBF2 IDBFI IDBFO 7 DECIMAL ARITHMETIC INSTRUCTIONS DAA Function AC BCD AC Description Converts the content of AC to binary format and then restores to AC When this instruction is executed the AC must be the result of any added instruction The Carry Flag CF will be affected DAA Rx Function AC Rx BCD AC Description Converts the content of AC to binary format and then restores to AC and data memory specified by Rx When this instruction is executed the AC must be the result of any added instruction The Carry Flag CF will be affected DAA HL Function AC R HL BCD AC Description Converts the content of AC to decimal format and then restores to AC and data memory specified by HL When this instruction is executed the AC must be the result of any added instruction The Carry Flag CF will be affected AC data before DAA CF data before DAA AC data after DAA CF data after DAA execution execution execution execution 0 9 AC 6 0 3 6 DAA HL Function AC HL BCD AC HL HL 1 Description Converts the content of AC to binary format and then restores to AC and data memory specified by HL The content of the index register HL will be incremented automatically after
144. rator D X Description Loads the data X X7 X0 and D to frequency generator to set the duty cycle and initial value The following table shows the preset data and the duty cycle setting po Thebitpatemofprestleter N O O bit 0 Note X0 X7 represents data specified in operand X Preset Letter D Duty Cycle 1 FRQD Rx The content of Rx and AC as preset data N 2 FRQD HL The content of tables TOM specified by index address buffer as preset data N 3 FRQXD X The data of operand in the instruction are assigned as preset data N TMS Rx Function Select timer 1 clock source and preset timer 1 Description The content of data memory specified by Rx and AC are loaded to timer 1 to start the timer The following table shows the bit pattern for this instruction Selectclock Setting value Rx2 The clock source option for timer 1 _ 3 PH9 PH3 FREQ o i Pa 1 l 1 J 131 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver TMS HL Function Select timer 1 clock source and preset timer 1 Description The content of table ROM specified by HL is loaded to timer 1 to start the timer The following table shows the bit pattern for this instruction Select clock p The clock source option for timer 1 TMSX X Function
145. rce setting Bit pattern Clock source setting The clock n foni th The clock source comes from X6 1 s 2 X6 0 the 0 Refer to section 3 3 4 for system clock BCLK 0 Bit pattern Clock source setting Bit pattern Clock source setting 2 1 0 001 port PHO X2 X1 X0 001 port PHO 2 1 0 010 port PH8 X2 X1 X0 010 port PH8 Chattering prevention clock of Chattering prevention clock of X2 X1 X0 100 port PH6 X2 X1 X0 100 port PH6 D Rx Function Frequency generator D Rx AC Description Loads the content of AC and data memory specified by Rx and D to frequency generator to set the duty cycle and initial value The following table shows the preset data and the duty cycle setting The bitpattern of presetleterN Duty Cyele TE 1 3 duty 1 2 duty 1 1 duty FRQ D HL Function Frequency generator D T HL Description Loads the content of Table ROM specified by HL and D to frequency generator to set the duty cycle and initial value The following table shows the preset data and the duty cycle setting The bit pattern of preset letter Note TO T7 represents the data of table 130 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver Preset Letter D FRQX D X Function Frequency gene
146. rent under 40 mA for each COM pin at Low Active Mode The LED alternating frequency can be selected in mask option All the LED alternating frequencies are based on the predivider s clock source frequency which is 32768 Hz The LED alternating frequency in 1 2 duty mode LED duty cycle 1 2 duty frequency The LED alternating frequency in 1 3 duty mode LED duty cycle 1 3 duty frequency The LED alternating frequency in 1 4 duty mode LED duty cycle 1 4 duty frequency The LED alternating frequency in 1 5 duty mode LED duty cycle 1 5 duty frequency 99 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver The LED alternating frequency in 1 6 duty mode LED duty cycle 1 5 duty frequency The LED alternating frequency in 1 7 duty mode LED duty cycle 1 5 duty frequency The LED alternating frequency in 1 8 duty mode LED duty cycle 1 5 duty LED alternating 113Hz 226 Hz frequency LED Lighting System and Maximum Number of Driving LED Segments LED Lighting System Maximum Number of M LED Static O O 1 3duty 1 4duty 1 6duty 1 7duty 1 8duty L 5duty TM87P18M allows some SEG pins to be the DC output ports and the remaining of the SEG pins to be the LED driver outputs When a SEG pin is defined as the DC output port the output data will remain intact even if the MCU enters the STO
147. reset X1 1 Halt release request flag HRF1 caused by underflow from the timer 1 is reset and stops the operating of timer 1 TM1 X2 1 Halt or stop release request flag HRF2 caused by the signal change at the INT pin is reset X3 1 Halt release request flag HRF3 caused by overflow from the predivider is reset X4 1 Halt release request flag HRF4 caused by underflow from the timer 2 is reset and stops the operating of timer 2 TM2 X5 1 Halt release request flag HRF5 caused by the signal change to L on KI1 4 in scanning interval is reset X6 1 Halt release request flag HRF6 caused by overflow from the RFC counter is reset X8 1 The last 5 bits of the predivider 15 bits are reset When executing this instruction X3 must be set to 1 simultaneously Preliminary 134 tenx technology inc Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver Appendix A 87 18 Instruction Table Instruction Machine Code Function Flag Remark NOP 0000 0000 0000 0000 No Operation LCT Lz Ry 0000 0017 ZZZZZYYY 12 lt 7SEG lt Ry 70H 77H lt JSEG R LCB LzRy 0000 010Z ZZZZZYYY 12 Z ro y Ry 70H 77H LCP Lz Ry 0000 011Z ZZZZZYYY 12 lt Ry amp AC Ry 70H 77H LCD Lz HL 0000 100Z ZZZZ Z000 Lz lt T HL LCT
148. ry tenx technology inc Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 4 LED DRIVER OUTPUT If the LED mode option is selected in the mask option TM87P18M will switch the LCD driver to the LED driver TM87P18M provides 32 segment pins SEG and 8 common pins COM to drive a LED module with 256 pixels For LED application the COM pin can be selected as active low LED display or active high LED display in mask option There are options for static 1 2 1 8 duty lighting systems There are only 2 bias options can be selected in mask option the one is 1 2 bias and the other is No bias option for the bias system In the LED mode the segment output pins SEG waveforms are low active type MASK OPTION table When COM pins drives the high active LED panel Mask Option name Selected item LCD LED ACTIVE TYPE 2 LED HIGH ACTIVE When COM pins drives the low active LED panel Mask Option name Selected item LCD LED ACTIVE TYPE 3 LED LOW ACTIVE The following schematics will illustrate the difference between high active mode and low active mode 1 High Active Mode SEG1 52 53 54 55 56 57 58 98 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 2 Low Active Mode COM1 Note Please limit the total sink cur
149. s 10H is binary subtracted the result loads to data memory address 10H R10 AC FH 0 DAS 10h Convert the content of the data memory address 10H to decimal format The result in the data memory address 10H is 9 and in the CF is 0 This represents the decimal number 1 12 TIMER 1 Re load RL1 Q S instruction IEF1 R ila reset TMR1 Interrupt FREQ 6 bit binary down 1 PH ___ counter HRF1 PH9 SCF5 B Halt release PH15 id Operand data 5 0 TMS instruction Interrupt accept signal ea PLC 2 instruction TMS instruction Initial reset This figure shows the TMRI organization 34 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 12 1 NORMAL OPERATION TMRI consists of a programmable 6 bit binary down counter which is loaded and enabled by executing TMS or TMSX instruction Once the TMR1 counts down to 3Fh it generates an underflow signal to set the halt release request flag HRF1 to 1 and then stop to count down When 1 and the TMRI interrupt enable flag IEF1 1 the interrupt is generated When 1 1 if the IEF1 0 and the TMRI halt release enable HEF1 1 program will escape from halt mode if CPU is in halt mode and t
150. s the immediate data Binary ADDs the contents of Ry D and CF the result is loaded to AC The Carry Flag CF will be affected D 0H FH ADCI Ry D Function AC Ry Ry D CF Description D represents the immediate data Binary ADDs the contents of Ry D and CF the result is loaded to AC and the working register Ry The Carry Flag CF will be affected D 0H FH SBCI Ry Function AC Ry D CF Description D represents the immediate data Binary subtracts the CF and immediate data D from the working register Ry the result is loaded to AC The Carry Flag CF will be affected D 0H FH SBCI D Function AC Ry Ry D CF Description D represents the immediate data Binary subtracts the CF and immediate data D from the working register Ry the result is loaded to AC and the working register Ry The Carry Flag CF will be affected D 0H FH 119 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver ADDI Function AC Ry D Description D represents the immediate data Binary ADDs the contents of Ry and D the result is loaded to AC The Carry Flag CF will be affected D 0H FH ADDI Ry D Function AC Ry Ry D Description D represents the immediate data Binary ADDs the contents of Ry and D the result is loaded to AC and the working register Ry The Carry Flag CF will b
151. se refer to 2 17 Note 3 The VDD1 level 1 2 VDD2 in the off state of SW is used as an intermediate voltage level for the LCD driver 17 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 1 3 BIAS AT Li BATTERY POWER SUPPLY The backup flag BCF must be reset after the operation of the halver circuit is fully stabilized and a voltage of approximately 1 2 VDD2 appears on the VDD1 pin Backup flag BCF BCF 0 ON 1 OFF CUP1 0 1u zz CUP2 VDD3 5 2 VDD2 Sw1 VDD1 Internal logic I BAK 0 1u 0 1u 0 1u GND e MASK OPTION TABLE Mask Option name Selected item POWER SOURCE 2 BATTERY OR HIGHER BIAS 3 1 3 BIAS Note 1 The input output ports operate between GND and VDD2 Note 2 The backup flag 15 set to the initial cycle When the backup flag is set to 1 the internal logic signal is operated on VDD2 and the driving power of the oscillator circuit increases and the operating current also increases Therefore unless it is required otherwise the backup flag must be reset to 0 after the initial cycle For the backup flag please refer to 2 17 Note 3 The level 1 2 VDD in the off state of SW1 is used as an intermediate voltage level for LCD driver
152. signals If the stop instruction is executed in the state that the stop release signal SRF is delivered the CPU will not enter stop mode but enter the halt mode When stop mode is released and an interrupt is accepted the halt release signal HRF is reset automatically 54 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver Chapter 3 Control Function 1 ERRUPT FUNCTION There are 7 different kinds of interrupt 3 external interrupts and 4 internal interrupts When an interrupt is accepted the program in execution is suspended temporarily and the corresponding interrupt service routine specified by a pre determined address in the program memory ROM will be called The following table shows the flag and service of each interrupt Table 3 1 1 Interrupt information Interrupt IOC or IOD TMRI Pre divider TMR2 Key matrix RFC counter INT pin source port underflow overflow underflow Scanning overflow 010H 014H 018H 01CH 020H 024H 028H vector 1 IEF4 IEF5 IEF6 enable flag Interrupt 6 5 1 3 ath 49 priority Interrupt 55 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver The following figure shows the Interrupt Control Circuit Interrupt 0 Specified signal change at IOC or
153. t will flow into the input buffer The default setting of the IOB port is input mode in the initial reset cycle each bit of the port can be defined as input mode or output mode respectively by executing a SPB instruction Executing an OPB 72 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver instruction can output the content of specified data memory to those pins which have been defined as output mode Executing an IPB instruction can store the IO pins signals into the specified data memory When the IO pins are defined as output mode executing an IPB instruction will store the content that is stored in the output latch into the specified data memory Before changing the I O pins to output mode the OPB instruction must be executed first to output the data to those output latches It will prevent the chattering signal on the I O pin when changing the I O mode port has a built in pull low resistor which can be selected in mask option and can be enabled disabled by executing a SPB instruction Pull low function option Mask Option name Selected item IOB PULL LOW RESISTOR 1 USE IOB PULL LOW RESISTOR 2 NO USE 5 3 IOC PORT IOCI IOC4 pins are MUXed with and pins respectively by mask option MASK OPTION table Mask Option name Selected item IOC1 KI1 2 IOCI 2
154. t mode returns by executing the RTS instruction after completion of interrupt service STOP Function Enters stop mode and stops all oscillators Description Before executing this instruction all signals on IOC port must be set to low The following 3 conditions cause the stop mode to be released 1 One of the signal on KI1 4 is H L LED LCD in scanning interval 2 A signal change in the INT pin 3 One of the signals on IOC port is H SCA X Function The data specified by X causes the halt mode to be released Description The signal change at port IOA IOC is specified The bit meaning of X X4 is shown below Halt mode is released when signal is applied to IOC X7 5 X3 0 is reserved SIE X Function Set Reset interrupt enable flag Description The IEFO is set so that interrupt 0 Signal change at port IOC specified by SCA is accepted The is set so that interrupt 1 underflow from timer 1 is accepted The IEF2 is set so that interrupt 2 the signal change at the INT pin is accepted The 4 is set so that interrupt 4 underflow from timer 2 is accepted The IEF6 is set so that interrupt 6 overflow from the RFC counter is accepted X7 is reserved imer Di 5 Function Set Reset halt release enable flag Description 1 1 The HEF is set so that halt mode is released by TMRI underflow The is set so that the halt mode is released by signal changed on INT pin X
155. ta memory specified by Rx and AC The content of AC and meaning of bit after execution of this instruction are as follows Bit 3 Bit 2 Bit 0 NA The overflow flag of 16 bit Watchdog timer System Clock counter of RFC RFVOF enable flag WDF Selection Flag CSF 6 INDEX ADDRESS INSTRUCTIONS MVU Rx Function QU Rx Description Loads content of Rx to the index address buffer U U3 Rx 3 U2 Rx 2 U1 Rx 1 00 18 10 MVH Rx Function lt Rx Description Loads content of Rx to higher nibble of index address buffer H3 Rx 3 H2 Rx 2 H1 Rx 1 HO Rx 0 MVL Rx Function L Rx Description Loads content of Rx to lower nibble of index address buffer L3 Rx 3 L2 Rx 2 L1 Rx 1 1 0 18 10 CPHL X Function If HL X force the next instruction as NOP Description Compares the content of the index register HL in lower 8 bits h and L with the immediate data X Note In the duration of the comparison of the index address all the Interrupt Enable Flags IEF have to be cleared to avoid malfunction If the compared result is equal the next executed instruction that is behind the CPHL instruction will be forced as NOP If the compared result is not equal the next executed instruction that is behind CPHL instruction will operate normally 126 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Drive
156. ter the key is depressed on the key matrix and then SCF7 will be set to 1 107 tenx technology inc Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 1 when is set to 1 the HALT released request HRF5 will be set to 1 after each scanning cycle regardless of key depression and then SCF7 will be set to 1 X7Xs5X4 000 in this setting each scanning cycle only checks one specified column K1 K16 on the key matrix The specified column is defined by the setting of X X5 Xo 0000 activates the column X Xo 0001 activates the K2 column X 1110 activates the K15 column X Xo activates K16 column X7X5X4 001 in this setting all of the matrix columns K16 will be checked simultaneously in each scanning cycle X not a factor X7X5X4 010 in this setting the key matrix scanning function will be disabled X Xo are not a factor X5X5X4 10X in this setting each scanning cycle checks 8 specified columns on the key matrix The specified column is defined by the setting of X3 0 activates K8 columns simultaneously 1 activates K9 K16 columns simultaneously X5 X are not a factor X7X5X4 110 in this setting each scanning cycle checks four specified columns on the key matrix The specified columns are defined by the setting of and X X3X 00 activa
157. tes the K1 K4 columns simultaneously 01 activates the K5 K8 columns simultaneously 10 activates K9 K12 columns simultaneously 11 activates the K13 K16 columns simultaneously X Xo are not a factor X5X5X4 111 in this setting each scanning cycle checks two specified columns the key matrix The specified columns are defined by the setting of X5 X and X3X2X 000 activates K2 columns simultaneously 001 activates K4 columns simultaneously 110 activates K14 columns simultaneously XXX 111 activates K15 K16 columns simultaneously Xo is not a factor 108 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information UM TM87P18M_E 4 Bit Microcontroller with LCD Driver 5 Rx Function Sets the Key matrix scanning output state Description When SEG1 16 is are used for LCD driver pin s sets the contents of AC and Rx to specify the key matrix scanning output state for each SEGn pin in the scanning interval The bit setting is the same as the SPKX instruction The bit patterns of AC and Rx corresponding to SPKX are shown below Instruction Bit7 Bit6 Bit5 Bit4 Bit3 2 Bitl 0 SPK Rx AC3 AC2 1 Rx3 Rx2 1 Rx0 SPKX X X7 X6 5 4 3 2 X0 SPK HL Function Sets the Key matrix scann
158. tion Description SUB HL Function Description SUB HL Function Description 4 Bit Microcontroller with LCD Driver lt HL AC HL 1 Binary adds the contents of HL and AC the result is loaded to AC The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory The Carry Flag CF will be affected AC Rx lt Rx AC Binary adds the contents of Rx and AC the result is loaded to AC and the data memory Rx The Carry Flag CF will be affected AC HL lt HL AC Binary adds the contents of HL and AC the result is loaded to AC and the data memory HL HL indicates an index address of data memory The Carry Flag CF will be affected AC HL lt HL AC HL HL 1 Binary adds the contents of HL and AC the result is loaded to AC and the data memory HL The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory The Carry Flag CF will be affected AC Rx AC B 1 Binary subtracts the content of AC from the content of Rx the result is loaded to AC The Carry Flag CF will be affected AC lt HL AC B 1 Binary subtracts the content of AC from the content of 9 HL the result is loaded to AC HL indicates an index address of data memory The Carry Flag CF will
159. tion LCD latch Lz data decoder Ry Description The content of working register specified by Ry are loaded to the LCD latch specified by Lz through the data decoder Lz 00 1FH Ry 0 7H LCB Lz Ry Function LCD latch Lz data decoder Ry Description The content of working register contents specified by Ry are loaded to the LCD latch specified by Lz through the data decoder If the content of Ry is 0 the output of the data decoder will consist entirely of 0 Lz 00 1FH Ry 0 7H LCP Lz Ry Function LCD latch Lz lt Ry AC Description The content of working register contents specified by Ry and the contents of AC are loaded to the LCD latch specified by Lz Lz 00 Ry 0 7H 104 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 E 4 Bit Microcontroller with LCD Driver Table 5 2 The mapping table of LCD latches with the contents of AC and Ry __ DBUSA DBUSB DBUSC DBUSD DBUSE DBUSF DBUSG DBUSH LCD Lz HL Function LCD latch Lz TAB HL Description HL indicates an index address of table ROM The content of table ROM specified by HL are loaded to the LCD latch specified by Lz directly Refer to Table 5 2 Lz 00 LCT Lz HL Function LCD latch Lz data decoder HL Description The content of index RAM specified by HL are loaded to the LCD latch specified
160. transmission of SCF1 SCFI will be reset to 0 by executing a SCA instruction and the chattering prevention clock will be enabled at the same time If 75 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver SCF1 has been set to 1 a halt release request flag 0 HRFO will be generated In this case if the Interrupt Enable Flag IEFO of the port IOC is set the interrupt will be accepted Since the IOC port is not available to hold the information of the signal on the input pins of IOC1 to IOCA the input data on the port IOC should be read into the RAM immediately after the halt mode is released 5 4 IOD PORT The default setting of IOD port is input mode in the initial reset cycle each bit of the port can be defined as input mode or output mode respectively by executing a SPD instruction Executing an OPD instruction can output the content of specified data memory to the pins which has been defined as output mode Executing IPD instructions can store the signals applied to the IOD pins into the specified data memory When the IOD pins are defined as output mode executing an IPD instruction will store the data that stored in the output latches into the specified data memory Before changing the I O pins to output mode the OPD instruction must be executed first to output the data to those output latches It will prevent the chattering signal on the I O pin
161. ts that shares the memory space with the instruction ROM as shown in the figure above This memory space stores the constant data or look up tables for the usage of the main program the table ROM addresses can be specified by the index address register HL The data width can be 8 bits 256 16 N x 8 bits or 4 bits 512 16 N x 4 bits depending on the usage Please refer to the explanation in the instruction chapter for details 29 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 5 INDEX ADDRESS REGISTER HL This is a versatile address pointer for the data memory RAM and table ROM TROM The index address register HL is a 12 bit register and the content of the register can be modified by executing MVH MVL and MVU instructions The execution of the MVL instructions will load the content of the specified data memory to the lower nibble of the index register L In the same manner the execution of the MVH and MVU instructions will load the content of the data RAM Rx to the higher nibble of the register H and U respectively U register H register L register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bitl BitO Bit3 Bit2 Bitl IDBF11 10 IDBF9 IDBF8 IDBF7 IDBF6 IDBF5 IDBF4 IDBF3 IDBF2 IDBFI IDBFO The index address register can specify the full range addresses
162. uction can also enable the pull low device and disable the low level hold device Executing the SPC Oh instruction will disable the pull low device and enable the low level hold device Once an IOC pin is defined as the output mode both the pull low resistor and the low level hold device will be disabled CLK gt o bit0 bitl D CLK 1 it IOC2 7o Initial clear SPC bit2 d edge dectect amp 3 chattering SCF1 Data d Bus D P cu IOC3 D erie gt o D bit3 odh 1004 09 129 bit3 M O m Control 2 1 Note M O is mask option V This figure shows the organization of IOC port 74 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information UM TM87P18M_E 4 Bit Microcontroller with LCD Driver Note The pins in input mode should not be in floating or a large current straight through current will flow into the input buffer when both the pull low device and the L level hold device are disabled MASK OPTION table Pull low function option Mask Option name Selected item IOC PULL LOW RESISTOR 1 USE IOC PULL LOW RE
163. upt is accepted the halt release signal is reset automatically 2 signal change IOC or IOD port is specified by the SCA instruction SCF1 or SCF3 3 The halt release condition specified by the SHE instruction is met HRF1 HRF6 When the halt mode is released in either 2 or 3 it is necessary to execute the MSB or the MSC or the MCX instruction to test the halt release signal It is also necessary to execute the PLC instruction to reset the halt release signal HRF Even the HALT instruction is executed in the state that the halt release signal is delivered the MCU does not enter the halt mode 51 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 17 BACK UP FUNCTION TM87P18M provides a back up mode to avoid system malfunctioning under heavy loading such as active buzzer LED lighting etc since heavy loading will cause a large voltage drop in the supply voltage the system will malfunction under this condition In back up mode the 32 768 KHz Crystal oscillator will increase the driving ability and switch the internal power BAK pin from VDD1 to VDD2 Li power option only Under this condition all the functions in TM87P18M will work under VDD2 voltage level It will improve the power noise immunity of TM87P18M but it also increases the power consumption If it is not in back up mode the 32 768 KHz Crystal oscillator
164. w counter is equal to 8 exit subroutine Disable the re load function Preliminary 37 tenx technology inc Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 13 TIMER 2 TMR2 The following figure shows the TMR2 organization Re load RL2 TM2 instruction IEF Initial reset 6 bit binary down Interrupt counter FREQ 3 5 SCF 9 6 11 Halt release 13 15 Operand Data X5 X0 Operand Data X8 X7 X6 TM2 instruction 2 instruction Interrupt accept signal PLC 10h instruction gt TENX Initial reset DED Q Control signal of RFC counter falling edge of the 1st clock after TM2 is enabled 13 1 NORMAL OPERATION TMR2 consists of a programmable 6 bit binary down counter which can be loaded and enabled executing either the TM2 or the TM2X instructions Once TMR2 counts down to 3Fh it stops counting then generates an underflow signal and sets the halt release request flag 4 HRF4 to 1 When HRF4 1 and the TMR2 interrupt enabler IEF4 is set to 1 the interrupt occurs When HRF4 1 IEF4 0 and the TMR2 halt release enabler HEF4 is set to 1 the program will exit from the halt mode if CPU is in the halt mode and HRF4 sets the start condition flag 6 SCF6 to 1 in the status register 4 STS4 After power on reset the default clo
165. will be all 0 this is used for blanking the leading digit 0 on the LCD panel The LCP instruction transfers content of the RAM Rx and accumulator AC to DBUSA DBUSH directly by passing the data decoder The LCD instruction transfers the table ROM data T HL to DBUSA DBUSH directly bypassing the data decoder 94 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver Table 4 3 2 The bit mapping table of LCP and LCD instructions DBUSA DBUSB DBUSC DBUSD DBUSE DBUSF DBUSG DBUSH If we define that a pixel is a pattern on LCD panel corresponding to a specified segment and common 87 18 can drive a LCD panel which contains up to 256 32 SEGs and 8 COM pixels Each pixel needs a pixel latch to store its display information ON or OFF so there are total 256 pixel latches in latch circuitry The input data of the pixel latch comes from DBUS data and the strobe signal comes from PSTB signal The segment LRAM determines the connection between DBUS data the data input of a latch circuit and so does the connection between PSTB signals and the strobe signal The connection is performed in mask option Each latch circuit can select one of 8 DBUS data and select one of 32 PSTB signals In this way the configuration of LCD panel s pixel is very flexible Among 256 signals obtainable by
166. xecuting a jump instruction except JMP and CALL the program counter PC will be loaded with the specified address in the operand of the instruction All these relative jump instructions can only 26 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver be used to address the current page that is when the current page is page 0 PC11 0 only the range from 000h 7FFh is accessible when the current page is page 1 PC11 1 only the range from 800h FFFh is accessible PC current page PC11 specified address in the operand Return instruction RTS PC content of stack specified by the stack pointer Stack pointer stack pointer 1 Table 2 1 Initial reset Interrupt 2 INT pin input port or 2901 timer 1 interrupt MERC pre divider interrupt Interrupt 4 timer 2 interrupt Interrupt 5 Key Scanning interrupt Interrupt 6 RFC counter interrupt Subroutine 11 P10 to PO the 11 Low order bits of instruction operand P11 page register When executing a subroutine call instructions or interrupt service routine the content of the program counter PC are automatically saved to the stack register STACK 4 PROGRAM TABLE MEMORY The built in mask ROM is organized into 4096 x 16 bits There are 2 pages of memory space in this mask ROM Page 0 covers the address ranging from 000
167. z 3 0V 200 KHz 250 KHz 300 KHz 500 KHz 3 0V 400 KHz 500 KHz 600 KHz 6 ELECTRICAL CHARACTERISTICS At 1 VDD2 3 0V Li At 2 VDD2 5 0V Input Resistance Name Symb Condition Min Typ Max Unit L Level Hold Rilhi Vi 0 2VDD2 1 10 40 100 KQ Tr IOC RIIh2 Vi 0 2VDD2 2 5 20 50 KQ Vi VDD2 1 200 500 1000 KQ IOA B C Pull Down Tr Rmad2 2 2 100 250 500 Rintul Vi VDD2 1 200 500 1000 KQ INT Pull up Tr Rintu2 Vi VDD2 2 100 250 500 KQ Rintd1 Vi GND 1 200 500 1000 KQ INT Pull Down Tr Rintd2 Vi GND 2 100 250 500 KQ RES Pull Down R Rres Vi GND or VDD2 1 2 10 45 100 KQ 7 DC Output Characteristics At 3 VDD2 2 4V Li At 4 VDD2 4 0V Name Symb Condition Port Min Typ Max Unit e Voh3c Ioh 1 mA 3 COMS 8 DC9 2 0 V Output H Voltage Ioh 3 4 SEG28 30 DC31 32 V H Vol3c Iol 2 mA 3 SEG40 41 0 4 V voc Tol 6 44 IOC IOD 0 8 V Voh3c 3 83 2 0 Cue tones aie easier V narum Vol3c 101 5 mA 3 i 0 4 oase l Volde 10110 4 0 8 V 13 tenx technology inc Preliminary Rev 1 0 2012 10 05 Advance Information 87 18 4 Bit Microcontroller with LCD Driver 8 Segment Driver Output Characteristics

TM87P18M 4-Bit Microcontroller with LCD Driver User Manual

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