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HMC1197LP7FE - Analog Devices

1. Performance 2646 96 MHz Performance 2646 96 MHz Exact Frequency Mode ON 121 Exact Frequency Mode OFF 121 40 40 60 y 100 8 E E p 120 2 i i 140 160 180 ET d E RT 1 E a a 10000 s 100000 OFFSET KHz OFFSET KHz Figure 32 Closed Loop Phase Noise With Figure 31 Forward Transmission Gain External VCO HMC384LP4E 2200 MHz 20 40 60 z 521 EXT INLOO 3 0 a o Sz B 10 027100 2 2 420 5 7 lt g 140 E 160 o M i ais 180 400 800 1200 1600 2000 2400 2800 1 10 100 1000 10000 OUTPUT FREQUENCY MHz OFFSET KHz 1 Measured from a 50 source with a 100 external resistor termination See PLL with Integrated RF VCOs Operating Guide Reference Input Stage section for more details Full FOM performance up to maximum 3 3 Vpp input voltage 2 122 88 MHz clock input PFD 61 44 MHz Channel Spacing 240 KHz 3 S21 from Ext_VCO pin 43 44 in and LO pin32 33 out For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com LL gt lt a or gt LLI Q z lt H 10 O LL gt lt C D m gt m O 0 2 lt or H HMC1197LP7FE MICROWAVE CORPORATION 0
2. Bas 2 iu 38 VCC2 Differential Auxiliary LO output CP BOT reas O qu wei External LO Input 2 4 7 Ar 53 Lop woo EJ GEI Gs sw T VA Gal LON Exact Frequency Mode XREFP 53 ode x CE CHIP EN 0 Hz Fractional Frequency Error DvoD 7 zm 50 Programmable RF Output Phase B Fa 7 29 N C EN Mop 53 45 CE Output Phase Synchronous Frequency Changes IFIP HO GO 27 v3 Output Phase Synchronization QN TD 25 IN wel Internal LO Mute Function ap 12 05 IP AL BARBBARBARARARA 48 Lead 7x7 mm QFN Package 49 mm2 PACKAGE BASE oo aa a 2 2 2 gt gt amo 2 ZZ RFOUT GND General Description The HMC1197LP7FE is a low noise high linearity Direct Quadrature Modulator with Fractional N PLL amp VCO RFIC which is ideal for digital modulation applications from 0 1 to 4 0 GHz including Cellular 3G LTE WiMAX 4G Broadband Wireless Access amp ISM circuits housed in a compact 7x7 mm LP7 SMT QFN package the HMC1197LP7FE RFIC requires minimal external components amp provides a low cost alternative to more complicated double upconversion architectures The RF output port is single ended and matched to 50 Ohms with no external components Auxiliary LO output differential or single ended enables the HMC1197LP7FE to distribute identical frequency and phase signals to multiple destinations Individual gain setti
3. o o 100 1000 10000 100000 1 10 100 1000 10000 100000 OFFSET KHz OFFSET KHz Div1 Div62 Figure 19 Auxiliary LO Output Fractional Mode Closed Loop Phase Noise 4100 MHz with various divider ratios 80 Div8 Div16 Div32 Bc Hz S E PHASE NOISE d E a o 180 100 1000 10000 100000 10 100 1000 10000 100000 OFFSET KHz OFFSET KHz Div8 Div16 Div32 Div62 Divi Div2 0 Figure 20 Auxiliary LO Output Fractional Mode Closed Loop Phase Noise 3300 MHz with various aii ratios 2 80 T _ PHASE NOISE o 180 Lin 10 100 1000 10000 100000 OFFSET KHz Div8 Div16 Div32 Div62 Divi Div2 Div4 1 Using 122 88 MHz clock input 61 44 MHz PFD 2 5 mA CP 174 uA Leakage 2 Using 100 MHz clock input 50MHz PFD 2 5 mA CP 174 uA Leakage For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com LL gt lt a LLI 0 2 lt H 10 O LL gt lt 0 s LL gt LLI Q 0 2 lt H HMC1197LP7FE MICROWAVE CORPORATION 03 0314 ey
4. Output divider settings configured in Reg 16h divide by 2 4 6 60 62 to generate frequencies from 33 MHz to 2050 MHz or divide by 1 to generate fundamental frequencies between 2050 MHz and 4100 MHz e Output gain settings Reg 16h 7 6 Reg 16h 9 8 e Single ended or differential output operation Reg 17h 9 8 e Always Mute Reg 16h 5 0 e Mute when unlock Reg 17h 7 VCO Calibration VCO Auto Calibration AutoCal The HMC1197LP7FE uses a step tuned type VCO A step tuned VCO is a VCO with a digitally selectable capacitor bank allowing the nominal center frequency of the VCO to be adjusted or stepped by switching in out VCO tank capacitors A step tuned VCO allows the user to center the VCO on the required output frequency while keeping the varactor tuning voltage optimized near the mid voltage tuning point of the HMC1197LP7FE s charge pump This enables the PLL charge pump to tune the VCO over the full range of operation with both a low tuning voltage and a low tuning sensitivity kvco The VCO switches are normally controlled automatically by the HMC1197LP7FE using the Auto Calibration feature The Auto Calibration feature is implemented in the internal state machine It manages the selection of the VCO sub band capacitor selection when a new frequency is programmed The VCO switches may also be controlled directly via register Reg 15h for testing or for other special purpose operation To use a step tuned VCO in a close
5. 03 0314 WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz Figure 2 RF Output IP3 P1dB amp Noise Floor Figure 1 RF Output Power vs Frequency 20 MHz Offset vs Frequency Over Temperature Over Temperature 40 EARTH FRIENDLY N M PB Ba a OUTPUT IP3 i a B w zH ugp ZHN 0 HOO 4 3SION LNdLNO OUTPUT POWER dBm OUTPUT P1dB dBm amp OUTPUT IP3 dBm 0 1000 2000 3000 4000 0 1000 2000 3000 4000 FREQUENCY MHz FREQUENCY MHz 25C 85C 25C 85C 40C Figure 3 Uncalibrated Carrier Feedthrough Figure 4 Calibrated Carrier Feedthrough vs Frequency Over Temperature vs Frequency Over Temperature 0 0 i o moa o o 20 10 O LL gt lt 0 LLI gt LLI Q 0 2 lt H Bo 30 40 No d 50 CARRIER FEEDTHROUGH dBm ford CARRIER FEEDTHROUGH dBm d TE o 60 70 o o 0 1000 2000 3000 4000 0 1000 2000 3000 4000 FREQUENCY MHz FREQUENCY MHz 25C 85C 40C 25C 85C 40C Figure 5 Uncalibrated Carrier Feedthrough vs Frequency Over Temperature When Modulator is Disabled Figure 6 RF Return Loss vs Frequency 20 0 30 40 a a 50 10 60 2 a z 70 Y 15
6. Frequency MHz 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 20002 Fiter Sank 1 5 0 7 8 9 10 11 15 Selection Calibrated vs Uncalibrated Test Results During the Uncalibrated Sideband and Carrier Suppression tests care is taken to ensure that the I Q signal paths from the Vector Signal Generator VSG to the Device Under Test DUT are equal The Uncalibrated Sideband and Carrier Suppression plots were measured at T 40 C 25 C and 85 C The Calibrated Sideband Suppression data was plotted after a manual adjustment of the 1 amplitude balance and I Q phase offset skew at 25 C 5V and 3 3V Vcc LO maximum power level The 25 C adjustment settings were held constant during tests over temperature The Calibrated Carrier Suppression data was plotted after a manual adjustment of the IP IN amp QP QN DC offsets at 25 C 5V and 3 3V Vcc LO maximum power level The 25 C adjustment settings were held constant during tests over temperature For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com O LL gt lt a as gt LLI Q 0 2 lt H HMC1197LP7FE MICROWAVE CORPORATION
7. Swe CHARGE FREQUENCY 2 Regt7h 02 Reg16h 10 poe ee PUMP DETECTOR Regi6h 7 6 XREFP R Reg16h 9 8 DIVIDER Reg17h 05 EN Reg17h 09 Single Ended EN LO2 N 102_ Figure 35 HMC1197LP7FE PLL VCO Block Diagram 1 1 PLL Overview The PLL divides down the VCO output to the desired comparison frequency via the N divider integer value set in Reg fractional value set in Reg 04h compares the divided VCO signal to the divided reference signal reference divider set in Reg 02h in the Phase Detector PD and drives the VCO tuning voltage via the Charge Pump CP configured in Reg 09h to the VCO subsystem Some of the additional PLL subsystem functions include e Delta Sigma configuration Reg 06h e Exact Frequency Mode Configured in Reg OCh Reg 06h Reg 03h and Reg 04h e Lock Detect LD Configuration Reg 07h to configure LD and Reg OFh to configure LD_SDO output pin e External CEN pin used as hardware enable pin Typically only writes to the divider registers integer part Reg 03h fractional part Reg 04h VCO Divide Ratio part Reg 04h are required for HMC1197LP7FE output frequency changes Divider registers of the PLL Reg 03h and Reg 04h set the fundamental frequency 2050 MHz to 4100 MHz of the VCO Output frequencies ranging from 33 MHz to 2050 MHz are generated by tuning to the appropriate fundamental VC
8. the following manner 27 cok the smallest channel VCO frequency that is greater than fy Reg04h ceil wherefy floor fyco fpp and fyco7 as shownin Figure 40 represents Example To configure the HMC1197LP7FE for Exact Frequency Mode for equally spaced intervals of 100 kHz where first channel Channel 1 fyco1 2800 200 MHz and Phase Detector PD rate fpp 61 44 MHz proceed as follows First check that the exact frequency mode for this fyco 2800 2 MHz Channel 1 and fyco2 2800 2 MHz 100 kHz 2800 3 MHz Channel 2 is possible f f fgcd 9CO fy coi fep and fogs gt ER ne foca2 9 0 2 E3 61 44 x108 000 2800 2 108 61 44 109 120510 gt 8750 6 90d 2800 3 108 61 44 10 20 10 a 3750 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com earittite HMC1197LP7FE MICHOWAVE CORPORATION CORPORATION v03 0314 RoHS v F3 EARTH FRIENDLY 1 3 8 1 4 1 5 WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz If EQ 16 is satisfied for at least two of the equally spaced interval channel frequencies fyco1 fyco2 fvco3 fvcon as it is above Hittite Exact Frequency Channel Mode is possible for all
9. 80 m ui 2 50 20 lt O 100 110 25 0 1000 2000 3000 4000 0 05 1 15 2 25 3 35 4 FREQUENCY MHz FREQUENCY GHz 25C 85C 40C 1 See note titled Calibrated vs Uncalibrated test results herein For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com earittite HMC1197LP7FE MICHOWAVE CORPORATION CORPORATION v03 0314 ra WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz Figure 8 RF Output IP3 P1dB amp Noise Floor Figure 7 RF Output Power amp SBR e 20 MHz Offset vs Frequency vs Frequency Over LO Power Over LO Power 40 EARTH FRIENDLY OUTPUT POWER OUTPUT IP3 30 20 10 F OUTPUT P1dB OLR 10 OUTPUT POWER dBm 20 SIDEBAND S PPRESSION 30 0 1000 2000 3000 4000 0 1000 2000 3000 4000 FREQUENCY MHz FREQUENCY MHz Figure 9 Uncalibrated Sideband Suppression Figure 10 Calibrated Sideband Suppression vs Frequency Over Temperature vs Frequency Over Temperature 0 0 F4 20 30 40 50 60 70 80 90 100 0 1000 2000 3000 4000 0 1000 2000 3000 4000 FREQUENCY MHz FREQUENCY MHz NOISSAYddNS aNvaaais OUTPUT P1dB dBm amp OUTPUT IP3 dBm Low 0 Medium 1 High 2
10. Max 3 Low 0 Medium 1 High 2 Max 3 SIDEBAND SUPPRESSION dBc SIDEBAND SUPPRESSION dBc 25C 85C 40C 25C 85C 40C Figure 12 RF Output IP3 P1dB amp NoiseFloor Figure 11 RF Output Power amp SBR 20 MHz Offset vs Frequency vs Frequency Over Supply Voltage Over Supply Voltage OUTPUT POWER g 8 s v i 20 E A E zZ gt 20 Ini A 2 5 E 8 1 3 5 P Eo OUTPUT P1dB 9 o 5 S o 10 SIDEBAND SUPPRESSION 5 20 E 0 1000 2000 3000 4000 30 FREQUENCY MHz 0 1000 2000 3000 4000 FREQUENCY MHz 4 75V 5 0V 5 25V 4 75V 5 00V 5 25V 1 See note titled Calibrated vs Uncalibrated test results herein For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com O LL gt lt D gt m 0 2 lt or H 10 O LL gt lt 0 s LL gt LLI Q 0 2 lt H ESMittite HMC1197LP7FE MICROWAVE CORPORATION 03 0314 4 WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz Figure 14 RF Output Noise EARTH FRIE
11. section e Or reading from Reg 12h 1 where Reg 12h 1 1 indicates locked and Reg 12h 1 0 indicates an unlocked condition The LD circuit expects the divided VCO edge and the divided reference edge to appear at the PD within a user specified time period window repeatedly Either signal may arrive first only the difference in arrival times is significant The arrival of the two edges within the designated window increments an internal counter Once the count reaches and exceeds a user specified value Reg 07h 2 0 the HMC1197LP7FE declares lock Failure in registering the two edges in any one window resets the counter and immediately declares an un locked condition Lock is deemed to be reestablished once the counter reaches the user specified value Reg 07h 2 0 again Lock Detect Configuration Optimal spectral performance in fractional mode requires CP current and CP offset current configuration discussed in detail in section 1 3 1 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com earittite HMC1197LP7FE MICHOWAVE CORPORATION CORPORATION v03 0314 ra WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY These settings in Reg 09h impact the required LD window size in
12. 10 3 R W Reserved 8 16d Reserved 0 AutoCal Enabled 1 AutoCal disabled 12 R W Reserved 1 0 Reserved Set the AutoCal FSM and VSPI Clock 50 MHz maximum 0 Input Crystal Reference 14 13 R W FSM VSPI Clock Select 2 1 1 Input Crystal Reference 4 2 Input Crystal Reference 16 3 Input Crystal Reference 32 11 R W AutoCal Disable 1 0 O LL gt lt D gt m O 0 2 lt or H 16 15 R W Reserved 2 0 Reserved 0 Does not attempt to relock if lock is lost 17 R W Auto relock one Try 1 0 1 Attempts to relock if Lock Detect fails for any reason Only tries once 23 18 R W Reserved 5 0 Reserved For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com 10 LL gt lt a N 22 gt LLI Q 0 2 lt H HMC1197LP7FE MICROWAVE CORPORATION 03 0314 ae WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY 2 13 Reg OBh PDICP Register DEFAULT 78061 h BIT TYPE NAME Width Default DESCRIPTION 3 0 R W Reserved 4 1 Reserved Inverts the PD polarity program to 0 0 Use with a positive tuning slope VCO and Passive Loop Filter default when using inte
13. 4000 MHz EARTH FRIENDLY 2 22 Reg 16h Gain Divider Register Default 6C1 h BIT TYPE NAME Width Default DESCRIPTION 0 Mute VCO and PLL buffer On RF output stages Off 1 Fo 2 Fo 2 3 invalid defaults to 2 4 Fo 2 x 5 invalid defaults to 4 5 0 R W RF Divide Ratio 6 1 6 Fo 6 60 Fo 60 61 invalid defaults to 60 62 Fo 62 gt 62 invalid defaults to 62 Max Gain Max Gain dB Max Gain 6 dB Max Gain 9 dB LO Output Buffer Gain 7 6 RIN Control Max Gain Max Gain 3 dB Max Gain 6 dB Max Gain 9 dB LO2 Output Buffer gain 9 8 EUN Control O mcoj o nmnmco Divider Output Stage Gain 1 Max Gain 10 R W Control 0 Max Gain 3 dB 10 O LL gt lt C D m gt m O 0 2 lt or H 23 11 R W Reserved 13 0 Reserved For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com t JHittite HMC1197LP7FE MICROWAVE CORPORATION CORPORATION 03 0314 WIDEBAND DIRECT QUADRATURE MODULATOR 7 w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY 2 23 Reg 17h Modes Register Default 1AB h BIT TYPE NAME Width Default DESCRIPTIO
14. LL gt LLI Q 0 2 lt H wAittite HMC1197LP7FE MICROWAVE CORPORATION 03 0314 RoHS EARTH FRIENDLY 1 6 WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz It is also possible to leave various blocks on when in Power Down see Reg 01h including a Internal Bias Reference Sources Reg 01h 2 b PD Block Reg 01h 3 c CP Block Reg 01h 4 d Reference Path Buffer Reg O1h 5 e VCO Path buffer Reg O1h 6 f Digital I O Test pads Reg 01h 7 To mute the output but leave the PLL and VCO locked please refer to 1 2 4 section General Purpose Output GPO Pin The PLL shares the LD SDO Lock Detect Serial Data Out pin to perform various functions While the pin is most commonly used to read back registers from chip via the SPI it is also capable of exporting a variety of signals and real time test waveforms including Lock Detect It is driven by a tri state CMOS driver with 200 O Rout It has logic associated with it to dynamically select whether the driver is enabled and to decide which data to export from the chip In its default configuration after power on reset the output driver is disabled and only drives during appropriately addressed SPI reads This allows it to share the output with other devices on the same bus The pin driver is enabled if the chip is addressed ie The last 3 bits of SPI cycle 000 b before the rising edge of SEN If SEN rises before SCK has cl
15. _ Reference to GND Junction Temperature 150 C Thermal Resistance Ry P junction to ground paddle FION Storage Temperature 65 to 150 C Operating Temperature 40 to 85 C ESD Sensitivity HBM 1C Outline Drawing TOP VIEW BOTTOM VIEW PIN 48 280 256 012 0 31 022 6 T 272 6 90 7 007 93 i4 017 0 44 B UUUUUUUUUUUU 1 36 q D C r gt q g D H1197 eae d SN OO ce NN XXXX A7 5 ae D NN Te D C D 12 25 a C nnannannnnng gt LOT NUMBER 012 0 30 REF db 5 016 0 40 REF 1031 0 80 NOTES 007 935 1 PACKAGE BODY MATERIAL LOW STRESS INJECTION MOLDED PLASTIC SILICA s AND SILICON IMPREGNATED i ME 2 LEAD AND GROUND PADDLE MATERIAL COPPER ALLOY C3 005 0 08 C C 8 LEAD AND GROUND PADDLE PLATING 100 MATTE TIN 4 DIMENSIONS ARE IN INCHES MILLIMETERS 5 LEAD SPACING TOLERANCE IS NON CUMULATIVE 6 CHARACTERS TO BE HELVETICA MEDIUM 025 HIGH WHITE INK OR LASER MARK LOCATED APPROX AS SHOWN 7 PAD BURR LENGTH SHALL BE 0 15mm MAX PAD BURR HEIGHT SHALL BE 0 25mm MAX 8 PACKAGE WARP SHALL NOT EXCEED 0 05mm 9 ALL GROUND LEADS AND GROUND PADDLE MUST BE SOLDERED TO PCB RF R 10 REFER TO HITTITE APPLICATION NOTE FOR SUGGESTED PCB LAND PATTERN Table 7 Package Information Part Number Package Body Material Lead Finish MSL Rating Package Marking P er 1197 HMC1197LP7FE RoHS compliant Low Stress Injec
16. gt lt C Call CP1 4 Charge Y oLOP 2 Detector 1 1 2 62 XREFP m gt O Lu lt RFOUT M The HMC1197LP7FE is a low noise high linearity Direct Quadrature Modulator with Fractional N PLL amp VCO RFIC designed for directly converting complex modulated baseband signals from zero IF or low IF to RF transmission levels from 100 MHz to 4 GHz The HMC1197LP7FE s excellent noise and linearity performance makes it suitable for a wide range of transmission standards including single and multicarrier CDMA UMTS CDMA2000 GSM EDGE W CDMA TD SCDMA and WiMAX LTE applications As shown in the simplified block diagram Figure 43 the HMC1197LP7FE offers an easy to use complete direct conversion solution in a highly compact 7 x 7 mm plastic package thereby reducing cost area and power consumption The HMC1197LP7FE modulator consists of the following functional blocks 1 PLL amp VCO 1 0 Theory of Operation 2 modulator and input differential voltage to current converters and upconverting mixers and the differential to single ended converter high Accuracy LO quadrature phase splitter and LO limiting amplifiers 3 Harmonic Low Pass Filter 3 2 I Q Modulator The differential baseband inputs QP QN IP and IN present a high impedance The DC common mode voltage at the baseband inputs sets the currents in the and Q double balanced mixers The
17. where the magnitude of the offset is set by Reg 09h 20 14 and the direction is selected by Reg 09h 21 1 for up and Reg 09h 22 1 for down offset CP Gain is used at all times while CP Offset is only recommended for fractional mode of operation Typically the CP Up and Down gain settings are set to the same value Reg 09h 13 7 Reg 09h 6 0 UP Offset Reg09 21 UP Gain j 0 635uA Reg09 13 7 1 0 2 54mA 5uA Step 20uA Step Reg09 20 14 UP REF PATH PD e Filter VCO PATH DN DN Offset Reg09 22 DN Gain 0 635uA Reg09 6 0 1 5uA Step 0 2 54mA Reg09 20 14 20uA Step Figure 38 Charge Pump Gain amp Offset Control Charge Pump Gain Charge pump Up and Down gains are set by Reg 09h 13 7 and Reg 09h 6 0 respectively The current gain of the pump in Amps radian is equal to the gain setting of this register divided by 2rr Typical CP gain setting is set to 2 to 2 5 mA however lower values can also be used Values 1 mA may result in degraded Phase Noise performance For example if both Reg 09h 13 7 and Reg 09h 6 0 are set to 50d the output current of each pump will be 1 mA and the phase frequency detector gain k 1 mA 2r radians or 159 pA rad For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Sup
18. Down Mode description for more information 2 R W Keep Bias On 1 0 keeps internal bias generators on ignores Chip enable control 3 R W Keep PFD Pn 1 0 keeps PFD circuit on ignores Chip enable control 4 R W Keep CP On 1 0 keeps Charge Pump on ignores Chip enable control 5 R W Keep Reference Buffer ON 1 0 keeps Reference buffer block on ignores Chip enable control 6 R W Keep VCO on 1 0 keeps VCO divider buffer on ignores Chip enable control 7 R W Keep GPO Driver ON 1 0 keeps GPO output Driver ON ignores Chip enable control 9 8 R W Reserved 2 0 reserved 2 4 Reg 02h REFDIV Register DEFAULT 1h Bit Type Name Width Default Description Reference Divider R Value EQ 8 13 0 R W rdiv 14 1 min 1 max max 214 1 3FFFh 16383d 2 5 Reg 03h Frequency Register Integer Part DEFAULT 19h Bit Type Name Width Default Description Divider Integer part used in all modes see EQ 10 Fractional Mode min 20d 18 0 R W Integer Setting 19 Fu max 219 4 7FFFCh 524 284d Integer Mode min 16d max 219 1 7FFFFh 524 287d For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com HMC1197LP7FE MICROWAVE CORPORATION 03 0314 a WIDEBAND DIRECT QUADRATURE MODULATOR S w Fractiona
19. MODULATOR E w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY Table 1 Electrical Specifications See Test Conditions on page 4 Parameter Typ Typ Typ Typ Units Frequency Range RF 450 960 1700 2200 2200 2700 3400 4000 MHz Output Power 2 0 14 1 3 3 2 dBm Conversion Voltage Gain 6 0 5 1 5 3 7 2 dB Output P1dB 10 5 10 5 10 9 5 dBm Output Noise Floor 159 5 157 0 156 5 156 5 dBm Hz Output IP3 28 5 26 5 26 0 23 5 dBm ree hia ala 40 37 0 33 5 34 5 ue um 45 45 43 30 5 dBc RF Port Return Loss 12 5 15 16 16 dB Table 2 Electrical Specifications Continued LL gt lt a or gt LLI Q z lt H Parameter Conditions Min Typ Max Units RF Output RF Frequency Range 100 4000 MHz RF Return Loss 15 dB Baseband Input Port Baseband Input DC Voltage Vbbdc 0 5 0 4 to 0 6 V Baseband Input DC Bias Current Ibbdc Single ended 110 pA Single ended Baseband Input Capacitance De embed to the lead of the device 4 5 pF DC Power Supply Supply Voltage VCC1 VCC2 VCC3 VDDLS VDDCP BIAS IF1P 4 75 5 0 5 25 V Modulator ON and PLL ON 320 mA Supply Current of 5V Supply I Modulator OFF and PLL ON 152 mA Modulator OFF and PLL OFF 12 mA DVDD RVDD VCCPD 315 13 3 3 45 v Modulator ON and PLL ON 48 mA Supp
20. Min Max Recommended Min Max 10 YES 0 6 2 5 x x x 10 YES 0 6 2 5 x x x 25 YES 0 6 2 5 ok 8 15 50 YES 0 6 2 5 YES 6 15 100 YES 0 6 2 5 YES 5 15 150 ok 0 9 2 5 YES 4 12 200 ok 12 2 5 YES 3 8 Input referred phase noise of the PLL when operating at 50 MHz is between 148 and 150 dBc Hz at 10 kHz offset depending upon the mode of operation The input reference signal should be 10 dB better than this floor to avoid degradation of the PLL noise contribution It should be noted that such low levels are only necessary if the PLL is the dominant noise contributor and these levels are required for the system goals Reference Path R Divider The reference path R divider is based on a 14 bit counter and can divide input signals by values from 1 to 16 383 and is controlled via Reg 02h RF Path N Divider The main RF path divider is capable of average divide ratios between 219 5 524 283 and 20 in fractional mode and 219 1 524 287 to 16 in integer mode Lock Detect The Lock Detect LD function indicates that the HMC1197LP7FE is indeed generating the desired frequency It is enabled by writing Reg 07h 11 1 The HMC1197LP7FE provides LD indicator in one of two ways e As an output available on the LD_SDO pin of the HMC1197LP7FE Configuration is required to use the LD_SDO pin for LD purpose for more information please see 1 8 Serial Port Open Mode and 1 3 5 3 Configuring LD_SDO Pin for LD Output
21. Phone 978 250 3343 or apps hittite com O LL gt lt D gt m O 0 2 lt or H LL gt lt a 0 s LL gt LLI Q 0 2 lt H wAittite HMC1197LP7FE MICROWAVE CORPORATION 03 0314 WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY Reg 04h round 0 1 x 224 round 1677721 6 1677722 50e6 1677722 fico 56 2805 MHz 1 192 Hz error 14 fyco fout 1402 5 MHz 0 596 Hz error EQ 15 In this example the output frequency of 1402 5 MHz is achieved by programming the 19 bit binary value of 56d 38h into intg_reg in Reg 03h and the 24 bit binary value of 1677722d 19999Ah into frac_reg in Reg 04h The 0 596 Hz quantization error can be eliminated using the exact frequency mode if required In this example the VCO output fundamental 2805 MHz is divided by 2 Reg 16h 5 0 2h 1402 5 MHz 1 3 7 5 Exact Frequency Tuning Due to quantization effects the absolute frequency precision of a fractional PLL is normally limited by the number of bits in the fractional modulator For example a 24 bit fractional modulator has frequency resolution set by the phase detector PD comparison rate divided by 224 The value 224 in the denominator is sometimes referred to as the modulus Hittite PLLs use a fixed modulus which is a binary number In some types of fractional PLLs the modulus is
22. QPSK For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com earittite HMC1197LP7FE MICHOWAVE CORPORATION CORPORATION v03 0314 ra WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz 3 10 Using an External VCO In order to configure HMC1197LP7FE to use with an external VCO Register 17 needs to be configured to disable the on chip VCO and VCO to PLL path Enable External Buffer second CP link and External I O switch To make these changes Reg 17 0 11 should be configured as 3157d HMC1197LP7FE is configured as PLL alone used with External VCO HMC384LP4E Loop Filter components are used as in Figure 53 R45 R48 820 820 CP1 e e e 219657 R46 L C55 67 22pF 1 8K 39pF T 39pF C49 z T 0 001uF Figure 53 Loop filter components for HMC1197LP7FE is configured as PLL alone used with external VCO HMC384LP4E A e co 100 PHASE NOISE dBc Hz 1 10 100 1000 10000 OFFSET KHz Figure 54 Closed Loop Phase Noise with External HMC384LP4E VCO 2200 MHz For detailed theory of operation of PLL VCO please refer to the PLLs with Integrated VCOs RF VCOs Operating Guide For price delivery and to place orders Hittite Microwave Corporation 2 Eliza
23. as cycle slipping Cycle slipping causes the pull in rate during the locking phase to vary cyclically Cycle Slipping increases the time to lock to a value greater than that predicted by normal small signal Laplace analysis 10 O LL gt lt 0 s LL gt LLI Q 0 2 lt H The HMC1197LP7FE PD features an ability to reduce cycle slipping during frequency tunning The Cycle Slip Prevention CSP feature increases the PD gain during large phase errors 1 3 7 Frequency Tuning HMC1197LP7FE VCO subsystem always operates in fundamental frequency of operation 2050 MHz to 4100 MHz The HMC1197LP7FE generates frequencies below its fundamental frequency 33 MHz to 2050 MHz by tuning to the appropriate fundamental frequency and selecting the appropriate Output Divider setting divide by 2 4 6 60 62 in Reg 16h 5 0 The HMC1197LP7FE automatically controls frequency tuning in the fundamental band of operation for more information see 1 2 1 VCO Calibration To tune to frequencies below the fundamental frequency range lt 2050 MHz it is required to tune the HMC1197LP7FE to the appropriate fundamental frequency then select the appropriate output divider setting divide by 2 4 6 60 62 in Reg 16h 5 0 1 3 71 Integer Mode The HMC1197LP7FE is capable of operating in integer mode For Integer mode set the following registers a Disable the Fractional Modulator Reg 06h 11 0 b Bypass the Modulator circu
24. desired channel frequencies and can be configured as follows 2800 2 10 f floor 601 floor 45d 2Dh is Bedui ES fep 61 44 x108 6 6 2 BHegOCh 61 44 10 61 44x10 _ 30720 COOh 9 ged t00 109 61 44100 20000 where fycoxs1 is the desired channel spacing 100 kHz in this example 3 To program Reg 04h the closest integer N boundary frequency fy that is less than the smallest channel VCO frequency fyco must be calculated fy floor fyco7 fpp Using the current example 2800 2x108 fy fpp xfloor 45 x 61 44 x 108 2764 8 MHz Then 61 44x108 ficos E fy PD 2 Reg 04h E for channel 1 where 2800 2 MHz 224 2800 2x10 2764 8x10 6144x408 96665600 938000h x ceil 4 change from channel 1 fyco 2800 2 MHz to channel 2 fyco2 2800 3 MHz only Reg 04h needs to be programmed as long as all of the desired exact frequencies fyco Figure 40 fall between the same integer N boundaries fy lt fycox lt fy 1 In that case 224 2800 3 109 2764 8 108 6144x108 9693867 93EAABh_ and soon x Reg 04h ceil Seed Register The start phase of the fractional modulator digital phase accumulator DPA may be set to any desired phase relative to the reference frequency The phase is programmed in Reg 1Ah and Exact Frequency Mode is required Phase 2n x Reg1Ah 2 via the seed re
25. evaluation circuit board shown is available from Hittite upon request Evaluation PCB Schematic To view this Evaluation PCB Schematic please visit www hittite com and choose HMC1197LP7FE from the Search by Part Number pull down menu to view the product splash page Table 9 Evaluation Order Information Item Contents Part Number Evaluation PCB Only HMC1197LP7FE Evaluation PCB EVALO1 HMC1197LP7F HMC1197LP7FE Evaluation PCB USB Interface Board Evaluation Kit 6 USB A Male to USB B Female Cable EKITO1 HMC1197LP7F CD ROM Contains User Manual Evaluation PCB Schematic Evaluation Software Hittite PLL Design Software For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com earittite HMC1197LP7FE MICHOWAVE CORPORATION CORPORATION v03 0314 ra WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY 1 0 Theory of Operation The block diagram of HMC1197LP7FE PLL with Integrated VCO is shown in Figure 35 EXT_VCO_P EXT_VCO_N VTUNE vco CAL LOOP Reg15h 09 FILTER VOLTAGE Reg17h 06 Regt7n 01 EN Real 79003 Single Ended EN EN Regi7h 04 Regt 7h 08 Regi7h 11 EN CP1 N i 10 DIVIDER PHASE tm i LO_N 2 4 6 62
26. fractional mode of operation To function the required lock detect window size is provided by EQ 10 lome A _ 2 66 x10 sec Fpp Hz x Iop A Fro Hz LD Window seconds 5 in Fractional Mode EQ 10 LD Window seconds in Integer Mode x where Fpp is the comparison frequency of the Phase Detector lop offset S the Charge Pump Offset Current Reg O9h 20 14 Icp is the full scale current setting of the switching charge pump Reg O9h 6 0 or Reg 09h 13 7 If the result provided by EQ 10 is equal to 10 ns Analog LD can be used Reg 07h 6 0 Otherwise Digital LD is necessary Reg 07h 6 1 Table 12 provides the required Reg 07h settings to appropriately program the Digital LD window size From Table 12 simply select the closest value in the Digital LD Window Size columns to the one calculated in EQ 10 and program Reg 07h 9 8 and Reg 07h 7 5 accordingly Table 12 Typical Digital Lock Detect Window LD Timer Speed Digital Lock Detect Window Size Reg07 9 8 Nominal Value ns Fastest 00 6 5 8 11 17 29 53 100 195 01 7 8 9 12 8 21 36 68 130 255 10 74 9 2 13 3 22 38 72 138 272 Slowest 11 7 6 10 2 15 4 26 47 88 172 338 EE Bo on 000 001 010 011 100 101 110 111 1 3 5 2 Digital Window Configuration Example Assuming fractional mode with a 50 MHz PD and e Charge Pump gain of 2 mA Reg 09h 13 7 64h Reg O9h 6 0 64h e Down Offs
27. in the SPI shifter should be held constant for at least 2 PFD clock periods after SEN is asserted to allow this retiming to happen cleanly Exact Frequency Mode 1 Exact Frequency Mode Enabled 5 RA Enable 1 0 0 Exact Frequency Mode Disabled 6 R W Reserved 1 0 Reserved 0 Use Modulator Required for Fractional Mode 1 Bypass Modulator Required for Integer Mode Note When enabled fractional modulator output is ignored but 7 R W Fractional Bypass 1 0 i fractional modulator continues to be clocked if Reg O6h 11 1 This feature can be used to test the isolation of the digital frac tional modulator from the VCO output in integer mode 1 loads the modulator seed start phase whenever the fractional 6 FN XRucss d E 7 register Reg 04h is written 0 when fractional register Reg 04h write changes frequency modulator starts at previous value phase 10 9 R W Reserved 2 3 Reserved 11 R W Delta Sigma Modulator 1 1 0 Disable DSM used for Integer Mode Enable 1 Enable DSM Core required for Fractional Mode 23 12 R W Reserved 12 en Reserved For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com t JHittite HMC1197LP7FE MICROWAVE CORPORATION CORPORATION 03 0314 WIDEBAND DIRECT QUADRAT
28. line 9 FM PISHDIGINRET 9 Prevents conflicts on the SPI bus 23 10 R W Reserved 14 0 Reserved 2 16 Reg 10h Tuning Register DEFAULT 80 h BIT TYPE NAME Width Default DESCRIPTION VCO selection resulting from AutoCalibration 7 0 R VCO Tune Curve 8 i 0 maximum frequency 1111 1111 b minimum frequency Indicates if the VCO tuning is in process 8 R VCO Tuning Busy 1 0 1 Busy 0 Not Busy For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com LL gt lt a or gt LLI Q z lt H HMC1197LP7FE MICROWAVE CORPORATION 08 0314 RoHS WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY 2 17 Reg 11h SAR Register Read Only BIT Width Default DESCRIPTION 19 dp 18 0 R SAR Error Magnitude Count 19 SAR Error Magnitude Count SAR Error Sign LL 19 R SAR Error Sign 1 0 0 positive 1 negative x 23 20 R Reserved 4 0 Reserved 2 18 Reg 12h GPOILD Register Read Only BIT TYPE NAME Width Default DESCRIPTION n 0 R GPO Out 1 0 GPO Output gt 1 R L
29. loss of the low pass filter For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com LL gt lt a or gt LLI Q z lt H 10 O LL gt lt a 0 s LL gt LLI Q 0 2 lt H HMC1197LP7FE MICROWAVE CORPORATION 03 0314 WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY INSERTION LOSS dB 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 FREQUENCY MHz Figure 45 Insertion loss of the low pass filter LO harmonic filters 16 user programmable bands enable the user to optimally attenuate 2 and or 3 LO harmonics in order to maximize sideband rejection performance Table 15 The frequency band selection for optimal 3 harmonic attenuation Bis 500 600 900 1000 1100 1200 1300 1400 1500 1600 1700 21800 eller Bank 0 1 4 6 7 8 9 11 12 13 13 14 15 Selection Table 16 The frequency band selection for optimal 2 harmonic attenuation us 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 2600 22700 Filter Bank 0 1 4 5 7 8 9 10 1 12 13 14 15 Selection Uncalibrated si
30. m 0 n 5 provides 781 kHz of resolution and adds 8 6 us of AutoCal time to a normal frequency hop Once the AutoCal sets the final switch value 8 64 us after the frequency change command the fractional register will be loaded and the loop will lock with a normal transient predicted by the loop dynamics Hence as shown this example that AutoCal typically adds about 8 6 us to the normal time to achieve frequency gt lock Hence AutoCal should be used for all but the most extreme frequency hopping requirements Table 10 AutoCal Example with F 50 MHz R 1 0 2 O S SON RO 0 0 1 0 02 4 92 25 MHz ac 1 1 2 0 04 5 04 12 5 MHz 2 2 4 0 08 5 28 6 25 MHz 3 3 8 0 16 5 76 3 125 MHz 4 5 32 0 64 8 64 781 kHz 5 6 64 1 28 12 48 390 kHz 6 7 128 2 56 20 16 195 kHz 7 8 256 5 12 35 52 98 kHz 1 2 1 5 Manual VCO Calibration for Fast Frequency Hopping If it is desirable to switch frequencies quickly it is possible to eliminate the AutoCal time by calibrating the VCO in advance and storing the switch number vs frequency information in the host This can be done by initially locking the HMC1197LP7FE on each desired frequency using AutoCal then reading and storing the selected VCO switch settings The VCO switch settings are available inReg 15h 8 1 after every AutoCal operation The host must then program the VCO switch settings directly when changing frequencies Manual writes to the
31. nominal baseband input DC common mode voltage used in the characterization of the HMC1197LP7FE is 0 45V which should be externally applied The baseband input DC common mode voltage can be varied between 0 4V and 0 5V to optimize overall modulator performance It is not recommended to leave the baseband For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com earittite HMC1197LP7FE MICHOWAVE CORPORATION CORPORATION v03 0314 RoHS v F3 EARTH FRIENDLY 3 3 WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz inputs floating which generates excessive current flow that may cause damage to the IC The baseband inputs should be pulled down to GND in shutdown mode The nominal baseband input AC Voltage used in the characterization of the HMC1197LP7FE is 1 3Vpp differential The baseband input AC voltage can be varied to optimize overall modulator performance It is recommended to drive the baseband inputs differentially to reduce even order distortion products and also use reconstruction filters at the baseband inputs to avoid aliasing modulator includes a LO quadrature phase splitter that generates two carrier signals in quadrature followed by LO limiting amplifiers which are used to drive the and Q mixers with satu
32. parts 9 6 R W Reserved 4 15d Reserved 0 VCO Buffer and Prescaler Bias Disable 10 R W nd ciii ied 1 id 1 VCO Buffer and Prescaler Bias Enable Only applies to External VCO 20 11 R W Reserved 10 55d Reserved 21 R W High Frequency Reference 1 0 Program to 1 for XTAL 200 MHz 0 otherwise Output Logic Level on LD SDO pin 22 R W SDO Output Level 1 0 0 1 8 V Logic Levels 1 DVDDSV Logic Level 23 R W Reserved 1 Od Reserved For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com LL gt lt a gt LLI Q z lt H 10 O LL gt lt 0 s LL gt LLI Q 0 2 lt H HMC1197LP7FE MICROWAVE CORPORATION 08 0314 4 WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY 2 11 Reg 09h Charge Pump Register DEFAULT 547264 h Bit Type Name Width Default Description Charge Pump DN Gain Control 20 uA4step Affects fractional phase noise and lock detect settings 100d 9 0 6 0 R W CP DN Gain 7 64h 1d 20 pA 2d 40 pA 127d 2 54mA Default 2mA Charge Pump UP Gain Control 20 pA per step Affects fractional phase noise and lock detect settings 09 0 13 7
33. to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com O LL gt lt D gt m O 0 2 lt oc H 10 O LL gt lt 0 s LL gt LLI Q 0 2 lt H ESMittite HMC1197LP7FE MICROWAVE CORPORATION 03 0314 4 WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz 3 8 W CDMA Operation The HMC1197LP7FE is suitable for W CDMA operation Figure 51 shows the adjacent and alternate channel power ratios for the HMC1197LP7FE at an LO frequency of 2140 MHz The HMC1197LP7FE is able to deliver about 72 dBc ACPR and 77 dBc AItCPR at an output power of 10 dBm ACPR and AItCPR performances of the HMC1197LP7FE can be improved by adjusting the DC common mode level on the and Q baseband inputs ACPR and AItACPR dB 35 30 25 20 15 10 5 0 OUTPUT POWER dBm ACPR AItACPR Figure 51 The HMC1197LP7FE ACPR and AItCPR vs Output Power WCDMA 3 9 LTE Operation The HMC1197LP7FE is suitable for LTE applications The EVM performance of the HMC1197LP7FE in a LTE environment is shown in Figure 52 EVM rms 15 12 9 6 3 0 3 OUTPUT POWER dBm 700 MHz 1700 MHz Figure 52 The HMC1197LP7FE EVM vs Output Power LTE Downlink 25RB
34. would occur at multiples of the channel spacing The Hittite method on the other hand is able to generate exact frequencies between adjacent integer N boundaries while still using the full 24 bit phase accumulator modulus thus achieving exact frequency steps with a high phase detector comparison rate which allows Hittite PLLs to maintain excellent phase noise and spurious performance in the Exact Frequency Mode 1 3 7 6 Using Hittite Exact Frequency Mode If the constraint in EQ 16 is satisfied HMC1197L P7FE is able to generate signals with zero frequency error at the desired VCO frequency Exact Frequency Mode may be re configured for each target frequency or be set up for a fixed fy oq which applies to all channels 1 3 7 6 1 1 Configuring Exact Frequency Mode For a Particular Frequency 1 Calculate and program the integer register setting Reg 03h floor fyco fpp where the floor function is the rounding down to the nearest integer Then the integer boundary frequency fy Nin fep 2 Calculate and program the exact frequency register value Reg OCh fpp fgcg where fgca K fy fep 3 Calculate and program the fractional register setting Reg 04h where ceil is the ceiling function meaning round up to the nearest integer Example To configure the HMC1197LP7FE for exact frequency mode at fyco 2800 2 MHz where Phase Detector PD rate fpp 61 44 MHz Pro
35. 2 16 fin N gt 20 0 fiac where N fycoy fpa b fog lt 100 MHz For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com earittite HMC1197LP7FE MICHOWAVE CORPORATION CORPORATION v03 0314 ra WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY Suppose the HMC1197LP7FE output frequency is to operate at 2 01 GHz Our example crystal frequency iS 50 MHz R 1 and m 0 Figure 37 hence Trsy 20 ns 50 MHz Note when using AutoCal the maximum AutoCal Finite State Machine FSM clock cannot exceed 50 MHz see Reg OAh 14 13 The FSM clock does not affect the accuracy of the measurement it only affects the time to produce the result 5 This same clock is used to clock the 16 bit VCO serial port If time to change frequencies is not a concern then one may set the calibration time for maximum accuracy x and therefore not be concerned with measurement resolution Using an input crystal of 50 MHz R 1 and fpd 50 MHz the times and accuracies for calibration using EQ 6 and EQ 8 are shown in Table 10 Where minimal tuning time is 1 8 of the VCO band spacing Across all VCOs a measurement resolution better than 800 kHz will produce correct results Setting j
36. 8 0314 RoHS WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY Figure 33 Auxiliary LO Differential Output Figure 34 Auxiliary LO Single Ended Output Return Loss Return Loss 0 0 RETURN LOSS dB a RETURN LOSS dB a 100 1000 100 1000 OUTPUT FREQUENCY MHz OUTPUT FREQUENCY MHz Table 5 Loop Filter Configuration Loop Filter C1 C2 c3 Re RE p Loop Filter Design BW kHz pF nF pF pF R R4 VTUNE capi R2 C1 c3 C4 156 180 6 8 47 47 2 2 1 1 E 1 62 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com t JHittite HMC1197LP7FE MICROWAVE CORPORATION CORPORATION 03 0314 ba WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY Table 6 Absolute Maximum Ratings ELECTROSTATIC SENSITIVE DEVICE VDDCP BIAS IF1P EN MOD 0 3V to 5 5V OBSERVE HANDLING PRECAUTIONS V3 DVDD RVDD VCCPD _ VCCPS VCCHF Baseband Input Voltage AC
37. ANALOG Mittite DEVICES MICROWAVE PRODUCTS FROM ANALOG DEVICES Analog Devices Welcomes Hittite Microwave Corporation NO CONTENT ON THE ATTACHED DOCUMENT HAS CHANGED www analog com www hittite com THIS PAGE INTENTIONALLY LEFT BLANK LL gt lt aa LL gt 0 2 lt H MICROWAVE CORPORATION v03 0314 HMC1197LP7FE ba WIDEBAND DIRECT QUADRATURE MODULATOR E w Fractional N PLL amp VCO 100 4000 MHz Typical Applications Features The HMC1197LP7FE is Ideal for Multiband Multi standard Cellular BTS Diversity Transmitters Fixed Wireless or WLL SM Transceivers 900 amp 2400 MHz Very Low Noise Floor 159 5 dBm Hz Excellent Carrier amp Sideband Suppression Very High Linearity 28 5 dBm OIP3 High Output Power 10 5 dBm Output P1dB High Modulation Accuracy GMSK QPSK QAM SSB Modulators Multiband Basestations amp Repeaters Functional Diagram Maximum Phase Detector Rate 100 MHz Low Phase Noise 110 dBc Hz in Band Typical PLL FOM Ca wm 230 dBc Hz Integer Mode 227 dBc Hz Fractional SeSSSRESS as as Mode FRERBERBE 3 E lt 180 fs Integrated RMS Jitter 1 kHz to 20 MHz VDDCP 1 Control 36 VTUNE
38. CRIPTION 21697d 18 0 R W Reserved 19 1 Reserved External Input buffer BIAS 19 R W 1 0 External Input buffer BIAS bitO bito External Input buffer BIAS 20 R W 1 0 External Input buffer BIAS bit1 bit1 23 21 R W Reserved 3 0 Reserved 2 25 Reg 19h Cals Register Default AAA h BIT TYPE NAME Width Default DESCRIPTION 23 0 R W Reserved 2 MUR Reserved Program to AB2h For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com O LL gt lt a 0 gt LLI Q 0 2 lt H 10 LL gt lt 0 s LL gt LLI Q 0 2 lt H HMC1197LP7FE MICROWAVE CORPORATION 03 0314 4 WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY 2 26 Reg 1Ah Seed Register Default B29DOBh BIT TYPE NAME Width Default DESCRIPTION Used to program output phase relative to the reference frequency Exact Frequency Mode required When not using Exact Frequency Delta Sigma Modulator 24 11705611d Mode and Auto seed Enable RegO6h 8 1 Reg1Ah sets the start Seed B29DOBh phase of output signal If AutoSeed disable RegO6h 8 20 Reg1Ah is the start phase of the signal after every frequency ch
39. LLI Q 0 2 lt H E JHittite HMC1197LP7FE MICROWAVE CORPORATION 03 0314 4 WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY CARRIER FEEDTHROUGH dBm 0 1000 2000 3000 4000 FREQUENCY MHz 25C 85C 40C Figure 47 The HMC1197LP7FE Calibrated Carrier Feedthrough 3 5 Sideband Suppression Calibration Sideband suppression is related to relative gain and relative phase offsets between the l channel and Q channel The amplitude and phase difference between the and Q inputs can be adjusted in order to optimize the sideband suppression for a specific frequency band and LO power level The amplitude and phase offsets at the and Q inputs should be iteratively adjusted until a minimum sideband suppression level is obtained The externally available amplitude and phase steps and the modulator s noise floor limit the minimum achievable calibrated sideband suppression level Figure 48 illustrates the typical calibrated sideband suppression performance of the HMC1197LP7FE In this characterization of the HMC1197LP7FE sideband suppression was calibrated at every 500MHz LO frequency steps at 25C and external amplitude and phase offset settings were held constant during tests over temperature SIDEBAND SUPPRESSION dBc 0 1000 2000 3000 4000 FREQUENCY MHz 25C 85C 40C Figure 48 The HMC1197LP7FE Calibrated Sideband Suppr
40. N Master enable for the entire VCO Subsystem 1 Enable 0 R W VCO SubSys Master Enable 1 1 0 Disable Chip Enable is also required to set as enable mode 1 R W VCO Enable 1 1 R W External VCO Buffer Enable 1 0 External VCO Buffer to output stage enable Only used when locking an external VCO 3 R W PLL Buffer Enable 1 1 PLL Buffer Enable Used when using an internal VCO 4 R W LO1 Output Buffer Enable 1 0 Enables LO1 LO_P amp LO_N pins output buffer 5 R W LO2 Output Buffer Enable 1 1 Enables the LO2 LO2_N amp LO2_P pins output buffer 6 R W External Input Enable 1 0 Enables External VCO input 7 R W Pre Lock Mute Enable 1 1 Mute both output buffers until the PLL is locked Enables Single Ended output mode for LO output i 1 Single ended mode LO_N pin is enabled and LO P pin is 8 R W LOJ AE Ended 1 1 disabled 0 Differential mode both LO N and LO P pins enabled Please note that single ended output is only available on LO N pin Enables Single Ended output mode for LO2 output E 1 Single ended mode LO2_N pin is enabled and LO2_P pin is 9 gw 10 SER ane 1 0 disabled 0 Differential mode both LO2_N and LO2_P pins enabled Please note that single ended output is only available on LO2 N pin 10 R W Reserved 1 0 Reserved Connects CP to CP1 or CP2 output 11 R W Charge Pump Output Select 1 0 0 CP1 1 CP2 23 12 R W Reserved 12 0 Reserved 2 24 Reg 18h Bias Register Default 54C1 h BIT TYPE NAME Width Default DES
41. NDLY Figure 13 RF Output Power e 20 MHz Offset vs Output Power vs Baseband Voltage 2100 MHz Over LO Frequency 1z Hm 7 7 ae 10 F I 8 8745 150 5 5 8 a 4 9 155 5 3f D 160 of 3 4 5 165 2 0 9 1 2 3 4 5 10 5 0 5 INPUT BASEBAND VOLTAGE Vpp diff OUTPUT POWER dBm LO 930MHz LO 1930MHz LO 2530MHz LO 3530MHz Figure 15 Normalized Baseband Frequency Response BASEBAND FREQUENCY RESPONSE dBc 1 10 100 1000 IF FREQUENCY MHz 1 1 Q input bandwidth normalized to gain at 1 MHz fLO 1800 MHz I Q inputs are matched to 100 Ohms differentially For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com HMC1197LP7FE MICROWAVE CORPORATION CORPORATION 03 0314 RoHSY E EARTH FRIENDLY Figure 16 Auxiliary LO Output Open Loop Phase Noise 3600 MHz PHASE NOISE dBc Hz Figure 18 Auxiliary LO Output Open Loop Phase Noise 4100 MHz 40 60 25 8o PHASE NOISE dBc Hz WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz Figure 17 Auxiliary LO Output Fractional Mode Closed Loop Phase Noise 3600 MHz with various divider ratios 80 100 N PHASE NOISE dBc H ES S
42. O frequency 2050 MHz to 4100 MHz by programming N divider Reg 03h and Reg 04h and programming the output divider divide by 1 2 4 6 60 62 programmed in Reg 16h in the VCO register For detailed frequency tuning information and example please see 1 3 7 Frequency Tuning section For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com LL gt lt a or gt LLI Q z lt H 10 O LL gt lt 0 s LL gt LLI Q 0 2 lt H wAittite HMC1197LP7FE MICROWAVE CORPORATION 03 0314 RoHS EARTH FRIENDLY 1 2 1 2 1 1 2 1 1 WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz VCO Overview The VCO consists of a capacitor switched step tuned VCO and an output stage In typical operation the VCO is programmed with the appropriate capacitor switch setting which is executed automatically by the PLL AutoCal state machine if AutoCal is enabled Reg OAh 11 0 see section 1 2 1 VCO Calibration for more information The VCO tunes to the fundamental frequency 2050 MHz to 4100 MHz and is locked by the CP output from the PLL subsystem The VCO controls the output stage of the HMC1197LP7FE enabling configuration of e
43. R W CP UP Gain 7 64h 1d 20 pA 2d 40 pA 127d 2 54mA Default 2mA Charge Pump Offset Control 5 pA step Affects fractional phase noise and lock detect settings 0 0 20 14 R W Offset Magnitude 7 81 1 5 2d 10 pA 127d 635 pA Default 405 21 R W Offset UP enable 1 0 Sets Direction of Reg 09h 20 14 Up 0 UP Offset Off 22 R W Offset DN enable 1 1 Sets Direction of Reg 09h 20 14 Down 0 DN Offset Off Only recommended with external VCOs and Active Loop Filters When enabled the HMC1197LP7FE increases CP current by 3 mA thereby improving phase noise perfor mance and increasing loop bandwidth 23 R W HiK charge pump Mode 1 0 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com earittite HMC1197LP7FE MICHOWAVE CORPORATION CORPORATION v03 0314 WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY 2 12 Reg 0Ah VCO AutoCal Configuration Register DEFAULT 2046 h Bit Type Name Width Default Description Used by internlan AutoCal state machine R Divider Cycles 2 0 R W Vtune Resolution 3 6d 7 256 div cycles for frequency measurement Measurement should last gt 4 usec Note 1 does not work if R divider 1
44. SCK Rising Edge to SDO time 8 2ns40 2ns pF ns te Recovery Time 10 ns t7 SCK 32 Rising Edge to SEN Rising Edge 10 ns O LL gt lt D gt m O 0 2 lt or H For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com 10 O LL gt lt 0 s LL gt LLI Q 0 2 lt H wAittite HMC1197LP7FE MICROWAVE CORPORATION 03 0314 4 WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY FIRST CYCLE 1 18 19 20 24 25 29 30 31 32 uut t t7 2 te SDI d5 ao r4 r3 2 al a0 x READ Address Register Address 00000 ts LD_SDO font TRI STATE SEN Chip Address 000 LD GPO SECOND CYCLE SCK SDI SEN Note Read back on LD SDO can function without SEN Hoewer SEN rising edge is required to return the LD_SDO to the GPO state Figure 42 Serial Port Timing Diagram READ For more information on using the GPO pin while in SPI Mode please see section 1 8 Serial Port Overview For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www
45. URE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY 2 9 Reg 07h Lock Detect Register DEFAULT 200844 h Bit Type Name Width Default Description lock detect window sets the number of consecutive counts of divided VCO that must land inside the Lock Detect Window to declare LOCK 0 5 1 32 2 0 R W Ikd wincnt max 3 4 2 96 3 256 4 512 5 2048 6 8192 7 65535 10 3 R W Reserved 8 8 Reserved 0 LD disable 11 R W LD Enable 1 1 1 LD enable 19 12 R W Reserved 8 0 Reserved 0 to 1 transition triggers the training Lock Detect Training is only required after changing Phase Detector frequency 20 R W Lock Detect Training 9 0 After changing PD frequency a toggle Reg 07h 20 from 0 to 1 retrains the Lock Detect Cycle Slip Prevention enable When enabled if the phase error becomes larger than 21 RAN Gar Enable L approx 70 of the PFD period the charge pump gain is increased by approx 6mA for the duration of the cycle 23 22 R W Reserved 2 0 Reserved 2 10 Reg 08h Analog EN Register DEFAULT 1BFFF h Bit Type Name Width Default Description 4 0 R W Reserved 5 31d Reserved 0 Pin LD_SDO disabled 1 and RegFh 7 1 Pin LD_SDO is always driven this is 5 R W a Purpose Output Pin 1 td required for use of GPO port 1 and RegFh 7 0 LDO SPl is off if chip address not equal to 000 b allowing a shared SPI with other compatible
46. VCO switches are executed immediately as are writes to the integer and fractional registers when AutoCal is disabled Hence frequency changes with manual control and AutoCal disabled requires a minimum of two serial port transfers to the HMC1197LP7FE once to set the VCO switches and once to set the PLL frequency If AutoCal is disabled Reg OAh 11 1 the VCO will update its registers with the value written via Reg 15h 8 1 immediately 1 2 2 Registers required for Frequency Changes in Fractional Mode A large change of frequency in fractional mode Reg O6h 11 1 may require Main Serial Port writes to 1 The integer register intg Reg 03h only required if the integer part changes 2 Manual VCO Tuning Reg 15h only required for manual control of VCO if Reg OAh 11 1 AutoCal disabled For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com 10 LL gt lt 0 s LL gt LLI Q 0 2 lt H waAittite HMC1197LP7FE MICROWAVE CORPORATION 03 0314 ay WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY 3 VCO Divide Ratio and Gain Register e Reg 16h 5 0 is required to change the VCO Output Divider value if needed e Reg 16h 10 6 is required to change the Output G
47. WIDEBAND DIRECT QUADRATURE MODULATOR E w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY Figure 21 Auxiliary LO Output Figure 22 Auxiliary LO Output Open Loop Phase Noise vs Frequency Open Loop Phase Noise vs Temperature 40 100 60 E Wiz Otter E 120 a 130 100 un E 140 2 420 g ID m 150 pA 2 140 2 160 160 170 180 i 180 1 10 100 1000 10000 100000 30 100 300 1000 4000 OFFSET KHz FREQUENCY MHz 3943 3 M 2888 40 3491 74 MHz 2129 4 MHz Figure 23 Auxiliary LO Output Power vs Temperature 1 Figure 24 Integrated RMS Jitter 121 15 038 ee 10 z 0 25 8 m 02 5 o a E 0 15 3 EOD S 5 0 05 uk 100 I 1000 0 500 ie E E ar 3500 1000 OUTPUT FREQUENCY MHz OUTPUT FREQUENCY MHz 85C 40C 27C 40C 276 85 Figure 26 Reference Input Sensitivity Figure 25 Typical VCO Sensitivity Square Wave 50 131 80 220 70 222 60 224 S I 226 S 40 9 g 2 230 20 10 232 0 234 TUNING VOLTAGE V REFERENCE POWER dBm ML core Tuning Cap 15 H core Tuning Cap 7 14 MHz Square Wave 25 MHz Square Wave 50 MHz Square Wave 100 MHz Square Wave MH core Tunin
48. ain if needed 4 The fractional register Reg 04h The fractional register write triggers AutoCal if Reg OAh 11 0 and is loaded into the Delta Sigma modulator automatically after AutoCal runs If AutoCal is disabled Reg OAh 11 1 the fractional frequency change is loaded into the Delta Sigma modulator immediately when the register is written with no adjustment to the VCO Small steps in frequency in fractional mode with AutoCal enabled Reg OAh 11 0 usually only require a single write to the fractional register Worst case 3 Main Serial Port transfers to the HMC1197LP7FE could be required to change frequencies in fractional mode If the frequency step is small and the integer part of the frequency does not change then the integer register is not changed In all cases in fractional mode it is necessary to write to the fractional register Reg 04h for frequency changes 1 2 3 Registers Required for Frequency Changes in Integer Mode A change of frequency in integer mode Reg O6h 11 0 requires Main Serial Port writes to 1 VCO register e 15h only required for manual control of VCO if Reg OAh 11 1 AutoCal disabled e 16h is required to change the VCO Output Divider value if needed 2 The integer register Reg 03h e In integer mode an integer register write triggers AutoCal if Reg OAh 11 0 and is loaded into the prescaler automatically after AutoCal runs If AutoCal is disabled Reg OAh 11 1 the integer frequency chang
49. angel LO Phase 2n x Reg1Ah 224 23 0 R W 2 27 Reg 21h Programmable Harmonic LPF Register Chip ID 6h Regaddress 01h Reg01h Write Only BIT TYPE NAME DEFLT DESCRIPTION Low Pass Filter 3 dB bandwidth setting on the output of LO pins LO_N amp LO_P pins 0 970 MHz 1 1000 MHz 2 1030 MHz 3 1055 MHzI 4 1085 MHz 5 1120 MHz 15 6 1155 MHz Fh 7 1195 MHz 8 2335 MHz 9 2430 MHz 10 2530 MHz 11 2655 MHz 12 2770 MHz 13 2940 MHz 14 3145 MHz 15 3400 MHz 15 0 Harmonic LPF Band select 16 Reserved 23 16 Reserved 8 A write of C1h is required every time bandwidth setting in Reg 21h 15 0 is changed For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com Eittite HMC1197LP7FE MICROWAVE CORPORATION 03 0314 4 WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY QNe IN fi Figure 43 The HMC1197LP7FE Simplified Block Diagram 3 0 Application Information 3 1 Principle of Operation e o 2 a J d D TE GG 3888 Cr
50. aseband inputs of the modulator If exactly the same DC common mode voltage is applied to each of the baseband inputs and there were no DC offsets at the differential baseband inputs the LO leakage at the RF output would be perfectly suppressed By adding small DC offset voltages at the differential baseband inputs the carrier feedthrough can be optimized for a specific frequency band and LO power level The carrier feedthrough can not be calibrated by the DC common mode level at the and Q baseband inputs DC offsets at the differential and Q baseband inputs should be iteratively adjusted until a minimum carrier feedthrough level is obtained Externally available offset voltage step resolution and the modulator s noise floor limit the minimum achievable calibrated carrier feedthrough level The typical offset voltages for optimization are less than 15mV Figure 47 illustrates the typical calibrated carrier feedthrough performance of the HMC1197LP7FE In this characterization of the HMC1197LP7FE carrier feedthrough was calibrated with 500MHz LO frequency steps at 25C and external offset voltage settings were held constant during tests over temperature For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com 10 O LL gt lt a 0 s LL gt
51. at 40C Measured at 40C Calibrated at 40C Measured at 85C Calibrated at 27C Measured at 27C Figure 36 Typical VCO Tuning Voltage After Calibration The calibration is normally run automatically once for every change of frequency This ensures optimum selection of VCO switch settings vs time and temperature The user does not normally have to be concerned about which switch setting is used for a given frequency as this is handled by the AutoCal routine The accuracy required in the calibration affects the amount of time required to tune the VCO The calibration routine searches for the best step setting that locks the VCO at the current programmed frequency and ensures that the VCO will stay locked and perform well over it s full temperature range without additional calibration regardless of the temperature that the VCO was calibrated at Auto Calibration can also be disabled allowing manual VCO tuning Refer to section 1 2 1 5 for a descrip tion of manual tuning 1 2 1 2 2 Auto reLock on Lock Detect Failure It is possible by setting Reg OAh 17 to have the VCO subsystem automatically re run the calibration routine and re lock itself if Lock Detect indicates an unlocked condition for any reason With this option the system will attempt to re Lock only once 1 2 1 3 3 VCO AutoCal on Frequency Change Assuming Reg OAh 11 0 the VCO calibration starts automatically whenever a frequency change is requested If it is desired to rerun
52. beth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com O LL gt lt D gt m O 0 2 lt or H
53. ceed as follows Check EQ 16 to confirm that the exact frequency mode for this fyco is possible f 9ed fuco fp ANA f gt ES 7 61 44x108 sa 8750 9d 2800 2 108 61 44 x 10 120x108 gt Since EQ 16 is satisfied the HMC1197LP7FE can be configured for exact frequency mode at fyco 2800 2 MHz as follows For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com LL gt lt a or gt LLI Q z lt H 10 O LL gt lt 0 s LL gt LLI Q 0 2 lt H Eittite HMC1197LP7FE MICROWAVE CORPORATION 03 0314 WIDEBAND DIRECT QUADRATURE MODULATOR AEs w Fractional N PLL amp VCO 100 4000 MHz 1 Nyy Reg 03h foor ca toor 28002210 pe 2Dh fep 61 44x108 _ 61 44x106 3072d C00h 2 gcd fico ficox fep ged 100x108 61 44x108 20000 3 To program Reg 04h the closest integer N boundary frequency fy that is less than the desired VCO frequency must be calculated fy fep Njyr Using the current example fy fopx Nr 45 61 44 106 2764 8 MHz 224 f 224 2800 2 x106 2764 8 106 fu 96665600 938000h Then Reg04h cl 61 44 108 1 3 7 6 2 2 H
54. crowave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com earittite HMC1197LP7FE MICHOWAVE CORPORATION CORPORATION v03 0314 ra WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY 1 7 Chip Identification The chip id information may be read by reading the content of read only register chip ID in Reg 00h For HMC1197LP7FE chip id is C7701Ah 1 8 SERIAL PORT Overview TH The SPI protocol has the following general features 3 bit chip address enable the use of up to 8 devices connected to the serial bus gt lt b Simultaneous Write Read during the SPI cycle as c 5 bit address space d 3 wire for Write Only capability 4 wire for Read Write capability ap Typical serial port operation can be run with SCLK at speeds up to 50 MHz s 1 8 1 Serial Port WRITE Operation AVDD DVDD 3V AGND DGND OV TY Table 13 SPI WRITE Timing Characteristics Parameter Conditions Min Typ Max Units dp ty SDI setup time to SCLK Rising Edge 3 ns WEE to SCLK Rising Edge to SDI hold time 3 ns lt tg SEN low duration 10 ns t4 SEN high duration 10 ns H t5 SCLK 32 Rising Edge to SEN Rising Edge 10 ns te Recovery Time 10 ns Max Serial port Clock Speed 50 MHz A typical WRITE cycle is shown in Figur
55. d loop the VCO must be calibrated such that the HMC1197LP7FE knows which switch position on the VCO is optimum for the desired output frequency The HMC1197LP7FE supports Auto Calibration AutoCal of the step tuned VCO The AutoCal fixes the VCO tuning voltage at the optimum mid point of the charge pump output then measures the free running VCO frequency while searching for the setting which results in the free running output frequency that is closest to the desired phase locked frequency This procedure results in a phase locked oscillator that locks over a narrow voltage range on the varactor A typical tuning curve for a step tuned VCO is shown in Figure 36 Note how the tuning voltage stays in a narrow range over a wide range of output frequencies such as fast frequency hopping For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com earittite HMC1197LP7FE MICHOWAVE CORPORATION CORPORATION v03 0314 ra WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY TUNE VOLTAGE AFTER CALIBRATION V 1 ub scoop doo os hog d aede ui d du 1900 2100 2300 2500 2700 2900 3100 3300 3500 3700 3900 4100 4300 VCO FREQUENCY MHz Calibrated at 85C Measured at 85C Calibrated at 85C Measured at 40C Calibrated
56. deband rejection can be further improved by empirically selecting the filter bank that provides the highest rejection for a given frequency See Table 15 Table 16 and Figure 46 Table 17 Empirical filter band selection dn 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 gt 2000 Fiter Barik 0 1 5 7 8 0 7 8 9 10 11 15 Selection For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com earittite HMC1197LP7FE MICHOWAVE CORPORATION CORPORATION v03 0314 ra WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY 0 1000 2000 3000 4000 FREQUENCY MHz UNCALIBRATED SIDEBAND SUPPRESSION dBc 3rd Harmonic Suppression 2nd Harmonic Suppression Empirical Band Selection Figure 46 Sideband suppression vs frequency for different filter band selections O LL gt lt D gt m O 0 2 lt or H The filter bank selection process for optimal sideband rejection performance also depends on the LO power level at the output of the PLL VCO LO power in this example set to maximum power level 3 4 Carrier Feedthrough Calibration Carrier feedthrough is related to the DC offsets at the differential b
57. e 41 a The Master host places 24 bit data d23 d0 MSB first on SDI on the first 24 falling edges of SCLK b the slave HMC1197LP7FE shifts in data on SDI on the first 24 rising edges of SCLK c Master places 5 bit register address to be written to r4 r0 MSB first on the next 5 falling edges of SCLK 25 29 d Slave shifts the register bits on the next 5 rising edges of SCLK 25 29 Master places 3 bit chip address a2 a0 MSB first on the next 3 falling edges of SCLK 30 32 Hittite reserves chip address a2 a0 000 for HMC1197LP7FE Slave shifts the chip address bits on the next 3 rising edges of SCLK 30 32 Master asserts SEN after the 32nd rising edge of SCLK Slave registers the SDI data on the rising edge of SEN Master clears SEN to complete the WRITE cycle m For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com 10 O LL gt lt 0 s LL gt LLI Q 0 2 lt H HMC1197LP7FE MICROWAVE CORPORATION ROWAVE CORPORATION 08 0314 WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY ULL n Eg o Figure 41 Serial Port Timing Diagram WRITE 1 8 2 Serial Port READ Operation A typical READ cycle is
58. e HMC1197LP7FE If locked LD_SDO will be high As the name suggests LD SDO pin is multiplexed between LD and SDO Serial Data Out signals Hence LD is available on the LD SDO pin at all times except when a serial port read is requested in which case the pin reverts temporarily to the Serial Data Out pin and returns to the Lock Detect Flag after the read is completed LD can be made available LD_SDO pin at all times by writing Reg OFh 6 1 In that case the HMC1197LP7FE will not provide any read back functionality because the SDO signal is not available 1 3 6 Cycle Slip Prevention CSP When changing VCO frequency and the VCO is not yet locked to the reference the instantaneous frequencies of the two PD inputs are different and the phase difference of the two inputs at the PD varies rapidly over a range much greater than 27 radians Since the gain of the PD varies linearly with phase up to 27 the gain of a conventional PD will cycle from high gain when the phase difference approaches a multiple of 27 to low gain when the phase difference is slightly larger than a multiple of 0 radians The output current from the charge pump will cycle from maximum to minimum even though the VCO has not yet reached its final frequency The charge on the loop filter small cap may actually discharge slightly during the low gain portion of the cycle This can make the VCO frequency actually reverse temporarily during locking This phenomena is known
59. e is loaded into the prescaler immediately when written with no adjustment to the VCO Normally changes to the integer register cause large steps in the VCO frequency hence the VCO switch settings must be adjusted AutoCal enabled is the recommended method for integer mode frequency changes If AutoCal is disabled Reg OAh 11 1 a prior knowledge of the correct VCO switch setting and the corresponding adjustment to the VCO is required before executing the integer frequency change 1 2 4 VCO Output Mute Function The HMC1197LP7FE features an intelligent output mute function with the capability to disable the VCO output while maintaining the PLL and VCO subsystems fully functional The mute function is automatically controlled by the HMC1197LP7FE and provides a number of mute control options including 1 Always mute Reg 16h 5 0 Od This mode is used for manual mute control 2 Automatically mute the outputs during VCO calibration Reg 17h 7 1 that occurs during output frequency changes This mode can be useful in eliminating any out of band emissions during freqeuncy changes and ensuring that the system emits only desired frequencies It is enabled by writing Reg 17h 7 1 Typical isolation when the HMC1197LP7FE is muted is always better than 60 dB and is 30 dB better than disabling the output buffers of the HMC1197LP7FE via Reg 17h 5 4 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive C
60. er Reg 03h and fractional Reg 04h register contents 24 N N 4 N 2 EQ 2 The AutoCal state machine runs at the rate of the FSM clock Tesy where the FSM clock frequency cannot be greater than 50 MHz m Tisy z T si 2 m is 0 2 4 or 5 as determined by Reg 0Ah 14 13 The expected number of VCO counts V is given by V floor N 2 EQ 4 The nominal VCO frequency measured fycom is given by n oe V La 2 i R EQ 5 where the worst case measurement error ferr is n 7 am z f 2 EQ 6 Reg02 CALIBRATION WINDOW RTytai x2 RegA 14 13 Start Stop RegA 2 0 m 0 2 4 5 n 0 1 2 3 5 6 7 8 50 MHz Max for FSM VSPI Clocks c Figure 37 VCO Calibration A 5 bit step tuned VCO for example nominally requires 5 measurements for calibration worst case 6 measurements and hence 7 VSPI data transfers of 20 clock cycles each Total calibration time worst case is given by K128T OT pp 2 7 20T pop EQ 7 or equivalently Thar Tyra 6R 2 140 3 128 2 EQ 8 For guaranteed hold of lock across temperature extremes the resolution should be better than 1 8 the frequency step caused by a VCO sub band switch change Better resolution settings will show no improvement 1 2 1 4 1 1 VCO AutoCal Example The HMC1197LP7FE must satisfy the maximum f limited by the two following conditions a N
61. ession For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com earittite HMC1197LP7FE MICHOWAVE CORPORATION CORPORATION v03 0314 ra WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY 3 6 Linearity Optimization Output IP3 OIP3 of the HMC1197LP7FE depends on the DC common mode level at the and Q baseband inputs The DC common mode level at the and Q baseband inputs can be adjusted in order to optimize the OIP3 for a specific frequency band Figure 49 illustrates the typical relationship between OIP3 and the DC common mode level at the and Q baseband inputs for different LO frequencies As shown in Figure 49 OIP3 of the HMC1197LP7FE can be optimized up to 35dBm OUTPUT IP3 dBm 0 4 0 45 0 5 0 55 0 6 BASEBAND VOLTAGE V 450 MHz 900 MHz 1900 MHz 2600 MHz 3500 MHz Figure 49 The HMC1197LP7FE Linearity Optimization 3 7 GSM EDGE Operation The HMC1197LP7FE is suitable for GSM EDGE applications The EVM performance ofthe HMC1197LP7FE in a GSM EDGE environment is shown in Figure 50 15 12 9 6 3 0 3 6 OUTPUT POWER dBm 900 MHz 1900 MHz Figure 50 The HMC1197LP7FE EVM vs Output Power GSM EDGE 8 PSK For price delivery and
62. et Reg 09h 22 21 10 b e Offset current magnitude of 400 pA Reg 09h 20 14 50h Applying EQ 11 the required LD window size is 0 4 10 A 1 2 66 x10 50 x 10 Hz x 2x10 A 50 x 10 Hz LD Window seconds _ _ 13 33 nsec EQ 11 Locating the Table 12 value that is closest to the EQ 11 result in this case 13 3 13 33 To set the Digital LD window size simply program Reg 07h 9 8 10 b and Reg 07h 7 5 010 b according to Table 12 There is always a good solution for the lock detect window for a given operating point The user should understand however that one solution does not fit all operating points As observed from EQ 11 If charge pump offset or PD frequency are changed significantly then the lock detect window may need to be adjusted For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com LL gt lt a or gt LLI Q z lt H ES ittite HMC1197LP7FE MICROWAVE CORPORATION 03 0314 ay WIDEBAND DIRECT QUADRATURE MODULATOR E w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY 1 3 5 3 Configuring LD SDO Pin for LD Output Setting Reg OFh 4 0 1 will display the Lock Detect Flag on LD_SDO pin of th
63. g Cap 7 CL core Tuning Cap 15 L core Tuning Cap 15 CH core Tuning Cap 15 1 Both Aux LO and MOD LO Gain Set to 3 Max Level both Aux LO and MOD LO Buffer Enabled measured from Auxiliary LO Port 2 RMS Jitter data is measured in fractional mode using 50 MHz reference frequency from 1 kHz to 100 MHz integration bandwidth 3 Measured from a 50 source with a 100 external resistor termination See PLL with Integrated RF VCOs Operating Guide Reference Input Stage section for more details Full FOM performance up to maximum 3 3 Vpp input voltage For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com earittite HMC1197LP7FE MICHOWAVE CORPORATION CORPORATION v03 0314 e WIDEBAND DIRECT QUADRATURE MODULATOR E w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY Figure 27 Reference Input Sensitivity Sinusoid Wave 50 Figure 28 Figure of Merit for PLL VCO 200 200 205 R 210 f i vs Offset R a 290 nemen 2 FOM 1 Noise FOM dBc Hz 1 d N N a NORMALIZED PHASE NOISE dBc Hz m 235 OFFSET Hz 14 MHz sin 50 MHz sin 25 MHz sin 100 MHz sin Figure 30 Fractional N Spurious
64. ge 1 2 4 6 8 62 PLL RF Divider Characteristics 19 Bit N Divider Range Integer Max 2 1 524 287 Fractional nominal divide ratio varies 19 Bit N Divider Range Fractional 3 4 dynamically max 524 283 REF Input Characteristics Max Ref Input Frequency Ref Input Voltage AC Coupled Ref Input Capacitance 14 Bit R Divider Range VCO Open Loop Phase Noise at fo 4 GHz 10 kHz Offset dBc Hz 100 kHz Offset dBc Hz 1 MHz Offset dBc Hz 10 MHz Offset dBc Hz 100 MHz Offset dBc Hz VCO Open Loop Phase Noise at fo 9 3 GHz 2 1 5 GHz 10 kHz Offset dBc Hz 100 kHz Offset dBc Hz 1 MHz Offset dBc Hz 10 MHz Offset dBc Hz 100 MHz Offset dBc Hz Figure of Merit Floor Integer Mode Normalized to 1 Hz 230 dBc Hz Floor Fractional Mode Normalized to 1 Hz 227 dBc Hz Flicker Both Modes Normalized to 1 Hz 268 dBc Hz For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com HMC1197LP7FE MICHOWAVE CORPORATION CORPORATION v03 0314 WIDEBAND DIRECT QUADRATURE MODULATOR E w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY Table 2 Electrical Specifications Continued Parameter Conditions VCO Characteristics VCO Tun
65. gister Reg 1Ah 23 0 The HMC1197LP7FE will automatically reload the start phase seed value into the DPA every time a new fractional frequency is selected Certain zero or binary seed values may cause spurious energy correlation at specific frequencies For most cases a random or non zero non binary start seed is recommended Soft Reset amp Power On Reset The HMC1197LP7FE features a hardware Power on Reset POR All chip registers will be reset to default states approximately 250 us after power up The PLL subsystem SPI registers may also be soft reset by an SPI write to register Reg OOh Power Down Mode Power down the HMC1197LP7FE by pulling CEN pin pin 17 low assuming no SPI overrides Reg O1h 0 1 This will result in all analog functions and internal clocks disabled Current consumption will typically drop below 10 pA in Power Down state The serial port will still respond to normal communication in Power Down mode It is possible to ignore the CEN pin by setting Reg 01h 0 0 Control of Power Down Mode then comes from the serial port register Reg O1h 1 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com LL gt lt a gt LLI Q 2 lt H 10 O LL gt lt 0 s
66. helmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com earittite HMC1197LP7FE MICHOWAVE CORPORATION CORPORATION v03 0314 RoHS v F3 EARTH FRIENDLY 1 3 1 3 1 1 3 1 1 1 3 1 2 WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz PLL Overview Charge Pump CP amp Phase Detector PD The Phase detector PD has two inputs one from the reference path divider and one from the RF path divider When in lock these two inputs are at the same average frequency and are fixed at a constant average phase offset with respect to each other We refer to the frequency of operation of the PD as fpa Most formulae related to step size delta sigma modulation timers etc are functions of the operating frequency of the PD fpa fpa is also referred to as the comparison frequency of the PD The PD compares the phase of the RF path signal with that of the reference path signal and controls the charge pump output current as a linear function of the phase difference between the two signals The output current varies linearly over a full 27 radians 360 of input phase difference Charge Pump A simplified diagram of the charge pump is shown in Figure 38 The CP consists of 4 programmable current sources two controlling the CP Gain Up Gain Reg 09h 13 7 and Down Gain Reg O9h 6 0 and two controlling the CP Offset
67. here they arrive a full cycle late The specific level of charge pump offset current Reg 09h 20 14 is provided in EQ 9 It is also plotted in Figure 39 vs PD frequency for typical CP Gain currents 10 O LL gt lt 0 s LL gt LLI Q 0 2 lt H Required CP Offset 4 3 x10 x Fpp x lep 0 25 x lo EQ 9 where Fpp Comparison frequency of the Phase Detector Hz lop is the full scale current setting A of the switching charge pump set in Reg O9h 6 0 13 7 c CP Current 22 5 mA 3 c x 1 D Current 2 E a i o r4 0 20 40 60 80 100 PHASE DETECTOR FREQUENCY MHz Recommended CP offset current vs PD frequency for typical CP gain currents Calculated using EQ 9 The required CP offset current should never exceed 25 of the programmed CP current It is recommended to enable the Up Offset and disable the Down Offset by writing Reg 09h 22 21 10 b Operation with CP offset influences the required configuration of the Lock Detect function Refer to the description of Lock Detect function in section 1 3 5 When operating with PD frequency gt 80MHz the CP Offset current should be disabled for the frequency change and then re enabled after the PLL has settled If the CP Offset current is enabled during a frequency change it may not lock For price delivery and to place orders Hittite Microwave Corporat
68. hittite com Application Support Phone 978 250 3343 or apps hittite com earittite HMC1197LP7FE MICHOWAVE CORPORATION CORPORATION v03 0314 WIDEBAND DIRECT QUADRATURE MODULATOR E w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY 2 0 PLL Register Map 2 1 Reg 00h ID Register Read Only DEFAULT C7701A h 90 Bit Type Name Width Default Description Q 23 0 RO chip ID 24 C7701A Chip ID Number 2 2 Reg 00h Open Mode Read Address RST Strobe Register Write Only Bit Type Name Width Default Description gt lt 4 0 WO Read Address 5 WRITE ONLY Read Address for next cycle as 5 WO Soft Reset 1 WRITE ONLY Soft Reset set to 0 during operation 23 6 WO Not Defined 18 Not Defined set to write Oh dp 2 3 Reg 01h Chip Enable Register DEFAULT 3h Bit Type Name Width Default Description gt 1 Chip enable via CHIP EN pin Reg 01h 0 1 and TY CHIP EN pin low places the HMC1197LP7FE in Power Down Mode 0 R W Chip Enable Pin Select 1 1 0 Chip enable via SPI Reg 01h 0 0 CHIP EN pin ignored see Power Down Mode description for more WEE details lt Controls Chip Enable Power Down if Reg 01h 0 0 Reg 01h 0 0 Reg O1h 1 1 chip is enabled CHIP_ s EN pin don t care n BW ep Chip enable 1 Reg O1h 0 0 and Reg 01h 1 0 chip disabled CHIP EN pin don t care see Power
69. ing Sensitivity at 3862 MHz Measured at 2 5 V VCO Tuning Sensitivity at 3643 MHz Measured at 2 5 V VCO Tuning Sensitivity at 3491 MHz Measured at 2 5 V VCO Tuning Sensitivity at 3044 MHz Measured at 2 5 V VCO Tuning Sensitivity at 2558 MHz Measured at 2 5 V VCO Tuning Sensitivity at 2129 MHz Measured at 2 5 V VCO Supply Pushing Measured at 2 5 V 2 MHz V Table 3 Test Conditions Unless Otherwise Specified the Following Test Conditions Were Used Parameter Condition Temperature 25 C Baseband Input Frequency 200 kHz Baseband Input DC Voltage Vbbdc 0 5 V Baseband Input AC Voltage Peak to Peak Differential and Q 1 0V Baseband Input AC Voltage for OIP3 Measurements Peak to Peak Differential and Q 500 mV per tone 150 amp 250 KHz Baseband Input AC Voltage for Noise Floor Measurements Peak to Peak Differential and Q no baseband input voltage Frequency Offset for Output Noise Measurements 20 MHz Supply Voltage VCC1 VCC2 VCC3 VDDLS VDDCP BIAS 5 0V Supply Voltage V3 DVDD RVDD VCCPD VCCPS VCCHF 3 3V LO Power Level Maximum Power Mounting Configuration Refer to HMC1197LP7FE Application Schematic Herein Sideband amp Carrier Feedthrough Uncalibrated Table 4 Filter Bank Selection vs Frequency ES 500 600 700 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2000
70. ion 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com earittite HMC1197LP7FE MICHOWAVE CORPORATION CORPORATION v03 0314 ra WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY 1 3 1 4 Phase Detector Functions Phase detector register Reg OBhallows manual access to control special phase detector features Setting Reg OBh 5 0 masks the PD up output which prevents the charge pump from pumping up Setting Reg OBh 6 0 masks the PD down output which prevents the charge pump from pumping down Clearing both Reg OBh 5 and Reg OBh 6 tri states the charge pump while leaving all other functions operating internally PD Force UP Reg OBh 9 1 and PD Force DN Reg OBh 10 1 allows the charge pump to be forced up or down respectively This will force the VCO to the ends of the tuning range which can be useful in VCO testing 1 3 2 Reference Input Stage RVDD AC couple LL gt lt a gt LLI Q 2 lt H 1000 Figure 39 Reference Path Input Stage The reference buffer provides the path from an external reference source generally crystal based to the R divider and eventually to the phase detector The buffer has two modes of operation controlled by Reg 08h 21 High Gain Reg 08h 21 0 recomme
71. it Reg 06h 7 1 In integer mode the VCO step size is fixed to that of the PD frequency Integer mode typically has 3 dB lower phase noise than fractional mode for a given PD operating frequency Integer mode however often requires a lower PD frequency to meet step size requirements The fractional mode advantage is that higher PD frequencies can be used hence lower phase noise can often be realized in fractional mode Charge Pump offset should be disabled in integer mode Reg 09h 22 14 Oh For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com earittite HMC1197LP7FE MICHOWAVE CORPORATION CORPORATION v03 0314 RoHS v Fx EARTH FRIENDLY 1 3 7 2 1 3 7 3 1 3 7 4 WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz Integer Frequency Tuning In integer mode the digital modulator is shut off and the N divider Reg 03h may be programmed to any integer value in the range 16 to 219 1 To run in integer mode configure Reg 06h as described then program the integer portion of the frequency as explained by EQ 12 ignoring the fractional part a Disable the Fractional Modulator Reg O6h 11 b Bypass the delta sigma modulator Reg 06h 7 1 c To tune to frequencies lt 2050 MHz select the appropriate out
72. ittite Exact Frequency Channel Mode If it is desirable to have multiple equally spaced exact frequency channels that fall within the same interval ie fy lt fycok lt fy j where is shown in Figure 40 and 1 lt lt 224 it is possible to maintain the same integer N Reg 03h and exact frequency register Reg OCh settings and only update the fractional register Reg 04h setting The Exact Frequency Channel Mode is possible if EQ 16 is satisfied for at least two equally spaced adjacent frequency channels i e the channel step size To configure the HMC1197LP7FE for Exact Frequency Channel Mode initially and only at the beginning integer Reg 03h and exact frequency Reg OCh registers need to be programmed for the smallest fyco frequency fyco in Figure 40 as follows 1 Calculate and program the integer register setting Reg 03h Nr floor fyco7 fpp where fyco is shown in Figure 40 and corresponds to minimum channel VCO frequency Then the lower integer boundary frequency is given by fy fpo 2 Calculate and program the exact frequency register value Reg OCh where gcd fycok1 greatest common divisor of the desired equidistant channel spacing and the PD frequency fycoxs1 fycox and fpp Then to switch between various equally spaced intervals channels only the fractional register Reg 04h needs to be programmed to the desired VCO channel frequency fyco
73. l N PLL amp VCO 100 4000 MHz EARTH FRIENDLY 2 6 Reg 04h Frequency Register Fractional Part DEFAULT 0h Bit Type Name Width Default Description Divider Fractional part 24 bit unsigned see Fractional Frequency Tuning Fractional Division Value Reg4 23 0 2 24 23 0 R W Fractional Setting 24 0 Used in Fractional Mode only min 0 224 1 FFFFFFh 16 777 215d 2 7 Reg 05h Reserved Bit Type Name Width Default Description 23 0 R W Reserved 24 0 Reserved 2 8 Reg 06h Delta Sigma Modulator Register DEFAULT 30F0Ah 10 LL gt lt 0 s LL gt LLI Q 0 2 lt H BIT TYPE NAME Width Default DESCRIPTION 1 0 R W Reserved 2 2 Reserved Program to Oh Select the Delta Sigma Modulator Type 0 1st order 3 2 R W DSM Order 2 2 1 2nd Order 2 3rd Order Recommended 3 Reserved 0 Normal SPI Load all register load on rising edge of SEN 1 Synchronous SPI registers Reg 03h Reg 04h Reg 1Ah wait to load synchronously on the next internal clock cycle Normally When this bit is 0 SPI writes into the internal state 4 R W Synchronous SPI Mode 1 0 machines counters happen asynchronously relative to the internal clocks This can create freq phase disturbances if writing register 3 4 1 When this bit is enabled the internal SPI registers loaded synchronously with the internal clock This means that the data
74. ly Current of 3 3V Supply I Modulator OFF and PLL ON 48 mA Modulator OFF and PLL OFF 1 mA Enable Disable Interface EN High Level Modulator disabled 5 V EN Low Level Modulator enabled 0 V Enable Disable Settling Time 400 400 ns LO Leakage Isolation EN MOD 5V LO 2 1GHz 75 dBm Logic Inputs Logic High 1 2 Logic Low 0 6 Input Current 1 uA Input Capacitance 2 pF LO Output Characteristics LO Output Frequency 50 4100 MHz VCO Frequency at PLL Input 2000 4100 MHz For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com 10 LL gt lt a N s LLI gt LLI Q 0 2 lt H HMC1197LP7FE MICROWAVE CORPORATION 03 0314 a WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY Table 2 Electrical Specifications Continued Parameter Conditions VCO Fundamental Frequency VCO Output Divider VCO Output Divider Range 1 2 4 60 62 PLL RF Divider Characteristics Integer 524287 19 Bit N Divider Range Fractional 524283 Phase Detector PD Fractional Mode PD Frequency meer ntege Harmonics fo Mode at 4000 MHz 2nd 3rd 4th 30 22 32 VCO Output Divider VCO RF Divider Ran
75. n Divisor fy maximum integer boundary frequency lt fyco1 fpp frequency of the Phase Detector and fyco are the channel step frequencies where 0 lt lt 224 1 As shown in Figure 40 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com earittite HMC1197LP7FE MICHOWAVE CORPORATION CORPORATION v03 0314 ba WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY fvco fvco2 Integer Integer Boundary Boundary gt fy fco2 fvco4 fvcoZ 2 fcoZt fco2 1 fy fep les Figure 40 Exact Frequency Tuning Some fractional PLLs are able to achieve this by adjusting shortening the length of the Phase Accumulator the denominator or the modulus of the Delta Sigma modulator so that the Delta Sigma modulator phase accumulator repeats at an exact period related to the interval frequency fycox 1 in Figure 40 Consequently the shortened accumulator results in more frequent repeating patterns and as a result often leads to spurious emissions at multiples of the repeating pattern period or at harmonic frequencies of fycok For example in some applications these intervals might represent the spacing between radio channels and the spurious
76. nded below 200 MHz and High frequency Reg 08h 21 1 for 200 to 350 MHz operation The buffer is internally DC biased with 100 O internal termination For 50 match an external 100 resistor to ground should be added followed by an AC coupling capacitor impedance 1 then to the XREFP pin of the part At low frequencies a relatively square reference is recommended to keep the input slew rate high At higher frequencies a square or sinusoid can be used The following table shows the recommended operating regions for different reference frequencies If operating outside these regions the part will normally still operate but with degraded reference path phase noise performance For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com 10 LL gt lt 0 s LL gt LLI Q 0 2 lt H waAittite HMC1197LP7FE MICROWAVE CORPORATION v03 0314 RoHS m E EARTH FRIENDLY 1 3 3 1 3 4 1 3 5 1 3 5 1 WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz Table 11 Reference Sensitivity Table Square Input Sinusoidal Input Reference Input Slew gt 0 5V ns Recommended Swing Vpp Recommended Power Range dBm Frequency MHz Recommended
77. ngs ensure optimal signal levels tailored to each output External VCO input allows the HMC1197LP7FE to lock external VCOs and enables cascaded LO architectures for MIMO radio applications Two separate Charge Pump CP outputs enable separate loop filters optimized for both integrated and external VCOs and seamless switching between integrated or external VCOs during operation Programmable RF output phase feature can further phase adjust and synchronize multiple HMC1197LP7FEs enabling scalable MIMO and beam forming radio architectures Integrated programmable Low Pass Filter LPF on the modulator LO input ensures no LO harmonic contribution to modulator sideband rejection performance Sixteen programmable LPF bands enable true wideband operation eliminating the need for external band specific harmonic filtering hardware Additional features include configurable LO output mute function Exact Frequency Mode that enables the HMC1197LP7FE to generate fractional frequencies with Hz frequency error and the ability to synchronously change frequencies without changing the phase of the output signal For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com t JHittite HMC1197LP7FE MICROWAVE CORPORATION CORPORATION v03 0314 RoHSY FY WIDEBAND DIRECT QUADRATURE
78. ock Detect Out 1 0 Lock Detect Output TY 23 2 R Reserved 22 7h Reserved 2 19 13h BIST Register Read Only 2 BIT TYPE NAME Width Default DESCRIPTION 16 0 R Reserved 16 Reserved For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com earittite MICROWAVE CORPORATION CORPORATION 03 0314 HMC1197LP7FE RoHSY FS WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY 2 20 Reg 14h Auxiliary SPI Register BIT TYPE NAME Width Default DESCRIPTION 1 Use the 3 outputs as an SPI port 0 RW 1 8 0 Use the 3 outputs as a static GPO port along with Reg 14h 3 1 8 1 R W Aux GPO Values 3 0 3 Output values can be set indivually when Reg 10h 0 1 7 RW AGRO SAY 0 0 1 8 V output out of the Auxiliary GPO pins when Reg 10h 0 1 1 3 3 V output out of the Auxiliary GPO pins when Reg 10h 0 1 8 5 R W Reserved 4 1 Reserved When set CHIP_EN pin is used as a trigger for phase synchronization Can be used to synchronize multiple 9 R W Phase Sync 1 1 HMC1197LP7FE or to along with the Reg 1Ah value to phase step the output Exact Frequency Mode must be enabled Option to send GPO multiplexed data ex Lock Detect to one
79. ocked in an invalid non zero chip address the HMC1197LP7FE will start to drive the bus The WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO will naturally switch away from the GPO data and export the SDO during an SPI read To prevent this automatic data selection and always select the GPO signal set Prevent AutoMux of SDO Reg OFh 6 1 The phase noise performance at this output is poor and uncharacterized The GPO output should not be toggling during normal operation because it may degrade the spectral performance Note that there are additional controls available which may be helpful if sharing the bus with other devices e To disable the driver completely set Reg O8h 5 0 it takes precedence over all else e disable either the pull up or pull down sections of the driver Reg OFh 8 1 or Reg OFh 9 1 respectively Example Scenarios e Drive SDO during reads tri state otherwise to allow bus sharing e No action required e Drive SDO during reads Lock Detect otherwise e Set GPO Select Reg 4 0 00001 b which is default e Set Prevent GPO driver disable Reg OFh 7 1 e Always drive Lock Detect e Set Prevent AutoMux of SDO Reg OFh 6 1 e Set GPO Select Reg OFh 4 0 00001 which is default e Set Prevent GPO driver disable Reg OFh 7 1 The signals available on the GPO are selected in Reg OFh 4 0 For price delivery and to place orders Hittite Mi
80. of the auxiliary outputs 0 None 11 10 R W Aux SPI GPO Output 2 0 1 to 0 2 to 1 3 to 2 When disabled 0 Outputs Hi Z 13 12 R W Aux SPI Outputs 2 0 1 Outputs stay driven 2 Outputs driven to high 3 Outputs driven to low 23 14 R W Reserved 10 0 Reserved 2 21 Reg 15h Manual VCO Config Register Default F48A0 h BIT TYPE NAME Width Default DESCRIPTION en 1 VCO subsystem manual calibration enabled 0 POM Manual 1 0 0 VCO subsystem manual calibration disabled 5 1 R W Capacitor Switch Setting 5 oA capacitor switch setting 8 6 R W Manual VCO Selection 3 2 selects the VCO core sub band 1 Manual VCO tuning enabled 9 R W Manual VCO Tune Enable 1 0 0 Manual VCO tuning disabled 15 10 R W Reserved 6 d Reserved Enable Auto Scale CP cur 1 Automatically scale CP current based on VCO frequency and 16 R W rent 1 1 capacitor setting 0 Don t scale CP current 23 17 R W Reserved 7 7d Reserved For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com 16 O LL gt lt a gt LLI Q z lt H HMC1197LP7FE MICROWAVE CORPORATION 03 0314 a WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100
81. onnected to GND or left floating the chip is 9 EN MOD fully enabled When connected to VCC the LO amplifiers and the mixers are disabled 10 IF1P Supply voltage for the LO and mixer stage 5 0V nominal Q channel differential baseband input These are high impedance ports The nominal recommended bias voltage is 0 45V 0 4V 0 5V I I The nominal recommended baseband input AC voltage is 1 3V peak to peak differential By adjusting the DC offsets on ports QN amp QP the Carrier Suppression of the device can be optimized for a specific frequency band and LO power level The typical offset voltege for 11 12 QN QP a EAE optimization is less than 15 mV The amplitude and phase difference between The and Q inputs can be adjusted in order to optimize the Sideband Suppression for a specific frequency band and LO power level 15 16 17 Be Ee GND These pins and package base must be connected to RF and DC ground DC coupled and matched to 50 Ohms 19 REQUT Output requires an external DC blocking capacitor 21 VCC3 Supply voltage for the output stages 5 0V nominal channel differential baseband input These are high impedance ports The nominal recommended bias voltage is 0 45V 0 4V 0 5V The nominal recommended baseband input AC voltage is 1 3V peak to peak differential By adjusting the DC offsets on ports IN amp IP the Carrier Suppression of the device can be optimized for a specific frequency band and LO power level The typical offset voltege fo
82. port Phone 978 250 3343 or apps hittite com LL gt lt a gt LLI Q 2 lt H Eittite HMC1197LP7FE MICROWAVE CORPORATION 03 0314 WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY 1 3 1 3 Charge Pump Phase Offset In Integer Mode the phase detector operates with zero offset The divided reference signal and the divided VCO signal arrive at the phase detector inputs at the same time Integer mode does not require any CP Offset current When operating in Integer Mode simply disable CP offset in both directions Up and down by writing Reg O9h 22 21 00 and set the CP Offset magnitude to zero by writingReg O9h 20 14 0 In Fractional Mode CP linearity is of paramount importance Any non linearity degrades phase noise and spurious performance In fractional mode these non linearities are eliminated by operating the PD with an average phase offset either positive or negative either the reference or the VCO edge always arrives first at the PD ie leads A programmable CP offset current source is used to add DC current to the loop filter and create the desired phase offset Positive current causes the VCO to lead negative current causes the reference to lead The CP offset is controlled via Reg 09h 20 14 The phase offset is scaled from degrees that is the reference and the VCO path arrive in phase to 360 degrees w
83. positive input 45 VCCHF Analog supply 3 3V nominal 46 VCCPS Analog supply Prescaler 3 3V nominal 47 VCCPD Analog supply Phase Detector 3 3 V nominal 48 VDDLS Analog supply Charge Pump 5 0 V nominal For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com O LL gt lt D m gt m 0 2 lt or H 10 O LL gt lt C D m gt m O 0 2 lt or H HMC1197LP7FE MICROWAVE CORPORATION 03 0314 as WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY Evaluation PCB Le 4 R32 uite 600 00641 00 1 i 4 1 VTUNE DUM 8 11315 P6 R xit 1 2 dU af f VUA j C78 10 SUPPLY 3 mE 4 d M n ER PB IFIP UW C30 Ll 25 26 y 22 27 The circuit board used in the application should use RF circuit design techniques Signal lines should have 50 ohm impedance while the package ground leads and exposed paddle should be connected directly to the ground plane similar to that shown A sufficient number of via holes should be used to connect the top and bottom ground planes The
84. put divider valueReg 16h 5 0 Fractional Mode The HMC1197LP7FE is placed in fractional mode by setting the following registers a Enable the Fractional Modulator Reg 06h 11 1 b Connect the delta sigma modulator in circuit Reg 06h 7 20 Fractional Frequency Tuning This is a generic example with the goal of explaining how to program the output frequency Actual variables are dependant upon the reference in use The HMC1197LP7FE in fractional mode can achieve frequencies at fractional multiples of the reference The frequency of the HMC1197LP7FE fico is given by ital fyco Nint fint frac EQ 12 fout fvcol EQ 13 Where fout is the output frequency after any potential dividers k is 1 for fundamental or k 2 4 6 58 60 62 depending on the selected output divider value Reg 16h 5 0 Nint is the integer division ratio Reg 03h an integer number between 20 and 524 284 is the fractional part from 0 0 to 0 99999 Nac Reg 04 224 R is the reference path division ratio Reg 02h 1 is the frequency of the reference oscillator input fod is the PD operating frequency fyta R As an example fout 1402 5 MHz k 2 tas 2 805 MHz fai 50 MHz R 1 fod 50 MHz Nint 56 01 For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support
85. r optimization 25 26 IP IN is less than 15 mV The amplitude and phase difference between The and Q inputs can be adjusted in order to optimize the Sideband Suppression for a specific frequency band and LO power level 27 V3 Supply pin for low pass filter 3 3V nominal 31 CHIP_EN Chip Enable Connect to logic high for normal operation LO outputs AC coupled and matched to 50 Ohms single ended Do not need external DC decoupling 32 33 LON LOP capacitors The ports could be single ended or differential 34 VCC1 VCO analog supply 1 5 0V nominal 35 2 VCO analog supply 2 5 0 nominal 36 VTUNE VCO Varactor Tuning Port Input 37 SEN PLL Serial Port Enable CMOS Logic Input 38 SDI PLL Serial Port Data CMOS Logic Input 39 SCK PLL Serial Port Clock CMOS Logic Input For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com earittite HMC1197LP7FE MICROWAVE MICROWAVE CORPORATION v03 0314 WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY Pin Descriptions Pin Number Function Description 40 LD SDO Lock Detect or Serial Data or General Purpose CMOS Logic Output GPO 43 EXT_N External VCO negative input 44 EXT_P External VCO
86. rated signal levels Therefore the LO path is immune to large variations in the LO input signal level and the modulator performance does not vary much with LO input power After upconversion the outputs of the and Q mixers are summed together differentially and converted to single ended RF output The single ended RF output port is internally matched to 50 Ohms and does not require any external matching components Only a standard DC blocking capacitor is required at this interface Harmonic Low Pass Filter High LO harmonic content causes amplitude and phase mismatches and ultimately performance degradation in modulator sideband rejection Targeted minimum io harmonic level Targeted maximum modulator sideband rejection 3rd LO Harmonic MODULATOR SIDEBAND REJECTION dBc 80 70 60 50 40 30 20 10 0 LO HARMONIC LEVEL dBc Figure 44 Typical impact of 2nd and 3rd LO harmonic on sideband rejection As shown in Figure 44 in a typical modulator with 1xLO input both the 2nd and 3rd LO harmonics affect the modulator sideband rejection performance at levels gt 20 dBc relative to the LO signal power It also shows that the 3 LO harmonic has greater impact on modulator sideband rejection performance than the 2 and that there is little effect of the 2 LO harmonic on modulator sideband rejection once the 2 LO harmonic is below 20 dBc levels relative to the LO signal level Figure 45 shows the typical insertion
87. rnal VCO 4 R W FD Phase Select 1 0 1 Use with a Negative Slope VCO or with an inverting Active Loop Filter with a Positive Slope VCO Only recommended when using an External VCO and an active loop filter 5 R W PD Up Output Enable 1 1 Enables the PD UP output see also Reg OBhj9 6 R W PD Down Output Enable 1 1 Enables the PD DN output see also Reg OBh 10 8 7 R W Reserved 2 0 Reserved Program to Od 9 R W Force CP UP 1 0 Forces CP UP output on if CP is not forced down Use for Test only 10 R W Force CP DN 1 0 Forces CP DN output on if CP is not forced up Use for Test only 11 B W Force CP Mid Rail 1 0 Force CP Mld Rail Use for Test only if Force CP UP or Force CP DN are enabled they have precedence 23 12 R W Reserved 1g Reserved 2 14 Reg OCh Exact Frequency Register BIT TYPE NAME Width Default DESCRIPTION Comparison Frequency divided by the correction rate Must be an integer Frequencies at exactly the correction rate will have zero frequency error Only works in modulator Mode B 3rd order recommended modulator type in Reg06 3 2 Reg OCh must be 0 if 23 0 R W Number of Channels per Fpd 24 0 using ohter DSM type 0 Disabled 1 Invalid gt 2 valid max 224 1 FFFFFFh 16 777 215d For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hi
88. shown in Figure 42 In general the LD_SDO line is always active during the WRITE cycle During any SPI cycle LD_SDO will contain the data from the current address written in Reg OOh 4 0 If Reg OOh 4 0 is not changed then the same data will always be present on LD_SDO when an Open Mode cycle is in progress If it is desired to READ from a specific address it is necessary in the first SPI cycle to write the desired address to Reg OOh 4 0 then in the next SPI cycle the desired data will be available on LD_SDO An example of the two cycle procedure to read from any address follows a The Master host on the first 24 falling edges of SCLK places 24 bit data d23 d0 MSB first on SDI as shown in Figure 42 d23 d5 should be set to zero 04 00 address of the register to be READ on the next cycle b the slave HMC1197LP7FE shifts in data on SDI on the first 24 rising edges of SCK c Master places 5 bit register address 4 0 the READ ADDRESS register MSB first on the next 5 falling edges of SCK 25 29 r4 r0200000 d Slave shifts the register bits on the next 5 rising edges of SCK 25 29 e Master places 3 bit chip address a2 a0 MSB first on the next 3 falling edges of SCK 30 32 Chip address is always 000 b f Slave shifts the chip address bits on the next 3 rising edges of SCK 30 32 g Master asserts SEN after the 32nd rising edge of SCK h i J Slave registers the SDI data on the rising edge of SEN Ma
89. ster clears SEN to complete the the address transfer of the two part READ cycle If one does not wish to write data to the chip during the second cycle then it is recommended to simply rewrite the same contents on SDI to Register zero on the READ back part of the cycle k Master places the same SDI data as the previous cycle on the next 32 falling edges of SCK I Slave HMC1197LP7FE shifts the SDI data on the next 32 rising edges of SCK On these same edges the slave places the desired read data ie data from the address specified in Reg OOh 4 0 of the first cycle on LD_SDO which automatically switches to SDO mode from LD mode disabling the LD output m Master asserts SEN after the 32nd rising edge of SCK to complete the cycle and revert back to Lock Detect on LD_SDO For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com HMC1197LP7FE MICROWAVE MICROWAVE CORPORATION v03 0314 WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY Table 14 SPI Read Timing Characteristics Parameter Conditions Typ Units ty SDI setup time to SCK Rising Edge 3 ns to SCK Rising Edge to SDI hold time 3 ns tg SEN low duration 10 ns t4 SEN high duration 10 ns t5
90. the AutoCal routine for any reason at the same frequency simply rewrite the frequency change with the same value and the AutoCal routine will execute again without changing final frequency 1 2 1 4 4 VCO AutoCal Time amp Accuracy The VCO frequency is counted for Tmm the period of a single AutoCal measurement cycle Del 2 1 is set by Reg OAh 2 0 and results in measurement periods which are multiples of the PD period 7 8 R is the reference path division ratio currently in use Reg 02h is the period of the external reference crystal oscillator The VCO AutoCal counter will on average expect to register N counts rounded down floor to the nearest integer every PD cycle N is the ratio of the target VCO frequency fyco to the frequency of the PD foa where N can For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com LL gt lt a or gt LLI Q z lt H 10 O LL gt lt 0 s LL gt LLI Q 0 2 lt H ESMittite HMC1197LP7FE MICROWAVE CORPORATION 03 0314 4 WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY be any rational number supported by the N divider N is set by the integ
91. tion Molded Plastic 100 matte Sn MSL1 XXXX 1 Max peak reflow temperature of 260 C 2 4 Digit lot number XXXX For price delivery and to place orders Hittite Microwave Corporation 2 Elizabeth Drive Chelmsford MA 01824 Phone 978 250 3343 Fax 978 250 3373 Order On line at www hittite com Application Support Phone 978 250 3343 or apps hittite com LL gt lt a or gt LLI Q z lt H 10 O LL gt lt a N 22 gt LLI Q 0 2 lt H HMC1197LP7FE MICROWAVE CORPORATION 03 0314 ay WIDEBAND DIRECT QUADRATURE MODULATOR E w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY Table 8 Pin Descriptions Pin Number Function Description 1 VDDCP Power Supply for charge pump analog section 5 0V nominal 2 BIAS External bypass decoupling for precision bias circuits 5 0V nominal 3 4 CP1 CP2 Charge Pump Outputs 5 RVDD Reference Supply 3 3V nominal 6 XREFP Reference Input DC bias is generated internally Normally AC coupled externally ri DVDD DC Power Supply for Digital CMOS Circuitry 3 3V nominal 8 13 14 22 23 24 28 N C The pins are not connected internally however all data shown herein was measured with these pins 29 30 41 42 connected to RF DC ground externally This pin has a 10 Kohm pulldown resistor to GND When c
92. ttite com Application Support Phone 978 250 3343 or apps hittite com t JHittite HMC1197LP7FE MICROWAVE CORPORATION CORPORATION 03 0314 ba WIDEBAND DIRECT QUADRATURE MODULATOR w Fractional N PLL amp VCO 100 4000 MHz EARTH FRIENDLY 2 15 Reg OFh GPO Register BIT TYPE NAME Width Default DESCRIPTION Select signal to be output to SDO pin when enabled DEFAULT LOCK DETECT Data from RegOF 5 Lock Detect Output Lock Detect Trigger Lock Detect Window Output Ring Osc Test Pullup Hard from CSP PullDN hard from CSP Reserved Reference Buffer Output 9 Ref Divider Output 10 VCO divider Output 11 Modulator Clock from VCO divider 12 Auxiliary Clock 13 Aux SPI Clock 14 Aux SPI Enable 15 Aux SPI Data Out 16 PD DN 17 PD UP 18 SD3 Clock Delay 19 SD3 Core Clock 20 AutoStrobe Integer Write 21 Autostrobe Frac Write 22 Autostrobe Aux SPI 23 SPI Latch Enable 24 VCO Divider Sync Reset 25 Seed Load Strobe 26 29 Not Used 30 SPI Output Buffer En 31 Soft RSTB 5 R W GPO Test Data 1 0 1 GPO Test Data when GPO Select 0 ON 4 0 R W GPO 5 1 1 Outputs GPO data only 6 RAN prevent Automix SDO 1 0 0 Automuxes between SDO GPO data 7 R W Reserved 1 0 Reserved Program to 1 if external pull ups are used on the SDO line 8 RO Disable PFET 9 Prevents conflicts on the SPI bus Program to 1 if external pull downs are used on the SDO
93. variable which allows exact frequency steps to be achieved with decimal step sizes Unfortunately small steps using small modulus values results in large spurious outputs at multiples of the modulus period channel step size For this reason Hittite PLLs use a large fixed modulus Normally the step size is set by the size of the fixed modulus In the case of a 50 MHz PD rate a modulus of 224 would result in a 2 98 Hz step resolution or 0 0596 ppm In some applications it is necessary to have exact frequency steps and even an error of 3 Hz cannot be tolerated Fractional PLLs are able to generate exact frequencies with zero frequency error if N can be exactly represented in binary eg N 50 0 50 5 50 25 50 75 etc Unfortunately some common frequencies cannot be exactly represented For example Nia 0 1 1 10 must be approximated as round 0 1 x 224 224 0100000024 At fpp 50 MHz this translates to 1 2 Hz error Hittite s exact frequency mode addresses this issue and can eliminate quantization error by programming the channel step size to Fpp 10 in Reg OCh to 10 in this example More generally this feature can be used whenever the desired frequency fyco can be exactly represented on a step plan where there are an integer number of steps 2 across integer N boundaries Mathematically this situation is satisfied if f COk Mod fyca 0 9Cd fycopfep and fygg Ej EQ 16 Where gcd stands for Greatest Commo

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