SuperH RISC engine Simulator/Debugger V.9.09.00 Supplementary
Contents
1. RISC engine Simulator Debugger V 9 09 00 Supplementary Information for User s Manual Table 6 1 lists the commands that have been added to V 9 09 00 For details on the command syntax refer to the online help for the SuperH RISC engine Simulator Debugger Table 6 1 New Commands Command Abbreviation Description OSOBJECT_ALL_ADD OAA Adds OS objects of a specific object type OSOBJECT_ALL_ DELETE OAD Deletes OS objects in a specific sheet OSOBJECT_AUTO_UPDATE OAU Changes the automatic update setting to Auto and Break OSOBJECT_DATA_LOWLINE ODU Moves an OS object to the next line OSOBJECT_DATA_SAVE ODS Saves the information on an OS object to a file OSOBJECT_DATA_UPLINE ODL Moves an OS object to the previous line OSOBJECT_DISPLAY OD Shows the information on an OS object OSOBJECT_NO_UPDATE ONU Changes the automatic update setting to Lock OSOBJECT_ONE_ADD OOA Adds an OS object OSOBJECT_ONE_DELETE OOD Deletes an OS object OSOBJECT_ONE_EDIT OOE Edits an OS object OSOBJECT_SETTING_LOAD OSL Loads OS object settings from a file OSOBJECT_SETTING_SAVE OSS Saves OS object settings in a file OSOBJECT_STOP_UPDATE OSU Changes the automatic update setting to Break REJ10J1997 0100 Rev 1 00 April 2009 Page 13 of 15 Supplementary Information for User s Manual g E N ESAS SuperH RISC engine Simulator Debugger V 9 09 00 7 Messages 7 1 Error Me2. Please contact a Renesas sales office if you have any questions regarding the information contained in this document Renesas semiconductor products or if you have any other inquiries 2009 Renesas Technology Corp All rights reserved REJ10J1997 0100 Rev 1 00 April 2009 Page 15 of 15
3. 2 The following notes apply to memory resources for the SH2A FPU series Memory resources can only be allocated on 8 kbyte boundaries If a memory resource is allocated to an address range that does not have 8 kbyte boundaries the boundaries will be adjusted to 8 kbyte boundaries that encompass the specified range Accordingly address ranges of attributes are allocated on 8 kbyte boundaries When a memory resource does not take up a full 8 kbyte range the memory that is actually used must be within the range defined in the hardware manual Do not clear the default allocation of a memory resource as I O area If such an allocation is cleared operation of the cache memory will be incorrect REJ10J1997 0100 Rev 1 00 April 2009 Page 10 of 15 Supplementary Information for User s Manual g E N ESAS SuperH RISC engine Simulator Debugger V 9 09 00 4 Profile The specification of the profiler function for the SH 2A was changed in V 9 08 00 This section describes the new specification of the profiler function 4 1 Types and Purposes of the Profile Data Displayed by the Profiler Function The profile data to be displayed depends on the CPU In the case of the SH2A FPU the profile data consists of the items listed below a When the internal ROM has been disabled Cycle the number of cycles for execution ICache miss the number of instruction cache misses OCache miss the number of operand cache misses Ext_mem
4. V 9 09 00 When the memory type is not ROM Number of cycles states for read access to the specified type of memory Write state count When the memory type is ROM Throughput When the memory type is not ROM Number of cycles states for write access to the specified type of memory Notes 1 In terms of the memory resources of the SH2A FPU note the following In the memory areas that are fixed as ROM or RAM selection of another memory type or allocation in two or more ranges is not possible The memory areas that are fixed as ROM and RAM are given below Area Address Range Remark ROM 0x00000000 0x01 FFFFFF When the internal ROM has been enabled RAM OxFFF80000 OxFFFBFFFF No addresses in reserved areas can be specified The reserved areas are given below Area Address Range Remark Reserved 0x20000000 0x21FFFFFF When the internal ROM has been enabled 0x84000000 OxE7FFFFFF Memory can only be allocated on 8 kbyte boundaries If memory is allocated to an address range that does not have 8 kbyte boundaries the boundaries will be adjusted to 8 kbyte boundaries that encompass the specified range Numbers of cycles for access to the areas fixed as ROM and RAM are as follows Area Number of Cycles for Number of Cycles for Reading Latency Writing Throughput ROM 1to4 RAM 1or2 1 to 4 2 The memory map setting for area that is all
5. the number of times external memory was accessed m e e 1 O_area the number of times internal I O area was accessed Int_mem the number of times internal memory was accessed b When the internal ROM has been enabled Cycle the number of cycles for execution ROM ICache miss the number of instruction ROM cache misses ROM OCache miss the number of operand ROM cache misses Ext_mem the number of times external memory was accessed I O_area the number of times internal I O area was accessed Int_mem the number of times internal memory was accessed REJ10J1997 0100 Rev 1 00 April 2009 Page 11 of 15 l SuperH RISC engine Simulator Debugger V 9 09 00 m EN ESAS Supplementary Information for User s Manual 5 Windows Table 5 1 lists the windows that have been added to V 9 08 00 and table 5 2 shows a window that has been modified in V 9 09 00 For details on these windows refer to the online help for the SuperH RISC engine Simulator Debugger Table 5 1 New Windows Window Name Description OS Object Shows the states of OS objects such as tasks and semaphores Task Trace Shows the history of task execution in a program that uses a real time OS Task Analyze Shows the current CPU occupancy Table 5 2 Modified Window Window Name Description Memory Modified to support the automatic update function REJ10J1997 0100 Rev 1 00 April 2009 Page 12 of 15 2CENESAS 6 Command Line SuperH
6. where the fixed area starts Oxnnnnnnnn Address where the fixed area ends April 2009 Page 14 of 15 g N ESAS SuperH RISC engine Simulator Debugger V 9 09 00 Supplementary Information for User s Manual Notes regarding these materials 1 This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document 2 Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document including but not limited to product data diagrams charts programs algorithms and application circuit examples 3 You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use When exporting the products or technology described herein you should follow the applicable export control laws and regulations and procedures required by such laws and regulations 4 All information included in this document such as product data diagrams charts p
7. IOFFFFF F1800000 F1SFFFFF F2000000 F2001 FFF F2800000 F2801 FFF F3000000 F3001 FFF F3800000 F3801 FFF F4000000 F4001 FFF F5000000 F5001 FFF FFF80000 FFFOFFFF Figure 3 1 Simulator System Dialog Box Memory Page The following items can be specified in this dialog box Memory Map Displays the types of memory addresses where each starts and ends data bus width and number of access cycles Memory Resource Displays the access type and start and end addresses of the current memory resource The following buttons are used to alter Memory Map add modify or delete entries Add items to Memory Map Clicking on this button opens the Set Memory Map dialog box figure 3 2 in which an item can be added to the map al Modify an item in Memory Map Select the item to be modified in the list box and click on this button This opens the Set Memory Map dialog box figure 3 2 in which the selected memory map item can be modified Delete an item from Memory Map Select the item to be deleted in the list box and click on this button REJ10J1997 0100 Rev 1 00 April 2009 Page 7 of 15 QE NESAS Supe RISC engine Simulator Debugger V 9 09 00 upplementary Information for User s Manual In Memory Map the start address end address memory type data bus width number of cycles for reading and number of cycles for writing are displayed in that order The memory types are as follows e SH2A FPU ROM internal
8. ROM RAM internal RAM EXT external memory I O internal I O EEPROM e SH4A LRAM internal RAM EXT external memory I O internal I O IERAM internal RAM enhanced version only e SH4AL DSP XRAM internal XRAM YRAM internal YRAM URAM user RAM EXT external memory I O internal I O ILRAM internal RAM enhanced version only Click on the OK or Apply button to store the modified settings Click on the Cancel button to close this dialog box without modifying the settings 3 2 Set Memory Map Dialog Box The Set Memory Map dialog box specifies the memory map of the target CPU The contents of this dialog box depend on the target CPU The simulator debugger uses the data specified in this box to calculate numbers of cycles for memory access Cancel Begin address H 00000000 Bl End address H 05FFFEFF Data bus size 16 bi Read state count Write state count Figure 3 2 Set Memory Map Dialog Box The following items are specified Memory type Memory type Begin address Address where the area of the given type starts End address Address where the area of the given type ends Data bus size Memory data bus width Read state count When the memory type is ROM Latency REJ10J1997 0100 Rev 1 00 April 2009 Page 8 of 15 Supplementary Information for User s Manual g E N ESAS SuperH RISC engine Simulator Debugger
9. Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers office
10. To our customers Old Company Name in Catalogs and Other Documents On April 1 2010 NEC Electronics Corporation merged with Renesas Technology Corporation and Renesas Electronics Corporation took over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 1 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http www renesas com inquiry CENESAS 8 10 11 12 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is grant
11. ed hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document but
12. eline simulation REJ10J1997 0100 Rev 1 00 April 2009 Page 3 of 15 l SuperH RISC engine Simulator Debugger V 9 09 00 m EN ESAS Supplementary Information for User s Manual 1 3 Cache The cache capacity specifiable in the Cache Capacity dialog box is 8 16 32 or 64 Kbytes For details on cache see sections 2 8 Cache and 3 12 Viewing the Cache Contents in the SuperH RISC engine Simulator Debugger User s Manual 1 4 Memory Management Unit MMU The page size and protection key are shown as 4 and 6 bit data respectively in the TLB window For details on the MMU see sections 2 7 Memory Management Unit MMU and 3 11 Viewing the TLB Contents in the SuperH RISC engine Simulator Debugger User s Manual REJ10J1997 0100 Rev 1 00 April 2009 Page 4 of 15 2CENESAS 2 Simulating Peripheral Functions 2 1 SuperH RISC engine Simulator Debugger V 9 09 00 Supplementary Information for User s Manual Settings for Simulation of Peripheral Functions Settings for simulation of peripheral functions can be made on the Peripheral Function Simulation tabbed page of the Set Simulator dialog box Set Simulator CPU Configuration Peripheral Function Simulation m Peripheral Functions Module Name File Name Enable All O TMu C HE W40500R 56ENGST ools Renesas De Disable All fi 7 Peripheral Clock Rate T Don t show this dialog box F
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14. f Peripheral FUNCTIONS ccceeeceeeeeeeeeeeceeeeeceaeeeseaeeeeaeeseeeeesaeeesaaeeeeneeee 5 2 2 Simulation Of Timer MOGUICS iis usstraiini iniiis aa ty side a Aaaa E AAE E AEE AE 5 BS Memory Map pling asr rissssiiustanenideraaie siaaa anaana aaa a i aaa aa e aaa ana 7 3 1 Modifying the Memory Map and Memory Resource SettingS c cccccccsscceessseeeeessnteeeessseeeeeeaaes 7 3 2 Set Memory Map Dialog BOX 0 ccccceesceceeeeeeeeeeeaeeeeeeeceaeeeeaaeeeeaeeseeeeceaeeeeaaeseeaeeeseaeeseaaeseeaeeseeeees 8 3 3 Set Memory Resource Dialog BOX cceccceccceeeeeeeeeeeeeceeeeeeeaeeeseaeeseneeeseaeeesaaeeeeeeeseeeeseaeeeeaeeneaes 10 A PROTIG aussies eaaa eana aaa a a aai aa aa testes lean eevee eaaa 11 4 1 Types and Purposes of the Profile Data Displayed by the Profiler Function cccesseeeeees 11 5 WINDOWS erengan aaee n a a a E Ea E EE a EEE a ET ENS 12 6 G mmand Eine rcecney enuhan erat here a a a aa aTa 13 7a MESSAQOS cecicc cceiateves ies iicaaatategeheeaadsabiaceesadestesed sbalitewadte crlanscaalaesdubsdtyaadaeandeancesmeissealeeasthiigeahiieebiae 14 LV Enor M SSageSiiciisisia inde iti eta ein he aA ahi ed nee 14 REJ10J1997 0100 Rev 1 00 April 2009 Page 1 of 15 l SuperH RISC engine Simulator Debugger V 9 09 00 m EN ESAS Supplementary Information for User s Manual 1 Support for the Enhanced SH 4A Series MPUs Enhanced MPUs have been added to the SH 4A series The target names for the enha
15. ics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics 2CENESAS SuperH RISC engine Simulator Debugger V 9 09 00 Supplementary Information for User s Manual Introduction This document describes how V 9 09 00 of the SuperH RISC engine Simulator Debugger differs from V 9 08 00 Before using the simulator debugger carefully read this document the SuperH RISC engine Simulator Debugger User s Manual and the online help for the SuperH RISC engine Simulator Debugger Contents 1 Support for the Enhanced SH 4A Series MPUS 0 ceccceceeeeeeeeeeeeseeceeeeeceaeeeeaaeseeeeeseaeeesaeeesaaeeeenees 2 Te Range Of SimMUlatONsi sritan usanidi aaa dna aaa A AA aa RARE R EEEE NNAS 2 1 2 Type of Simulation and Endian 0 cccccccecceceeeeeeeeeceeeeceeeeeceaeeesaaeseeneeseaeeesaaeeesaaeeseeeescaeeesaeeseneeeeaees 3 did GaGh iss tnaienies Gas nie tei Gia ieee wi Adee dea ac 4 1 4 Memory Management Unit MMU ccccccceeceeeeeeee cence eceaeeeeaaeeeeeeeseaeeecaaesesaaeeeeeeeseaeeesaeeseneeeeaees 4 2 Simulating Peripheral FUNCTIONS ccccceeeececeeeeeeeeeeeeeee cee eeeeaeeeeaeeseeeeeceaeeesaaeeeeaeeseeeeeesaaesseaeeseeneess 5 2 1 Settings for Simulation o
16. igure 2 1 Set Simulator Dialog Box Peripheral Function Simulation Page For details on simulation of peripheral functions see section 3 3 Simulating Peripheral Functions in the SuperH RISC engine Simulator Debugger User s Manual 2 2 Simulation of Timer Modules V 9 09 00 of the simulator debugger has additional channels for simulation of timer modules in the SH 2A and SH 4A Table 2 1 Simulation of Timer Modules SH 2A SH 4A Timer CMT TMU Number of channels 2 channel 1 added 6 channels 1 2 4 and 5 added Counter 16 bit counter Auto reload 32 bit counter Counter input clock Four types of internal clock P 8 Po 32 Po 128 and P 512 are selectable e Five types of internal clock P 4 Po 16 Po 64 Po 256 and Po 1024 are selectable e External clock and output clock from the on chip RTC are not supported Input capture Not supported channel 2 Interrupts e Compare match interrupts are supported both channels e Interrupts as a trigger of a DMA transfer are not supported e Underflow interrupts are supported all channels e Input capture interrupts are not supported channel 2 REJ10J1997 0100 Rev 1 00 April 2009 Page 5 of 15 Supplementary Information for User s Manual g E N ESAS SuperH RISC engine Simulator Debugger V 9 09 00 Table 2 2 lists the timer control registers in the CMT and TMU supported by the simulator debugger Table 2 2 Timer Cont
17. nced MPUs are SH4AL DSP SH X2 Simulator and SH 4A SH X2 Simulator Both targets support pipeline and instruction unit simulation 1 1 Range of Simulation The simulator debugger for the enhanced SH 4A MPUs support the following CPU functions Table 1 1 CPU Functions Supported by the Simulator Debugger for the Enhanced SH 4A MPUs Names of Debugging Endian MMU Cache Control BSC DMAC Timer Platforms Register SH 4A SH X2 O O O O A SH4AL DSP SH X2 O O O O A Note O Supported Not supported A Partly supported Differences in the simulator debugger operation compared to that for the other SH 4A series MPUs are given in the following sections REJ10J1997 0100 Rev 1 00 April 2009 Page 2 of 15 a g E Ni E S ANS SuperH RISC engine Simulator Debugger V 9 09 00 Supplementary Information for User s Manual 1 2 Type of Simulation and Endian The type of simulation and endian can be selected on the CPU Configuration tabbed page of the Set Simulator dialog box that appears when the simulator debugger is started up Set Simulator Figure 1 1 Set Simulator Dialog Box CPU Configuration Page The following items are selectable on the CPU Configuration page Endian Endian for the CPU Big Big endian Little Little endian Simulation Mode Simulation mode Functional Instruction unit simulation Cycle Base Pip
18. ocated to a system memory resource cannot be deleted or modified Start by deleting the system memory resource allocation on the Memory tab of the Simulator System dialog box then delete or modify the memory map setting Clicking on the OK button stores the modified settings Clicking on the Cancel button closes the dialog box without modifying the settings REJ10J1997 0100 Rev 1 00 April 2009 Page 9 of 15 l SuperH RISC engine Simulator Debugger V 9 09 00 m EN ESAS Supplementary Information for User s Manual 3 3 Set Memory Resource Dialog Box The Set Memory Resource dialog box is used to set and modify memory resources Set Memory Resource 2 xi Begin Address K z Cancel End Address H o0000000 Attribute Read wiite Figure 3 3 Set Memory Resource Dialog Box The following items are specified Begin Address Address where the memory area to be allocated starts End Address Address where the memory area to be allocated ends Attribute Access type Read Read only Write Write only Read Write Readable writable Click on the OK button after specifying Begin Address End Address and Attribute Click on the Cancel button to close the dialog box without modifying the settings Notes 1 When a memory resource is set memory in the host computer will be used If the user allocates excessive memory resources operation of the host computer will be extremely slow
19. rograms algorithms and application circuit examples is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas products listed in this document please confirm the latest product information with a Renesas sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website http www renesas com 5 Renesas has used reasonable care in compiling the information included in this document but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document 6 When using or otherwise relying on the information in this document you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application Renesas makes no representations warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products 7 With the exception of products specified by Renesas as suitable for automobile applications Renesas products are not designed manufactured or tested for applications or otherwise in systems the failure or malfunction of which ma
20. rol Registers Debugging Platform Timer Control Register SH 2A CMT CMSTR wn Cc xe Ss e gt CMCSRO CMCNTO CMCORO CMCSR1 CMCNT1 CMCOR1 SH 4A TMU TOCR TSTRO TCORO TCNTO TCRO TCOR1 TCNT1 TCR1 TCOR2 TCNT2 TCR2 TCPR2 TSTR1 TCOR3 TCNT3 TCR3 TCOR4 TONT4 TCR4 TCORS TCNT5 D gt O O O O Of 0 O O O 0 0 gt 0 0 Of O O O 0 0 0 0 TCR5 Note O Supported A Partly supported only for the bits associated with the functions given in table 2 1 Not supported only memory resources have been allocated REJ10J1997 0100 Rev 1 00 April 2009 Page 6 of 15 g E N ESAS SuperH RISC engine Simulator Debugger V 9 09 00 Supplementary Information for User s Manual 3 Memory Mapping The specification of memory mapping for the SH 2A was changed in V 9 08 00 This section describes the new specification of memory mapping 3 1 Modifying the Memory Map and Memory Resource Settings The Memory tabbed page in the Simulator System dialog box is used to set and modify the memory map and memory resource settings Simulator System a E 2 xi System Memory Memory Map Da da Ka gt s Memory Resource lee a oooo0000 001FFFFF oo0o0000 OOOFFFFF FOOOOO00 F5FFFFFF FOOOO000 FOOFFFFF FFF80000 FFFBFFFF FOs00000 FOSFFFFF FFFCOOOO FFFFFFFF F1000000 F
21. rtain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electron
22. ssages Table 7 1 lists the error messages that have been added or modified in V 9 09 00 Table 7 1 New or Modified Error Messages Message Incorrect memory type The specified address range includes an area fixed as rr Area fixed as rr OXmmmmmmmm Oxnnnnnnnn Description An attempt was made to assign another memory type to an area fixed as ROM or RAM rr ROM or RAM Oxmmmmmmmm Address where the fixed area starts Oxnnnnnnnn Address where the fixed area ends Allocating two or more ranges in an area fixed as rr is not possible Area fixed as rr O0xmmmmmmmnm Oxnnnnnnnn An attempt was made to allocate two or more ranges in an area fixed as ROM or RAM rr ROM or RAM Oxmmmmmmmm Address where the fixed area starts Oxnnnnnnnn Address where the fixed area ends Incorrect address The specified address range includes a reserved area Reserved area 0xmmmmmmmn Oxnnnnnnnn An attempt was made to map memory to a reserved area Oxmmmmmmmm Address where the reserved area starts Oxnnnnnnnn Address where the reserved area ends I O area does not exist I O area OxFOO00000 OxF5FFFFFF No memory has been mapped as the I O area Incorrect address The specified address range is outside an area fixed as rr Area fixed as rr 0xmmmmmmmnm Oxnnnnnnnn REJ10J1997 0100 Rev 1 00 An attempt was made to map memory beyond the boundaries of an area fixed as ROM or RAM rr ROM or RAM Oxmmmmmmmm Address
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