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EVM-91L30

1. lt 41 8 1 EYE DIAGRAM TEST 41 Figure 8 0 Remove Analog Local 41 Figure 8 1 Ignore PRBS Sync and PRBS Sync Hist 42 Figure 5 2 XRT91L30 Eye Diagram m 42 8 2 XRT91L30 CURRENT CONSUMPTION MEASUREMENT 43 Figure 8 3 Main GUI Window 44 Figure 8 4 Select Data 44 Figure 8 5 Select Looptiming 45 Figure 8 6 Enable FPGA Remote 45 EXAR Experience Our Connectivity EVM 91 L30 SONET STS 12 STS 3 or SDH STM A STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 Figure 1 0 XRT91L30 Block Diagram STS 12 STM 4 or STS 3 STM 1 TRANSCEIVER 2 p PISO EE E gt Parallel Inp
2. Digital Loopback 32 Bit User Pattern gt CMU Freqency Select Remote Serial LB User Pattern 55555555 e 77 76 MHz 19 44 MHz System Control Tx P Clock Direction pres Input goin Q Pattern Sync Transmit Timing Pattern sync Hist Click Write Pattern Local Timing Loop Timing Reset Pat Sync Hist Start Poll CDR Reference Clock Select SEP Module Control Ss TxDisable ForceLOS Mode Bypassed 9 SFP Detect Master Reset PxLOS Force Reframe LOS Det Disable Tx Fault In Progress 31 EXAR Experience Our Connectivity SONET STS 12 STS 3 or SDH STM 4 STM 1 XRT91L30 Optical Evaluation Board User Manual EVM 91L30 Feb 09 2006 Step 11 Click on Start Poll button The In Progress indicator will start flashing green when polling has begun Figure 6 26 Start Polling XRT91L30 Evaluation System X XRT31L30 Control Local Loopbacks ue n tt Data Rate Analog Loopback v Te Faem n 1 26 Digital Loopback 32 Bit User Pattern v CMU Fregency Select Remote Serial LB UserPattem 55555555 e 77 76 MHz 19 44 MHz System Control Tx P Clock Direction T gon e ZUR Pattern Sync 00000000 Transmit Timing 9 Pattern sync Hist Local Timing Loop Timing Reset Pat Sync Hist start Poll CDR Reference Clock Select SEP Module Control A CMU C CDRAUX 7 T
3. Input Output Transmitted 00000000 Pom User Pattern Transmit Timing Pattern Sync Hist Local Timing t TENE Reset Pat Sync Hist Start Poll CDR Reference Clock Select SEP Madule Control e CMU CDRAUX a Tx Disable ForceeLOS Bypassed W SFP Detect Master Reset WRxLOS Force Reframe LOS Det Disable Tx Fault Q In Progress 28 Experience Our Connectivity EVM 91L30 SONET STS 12 STS 3 or SDH STM 4 STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 Step 5 Select Output direction for the XRT91L30 transmit parallel clock This is due to the FPGA design limitation when using the 32 bit User Pattern generator Figure 6 20 Select Transmit Parallel Clock Output Direction XRT91L30 Evaluation System XRT31L30 Control Data Rate 155 52 Mbps 622 08 Mbps CMU Fregency Select e 77 75 MHz 19 44 MHz Tx P Clock Direction Input e Output Transmit Timing LocalTiming C x Local Loopbacks Analog Loopback Digital Loopback Tx Pattern On 00000000 Remote Serial LB System Control E FPGA Remote Loopback Pattern Sync Pattern Sync Hist User Pattern Write Pattern Transmitted User Pattern 00000000 Select Output Tx Parallel Clock Direction fart OK CDR Reference Clock Select SEP Module Control CMU CDR AUX Tx Disable E 0
4. Experience Our Connectivity EVM 91 L30 SONET STS 12 STS 3 or SDH STM 4 STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 622 08 155 52 MBPS SONET STS 12 STS 3 SDH STM 4 STM 1 XRT91L30 Transceiver Evaluation Board User Manual Experience Our Connectivity EVM 91 L30 SONET STS 12 STS 3 or SDH STM 4 STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 Figure 1 0 XRT91L30 Block Diagram 4 1 0 OVERVIEW 4 2 0 EVALUATION BOARD 1 61 5 Figure 2 0 XRT91L30 Optical Evaluation Board revision 0 5 2 1 FPGA FUNCTIONALITY AND CONTROL 6 2 2 XRT91L30 CLOCK REFERENCE 6 2 EA TURES 6 2 4 EVALUATION BOARD
5. 7 3 0 USB DRIVER AND GRAPHICAL USER INTERFACE INSTALLATION 8 3 1 INSTALLING THE EXAR USB DRIVER 2 8 Figure 3 1 Add New HardWOEG noc sue cuu ed 8 Figure 3 2 Select Display Available Drivers and then Next 9 Figure 3 3 Select Other detected devices and then Next 9 Figure 3 4 Select Have aaa kae a x KaL E dua Ea UE unu x apis 10 Figure 3 5 Find the location of the drivers located on the CD 10 Figure 3 6 Install FROME DISK 10 Figure 3 7 nido M 11 Figur TS 11 Figure 3 9 Installation Successful 12 3 2 INSTALLING THE XRT91L30 EVALUATION 12 Figure 3 10 TSS a aa a A iN 12 4 0 XRT91L30 EVALUATION SOFTWARE 13 4 1 STARTING THE EVALUATION 13 TUS TES oeo 13
6. 24 Experience Our Connectivity EVM 91L30 SONET STS 12 STS 3 or SDH STM 4 STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 Step 7 To enable the 2 1 PRBS pattern generator and analyzer block within the FPGA select the 42 1 PRBS Pattern box from the pattern selection menu Figure 6 13 Select 2 1 PRBS Pattern Generator and Analyzer XRT91L30 Evaluation System x Force LOS Force Reframe XRT31L30 Control Data Rate e 155 52 Mbps 622 08 Mbps CMU Fregency Select e 77 76 MHz 19 44 MHz Tx P Direction Input e Output Transmit Timing LocalTiming Loop Timing CDR Reference Clack Select fe CMU CDRAUX CDR Mode Bypassed LOS Det Disable Local Loopbacks Analog Loopback Digital Loopback Remote Serial LB system Control i FPGA Remote Loopback Pattern Sync Pattern Sync Hist Reset Pat Sync Hist SFP Module Control Tx Disable SFP Detect RxLOS Tx Fault 2 31 1 PRBS Pattern gt 32 Bit User Pattern 2 31 1 PRBS Pattern Tra 010070000000 User Pattern Start Poll OK Master Reset In Progress Select PRBS Pattern Note If PRBS Pattern generator and analyzer is not selected 32 bit User Pattern selected a 32 bit user pattern defined in the User Pattern buffer will be transmitted
7. Limitation 1 Due to FPGA design limitations the Evaluation Board currently does not support Analog and Digital Local Loopbacks in STS 12 STM 4 data rate mode using 19 44 MHz reference clock This limitation will be removed in the future At this time one can use 77 76 MHz reference clock in STS 12 STM 4 data rates to invoke Analog and Digital Local Loopbacks This limitation does not apply to STS 3 STM 1 data rates Limitation 2 The PRBS state machine design implemented the Transmit Parallel Clock Output TXPCLK lO to be configured for Output Therefore set the Tx P Clock Direction to Output whenever transmitting PRBS pattern This limitation also applies when using the 32 bit User Pattern generator Limitation 3 Whenever FPGA Remote Loopback is used Looptiming must be implemented This guarantees that transmit timing is synchronous to the signal source timing thereby preserving data integrity at high SONET SDH bit rates Experience Our Connectivity EVM 91 L30 SONET STS 12 STS 3 or SDH STM 4 STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 3 0 USB DRIVER AND GRAPHICAL USER INTERFACE INSTALLATION This section details the installation of the software GUI provided as part of the evaluation process It includes the following topics 3 1 Installing the Exar USB Driver 3 2 Installing the Evaluation Software 3 1 INSTALLING THE EXAR USB DRIVER In order to operate the XRT91L30 GUI with the XRT91L30 Eva
8. 4 2 USING THE EVALUATION SOFTWARE 14 Figure 4 2 Main GUI Window s sud wks atu oa Gueule dava uuu 14 4 3 XRT91L30 GUI CONTROL DISPLAY ASSOCIATION 15 Table 1 0 XRT91L30 GUI Display Cross 15 Table 1 1 FPGA Functions GUI Display Cross Reference 16 5 0 SETTING UP THE XRT91L30 EVALUATION BOARD FOR SONET SDH TESTING 17 Figure 5 1 Transceiver Test 17 6 0 EXAMPLE APPLICATIONS cisssccetisetiseerestceracsenosecuseccuedesincesdeseetosesnscndvedevenesedcuavast 18 6 1 LOOPBACK OPERATIONS sssssssnnnunnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nnnm mnnn nnna 18 6 1 1 Serial Remote 18 Figure 6 1 XRT91L30 Serial Remote 18 Figure 6 2 Main GUI Window 19 Figure 6 3 Select Dat
9. Desi qu Du Ced d 32 Figure 6 27 Verify Transmitted Pattern 32 MASTER 33 PIQUIC 6 26 Master 33 6 4 SFP MODULE CONTROL M 33 Table 2 0 SFP Module Control 801 33 Figure 6 29 SFP Module Control 33 7 0 CONFIGURING THE XRT91L30 EVALUATION BOARD FOR JITTER MEASUREMENTS 34 Figure 7 0 Jitter Measurement Setup 34 7 1 HOW TO MEASURE OPTICAL JITTER TOLERANCE OF THE XRT91L30 34 Figure 7 1 Select 2 2 35 Figure 7 2 Optical Signal Strength Test Equipment 35 Figure 7 3 STS 3 GR 253 Jitter Tolerance Mask Test Equipment 35 7 2 HOW TO MEASURE OPTICAL JITTER TRANSFER OF THE XRT91L390 36 Figure 7
10. Fregency Select e 77 75 MHz 19 44 MHz Tx P Clock Direction Input e Output Transmit Timing Local Timing Loop Timing CDR Reference Clock Select e CMU CDR AUX ForceLOS Mode Bypassed Force Reframe LOS Det Disable Local Loopbacks Analog Loopback Digital Loopback Tx Pattern On Enable Transmit Pattern Remote Serial LB User Patten 00000000 System Control FPGA Remote Write Pattern i Loopback Transmitted 00000000 User Pattern wW Pattern Sync Hist Reset Pat Sync Hist Start Poll SFP Module Control Tx Disable SFP Detect Master Reset PxLOS Tx Fault In Progress Step 8 Select 32 bit User Pattern on the Pattern Selection box below Figure 6 23 Select 32 bit User Pattern XRT91L30 Evaluation System RT91L30 Control Data Rate 155 52 Mbps 622 08 Mbps CMU Freqency Select e 77 76 MHz 19 44 MHz Tx P Clock Direction Input e Output Transmit Timing LocalTiming Loop Timing CDR Reference Clock Select e CMU CDRAUX ForceLOS f CDR Mode Bypassed Force Reframe LOS Det Disable Local Loopbacks Analog Loopback Digital Loopback Remote Serial LB system Control FPGA Remote Tx Pattern On 32 User Pattern v 32 Bit User Pattern 2 X 1 PRBS Pattern Select 32 bit User Pattern Loopback Transmitted 00000000 User Pattern W Pattern Sy
11. Manual Feb 09 2006 Figure 6 15 Check Pattern 26 Figure 6 16 Check Pattern LOSS 26 6 2 TRANSMITTING A USER DESIRED 32 BIT PATTERN nennen enar 20 Figure 6 18 XRT91L30 Serial Remote 28 Figure 6 19 Select Data Rale 28 Figure 6 20 Select Transmit Parallel Clock Output Direction 29 Figure 6 21 Select Local 0 29 Figure 6 22 Enable Transmit Pattern On 30 Figure 6 23 Select 32 bit User Pattern 30 Figure 6 24 Enter 32 bit User Pattern 31 Figure 6 25 Click Write Paltern uiuo tractus tuu p Des Deu cra xE Dco o iuga 31 Figure 6 26 Start Polling oisi xu Deseciuaamcvadutevidts uiua radured0eBdsdax rave Dre C mua
12. Progress 21 EXAR Experience Our Connectivity EVM 91 L30 SONET STS 12 STS 3 or SDH STM A STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 6 1 2 PRBS Pattern Synch Test using Analog Local Loopback This loopback needs to be invoked whenever local diagnostic is desired as such when the PRBS generator and analyzer are used Local transmit data is looped back at the analog drivers Figure 6 7 XRT91L30 Analog Local Loopback Analog Local Loopback ow i LVPECL iu Tx Parallel Input FIFO PISO Output Drivers Tx Serial Output LVPECL Rx Parallel Output Input ae Configuring for 2 1 PRBS pattern test using Analog Local Loopback Operation Step 1 Proceed with the same steps as Step 1 through Step 4 for Remote Serial Loopback Operation in configuring the XRT91L30 board Step 2 Select the desired Data Rate signal STS 3 STM 1 at 155 52 Mbps or STS 12 STM 4 at 622 08 Mbps Figure 6 8 Select Data Rate XRT91L30 Evaluation System XRT31L30 Control Local Loopbacks XP tt Data Rate Analog Loopback PAESE 15552MMbps 622 08 Mbps Digital Loopback 22 BitUserPattem x CMU 5 55561 Select STS 3 575 12 Data Rate dude LB UserPetem 00000000 Tx P Clock Direction ale F ONON Input Output Transmitted 00000000 User Pattern Transmit Timing w Pattern Sync Hist Local Timing Loop Timing Reset Pat Sync Hist
13. U1 Controller 1f n 2 J A U7 U4 U11 XRT91L30 gt p Power Regulator mimi 30 Evaluation Board 3000027 Optional Clock Power LED GPIO Bus JTAG Recoverey Input Evaluation board consists of XRT91L30 device U11 connected to a Small Form Factor Pluggable SFP module U12 Since the XRT91L30 is a pure hardware pin control device and does not support microprocessor interface the XRT91L30 hardware control pins are interfaced to a field programmable logic device FPGA U3 The logical level of the XRT91L30 control pins is controlled from a Graphical User Interface GUI program installed on a personal computer PC Evaluation board power and GUI communication interface are then both provided through the Universal Serial Bus USB from the PC Other system level components on the evaluation board include a USB microcontroller U1 a switching power regulator U4 and a 77 76 MHz crystal oscillator U7 There are several other optional components for evaluation of supported special features of the XRT91L30 device EXAR Experience Our Connectivity EVM 91 L30 SONET STS 12 STS 3 or SDH STM A STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 2 1 FPGA FUNCTIONALITY AND CONTROL The FPGA controls most of the function of the device under test DUT in this case t
14. by checking the on the Remote Serial LB box Figure 6 4 Select Looptiming XRT91L30 Evaluation System x RT91L30 Control Data Rate e 155 52 Mbps 622 08 Mbps CMU Fregency Select e 77 76 MHz 19 44 MHz Tx P Clock Direction e Input Output Transmit Timing Local Timing Loop Timing Local Loopbacks Analog Loopback Digital Loopback Tx Pattern On 00000000 Remote Serial LB system Control a FPGA Remote User Pattern Write Pattern Loopback Transmitted 00000000 2 Pattern Sync User Pattern w Pattern Sync Hist k Reset Pat Sync Hist Start Poll CDR Reference Clock Control CMU C Select Loop Timing ea Force LOS CDR Mode Bypassed Force Reframe LOS Det Disable SFP Detect Master Reset RxLOS Tx Fault In Progress Figure 6 5 Enable Serial Remote Loopback XRT91L30 Evaluation System x RT91L30 Control Data Rate e 155 52 Mbps 622 08 Mbps CMU Fregency Select e 77 76 MHz 18 44 MHz Tx P Clock Direction e Input Output Transmit Timing Local Timing Loop Timing CDR Reference Clock Select CMU CDRAUX ForceLOS CDR Mode Bypassed Force Reframe LOS Det Disable Local Loopbacks Analog Loopback Digital Loopback Tx Pattern 00000000 Remote Serial User Pattern Sy Nem Control Enable Remote Serial Loopback ransmited 00000000 EUA User Pattern
15. using Analog Local Loopback Use step 1 thru step 8 Step 2 Remove the Analog Local Loopback Do not enable any loopbacks Step 3 Select the desired reference clock frequency 77 76 MHz or 19 44 MHz to be tested Figure 7 10 Select Desired Reference Clock Frequency to be tested CMU Fregency Select e 77 75 MHz 19 44 MHz Select Desired Reference Clock Frequency Step 4 Select Local Timing Mode for the XRT91L30 transmit timing Figure 7 11 Select Local Timing Transmit Timing LocalTiming Loop Timing Select Local Timing Step 5 Select the proper SONET SDH data rate source on test equipment and verify test equipment is able to obtain valid signal from the XRT91L30 optical transmitter Note Since the XRT91L30 is independently transmitting unframed 2 1 PRBS pattern to the test equipment data integrity and pattern sync on the tester is not expected However tester should detect an unframed OC12 STM 4 or OC3 STM 1 signal 39 EXAR Experience Our Connectivity 91 130 SONET STS 12 STS 3 SDH STM 4 STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 Step 5 Verify that the optical signal strength is valid for jitter measurements Adjust optical signal strength by adding removing optical attenuators or slightly adjusting optical coupler until desired optical signal strength is achieved for valid jitter measurements Figure 7 12 Verify Optical Signal Strength Test Equipment RESULTS OPT
16. 4 Select Looptiming 36 Figure 7 5 STS 3 GR 253 Jitter Transfer Mask Test Equipment 36 Figure 7 6 Verify Optical Signal Strength Test Equipment 37 Figure 7 7 Jitter Transfer Calibration Test Equipment 37 Figure 7 8 Reattach Evaluation Board optical cable 38 Figure 7 9 Re Verify Optical Signal Strength Test Equipment 38 7 3 HOW TO MEASURE OPTICAL INTRINSIC JITTER OF THE XRT91L30 39 Figure 7 10 Select Desired Reference Clock Frequency to be tested 39 Figure 7 11 Select Local 1 iie ricotta kino rani xv vaa yx Oc Vus 39 Figure 7 12 Verify Optical Signal Strength Test Equipment 40 Table 3 0 SONET SDH Jitter Frequency Bandpass Filters 1 544 kb s Networks 40 Table 3 1 SONET SDH Jitter Frequency Bandpass Filters 2048 kb s Networks 40 Figure 7 13 RMS Jitter Measurement Test Equipment 40 8 0 OTHER MEASUREMENTS
17. 7 7 Once optical loopback cable is inserted verify data integrity and pattern sync 36 EXAR Experience Our Connectivity 91 130 SONET STS 12 STS 3 SDH STM 4 STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 Step 6 Verify that the optical signal strength is valid for jitter measurements before proceeding with calibration Adjust optical signal strength by adding removing optical attenuators or slightly adjusting optical coupler connector until desired optical signal strength is achieved for valid jitter measurements Figure 7 6 Verify Optical Signal Strength Test Equipment RESULTS OPTICAL POWER DUT OF RANGE BER 9 JITTER 40 30 20 10 dBm Be a ees OPTICAL PWR 15 0 dBm ELAPSED TIME 00d 1 55m 265 Step 7 Follow test equipment instructions for calibration and do not interrupt calibration process Figure 7 7 Jitter Transfer Calibration Test Equipment PC with XRT91L30 Eval Board GUI TransFer Function Calibration In Progress Press to Abort Optical Network Tester Self Calibration Process Proportion complete 77 rz FPGA detach 223 eval board optical cable XRT91L30 during optical Eval Board calibration loopback cable for calibration 37 EXAR Experience Our Connectivity EVM 91 L30 SONET STS 12 STS 3 or SDH STM A STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 Step 8 Once initial c
18. 8 CDR Mode Bypassed w SFP Detect Master Reset RxLOS Force Reframe LOSDetDisable Tx Fault In Progress Step 6 Select Local Timing mode for the XRT91L30 transmit timing Figure 6 21 Select Local Timing XRT91L30 Evaluation System RT91L30 Control Data Rate 155 52 Mbps 622 08 Mbps CMU Fregency Select e 77 75 MHz 19 44 MHz Tx P Clock Direction C Input e Output Transmit Timing LocalTiming Loop Timing CD K eference Clock Select d Select Local Timing Force LOS CDR Mode Bypassed LOS Det Disable Force Reframe Local Loopbacks Analog Loopback Digital Loopback Tx Pattern On 00000000 Remote Serial LB System Control FPGA Remote Loopback Pattern Sync w Pattern Sync Hist User Pattern Vvrite Pattern i Transmitted User Pattern 00000000 Reset Pat Sync Hist Start Poll SFP trol odule Contro Tx Disable SFP Detect Master Reset RxLOS QJ Tx Fault In Progress 29 EXAR Experience Our Connectivity EVM 91L30 SONET STS 12 STS 3 or SDH STM 4 STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 Step 7 To enable the transmission of pattern signal from the FPGA check the Tx Pattern On box Figure 6 22 Enable Transmit Pattern On gt XRT91L30 Evaluation System XRT31L30 Control Data Rate e 155 52 Mbps 622 08 Mbps CMU
19. ICAL POWER DUT OF RANGE BER JITTER 40 30 20 10 dBm Beene ne ee ee eee ee OPTICAL PWR 15 0 dBm ELAPSED TIME OOd Olh 55 265 Step 6 Configure the test equipment for jitter measurements and select the appropriate SONET SDH STS 12 STM 4 or STS 3 STM 1 jitter frequency filters on the test equipment according to the table below Table 3 0 SONET SDH Jitter Frequency Bandpass Filters 1 544 kb s Networks DATA RATE SONET GR 253 FILTER STANDARD SDH G 783 FILTER STANDARD 155 52 Mbps 12 KHz 1 3 MHz 12 KHz 1 3 MHz 622 08 Mbps 12 KHz 5 0 MHz 12 KHz 5 0 MHz Table 3 1 SONET SDH Jitter Frequency Bandpass Filters 2048 kb s Networks DATA RATE SONET GR 253 FILTER STANDARD SDH G 783 FILTER STANDARD 155 52 Mbps 12 KHz 1 3 MHz 65 KHz 1 3 MHz 622 08 Mbps 12 KHz 5 0 MHz 250 KHz 5 0 MHz Step 7 Begin measuring jitter and permit test equipment to measure peak to peak and rms values over a sixty second interval 1 minute maximum per G 783 section 9 3 1 1 Figure 7 13 RMS Jitter Measurement Test Equipment RESULTS JITTER VE PEAK 0 008UI UE PERK 0 01501 PERK PERK 024LUI RMS 0 003UI FILTERS 1 ELAPSED TIME 009 00h 0 065 40 Experience Our Connectivity E V M 9 1 L 3 SONET STS 12 STS 3 SDH STM 4 STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 8 0 Other Measurements The following test measurements may also be done on the
20. Local Timing Pre inp CDR Reference Clock Select ad Pattern Sync History Error ForceLOS CDR Mode Bypassed SFP Detect Master Reset RxLOS Force Reframe LOS Det Disable Tx Fault Q In Progress 26 EXAR Experience Our Connectivity EVM 91 L30 SONET STS 12 STS 3 or SDH STM A STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 To reset the momentary Pattern Sync Hist indicator click the Reset Pat Sync Hist button Figure 6 17 Resetting Pattern Loss Indicator XRT91L30 Evaluation System X RT91L30 Control Local Loopbacks Data Rate e 155 52 Mbps 622 08 Mbps v Tx Pattern v Analog Loopback ous Digital Loopback 2 31 1 PRBS Pattern CMU Freqency Select Remote Serial LB User Pattern 00000000 e 77 76 MHz 19 44 MHz System Control Tx P Clock Direction a een Write Pattern C Input Output Transmitted 00000000 User Pattern Transmit Timing W Pattern Sync Hist LocalTiming Loop Timing Polling Press to Stop Reset Pat Sync Hist CDR Reference Clock Select SFP hiodh CMU CDR AUX TxDi Force LOS CDR Mode Bypassed SFP Detect Master Reset RxLOS Force Reframe LOS Det Disable Tx Fault In Progress 27 EXAR Experience Our Connectivity EVM 91 L30 SONET STS 12 STS 3 or SDH STM A STM 1 XRT91L30 Optical Evaluation Board User Manual Fe
21. P Module Control SFF Module Control Tx Disable SFP Detect Px LOS Tx Fault 33 EXAR Experience Our Connectivity EVM 91 L30 SONET STS 12 STS 3 or SDH STM A STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 7 0 CONFIGURING THE XRT91L30 EVALUATION BOARD FOR JITTER MEASUREMENTS There are three types of jitter measurement of interest in the XRT91L30 transceiver product They are received jitter tolerance jitter transfer and transmit intrinsic jitter e How to measure optical Jitter Tolerance of the XRT91L30 e How to measure optical Jitter Transfer of the XRT91L30 e How to measure optical Intrinsic Jitter of the XRT91L30 Since the XRT91L30 Evaluation Board uses an optical interface a network tester with an optical interface capable of jitter measurements will be required to successfully characterize optical jitter performance on the XRT91L30 Below 15 a simple diagram of the jitter measurement setup Figure 7 0 Jitter Measurement Setup PC with XRT91L30 Eval Board GUI SS Optical Network Tester i gm 91130 FPGA USB cable mode fiber XRT91L30 Eval Board 7 1 HOW TO MEASURE OPTICAL JITTER TOLERANCE OF THE XRT91L30 To successfully perform this test the user needs to configure the XRT91L30 into Remote Serial Loopback Looptiming Step 1 Configure the XRT91L30 for Serial Remote Loopback as outlined in the Example Applications in section 6 1 1 Serial Remot
22. PGA Loopback Enabled Enables transmission of Selected Pattern LI No transmit pattern selected Begin pattern transmission Selects User desired 32 bit pattern 32 BitUserPatten v or Auto generated 2 1 PRBS 32 Bit User Pattern attern N 1 PRBS Pattern Pattern Select 32 bit User Pattern Hexadecimal User Pattern User Pattern 5 Writes desired pattern into buffer Write Fattern Write Pattern Transmitted 0000000 Transmitted User Indicates transmitted user pattern User Pattern Pattern Sync Pattern Sync Indicates PRBS pattern sync status zd Indicates PRBS pattern error 9 Pattern Sync Hist Pattern Sync Hist history Reset Pat syne Hist Indicates currently pollin Tx Pattern On Tx Pattern On Select Transmit Pattern n Resets Pattern Sync History Reset Pattern Sync indicator EXAR Experience Our Connectivity EVM 91 L30 SONET STS 12 STS 3 or SDH STM A STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 5 0 SETTING UP THE XRT91L30 EVALUATION BOARD FOR SONET SDH TESTING Figure 5 1 Transceiver Test Setup PC with XRT91L30 Eval Board GUI Optical SS Network Tester rz FPGA USB cable 9130 single mode fiber XRT 91L30 Eval Board Use the following steps in configuring the XRT91L30 Evaluation Board 1 Install Exar supplied USB drivers and XRT91L30 GUI on the PC 2 Connect th
23. Start Pall CDR Reference Clock Select SEP Module Control CMU CDR AUX m Tx Disable 08 Mode Bypassed W SFP Detect Master Reset Rx LOS Force Reframe LOS Det Disable Tx Fault In Progress 22 Experience Our Connectivity EVM 91L30 SONET STS 12 STS 3 or SDH STM 4 STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 Step 3 Select Output direction for the XRT91L30 transmit parallel clock This is due to the FPGA design limitation when using the 2 1 PRBS pattern generator Figure 6 9 Select Transmit Parallel Clock Output Direction XRT91L30 Evaluation System XRT31L30 Control Data Rate 155 52 Mbps 622 08 Mbps CMU Fregency Select e 77 75 MHz 19 44 MHz Tx P Clock Direction Input e Output Transmit Timing CDR Reference Clock Select e CMU CDRAUX ForceLOS CDR Mode Bypassed Force Reframe LOS Det Disable Local Loopbacks Analog Loopback Digital Loopback Tx Pattern On 00000000 Remote Serial LB System Control FPGA Remote Loopback User Pattern Write Pattern i Transmitted Pattern Sync User Pattern Pattern Sync Hist 00000000 LocalTiming C Select Output Tx Parallel Clock Direction tart pai SFP Module Control Tx Disable SFP Detect Master Reset RxLOS W Tx Fault In Progress Step 4 Select Local Timing m
24. T91L30 Evaluation System X XRT31L30 Control Local Loopbacks gt 5 tt Data Pate Analog Loopback e 155 52 Mbps 622 08 Mbps Digital Loopback 2 31 1 PRBS Pattern CMU Fregency Select Uncheck to remove Analog Local Loopback e 77 76 MHz 19 44 MHz System Control Ru Tx P Clock Direction a 0 in _ Pattern C Input e Output Transmitted 00000000 Pattern Sync User Pattern Transmit Timing 2 Pattern Sync Hist imi Loop Timi Polling Local Timing eee Reset Pat Sync Hist Press to Stop CDR Reference Clock Select SFP Madule Control ForceeLOS Mode Bypassed SFP Detect Master Reset 105 Force Reframe LOS Det Disable Tx Fault Qin Progress EXAR Experience Our Connectivity EVM 91 L30 SONET STS 12 STS 3 or SDH STM A STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 Step 4 Ignore PRBS Sync Error and PRBS Sync Hist Error Ignore SFP Module errors as well This error is due to the removal of the SFP optical module and loopbacks being removed and PRBS data not being sent back to the PRBS analyzer Figure 8 1 Ignore PRBS Sync and PRBS Sync Hist Error XRT91L30 Evaluation System X RT91L30 Control Local Loopbacks Data Rate Tx Pattern On Analog Loopback 155 52 Mbps 622 08 Mbps Digital Loopback 2 31 1 PRBS Pattern v CMU Fregency Select _ dd Remote Serial LB User Pattern 00000000 e 7776 MHz 18 44 MHz
25. XRT91L30 Evaluation Board These types of test may require hardware board modifications 8 1 Eye diagram test setup 8 2 XRT91L30 Current Consumption Measurement 8 1 EYE DIAGRAM TEST SETUP To display the eye diagram pattern successfully the user must have the following A high speed digital oscilloscope A high impedance or 50 Ohm effective termination differential high speed probe with a minimum bandwidth at least twice the data rate frequency Use a probe with a minimum of 2 GHz bandwidth he XRT91L30 Evaluation Board schematic for reference In addition the user must configure the XRT91L30 to do the following e Transmit 2 1 PRBS pattern e Normal Mode of Operation Remove Loopbacks e Local Timing Mode Step 1 Remove the SFP optical module Find pin 5 and pin 6 of the XRT91L30 These are the TXOP and TXON LVPECL high speed differential outputs respectively Prepare the pins for probing this may or may not require soldering biasing resistors as required by the differential probe manufacturer Refer to XRT91L30 Evaluation Board schematic for reference and termination information Step 2 Configure the XRT91L30 to transmit the internally generated 2 1 PRBS pattern as outlined in Example Applications in section 6 1 2 PRBS Pattern Synch Test using Analog Local Loopback Use step 1 thru step 8 Step 3 Remove the Analog Local Loopback Do not enable any loopbacks Figure 8 0 Remove Analog Local Loopback XR
26. a Rate ean 19 Figure 6 4 LOOP TWINS TT 20 Figure 6 5 Enable Serial Remote 0000 6 20 Figure 6 6 Disable Serial Remote 00 0 6 21 6 1 2 PRBS Pattern Synch Test using Analog Local Loopback 22 Figure 6 7 XRT91L30 Analog Local Loopback 22 Figure 6 8 Select Data Hal niic Ph redi 22 Figure 6 9 Select Transmit Parallel Clock Output Direction 23 Figure 6 10 Select Local uiia tuni na xou Eu suani Rex aca run sn ues 23 Figure 6 11 Enable Analog Local Loopback eee 24 Figure 6 12 Enable Transmit Pattern On 24 Figure 6 13 Select 2 1 PRBS Pattern Generator and 25 Fi r 6 14 Start dele aa 25 Experience Our Connectivity EVM 91 L30 SONET STS 12 STS 3 or SDH STM 4 STM 1 XRT91L30 Optical Evaluation Board User
27. alibration is done replace the optical loopback cable on the test equipment with the Evaluation Board optical cable Verify that transmit and receive cables are properly oriented and test equipment receiver does not declare Loss of Signal Once Evaluation Board optical cable is inserted and data integrity and pattern sync is achieved verify that the optical signal strength is valid for jitter measurements before proceeding to the next step Figure 7 8 Reattach Evaluation Board optical cable PC with XRT91L30 Eval Board GUI 6 Optical Network Tester USB cable 09 single mode fiber XRT91L30 Eval Board Figure 7 9 Re Verify Optical Signal Strength Test Equipment RESULTS OPTICAL POWER DUT OF RANGE BER ONLY BER amp JITTER 40 30 20 10 OdBn Mint vices seen OPTICAL PWR 15 0 dBm ELAPSED TIME 00d 1 55m 265 Step 9 Begin Jitter Transfer Measurements 38 EXAR Experience Our Connectivity EVM 91 L30 SONET STS 12 STS 3 or SDH STM A STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 7 3 HOW TO MEASURE OPTICAL INTRINSIC JITTER OF THE XRT91L30 To successfully perform this test the user needs to configure the XRT91L30 into e Transmit a 27 1 PRBS pattern Local Timing Mode Step 1 Configure the XRT91L30 to transmit the internally generated 2 1 PRBS pattern as outlined in Example Applications in section 6 1 2 PRBS Pattern Synch Test
28. b 09 2006 6 2 TRANSMITTING A USER DESIRED 32 BIT PATTERN A 32 bit User Pattern can be quickly generated at the FPGA to be transmitted thru the transmit byte wide parallel interface of XRT91L30 Figure 6 18 XRT91L30 Serial Remote Loopback FPGA 32 bit User Pattern Normal Mode Operation 32 bit Buffer 32 bit User Pattern OxAA Guiput Drivers TX Serial Output OxAA OxAA LVPECL Input Drivers RX Serial Input Configuring the XRT91L30 for 32 bit User Pattern Transmission Step 1 With the Exar USB drivers and the XRT91L30 GUI installed connect the USB cable to both the PC and the XRT91L30 Evaluation Board Verify power supply on the board by checking Power LED Step 2 Connect the optical cable from the test equipment optical interface to the SFP optical module on the Evaluation Board This cable is included in the XRT91L30 evaluation kit Step 3 Launch the XRT91L30 application GUI See section 4 1 Starting the Evaluation Software Step 4 Once the application GUI Start Test is running select the desired Data Rate signal STS 3 STM 1 at 155 52 Mbps or STS 12 STM 4 at 622 08 Mbps Figure 6 19 Select Data Rate XRT91L30 Evaluation System X XRTI1L30 Control Local Loopbacks C um tt Data Rate Analog Loopback EI e 155 52NVbps 622 08 Mbps Digital Loopback CMU VA 77 Select STS 3 or STS 12 Data Rate j UserPattem 00000000 Tx P Clock Direction ee
29. cking on OK will close the main window Figure 4 2 Main GUI Window XRT91L30 Evaluation System ARTSTL3U Control Local Loopbacks E TxF E tt Data Rate Analog Loopback Ho s 155 52 Mbps Mbps Digital Loopback CMU Fregency select Remate Serial LB a 100000000 77 76 MHz 18 44 MHz System Control TxP Clock Direction TURIS s Input Output Transmitted 100000000 User Pattern Transmit Timing a Pattern Sync Hist Local Timing Reset Pat syne Hist Start Poll LOR Reference Clock Select CEP Madule Cantal ForceelOS CDR Mode Bypassed Master Reset Ww Rx LOS Force Reframe LOS Det Disable ix Faul In Progress EXAR Experience Our Connectivity EVM 91 L30 SONET STS 12 STS 3 or SDH STM A STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 4 3 XRT91L30 GUI CONTROL DISPLAY ASSOCIATION Below is a table outlining the GUI software control display association to the XRT91L30 hardware control pins Table 1 0 XRT91L30 GUI Display Cross Reference Main GUI Window XRT91L30 Control Display Hardware pin Hardware Pin description Data Rate Data Rate Selecti 1555 59 515 12 815 3 2 29 TE PETER 15552Mbps 622 08 Mbps CMU Freqency Select Clock Multiplier Unit 77 76 MHz C 19 44 MHz 3 CMUFREQSEL Reference Frequency Select Tx P Clock Direction Transmit Parallel Clock Input C Output 48 PIO_CTRL Input Output Select Transm
30. controllers Sound video and game controllers Storage device lt Back Experience Our Connectivity E V 9 1 L 3 0 SONET STS 12 STS 3 SDH STM 4 STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 Figure 3 4 Select Have Disk Add New Hardware Wizard Select the manufacturer and model of your hardware device If you havea v disk that contains the updated driver click Have Disk To install the updated driver click Finish Manufacturers Models Boca Research Boca Complete Communicator Moce Sierra Semiconductor YI 5 Have Disk lt Back Cancel Figure 3 5 Find the location of the drivers located on the CD File name Folders Jexarush inf Es drivers exar_usb_ drivers Cancel exarusb inf ey e drivers 25 exar ush drivers The following window will appear confirming the location of the driver Select OK Figure 3 6 Install From Disk Install From Disk Insert the manufacturer s installation disk inta a the dive selected and then click Cancel Copy manufacturer s files fram E driversvesar usb drivers gt Browse 10 EXAR Experience Our Connectivity EVM 91 L30 SONET STS 12 STS 3 or SDH STM 4 STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 The driver will appear in the Have Disk wind
31. ds for proper connection as well Step 12 Record the XRT91L30 current consumption and the voltage at the L4 pad lead with reference to board Ground the user will need this information to calculate the total power consumption Note that FPGA Remote Loopback exercises all the logical blocks and analog drivers in the XRT91L30 thereby providing the worst case condition for power consumption measurement 45
32. e Exar supplied standard USB cable to the PC 3 Connect PC USB cable to the USB Port on the board Verify power supply on the board by checking Power LED Connect optical cable to SFP module Launch XRT91L30 GUI Application Configure the XRT91L30 for proper data rate and operation EXAR Experience Our Connectivity EVM 91 L30 SONET STS 12 STS 3 or SDH STM A STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 6 0 EXAMPLE APPLICATIONS The following example applications are provided in this manual 6 1 Loopback Operations 6 1 1 Serial Remote Loopback 6 1 2 PRBS Pattern Sync Test using Analog Local Loopback 6 2 Transmitting a user desired 32 bit Pattern 6 3 Master Reset 6 4 SFP Module Control 6 1 LOOPBACK OPERATIONS Loopback operations generally fall under 2 different categories and are referenced with respect to the device Remote loopback and Local Loopback are both available on the XRT91L30 device Remote Loopback indicates that remote equipment test equipment signal is routed back to the equipment Hence all types of remote loopback routes received signal back to the transmit side Local loopback indicates that link layer or terminal equipment signal hence local signal is routed back to the link layer or terminal equipment This means locally transmitted signal is routed back to the receiver 6 1 1 Serial Remote Loopback To quickly diagnose line integrity back to remote or test equipment a serial rem
33. e Loopback 34 EXAR Experience Our Connectivity 91 130 SONET STS 12 STS 3 SDH STM 4 STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 Step 2 Select Looptiming Mode for the XRT91L30 transmit timing Figure 7 1 Select Looptiming Transmit Timing Local Timing Timing Select Loop Timing Step 3 Select the proper SONET SDH data rate source and payload pattern on test equipment and verify recovered data integrity and pattern sync on test equipment Step 4 Verify that the optical signal strength is valid for jitter measurements Adjust optical signal strength by adding removing optical attenuators or slightly adjusting optical coupler connector until desired optical signal strength is achieved for valid jitter measurements Figure 7 2 Optical Signal Strength Test Equipment RESULTS OPTICAL POWER OF RANGE BER JITTER 40 30 2 10 OdBn be re OPTICAL PWR 15 0 dBm ELAPSED TIME 00d Olh 55 265 Step 5 Configure the test equipment for Jitter Tolerance measurements and select the appropriate Jitter Tolerance Mask Standard for SONET STS 12 STS 3 or SDH STM 4 STM 1 Figure 7 3 STS 3 GR 253 Jitter Tolerance Mask Test Equipment GR 253 Mask 155Mb s c c b e Li amp Zi ur om gt r Amplitude UI 1 i j j Freq Hz 0 1 1 10 100 1K 1 1 1M Step 6 Begin Jitter Tolerance M
34. easurements 35 EXAR Experience Our Connectivity EVM 91 L30 SONET STS 12 STS 3 or SDH STM A STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 7 2 HOW TO MEASURE OPTICAL JITTER TRANSFER OF THE XRT91L30 To successfully perform this test the user needs to configure the XRT91L30 into e Remote Serial Loopback Looptiming Step 1 Configure the XRT91L30 for Serial Remote Loopback as outlined in the Example Applications in section 6 1 1 Serial Remote Loopback Step 2 Select Looptiming Mode for the XRT91L30 transmit timing Figure 7 4 Select Looptiming Transmit Timing Local Timing Loop Timing Select Loop Timing Step 3 Select the proper SONET SDH data rate source and payload pattern on test equipment and verify recovered data integrity and pattern sync on test equipment Step 4 Configure the test equipment for Jitter Transfer measurements and select the appropriate Jitter Transfer Mask Standard for SONET STS 12 STS 3 or SDH STM 4 STM 1 Figure 7 5 STS 3 GR 253 Jitter Transfer Mask Test Equipment GR 253 Mask 155 5 dB Gain E Gy 60 Freq Hz 10 100 1K 10K 100K 1M Step 5 Most test equipment will require an initial jitter transfer calibration before proceeding with jitter transfer measurements Therefore detach the Evaluation Board connected optical cable from the test equipment and replace a with an optical loopback cable for the calibration process See Figure
35. ed it can be found through the Start Menu gt Exar gt XRT91L30 Evaluation Once selected it will open up the application To begin the GUI select Test from the menu bar and then Start Test The GUI will automatically download the FPGA before it starts To download a different FPGA than the default offering select Test gt Download FPGA Figure 4 1 Start Test 91 30 ox File Test Help start Test LISB Read Mrite Download FPGA EXAR Experience Our Connectivity EVM 91 L30 SONET STS 12 STS 3 or SDH STM A STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 4 2 USING THE EVALUATION SOFTWARE It is possible to achieve full device functionality through the GUI Selecting a check box will enable disable a certain feature Upon each selection the control pin assertion occurs immediately and is displayed in the main GUI window In addition FPGA features are also accessed and can be enabled or disabled through the main GUI window Status indicators will begin polling upon selecting the Start Poll button and will continue to poll every 250 milliseconds until it is stopped Upon polling the value of the transmitted pattern will be displayed in the transmit pattern section To send a desired 32 bit sequential pattern enter the relevant 4 byte value in the data box and select Write Pattern However the Tx Pattern On needs to be enabled to begin transmission of selected pattern Cli
36. ern Sync Hist LocalTiming lI Timing Reset Pat Sync Hist Start Poll CDR Reference Clock SED Module Control CMU y TT Loop Timing L Disable Force LOS CDR Mode Bypassed SFP Detect Master Reset RxLOS Force Reframe LOS Det Disable Tx Fault In Progress Step 10 Enable the FPGA Remote Loopback by checking the on the FPGA Remote Loopback box Figure 8 6 Enable FPGA Remote Loopback XRT91L30 Evaluation System Eq RT91L30 Control Local Loopbacks Tx Pattern Data Pate Analog Loopback e 155 52 Mbps 622 08 Mbps Digital Loopback CMU Fregency Select Remote Serial LB ear EB 00000000 e 77 76 MHz 19 44 MHz System Control Tx P Clock Direction fea AE Pattern Input Output N Transmitted 00000000 yattern Sync Enable FPGA Remote Loopback Local Timing Reset Pat Sync Hist Start Poll CDR Reference Clock Select Transmit Timing SFP Module Control OK Qu CDRAUX Tx Disable ForceLOS Bypassed SFP Detect Master Reset PxLOS Force Reframe LOS Det Disable Tx Fault Qin Step 11 Check test equipment for valid pattern synchronization Note If the test equipment receiver reports a Loss of Signal it is likely that the optical cable is not properly oriented Switch the transmit and receive cables on the test equipment and verify data integrity Check the L4 lea
37. he XRT91L30 All access to XRT91L30 control pins are defined through the use of the Exar supplied XRT91L30 GUI 2 2 XRT91L30 CLOCK REFERENCE The 77 76 MHz oscillator clock is internally divided by four within the FPGA to generate19 44 MHz clock The appropriate reference clock frequency is then selected based upon the polarity of CMUFREQSEL setting on the GUI RefCIk TTL FPGA output is then applied to the XRT91L30 TTLREFCLK input that feeds the Clock Multiplier Unit CMU Phase Locked Loop PLL A 77 76 MHz clock is also applied to the CDRAUXREFCLK input CDRREFSEL setting will then determine the source of the Clock and Data Recovery CDR reference clock Differential reference clock input is not used on the evaluation board However it is possible to apply differential reference clock by installing some of the optional components See evaluation board schematic for reference 2 3 FPGA FEATURES STS 12 STM 4 or STS 3 STM 1 optical signal is received by the optical module and converted to VPECL electrical signal before being interfaced to the XRT91L30 The XRT91L30 then recovers the clock and data and converts the serial data to SONET SDH byte wide parallel data and outputs the recovered divide by eight clock that is synchronous to the parallel data The FPGA performs the task of the terminal end unit and allows a system level FPGA Remote Loopback function where the received byte wide data coming from the XRT91L30 is looped back within t
38. he FPGA and sent to the byte wide transmit input interface of the XRT91L30 Note This is system level loopback is significantly different from the XRT91L30 device s diagnostic serial Remote Loopback Serial Remote Loopback occurs internally within the XRT91L30 and received serial data is looped back to the transmitter before serial deserializer SERDES conversion Serial Remote Loopback is meant to be used for diagnostics In addition the FPGA also contains a 2 1 PRBS pattern generator and PRBS data integrity checker A status LED indicator called Pattern Sync indicates when the PRBS pattern is currently locked Another status LED indicator called Pattern Sync History indicates if there was a momentary loss of PRBS sequence It is also possible to transmit a fixed pattern rather than PRBS by selecting the 32 bit User Pattern and entering the fixed pattern on the 32 bit User Pattern window However error checking is not performed when fixed pattern is being transmitted EXAR Experience Our Connectivity EVM 91 L30 SONET STS 12 STS 3 or SDH STM A STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 2 4 EVALUATION BOARD LIMITATIONS 1 ALOOP and DLOOP not supported when operating at STS 12 STM 4 rate using 19 44 MHz reference clock 2 Transmit Parallel Clock must be configured for Output when transmitting 2 1 PRBS pattern or 32 bit User Pattern 3 Looptiming must be implemented when using FPGA Remote Loopback
39. in lieu of PRBS pattern when Tx Pattern is enabled However pattern error checking is not available for fixed patterns The user will not be able to rely on Pattern Sync and Pattern Sync Hist for error checking Step 8 Check Pattern Sync status indicator by clicking on Start Poll button The In Progress indicator will start flashing green when polling has begun Figure 6 14 Start Polling XRT91L30 Evaluation System x XRT31L30 Control Data Rate 155 52 Mbps CMU Fregency Select 7776 MHz Tx P Clock Direction Input e Output Transmit Timing Local Timing CDR Reference Clock Select Force LOS Force Reframe 622 08 Mbps 19 44 MHz Loop Timing CMU CDR AUX CDR Mode Bypassed LOS Det Disable Local Loopbacks Analog Loopback Digital Loopback Remote Serial LB system Control FPGA Remote Loopback Pattern Sync Pattern Sync Hist Reset Pat Sync Hist SFP Module Control Tx Disable QJ SFP Detect W RxLOS Tx Fault lv Tx Pattern On 2 31 1 PRBS Pattern gt User Pattern 00000000 Write Pattern Transmitted User Pattern Start Poll In Progress 00000000 N Master Reset 25 Experience Our Connectivity 91 130 SONET STS 12 STS 3 SDH STM 4 STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 Valid PRBS pattern synchron
40. it Timing LOOPTIMING Looptiming Select Local Timing Loop Timing CDR Reference Clock Select Clock and Data Recovery CMU CDRAUX 60 CDRREFSEL Reference Frequency Select Force LOS Signal Detect Input 33 LOSEXT 1 Normal Mode Force LOS Data Mute Force Reframe 11 NW _ Normal Mode Force Reframe Clock and Data Recovery Unit Disable and Bypass i CI Internal CDR Enabled Internal CDR Bypassed Internal LOS Detect Disable 7 1 Monitor and Mute upon LOS LOS detect disabled Analog Local Loopback Enable 64 LI Normal Mode ALOOP Enabled Digital Local Loopback Enable CDR Mode LOS Det Disable Analog Loopback Digital Loopback 62 LI Normal Mode DLOOP Enabled Bemote Serial LB 63 serial Remote Loopback Enable LI Normal Mode RLOOPS Enabled EXAR Experience Our Connectivity EVM 91 L30 SONET STS 12 STS 3 or SDH STM A STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 In addition the table below also outlines the GUI control display association to the FPGA features and functions Main GUI WINGOW FPGA Function Functional Description Control Display RXDO 7 0 RXPCLKO pins and XRT91L30 Table 1 1 FPGA Functions GUI Display Cross Reference FPGA receives byte wide parallel data clock from FEGA Remote FPGA Remote loops data back to the Loopback Loopback TXDI 7 0 TXPCLK_IO pins of the 1 Normal Mode Thru Mode F
41. ivers To install the drivers follow the prompts and manually select the exarusb inf file from the included driver zip file 3 2 INSTALLING THE XRT91L30 EVALUATION GUI To install the XRT91L30 GUI double click on the installation file enclosed in the Exar CD as part of the evaluation package This will place the relevant GUI files in an Exar created folder along with the necessary FPGA file Since the XRT91L30 is a pure hardware control device it is necessary to drive the GUI through use of an FPGA file This is automatically done when Test gt Start Test is selected Figure 3 10 Start Test XRT91L30 Test Application 4 File Test Help start Test LISB Read Mrite Download FPGA EXAR Experience Our Connectivity EVM 91 L30 SONET STS 12 STS 3 or SDH STM A STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 4 0 XRT91L30 EVALUATION SOFTWARE This section details the operation of the software GUI provided as part of the evaluation process It includes the following topics 4 1 Starting the Evaluation Software 4 2 Using the Evaluation Software 4 3 XRT91L30 GUI Control Display Association 4 1 STARTING THE EVALUATION SOFTWARE The evaluation software allows the user to do the following Configure the XRT91L30 for proper operation Poll FPGA current PRBS Pattern Sync History status Download a new FPGA code Enable Disable XRT91L30 features with the click of a button Once the XRT91L30 GUI is install
42. ization is indicated by a green LED PRBS pattern reception failure is indicated by a red LED Figure 6 15 Check Pattern Sync XRT91L30 Evaluation System X RT91L30 Control Local Loopbacks F E v tt Data Rate Analog Loopback aca d Qus Digital Loopback 2 31 1 PRBS Pattern v Remote Serial LB User Pattern 00000000 e 77 76 MHz 19 44 MHz System Control Tx P Clock Direction a Missed C Input Output Transmitted 00000000 User Pattern Transmit Timing sync Hist Local Timing Loop Timing Check Pattern Sync dm CDR Reference Clock Select SEP Module Control CMU CDRAUX Tx Disable E ForceLOS CDR Mode Bypassed gt Master Reset Force Reframe LOS Det Disable Tx Fault in Progress The Pattern Sync Hist indicator flags momentary errors in PRBS transmission and reception Momentary and current error occurrence is indicated by a yellow LED Figure 6 16 Check Pattern Loss XRT91L30 Evaluation System X RT91L30 Control Local Loopbacks 7 s v Data Rate Analog Loopback emen s 155 52Mbps 622 08 Mbps Digital Loopback 2 31 1 PRBS Pattem v CMU Select Remote Serial LB User Pattem 00000000 e 77 76 MHz 19 44 MHz System Control TxP Clock Direction FPGA Remote Write Pattern Loopback Input Output Pattern Sync 100000000 Transmit Timin Pattern Sync Hist 9
43. lock Select fe CMU CDRAUX Force LOS CDR Mode Bypassed LOS Det Disable Force Reframe Local Loopbacks Tx Pattern On Vigital Loopback Enable Analog Local Loopback 00000000 _ 00000000 System Control j Write Pattern E FPGA Remote Transmitted Loopback Pattern Sync User Pattern Pattern Sync Hist Reset Pat Sync Hist Start Poll Analog Loopback 00000000 SFP Module Control Tx Disable SFP Detect Master Reset RxLOS QJ Tx Fault In Progress Step 6 To enable the transmission of pattern signal from the FPGA check the Tx Pattern On box Figure 6 12 Enable Transmit Pattern On e XRT91L30 Evaluation System XRT31L30 Control Data Rate e 155 52 Mbps 622 08 Mbps CMU Fregency Select e 77 75 MHz 19 44 MHz Tx P Clock Direction Input e Output Transmit Timing LocalTiming Loop Timing CDR Reference Clock Select e CMU CDRAUX 08 CDR Mode Bypassed Force Reframe LOS Det Disable Local Loopbacks Analog Loopback Digital Loopback Tx Pattern On Enable Transmit Patter Remote Serial LB User Patten 00000000 system Control FPGA Remote Loopback Write Pattern i Transmitted 00000000 User Pattern Ww Pattern Sync Hist Reset Pat Sync Hist Start Poll SFP Module Control Tx Disable SFP Detect Master Reset W Rx Los Tx Fault In Progress
44. luation board it is necessary to install the Exar USB drivers Upon plugging the evaluation board into the computer the system should recognize a new device and prompt for a driver A window should appear similar to the one below Figure 3 1 Add New Hardware This searches for new divers for EXAR Eval Board 320 USB A device diver is software program that makes Cancel EXAR Experience Our Connectivity EVM 91 L30 SONET STS 12 STS 3 or SDH STM 4 STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 The drivers are included in the Exar CD in the folder labeled Drivers To install from the CD select Display a lists of all the drivers in a specific location so you can select the driver you want Figure 3 2 Select Display Available Drivers and then Next Add New Hardware Wizard What do you want Windows to do for the best diver for your device Recommended lt Display a tof al the divers ina Figure 3 3 Select Other detected devices and then Next Add New Hardware Wizard Select the type of device from the list below then click Next Network adapters Other detected devices Other devices Palm 05 Handheld Devices socket Ports COM amp LPT Printer SBP2 SES
45. m Syne User Pattern Transmit Timing W Pattern Sync Hist Local Timing Reset Sync Hist Start Poll CDR Reference Clock Select SFP Module Control fe CMU CDRAUX Tx Disable ForceLOS CDR Mode Bypassed W SFP Detect Master Reset Px LOS Force Reframe LOS Det Disable Tx Fault In Progress Step 5 Select the desired Data Rate signal STS S STM 1 at 155 52 Mbps or STS 12 STM 4 at 622 08 Mbps Figure 6 3 Select Data Rate XRT91L30 Evaluation System x XRT31L30 Control Local Loopbacks C tt Data Rate Analog Loopback Mi op e 1555avbps 622 08 Mbps Digital Loopback i2BiUserPatem CMU Free Select 575 3 STS 12 Data Rate 9 is LB UserPatem 00000000 e 77 76 ntrol TxP Clock Direction ae Pattern Input C Output Transmitted 00000000 Svne User Pattern Transmit Timing w Pattern Sync Hist Local Timing s Reset Pat Sync Hist start CDR Reference Clock Select SFP Madule Control CDRAUX Tx Disable 08 Mode Bypassed v SFP Detect Master Reset Px LOS Force Reframe LOS Det Disable Tx Fault In Progress EXAR Experience Our Connectivity SONET STS 12 STS 3 or SDH STM 4 STM 1 XRT91L30 Optical Evaluation Board User Manual EVM 91L30 Step 6 Select Looptiming mode for the XRT91L30 transmit timing Step 7 Enable the Remote Serial Loopback
46. nc Hist Reset Pat Sync Hist Start Pall SFP M odule Control Tx Disable Q9 SFP Detect Master Reset PxLOS Tx Fault In Progress 30 Experience Our Connectivity 91 130 SONET STS 12 STS 3 SDH STM 4 STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 Step 9 Enter the value OXAAAAAAAA to transmit 1010 0x55555555 to transmit 0101 pattern Figure 6 24 Enter 32 bit User Pattern XRT91L30 Evaluation System Eq XRT31L30 Control Local Loopbacks gt Data Rate Analog Loopback dis d e 155 52 Mbps 622 08 Mbps Digital Loopback 32 Bit UserPatten E ede Aem Remote Serial LB User Pattern 55555555 e 77 76 MHz 19 44 MHz System Control N T FPGA Remote Write Pattern Tx P Clock Direction Loopback Input Output Transmitted P Q Patem Syne 7 5 vv User Pattern Transmit Timing w Pattern Sync Hist Local Timing cc Reset Pat Sync Hist start Poll CDR Reference Clock Select SEP Module Control ForceLOS CDR Bypassed S T Master Reset Force Reframe LOS Det Disable Tx Fault In Progress Step 10 Click on Write Pattern to load the user pattern into the FPGA buffer Figure 6 25 Click Write Pattern XRT91L30 Evaluation System X XRT31L30 Control Local Loopbacks F Data Rate Analog Loopback ad te
47. ode for the XRT91L30 transmit timing Figure 6 10 Select Local Timing XRT91L30 Evaluation System XRT31L30 Control Data Rate 155 52 Mbps 622 08 Mbps CMU Fregency Select e 77 76 MHz 18 44 MHz Tx P Clock Direction Input Output Transmit Timing LocalTiming Loop Timing CD K eference Clock Select Q Select Local Timing Force LOS CDR Mode Bypassed Force Reframe LOS Det Disable Local Loopbacks Analog Loopback Digital Loopback Tx Pattern On 00000000 Remote Serial LB System Control FPGA Remote Loopback Pattern sync Pattern Sync Hist User Pattern Vvrite Pattern i Transmitted User Pattern 00000000 Reset Sync Hist Start Poll SFP Mod trol Tx Disable SFP Detect Master Reset Rx LOS QJ Tx Fault In Progress 23 Experience Our Connectivity EVM 91L30 SONET STS 12 STS 3 or SDH STM 4 STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 Step 5 Enable the Analog Local Loopback by checking the Analog Loopback box in Local Loopbacks section Figure 6 11 Enable Analog Local Loopback a XRT91L30 Evaluation System XRT31L30 Control Data Rate 155 52 Mbps 622 08 Mbps CMU Fregency Select e 77 75 MHz 19 44 MHz Tx P Clock Direction Input e Output Transmit Timing LocalTiming Loop Timing CDR Reference C
48. ote loopback can be invoked Figure 6 1 XRT91L30 Serial Remote Loopback Serial Remote Loopback FIFO PISO Re Timer TX Serial Output Output Drivers LVPECL RX Parallel Output mH SIPO CDR E Input Drivers 5 RX Serial Input Configuring for Remote Serial Loopback Operation Step 1 With the Exar USB drivers and the XRT91L30 GUI installed connect the USB cable to both the PC and the XRT91L30 Evaluation Board Verify power supply on the board by checking Power LED Step 2 Connect the optical cable from the test equipment optical interface to the SFP optical module on the Evaluation Board This cable is included in the XRT91L30 evaluation kit Step 3 Launch the XRT91L30 application GUI See section 4 1 Starting the Evaluation Software Experience Our Connectivity 91 130 SONET STS 12 STS 3 SDH STM 4 STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 Step 4 Once the application GUI Start Test is running you should see a similar window below with the XRT91L30 default settings Figure 6 2 Main GUI Window XRT91L30 Evaluation System Eq XRT31L30 Control Local Loopbacks tt Data Rate Analog Loopback eigen te 155 52 Mbps 622 08 Mbps Digital Loopback CMU Freqency Select Remote Serial User Pattern 00000000 e 77 76 MHz 19 44 MHz System Control Tx P Clock Direction E ae Write Pattern Input Output Transmitted 00000000 9 Ponra
49. ow and should be selected Press Next to install the driver Figure 3 7 Driver Select Select the manufacturer and model of your hardware device If vou have a disk that contains the updated driver click Have Disk To install the updated driver click Finish Models ESAR Eval Board w Silabs 0 20 USB 5 4 2005 Have Disk Now that the system has found the appropriate drivers select Next to install the Exar driver Figure 3 8 Install Driver Windows driver file search for the device Eval Board w Silabs 320 USB win dows snow ready to install the selected driver for this device Click Back to select a different driver or click Next to continue Location af driver EADRIVERSNEXAR LIISEXARUSE INF Cancel 11 Connectivity V 9 1 L 3 SONET STS 12 STS 3 or SDH STM 4 STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 The driver is now installed in the system and is ready to run the Exar Evaluation GUI Figure 3 9 Installation Successful Add New Hardware Wizard Eval Board w Silabs C8051F320 USB windows has finished installing the software you selected that your new hardware device requires Note Included in the driver zip package are two files exarusb inf and exarusb sys Upon first connecting the board to your computer you may be prompted to install the Exar USB dr
50. owing e Anetwork test equipment capable of sourcing STS 12 STM 4 or STS 3 STM 1 Acurrent meter capable of measuring current accurately in milliamps Avolt meter capable of measuring voltage accurately in hundredths he XRT91L30 Evaluation Board schematic for reference In addition the user may configure the XRT91L30 to do the following but is not necessary FPGA Remote Loopback Looptiming Mode Step 1 Review the XRT91L30 Evaluation Board schematic and locate L4 This ferrite bead supplies the entire power to the XRT91L30 silicon Note that VCCDUT from the XRT91L30 power supply pins lead to this ferrite bead Step 2 Locate and remove L4 ferrite bead on the XRT91L30 Evaluation Board Store L4 ferrite bead in a secure container for reinstallation at a later time Step 3 Attach and secure leads to L4 soldering pads It should be long enough to prevent shorting the board These leads should also be secured and prevented from physical stress when the current meter is attached to the leads Check for soldering for shorts and remove errant solder on the board before proceeding The board should be cleaned with a solder flux remover at the soldering site to prevent flux contamination and corrosion Step 4 Connect the USB cable to both the PC and the XRT91L30 Evaluation Board Verify power supply on the board by checking Power LED Attach the current meter lead to the L4 leads and verify power to the XRT91L30 by monitoring curren
51. re 8 4 Select Data Rate XRT91L30 Evaluation System x XRT31L30 Control Local Loopbacks C tt Data Rate Analog Loopback Mi op e 1555avbps 622 08 Mbps Digital Loopback i2BiUserPatem CMU Free Select 575 3 STS 12 Data Rate 9 is LB UserPatem 00000000 e 77 76 ntrol TxP Clock Direction ae Pattern Input C Output Transmitted 00000000 Svne User Pattern Transmit Timing w Pattern Sync Hist Local Timing s Reset Pat Sync Hist start CDR Reference Clock Select SFP Madule Control CDRAUX Tx Disable 08 Mode Bypassed v SFP Detect Master Reset Px LOS Force Reframe LOS Det Disable Tx Fault In Progress 44 EXAR Experience Our Connectivity 91 130 SONET STS 12 STS 3 SDH STM 4 STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 Step 9 Select Looptiming mode for the XRT91L30 transmit timing Figure 8 5 Select Looptiming XRT91L30 Evaluation System X RT91L30 Control Local Loopbacks 5 tt Data Rate Analog Loopback NR 155 52 Mbps 622 08 Mbps Digital Loopback 32 BitUserPattem x CMU Fregency Select qency _ Remote Serial User Pattern 00000000 e 77 76 MHz 18 44 MHz System Control Tx P Clock Direction Am d manm Input Output Transmitted 00000000 2 Pattern Sync User Pattern Transmit Timing w Patt
52. system Control Tx P Clock Direction E Write Pattern Input Output Transmitted 00000000 Q Pattern Sync lisar Pitam Transmit Timing 2 Pattern Sync Hist Local Timing Loop Timing Pat Sync Hist Press to Stan CDR Reference Clock Select ag IGNORE Pattern Sync Errors CMU CDR AUX TxDisable LE ForceLOS Bypassed SFP Detect Master Reset RN OS Force Reframe LOS Det Disable in Proaress IGNORE SFP Module Errors Step 5 Securely and gently attach the probe to TXOP and TXON LVPECL high speed differential output pins Be extremely careful not to subject the pins to physical stress as it may be damaged Attach the differential probe to the oscilloscope Step 6 Configure and adjust the oscilloscope settings to superimpose the XRT91L30 LVPECL high speed differential outputs over time Your eye diagram should look to something similar below Figure 8 2 XRT91L30 Eye Diagram OC 12 Ch1 200 M 1 25ns 20 0655 IT 2 35 8ns Chl y 4 Ch1 200 M 250 20 0GS s IT 1 0psipt 5 B ns Chl 16 0mV 42 EXAR Experience Our Connectivity EVM 91 L30 SONET STS 12 STS 3 or SDH STM A STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 8 2 XRT91L30 CURRENT CONSUMPTION MEASUREMENT To successfully measure the current consumption on the XRT91L30 the user must have the foll
53. t consumption on the current meter Step 5 Connect the optical cable from the test equipment optical interface to the SFP optical module on the Evaluation Board This cable is included in the XRT91L30 evaluation kit Step 6 Launch the XRT91L30 application GUI See section 4 1 Starting the Evaluation Software 43 Experience Our Connectivity 91 130 SONET STS 12 STS 3 SDH STM 4 STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 Step 7 Once the application GUI Start Test is running you should see a similar window below with the XRT91L30 default settings Figure 8 3 Main GUI Window XRT91L30 Evaluation System Eq XRT31L30 Control Local Loopbacks tt Data Rate Analog Loopback eigen te 155 52 Mbps 622 08 Mbps Digital Loopback CMU Freqency Select Remote Serial User Pattern 00000000 e 77 76 MHz 19 44 MHz System Control Tx P Clock Direction E ae Write Pattern Input Output Transmitted 00000000 9 Ponram Syne User Pattern Transmit Timing W Pattern Sync Hist Local Timing Reset Sync Hist Start Poll CDR Reference Clock Select SFP Module Control fe CMU CDRAUX Tx Disable ForceLOS CDR Mode Bypassed W SFP Detect Master Reset Px LOS Force Reframe LOS Det Disable Tx Fault In Progress Step 8 Select the desired Data Rate signal STS S STM 1 at 155 52 Mbps or STS 12 STM 4 at 622 08 Mbps Figu
54. ut m Serial Output lt TXDI 7 0 8 gt be c TXPCLK IO ig 5 REFCLKP N NE z c TTLREFCLK CDRAUXREFCLK SIPO x K RX DOJ7 0 Serial Input CDR lt Parallel 8 x RXIP N XRXCLKIP N RXPCLKO Control Block Clock Control Loop Filters oa T WN A lt lt O 1 0 OVERVIEW 1 CAP2N Reset STS 12 STS 3 LOOPTIME RLOOPS DLOOP ALOOP OOF FRAMEPULSE DLOSDIS LOSEXT CMUREF SEL CDRREFSEL CDRDIS PIO CTRL This is evaluation board manual is intended to help the user become familiarized to operate the XRT91L30 Demo board and run traffic with minimum effort Requirements 1 XRT91L30 Evaluation Board 2 OC 12 OC 3 or STM 4 STM 1 generator analyzer test equipment with optical interface 3 Windows PC with USB port amp USB cable for power supply and GUI interface 4 XHRT91L30 supplied USB drivers and GUI to be installed on the PC using Win98 2000 or XP 5 XRI91L30 data sheet rev P1 0 8 or newer Experience Our Connectivity EVM 91 L30 SONET STS 12 STS 3 or SDH STM 4 STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 2 0 EVALUATION BOARD ARCHITECTURE XRT91L30 Evaluation board provides a simple and efficient way to quickly evaluate functionality and performance of the XRT91L30 SONET SDH STS 12 STM 4 or STS S STM 1 Transceiver Figure 2 0 XRT91L30 Optical Evaluation Board revision 0 SFP Optical U12 UsB
55. wf Pattern Sync Hist Reset Pat Sync Hist Start Poll SFP odule Control Tx Disable SFP Detect Master Reset Rx LOS Q9 Tx Fault In Progress Step 8 Check test equipment for valid pattern synchronization Note If the test equipment receiver reports a Loss of Signal it is likely that the optical cable is not properly oriented Switch the transmit and receive cables on the test equipment and verify data integrity 20 Feb 09 2006 EXAR Experience Our Connectivity 91 130 SONET STS 12 STS 3 SDH STM 4 STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 Step 9 OPTIONAL To disable Remote Serial Loopback uncheck the Remote Serial LB box Figure 6 6 Disable Serial Remote Loopback XRT91L30 Evaluation System x RT91L30 Control Local Loopbacks 5 tt Data Rate Analog Loopback RD 155 52 Mbps 622 08 Mbps Digital Loopback 32 BitUserPattem x CMU Freqency Select Remote Serial User Pattern 00000000 e 77 75 MHz 19 44 MHz Stem Control TxP Clock Direction Uncheck to Disable Remote Serial Loopback Input utput ransmited 00000000 User Pattern Transmit Timing w Pattern Sync Hist LocalTiming Loop Timing HEBES Start Poll CDR Reference Clock Select SFE Module Canto e CMU CDRAUX Tx Disable ForceLOS Bypassed E Master Reset Force Reframe LOS Det Disable Tx Fault In
56. x Disable Start Polling ForeeLOS CDR Mode Bypassed v SFP Detect Master Reset PxLOS Force Reframe LOS Det Disable Tx Fault Progress Step 12 Verify that the desired pattern is displayed on the Transmitted User Pattern window This is the pattern currently transmitted by the XRT91L30 Figure 6 27 Verify Transmitted Pattern jw TxPatter On 3z Bit User Pattern gt Pattern Transmitted User Pattern 55555555 Verify Transmit User Pattern 32 EXAR Experience Our Connectivity EVM 91 L30 SONET STS 12 STS 3 or SDH STM A STM 1 XRT91L30 Optical Evaluation Board User Manual Feb 09 2006 6 3 MASTER RESET Whenever necessary the XRT91L30 can be reset To invoke this click on the Master Reset button This will automatically toggle the hardware reset pin on the XRT91L30 Figure 6 28 Master Reset Falling Press to Stop Master Reset In Prd Click to Reset XRT91L30 6 4 SFP MODULE CONTROL This section is mainly a register status box that includes the ability to disable the SFP module optical transmitter Table 2 0 SFP Module Control Box Function Description Cd Tx Disable Checking this box disables the optical transmitter SFP Detect LED detects the absence of the SFP optical module RxLOS Hed LED detects Loss of Signal Tx Fault Hed LED detects failure in optical transmission Figure 6 29 SF

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