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SIS3820 VME Scaler User Manual

1. Bit Function w r Default 31 1 Shot IRQ UPDATE Status IRQ source 7 reserved 0 30 unused Status IRQ source 6 reserved 0 29 unused Status IRQ source 5 reserved 0 28 unused Status IRQ source 4 FIFO almost full 0 27 unused Status IRQ source 3 overflow 0 26 unused Status IRQ source 2 acquisition completed 0 25 unused Status IRQ source 1 FIFO threshold 0 24 unused Status IRQ source 0 LNE clock shadow 0 23 Clear IRQ source 7 Status flag source 7 0 22 Clear IRQ source 6 Status flag source 6 0 21 Clear IRQ source 5 Status flag source 5 0 20 Clear IRQ source 4 Status flag source 4 0 19 Clear IRQ source 3 Status flag source 3 0 18 Clear IRQ source 2 Status flag source 2 0 17 Clear IRQ source 1 Status flag source 1 0 16 Clear IRQ source 0 Status flag source 0 0 15 Disable IRQ source 7 Status VME IRQ 0 14 Disable IRQ source 6 Status internal IRQ 0 13 Disable IRQ source 5 0 0 12 Disable IRQ source 4 0 0 11 Disable IRQ source 3 0 0 10 Disable IRQ source 2 0 0 9 Disable IRQ source 1 0 0 8 Disable IRQ source 0 0 0 7 Enable IRQ source 7 Status enable source 7 read as 1 if enabled O if disabled 0 6 Enable IRQ source 6 Status enable source 6 read as 1 if enabled 0 if disabled 5 Enable IRQ source 5 Status enable source 5 read as 1 if enabled O if disabled 0 4 Enable IRQ source 4 Status enable source 4 read as 1 if enabled 0 if disabled 0 3 Enable IRQ source 3 Status enable source 3 read as 1 if enabled
2. Preset channel select 17 32 compare S d Y Preset enable and hit bits 16 17 Scaler channel 17 Scaler channel 16 AND Scaler channel 15 selected scaler channel preset value group 1 compare Y Preset enable and hit bits 0 1 Preset channel select 1 16 Scaler channel 1 Page 40 of 72 SIS Documentation SIS3820 SIS GmbH t VME Scaler VME 7 19 Inhibit count disable register 0x200 define SIS3820_INHIBIT 0x200 read write D32 This read write register is used for software inhibit of individual channels or arbitrary channel groups The inhibit condition is an OR of the front panel inhibit where activated and the inhibit register Bit Function 31 0 enable 1 inhibit channel 32 counting 0 0 enable 1 inhibit channel 1 counting At power up or after key reset the register the register will read 0 1 e all scaler channels are active 7 20 Counter clear register 0x204 define SIS3820 COUNTER CLEAR 0x204 write only D32 On write access to this register each channel can be cleared individually by the setting of the corresponding bit Bit write Function 31 1 clear channel 32 0 1 clear channel 1 7 21 Counter Overflow register 0x208 define SIS3820 COUNTER OVERFLOW 0x208 read write D32 This regis
3. 7 11 CBLT Broadcast setup register define SIS3820 CBLT BROADCAST SETUP 0x30 read write D32 This read write register defines whether the SIS3820 will participate in a CBLT The configuration of this register and the registers of other participating modules is essential for proper CBLT behaviour CBLT is supported from the shadow register set and the SDRAM in FIFO emulation mode Bit Function 31 CBLT Broadcast address bit 31 30 CBLT Broadcast address bit 30 29 CBLT Broadcast address bit 29 28 CBLT Broadcast address bit 28 27 CBLT Broadcast address bit 27 26 CBLT Broadcast address bit 26 25 CBLT Broadcast address bit 25 24 CBLT Broadcast address bit 24 23 0 22 0 21 0 20 0 19 0 18 0 17 0 16 0 15 Geographical address bit 4 14 Geographical address bit 3 13 Geographical address bit 2 12 Geographical address bit 1 11 Geographical address bit 0 10 0 9 0 8 0 7 0 6 0 5 Enable Broadcast Master 4 Enable Broadcast 3 0 2 First to be set to 1 on the first module in the CBLT chain 1 Last to be set to 1 on the last module in the CBLT chain 0 enable CBLT to be set to 1 on all modules in the CBLT chain The function meaning of the CBLT and the geographical address is illustrated in section 14 7 1 Page 29 of 72 SIS Documentation SIS3820 SIS GmbH A VME Scaler VM
4. Bit Function Default 31 0 e 0 16 0 15 0 14 0 13 0 12 RORA ROAK Mode 0 RORA 1 ROAK 0 11 VME IRQ Enable 0 IRQ disabled 1 IRQ enabled 0 10 VME IRQ Level Bit 2 0 9 VME IRQ Level Bit 1 0 8 VME IRQ Level Bit 0 0 H IRQ Vector Bit 7 placed on D7 during VME IRQ ACK cycle 0 6 IRQ Vector Bit 6 placed on D6 during VME IRQ ACK cycle 0 5 IRQ Vector Bit 5 placed on D5 during VME IRQ ACK cycle 0 4 IRQ Vector Bit 4 placed on D4 during VME IRQ ACK cycle 0 3 IRQ Vector Bit 3 placed on D3 during VME IRQ ACK cycle 0 2 IRQ Vector Bit 2 placed on D2 during VME IRQ ACK cycle 0 1 IRQ Vector Bit 1 placed on D1 during VME IRQ ACK cycle 0 0 IRQ Vector Bit 0 placed on DO during VME IRQ ACK cycle 0 The power up default value reads Ox 00000000 Page 22 of 72 SIS Documentation SIS3820 SIS GmbH A VME Scaler VME 7 4 Interrupt Control Status register OxC define SIS3820 IRQ CONTROL OxC read write D32 The interrupt sources are enabled with the interrupt control register The interrupt source is cleared in the interrupt service routine The status internal IRQ flag can be used for tests without activating VME interrupt generation It is set whenever an interrupt would be generated if interrupting would be enabled in the interrupt configuration register fourth condition is reserved for future use
5. The SIS3820 board comes with the sis3820 h header file that defines register offsets as well as relevant bit addresses within the registers This header file should facilitate SIS3820 software development for all platforms C example code for the SIS3820 is provided for both Visual C and LINUX The code was written to be used with the SIS1100 3100 PCI to VME interface but should be readily portable to other environments Page 68 of 72 SIS Documentation SIS3820 SIS GmbH t VME Scaler VME 16 Glossary Following shorthands expressions are used throughout the manual Term Explanation ChN Channel N as LNE source CIP Copy in progress data are copied from the frontend FPGA registers to memory registers on the VME FPGA Clock Shadow Initiate copy process of frontend scaler data to register set FPGA Field Programmable Gate Array KA Key address Write access with arbitrary data to a key address initiates the specified function LNE Load Next Event Initiate next counting period save data from previous counting period MCS Multi Channel Scaler Page 69 of 72 SIS Documentation SIS3820 SIS GmbH y VME Scaler VME 17 Index 1 DO a GAR Re ae ties 10 dwell me s 10 38 10 MH 2 OI aiii es 36 E 2 EFEO e n N 48 53 57 ZEN ME a aoe 8 10 30 68 CASE seas oi da voces EESE 24 EEPROM Ana r E e EEA 42 A E A O td at 15 EE 8 EN_GEO ENEE 15 DD id iio 8 11 15 51 Enable ner dre 61 ADE e
6. DI A Coho SN eas 8 63 FIFO almost Du 23 data Tomat 37 FIFO threshold oooooonoccccnococccononaccnonancconnnnns 23 24 Data Format 44 EN TEE 23 24 PVC IDC hoes lts 67 eg Wii Beastial 23 25 EEN 22 preset reached iii iia 24 DS Mii been DEE eene 68 SOUICE 2 iris 24 DS 2430 iii Ais Ad 42 O 24 Page 70 of 72 SIS Documentation SIS3820 SIS GmbH VME Scaler VME Source Dae Shits Sivan Boies whee 24 non clearing sse eee eee eee 25 37 61 SOUICE 2 2 wine eR Reh i Shaka 24 26 O operations iise arent sia eieae eini 33 o eeh See dee Ee eh 24 25 QUO h rons ca ira 35 60 SOUICO ee gees ege EA doit losas ect 25 UE 58 IRQ Tiodemcosidiicis atic ha did aon 22 SDRAM sitiada ltda ee 35 60 ROARK ois cases Acs nein a ida ad 22 mode RORA csi triste cd ea dadas aes 22 25 MHz test pulses es sese ee eee 20 counter LOSE vives eege sonido ee donadas costes dente 20 J modes of operation sees sees eee 33 J115 monostabDle eate ie Ta diato ak ENT ATE dha E e 47 AEN 52 Multi channel scaler sees ee eee 10 MAA TS 52 Mul scalmg noo 60 JTAG anotadas alaba 9 52 N jumper Setting 51 K NIM eege acia da 55 57 TRA ss cat s odia 69 d L Old COUNTER eege deed ed sessed a ee en 61 Operating conditions oocoococccnconononocconononanannnonncnnono 67 latching ocaler ecn n RE 10 59 output LED mana pad 47 JA ein etek Ee 35 ACCESS iii ti 47 LE 1 ins din 60 IR 13 COPY iN Progress 60 Colo nia e si 47 al citan tia tinas 35 TLS a E E e TE E i 67 SDRAM empt
7. 11 15 XC1BV04 un 52 Page 72 of 72
8. 24 Status Operation Armed 23 Status Operation SDRAM FIFO Test Enabled 22 switch off reference pulser channel 1 0 21 counter test mode 0 20 clear 25MHz test pulses 0 19 0 18 Status Operation MCS Enabled Active 17 0 16 switch off user LED Status Operation Scaler Enabled Active 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 switch on reference pulser channel 1 Status reference pulser 5 enable counter test mode Status counter test mode enable 4 enable 25MHz test pulses Status 25MHz test pulses 3 0 2 0 1 0 0 switch on user LED Status User LED 1 LED on 0 LED off denotes power up default setting i e the power up reading of the register is 0x0 Page 19 of 72 SIS Documentation SIS3820 SIS GmbH VME Scaler VME 7 1 1 Counter test mode VME Key test pulse signals will be counted by all non inhibited counters in test mode Counter test mode has to be activated for 25 MHz test pulse operation also 7 1 2 25 MHz test pulse mode All non inhibited scaler channels will count 25 MHz test pulses 1f this bit and the counter test mode bit is set 7 1 3 Reference pulser channel 1 Channel 1 will count 50 MHz reference pulses precision defined by the on board 100 ppm 50 MHz quarz if this bit is set Note test mode has priority over reference pulser i e reference pulses will not be counted if test mode with or without 25 MHz test pulse mode is active Page 20 of
9. 4 IN18 IN18 3 2 IN IN1 1 2 IN17 IN17 1 Front view Front view INx ECL High active INx ECL High active INx ECL Low active INx ECL Low active Control Connector Input 1 4 Output 5 8 PIN _ SIGNAL SIGNAL PIN 20 GND GND 19 18 OUT8 OUT8 17 16 OUT7 OUT7 15 14 OUT6 OUT6 13 12 OUTS OUT5 11 10 GND GND 9 8 IN4 IN4 H 6 IN3 IN3 5 4 IN2 IN2 3 2 IN IN 1 Front view INx ECL High active INx ECL Low active OUTx ECL High active OUTx ECL Low active Page 48 of 72 SIS Documentation SIS3820 VME Scaler SIS GmbH t VME 9 3 2 TTL Data Connector Channel 1 16 Data Connector Channel 17 32 PIN SIGNAL SIGNAL PIN PIN SIGNAL SIGNAL PIN 32 IN16 GND 31 32 IN32 GND 31 30 INIS GND 29 30 IN31 GND 29 28 IN14 GND 27 28 IN30 GND 27 26 IN13 GND 25 26 IN29 GND 25 24 IN12 GND 23 24 IN28 GND 23 22 IN11 GND 21 22 IN27 GND 21 20 IN10 GND 19 20 IN26 GND 19 18 INO GND 17 18 IN25 GND 17 16 IN8 GND 15 16 IN24 GND 15 14 IN7 GND 13 14 IN23 GND 13 12 IN6 GND 11 12 IN22 GND 11 10 INS GND 9 10 IN21 GND 9 8 IN4 GND 7 8 IN20 GND 7 6 IN3 GND 5 6 IN19 GND 3 4 IN2 GND 3 4 IN18 GND 3 2 IN GND 1 2 IN17 GND 1 Front view Front view INx TTL Low active
10. DGND DGND 32 not connected notconnected 32 not connected not connected Page 65 of 72 SIS Documentation SIS3820 SIS GmbH AA VME Scaler VME 15 2 Row d and z Pin Assignments The SIS3820 is ready for the use with VME64x and VME64xP backplanes Features include geographical addressing PCB revisions V2 and higher and live insertion hot swap The used pins on the d and z rows of the P1 and P2 connectors are listed below Position P1 J1 P2 J2 Row z Row d Row z Row d 1 VPC 1 2 GND GND 1 GND 3 4 GND GND 5 6 GND GND 7 8 GND GND 9 GAP 10 GND GAO GND 11 RESP GA1 12 GND GND 13 GA2 14 GND GND 15 GA3 16 GND GND 17 GA4 18 GND GND 19 20 GND GND 21 22 GND GND 23 24 GND GND 25 26 GND GND 27 28 GND GND 29 30 GND GND 31 GND 1 GND 1 32 GND VPC 1 GND VPC 1 Note Pins designated with 1 are so called MFBL mate first break last pins on the installed 160 pin connectors VPC 1 pins are connected via inductors Page 66 of 72 SIS Documentation SIS3820 SIS GmbH t VME Scaler VME 15 3 Connector Types Find below a list
11. a CBLT over the 4 modules with the selected geographical addresses showing up in the header and trailer words If the modules contain no scaler data in FIFO emulation mode the resulting VME data will look like shown below 32 bit data word Content Comment 1 0x08000000 Header module 1 Geo 1 2 0x08000008 Trailer module 1 8 Bytes 3 0x 10000000 Header module 2 Geo 2 4 0x 10000008 Trailer module 2 8 Bytes 5 0x 18000000 Header module 3 Geo 3 6 0x 18000008 Trailer module 3 8 Bytes 7 0x20000000 Header module 4 Geo 4 8 0x20000008 Trailer module 4 8 Bytes Page 63 of 72 SIS Documentation SIS3820 SIS GmbH y VME Scaler VME 14 7 2 CBLT hints While it is trivial to setup a block of modules for CBLT readout one has to be aware of specialities of this readout form e The user has to make sure that the read access to the CBLT address is a block transfer with address modifier AM 0xB e g 1 e the modules will not respond to a read which 1s broken down into many single reads AM 0x9 e g This can be verified with a VME diagnosis module like the VDIS or with an oscilloscope and an extender e The data have to be read in one big chunk otherwise the transfer will re commence in the first module of the block after a termination Many CPUs have 256 Bytes as maximum block size to give a second VME master a chance to get bus mastership If the anticipated maximum number of data word
12. bit1 0 bitO 1 Mode 2 bit2 0 bitl 1 bitO 0 Mode 3 bit2 0 bitl 1 bitO 1 Mode 4 bit2 1 bit1 0 bitO 0 Modes 5 to 7 reserved Input assignment input 1 gt no function input 2 gt no function input 3 gt no function input 4 gt no function input gt external next pulse LNE clock shadow input 2 gt external user bit 1 input 3 gt external user bit 2 input 4 gt inhibit LNE input 1 gt external next pulse LNE clock shadow input 2 gt external user bit 1 input 3 gt inhibit counting input 4 gt inhibit LNE input 1 gt external next pulse LNE clock shadow input 2 gt external user bit 1 input 3 gt external user bit 2 input 4 gt inhibit counting input 1 gt inhibit counting channels 1 8 input 2 gt inhibit counting channels 9 16 input 3 gt inhibit counting channels 17 24 input 4 gt inhibit counting channels 25 32 input 1 gt no function input 2 gt no function input 3 gt no function input 4 gt no function Note following LNE sources are affected by the LEN inhibit input external LNE front panel signal internal 10 MHz channel N ChN Page 34 of 72 SIS Documentation SIS3820 SIS GmbH VME Scaler VME 7 15 3 Output mode The SIS3820 SCALER board has 4 control outputs They can be assigned to different signals with the 2 output modes bit of the acquisision operation mode register as listed in the table b
13. configuration cceeeeseeeeeeeeeeeeeeee 22 Page 71 of 72 SIS Documentation SIS3820 SIS GmbH y VME Scaler VME interrupt Control 22 T interrupt control StatUS see eee eee eee 23 LNR bannel OA 39 d e EE 52 A O te eee 64 modal Md 21 ES EEN e ege D e 52 module Id and firmware revisgion 11 3 EE Ee eet 52 One Wild di 42 i A POC RENE S 39 44 61 Technical Propertes Features sees sese eee 8 Ss CH See SS 25 CA A 53 54 Bae agen ee Ay eMac UA INIS Overflow E 41 E EH EE 63 NN EE 41 TM a ad da re 49 56 preset channel seet 40 Tund 22 preset enable and hit ca Seene ee 14 59 A ba preset enable mask esse eee eee 10 U preset 1 earnee re t n E 28 lt preset hit MASK tooodo 10 Universe lL 22 user presetyalleu ici S 10 bit 1 34 44 RE E E 28 m EE Se EE EE 28 ee os at Set NIE cas TA ce AIR ALT ta cog pee SDR AMES Eick atc he arr accents 30 43 SC eege ee Shadow E E CO ee 2 O AN AAA A 22 EE 45 RECH 22 V rotary SWIC EE 15 KIEM EE 10 A MEC aa 52 A 64 Bain ii a es nad 22 ymp O nn 64 67 A See Een dee DEA Ee 10 SDRAM ooo ooo ooo soos 9 37 61 67 ACCESS LOSE Se 11 SORA 35 SS GR EE e E EENEG 35 EE z SN NOS 8 d EE O ae tg pe he 68 Signal Specification esse eee 57 eege E EE 57 ME e Inputs 57 NV ME 64K e r its 8 15 66 67 ESAS a KEE dl da 66 SIS1100 3100 ecco 11 68 d E RERNA OS 65 SS A A a teenie 30 W SIS3100 HISC AL 10 hd j TET AS 11 68 Watchdog EE 5 Software Support 68 X AE NEE 11 15 AN Taala
14. ege EENEG EES evades eset 43 1 23 2 incrementing VME Masters sia wes oil tod A acted lia SE ie dai ds dotes dos ix tet 43 7 24 SDRAM address space Us RUUUOU 0x FFCT nn nono nono nnnrnn nc cn nnnranccnnes 43 8 Data Format ua ld old eege 44 8 1 32 bit Mode cai a iia 44 8 2 24bit Modernidad ees 44 8 3 16 bit EE 45 E EE e 45 9 Front pane ME eq penta eed tee ems asada and NA cans 46 9 1 Front RT E EST TL undeet erte EE EENS Ee SE ee 46 9 2 Front Panel E A D ES E EEE o e 47 9 3 Flat cable Input Output Pin Assignment 00 cc ceceeseeecseeeecsseeecesecseesecsecseesecsesseceaeeecsaecateeesaecaeesesaeenae 48 ESP WE ei EE 48 A RON 49 10 Board B eT ere 50 TSW JUMP SELENE e 51 IT EE 51 DE IA 51 11 3 JIPITO JTAG dE E 52 ILA CONSO0 STAG sexs ie irs reas 52 12 Input Configura on tinc 53 M21 SR e EE 53 12 2 O E 54 123 NIM eebe listones illa 55 KS VE EE 56 12 41 TTELEMO nato ion lio ci 56 124 2 Er RR E UE EE 56 E EE ET e EE 57 Bh a 1 21 Eelere o See ee 57 13 2 Lu EE 57 133 GE CT 57 14 Theory OF Opera nina ciales Edi ENEE 58 tt Enable Lori A deat E AE Ee EES 58 A Readon OCN 59 T43 Eatehine Scalen caducidad dnde caida Eiere bec Wasa Be eren ee der bd de debe il EE 59 14 4 Preset SCalim E 59 14 5 Multiscaling MES alain 60 1431 NA 60 14 52 arm enable with MCS ege n cavetenntonssentenshouiecesnsuubeccevivnswesadeesndevnenteens 61 14 6 Clearms non clearing Mode tii iii 61 14 7 CBLT readout not implemented in 38
15. mode 1 2 3 CHN enabled selected Key Enable Key Reset E Clear Acq Preset Page 58 of 72 SIS Documentation SIS3820 SIS GmbH t VME Scaler VME 14 2 Read on the fly The SIS3820 supports read on the fly i e readout in parallel to the acquisition of new counts with an accuracy down to the lowest bit at the full counting rate of 200 MHz While the uncertainty on a read on the fly is one count no counts are lost A read from a counter register of the SIS3820 initiates a clock shadow transaction and the actual counter value that is read from VME is taken from the shadow register The counter values of all 32 scaler channels are latched to the shadow registers simultaneously when the read on the fly is done in BLT32 Minimum difference in time i e less than 5 ns variation of the read values can be achieved with this mechanism 14 3 Latching scaler Counter data can be copied to the shadow registers in three ways e Key VME LNE clock shadow e external next pulse LNE clock shadow with input modes 1 2 and 3 e read from the counter registers Shadow register data are not altered updated in the normal counting process i e the latched values can be re read until they are overwritten by the next clock shadow cycle 14 4 Preset Scaling In preset mode the counting mode is started by an enable command and stopped by a channel reaching the preset value of counts The preset reached state can be
16. of connector types that are used on the SIS3820 Connector Purpose Part Number 160 pin zabcd VME P1 P2 Harting 02 01 160 2101 20 pin header Control flat cable versions DIN41651 20 Pin AMP e g 34 pin header Inputs flat cable versions DIN41651 34 Pin AMP e g LEMO Control and Input LEMO versions LEMO ERN 00 250 CTL SDRAM SDRAM memory socket Berg 88638 60002 15 4 Power consumption The SIS3820 is a single 5 V supply board Lower positive voltages 3 3 V and 2 5 V are generated with low dropout regulators 5 V is generated with up to 3 DC DC converters Board type Voltage _ Current SIS3820 SCALER 32 ECL channels 5 V 2 0 A SIS3820 SCALER 32 TTL channels 5 V 13A SIS3820 CLOCK 32 NIM channels 5 V 3 2 A 15 5 Operating conditions 15 5 1 Cooling Although the SIS3820 is mainly a 2 5 and 3 3 V low power design forced air flow is required for the operation of the board The board may be operated in a non condensing environment at ambient temperatures between 10 and 40 Celsius 15 5 2 Hot swap live insertion Please note that the VME standard does not support hot swap by default The SIS3820 is configured for hot swap in conjunction with a VME64x backplane In non VME64x backplane environments the crate has to be powered down for module insertion and removal 15 6 LED selftest During power up self test and FPGA configuration all LEDs except th
17. throughput as minimum setup time is involved 7 23 2 incrementing VME master Most VME masters use address auto incrementing on block transfers The FIFO address space of 64 Bytes is a good compromise for large memories also The user has to set up several block transfers to read larger portions of memory 7 24 SDRAM address space 0x80000 OxFFFFFC define SIS3820 SDRAM BASE 0x800000 read only D32 BLTs For larger memories than 64 MBytes SDRAM sections pages of 64 MBytes are selected with the SDRAM page register Page 43 of 72 SIS Documentation SIS3820 SIS GmbH A VME Scaler VME 8 Data Format The SIS3820 has 4 different data formats They are defined by the data format bits of the acquisition operation mode registermode Non MCS data format is the same as 32 bit MCS 8 and 16 bit mode were implemented to achieve both lower minimum dwell times and data volume reduction in low count rate short dwell time environments MCS Bit 1 MCS Bit 0 Mode 0 0 32 bit 0 1 24 bit channel user 1 0 16 bit 1 1 8 bit 8 1 32 bit Mode The data word contains the straight scaler contents in this mode Bits 31 24 Bits 23 16 Bits 15 8 Bits 7 0 Data Bits 31 24 Data Bits 23 16 Data Bits 15 8 Data Bits 7 0 8 2 24 bit Mode The lower 24 bits hold the scaler value in this mode the upper eight data bits contain the latched status of the two user bitss and the bank and ch
18. 000 03477ce7 00000000 00000000 00000000 cho2 cho6 ch10 ch14 ch18 ch22 ch26 ch30 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 now with reference pulser on SIS3820 scaler counting gotwords 32 scaler data chol cho5 cho9 ch13 ch17 ch21 ch25 ch29 0eedfb33 00000000 00000000 00000000 0348d70d 00000000 00000000 00000000 cho2 cho6 ch10 ch14 ch18 ch22 ch26 ch30 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 cho3 cho7 chil ch15 ch19 ch23 ch27 ch31 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ch1 enabled cho3 cho7 chil ch15 ch19 ch23 ch27 ch31 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 cho4 ch08 ch12 ch16 ch20 ch24 ch28 ch32 cho4 ch08 ch12 ch16 ch20 ch24 ch28 ch32 Note The 50 MHz reference pulse generator will give you accuracy of your LINUX system 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 an idea on the sleep scheduling Page 12 of 72 SIS Documentation SIS3820 SIS GmbH 4 VME Scaler VME 5 3 4 Multiscaler MCS MCS mode is demonstrated with the program sis3820_mcs c With respect to the fact that SDRAM mode with a fixed number of acquisitions is used its kind of a minimum approach that does not m
19. 06ee942 ch04 00000000 scan 008 cho1 00000000 ch02 00000000 ch03 0076e9f4 ch04 00000000 scan 009 cho1 00000000 ch02 00000000 ch03 00000000 ch04 00438a6e scan 010 cho1 00000000 ch02 00000000 ch03 00000000 ch04 00a7d8 7 Page 13 of 72 SIS Documentation SIS3820 SIS GmbH VME Scaler VME 5 3 5 Preset Scaler The sis3820_preset example illustrates preset scaling Counter group is activated for preset scaling with channel 4 selected as preset channel A value of 0x1000000 is written to the preset value register of counter group 1 and the logic enabled afterwards The status of the preset enable and hit register is polled until channel group 1 has reached its preset value mkiemki sis1100 sis3820 gt sis3820 preset gotwords 32 scaler data cho1 00000000 cho2 00000000 ch03 00000000 ch04 01000002 cho5 00000000 ch06 00000000 ch07 00000000 ch08 00000000 cho9 00000000 ch10 00000000 chil 00000000 ch12 00000000 ch13 00000000 ch14 00000000 ch15 00000000 ch16 00000000 ch17 00000000 ch18 00000000 ch19 00000000 ch20 00000000 ch21 00000000 ch22 00000000 ch23 00000000 ch24 00000000 ch25 00000000 ch26 00000000 ch27 00000000 ch28 00000000 ch29 00000000 ch30 00000000 ch31 00000000 ch32 00000000 mkiemki sis1100 sis3820 gt Note It will take in the order of 140 ns after the preset condition was detected before the counter will stop counting This implies that the actual stored counter value will be greater than the preset value fo
20. 20 01 01 firmware sss sese sese essen 62 147 IL CBET Setup example nunca cluspwevsbns ratheetusebe eth R 63 AT OBESA ds 64 AAA O eegene ee 65 kO Nee OE T EE 65 15 2 Row dand z Pin A egtgtnentg eii o ie dia 66 15 3 Connector TY pesitos tico did aia di EEEE VEEE E Sante 67 Uer EE 67 15 5 RL EE Me 67 ISS Cool aiii Ae Ai A Bote ied tl Ee 67 15 5 2 Hotswap iveinseri Mitin A A ti e ee sas 67 Page 4 of 72 SIS Documentation SIS3820 SIS GmbH t VME Scaler VME 15 6 EED selftest aior erioa aia eae 67 157 VME readout performance sinees iaren erne ainan iian eese Ser EE EaR eaae T E Bhide 68 15 8 Software HDD s NN 68 A EE 69 A 70 Page 5 of 72 SIS Documentation SIS3820 SIS GmbH l VME Scaler VME Page 6 of 72 SIS Documentation SIS3820 SIS GmbH VME Scaler VME 2 Introduction The SIS3820 is a multi purpose counter It combines the functionality of the SIS3800 scaler and the SIS3801 multiscaler with extended funtions The proven concept of flexible leaded component based frontend circuitry in conjunction with more recent FPGA field programmable gate array technology results in unprecedented flexibility to implement the given readout application Applications comprise but are not limited to Nuclear Phyics Particle Physics Neutrino Astrophysics Synchrotron Radiation Neutron Scattering Machine accelerator diagnosis Scanning microscope readout 2 1 Implementation note firm
21. 72 SIS Documentation SIS3820 SIS GmbH i VME Scaler VME 7 2 Module Id and Firmware Revision Register 0x4 read define SIS3820 MODID 0x4 read only D32 This register reflects the module identification of the SIS3820 and its minor and major firmware revision levels The major revision level will be used to distinguish between substantial design differences and experiment specific designs while the minor revision level will be used to mark user specific adaptations Bit Function Reading 31 Module Id Bit 15 30 Module Id Bit 14 29 Module Id Bit 13 3 28 Module Id Bit 12 27 Module Id Bit 11 26 Module Id Bit 10 25 Module Id Bit 9 8 24 Module Id Bit 8 23 Module Id Bit 7 22 Module Id Bit 6 7 21 Module Id Bit 5 20 Module Id Bit 4 19 Module Id Bit 3 18 Module Id Bit 2 17 Module Id Bit 1 0 16 Module Id Bit 0 15 Major Revision Bit 7 14 Major Revision Bit 6 13 Major Revision Bit 5 12 Major Revision Bit 4 11 Major Revision Bit 3 10 Major Revision Bit 2 9 Major Revision Bit 1 8 Major Revision Bit 0 7 Minor Revision Bit 7 6 Minor Revision Bit 6 5 Minor Revision Bit 5 4 Minor Revision Bit 4 3 Minor Revision Bit 3 2 Minor Revision Bit 2 1 Minor Revision Bit 1 0 Minor Revision Bit 0 7 2 1 Major revision numbers Find below a table with major revisi
22. 74F245 Control Connector Input 1 4 Output 5 8 PIN SIGNAL SIGNAL PIN 20 GND GND 19 18 OUT8 GND 17 16 OUT7 GND 15 14 OUT6 GND 13 12 OUTS GND 11 10 GND GND 9 8 IN4 GND 7 6 IN3 GND 5 4 IN2 GND 3 2 INI GND 1 Front view INx TTL Low active 74F245 OUTx TTLLow active 74F244 INx TTL Low active 74F245 Page 49 of 72 SIS GmbH VME SIS3820 VME Scaler SIS Documentation 10 Board Layout Find below a printout of the top assembly drawing T BLECK Zeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeee SS NOA eeeeeeeeeeeeeeegeeeeeeeeeeeeee EL SN Oeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeee Lhe E Le m n DI UL D U IL IL W Simm Whi Um 11 ee HIH IIA IA Pht 11H 111 PL 11T 1 MAEN 2 EI I 1111111 oe E wall A Sram MOLOI Ki ac KE ma Li ki ac Dr SIS ee e L OPIL O GE pi neeese 0000000 2 fl ee SS See E ADLADI DOT GOL LOTO AOIC ZO Ue te mozme o o o me e o nai i Ey T RG ir qu ele o e e ele TOH Sms LT1594CT 1 e ge eis SE ei ee N Gm kee rami STO L6801M 393 td Hei vrezi sl III UUU WA LT15B4CT perreo Serena Benes Sch IW II H 1 oeeeeeeeeeeeeee e000000000000000 e0886800888080080 6005000000000000 usia FAME o ae a ee mje 6 UD HH mai III l DE meee i CN Bel O ULI ue Page 50 of 72 SIS Documenta
23. C define SIS3820 FIFO WORDCOUNT_THRESHOLD 0x3C read write D32 This read write only register holds the fill level threshold for interrupt generation The FIFO word counter longword i e number of 32 bit words threshold is compared to the FIFO word counter register contents an interrupt is generated as soon as the number of data words in the SDRAM exceeds the threshold Bit Function 31 none read as 0 28 none read as 0 27 FIFO word counter threshold bit 27 1 FIFO word counter threshold bit 1 0 FIFO word counter threshold bit 0 Notes e in principle memory strips of up to 1 GByte can be handled with this 28 bit deep FIFO word counter threshold implementation e the 3820 01 Ol firmware will set a FIFO error as soon as 64 MB 512 longwords are reached with the possibility of data words still being buffered in pipelines and being stored without data loss Page 32 of 72 SIS Documentation SIS3820 VME Scaler SIS GmbH VME 7 15 Acquisition Operation Mode register 0x100 define SIS3820 ACQUISITION MODE 0x100 read write D32 Bit Function Default 31 reserved 30 Operation Mode bit 2 29 Operation Mode bit 1 28 Operation Mode bit 0 27 Reserved 26 Reserved 25 Reserved 24 reserved 23 Control outputs inverted 22 reserved 21 Control output mode bit 1 20 Control output mode
24. E 7 12 SDRAM page register 0x34 define SIS3820 SDRAM PAGE 0x34 read write D32 This read write register was implemented to reduce the address space that is occupied by the SIS3820 The idea is to divide the SDRAM that can have a size of up to 1024 Mbytes into 8 MByte pages The contents of the SDRAM page register defines what 8 MByte page is addressed The page will be incremented automatically during a block transfer BLT32 MBLT64 2eVME beyond a page boundary This will allow you to read large chunks of memory with the SIS3100 VMe sequencer and similar hardware in one go The page number is not modified by the MCS scaler data acquisition process e Function LA none read as 0 none read as O page number bit 6 page number bit 5 page number bit 4 page number bit 3 page number bit 2 page number bit 1 SIR ISCH ECH KOERSCH oo page number bit 0 The power up value for the page number is 0 Page 30 of 72 SIS Documentation SIS3820 SIS GmbH t VME Scaler VME 7 13 FIFO word counter memory address pointer register 0x38 define SIS3820 FIFO WORDCOUNTER 0x38 read D32 This read only register holds SDRAM fill level information Bit Function 31 none read as 0 28 none read as 0 27 word counter bit 27 1 word counter bit 1 0 word counter bit 0 The word counter is e clear
25. GmbH t VME Scaler VME 12 3 NIM The 50 Q input termination can be removed in groups of four channels by removing the corresponding resistor networks The termination of single control inputs can be disabled with jumpers J101 through J108 an open jumper disables the termination of the corresponding channel Network Channels U15 Pins 10 to 6 1 4 U15 Pins 1 to5 5 8 U35 Pins 10 to6 9 12 U35 Pins 1 to 5 13 16 U55 Pins 10 to 6 17 20 U55 Pins 1 to5 21 24 U75 Pins 10 to 6 25 28 U75 Pins 1 to5 29 32 U115 Pins 10 to 6 Control 1 4 U115 Pins 1 to 5 Control 5 8 The schematics of the NIM input circuitry is shown below GND ga Ref 0 35 V Page 55 of 72 SIS Documentation SIS3820 SIS GmbH y VME Scaler VME 12 4 TTL The TTL input level option is possible with LEMO and flat cable connectors 12 4 1 TTL LEMO The low active TTL LEMO input circuitry is sketched below A high active version can be implemented by replacing the 74F245 with a 74F640 es 1K 245 12 4 2 TTL Flat Cable In the flat cable TTL version the positive right hand side of the connector is tied to ground ee 7 1K E 245 Page 56 of 72 SIS Documentation SIS3820 SIS GmbH t VME Scaler VME 13 Signal Specification 13 1 Control Signals The width of clear and external next pulses has to be greater or equal 10 ns an external inh
26. IRQ source 0 edge sensitive In multiscaler or multi channel scaler MCS mode interrupt source 0 is associated to the LNE load next event signal The interrupt is issued whenever a LNE signal triggers scaler value transfer to memory The interrupt will be induced by the rundown of the preset value if LNE prescaling is active In scaler mode the LNE interrupt is driven by the clock shadow signal 7 4 1 2 FIFO threshold IRQ source 1 level sensitive The FIFO threshold IRQ source can be used for efficient readout in FIFO emulation mode The interrupt will be triggered as soon as the number of data words in memory will exceed the non 0 value of the FIFO threshold register 7 4 1 3 Acquisition completed IRQ source 2 edge sensitive The number of counting periods to acquire data can be defined with the acquisition preset register in MCS mode The acquisition completed interrupt source can be used to trigger an interrupt with this condition Page 24 of 72 SIS Documentation SIS3820 SIS GmbH t VME Scaler VME 7 4 1 4 Overflow IRQ source 3 level sensitive The overflow interrupt source is triggered if one or more counters exceed the 32 bit range The overflow registers can be used to identify the channel that has caused the interrupt Overflow interrupt generation is active in non clearing mode only 7 4 1 5 FIFO almost full IRQ source 4 edge sensitive This interrupt source can be used to catch the FIFO almost full error
27. O if disabled 0 2 Enable IRQ source 2 Status enable source 2 read as 1 if enabled 0 if disabled 0 1 Enable IRQ source 1 Status enable source 1 read as 1 if enabled O if disabled 0 0 Enable IRQ source 0 Status enable source 0 read as 1 if enabled 0 if disabled 0 The power up default value reads 0x 00000000 Note The clear IRQ source bits are relevant for edge sensitive IRQs only Page 23 of 72 SIS Documentation SIS3820 SIS GmbH VME Scaler VME The generation of the status flags the IRQ flags and the actual IRQ is illustrated with the schematic below IRQ ACK cycle V EN Status FLAG Source 0 Status IRQ Source 0 Source 0 VME IRQ enable Clear Enable 0 IRQ_Update internal A N D ez Status FLAG Clear IRQ ROAK case Source 1 Source 1 Status IRQ Source 1 VME_IRQ Enable 1 Mux VMEIRQ AND m Status FLAG Source 7 IRQ RORA case Source 7 Clear Enable 7 Note Source 0 is shown as edge sensitive and source 1 as level sensitive input in the drawing above Which interrupt sources are edge and level sensitive may vary from firmware implementation to firmware implementation 7 4 1 Interrupt sources A short explanation of the implemented interrupt sources is given in the following subsections 7 4 1 1 LNE clock shadow
28. SIS Documentation SIS3820 SIS GmbH t VME Scaler VME SIS3820 VME Scaler User Manual SIS GmbH Harksheider Str 102A 22399 Hamburg Germany Phone 49 0 40 60 87 305 0 Fax 49 0 40 60 87 305 20 email info Ostruck de http www struck de Version 1 00 as of 24 06 03 Page 1 of 72 SIS Documentation SIS3820 SIS GmbH A VME Scaler VME Revision Table Revision Date Modification 0 0x 13 02 02 Start of module definition 0 10 23 06 03 Prerelease 1 00 24 06 03 First official release Page 2 of 72 SIS Documentation SIS3820 VME Scaler SIS GmbH VME 1 Table of contents T Table 0 COMTI aii tor iaa tad 3 E ee 7 2 Implementation note firmware version 3820 01 01 7 gt gt Technical Properties Pe atutes ur dd EE 8 d Functional lirica 9 4 1 Block Diaria li a Bante a ds iia 9 4 2 SModesof Operations uecht S desc 10 4 2 1 S aler COUMEL csi di E e dedos IA adan 10 4 2 2 Latchine Scale aia in ia diia dla dica 10 4253 PILOSEUS CALE WEE 10 4 2 4 Multi channel Scaler MCS cc ccssccssssecssccssssecseccsssseceeecsssecsssesensecsacessasessascesnsesscesneessnsesensess 10 4 2 5 Histogramming Scaler not in 3820 01 01 design 10 O 11 Sel Installation e sepsis cacci cui idad indeed ZRA i en ves dagannencevstees des deed ob eveuecentandecetsveendns ave 11 5 2 LINUX example test code tna a 11 5 3 Initial VME access fest ecrire Eed cance tac n ii
29. a 64 enable LOGIC yeter eierne e 58 address enable Source or 36 61 CBE iii 64 F geographical signans ar a 63 address MPa 16 PPO o Nes 61 address moder 64 almost fullscreen a 31 Address SPACE iii e 15 FIFO address space ss esse ee eee eee 43 addressing MOM Wale ii EE 52 geogra meal iii rica iris 8 EPA inicia 67 69 E TT 64 front panel iii aria 8 UM ala 36 58 61 Front Panel ATM Ee rin 36 61 NED EE 47 B Front Panel Layout 46 G back plane voii i 8 15 67 bank ii lt deta 44 6 Sao 15 BERR sitiado iii Si ice 43 62 geographical addressing sse eee ee eee ee eee 66 block MTM 9 lO Yi 69 BLT 32 ita 8 30 63 68 GND cuina 52 board layout acota geed bee 50 H BOND etnicidad ea tens de 22 DUELO A die 17 62 O gies a ee 63 68 C header word WEE 64 histogramming scaler sese eee eee ee 10 CBL eege geed Eed 8 16 29 62 Hots 1 tii 66 67 EE 64 I ut CEET 64 setup example sss sees eee eee 63 Input Configuration sese ee ee eee ee eee eee eee 53 Channel number sese sees eee eee 44 installation A 11 CON E 61 Intel iii nidad 22 Clinica ies 27 69 interr pt eisen OAc anda 24 Clock Shadow sss sees 24 34 35 59 interrupt SOU 24 A EE Ee ee ged Sone 52 INterrupt TH 24 COMMECTON agesate kee ee 8 Interrupter TTT 22 Connector Tvpes ian 67 Interrupter ty Peirano ees da 22 COME iii iii dis tin 67 introductions tei asek e re id 7 COUNT dd 10 IRQ CUITENE COUNTED eoon Eeer 61 acquisitions Teached 24 D almost tl ais ad ios 25 Clock Shad Wii ii its 23 24
30. a EK tases scada E rE TE TEE nidad estate 11 ak User LED testis ege ON 11 5 3 2 Readout of Module Id and firmware revision register sss esse sese eee 11 3 33 Standard WEE 12 3 34 Multiscaler MCS tt ia Sates dia otis een Bee erte ata 13 53 3 O A ON 14 6 NME A A II A A A 15 6 1 Address Map viii sesschssssveethesevesbecsseibdstasessyscsbbessd veessdassbeds adeSestheschyacddoveussbossesiedsdgevsehsctsvesidevesessocsavsteses 16 T Register O o Salata aha aN bent cas 18 7 1 Control Status Register Ox write read sss sese 19 SS A O 20 T223 MHZ test pulse MOG il aiii iii diia 20 11 3 Reference pulser channel llueve date sees eaten eects 20 7 2 Module Id and Firmware Revision Register 0x4 read 21 7 2 1 Major revision number 21 7 3 Interrupt configuration register OX8 sees ee eee eee eee 22 TIT RO modes A A A ey ee AE 22 7 4 Interrupt Control Status register OXC ccs5 scsasesstssessbepessecoehdstssennsacestsensicesepysasdioussbapssoueeedessbuessbevionioas 23 R SN 24 7 5 DANI AAA TTT aT EAEra METH ROST TR 26 7 6 Acquisition countregister 0x14 EE 26 7 7 ENE Prescaler factor register OL islas ion Said secano 27 7 8 Preset value register counter group 1 OX20 nono nono nn cnn none canon non nrnnnss 28 7 9 Preset value register counter group 2 OX24 ooooonccciccnocnnocnoonononconoconocononnoconoconocn nono nono nonn con no rn ncnn crac nrnnenns 28 7 10 Preset Enable and Hit register UNN 28 7 11 CBLT Broadcast setup regist
31. ake use of the full capabilities of the SIS3820 The example uses the internal 10 MHz LNE source which is run through the LNE prescaler to minimize the need for external signals The number of acquisitions is preset with the acquisition preset register The acquisition count register is used to determine completion of the acquisition process Find below the output of the program for 11 LNEs corresponding to 11 time slices with an input rate of 11 MHz moved across scaler channel 1 to channel 4 as the MCS acquisition is going on Note that the CLR LED is pulsed with every LNE and that the S LED is on from the enable command until the acquisition preset has been reached mkiemki sis1100 sis3820 gt sis3820 mcs MCS mode scan 1 completed MCS mode scan 2 completed MCS mode scan 3 completed MCS mode scan 4 completed MCS mode scan 5 completed MCS mode scan 6 completed MCS mode scan 7 completed MCS mode scan 8 completed MCS mode scan 9 completed MCS mode scan 10 completed gotwords 40 scaler data scan 001 ch01 00a7d8f7 cho2 00000000 ch03 00000000 ch04 00000000 scan 002 ch01 00a7d8f7 cho2 00000000 ch03 00000000 ch04 00000000 scan 003 cho1 008 5010 cho2 00000000 ch03 00000000 ch04 00000000 scan 004 cho1 00000000 ch02 003d3c9f ch03 00000000 ch04 00000000 scan 005 cho1 00000000 ch02 00a7d8f7 ch03 00000000 ch04 00000000 scan 006 cho1 00000000 ch02 00225536 ch03 00000000 ch04 00000000 scan 007 cho1 00000000 ch02 00000000 ch03 0
32. angular encoder clock ticks stepper motor ticks as consecutive bins 14 6 Clearing non clearing mode The SIS3820 has two sets of counters The two sets are the actual counters and the old counters Both counter sets are preset to O after a power up key reset or counter clear The actual counter set becomes active with the count enable At LNE or read shadow following process is initiated depending on the non clearing mode bit of the acquisition operation mode register non clearing mode 0 e the contents of the current counter set is subtracted from the contents of the old counter set which was latched by the previous LNE clock shadow and the difference is stored in the shadow register set or copied to SDRAM FIFO e the contents of the current counter set is stored to the old counter set non clearing mode 1 e the contents of the current counter set is stored to the shadow register set or copied to SDRAM FIFO Page 61 of 72 SIS Documentation SIS3820 SIS GmbH A VME Scaler VME 14 7 CBLT readout not implemented in 3820 01 01 firmware CBLT is a method to speed up the readout of small amounts of data from a larger number of slaves in conjunction with long setup time masters As header and trailer words are added in CBLT this readout approach is less efficient than low setup overhead list sequencer readout of masters like the SIS3100 VME sequencer Modules which are supposed to partic
33. annel information The bit names and their function are listed in the table below Bit Contents U2 User Bit 2 Ul User Bit 1 0 0 C4 Channel number Bit 4 C3 Channel number Bit 3 C2 Channel number Bit 2 Cl Channel number Bit 1 CO Channel number Bit 0 Bits 31 24 Bits 23 16 Bits 15 8 Data Bits 7 0 U2 Ul 0 C4 C3 C2 C1 CO Data Bits 23 16 Data Bits 15 8 Data Bits 7 0 Page 44 of 72 SIS3820 VME Scaler SIS Documentation SIS GmbH L VME 8 3 16 bit Mode The data word contains the straight scaler contents in this mode Bits 31 24 Bits 23 16 Bits 15 8 Bits 7 0 Scaler channel N 1 bits 15 0 Scaler channel N bits 15 0 8 4 8 bit Mode The data word contains the straight scaler contents in this mode Bits 31 24 Bits 23 16 Bits 15 8 Bits 7 0 Scaler channel N 3 Scaler channel N 2 Scaler channel N 1 Scaler channel N bits 7 0 bits 7 0 bits 7 0 bits 7 0 Page 45 of 72 SIS Documentation SIS3820 SIS GmbH A VME Scaler VME 9 Front panel elements 9 1 Front Panel Layout The front panel of the SIS3820 is equipped with 8 LEDs 8 control in and outputs and 32 frontend in outputs On flat cable units ECL and TTL the control connector is a 20 pin header flat cable connector and the channel inputs are fed via two 34 pin headers On LEMO NIM and TTL units the con
34. bit 0 19 Control inputs inverted 18 Control input mode bit 2 17 Control input mode bit 1 16 Control input mode bit O 15 reserved 14 reserved 13 Reserved select add mode 12 select SDRAM mode H Reserved 10 Reserved 9 Arm Enable source bit 1 Arm Enable source bit 0 Reserved LNE source bit 2 LNE source bit 1 LNE source bit 0 data format bit 1 data format bit 0 Reserved Cle Al WS BR Mn aj oo select non clearing mode Oll l OY Ol CO COLO Ol elel op ojojop G l l l Gl IG llla o The power up default value reads Ox 00000000 7 15 1 Modes of Operation modes Op Mode bit 2 Op Mode bit 1 Op Mode bit0 Mode of operation 0 0 0 Scaler Counter Latching Scaler 0 0 1 reserved 0 1 0 Multi channel Scaler 0 1 1 reserved Histogramming Scaler 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 SDRAM FIFO VME write test mode Page 33 of 72 SIS Documentation VME Scaler VME 7 15 2 Input modes The SIS3820 SCALER board has 4 control inputs They can be assigned to different signals with the 3 input modes bit of the acquisision operation mode register as listed in the table below All inputs can be inverted with the control inputs inverted bit of the same register Control Input Mode Mode 0 bit2 0 bit1 0 bitO 0 Mode 1 bit2 0
35. bit channel 1 Examples If OxFFFF is written to the copy disable register channels 17 through 32 data will be copied to memory if 0xFFFF0000 is set channels 1 through 16 will be stored Note on copy disable behavior limitations Data forma Copy disable behavior limitations 32 or 24 bit Arbitrary channels can be disabled in a selective fashion 16 bit Groups of 2 channel pairs are copied Chl and 2 Ch2 and 4 e g The corresponding dual channel group is copied if the disable bit of the first channel of the group Ch1 3 e g is not set 8 bit Groups of 4 channel are copied Chl 2 3 and 4 Ch5 6 7 and 8 e g The corresponding four channel group is copied if the disable bit of the first channel of the group Ch1 5 e g is not set Page 38 of 72 SIS Documentation SIS3820 SIS GmbH t VME Scaler VME 7 17 LNE channel select register 0x108 define SIS3820 LNE CHANNEL SELECT 0x108 read write D32 This read write register allows to define which of the 32 front panel scaler channels is used as LNE source in LNE channel N mode The LNE channel has to be selected before the counting process is started and can not be changed during acquisition Bit Function 31 no function read as O 5 no function read as O 4 bit 4 of LNE channel 3 2 1 G 0 bit O of LNE channel Notes 1 The maximum input frequency for the LNE channel is limi
36. condition It is set if the fill level of the SDRAM exceeds 64 MB 512 words in FIFO mode The condition has to be resolved by a KEY_SDRAM_FIFO_RESET Page 25 of 72 SIS Documentation SIS3820 SIS GmbH A VME Scaler VME 7 5 0x10 Acquisition preset register define SIS3820 ACQUISITION PRESET 0x10 read write D32 This read write register allows you to define the number of counting periods to acquire in MCS mode The preset value is 32 bit wide A preset value of O results in continuous MCS operation Further LNEs are ignored after completion of acquisition until a key reset acquisition VME access 1s performed The completion flag is cleared upon reset acquisition also Bit Function 31 bit 31 of preset value 0 bit 0 of preset value e The register can be used in scaler mode also e it is not associated with a direct interrupt Interrupt generation can be accomplished in conjunction with the acquisition completed IRQ source 2 edge sensitive e The status flag of the active mode scaler enabled e g will be cleared upon completion 7 6 Acquisition count register 0x14 define SIS3820 ACQUISITION COUNT 0x14 read D32 This 32 bit wide read only register holds the number of acquisitions It is cleared with the start operation and incremented with consecutive LNE pulses The contents of the acquisition count register is compared with the contents of the acquisition preset register if the later i
37. de Shielding VME64x Front panel VME64x extractor handles on request single supply 5 V in field firmware upgrade capability Page 8 of 72 SIS Documentation SIS3820 SIS GmbH VME Scaler VME 4 Functionality The functionality of the SIS3820 is a combination of hardware printed circuit board design stuffing options and firmware The module consists of two FPGAs that hold the frontend logic and on FPGA that holds the VME interface the SDRAM controller and the control logic functions Logic level adaptation is handled by classic DIL components and single inline SIL resistor networks The firmware is loaded from a serial PROM at power up Both JTAG and VME can be used for in field firmware upgrades changes 4 1 Block Diagram Page 9 of 72 SIS Documentation SIS3820 SIS GmbH y VME Scaler VME 4 2 Modes of operation 4 2 1 Scaler Counter In standard counter scaler mode data can be read on the fly with an accuracy to the least significant bit No counts are lost in read on the fly mode 4 2 2 Latching Scaler In latching scaler mode scaler values are copied to a shadow register set upon a front panel signal LNE or a VME command Broadcast functionality is implemented for the later to allow for minimum time difference over a set of several SIS3820s without front panel cabling 4 2 3 Preset Scaler The SIS3820 can be operated as preset scaler An arbitrary channel or a combination of cha
38. dwell times 4 2 5 Histogramming Scaler not in 3820 01 01 design Histogramming scaler mode MCS mode with add enabled allows to acquire and add MCS data of several repeated scans in SDRAM without CPU interaction The user has to make sure that the reset to the first bin and the number of bins are issued with the accuracy that is required by the application I e no number of bin reset checking mechanism is implemented unlike in the SIS3100 HISCAL DSP based design Page 10 of 72 SIS Documentation SIS3820 SIS GmbH t VME Scaler VME 5 Getting started This section is intended for the first time SIS3820 user In some cases it may be good enough to use the provided header file and C examples to get acquainted to a couple of the modules functions before looking at the other sections of the manual in more detail If you have a SIS1100 3100 PCI to VME interface under LINUX or under Win2K XP with Visual C you can use the provided example code without modifications 5 1 Installation e Select addressing A32 or geographical address mode with J1 factory default is A32 e Select base address with SW3 and SW4 in non geographical addressing the default base address setting is 0x38000000 turn VME crate power off install your SIS3820 board in the VME crate connect inputs turn VME crate power back on verify that the P power and R ready LEDs are on and all other LEDs are off after the approximately 2s long power up self test cyc
39. e Ready R LED are on After the initialization phase is completed all LEDs except the Ready R LED and the Power P have to go off Differing behavior indicates either a problem with the download of the firmware boot file or one or more FPGAs and or the download logic Page 67 of 72 SIS Documentation SIS3820 SIS GmbH y VME Scaler VME 15 7 VME readout performance A SIS3820 can generate in excess of 128 MBytes s worth of data at the minimum dwell time with 32 channels active in 32 bit mode in principle A more realistic data rate in the short dwell time regime is 64 MBytes s as 8 bits counter depth will be sufficient to hold the maximum possible number of counts The VME interface was optimized with respect to the block transfer readout of this possible substantial amount of data Find below a table of block transfer speeds of the SIS1100 3100 PCI to VME interface on readout of data from the SDRAM of the SIS3820 The measurements were made with 40 longword blocks the speed was computed by dividing the number of bytes be the difference of the leading edge of the first DS1 and the trailing edge of the last DS1 Mode Transfer speed BLT32 25 MB s MBLT64 50 MB s 2e VME 88 MB s Note you have to be aware that the typical setup time for a block transfer is in the 25 us ballpark Le you will want to read out large blocks of data in high speed applications to minimize overhead 15 8 Software Support
40. ed upon SIS3820_KEY_RESET and SIS3820_KEY_SDRAM_FIFO_RESET e incremented on data being written to SDRAM FIFO in MCS mode or SDRAM FIFO VME write test mode e decremented when data are read from the memory by VME Note if you read the same data from SDRAM more than once in non FIFO mode the word counter will not reflect the actual fill level i e FIFO mode is the main word counter application SDRAM Address pointers non VME accessible In FIFO Mode e write and read pointers are reset upon SIS3820_KEY_RESET and SIS3820_ KEY SDRAM_FIFO_RESET e the write pointer is incremented upon SDRAM write cycles MCS mode e the read pointer is decremented upon SDRAM VME read cycles In SDRAM Mode e write and read pointers are reset upon SIS3820_KEY_RESET and SIS3820_ KEY SDRAM_FIFO_RESET e the write pointer is incremented upon SDRAM write cycles MCS mode e the read pointer is defined by the VME address An internal FIFO almost full flag which blocks further writes LNEs is generated in FIFO mode at 64 MBytes 512 words Data from up to two LNE cycles may be pipelined and still be written to memory at this point This condition reflects the error case and has to be avoided by readout in parallel to acquisition It is available as interrupt source 4 and has to be cleared with a SIS3820_KEY_SDRAM_FIFO_RESET Page 31 of 72 SIS Documentation SIS3820 SIS GmbH A VME Scaler VME 7 14 FIFO word counter threshold 0x3
41. elow All outputs can be inverted with the control outputs inverted bit of the same register Control Output Mode Output assignment Mode 0 output 5 gt Scaler mode LNE pulse MCS Mode CIP bit1 0 bit0 0 output 6 gt SDRAM empty output 7 gt SDRAM threshold output 8 gt User output Led Mode 1 output 5 gt Scaler mode LNE pulse MCS Mode CIP bit1 0 bit0 1 output 6 gt Enabled output 7 gt 50 MHz output 8 gt User output User LED Modes 2 to 3 reserved output 5 gt 0 output 6 gt 0 output 7 gt 0 output 8 gt 0 Note The user output is switched on and off with the same bit of the control register as the user LED 7 15 4 SDRAM mode This bit defines whether the the SIS3820 is operated in SDRAM or FIFO emulation mode SDRAM mode bit Mode 0 FIFO emulation 1 SDRAM Page 35 of 72 SIS Documentation SIS3820 SIS GmbH A VME Scaler VME 7 15 5 Arm enable source The two arm enable source bits define what signal the enable is derived from In channel N source mode the LNE channel register defines what scaler channel the enable signal is derived from Arm Enable Bit 1 Arm Enable Bit 0 Arm Enable source 0 0 LNE Front panel control signal 0 1 Channel N ChN 1 0 reserved 1 1 reserved Notes 1 be aware that the front panel control signal is active with input modes 1 2 and 3 only 2 ChN stands f
42. emporarily in non working condition JP570 has 3 pins Depending on whether pins 1 and 2 or 2 and 3 are closed the JTAG source is defined as listed below Closed JTAG source 1 2 VME 2 3 JTAG connector CON 500 11 4 CON500 JTAG The SIS3820 on board logic can load its firmware from a serial PROM The firmware can be upgraded through VME future option or the JTAG connector A list of firmware designs can be found under http www struck de sis3820firm htm Hardware like the XILINX HW JTAG PC in connection with the appropriate software the XILINX WebPACK is furnished on the accompanying CDROM will be required for in field JTAG firmware upgrades through the JTAG connector The JTAG connector is a 9 pin single row 1 10 inch header the pin assignment on the connector can be found in the table below Pin Short hand Description 1 VCC Supply voltage 2 GND Ground 3 nc not connected cut to avoid polarity mismatch 4 TCK test clock 5 nc not connected 6 TDO test data out 7 TDI test data in 8 nc not connected 9 TMS test modus Note close the J90 disable watchdog jumper for firmware upgrades Page 52 of 72 SIS Documentation SIS3820 SIS GmbH t VME Scaler VME 12 Input Configuration SIS36 38xx boards are available for NIM TTL ECL and LVDS input levels and in LEMO and flat cable versions The boards are factory configured for the specified input l
43. er SIS GmbH 4 VME 7 Register description The function of the individual registers is described in detail in this section The first line after the subsection header in Courier font like define SIS3820 CONTROL STATUS 0x0 read write D32 refers to the sis3820 h header file Page 18 of 72 SIS Documentation SIS3820 SIS GmbH i VME Scaler VME 7 1 Control Status Register 0x write read define SIS3820 CONTROL STATUS 0x0 read write D32 The control register is in charge of the control of some basic properties of the SIS3820 board like enabling test pulse generators It is implemented via a selective J K register a specific function is enabled by writing a 1 into the set enable bit the function is disabled by writing a 1 into the clear disable bit which location is 16 bit higher in the register An undefined toggle status will result from setting both the enable and disable bits for a specific function at the same time On read access the same register represents the status register Bit write Function read Function 31 Status external LATCH Bit2 depend from Input Mode 30 Status external LATCH Bitl depend from Input Mode 29 Status external Input Bit2 depend from Input Mode 28 Status external Input Bitl depend from Input Mode 27 Overflow 26 0 25 0
44. er nono none no non n arnein Aies ariasi a ien 29 7 12 SDRAM page register Us24 T e ie arie Ee EE Ei i aiea a iii 30 7 13 FIFO word counter memory address pointer register 0X38 sees 31 7 14 FIFO word counter threshold s i 32 7 15 Acquisition Operation Mode register OX 100 eceeceesseesseesceseeeseeeeeeseeeseceseeesecseeeeeseceseenaeenaeenaesaes 33 TAS 1 Modes of Operation Te TTT 33 G IE ee 34 D I e e ME Re 35 La SDRAM mode cia eier 35 TASS O IA ipa e ae E EE ta saben vee ibe do ude ool ogbee dea dace E E AEAEE Ri 36 TISO NTEINE SOULCE A NEO 36 b NR E EE EE 37 71538 Cle ring non EE 37 J 16 Copy disable register eh eege eegend hues dio dae 38 7 17 LNE channel select register 0X108 Juracie a t a E E a a 39 Page 3 of 72 SIS Documentation SIS3820 SIS GmbH VME Scaler VME 7 18 PRESET channel select register OX LOC see 40 TAg e E EE 40 7 19 Inhibit count disable register Us 2001 41 120 Counter clearregister SZ 22 Seege eo dotada Ee sued oth EEEE deed NEE dades de snsausdedanuaseads tuts 41 7 21 Counter Overflow register 0X208 eea conc nn a OKEE nn nn nn Se EEEE SEEE EE 41 122 One wire Td register tO cde scce cscaceceusds tees detec vent Ge sckd cd ta cuneate edaih ve0d dicte bat did di deste is da 42 7 23 FIFO address space Ox80000 OXFFFFFC asse eesceceseceesceceseeeeneeceseeesaeeceacessneeceeeeneeceeneeenaeceeeeeenaeeees 43 7 23 1 Non incrementing VME MASET ocioso sevens a Eed EEGEN
45. evel and connector type Input termination is installed 12 1 ECL The 100 Q input termination can be removed in groups of four channels by removing the corresponding resistor networks The termination of single control inputs can be disabled with jumpers J101 through J108 an open jumper disables the termination of the corresponding channel Network Channels 1 K Networks RN10 1 4 RN11 12 RN20 5 8 RN21 22 RN30 9 12 RN31 32 RN40 13 16 RN41 41 RN50 17 20 RN51 52 RN60 21 24 RN61 62 RN70 25 28 RN71 72 RN80 29 32 RN81 82 RN110 Control 1 4 RN111 RN112 RN120 Control 5 8 RN121 RN122 The schematics of the ECL input circuitry is shown below GND SIL RN 1 X1 SIL RN 1 X0 SIL RN 1 X2 Page 53 of 72 SIS Documentation SIS3820 SIS GmbH y VME Scaler VME 12 2 LVDS The 100 Q input termination can be removed in groups of four channels by removing the corresponding resistor networks The termination of single control inputs can be disabled with jumpers J101 through J108 an open jumper disables the termination of the corresponding channel Network Channels RN10 1 4 RN20 5 8 RN30 9 12 RN40 13 16 RN50 17 20 RN60 21 24 RN70 25 28 RN80 29 32 RN110 Control 1 4 RN120 Control 5 8 The schematics of the LVDS input circuitry is shown below SIL RN 1 X0 H Page 54 of 72 SIS Documentation SIS3820 SIS
46. ibit disable counting has to be present for the period you desire to disable counting An internal delay of some 15 ns has to be taken into account for all external signals 13 2 Inputs The SIS3820 is specified for counting rates of 250 MHz for ECL and NIM signals and 100 MHz for the TTL case Thus the minimum high and low level duration is 2 0 ns 5 ns respective Signal deterioration over long cables has to be taken into account 13 3 User Bits The status of the user bits is latched with the leading edge of the external LNE pulse A setup time of greater equal 10 ns and a hold time of 25 ns is required i e the signal should have a length of greater 35 ns and has to be valid 10 ns before the leading edge of the LNE pulse arrives User bit information is pipelined i e the information that is stored with the scaler values was recorded at the beginning of the counting period Page 57 of 72 SIS Documentation SIS3820 SIS GmbH A VME Scaler VME 14 Theory of operation 14 1 Enable Logic The logic of the SIS3820 is disabled by default upon power up of the module due to the execution of a key reset In a standard counter application a key enable command is all that is required to enable the logic in MCS or preset mode other signals like arm and LNE are contributing as shown in the enable logic schematic below The enable logic should not be mixed with the counter enable disable for the individual channels LNE enabled
47. ipate in a CBLT have to get the same CBLT address in the case of the SIS3820 the CBLT address is defined by the upper 8 bits of the CBLT setup register The module closest to the CPU has to be defined as First CBLT module the module at the end of the chain is defined as Last CBLT module All modules have to have their CBLT enable bit set the modules must occupy a contiguous set of VME slots as shown in the sketch below The token is passed from the previous module to the next module via the IRQ daisy chain lines as soon as all data have been read The last module in the chain terminates the transfer with a VME bus error BERR VME Crate Schematic CBLT setup Page 62 of 72 SIS Documentation SIS3820 SIS GmbH t VME Scaler VME 14 7 1 CBLT Setup example Assume 4 SIS3820 as shown in the crate above are supposed to participate in a CBLT The modules are set to D32 addressing and VME base address configuration as shown in the table below 0x45 is used as CBLT address and the CBLT setup registers of the three modules are configured as shown in the list Module number D32 base address VME slot CBLT setup register Comment 1 0x20000000 11 0x45000805 First Geo 1 CBLT enable 2 0x21000000 12 0x45001001 CBLT enable Geo 2 4 0x22000000 13 0x45001801 CBLT enable Geo 3 4 0x23000000 14 0x45002003 Last Geo 4 CBLT enable A BLT32 read from VME address 0x45000000 will result in
48. ister 1 of 32 0x10C R W D32 PRESET channel select register 2 times 1 out of 16 0x200 R W D32 Inhibit count disable register 0x204 W D32 Counter Clear register 0x208 R W D32 Counter Overflow read and clear register 0x20C R D32 Johnson error register SIS internal use future use R W One wire Id register future use R W XILINX JTAG future use R W SDRAM Prom 0x400 KA D32 broadcast Key reset 0x404 KA D32 broadcast Key SDRAM FIFO reset 0x408 KA D32 broadcast Key test pulse 0x414 KA D32 broadcast Key Counter Clr 0x410 KA D32 broadcast Key VME LNE clock shadow 0x414 KA D32 broadcast Key operation arm 0x418 KA D32 broadcast Key operation enable 0x41C KA D32 broadcast Key operation disable 0x800 to 0x87C R D32 BLT32 CBLT Shadow registers UX AUU to 0xA7C R D32 BLT32 CBLT Counter registers R D32 BLT32 CBLT FIFO address space in FIFO emulation mode 0x800000 to W D32 BLT32 SDRAM or FIFO space array Oxfififc address window for page of 8 Mbytes R D32 BLT32 MBLT64 2eVme CBLT32 Page 16 of 72 SIS Documentation SIS3820 SIS GmbH VME Scaler VME Note SDRAM FIFO respective write access with active MCS mode will result in a VME bus error In MCS mode the memory is reserved for storage of the counter values The shorthand KA stands for key address Write access with arbitrary data to a key address initiates the specified function Page 17 of 72 SIS Documentation SIS3820 VME Scal
49. le 5 2 LINUX example test code The file sis3820 tar gz holds 5 LINUX example programs the sis3820 h header file and a Makefile to generate the executables 5 3 Initial VME access test Both the user LED and readout of the Module Id and firmware register provide a good way to verify that proper initial communciation with the SIS3820 can be established 5 3 1 User LED test The program sis3820_led c runs 30 cycles with the sequence user LED on sleep 1 user LED off sleep 1 5 3 2 Readout of Module Id and firmware revision register The program sis3820_readmodid c reads and displays the module identification and firmware register mkiemki sis1100 sis3820 gt sis3820_readmodid Module identification and firmware register reads 38200101 Page 11 of 72 SIS Documentation SIS3820 VME Scaler SIS GmbH VME 5 3 3 Standard Counter In the minimum counter application you enable the logic have the module count for a period of time and read out the scaler values after disabling the logic The sis3820_counter program runs 2 counting cycles of 5 s each During the second cycle the internal 50 MHz reference pulse generator is routed to channel 1 Sample output with a 11 MHz signal connected to scaler channel 17 is shown below mkiemki sis1100 sis3820 gt sis3820 counter SIS3820 scaler counting gotwords 32 scaler data chol cho5 cho9 ch13 ch17 ch21 ch25 ch29 00000000 00000000 00000000 00000
50. n that case Format Bit 1 Format Bit 0 Data Format 0 0 32 bit 0 1 24 bit with user bit and channel information 1 0 16 bit 1 1 8 bit A more detailed description of the data formats is given in section 8 7 15 8 Clearing non clearing This bit decides whether the scaler values are cleared upon LNE clock shadow or whether the counter contents will be preserved and the accumulated counts will be stored to SDRAM to the shadow registers The power up mode defaults to clearing i e the number of counts since the last readout cycle will be stored to SDRAM to the shadow registers Refer to section 14 6 for a description of the function behavior internal counter logic Note The overflow logic generation of overflow IRQ e g is active in non clearing mode only Page 37 of 72 SIS Documentation SIS3820 SIS GmbH A VME Scaler VME 7 16 Copy disable register 0x104 define SIS3820 COPY DISABLE 0x104 read write D32 This read write register allows for exclusion of channels from the LNE MCS mode The full copy loop is executed in pattern mode Channels with their corresponding bit set in the copy disable register are excluded from the copy process The minimum dwell time depend on the number of active channels and the selected data format refer to section 14 2 for a table of measured minimum dwell times Bit Function 31 copy disable bit channel 32 0 copy disable
51. nnels can be selected as the condition for the termination of the counting process The selection of the channel s is done via the preset enable mask register The first selected channel that reaches its preset value will terminate the counting process The actual preset values are defined though the preset value register set The internal 25 MHz pulse generator or a prescaled derived output can be used as time base for measurements if its enabled for channel 1 with this channel being enabled in the preset enable mask and the desired prescale factor stored into the channel 1 preset value register The terminating channel can be identified by the actual scaler data or the preset hit mask register if more than one preset channel is enabled 4 2 4 Multi channel Scaler MCS MCS mode allows for the buffered readout of variable or fixed lengths counting time intervals The interval length can be defined by an internal timer as well as by an external signal which can be prescaled also The minimum buffer memory size of 64 MB takes the realtime burden away from the VME master even at very short time intervals dwell times Two factors facilitate short dwell time applications The first is high speed VME readout of data from SDRAM in MBLT64 and 2eVME The second is data compression with a reduction in counter depth to 16 or 8 bit Data compression is also a good way to save VME bandwidth in lower count rate applications with V F converters e g at longer
52. on numbers used reserved to date Major revision number Application user 0x01 Generic SIS3820 32 channel scaler design OxEO SIS3820 CLOCK OxFO SIS3820 LATCH Page 21 of 72 SIS Documentation SIS3820 SIS GmbH A VME Scaler VME 7 3 Interrupt configuration register 0x8 define SIS3820 IRQ CONFIG 0x8 read write D32 In conjunction with the interrupt control register this read write register controls the VME interrupt behaviour of the SIS3820 Eight interrupt sources are foreseen for the time being four of them are associated with an interrupt condition the others are reserved for future use The interrupter type is DOS 7 3 1 IRQ mode In RORA release on register access mode the interrupt will be pending until the IRQ source is cleared by specific access to the corresponding disable VME IRQ source bit After the interrupt is serviced the source has to be activated with the enable VME IRQ source bit again In ROAK release on acknowledge mode the interrupt condition will be cleared and the IRQ source disabled as soon as the interrupt is acknowledged by the CPU After the interrupt is serviced the source has to be activated with the enable VME IRQ source bit again ROAK IRQ mode can be used in conjunction with the University of Bonn LINUX Tundra Universe II driver by Dr Jiirgen Hannappel on Intel based VME SBCs
53. or the selected LNE channel 7 15 6 LNE source The three LNE source bits define what signal the LNE load next event signal is derived from In channel N source mode the LNE channel register defines what scaler channel the LNE signal is derived from LNE Bit 2 LNE Bit 1 LNE Bit U LNE source 0 0 0 VME key address only ignore front panel signals 0 0 1 Front panel control signal 0 1 0 10 MHz internal pulser 0 1 1 Channel N ChN 1 0 0 Preset Scaler N LNE sources can be prescaled with the LNE prescaler where needed The LNE prescaler is active 1f the prescale factor register is loaded with a non zero value Routed through prescaler if 0 LNE source no VME key address only ignore front panel signals yes Front panel control signal yes 10 MHz internal pulser yes Channel N ChN no Preset Scaler N Note The maximum input frequency for the channel N or front panel LNE is limited to 10 MHz Page 36 of 72 SIS Documentation SIS3820 SIS GmbH t VME Scaler VME 7 15 7 Data format The data format bits allow you to select between a straight 32 bit and a 24 bit mode with information from the two user inputs and channel information For low rate and or short dwell time environments data reduction and lower dwell times can be accomplished by reduction of the scaler depth to 16 bit or even 8 bit Two respective four scaler values are packed into one 32 bit word i
54. owing sequence has to be used 1 disable LNE prescaler write 0x0 to the LNE prescaler factor register 2 enable LNE prescaler by writing the new LNE prescale value to the LNE prescaler factor register The LNE prescale factor is given by register value 1 If the an output mode with CIP front panel output is enabled the CIP signal can be used to synchronise external hardware to the actual LNE pulses after prescaling Example If 9999 decimal is written to the LNE prescale factor register with the prescaler and the 10 MHz to prescaler enabled via bits 6 and 7 of the control register the scaler will get LNE pulses with a frequency of 1 KHz Following LNE sources are routed through the LNE prescaler if the prescale factor has a non zero value external LNE front panel signal internal 10 MHz channel N ChN Note This implies that software LNE pulses are not routed through the LNE prescaler they do always initiate a direct LNE readout cycle Page 27 of 72 SIS Documentation SIS3820 SIS GmbH A VME Scaler VME 7 8 Preset value register counter group 1 0x20 define SIS3820 PRESET GROUP1 0x20 read write D32 The preset value for channels 1 16 is defined by this register The preset channel select register is used to define which of the 16 channels of the group is actually compared to the preset value Bit Function 31 Preset bit 31 0 Preset bit 0 7 9 Preset
55. r frequencies in excess of some 7 MHz Above output was generated with a symmetric 15 MHz source e g Page 14 of 72 SIS Documentation SIS3820 SIS GmbH t VME Scaler VME 6 VME Addressing As the SIS3820 features memory options with up 512 Mbytes of SDRAM A32 addressing was implemented as the only option Hence the module occupies an address space of OxFFFFFF Bytes i e 16 MBytes The SIS3820 firmware addressing concept is a pragmatic approach to combine standard rotary switch style settings with the use of VME64x backplane geographical addressing functionality The base address is defined by the selected addressing mode which is defined by jumper array J1 and possibly SW4 and SW3 in non geographical mode Function EN_A32 reserved EN_GEO reserved Lf EN_A32 EN_GEO Description 0 non A32 addressing reserved for future use 1 non A32 addressing reserved for future use 0 A32 addressing address compared with SW3 SW4 1 A32 addressing address compared with geographical address 0 jumper open 1 jumper closed re l lll The table below illustrates the possible base address settings JI Setting Bits GEO 31 30 29 28 27 26 25 24 SW4 SW3 tlhalalale x al al al lA Al A OO GGG Shorthand _ Explanation SW3 SW4 _ Setting of ro
56. s is bigger than that boundary you may have to define several smaller CBLT setups which will then stay below the boundary e In many cases the block size will not be known as it may depend on the number of hits in an ADC or TDC In that case the user will have to setup a CBLT with the number of possible words and rely on the capability of a block transfer terminated by a VME bus error and a returned Byte count to indicate the actual length of the transfer e SIS3820 scalers will have their access LED lit as soon as the header word is passed to the VME bus in a CBLT This gives you an easy way to make sure that the modules are responding to an access to their CBLT address Page 64 of 72 SIS Documentation SIS3820 SIS GmbH i VME Scaler VME 15 Appendix 15 1 P2 row A C pin assignments The P2 connector of the SIS3820 in 64 channel or clock module configuration has connections on rows A and C to feed the second set of 32 inputs to the module or for operation as backplane clock distributor for the SIS330x digitizer family This implies that the module can not be operated in a VME slot with a special A C backplane like VSB e g The pin assignments of P2 rows A C of the SIS3820 for both scaler and clock module is shown below 32 channel versions do not make use of P2 rows A C P2A Scaler Function Clock Func
57. s non zero Acquisition is completed as soon as the acquisition count is greater or equal than the acquisition preset value Bit Function 31 bit 31 of acquisition count 0 bit O of acquisition count Page 26 of 72 SIS Documentation SIS3820 SIS GmbH t VME Scaler VME 7 7 LNE Prescaler factor register 0x18 define SIS3820 LNE PRESCALE 0x18 read write D32 The LNE prescale factor register allows you to prescale the front panel LNE pulse clock ticks from an angular encoder e g the internal 10 MHz pulse generator or the channel N ChN LNE source The prescale factor is a 32 bit value The second case above allows you to run the multiscaler with a fixed time slice length The register can be reprogrammed while the scaler acquires data as long as the user makes sure not to change the prescale factor while an internal reload is in progress The period between two CIP pulses is safe for reprogramming Programming the prescale factor to 0 results in routing the raw signal to the LNE If the LNE rate after the prescaler is higher than the possible maximum excess LNE pulses are ignored the CIP output allows you to monitor the accepted LNE pulses Bit Function 31 LNE prescale factor bit 31 0 LNE prescale factor bit 0 If the new prescale factor is supposed to have an immediate effect i e if the new prescale factor and the input rate are smaller than the previous setting foll
58. signals soft or hardware clear OVL Overflow red Signals Overlow in one or more channels S Scaler Enable green Signals one or more enabled channels VU VIPA user LED __ green for future use The LED locations are shown in the portion of the front panel drawing below AO OCLR POQow ROOS U O Ovu The VME Access Clear and Scaler enable LEDs are monostable i e the duration of the on phase is stretched for better visibility the other LEDs reflect the current status An LED test cycle is performed upon power up refer to the chapter 15 6 Page 47 of 72 SIS Documentation SIS3820 SIS GmbH A VME Scaler VME 9 3 Flat cable Input Output Pin Assignments 9 3 1 ECL Data Connector Channel 1 16 Data Connector Channel 17 32 PIN SIGNAL SIGNAL PIN PIN SIGNAL SIGNAL PIN 32 IN16 IN16 31 32 IN32 IN32 31 30 INIS IN15 29 30 IN31 IN31 29 28 IN14 IN14 27 28 IN30 IN30 27 26 IN13 IN13 25 26 IN29 IN29 25 24 IN12 IN12 23 24 IN28 IN28 23 22 IN11 IN11 21 22 IN27 IN27 21 20 IN1O IN10 19 20 IN26 IN26 19 18 INO IN9 17 18 IN25 IN25 17 16 IN8 INS 15 16 IN24 IN24 15 14 IN7 IN7 13 14 IN23 IN23 13 12 IN6 IN6 11 12 IN22 IN22 11 10 INS INS 9 10 IN21 IN21 9 8 IN4 IN4 H 8 IN20 IN20 7 6 IN3 IN3 5 6 IN19 IN19 3 4 IN2 IN2 3
59. tary switch SW3 or SW4 respective y don t care GAO GA4 _ Geographical address bit as defined by the VME64x P backplane Notes e This concept allows the use of the SIS3820 in standard VME as well as in VME64x environments i e the user does not have to use a VME64x backplane e The factory default setting is 0x38000000 i e SW4 3 SW3 8 EN_A32 closed and EN_GEO open disabled Page 15 of 72 SIS Documentation SIS3820 SIS GmbH A VME Scaler VME 6 1 Address map Offset R W Mode Function Register 0x0 R W D32 Control Status register 0x4 R W D32 Module Id and firmware revision register 0x8 R W D32 Interrupt configuration register OxC R W D32 Interrupt control status register 0x10 R W D32 Acquisition preset register 0x14 R D32 Acquisition count register 0x18 R W D32 LNE prescale factor register 0x20 R W D32 Preset value register counter group 1 1 to 16 0x24 R W D32 Preset value register counter group 2 17 to 32 0x28 R W D32 Preset enable and hit register 0x30 R W D32 CBLT Broadcast setup register 0x34 R W D32 SDRAM page register 0x38 R W D32 FIFO Word count register 0x3C R W D32 FIFO Word count threshold register 0x100 R W D32 Acquisition Operation mode register 0x104 R W D32 Copy disable register 0x108 R W D32 LNE channel select reg
60. ted to 10 MHz 2 An inhibit of the selected channel front panel or selective count disable is ignored Hint make sure to activate the channel N LNE source in the acquisition operation mode register Page 39 of 72 SIS Documentation SIS3820 SIS GmbH A VME Scaler VME 7 18 PRESET channel select register 0x10C define SIS3820 PRESET CHANNEL SELECT Ox10C read write D32 This read write register allows to define which of the 32 front panel scaler channels is used as LNE source in LNE channel N mode The LNE channel has to be selected before the counting process is started and can not be changed during acquisition The channels are divided into two groups of 16 channels each due to the architecture of the SIS3820 Bit Function 31 no function read as 0 20 no function read as 0 19 bit 3 of PRESET channel select group2 18 re 17 ba 16 bit 0 of PRESET channel select group2 15 no function read as 0 4 no function read as 0 3 bit 3 of PRESET channel select group 2 ES 1 ES 0 bit O of PRESET channel select group Example a setting of 0x00000004 selects channel 5 as preset ChN LNE source 7 18 1 Preset scheme The overall preset scheme of the SIS3820 scaler is illustrated below a stop condition f OR Scaler channel 32 AND Scaler channel 31 selected scaler channel preset value group 2
61. ter holds the information on which channel has run into overflow condition On write access to this register the overflow bits of each channel can be cleared individually by the setting of the corresponding bit Bit write Function read Function 31 1 clear overflow bit of channel 32 Status of Overflow bit of channel 32 0 1 clear overflow bit of channel 1 Status of Overflow bit of channel 1 Page 41 of 72 SIS3820 VME Scaler SIS Documentation SIS GmbH A VME 7 22 One wire Id register tbd not implemented in 3820 01 01 firmware define SIS3820_ONE WIRE Oxtbd read write D32 A DS2430 256 Bit 1 wire EEPROM is installed on the SIS3820 to store the serial number of the module This information is stored in the 64 bit application register of the DS2430 in the factory Offset Contents Example SIS3820 64 SN 10 b Module Id oe 2 SDRAM _ 0x00 3 size 0x64 4 0x00 5 Serial 0x00 6 Number 0x00 7 Ox0A Note Module Id and SDRAM size are stored in hexadecimal form for better readability the serial number is stored as straight 32 bit decimal value Refer to the PDF data sheet of the DS2430 and the LINUX example program rom_read c on the SIS3820 documentation CDROM for details on the operation of the EEPROM Bit Read function Write f
62. tion P2C Scaler Function Clock Function 1 not connected 5 2 V 1 not connected 5 2 V 2 not connected 5 2 V 2 not connected 5 2 V 3 not connected 5 2 V 3 not connected 5 2 V 4 not connected notconnected 4 not connected not connected 5 not connected not connected 5 not connected not connected 6 DGND DGND 6 DGND DGND 7 Control 1 Pi CLOCK H 7 Control 0 Pi CLOCK L 8 DGND DGND 8 DGND DGND 9 Control 3 P2 START H 9 Control 2 P2 START L 10 Control 5 Pi STOP H 10 Control 4 P2 STOP lL 11 Control 7 Pi TEST H 11 Control 6 P2_TEST_L 12 DGND DGND 12 DGND DGND 13 DGND DGND 13 DGND DGND 14 G34_L16 not connected 14 G34_L15 not connected 15 G34_L14 not connected 15 G34_L13 not connected 16 G34_L12 not connected 16 G34_L12 not connected 17 G34_L10 not connected 17 G34_L9 not connected 18 G34_L8 not connected 18 G34_L7 not connected 19 G34_L6 not connected 19 G34_L5 not connected 20 G34_L4 not connected 20 G34_L3 not connected 21 G34_L2 not connected 21 G34_L1 not connected 22 DGND DGND 22 DGND DGND 23 G12 L16 not connected 23 G12_L15 not connected 24 G12_L14 not connected 24 G12_L13 not connected 25 G12_L12 not connected 25 G12 Lil not connected 26 G12_L10 not connected 26 G12_L9 not connected 27 G12_L8 not connected 27 G12_L7 not connected 28 G12_L6 not connected 28 G12_L5 not connected 29 G12_L4 not connected 29 G12_L3 not connected 30 G12_L2 not connected 30 G12_L1 not connected 31 DGND DGND 31
63. tion SIS3820 SIS GmbH t VME Scaler VME 11 Jumper settings pinouts The SIS3820 has 3 jumper fields and a JTAG connector Jumper field Function Jl J90 JP570 JTAG source CON500 JTAG connector The first pin of the jumper fields is marked by a square pin on the solder side and an extra frame on the silk screen of the component side 11 1 J1 J1 is in charge of the VME addressing mode At this point in time the user can select between rotary switch selected A32 addressing and geographical A32 addressing A closed position selects the corresponding function Function EN_A32 reserved EN_GEO reserved Lt The default setting is EN_A32 closed and all other positions opened 11 2 J90 J90 controls the reset behavior of the SIS3820 Function J90 reserved connect VME reset to SIS3820 reset reserved disable watchdog The default setting is VME reset closed and all other positions opened Note close the disable watchdog for firmware upgrades Page 51 of 72 SIS Documentation SIS3820 SIS GmbH A VME Scaler VME 11 3 JP570 JTAG source Firmware can be loaded to the XC18V04 serial PROM via a JTAG download cable XILINX JTAG PC4 e g or via the VME interface of the SIS3830 Please note that errors during this process can render a module t
64. trol in and outputs are grouped to one 8 channel block and the counter inputs are grouped into 2 blocks of 16 channels A mixed LEMO control flat cable counter input version is available also The units are 4 TE one VME slot wide the front panel is of EMC shielding type VIPA extractor handles are available on request or can be retrofitted by the user if he wants to change to a VIPA crate at a later point in time In the drawing below you can find the flat cable left hand side the LEMO control flat cable input middle and LEMO front panel layouts Note Only the aluminium portion without the extractor handle mounting fixtures is shown SIS GmbH CONTROL CONTROL 8 7 a RENTER CONTROL 1 0 SIS GmbH DATA SIS36 38xx SIS36 38xx d l 16 he DATA Page 46 of 72 SIS Documentation SIS3820 VME Scaler SIS GmbH t VME 9 2 Front Panel LEDs The SIS3820 has 8 front panel LEDs to visualize part of the units status Three LEDs according to the VME64xP standard Power Access and Ready plus 5 additional LEDs VME user LED Clear Overflow Scaler enable and VIPA user LED Designation LED Color Function A Access yellow Signals VME access to the unit P Power red Flags presence of VME power R Ready green Signals configured logic U VME user LED green To be switched on off under user program control CLR Clear yellow MCS mode signals LNE Latching scaler
65. unction 31 0 not used 16 0 not used 15 BUSY cmd RESET 14 Present cmd WRITE 13 0 cmd READ 12 0 reserved 11 0 reserved 10 0 reserved 9 reserved reserved 8 reserved reserved 7 read datum bit7 write datum bit7 6 read datum bit6 write datum bit6 5 read datum bit5 write datum bit5 4 read datum bit4 write datum bit4 3 read datum bit3 write datum bit3 2 read datum bit2 write datum bit2 1 read datum bit write datum bt 0 read datum bt write datum bt Page 42 of 72 SIS Documentation SIS3820 SIS GmbH t VME Scaler VME 7 23 FIFO address space 0x80000 0xFFFFFC define SIS3820 FIFO BASE 0x800000 read only D32 BLTs Scaler data can be read from the FIFO address space in FIFO emulation mode Both single cycle D32 and block transfer modes BLT32 MBLT64 2e VME are supported The FIFO address space spans 2048 Bytes or 512 long words to allow for block transfer with auto address incrementing VME masters A VME bus error BERR is driven actively by the SIS3820 1f you attempt to read from an empty FIFO 7 23 1 non incrementing VME master With a non auto incrementing VME master like the SIS3100 in FIFO mode e g you can read an arbitrary amount of data typically defined by the current value of the FIFO word counter register in one block transfer from the first address of the FIFO address space Blocking into smaller blockletts is handled by the hardware without user intervention This results in optimum VME
66. used as interrupt source As an alternative you can poll on the preset reached bit in the preset enable and hit register to check on the occurrence of the preset reached condition Preset scaling can be used as LNE source in multi channel scaling channel N mode also It will take in the order of 140 ns after the preset condition was detected before the counters will stop counting This implies that the actual stored counter value will be greater than the preset value for frequencies in excess of some 7 MHz Page 59 of 72 SIS Documentation SIS3820 SIS GmbH y VME Scaler VME 14 5 Multiscaling MCS Multi channel or multiscaling is a method to decouple the realtime behavior of fast counting processes from the VME readout process Data are buffered in an onboard memory and readout at a later point in time in an asynchronous fashion The SIS3820 uses standard 168 pin SDRAM memory strips as buffer the default size is 64 MBytes The memory can be used in e SDRAM mode e FIFO mode While SDRAM mode fits applications with a known number of acquisition cycles that will fit into the SDRAM strip completely FIFO mode allows for the sustained acquisition of measurements of an arbitrary number of readout cycles under the assumption that the VME master is capable of digesting the generated data rate The time slices or load next event LNE cycles can be defined by following processes e VME LNE e external LNE signal e internal 10 MH
67. value register counter group 2 0x24 define SIS3820 PRESET GROUP2 0x24 read write D32 The preset value for channels 17 32 is defined by this register The preset channel select register is used to define which of the 16 channels of the group is actually compared to the preset value Bit Function 31 Preset bit 31 0 Preset bit 0 7 10 Preset Enable and Hit register 0x28 define SIS3820 PRESET ENABLE HIT 0x28 read write D32 This register is used to enable one or both counter groups for preset operation and get the information which group has reached the preset value Bit write Function read Function 18 LNE latched preset reached status group 2 0 channel group 2 has not reached preset value 1 channel group 2 has reached preset value 17 preset reached status group 2 0 channel group 2 has not reached preset value 1 channel group 2 has reached preset value 16 ENABLE group 2 Status ENABLE group 2 2 LNE latched preset reached status group 1 0 channel group 1 has not reached preset value 1 channel group 1 has reached preset value 1 preset reached status group 1 0 channel group 1 has not reached preset value 1 channel group 1 has reached preset value 0 ENABLE group 1 Status ENABLE group 1 At power up or after key reset the register the register will read 0 Page 28 of 72 SIS Documentation SIS3820 SIS GmbH l VME Scaler VME
68. ware version 3820 01 01 Following functions are foreseen for future implementation but not part of the initial 01 01 SIS3820 design yet e Firmware upgrade from VME CBLT Histogramming scaler add mode One wire Id support Support for 512 and 1024 MB memory strips The firmware can be readily upgraded in field at a later point in time Page 7 of 72 SIS Documentation SIS3820 SIS GmbH 4 VME Scaler VME 3 Technical Properties Features This manual describes the implemented functionality for the SIS3820 SCALER firmware Other firmware designs are SIS3820 CLOCK clock distributor for up to 32 SIS330x VE digitizers and SIS3820 LATCH input register with counter and interrupt functionality Find below a list of key features of the SIS3820 32 channels 64 channel option 4 front panel control inputs 4 front panel control outputs 64 Mbytes SDRAM 512 1024 MB option 250 MHz counting rate ECL and NIM 100 MHz for TTL 50 MHz for P2 fed channels 32 bit counter depth NIM TTL ECL LVDS versions flat cable ECL TTL and LVDS and LEMO TTL NIM options multi channel latching and preset scaler operation shadow register latching scaler mode read on the fly latching scaler mode reference pulser test pulser A24 32 D32 BLT32 MBLT64 2e VME CBLT Geographical addressing mode in conjunction with VME64x backplane Interrupt capabilities Hot swap in conjunction with VME64x backplane VME64x Connectors VME64x Si
69. y REENEN 35 Po WE E EE leith 47 SDRAM dhreshold AAA 35 Cd ein pia 67 ONO 35 Re e e oo 47 EEN 41 S 13 selena 67 E UE e 11 19 1 EE 66 LED access 64 Fee EE abs 66 EEMO ios tiara 67 PIN ASSISNMENtS 51h oes Geter et 65 lev l Sensitive anna are R EE 24 BER gengt bd 66 LINUX E sev esise eae cat frotis 22 Pin Assignmentt sies et opatere 48 LINUX example test code 11 VN aT en aeea Ce deed 67 I L T 66 67 power CONSUMPTION c cccccocccnconcnnnononnnoncnnninnnnncnncnnon 67 LNE ais vis dins 10 26 34 57 59 61 69 preset sealei e gege Zeie saves iena 10 14 36 T T 34 preset scaling tia ieee 59 ENE prescalet ener iii 36 UK 40 LNE SOUTO ee ee ceda cda 36 PROM sio ic ses 9 52 LV DS A EE D eg tenia Meee hs 54 R ag read on the linia inane ils 59 LE ENK E 8 10 30 68 reference PULSED niire iie 20 ME Sii 10 30 60 register mode acquisition Count sees ee eee 13 26 e e 45 acquisition mode 33 39 DA e eons 44 acquisition Dreset see eee 13 24 26 27 SR ee EE 44 address pointer ee eee 31 32 EE 45 CBET SEUD TEE 16 62 63 channel Noreen herinni ek eege 39 40 CBLT broadcast setup sss sese sese ee eee 20 Clear EE EE 37 61 COMO iaa 21 BURG Sucia pia iii 60 Te TT scria ie 38 FIFO emulation eee eee 29 35 43 FIFO threshold erac aiaa OUEZ O at Y O 24 UD DEER 34 61 FIFO word conter 31 32 43 latching Scaer eee eee ee 47 firmware revision sse ee eee eee 21 MES dree Ser 13 24 26 38 47 58 Do tia 41 multiscal dica g Eder e 24 interrupt
70. z pulse generator e channel N as preset scaler The later three can be routed through a prescaler 14 5 1 Minimum dwell time Find below a table with minimum dwell times for a number of configurations Number of channels Channel depth bits Dwell time in ns 32 32 960 16 32 500 8 32 340 32 16 660 16 16 340 8 16 260 32 8 500 16 8 260 8 8 220 Please note that a depth of 8 bits i e 0 255 counts is by far sufficient to hold all counts that can occur at the maximum count rate and minimum dwell time The minimum dwell time for a given configuration can be measured on the CIP output with output mode 1 and 2 Page 60 of 72 SIS Documentation SIS3820 SIS GmbH t VME Scaler VME 14 5 2 arm enable with MCS 14 5 2 1 enable Use the key operation enable command for multiscaling with an internal time base prescaled internal 10 MHz pulse generator e g like in the sis3820_mcs example program The first time slice counting period will have the same length as consecutive slices this way 14 5 2 2 arm Use the key operation arm command for multiscaling with an external time base LNE source By means of the arm enable source bits of the operation mode register you can define whether the actual enable will be defined by the LNE front panel signal with input mode 1 2 or 3 active or the ChN source This way your first time slice counting period will have the same lengths

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