SuperTM Family E10A-USB Emulator Additional Document for
Contents
1. Nippon Bldg 2 6 2 Ohte machi Chiyoda ku Tokyo 100 0004 Japan 2CENESAS RENESAS SALES OFFICES http www renesas com Refer to http www renesas com en network for the latest and detailed information Renesas Technology America Inc 450 Holger Way San Jose CA 95134 1368 U S A Tel lt 1 gt 408 382 7500 Fax lt 1 gt 408 382 7501 Renesas Technology Europe Limited Dukes Meadow Millboard Road Bourne End Buckinghamshire SL8 5FH U K Tel lt 44 gt 1628 585 100 Fax lt 44 gt 1628 585 900 Renesas Technology Shanghai Co Ltd Unit 204 205 AZIACenter No 1233 Lujiazui Ring Rd Pudong District Shanghai China 200120 Tel lt 86 gt 21 5877 1818 Fax lt 86 gt 21 6887 7858 7898 Renesas Technology Hong Kong Ltd 7th Floor North Tower World Finance Centre Harbour City Canton Road Tsimshatsui Kowloon Hong Kong Tel lt 852 gt 2265 6688 Fax lt 852 gt 2377 3473 Renesas Technology Taiwan Co Ltd 10th Floor No 99 Fushing North Road Taipei Taiwan Tel lt 886 gt 2 2715 2888 Fax lt 886 gt 2 3518 3399 Renesas Technology Singapore Pte Ltd 1 Harbour Front Avenue 06 10 Keppel Bay Tower Singapore 098632 Tel lt 65 gt 6213 0200 Fax lt 65 gt 6278 8001 Renesas Technology Korea Co Ltd Kukje Center Bldg 18th FI 191 2 ka Hangang ro Yongsan ku Seoul 140 702 Korea Tel lt 82 gt 2 796 3115 Fax lt 82 gt 2 796 2145 Renesas Technology Malaysia Sdn Bhd2. Trace type group box of the Trace mode page In this function write the trace data in the specified user memory range Specify the start address to output a trace for the Start edit box in the User memory area group box and the end address for the End Address edit box Set the trace condition to be used Table 2 9 shows the memory output trace acquisition mode that can be set in each trace function Table 2 9 Memory Output Trace Acquisition Mode Type Mode Description Continuous Realtime trace trace occurs When the next branch occurs while the trace information is being output all the information may not be output The user program can be executed in realtime but some trace information will be lost Non realtime trace When the next branch occurs while the trace information is being output the CPU stops operations until the information is output The user program is not executed in realtime Trace buffer Trace continue full This function overwrites the oldest trace information to store the latest trace information Trace stop After the trace buffer becomes full the trace information is no longer acquired The user program is continuously executed Rev 1 00 Mar 03 2010 Page 25 of 40 RENESAS REJ10J2105 0100 Section 2 Software Specifications when Using the SH4AL DSP_custom_SoC To set the memory output trace acquisition mode click the Trace window with the right mouse button and se
3. Unit 906 Block B Menara Amcorp Amcorp Trade Centre No 18 Jin Persiaran Barat 46050 Petaling Jaya Selangor Darul Ehsan Malaysia Tel lt 603 gt 7955 9390 Fax lt 603 gt 7955 9510 Colophon 6 2 SuperH Family E10A USB Emulator Additional Document for User s Manual Supplementary Information on Using the SH4AL DSP_custom_SoC 2tENESAS Renesas Electronics Corporation 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan REJ10J2105 0100
4. compliance could void the user s authority to operate the equipment Rev 1 00 Mar 03 2010 Page v of vi RENESAS REJ10J2105 0100 Contents Section 1 Connecting the Emulator with the User System eens 1 1 1 Components of the Emulator ee cceeceeeeeeescesecesecesecsaecsaecaeeseeeeeeeeeeeseesseesaeesaeenaes 1 1 2 Connecting the Emulator with the User System eee ceeeeeeeeeeeeceeeeeseceseenseenaeenaes 3 1 3 Installing the H UDI Port Connector on the User System eee eeeeeeeeseeeseeeseeees 4 1 4 Pin Assignments of the H UDI Port Connector eee ceeeceeeeeeeeceeeeeseeeseesaeenseenaes 4 1 5 Recommended Circuit between the H UDI Port Connector and the MPU 4 Section 2 Software Specifications when Using 2 1 2 2 the SH4AL DSP_custoOMm_SOC ccceccccccccccecessessnsecececeeeesessnteeeeeeees 5 Differences between the SH4AL DSP_custom_SoC and the Emulator 0 ce 5 Specific Functions for the Emulator when Using the SH4AL DSP_custom_SoC 9 2 2 1 Event Condition Functions ccccccccccecessssseceeececsesssaececccecsenssaeceeeceesessseeeeeeeees 9 2 2 2 Trace FUnCtOms ennet E E sea ene a E E EA E EE O 17 2 2 3 Notes on Using the JTAG H UDI Clock TCK and AUD Clock AUDCK 27 2 2 4 Notes on Setting the Breakpoint Dialog BOX ssssssesssssessseeesssreeresrerreresreesssesees 27 2 2 5 Notes on Setting the Event Condition Dialog Box and the BREAKCONDITION_ SET Command
5. executing a program and ended when an event condition is satisfied When only the measurement start or end condition is specified performance cannot be measured Be sure to specify both of the measurement start and end conditions When the measurement start end conditions are specified step operation cannot be performed In addition when execution is restarted from the address where step operation has been stopped by the break conditions of BREAKPOINT or Event Condition step functions are used and operation is disabled Restart execution after the settings of the break conditions of BREAKPOINT or Event Condition have been canceled It is not possible to specify the break conditions and the measurement start end conditions at the same time with one channel If the measurement start end conditions are specified the settings of the break conditions will be disabled Table 2 10 Conditions Specified in the Action Page Item Description PA1 pai1_start_point Specifies the conditions of Event Condition that has been set as the measurement start condition of performance channel 1 pai_end_point Specifies the conditions of Event Condition that has been set as the measurement end condition of performance channel 1 PA2 pa2_start_point Specifies the conditions of Event Condition that has been set as the measurement start condition of performance channel 2 pa2_end_point Specifies the conditions of Event Condition that has been set as
6. lt mode gt of the PERFORMANCE_SET command They are displayed in CONDITION of the Performance Analysis window Rev 1 00 Mar 03 2010 Page 32 of 40 REJ10J2105 0100 RENESAS Section 2 Software Specifications when Using the SH4AL DSP_custom_SoC Table 2 11 Measurement Items Classification Type Measurement litem Option Note Disabled None Not measured CPU Cycle Elapsed cycles AC Except for power on period performance counted by the CPU clock Cycles executed in PM The number of privileged privileged mode mode cycles among the number of elapsed cycles Cycles for asserting BL The number of cycles when the SR BL bit the SR BL bit 1 among the number of elapsed cycles Instruction Number of effective The number of execution instructions issued instructions number of valid instructions issued number of cases of simultaneous execution of two instructions The number of valid instructions means the number of completed instructions Number of 2 2l The number of times that two instruction executed instructions are executed simultaneously simultaneously among the valid instructions issued Branch Number of BT The number of unconditional unconditional branch branches other than branches occurring after an exception However RTE is counted Exception Number of EA Interrupts are included interruption exceptions accepted Number of interrupts INT NMI is included accepted Number of UBC UBC Perfo
7. Breaks when the device address bus value or the program counter value matches the specified value Data bus condition Data Breaks when the device data bus value matches the specified value Byte word or longword can be specified as the access data size Bus state condition Bus State There are two bus state condition settings Bus state condition Breaks or acquires a trace when the data bus or the X Bus or Y Bus address bus of the device is matched Read Write condition Breaks or acquires a trace when the specified read write condition is matched Window address condition Breaks or acquires a trace when the data in the specified memory range is accessed System bus Breaks or acquires a trace when the address or data on the system bus is matched LDTLB instruction event condition Breaks when the device executes the LDTLB instruction Count Breaks when the conditions set are satisfied the specified number of times Branch trace condition Branch trace Breaks or acquires a trace when a branch occurs with the condition specified by the device By default trace acquisition is enabled Software trace Selects whether or not the software trace is acquired Action Selects the operation when a condition such as setting a break trace or performance start or end is matched Table 2 4 lists the combinations of conditions that can be set under Ch1 to Ch12 and the softw
8. Ch1 Rev 1 00 Mar 03 2010 Page 12 of 40 REJ10J2105 0100 RENESAS Section 2 Software Specifications when Using the SH4AL DSP_custom_SoC Table 2 5 Sequential Event Conditions cont Type Event Condition Description CPU CPU Extend Expands the CPU Sequential Extend page Sequential The sequential setting is enabled with any Event Page combination cont For details refer to section 2 2 1 Sequential Break Extension Setting in this manual SystemBus System Bus Ch9 gt 8 Sequential Sequential Event Page Event Halts a program when a condition is satisfied for Event Condition 9 8 An event condition must be set for Ch9 and Ch8 Ch8 gt 9 Halts a program when a condition is satisfied for Event Condition 8 9 An event condition must be set for Ch8 and Chg System Bus Extend Expands the System Bus Sequential Extend page The sequential setting is enabled with any combination For details refer to section 2 2 1 Sequential Break Extension Setting in this manual Rev 1 00 Mar 03 2010 Page 13 of 40 7tENESAS REJ10J2105 0100 Section 2 Software Specifications when Using the SH4AL DSP_custom_SoC Sequential Break Extension Setting Sequential setting CPU Sequential Event SystemBus Sequential Event CPU Sequential Extend Chi 1A_OA PreHit Channel Ch2UA OA DT_CT 7 CPU Match flag Match flag set gt 1 7 Ch2 A_OA_DT_CT PreHit Channel No Select X CPU Match flag
9. Condition Branch Software Box Address Data ASID Status address Bus Break Count Trace Trace Action Event O X X X X O X X X X O Condition B T 9 dialog and P box Event O X O O X xX X X X X O Condition B and 10 dialog P box Event O O oO O X X X O X X O Condition B and 11 dialog P box Event X X X X X X X X O X O Condition B T 12 dialog and P box Software X X X X X X X X X O Trace trace fixed dialog box Notes 1 O Can be setin the dialog box X Cannot be set in the dialog box 2 For the Action item B Setting a break is enabled T Setting a trace is enabled P Setting a performance start or end condition is enabled 7tENESAS Rev 1 00 Mar 03 2010 Page 11 of 40 REJ10J2105 0100 Section 2 Software Specifications when Using the SH4AL DSP_custom_SoC Sequential Setting In the emulator sequential Table 2 5 Sequential Event Conditions Type Event Condition setting of an Event Condition is enabled Description CPU 2 Channel Ch2 gt 1 Sequential Sequential Event Page Halts a program when a condition is satisfied in the order of Event Condition 2 1 An event condition must be set for Ch2 and Ch1 Ch4 gt 3 Halts a program when a condition is satisfied in the order of Event Condition 4 3 An event condition must be set for Ch4 and Ch3 Ch6 gt 5 Halts a program when a condition is satisfied in the order of Event Condition 6 5 An event condition mu
10. Power States Sleep Software Standby Module Standby and R Standby Low power consumption states consist of the sleep software standby module standby and R standby states The sleep software standby and R Standby states are switched using the SLEEP instruction When the emulator is used the sleep and software standby states can be cleared with either the normal clearing function or with the STOP button and a break will occur The power for some areas is turned off in R standby state and turned on in using the emulator Note The memory must not be accessed or modified in low power state using the SLEEP instruction 4 Reset Signal The reset signal of the device is only valid during emulation started by clicking on the GO button or STEP type button Accordingly the reset signal is not input to the device while the emulator is in the command input wait state Note Do not break execution of the user program while the reset bus release request or wait control signal is active Doing so will lead to a TIMEOUT error If the bus release request or wait control signal is fixed to the active level during a break in execution access to memory will cause a TIMEOUT error 5 Direct Memory Access Controller DMAC The DMAC operates even when the emulator is used When a data transfer request is generated the DMAC executes DMA transfer 6 Memory Access during User Program Execution When a memory is accessed from the memory window etc duri
11. REJ10J2105 0100 7tENESAS Section 2 Software Specifications when Using the SH4AL DSP_custom_SoC To set the AUD trace acquisition mode click the Trace window with the right mouse button and select Setting from the pop up menu to display the Acquisition dialog box The AUD trace acquisition mode can be set in the Trace Mode 1 or Trace Mode 2 group box in the Trace Mode page of the Acquisition dialog box Acquisition Trace Mode Trace type a AUD trace Internal trace C User Memory trace Trace Mode 1 Realtime trace C Non realtime trace Trace Mode 2 Trace continue Trace stop AUD Mode Abit C apit AUD trace display range Start pointer D255 End pointer D o User memory area abet ht H C End Address IHS Trace Extend Mode IT Trace data with PPC oree Figure 2 6 Trace Mode Page Rev 1 00 Mar 03 2010 Page 23 of 40 7tENESAS REJ10J2105 0100 Section 2 Software Specifications when Using the SH4AL DSP_custom_SoC Notes on AUD Trace 1 When the trace display is performed during user program execution the mnemonics operands or source is not displayed The AUD branch trace function outputs the differences between newly output branch source addresses and previously output branch source addresses The window trace function outputs the differences between newly output addresses and previously output address
12. c cc cccccccceeessssececececeesenssceeeeees 29 2 2 6 Note on Setting the UBC_MODE Command eee ceeceeseeeeeeeeeneeceteeeeneeenenes 29 2 2 7 Note on Setting the PPC_MODE Command ou eee eeeeeeeneceeeeeeneeceteeeeeeeneees 29 2 2 8 Performance Measurement Function ccccccccseessssececececeessnnceeececsessaeseeeeeees 30 Rev 1 00 Mar 03 2010 Page vi of vi REJ10J2105 0100 RENESAS Section 1 Connecting the Emulator with the User System Section 1 Connecting the Emulator with the User System 1 1 Components of the Emulator The E10A USB emulator supports the SH4AL DSP_custom_SoC Table 1 1 lists the components of the emulator Rev 1 00 Mar 03 2010 Page 1 of 40 RENESAS REJ10J2105 0100 Section 1 Connecting the Emulator with the User System Table 1 1 Components of the Emulator Classi Quan fication Component Appearance tity Remarks Hard Emulator box HS0005KCU01H ware Depth 65 0 mm Width 97 0 mm Height 20 0 mm Mass 72 9 g or HS0005KCU02H Depth 65 0 mm Width 97 0 mm Height 20 0 mm Mass 73 7 g User system interface gt 1 14 pin type cable Length 20 cm Mass 33 1 g User system interface 1 36 pin type cable Length 20 cm Mass 49 2 g only for HSOOO5KCU02H USB cable 1 Length 150 cm Mass 50 6 g Soft E10A USB emulator setup 1 HSO0005KCU01SR ware program CSD SuperH Family E10A HS0005KCU01HJ USB Emulator Users HS0005KCU01HE Manual Supplementary HS
13. cache miss read READ however the number of wait cycles of cache FIll is included due to contention Waited cycles for WCMW The number of wait cycles by operand cache miss an operand cache miss write WRITE Waited cycles for L WILR The number of wait cycles by I access READ L memory access READ of an operand Waited cycles for L WILW The number of wait cycles by I access WRITE L memory access WRITE of an operand Rev 1 00 Mar 03 2010 Page 37 of 40 RENESAS REJ10J2105 0100 Section 2 Software Specifications when Using the SH4AL DSP_custom_SoC Table 2 11 Measurement Items cont Classification Type Measurement item Option Note System bus System bus Number of requests RQ The number of valid bus cycles performance cells is counted by the only available system bus clock for Ch3 and Ch4 Number of RS responses The number of valid bus cycles cells is counted by the system bus clock Waited cycles for WRQ request The cycles for an issued request req that no acceptance signal gnt is issued to are counted by the system bus clock Even if the waits are issued simultaneously for multiple requests they are counted as 1 Waited cycles for WRS response The cycles for an issued response r_req that no acceptance signal r_gnt is issued to are counted by the system bus clock Even if the waits are issued simultaneously for multiple requests they are counted
14. information can be acquired in realtime The window trace function is also supported for acquiring memory access in the specified range memory access address or memory access data by tracing 2 14 pin type without AUD function The AUD trace function cannot be used because only the H UDI function is supported Since the 14 pin type connector is smaller than the 36 pin type 1 2 5 the size of the area where the connector is installed on the user system can be reduced Rev 1 00 Mar 03 2010 Page 3 of 40 RENESAS REJ10J2105 0100 Section 1 Connecting the Emulator with the User System 1 3 Installing the H UDI Port Connector on the User System Table 1 3 shows the recommended H UDI port connectors for the emulator Table 1 3 Recommended H UDI Port Connectors Connector Type Number Manufacturer Specifications 36 pin connector DX10M 36S Hirose Electric Co Ltd Screw type DX10M 36SE Lock pin type DX10G1M 36SE 14 pin connector 2514 6002 3M Limited 14 pin straight type Note When designing the 36 pin connector layout on the user board do not connect any components under the H UDI connector When designing the 14 pin connector layout on the user board do not place any components within 3 mm of the H UDI port connector 1 4 Pin Assignments of the H UDI Port Connector For the pin assignments of the 36 pin and 14 pin H UDI port connectors ask Renesas Technology Corp via a sales office 1 5 Recommended Circuit betwee
15. no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp its affiliated companies and their officers directors and employees against any and all damages arising out of such applications 9 You should use the products described herein within the range specified by Renesas especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges 10 Although Renesas endeavors to improve the quality and reliability of its products IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Please be sure to implement safety measures to guard against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other applicable measures Among others since the evaluation of microcomputer software alone is very difficult please evaluate the
16. on the Source or Disassembly window by refreshing the Memory window etc after Go execution However no break will occur at this address When the program halts with the event condition the mark disappears 2 2 5 Notes on Setting the Event Condition Dialog Box and the BREAKCONDITION_ SET Command 1 When Go to cursor Step In Step Over or Step Out is selected the settings of Event Condition 3 are disabled 2 When an Event Condition is satisfied emulation may stop after two or more instructions have been executed 3 Ifa PC break address condition is set to the slot instruction after a delayed branch instruction user program execution cannot be terminated before the slot instruction execution execution stops before the branch destination instruction 2 2 6 Note on Setting the UBC_MODE Command In the Configuration dialog box if User is set while the UBC mode list box has been set Ch10 CA_OA_R and Ch11 OA_OA_CT_R of Event Condition cannot be used 2 2 7 Note on Setting the PPC_MODE Command In the Configuration dialog box if User is set while the PPC mode list box has been set Ch1 and Ch2 of the performance analysis function and options 1 and 2 of the profile function cannot be used Rev 1 00 Mar 03 2010 Page 29 of 40 RENESAS REJ10J2105 0100 Section 2 Software Specifications when Using the SH4AL DSP_custom_SoC 2 2 8 Performance Measurement Function The emulator supports the performanc
17. safety of the final products or system manufactured by you 11 In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed the risk of accident such as swallowing by infants and small children is very high You should implement safety measures so that Renesas products may not be easily detached from your products Renesas shall have no liability for damages arising out of such detachment 12 This document may not be reproduced or duplicated in any form in whole or in part without prior written approval from Renesas 13 Please contact a Renesas sales office if you have any questions regarding the information contained in this document Renesas semiconductor products or if you have any other inquiries Rev 1 00 Mar 03 2010 Page iii of vi RENESAS REJ10J2105 0100 Regulatory Compliance Notices European Union Regulatory Notices on Electromagnetic Compatibility CE Certifications This product complies with the following European EMC standards e EMC Directive 2004 108 EC EN 55022 Class A WARNING This is a Class A product In a domestic environment this product may cause radio interference in which case the user may be required to take adequate measures EN 55024 Information for Traceability e Authorized representative Name Renesas Technology Corp Address Nippon Bldg 2 6 2 Ote machi Chiyoda ku Tokyo 100 0004 Japan e Manufacturer Name
18. AL DSP_custom_SoC 6 Note on DSP repeat loop A BREAKPOINT is equal to a branch instruction In some DSP repeat loops branch instructions cannot be set For these cases do not set BREAKPOINTs Refer to the hardware manual for details 7 When the Normal option is selected in the Memory area group box in the General page of the Configuration dialog box a BREAKPOINT is set to a physical address or a virtual address according to the MMU status of the device during command input when the VPMAP_SET command setting is disabled The ASID value of the PTEH register of the device during command input is used When VPMAP_SET command setting is enabled a BREAKPOINT is set to a physical address into which address translation is made according to the VP_MAP table However for addresses out of the range of the VP_MAP table the address to which a BREAKPOINT is set depends on the MMU status of the device during command input Even when the VP_MAP table is modified after BREAKPOINT setting the address translated when the BREAKPOINT is set valid 8 When the Physical option is selected in the Memory area group box in the General page of the Configuration dialog box a BREAKPOINT is set to a physical address A BREAKPOINT is set after disabling the MMU of the device upon program execution After setting the MMU is returned to the original state When a break occurs at the corresponding virtual address the cause of termination displayed in the
19. Electronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics C 7 D 2 T lt D z D rCENESAS SuperH Family E10A USB Emulator Additional Document for User s Manual Supplementary Information on Using the SH4AL DSP_custom_SoC Renesas Microcomputer Development Environment System SuperH Family E10A USB for SH4AL DSP_custom_SoC HSO4ALKCU01 HE Renesas Electronics ee i Rev 1 00 2010 03 Rev 1 00 Mar 03 2010 Page ii of vi REJ10J2105 0100 RENESAS Notes regarding these materials This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document 2 Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document inclu
20. L5 0x0000108e p_sam gt s6 aL6 J 0x00001092 p_sam gt sf aL7 0x00001096 p_sam gt s8 aL8 0x0000109a p_sam gt s9 aL9 Ox0000109e delete p_sam Figure 2 2 Source Window at Execution Halted Sequential Break Rev 1 00 Mar 03 2010 Page 16 of 40 REJ10J2105 0100 RENESAS Section 2 Software Specifications when Using the SH4AL DSP_custom_SoC 2 2 2 Trace Functions The emulator supports the trace functions listed in table 2 6 Table 2 6 Trace Functions Memory Output Function Internal Trace AUD Trace Trace Branch trace Supported eight branches Supported Supported Range memory access trace Supported eight events Supported Supported Software trace Supported eight events Supported Supported Table 2 7 shows the type numbers that the AUD function can be used Table 2 7 Type Number and AUD Function Type Number AUD Function HS0005KCU01H Not supported HSO0005KCU02H Supported Rev 1 00 Mar 03 2010 Page 17 of 40 RENESAS REJ10J2105 0100 Section 2 Software Specifications when Using the SH4AL DSP_custom_SoC Branch Trace Functions The branch source and destination addresses their source lines branch types and types of accessed bus masters are displayed Setting Method Select the check box in the Branch group box in the Branch Event page of the Event condition 12 dialog box that opens by double clicking on the Ch12 Branch column of the Eventpoint window The branch condition
21. No Select ds Challa PreHit Channel No Select d CPU Match flag No Select MM ChaqA PreHit Channel CPU Match flag z CPU Match flag Match flag set gt 0 z Ch5C0A PreHit Channel No Select CPU Match flag No Select x CHECOAD PreHit Channel No Select CPU Match flag z Chi OQA OA R PreHit Channel Ch414 CPU Match flag Ch110A OA DT_CT_R PreHit Channel No Select CPU Match flag Cht 2 Branch PreHit Channel No Select Figure 2 1 CPU Sequential Extend Page a Indicates the channel name for setting conditions b Selects a condition that is satisfied before the channel which sets up conditions When a channel name is selected it is required that the condition of the channel selected here must have already been satisfied When CPU Match flag is selected the CPU match flag must be set When a condition is selected by the channel selected here no break will occur c When a condition is satisfied the CPU match flag is set or cleared When a program breaks the CPU match flag is initialized Set the event condition for each channel in the Event Condition dialog box this also applies to the System Bus Sequential Extend page Rev 1 00 Mar 03 2010 Page 14 of 40 REJ10J2105 0100 RENESAS Section 2 Software Specifications when Using the SH4AL DSP_custom_SoC Usage Example of Sequential Break Extension Setting A tutorial program provided for the product is used as an example For the tutorial program refe
22. O4ALKCU01 Hu Information on Using the HSO4ALKCUO1HE SH4AL DSP_custom_SoC and Test program manual for HS0005KCU01H and HS0005KCU02H HS0005TM01HJ and HS0005TM01HE provided on a CD R Note Additional document for the MPUs supported by the emulator is included Check the target MPU and refer to its additional document Rev 1 00 Mar 03 2010 Page 2 of 40 REJ10J2105 0100 7tENESAS Section 1 Connecting the Emulator with the User System 1 2 Connecting the Emulator with the User System To connect the E10A USB emulator hereinafter referred to as the emulator the H UDI port connector must be installed on the user system to connect the user system interface cable When designing the user system refer to an example of recommended connection between the connector and the MPU shown in this manual In addition read the E10A USB emulator user s manual and hardware manual for the related device Table 1 2 shows the type number of the emulator the corresponding connector type and the use of AUD function Table 1 2 Type Number AUD Function and Connector Type Type Number Connector AUD Function HS0005KCU02H 36 pin connector Available HS0005KCU01H HS0005KCU02H 14 pin connector Not available The H UDI port connector has the 36 pin and 14 pin types as described below Use them according to the purpose of the usage 1 36 pin type with AUD function The AUD trace function is supported A large amount of trace
23. Renesas Solutions Corp Address Nippon Bldg 2 6 2 Ote machi Chiyoda ku Tokyo 100 0004 Japan e Person responsible for placing on the market Name Renesas Technology Europe Limited European Headquarters Address Dukes Meadow Millboard Road Bourne End Buckinghamshire SL8 5FH U K Rev 1 00 Mar 03 2010 Page iv of vi REJ10J2105 0100 RENESAS United States Regulatory Notices on Electromagnetic Compatibility FCC Certifications This equipment has been tested and found to comply with the limits for a Class A digital device pursuant to Part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instruction manual may cause harmful interference to radio communications Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense This device complies with Part 15 of the FCC Rules Operation is subject to the following two conditions 1 this device may not cause harmful interference and 2 this device must accept any interference received including interference that may cause undesired operation CAUTION Changes or modifications not expressly approved by the party responsible for
24. To our customers Old Company Name in Catalogs and Other Documents On April 1 2010 NEC Electronics Corporation merged with Renesas Technology Corporation and Renesas Electronics Corporation took over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 1 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http Awww renesas com inquiry 2CENESAS 10 11 12 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is gra
25. alts in the sleep mode d Extension setting of the performance result storing counter The 32 bit counter stores the result of performance and two counters can be used as a 64 bit counter To set a 64 bit counter check the Enable check box in the Extend counter group box of the Performance Analysis dialog box for Ch and Ch3 2 Displaying the result of performance The result of performance is displayed in the Performance Analysis window or the PERFORMANCE_ANALYSIS command in hexadecimal 32 bits However when the extension counter is enabled it is displayed in hexadecimal 64 bits Note Ifa performance counter overflows as a result of measurement will be displayed 3 Initializing the measured result To initialize the measured result select Initialize from the popup menu in the Performance Analysis window or specify INIT with the PERFORMANCE_ANALYSIS command Rev 1 00 Mar 03 2010 Page 40 of 40 REJ10J2105 0100 RENESAS SuperH Family E10A USB Emulator Additional Document for User s Manual Supplementary Information on Using the SH4AL DSP_custom_Soc Publication Date Rev 1 00 March 3 2010 Published by Sales Strategic Planning Div Renesas Technology Corp Edited by Customer Support Department Global Strategic Communication Div Renesas Solutions Corp 2010 Renesas Technology Corp All rights reserved Printed in Japan Renesas Technology Corp Sales Strategic Planning Div
26. annot be acquired for the following branch instructions e The BF and BT instructions whose displacement value is 0 e Branch to H A0000000 by reset Rev 1 00 Mar 03 2010 Page 21 of 40 RENESAS REJ10J2105 0100 Section 2 Software Specifications when Using the SH4AL DSP_custom_SoC AUD Trace Function This function is operational when the AUD pin of the device is connected to the emulator It is activated by selecting the AUD trace radio button in the Trace type group box of the Trace mode page Set the trace condition to be used Table 2 8 shows the AUD trace acquisition mode that can be set in each trace function Table 2 8 AUD Trace Acquisition Mode Type Mode Description Continuous Realtime trace trace occurs When the next branch occurs while the trace information is being output all the information may not be output The user program can be executed in realtime but some trace information will be lost Non realtime trace When the next branch occurs while the trace information is being output the CPU stops operations until the information is output The user program is not executed in realtime Trace buffer Trace continue full This function overwrites the oldest trace information to store the latest trace information Trace stop After the trace buffer becomes full the trace information is no longer acquired The user program is continuously executed Rev 1 00 Mar 03 2010 Page 22 of 40
27. are trace Rev 1 00 Mar 03 2010 Page 9 of 40 7tENESAS REJ10J2105 0100 Section 2 Software Specifications when Using the SH4AL DSP_custom_SoC Table 2 4 Dialog Boxes for Setting Event Conditions Function Bus Window Address Data State Address Branch Bus Bus ASID Condition Condition LDTLB Count Condition Dialog Condition Condition Condition Bus Window System Instruction Condition Branch Software Box Address Data ASID Status address Bus Break Count Trace Trace Action Event O X O O X X X X X xX O Condition B and 1 dialog P box Event O O O O X X X O X X O Condition B and 2 dialog P box Event O X O X X X X X X X O Condition B and 3 dialog P box Event O X O X X X X X X X O Condition B and 4 dialog P box Event X X O O O X X X X X O Condition B T 5 dialog and P box Event X X O O O X X X X X O Condition B T 6 dialog and P box Event X X X X X X O X X X Break Condition fixed 7 dialog box Event O X X X X O X X X X O Condition B T 8 dialog and P box Rev 1 00 Mar 03 2010 Page 10 of 40 REJ10J2105 0100 RENESAS Section 2 Software Specifications when Using the SH4AL DSP_custom_SoC Table 2 4 Dialog Boxes for Setting Event Conditions cont Function Bus Window Address Data State Address Branch Bus Bus ASID Condition Condition LDTLB Count Condition Dialog Condition Condition Condition Bus Window System Instruction
28. as 1 Rev 1 00 Mar 03 2010 Page 38 of 40 REJ10J2105 0100 7tENESAS Section 2 Software Specifications when Using the SH4AL DSP_custom_SoC Table 2 12 shows the measurement items and methods that are mainly used Table 2 12 Main Measurement Items Main Measurement Item Measurement Method Elapsed time Number of elapsed cycles x CPU clock cycles Number of execution instructions Number of valid instructions issued number of cases of simultaneous execution of two instructions Number of interrupts accepted Number of exceptions accepted Number of instruction fetches for both cache and non cache Number of memory accesses in an opcode Instruction cache hit ratio Number of instruction cache accesses instruction cache miss counts instruction cache access counts Number of operand accesses for both cache and non cache Number of memory accesses in an operand read number of memory accesses in an operand write Operand cache hit ratio read Number of operand cache accesses read number of operand cache misses read number of operand cache accesses read Operand cache hit ratio write Number of operand cache accesses write number of operand cache misses write number of operand cache accesses write Operand cache hit ratio Number of operand cache accesses read number of operand cache accesses write number of operand cache miss
29. be compiled and linked beforehand For details refer to the SuperH RISC engine C C Compiler Assembler Optimizing Linkage Editor User s Manual When the load module is downloaded on the emulator and is executed while a software trace function is valid the PC value that has executed the Trace x function the general register value for x and the source lines are displayed To activate the software trace function select the Acquire Software trace radio button in the Software trace dialog box that is opened by double clicking on the software Trace column of the Eventpoint window Note To cancel settings select the Don t care radio button in the Software trace dialog box or select Delete from the popup menu that is opened by clicking on the software Trace column with the right mouse button Internal Trace Function This function is activated by selecting the Internal trace radio button in the Trace type group box of the Trace mode page Set the trace condition to be used Notes 1 If an interrupt is generated at the program execution start or end including a step operation the emulator address may be acquired In such a case the following message will be displayed Ignore this address because it is not a user program address k EML 2 Ifacompletion type exception occurs during exception branch acquisition the next address to the address in which an exception occurs is acquired 3 Trace information c
30. but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers
31. der certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas
32. ding but not limited to product data diagrams charts programs algorithms and application circuit examples 3 You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use When exporting the products or technology described herein you should follow the applicable export control laws and regulations and procedures required by such laws and regulations 4 All information included in this document such as product data diagrams charts programs algorithms and application circuit examples is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas products listed in this document please confirm the latest product information with a Renesas sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website http www renesas com 5 Renesas has used reasonable care in compiling the information included in this document but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document 6 When using or otherwise relying on the information in this document you should evaluate the information in light of
33. e Specifications when Using the SH4AL DSP_custom_SoC iii Open the ASID page remove the check mark of the Don t care check box and enter the ASID value to be set When the ASID value is not set as a condition do not remove the check mark of the Don t care check box iv Open the Bus state page and specify the bus type and bus cycle that are to be set Event condition 5 Window address ASID Bus State Action Bus state M Read Write Read Write C Read C Write Figure 2 5 Bus State Page v Selecting the Acquire trace check box in the Action page enables acquiring memory access within the range Note To cancel settings select the popup menu that is opened by clicking on the Ch5 OA or Ch6 OA column with the right mouse button Rev 1 00 Mar 03 2010 Page 20 of 40 REJ10J2105 0100 RENESAS Section 2 Software Specifications when Using the SH4AL DSP_custom_SoC Software Trace Function Note This function can be supported with SHC C compiler manufactured by Renesas Technology Corp including OEM and bundle products V6 0 or later However SHC C compiler including OEM and bundle products V8 0 or later is needed when instructions other than those compatible with SH4 are output When a specific instruction is executed the PC value at execution and the contents of one general register are acquired by trace Describe the Trace x function x is a variable name to
34. e initialized as a value that has been automatically acquired Rev 1 00 Mar 03 2010 Page 7 of 40 RENESAS REJ10J2105 0100 Section 2 Software Specifications when Using the SH4AL DSP_custom_SoC 13 IO Window Modules are not described in the I O register file Usage must be in accord with the descriptions in the device manual The set of I O registers is customizable in the format for the T O register file 14 Illegal Instructions If illegal instructions are executed by STEP type commands the emulator cannot go to the next program counter 15 Reset CPU and Reset Go in the Debug Menu When Reset Mode of the Configuration dialog box is set as Auto an H UDI reset is issued by executing Reset CPU or Reset Go For the H UDI reset the clock pulse generator and RCLK watchdog timer are not initialized When User is selected and Reset CPU or Reset Go is executed a reset signal input from the user system is waited Rev 1 00 Mar 03 2010 Page 8 of 40 REJ10J2105 0100 RENESAS Section 2 Software Specifications when Using the SH4AL DSP_custom_SoC 2 2 Specific Functions for the Emulator when Using the SH4AL DSP_custom_SoC 2 2 1 Event Condition Functions The emulator is used to set 12 event conditions Ch1 to Ch12 and the software trace Table 2 3 lists the conditions of Event Condition Table 2 3 Types of Event Conditions Event Condition Type Description Address bus condition Address
35. e measurement function 1 Setting the performance measurement conditions To set the performance measurement conditions use the Performance Analysis dialog box and the PERFORMANCE_SET command When a channel line on the Performance Analysis window is clicked with the right mouse button the popup menu is displayed and the Performance Analysis dialog box is displayed by selecting Setting Performance An Condition Cycle rt e Selection of a count item OPU performance Cycle Count C hstruction C Branch C Exception interruption C Stalled Cycle C ILB performance C hstruction bus performance Operand bus performance C Access count C Access miss count C Waited cycle C System bus performance m Extend counter I Enable oeei Figure 2 8 Performance Analysis Dialog Box Note For the command line syntax refer to the online help Rev 1 00 Mar 03 2010 Page 30 of 40 REJ10J2105 0100 RENESAS Section 2 Software Specifications when Using the SH4AL DSP_custom_SoC a Specifying the measurement start end conditions Set the performance measurement conditions in the Action page after conditions have been set in the Event Condition dialog box that is opened by double clicking Ch1 to Ch6 and Ch8 to Ch12 on the Event Condition sheet of the Eventpoint window Notes When no measurement start end conditions are specified measurement is started by
36. es If the previously output address is the same as the upper 16 bits the lower 16 bits are output If it matches the upper 24 bits the lower 8 bits are output If it matches the upper 28 bits the lower 4 bits are output The emulator regenerates the 32 bit address from these differences and displays it in the Trace window If the emulator cannot display the 32 bit address it displays the difference from the previously displayed 32 bit address If the 32 bit address cannot be displayed the source line is not displayed In the emulator when multiple loops are performed to reduce the number of AUD trace displays only the IP counts up In the emulator the maximum number of trace displays is 65534 lines 32767 branches However the maximum number of trace displays differs according to the AUD trace information to be output Therefore the above pointers cannot be always acquired The AUD trace acquisition is not available when User is selected in the UBC mode list box of the Configuration dialog box In this case close the Trace window If a completion type exception occurs during exception branch acquisition the next address to the address in which an exception occurs is acquired Rev 1 00 Mar 03 2010 Page 24 of 40 REJ10J2105 0100 RENESAS Section 2 Software Specifications when Using the SH4AL DSP_custom_SoC Memory Output Trace Function This function is activated by selecting the Use Memory trace radio button in the
37. es read number of operand cache misses write number of operand cache accesses read number of operand cache accesses write System bus occupied rate of request bus The equivalent CPU clock value of the number of requests number of elapsed cycles System bus occupied rate of response bus The equivalent CPU clock value of the number of responses number of elapsed cycles Rev 1 00 Mar 03 2010 Page 39 of 40 7tENESAS REJ10J2105 0100 Section 2 Software Specifications when Using the SH4AL DSP_custom_SoC Each measurement condition is also counted when conditions in table 2 13 are generated Table 2 13 Performance Measurement Conditions to be Counted Measurement Condition Notes No caching due to the Counted for accessing the cacheable area settings of TLB cacheable bit Cache on counting Accessing the non cacheable area is counted less than the actual number of cycles and counts Accessing the cacheable X Y RAM and U RAM areas is counted more than the actual number of cycles and counts Branch count The counter value is incremented by 2 This means that two cycles are valid for one branch Notes 1 In the non realtime trace mode of the AUD trace and memory output trace normal counting cannot be performed because the generation state of the stall or the execution cycle is changed 2 Since the clock source of the counter is the CPU clock counting also stops when the clock h
38. kpoint set Disables the instruction cache Port G When AUD tracing is enabled the emulator forcibly changes the settings so that the AUD function is used 10 UBC 1 When User is specified in the UBC mode list box in the Configuration dialog box the UBC can be used in the user program Do not use the UBC in the user program as it is used by the emulator when EML is specified in the UBC mode list box in the Configuration dialog box Memory Access during Break In the enabled MMU when a memory is accessed and a TLB error occurs during break it can be selected whether the TLB exception is controlled or the program jumps to the user exception handler in TLB Mode in the Configuration dialog box When TLB miss exception is enable is selected a Communication Timeout error will occur if the TLB exception handler does not operate correctly When TLB miss exception is disable is selected the program does not jump to the TLB exception handler even if a TLB exception occurs Therefore if the TLB exception handler does not operate correctly a Communication Timeout error will not occur but the memory contents may not be correctly displayed 12 Loading Sessions Information in JTAG clock of the Configuration dialog box cannot be recovered by loading sessions Thus the TCK value will be 1 25 MHz If the Search the best JTAG clock option is used when the emulator is initiated the TCK value will b
39. lect Setting from the pop up menu to display the Acquisition dialog box The AUD trace acquisition mode can be set in the Trace Mode 1 or Trace Mode 2 group box in the Trace Mode page of the Acquisition dialog box Acquisition Trace Mode Trace type Trace Mode 1 Realtime trace C Non realtime trace Trace Mode 2 Trace continue Trace stop AUD Mode G Abt Bhit AUD trace display range Start pointer D255 End painten p O User memory area Start H3000 End Address H33 FF Trace Extend Mode IT Trace data with PPC E Figure 2 7 Trace Mode Page Rev 1 00 Mar 03 2010 Page 26 of 40 REJ10J2105 0100 RENESAS Section 2 Software Specifications when Using the SH4AL DSP_custom_SoC Notes 1 The memory range for which trace is output is the address on the system bus and not supported for the MMU or cache 2 Inthe memory range for output do not specify the ranges that the user program has been downloaded or the user program accesses 3 Do not select an internal RAM area as the memory range for output 4 The range for trace output must be MB or less 2 2 3 Notes on Using the JTAG H UDID Clock TCK and AUD Clock AUDCK 1 Set the JTAG clock TCK to a frequency no higher than that of the peripheral module clock CKP for the device 2 Set the AUD clock AUDCK frequency to 50 MHz or lower If the frequency is higher than 50 MHz
40. n the H UDI Port Connector and the MPU For recommended circuits between the H UDI plus AUD port connector 36 pins or H UDI port connector 14 pins and the chip when the emulator is in use ask Renesas Technology Corp via a sales office Rev 1 00 Mar 03 2010 Page4of40 Z REJ10J2105 0100 RENESAS Section 2 Software Specifications when Using the SH4AL DSP_custom_SoC Section 2 Software Specifications when Using the SH4AL DSP_custom_SoC 2 1 Differences between the SH4AL DSP_custom_SoC and the Emulator 1 When the emulator system is initiated it initializes the general registers and some of the control registers as shown in table 2 1 Initial value of MPU registers are undefined when the emulator is not connected Table 2 1 Register Initial Values at Emulator Link Up Register Emulator at Link Up RO to R14 H 00000000 R15 SP H A0000000 RO_BANK to R7_BANK H 00000000 PC H A0000000 SR H 700000F0 GBR H 00000000 VBR H 00000000 MACH H 00000000 MACL H 00000000 PR H 00000000 SPC H 00000000 SSR H 000000F0 RS H 00000000 RE H 00000000 MOD H 00000000 AOG A1G H 00000000 AO A1 H 00000000 XO X1 H 00000000 YO Y1 H 00000000 MO M1 H 00000000 DSR H 00000000 2 The emulator uses the H UDI do not access the H UDI 7tENESAS Rev 1 00 Mar 03 2010 Page 5 of 40 REJ10J2105 0100 Section 2 Software Specifications when Using the SH4AL DSP_custom_SoC 3 Low
41. ng user program execution the user program is resumed after it has stopped in the emulator to access the memory Therefore realtime emulation cannot be performed The stopping time of the user program is as follows Environment Host computer 800 MHz Pentium III JTAG clock 10 MHz TCK clock When a one byte memory is read from the command line window the stopping time will be about 42 ms Since the above values are for reference they differ according to the MPU in use Rev 1 00 Mar 03 2010 Page 6 of 40 REJ10J2105 0100 RENESAS Section 2 Software Specifications when Using the SH4AL DSP_custom_SoC 7 Memory Access during User Program Break The emulator can download the program for the flash memory area for details refer to section 6 22 Download Function to the Flash Memory Area in the SuperH Family E10A USB Emulator User s Manual Other memory write operations are enabled for the RAM area Therefore an operation such as memory write or BREAKPOINT should be set only for the RAM area Cache Operation during User Program Break When cache is enabled the emulator accesses the memory by the following methods At memory write Writes through the cache then issues a single write to outside The LRU is not updated At memory read Reads memory from the cache The LRU is not updated Therefore when memory read or write is performed during user program break the cache state does not change At brea
42. nted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document
43. office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions un
44. r to section 6 Tutorial in the SuperH Family E10A USB Emulator User s Manual The conditions of Event Condition are set as follows 1 Chl Breaks address H 00001068 when the condition Prefetch address break after executing is satisfied 2 Ch2 Breaks address H 00001058 when the condition Prefetch address break after executing is satisfied 3 Ch4 Breaks address H 0000107a when the condition Prefetch address break after executing is satisfied 4 Ch10 Breaks address H 00001086 when the condition Prefetch address break after executing is satisfied Note Do not set other channels 5 Set the CPU Sequential Extend page as shown in figure 2 1 Then set the program counter and stack pointer PC H 00000800 R15 H 00010000 in the Registers window and click the Go button If this does not execute normally issue a reset and execute the above procedures The program is executed up to the condition of Ch10 and halted Here the condition is satisfied in the order of Ch2 gt 1 gt 4 gt 10 Rev 1 00 Mar 03 2010 Page 15 of 40 RENESAS REJ10J2105 0100 Section 2 Software Specifications when Using the SH4AL DSP_custom_SoC fi 0x00001058 ali j 0x00001068 p_sam gt sort a 0x00001070 p_sam gt change a 0x00001076 p_sam gt s0 aL0 0x0000107a p_sam gt sl aL1 0x0000107e p_sam gt s aL 0x00001082 p_sam gt s3 aL3 Ox00001086 p_sam gt s4 al4 0x0000108a p_sam gt s5 a
45. rms OR to count the channel hit number of channel hits in the CPU Rev 1 00 Mar 03 2010 Page 33 of 40 RENESAS REJ10J2105 0100 Section 2 Software Specifications when Using the SH4AL DSP_custom_SoC Table 2 11 Measurement Items cont Classification Type Measurement Item Option Note CPU Stalled Cycles stalled in full SFM All items are counted performance cycle trace mode with independently cont multi counts Cycles stalled in full SF This item is not counted if the trace mode without stall cycle is generated multi counts simultaneously with a stall cycle that has occurred due to instruction execution TLB TLB Number of UTLB miss UMI The number of TLB miss performance for instruction fetch exceptions generated by an instruction fetch number of EXPEVT sets Number of UTLB miss UMO The number of TLB miss for operand fetch exceptions generated by an operand access number of EXPEVT sets Number of ITLB miss IM The number of ITLB misses for valid accesses does not include UTLB hits or misses Instruction bus Instruction Number of memory MIF The number of memory performance accesses for accesses by an instruction instruction fetch fetch Accesses canceled by an instruction fetch bus are not counted Instruction fetches which have been fetched in anticipation of a branch but not actually executed are counted Accesses by the PREFI instruction are included Number of instruction IC The n
46. ses are not included Number of operand CR cache access READ The number of operand cache reads during memory access read of an operand Number of operand CW cache access WRITE The number of operand cache reads during memory access write of an operand 7tENESAS Rev 1 00 Mar 03 2010 Page 35 of 40 REJ10J2105 0100 Section 2 Software Specifications when Using the SH4AL DSP_custom_SoC Table 2 11 Measurement Items cont Classification Type Measurement item Option Note Operand bus Access Number of internal XLR The number of accesses to XY performance count cont RAM access for memory in the device during cont operand fetch memory access read of an READ XY RAM or operand O L memory Accesses via the XY bus and the operand bus are included When MOVX and MOVY are executed simultaneously it increments one count regardless of the read or write Number of internal XLW The number of accesses to XY RAM access for memory in the device during operand fetch memory access write of an WRITE XY RAM operand or O L memory Accesses via the XY bus and the operand bus are included When MOVX and MOVY are executed simultaneously it increments one count regardless of the read or write Number of I L ILRW The number of accesses to I L memory access for operand fetch READ WRITE memory in the device during memory access read write of an operand Number of U RAM UR acce
47. ss READ The number of U memory accesses during memory access read of an operand Accesses via the cache are not included Number of U RAM UW access WRITE The number of U memory accesses during memory access write of an operand Accesses via the cache are not included Rev 1 00 Mar 03 2010 Page 36 of 40 REJ10J2105 0100 7tENESAS Section 2 Software Specifications when Using the SH4AL DSP_custom_SoC Table 2 11 Measurement Items cont Classification Type Measurement Item Option Note Operand bus Access Number of operand CMR The number of cache misses performance miss count cache miss READ by an operand cache access cont read number of accesses to the outside of the CPU core due to a cache miss Cache misses are not counted by the PREF instruction Number of operand CMW The number of cache misses cache miss WRITE by an operand cache access write number of accesses to the outside of the CPU core due to a cache miss Write through accesses are not counted Cache misses are not counted by the PREF instruction Number of U RAM UBM read buffer miss Waited Waited cycles for WOR The number of wait cycles by a cycle operand fetch memory access read of an READ operand Waited cycles for WOW The number of wait cycles by a operand fetch memory access write of an WRITE operand Waited cycles for WCMR The number of wait cycles by operand cache miss an operand
48. st be set for Ch6 and Ch5 Ch11 gt 10 Halts a program when a condition is satisfied in the order of Event Condition 11 10 An event condition must be set for Ch11 and Ch10 Many Ch3 gt 2 gt 1 Channel Sequential Halts a program when a condition is satisfied in the order of Event Condition 3 2 1 An event condition must be set for Ch3 Ch2 and Chi Ch4 gt 3 gt 2 gt 1 Halts a program when a condition is satisfied in the order of Event Condition 4 3 2 1 An event condition must be set for Ch4 Ch3 Ch2 and Ch1 Ch5 gt 4 gt 3 gt 2 gt 1 Halts a program when a condition is satisfied in the order of Event Condition 5 4 3 2 1 An event condition must be set for Ch5 Ch4 Ch3 Ch2 and Ch1 Ch6 gt 5 gt 4 gt 3 gt 2 gt 1 Halts a program when a condition is satisfied in the order of Event Condition 6 5 4 3 2 1 An event condition must be set for Ch6 Ch5 Ch4 Ch3 Ch2 and Ch1 Ch10 gt 6 gt 5 gt 4 gt 3 gt 2 gt 1 Halts a program when a condition is satisfied in the order of Event Condition 10 6 5 4 3 2 1 An event condition must be set for Ch10 Ch6 Ch5 Ch4 Ch3 Ch2 and Ch1 Ch11 gt 10 gt 6 gt 5 gt 4 gt 3 gt 2 gt 1 Halts a program when a condition is satisfied in the order of Event Condition 11 10 6 5 4 3 2 1 An event condition must be set for Ch11 Ch10 Ch6 Ch5 Ch4 Ch3 Ch2 and
49. status bar and the Output window is ILLEGAL INSTRUCTION not BREAKPOINT 9 When the Virtual option is selected in the Memory area group box in the General page of the Configuration dialog box a BREAKPOINT is set to a virtual address A BREAKPOINT is set after enabling the MMU of the device upon program execution After setting the MMU is returned to the original state When an ASID value is specified the BREAKPOINT is set to the virtual address corresponding to the ASID value The emulator sets the BREAKPOINT after rewriting the ASID value to the specified value and returns the ASID value to its original value after setting When no ASID value is specified the BREAKPOINT is set to a virtual address corresponding to the ASID value at command input 10 An address physical address to which a BREAKPOINT is set is determined when the BREAKPOINT is set Accordingly even if the VP_MAP table is modified after BREAKPOINT setting the BREAKPOINT address remains unchanged When a BREAKPOINT is satisfied with the modified address in the VP_MAP table the cause of termination displayed in the status bar and the Output window is ILLEGAL INSTRUCTION not BREAKPOINT Rev 1 00 Mar 03 2010 Page 280f40 REJ10J2105 0100 RENESAS Section 2 Software Specifications when Using the SH4AL DSP_custom_SoC 11 If an address of a BREAKPOINT cannot be correctly set in the ROM or flash memory area a mark will be displayed in the BP area of the address
50. the emulator will not operate normally 3 The set value of the JTAG clock TCK is initialized by executing Reset CPU or Reset Go Thus the TCK value will be 1 25 MHz When the Search the best JTAG clock option has been selected at initiation of the emulator the TCK value is initialized to a value that was automatically acquired 2 2 4 Notes on Setting the Breakpoint Dialog Box 1 When an odd address is set the next lowest even address is used 2 A BREAKPOINT is accomplished by replacing instructions of the specified address Accordingly it can be set only to the RAM areas in CSO to CS6 and the internal RAM areas A BREAKPOINT cannot be set to the following addresses ROM areas in CSO to CS6 Areas other than CSO to CS6 except for the internal RAM A slot instruction of a delayed branch instruction An area that can be only read by MMU 3 During step operation BREAKPOINTs are disabled 4 When execution resumes from the address where a BREAKPOINT is specified single step operation is performed at the address before execution resumes Therefore realtime operation cannot be performed 5 When a BREAKPOINT is set to the slot instruction of a delayed branch instruction the PC value becomes an illegal value Accordingly do not set a BREAKPOINT to the slot instruction of a delayed branch instruction Rev 1 00 Mar 03 2010 Page 27 of 40 RENESAS REJ10J2105 0100 Section 2 Software Specifications when Using the SH4
51. the measurement end condition of performance channel 2 PA3 pa3_start_point Specifies the conditions of Event Condition that has been set as the measurement start condition of performance channel 3 pa3_end_point Specifies the conditions of Event Condition that has been set as the measurement end condition of performance channel 3 PA4 pa4_start_point Specifies the conditions of Event Condition that has been set as the measurement start condition of performance channel 4 pa4_end_point Specifies the conditions of Event Condition that has been set as the measurement end condition of performance channel 4 Rev 1 00 Mar 03 2010 Page 31 of 40 RENESAS REJ10J2105 0100 Section 2 Software Specifications when Using the SH4AL DSP_custom_SoC Event condition 1 Address ASID Bus State Action pal _start_point C pal _enc_point e2 Start paint Si Zend paint eaa stan paint Gma end pint a4 stan paint a4 end mint Figure 2 9 Action Page Note PA1 or PA2 cannot be set for Ch8 and Ch9 b Measurement tolerance The measured value includes tolerance Tolerance will be generated before or after a break For details see table 2 13 c Measurement items Items are measured in the Performance Analysis dialog box for each channel from Ch1 to Ch4 A maximum of four conditions can be specified at the same time Table 2 11 shows the measurement items Options in table 2 11 are parameters for
52. the total system before deciding about the applicability of such information to the intended application Renesas makes no representations warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products 7 With the exception of products specified by Renesas as suitable for automobile applications Renesas products are not designed manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems or equipment or systems for transportation and traffic healthcare combustion control aerospace and aeronautics nuclear power or undersea communication transmission If you are considering the use of our products for such purposes please contact a Renesas sales office beforehand Renesas shall have no liability for damages arising out of the uses set forth above 8 Notwithstanding the preceding paragraph you should not use Renesas products for the purposes listed below 1 artificial life support devices or systems 2 surgical implantations 3 healthcare intervention e g excision administration of medication etc 4 any other purposes that pose a direct threat to human life Renesas shall have
53. to be acquired can be set Event condition 12 Branch event Action Branch V Acquire general branch instruction event Jj Acquire subroutine branch instruction event V Acquire exception branch instruction event Figure 2 3 Branch Event Dialog Box A branch trace can be acquired by selecting the Acquire trace check box of the Action page Note To cancel settings select Delete from the popup menu that is opened by clicking on the Ch12 Branch column with the right mouse button Rev 1 00 Mar 03 2010 Page 18 of 40 REJ10J2105 0100 RENESAS Section 2 Software Specifications when Using the SH4AL DSP_custom_SoC Range Memory Access Trace Functions The memory access within the specified range is acquired by a trace The read cycle write cycle or read write cycle can be selected as the bus type ASID value or bus cycle for trace acquisition Setting Method i To open the Event condition 5 or Event condition 6 dialog box double click on the Ch5 OA or Ch6 OA column of the Eventpoint window ii Remove the check mark of the Don t care check box in the Window address page and enter the memory range to be set Event condition 5 Window address ASID Bus State Action Window address Start address H 00000000 End address H 00000000 Som Figure 2 4 Window address Page Rev 1 00 Mar 03 2010 Page 19 of 40 RENESAS REJ10J2105 0100 Section 2 Softwar
54. umber of accesses for cache access an instruction cache during memory access of the opcode Rev 1 00 Mar 03 2010 Page 34 of 40 REJ10J2105 0100 RENESAS Section 2 Software Specifications when Using the SH4AL DSP_custom_SoC Table 2 11 Measurement Items cont Classification Type Measurement Item Option Note Instruction bus Instruction Number of ICM The number of cache misses performance cont instruction cache by an instruction cache cont miss access the number of accesses to the outside of the CPU core due to a cache miss Number of internal XL The number of accesses for RAM access for the XY memory in the device instruction fetch during memory accesses of XY RAM or O L the opcode memory Number of I L ILIF The number of accesses for memory access for the I L memory in the device instruction fetch during memory accesses of the opcode Number of U RAM ULF The number of accesses for memory access for the U memory in the device instruction fetch during memory accesses of the opcode Operand bus Access Number of memory MR The number of memory performance count access for operand accesses by an operand read fetch READ equal to loading on the operand bus Accesses by the PREF instruction or canceled accesses are not included Number of memory MW access for operand fetch WRITE The number of memory accesses by an operand write equal to storing memory on the operand bus Canceled acces
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