^1 USER MANUAL ^2 Accessory 10E
Contents
1. Top View Pin Symbol Function Description Notes 1 OUT12 Output Output 13 Sinking Sourcing 2 OUT13 Output Output 14 Sinking Sourcing 3 OUT14 Output Output 15 Sinking Sourcing 4 OUT15 Output Output 16 Sinking Sourcing 5 OUT 16 Output Output 17 Sinking Sourcing 6 OUT17 Output Output 18 Sinking Sourcing 7 OUT18 Output Output 19 Sinking Sourcing 8 OUTI9 Output Output 20 Sinking Sourcing 9 OUT20 Output Output 21 Sinking Sourcing 10 OUT21 Output Output 22 Sinking Sourcing 1 OUT22 Output Output 23 Sinking Sourcing 12 OUT23 Output Output 24 Sinking Sourcing This terminal block provide the inputs 13 24 for the ACC 10E Input Card I O Terminals 29 Accessory 10E TB3 Top 3 Pin Terminal Block 1 GNDI Reference Reference voltage o o 2 VI Voltage IV 3 GNDI Reference Reference voltage TB1 Bottom 12 Pin Terminal Block Pin Notes Sinking Sourcing Sinking Sourcing Sinking Sourcing Sinking Sourcing Sinking Sourcing Sinking Sourcing Sinking Sourcing Sinking Sourcing Sinking Sourcing 10 Sinking Sourcing 1 Sinking Sourcing 12 Sinking Sourcing This terminal block provide the inputs 25 36 for the ACC 10E Input Card OD ISI TANJA ELI o TB2 Bottom 12 Pin Terminal Block Top View Pin Notes l Sinking Sourcing Sinking Sourcing Sinking Sourcing Sinking Sourcing Sin2. 0 Reserved for future use 9 12 FFCO FFC8 FFDO FFD8 MACRO Station Y Base Address of I O Board as set by Board Jumper E1 E4 ACC 3E board or E15 E18 ACC 4E board MACRO Station Y Base Address of ACC 9E ACC 10E ACC 11E ACC 12E and ACC 13E for legacy systems 8800 8840 8880 88C0 FFEO FFE8 FFFO When this function is active the MACRO Station will copy values from the MACRO command input node registers to the I O board addresses it will copy values from the I O board addresses to the MACRO feedback output node registers Writing a 0 to a bit of the I O board enables it as an input letting the output pull high Writing a 1 to a bit of the I O board enables it as an output and pulls the output low The following table shows the mapping of I O points on the I O piggyback boards to the MACRO node registers I O points move from the least significant bit to the most significant bit 1 000 at Node bit 0 VO Point s Option 3 Part Present on Option 4 Matching MACRO X Register 1 000 1 015 Sub option A Yes Specified MACRO X Address 1 I O16 VO3I Sub option A Yes Specified MACRO X Address 2 1 032 VO47 Sub option A Yes Specified MACRO X Address 3 1 048 O71 Sub option B No Specified MACRO X Address 0 Examples 1169 00C0A000 8800 transfers 72 bit I O between an I O board set at 8800 and MACRO Nodes 2 COA0
3. M980 gt X C0A1 8 16 M980 gt X 78421 8 16 IO word 1 1st 16 bit word node2 M981 gt X C0A2 8 16 M981 gt X 78422 8 16 IO word 2 2nd 16 bit word node 2 M982 gt X C0A3 8 16 M982 gt X 78423 8 16 IO word 3 3rd 16 bit word node 2 M983 gt X C0A5 8 16 M983 gt X 78425 8 16 IO word 1 1st 16 bit word node 3 M984 gt X C0A6 8 16 M984 gt X 78426 8 16 IO word 2 2nd 16 bit word node 3 M985 gt X C0A7 8 16 M985 gt X 78427 8 16 IO word 3 3rd 16 bit word node 3 M1000 gt X 0770 8 16 M1000 gt X 0010F0 8 16 Input mirror word 1 M1001 gt Y 0770 8 16 M1001 gt Y 0010F0 8 16 Input mirror word 2 M1002 gt X 0771 8 16 M1002 gt X 0010F 1 8 16 Input mirror word 3 M1003 2Y 0771 8 16 M1003 gt Y 0010F1 8 16 Output mirror word 1 M1004 gt X 0772 8 16 M1004 gt X 0010F2 8 16 Output mirror word 2 M1005 gt Y 0772 8 16 M1005 gt Y 0010F2 8 16 Output mirror word 3 M1010 gt X 0773 8 16 M1010 gt X 0010F3 8 16 Old Image mirror word 1 M1011 gt Y 0773 8 16 M1011 gt Y 0010F3 8 16 Old Image mirror word 2 M1012 gt X 0774 8 16 M1012 gt X 0010F4 8 16 Old Image mirror word 3 S0 MI69 20C0A130 8800 S0 MI975 SC S0 MI19 4 SSAVEO S 550 OPEN PLC1 CLEAR 1000 M980 wordM1001 M981 1002 M982 IF M1000 M1010 M1010 M1000
4. 0010F 1 14 M907 gt Y 0010F 1 15 M908 gt Y 0010F1 16 M909 gt Y 0010F 1 17 M910 gt Y 0010F1 18 M911 gt Y 0010F1 19 M912 gt Y 0010F 1 20 M913 gt Y 0010F1 21 M914 gt Y 0010F 1 22 M915 gt Y 0010F1 23 M916 gt X 0010F2 8 M917 gt X 0010F2 9 M918 gt X 0010F2 10 M919 gt X 0010F2 I I M920 gt X 0010F2 12 M129 gt X 0010F2 13 M922 gt X 0010F2 14 M923 gt X 0010F2 15 M924 gt X 0010F2 16 M925 gt X 0010F2 17 M926 gt X 0010F2 18 M927 gt X 0010F2 19 M928 gt X 0010F2 20 M129 gt X 0010F2 21 M930 gt X 0010F2 22 M931 gt X 0010F2 23 M932 gt Y 0010F2 8 M933 gt Y 0010F2 9 M934 gt Y 0010F2 10 M935 gt Y 0010F2 I I M936 gt Y 0010F2 12 M937 gt Y 0010F2 13 M938 gt Y 0010F2 14 M939 gt Y 0010F2 15 M940 gt Y 0010F2 16 M941 gt Y 0010F2 17 M942 gt Y 0010F2 18 M943 gt Y 0010F2 19 M944 gt Y 0010F2 20 M945 gt Y 0010F2 21 M946 gt Y 0010F2 22 M947 gt Y 0010F2 23 MACRO Station I O Transfer 21 Accessory 10E Example 1 48 Inputs 48 Outputs Using 3X16 Bit Transfers For this example the inputs and outputs are not sharing the same Node Transfer Addresses COA1 COA2 C0A3 COAS COA6 and COA7 Each of the node transfer address can be defined as 16 bit addresses Ultralite 8 Axis Turbo Ultralite 8 Axis Description 1996 0FB33F 16841 0FB33F Enable nodes 0 1 2 3 4 5 8 9 12 amp 13 at PMAC Ultralite
5. 8 9 12 13 and up to six I O transfer nodes 2 3 6 7 10 11 There are two types of I O transfers allowed to send information to the Ultralite from the MACRO Station 48 bit transfer and 24 bit transfer The PMAC2 Ultralite and the MACRO Station enable you to transfer 72 bits per I O node Fora multi Master system 432 bits 6x72 of data may be transferred for each Master Ultralite in the ring If only one Master is used in the ring node 14 could be used for I O transfer which would give us 504 bits 7x72 of I O transfer data Ultralite MACRO IC MACRO Station Gate 2B VO Accessory Gate For all MACRO Station I O accessories the information is transferred to or from the accessory VO Gate to the MACRO Station CPU Gate 2B Information from the MACRO Station Gate 2B is then read or written directly to the MACRO IC on the Ultralite Once the information is at the Ultralite it can be used in your application motion programs or PLC programs Each I O board has jumper and software settings to select the I O transfer memory locations at both the I O transfer Gate and the MACRO transfer addresses These jumpers and software settings are discussed in this manual MACRO VO Gate Locations 8800 8802 8804 8840 8842 8844 8880 8882 8884 88C0 88C2 88C4 MACRO Station I O Node Transfer Addresses Node s Node 24 bit Node 16 bit upper 16 bits Transfer Addresses Transfer Add
6. C0A3 1169 00C0B000 8840 transfers 72 bit I O between an I O board set at 8840 and MACRO Node 10 COBO COB3 MI171 MI172 or MI173 specifies the registers used in 144 bit I O transfers between MACRO I O node interface registers and I O registers on a MACRO station It is used only if MI19 is greater than 0 The transfer utilizes two consecutive 72 bit X memory I O nodes The three 48 bit I O Gates must be the LOWER MIDDLE and UPPER configuration MI171 MI172 or MI173 is a 48 bit variable represented as 12 hexadecimal digits The first 6 digits specify the address of the first 72 bit real time MACRO node register sets to be used of the two The second 6 digits specify the address of 48 bit I O sets on an Option 3 or Option 4 board to be used 16 MACRO Station I O Transfer Accessory 10E The individual digits are specified as follows Digit Possible Values Description 1 0 Reserved for future use 2 0 Reserved for future use 3 6 COAO Nodes 2 3 COA4 Nodes 3 6 MACRO Station X Address of MACRO I O first 24 COA8 Nodes 6 7 COAC Nodes 7 10 COBO Nodes 10 11 COB4 Nodes 11 14 bit register of the two consecutive nodes 7 0 Reserved for future use 8 0 Reserved for future use 9 12 FFCO FFC8 FFDO FFD8 8800 8840 8880 88C0 FFEO FFE8 FFFO MACRO Station Y Base Address of I O Board as set by Board Jumper E1 E4 ACC 3E board or E15 E
7. CMD MS0 MI198 40 8807 set control word for ACC 10E CMD MS0 MI199 00 write 00 into Y 8807 0 8 control word Timer1 50 8388608 110 50 msec delay While Timerl gt 0 Endwhile CMD MS0O MI198 S48S8807 set control word for ACC 11E CMD MS0 MI199 07 write 07 into Y 8807 8 8 control word Timer1 50 8388608 110 50 msec delay While Timerl gt 0 Endwhile Disable PLC10 Close APPENDIX MACRO Legacy Systems The legacy systems are defined as MACRO CPU with the following part numbers e 602804 100 602804 101 602804 102 602804 103 602804 104 These systems do not have the extended addressing of the newer model MACRO CPU s 602804 105 through 602804 10A The addressing scheme for the legacy MACRO systems is listed below For Legacy MACRO systems the ACC 9E ACC 10E ACC 11E and ACC 12E will have the following base addess table E1 E4 VO Gate Transfer Jumpers Jumper UMAC MACRO El FFEO E2 FFE8 E3 FFFO E4 Not Available The ACC 65E ACC 66E and ACC 67E are not direct replacements for ACC 9E ACC 10E and ACC 11E I O cards The reason the self protected I O is not a direct replacement is because of the addressing scheme The older I O cards used the LOW MIDDLE and HIGH bytes of a base address and the MACRO I variables would read consecutive I O cards in this manner The self protected I O cards are addressed from the LOW bytes only Because of thi
8. M1011 M1001 M983 M1003 M984 M1004 M985 M1005 ENDIF CLOSE 22 sets up macro to transfer data for ACC 9E and 10E enable node 2 and 3 for I O sets interrupt period for data transfer Save to macro station reset macro station to enable new input new input new input OR M1001 M1011 mirror equal to actual mirror equal to actual mirror equal to actual input input word input word if inputs change process outputs old input mirror equal to new input mirror old input mirror equal to new input mirror Set outputs based on inputs or program logic Output word equals Output Mirror Word Output word equals Output Mirror Word Output word equals Output Mirror Word MACRO Station I O Transfer Accessory 10E Example 2 48 Inputs 48 Outputs Using 1X24 Bit Transfers For this example the inputs and outputs are not sharing the same Node Transfer Address COAO COA4 COA8 COBO Each of the node transfer addresses can be defined as 24 bit addresses Ultralite 8 Axis Turbo Ultralite 8 Axis Description 1996 0FB3FF 16841 0FB3FF Enable nodes 0 1 2 3 4 5 6 7 8 9 12 amp 13 at PMAC Ultralite M970 gt X C0A0 0 24 M970 gt X 78420 0 24 IO word 1 24 bit word node2 M971 gt X C0A4 0 24 M971 gt X 78424 0 24 IO word 2 24 bit word node 3 M972 gt X C0A8 0 24 M972 gt X 78428 0 24 IO word 3 24 bit word node 6 M973
9. 16 E14 amp E15 1 2 Sinking inputs with the ULN2803A IC for outputs 17 through 24 2 3 Sourcing outputs with the UDN2981A IC for outputs 17 through 24 E16 amp E17 1 2 Sinking inputs with the ULN2803A IC for outputs 25 through 32 2 3 Sourcing outputs with the UDN2981A IC for outputs 25 through 32 E18 amp E19 1 3 Sinking inputs with the ULN2803A IC for outputs 33 through 40 2 3 Sourcing outputs with the UDN2981A IC for outputs 33 through 40 E20 amp E21 1 4 Sinking inputs with the ULN2803A IC for outputs 41 through 48 2 3 Sourcing outputs with the UDN2981A IC for outputs 41 through 48 Hardware Address Limitations The ACC 10E has a hardware address limitation relative to the newer series of UMAC high speed IO cards The new IO cards have four addresses per chip select CS10 CS12 CS14 and CS16 This enables these cards to have up to 16 different addresses The ACC 9E ACC 10E ACC 11E and ACC 12E all have one address per chip select but also have the low byte middle byte and high byte type of addressing scheme and allows for a maximum of twelve of these IO cards UMAC Card Types UMAC Card Number of Category Maximum Card Addresses of cards Type ACC 9E ACC 10E 4 General IO 12 A ACC 11E ACC 12E ACC 65E ACC 66E 16 General IO 16 B ACC 67E ACC 68E ACC 14E ACC 28E ACC 36E 16 ADC and DAC 16 B ACC 59E ACC 53E ACC 57E 16 Feedback 16 B ACC
10. 32 J2 Top SE N 32 DB 15 Style Connector J1 Bottom Outputs 25 through 36 se ee ee ee ee Ge ee ee ee ee ee ee ee 32 JI BOMOMIC ONNOCION N ER RE M M X 32 DB 15 Style Connector J2 Bottom Outputs 37 through 48 ee sse 33 J2 Bottom Connector eese se ee ee ee ee AA ee RA ee Ge en ee AA tentent Ge ee AA ee ee ee Ge ee 33 Table of Contents Accessory 10E UnUn ee 35 PI UBUS 96 Pm Header rer tere patient ate rb eren 35 ii Table of Contents Accessory 10E INTRODUCTION The PMAC Accessory 10E is a general purpose output board to the UMAC Turbo or UMAC MACRO systems ACC 10E provides 48 lines of optically isolated outputs The actual I O writes are carried out using a special form of M variables which will be described later ACC 10E is one of the series of 3U rack I O accessories designed to transfer data through the UMAC BUS UBUS The other boards in the family of MACRO I O Accessory products include the following ACC 9E 48 optically isolated inputs ACC 10E 48 optically isolated outputs low power ACC 11E 24 inputs and 24 outputs low power all optically isolated ACC 12E 24 inputs and 24 outputs high power all optically isolated ACC 14E 48 bits TTL level VO Output Drivers The output drivers are organized in a set of six 8 bit groups Each group each byte may be ordered with e
11. 48 J2 Bottom Connector Front View 90000000 00000 0 Pin Notes l Sinking Sourcing 2 Sinking Sourcing 3 Sinking Sourcing 4 Sinking Sourcing 5 Sinking Sourcing 6 Sinking Sourcing 7 8 9 Sinking Sourcing 10 Sinking Sourcing 11 Sinking Sourcing 12 Sinking Sourcing 13 Sinking Sourcing 14 Sinking Sourcing 15 For sinking outputs use ULN2803A and jumper E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 from 1 2 For sourcing outputs use UDN2981A and jumper E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 from 2 3 I O Terminals 33 Accessory 10E 34 VO Terminals Accessory 10E UBUS PINOUTS P1 UBUS 96 Pin Header Front View Pin Row A Row B Row C 1 5Vdc 5Vdc 5Vdc 2 GND GND GND 3 BDO1 DATO BDOO 4 BDO3 SELO BD02 5 BD05 DATI BDO4 6 BD07 SELI BD06 7 BD09 DAT2 BD08 8 BD11 SEL2 BD10 9 BD13 DAT3 BD12 10 BD15 SEL3 BD14 11 BD17 DAT4 BD16 12 BD19 SEL4 BD18 13 BD21 DATS BD20 14 BD23 SELS BD22 15 BS1 DAT6 BSO 16 BAOI SEL6 BAOO 17 BAO3 DAT7 BAO2 18 BX Y SEL7 BAO4 19 CS3 BA06 CS2 20 BAOS BAO7 CS4 21 CS12 BA08 CS10 22 CS 16 BAO9 CS14 23 BA13 BA10 BA12 24 BRD BAI1 BWR 25 BS3 MEMCSO BS2 26 WAIT MEMCSI RESET 27 PHASE IREQI SERVO 28 PHASE IREQ2 SERVO 29 ANALOG GND IREQ3 ANALOG GND 30 15Vdc PWRGND 15Vdc 31 GND GND G
12. 48 Outputs Using 3X16 Bit Transfers eese 22 Example 2 48 Inputs 48 Outputs Using 1 X24 Bit Transfers esse see se ee see ek ee RA Ge ee Ge Re Re ee ee 23 Example 3 36 Inputs 36 Outputs Using 1X72 Bit Transfers eese 24 Setting up Control Word for MACRO TO sees se ee see Ge Ge ee enne enne Re etnies 25 APPENDIX MACRO Legacy Systems essere een eene remettre trennen trennen 26 EI E4 VO Gate Transfer Jumpers esse esse esse se se se ee see ee see etre Ge ee be ee be ee ee ee ee ee ee RA ee 26 VO TERMINALS wise sisie sesse M 29 TBI Top 12 Pin Terminal Block se se se eese Re ionieni sranna ee ee ee Re ee 29 TB2 Top 12 Pin Terminal Block eee sd se Es Eens sege Ee dee GE Ge ek De se RE ep ees gek Een EG Re SG EE eg 29 TBS Top 3 Pin Terminal BLOCK es aie gest eee eR Ge Ee se ER ek ee Ee be see GES ee GR ee n 30 TB1 Bottom 12 Pin Terminal Block se Re RR ER RA ER ee ER Re ee Ge ee ee Re ee RA ee ee nennen nen 30 TB2 Bottom 12 Pin Terminal Block se SR ee RR ER RA ER ee Ee Re enne ee Re ee ee RA ee ee ee ee ee 30 TB3 Bottom 3 Pin Terminal Block see se ER ee ER Re esee ee Re ER Re ee Ge AA ee Re ee AR Re ee nennen ee ee 3 DB15 Style Connector J1 Top Outputs 1 through 12 sese 31 JI TOP CONNEC EE ER AE EE EE 31 DB15 Style Connector J2 Top Outputs 12 through 24 ooo essere
13. 58E Devices Chip Select Addresses Chip UMAC Turbo MACRO UMAC Turbo MACRO Select Type A Card Type A Card Type B Card Type B Card 10 078C00 FFEO or 8800 078C00 079C00 8800 9800 07AC00 07BC00 A800 B800 12 078D00 FFE8 or 8840 078D00 079D00 8840 9840 07AD00 07BD00 A840 B840 14 078E00 FFFO or 8880 078E00 079E00 8880 9880 07AE00 07ECO0 A880 B880 16 078F00 88C0 078F00 079F00 88C0 98C0 07AF00 07BF00 A8C0 B8C0 4 Hardware Setup Accessory 10E Addressing Conflicts When just using only the type A UMAC cards or using only the type B UMAC cards in an application the user does not have to worry about potential addressing conflicts other than making sure the individual cards are set to the addresses as specified in the manual If the user has both type A and type B UMAC cards in their rack they should be aware of the possible addressing conflicts If the customer is using the Type A card on a particular Chip Select CS10 CS12 CS14 or CS16 then they cannot use a Type B card with the same Chip Select address unless the Type B card is a general IO type If the Type B card is a general IO type then the Type B card will be the low byte card at the Chip Select address and the Type A card s will be setup at as the middle byte and high byte addresses Type A and Type B Example 1 ACC 10E and ACC 36E If the user has an ACC 10E and ACC 36E the user cannot allow both cards to use the same Chip
14. 8 Y 078F02 0 8 VO bits 16 23 pio Y 5078C03 0 8 Y 078D03 0 8 Y 5078E03 0 8 Y 078F03 0 8 I O bits 24 31 e Y 078C04 0 8 Y 078D04 0 8 Y 5078E04 0 8 Y 5078F04 0 8 VO bits 32 39 E Y 5078C05 0 8 Y 078D05 0 8 Y 5078E05 0 8 Y 078F05 0 8 I O bits 40 47 Y 5078C07 0 8 Y 5078D07 0 8 Y 5078 07 0 8 Y 5078F07 0 8 Control Word Y 078C00 8 8 Y 078D00 8 8 Y 078E00 8 8 Y 078F00 8 8 I O bits 0 7 mt 1 5078C01 8 8 Y 078D01 8 8 Y 078E01 8 8 Y 078F01 8 8 I O bits 8 15 Sm Y 078C02 8 8 Y 078D02 8 8 Y 078E02 8 8 Y 078F02 8 8 I O bits 16 23 D E Y 078C03 8 8 Y 078D03 8 8 Y 078E03 8 8 Y 078F03 8 8 I O bits 24 31 en 5078C04 8 8 Y 078D04 8 8 Y 5078E04 8 8 Y 078F04 8 8 I O bits 32 39 He y 5078C05 8 8 Y 078D05 8 8 Y 078E05 8 8 Y 078F05 8 8 I O bits 40 47 Y 5078C07 8 8 Y 078D07 8 8 Y 5078E07 8 8 Y 078F07 8 8 Control Word Y 078C00 16 8 Y 078D00 16 8 Y 078E00 16 8 Y 078F00 16 8 I O bits 0 7 T Y 078C01 16 8 Y 078D01 16 8 Y 078E01 16 8 Y 078F01 16 8 I O bits 8 15 I Y 078C02 16 8 Y 078D02 16 8 Y 078E02 16 8 Y 078F02 16 8 VO bits 16 23 pe Y 078C03 16 8 Y 078D03 16 8 Y 078E03 16 8 Y 078F03 16 8 VO bits 24 31 S Y 5078C04 16 8 Y 078D04 16 8 Y 078E04 16 8 Y 078F04 16 8 I O bits 32 39 E Y 078C05 16 8 Y 078D05 16 8 Y 5078E05 16 8 Y 078F05 16 8 I O bits 40 47 Y 5078C07 16 8 Y 078D07 16 8 Y 078E07 16 8 Y 078F07 16 8 Control Word Data processing at these I O Gate Arrays is
15. Select because the data from both cards will be overwritten by the other card The solution to this problem is to make sure you do not address both cards to the same chip select Type A and Type B Example 2 ACC 10E and ACC 65E For this example the user could allow the two cards to share the same chip select because the ACC 65E is a general purpose IO Type B card The only restriction in doing so is that the ACC 65E must be considered the low byte addressed card and the ACC 10E must be jumpered to either the middle or high bytes jumper E6A E6H Hardware Setup 5 Accessory 10E Hardware Setup Accessory 10E USING ACC 10E WITH UMAC TURBO For the UMAC Turbo the ACC 10E can be used for general outputs only The registers used for the outputs are 8 bit registers and the user defines three 8 bit registers for each 24 bit I O port UMAC Turbo Memory Mapping for ACC 10E The Delta Tau I O Gate used on the ACC 10E is an 8 bit processor therefore the memory mapping to the I O bits is processed as 8 bit words at the Turbo UMAC Using this simple scheme you could process up to 576 144x4 bits of data for general purpose I O Jumper E1 Jumper E2 Jumper E3 Jumper E4 Description Y 078C00 0 8 Y 078D00 0 8 Y 078E00 0 8 Y 078F00 0 8 I O bits 0 7 T Y 078C01 0 8 Y 078D01 0 8 Y 078E01 0 8 Y 078F01 0 8 VO bits 8 15 Y 078C02 0 8 Y 078D02 0 8 Y 078E02 0
16. extremely fast If you were to map the machine I O to the ACC 10E memory locations you could do read or write bit wise or using 8 bit words Control Register The control register at address Base 7 permits the configuration of the IOGATE IC to a variety of applications The control register consists of 8 write read back bits Bits 0 7 The control register consists of two sections Direction Control and Register Select The direction control allows setting input bytes to be read only One of the advantages of the IOGATE IC is that we give the user the ability to define the bits as inputs or outputs This control mechanism allows the user to ensure the inputs will always be read properly Our traditional I O accessories always define the inputs and outputs by hardware The register select bits allow you to define the input or output bytes inversion control or the latching input features Since the ACC 10E does not have any input circuitry the control word for the ACC 67E should only be modified for direction control only Direction Control Bits Bits 0 to 5 of the control register simply control the direction of the I O for the matching numbered data register That is Bit n controls the direction of the I O at Base n A value of 0 in the control bit the default permits a write operation to the data register enabling the output Using Acc 10E with UMAC Turbo 7 Accessory 10E function for each line in the re
17. for the IO card at power up To accomplish this task a simple plc could be written to set up the control word properly For this example we will be setting up one ACC 11E ICO 24in 24out one ACC9E ICI 48 inputs and one ACC 10E IC2 48 outputs Control Word for ACC 10E M2007 Y 078C07 0 8 Hex 0 0 Binary 010101010101010 Bit 716151413 12 1110 AA Bits 0 7 are read write Bits 8 15 are read write Bits 16 23 are read write Bits 24 31 are read write Register Bits 32 39 are read write Select Bits 40 47 are read write 8 Using Acc 10E with UMAC Turbo Accessory 10E M2000 gt Y 078C00 0 8 I O bits 0 7 port A ICO M2001 gt Y 078C01 0 8 I O bits 8 15 port A ICO M2002 gt Y S5078C02 0 8 I O bits 16 23 port A ICO M2003 gt Y 078C03 0 8 I O bits 0 7 port B ICO M2004 gt Y 078C04 0 8 I O bits 8 15 port B ICO M2005 gt Y 078C05 0 8 I O bits 16 23 port B ICO M2006 gt Y 078Cc06 0 8 register selected M2007 gt Y 078Cc07 0 8 control register M2008 gt Y 078Cc00 8 8 I 0 bits 0 7 port A IC1 M2009 gt Y 078C01 8 8 I O bits 8 15 port A IC1 M2010 gt Y 078C02 8 8 I O bits 16 23 port A IC1 M2011 gt Y 078C03 8 8 I O bits 0 7 port B IC1 M2012 gt Y 078C04 8 8 I O bits 8 15 port B IC1 M2013 gt Y 078C05 8 8 I O bits 16 23 port B IC1 M2014 gt Y 5078C06 8 8 register selected M2015 gt Y S078C07 8 8 control register M2016 gt
18. gt X C0B0 0 24 M973 gt X 7842C 0 24 IO word 1 24 bit word node 7 M1000 gt X 0770 0 24 M1000 gt X 0010F0 0 24 Input mirror word 1 M1001 gt Y 0770 0 24 M1001 gt Y 0010F0 0 24 Input mirror word 2 M1002 gt X 0771 0 24 M1002 gt X 0010F1 0 24 Output mirror word 1 M1003 gt Y 0771 0 24 M1003 gt Y 0010F1 0 24 Output mirror word 2 M1010 gt X 0772 0 24 M1010 gt X 0010F2 0 24 Old Input mirror word 2 M1011 gt Y 0772 0 24 M1011 gt Y 0010F2 0 24 Old Input mirror word 3 0 MI975 CC 0 MI19 4 SAVEO 0 ANnNNNN 1000 M970 1001 M971 IF M1000 M1010 OR M1001 M1011 M1010 M1000 M1011 M1001 M973 M1002 M974 M1003 Output word ENDIF CLOSE 0 MI71 20C0A020 8800 enable node 2 3 6 sets up macro to transfer data for ACC 9E and 10E and 7 for I O at MACRO Station sets interrupt period for data transfer save to macro station reset macro station to enable OPEN PLC1 CLEAR new input mirror equal to actual input word new input mirror equal to actual input word if inputs change process outputs old input mirror equal to new input mirror old input mirror equal to new input mirror Set outputs based on inputs or program logic MACRO Station I O Transfer Output word equals Output Mirror Word equals Output Mirror Word 23 Accessory 10E Example 3 36 Inputs 36 O
19. with jumper E1 of ACC 11E selected MSO MI71 10C0A020 8800 2 96 bit I O transfer using nodes 2 3 6 and 7 jumper E1 of ACC 9E amp ACC 11E 72 inputs 24 outputs E6A E6H set to 1 2 on 1 board and E6A E6H set to 2 3 on 2 board MSO MI71 20C0A020 8800 3 144 bit I O transfer using nodes 2 3 6 7 10 and 11 using two ACC 9E 96 inputs and one ACC 10E 48 outputs Jumpers E1 on all ACC 9E selected and jumpers E1 on all ACC 10Es selected Jumpers E6A E6H selected 1 2 2 3 4 5 on Boards 1 2 and 3 respectively MSO MI71 30C0A020 8840 MI169 and MI170 specify the registers used in 72 bit I O transfers between one MACRO node interface register and I O registers on a MACRO station They are used only if MI19 is greater than 0 MI169 and MI170 are 48 bit variables represented as 12 hexadecimal digits The first 6 digits specify the address of 72 bit 24 amp 3 x 16 bit real time MACRO node register to be used The second 6 digits specify the address of the LOWER I O Gate on an Option 3 or Option 4 board to be used MACRO Station I O Transfer 15 Accessory 10E The individual digits are specified as follows Digit Possible Values Description 1 0 Reserved for future use 2 0 Reserved for future use 3 6 COAO Node 2 COA4 Node 3 MACRO Station X Address of MACRO I O node 24 bit COA8 Node 6 COAC Node 7 registers COBO Node 10 COB4 Node 11 7 0 Reserved for future use
20. 0 E4 88C0 078F00 E5 VO Gate Data Clock Select Jumper Function ES Servo Clock 2 3 Phase Clock default E6A E6H Layout Diagram 1 2 3 90000 00000800 gt 0e00000 lt m o a LLI LL Oo I D dd id du d i d 8 E6A E6H Node Select Jumpers Jumper Setting UMAC MACRO UMAC Turbo E6A E6H 1 2 Ist VO node set by MI69 Uses Bits 0 7 for six default and MI70 consecutive memory 1st and 2nd node by MI7I locations 48 bits E6A E6H 2 3 or 3 4 2nd I O node set by MI69 Uses Bits 8 15 for six and MI70 consecutive memory 3rd and 4th node by MI71 locations 48 bits E6A E6H 4 5 3rd I O node set byMI69 and Uses Bits 16 23 for six MI70 consecutive memory 5th and 6th node by MI71 locations 48 bits Could be different if Delta Tau built and tested the UMAC at the factory Example If the UMAC MACRO Rack specified two ACC 9E s one board would have EGA E6H jumpered 1 2 and the next board would be jumpered 2 3 etc Hardware Setup Accessory 10E E10 E21 Sinking or Sourcing Output Select Jumpers Description E10 amp Ell 1 2 Sinking inputs with the ULN2803A IC for outputs through 8 2 3 Sourcing outputs with the UDN2981A IC for outputs through 8 E12 amp E13 1 2 Sinking inputs with the ULN2803A IC for outputs 9 through 16 2 3 Sourcing outputs with the UDN2981A IC for outputs 9 through
21. 07 High word CS10 Y 8840 FFE8 Y 8847 0 8 MI198 40 8847 Low word CS12 Y 58847 8 8 MI198 48 8847 Middle word CS12 Y 8847 16 8 MI198 50 8847 High word CS12 Y 8880 FFFO Y 58887 0 8 MI198 4058887 Low word CS14 Y 58887 8 8 MI198 485 8887 Middle word CS14 Y 58887 16 8 MI198 50 8887 High word CS14 Y 88C0 Y S88C7 0 8 MI198 40 88C7 Low word CS16 Y S88C7 8 8 MI198 48 88C7 Middle word CS16 Y 588C7 16 8 MI198 50 88C7 High word CS16 for legacy systems Once we have the control word defined to MI 198 we can write to the individual bytes associated with the IO gate and make them either read only or read write default Byte 0 Byte 1 Byte 2 Byte 3 Byte4 Byte 5 Y 8800 0 8 Y 8801 0 8 Y 8802 0 8 Y 8803 0 8 Y 8804 0 8 Y 8805 0 8 Y 8800 8 8 Y 8801 8 8 Y 8802 8 8 Y 8803 8 8 Y 8804 8 8 Y 8805 8 8 Example MACRO Station has ACC 10E 48 out and ACC 11E 24in 24out set to base addresses 8800 0 8 and 8800 8 8 respectively define Timer 15111 plc countdown timer for Turbo Ultralite define Timerl M70 plc countdown timer for Ultralite MACRO Station I O Transfer 25 Accessory 10E M70 X 0700 0 24 8 countdown timer for non turbo PMAC Open PLC 10 Clear Timer1 2000 8388608 110 72 second delay to ensure MACRO While Timerl gt 0 Endwhile Station is powered up properly
22. 0F1 8 16 Output mirror word 2 M1004 gt Y 0771 8 16 M1004 gt Y 0010F1 8 16 Output mirror word 3 M1010 gt X 0771 0 24 M1010 gt X 0010F2 0 24 Old Input mirror word 1 M1011 gt Y 0771 8 12 M1011 gt Y 0010F2 8 12 Old Input mirror word 2 sets up macro to transfer data for ACC 11E sets interrupt period for data transfer new input mirror equal to actual input word if inputs change process outputs old input mirror equal to new input mirror old input mirror equal to new input mirror based on inputs or program logic word equals Output Mirror Word Use Only word equals Output Mirror Word word equals Output Mirror Word S0 MI169 00C0A000 8800 S0 MI975 4 enable node 2 for I O S0 MI19 4 SSAVEO save to macro station S 0 reset macro station to enable OPEN PLC1 CLEAR 1000 M970 1001 M981 amp S0FFF use only lower 12 bits IF M1000 M1010 OR M1001 M1011 M1010 M1000 M1011 M1001 Set outputs M983 M1001 amp F000 Output Upper 4 Bits M984 M1002 Output M985 M1003 Output ENDIF CLOSE 24 MACRO Station I O Transfer Accessory 10E Setting up Control Word for MACRO IO The Delta Tau IO gate array used on the UMAC IO accessories has the ability to allow any of the 48 bits be used as an input read or an output write To protect the inputs to be read only the user can define the individual bits as read only on a byte by byte basis T
23. 18 ACC 4E board MACRO Station Y Base Address of ACC 9E ACC 10E ACC 11E ACC 12E and ACC 13E for legacy systems When this function is active the MACRO Station will copy values from the MACRO command input node registers to the I O board addresses it will copy values from the I O board addresses to the MACRO feedback output node registers Writing a 0 to a bit of the I O board enables it as an input letting the output pull high Writing a 1 to a bit of the I O board enables it as an output pulling the output low The following table shows the mapping of I O points on the I O piggyback boards to the MACRO node registers I O points move from the least significant bit to the most significant bit VOOO at Node bit 0 VO Point s Option 3 Part Present on Option 4 Matching MACRO X Register I O00 1 015 Sub option A Yes Specified MACRO X Address 1 1 016 1 031 Sub option A Yes Specified MACRO X Address 2 1 032 1 047 Sub option A Yes Specified MACRO X Address 3 1 048 1 063 Sub option B No Specified MACRO X Address 5 1 064 1 079 Sub option B No Specified MACRO X Address 6 1 080 1 095 Sub option B No Specified MACRO X Address 7 1 096 1 0119 Sub option C No Specified MACRO X Address 0 1 0120 1 0143 Sub option C No Specified MACRO X Address 4 Example 1 Transfer 72 bits I O transfers using nodes 2 and 3 MSO MI171 00C0
24. 25 8002 gt Y 078C00 2 1 Output 2 8026 gt Y 078C03 2 1 Output 26 8003 gt Y 078C00 3 1 Output 3 8027 gt Y 078C03 3 1 Output 27 8004 gt Y 078C00 4 1 Output 4 8028 gt Y 078C03 4 1 Output 28 8005 gt Y 078C00 5 1 Output 5 8029 gt Y 078C03 5 1 Output 29 8006 gt Y 078C00 6 1 Output 6 8030 gt Y 078C03 6 1 Output 30 8007 gt Y 078C00 7 1 Output 7 8031 gt Y 078C03 7 1 Output 31 8008 gt Y 078C01 0 1 Output 8 8032 gt Y 078C04 0 1 Output 32 8009 gt Y S078C01 1 1 Output 9 8033 gt Y 078C04 1 1 Output 33 8010 gt Y 078C01 2 1 Output 10 8034 gt Y 078C04 2 1 Output 34 8011 gt Y 078C01 3 1 Output 11 8035 gt Y 078C04 3 1 Output 35 8012 gt Y 078C01 4 1 Output 12 8036 gt Y 078C04 4 1 Output 36 8013 gt Y 078C01 5 1 Output 13 8037 gt Y 078C04 5 1 Output 37 Using Acc 10E with UMAC Turbo 9 Accessory 10E 8038 gt Y S078C04 6 1 Output 38 8039 gt Y 078C04 7 1 Output 39 8040 gt Y 078C05 0 1 Output 40 8041 gt Y 078C05 1 1 Output 41 8042 gt Y 5078C05 2 1 Output 42 8043 gt Y 078C05 3 1 Output 43 8044 gt Y 5078C05 4 1 Output 44 8045 gt Y 078C05 5 1 Output 45 8046 gt Y 078C05 6 1 Output 46 8047 gt Y 5078C05 7 1 Output 47 8014 gt Y 5 078C01 6 1 Output 14 8015 gt Y 078C01 7 1 Output 15 8016 gt Y 078C02 0 1 Output 16 8017 gt Y 078C02 1 1 Output 17 8018 gt Y 078C02 2 1 Output 18 8019 gt Y 078C02 3 1 Output 19 8020 gt Y 078C02 4 1 Output 20 8021
25. 3 M129 gt X 772 13 M937 gt Y 772 13 M906 gt Y 771 14 M922 gt X 772 14 M938 gt Y 772 14 M907 gt Y 771 15 M923 gt X 772 15 M939 gt Y 772 15 M908 gt Y 771 16 M924 gt X 772 16 M940 gt Y 772 16 M909 gt Y 771 17 M925 gt X 772 17 M941 gt Y 772 17 M910 gt Y 771 18 M926 gt X 772 18 M942 gt Y 772 18 M911 gt Y 771 19 M927 gt X 772 19 M943 gt Y 772 19 M912 gt Y 771 20 M928 gt X 772 20 M944 gt Y 772 20 M913 gt Y 771 21 M129 gt X 772 21 M945 gt Y 772 21 M914 gt Y 771 22 M930 gt X 772 22 M946 gt Y 772 22 M915 gt Y 771 23 M931 gt X 772 23 M947 gt Y 772 23 20 MACRO Station I O Transfer Accessory 10E PMAC2 Turbo Ultralite Example M Variable Definitions SE EE SESSE M980 gt X 78421 8 16 IO word 1 1st 16 bit word node2 M981 gt X 78422 8 16 IO word 2 2nd 16 bit word node 2 M982 gt X 78423 8 16 IO word 3 3rd 16 bit word node 2 M983 gt X 78425 8 16 IO word 1 1st 16 bit word node 3 M984 gt X 78426 8 16 IO word 2 2nd 16 bit word node 3 M985 gt X 78427 8 16 IO word 3 3rd 16 bit word node 3 1000 X 0010F0 8 16 Input mirror word 1 1001 Y 0010F0 8 16 Input mirror word 2 L002 X 5 0010F1 8 16 Input mirror word 3 LOO3 Y SOO1OF1 8 16 Output mirror word 1 L004 X 5 0010F2 8 16 Output mirror word 42 L005 Y 5 0010F2 8 16 Output mirror word 3 1010 gt X 0010F3 8 16 Old I
26. 31 X 079432 X 079433 IC1 11 27 X 079434 X 079435 X 079436 X 079437 IC2 2 34 X 078420 X 07A421 X 07A422 X 07 A423 IC2 3 35 X 07A424 X 07A425 X 07A426 X 07A427 IC2 6 38 X 07A428 X 07A429 X 07A42A X 07A42B IC2 7 39 X 07A42C X 07A42D X 07 A42E X 07A42F IC2 10 42 X 07A430 X 07A431 X 07A432 X 07A433 IC2 11 43 X 07A434 X 07A435 X 07A436 X 07A437 IC3 2 50 X 07B420 X 07B421 X 07B422 X 07B423 IC3 3 51 X 07B424 X 07B425 X 07B426 X 07B427 IC3 6 54 X 07B428 X 07B429 X 07B42A X 07B42B IC3 7 55 X 07B42C X 07B42D X 07B42E X 07B42F IC3 10 58 X 07B430 X 07B431 X 07B432 X 07B433 IC3 11 59 X 07B434 X 07B435 X 07B436 X 07B437 Example If you wanted to read the inputs from the MACRO Station of the first 24 bit I O node address of node 2 X C0A0 then he she could point an M variable to the Ultralite or TURBO Ultralite I O node registers to monitor the inputs M980 gt X SC0A0 0 24 Ultralite node address M1980 X 078420 0 24 Turbo Ultralite MACRO ICO node 2 address These M variable definitions M980 or M1980 could then be used to monitor the inputs for either the Ultralite or Turbo Ultralite MACRO VO Software Settings 12 MACRO Station I O Transfer Accessory 10E The MACRO Station I O can be configured as either an input or an output The hardware connected to the MACRO I O boards determines whether or not the address
27. A00 8800 MACRO Station I O Transfer 17 Accessory 10E Reading and Writing to Node Addresses Delta Tau recommends that you read and write to the node address as complete words If the node address is 24 bits wide or 16 bits wide read or write to the M Variable assigned to that address Example Ultralite Turbo Ultralite M970 gt X C0A0 0 24 M970 gt X 78420 0 24 M980 gt X C0A 1 8 16 M980 gt X 78421 8 16 M981 gt X C0A2 8 16 M981 gt X 78422 8 16 M982 gt X C0A3 8 16 M982 gt X 78423 8 16 M1000 gt X 0770 0 24 M1000 gt X 0010F0 0 24 image word M1001 gt X 0771 8 16 M1001 gt X 0010F0 8 16 image word For Outputs M970 F00011 sets bits 0 4 20 21 22 amp 23 M980 8101 sets bits 0 8 amp 23 M970 M1000 sets M970 equal to M1000 M980 M1001 sets M980 equal to M1001 For Inputs M1000 M970 sets M1000 equal to M970 M1001 M980 sets M1001 equal to M980 If using the 48 bit read write method it would be ideal if the inputs and outputs were used in multiples of 16 Example 48 inputs 32 inputs 16 outputs 16 inputs 32 outputs or 48 output see Example 1 If the 16 bit word is to be split 8 in and 8 out then we would read the word at the beginning of the PLC and write the word at the end of the PLC However instead of writing the value of the inputs to the output word you must write zeros to all input bits of this in out word s
28. ND 32 5Vdc 5Vdc 5Vdc For more details about the JEXP see the UBUS Specification Document UBUS Pinouts 35
29. USER MANUAL Accessory LOE DELTA TAU Data Systems Inc NEW IDEAS IN MOTION Single Source Machine Control Power Flexibility Ease of Use 21314 Lassen Street Chatsworth CA 91311 Tel 818 998 2095 Fax 818 998 7807 www deltatau com Copyright Information 2003 Delta Tau Data Systems Inc All rights reserved This document is furnished for the customers of Delta Tau Data Systems Inc Other uses are unauthorized without written permission of Delta Tau Data Systems Inc Information contained in this manual may be updated from time to time due to product improvements etc and may not conform in every respect to former issues To report errors or inconsistencies call or email Delta Tau Data Systems Inc Technical Support Phone 818 717 5656 Fax 818 998 7807 Email support deltatau com Website http www deltatau com Operating Conditions All Delta Tau Data Systems Inc motion controller products accessories and amplifiers contain static sensitive components that can be damaged by incorrect handling When installing or handling Delta Tau Data Systems Inc products avoid contact with highly insulated materials Only qualified personnel should be allowed to handle this equipment In the case of industrial applications we expect our products to be protected from hazardous or conductive materials and or environments that could cause harm to the controller by damaging components or causing e
30. Y 078C00 1 M2017 gt Y 078C01 1 M2018 gt Y 078C02 1 M2019 gt Y 078C03 1 M2020 gt Y 078C04 1 M2021 gt Y 078C05 1 M2022 gt Y 078C06 1 I O bits 0 7 port A IC2 I O bits 8 15 port A IC2 I O bits 16 23 port A IC2 I O bits 0 7 port B IC2 I O bits 8 15 port B IC2 I O bits 16 23 port B IC2 register selected Ov OD OV OV OO OY OY ae N AE AR AE AE AK CO CO OO OO OO CO CO M2023 gt Y S078C07 1 control register M2007 gt Y 078C07 0 8 control word for 78C00 0 8 78C05 0 8 M2015 gt Y 078C07 8 8 control word for 78C00 8 8 78C05 8 8 M2023 gt Y 078C07 16 8 control word for 78C00 16 8 78C05 16 8 S PLC to initialize read write I O bits OPEN PLC 1 CLEAR M2007 07 define bits 0 23 as inputs and bits 24 47 as outputs ACC 11E M2015 3F define bits 0 23 and 24 47 as inputs ACC 9E M2023 S00 define bits 0 23 and 24 47 as outputs ACC 10E DIS PLCI1 CLOSE Accessory 10E I O M Variables for UMAC Turbo The following is a list of suggested M variables for the default jumper settings is provided You may assign any M variables to these addresses The user may make these M variable definitions and use them as general purpose I O for their PLC s or motion programs 8000 gt Y 078C00 0 1 Output 0 8024 gt Y 078C03 0 1 Output 24 8001 gt Y 078C00 1 1 Output 1 8025 gt Y 078C03 1 1 Output
31. ack output node registers Writing a 0 to a bit of the I O board enables it as an input letting the output pull high Writing a 1 to a bit of the I O board enables it as an output and pulls the output low Example 1 48 bit VO transfer using node 2 with jumper E1 of ACC 11E selected MSO MI69 10C0A130 8800 2 96 bit VO transfer using nodes 2 amp 3 jumper E1 of ACC 9E amp ACC 11E 72 inputs 24 outputs E6A E6H set to 1 2 on 1 board and E6A E6H set to 2 3 on 2 board MSO MI69 20C0A130 8800 3 288 bit VO transfer using nodes 2 3 6 7 10 and 11 using 3 ACC 9Es 144 inputs and 3 ACC 10Es 144 outputs Jumpers E1 on all ACC 9Es selected and jumpers E2 on all ACC 10Es selected Jumpers E6A E6H selected 1 2 2 3 4 5 on ACC 9E Input Boards 1 2 and 3 respectively Jumpers E6A E6H selected 1 2 2 3 4 5 on ACC 10E Output Boards 1 2 and 3 respectively MSO MI69 30C0A130 8800 MSO MI70 30C0AD30 8840 MT71 specifies the registers used in 24 bit I O transfers between MACRO I O node interface registers and I O registers on the MACRO Station I O accessory board It is used only if MI19 is greater than 0 MI71 is a 48 bit variable represented as 12 hexadecimal digits The first 6 digits specify the number and address of 48 bit real time MACRO node register sets to be used The second 6 digits specify the number and address of 48 bit I O sets on the MACRO Station I O accessory board to be used 14 MACRO Stati
32. anvvnnvrvrnnvrernsnervaenennsrsrnnereresnesvarnernsssrnnereresnen Control Register ita e det ee EA OE OE OE OE ER Direction Control AR RE tke EE RERUESFURS AES RC AHR E Ee Eo ue e Eripe n Me eee ERR ERRARE Register Select Control Bits eese esee enne ee Ge tenete trennen testen n trente enne ee enne Control Word Setup Example eese eene tenente enne Ged Ge ee Ge ee ee ee ee ee Accessory 10E I O M Variables for UMAC Turbo eese eene MACRO STATION VO TRANSFER e eeeeeeee se ese sees se Ee Se Ee tasas tasses suse tasa suse tasse Be Ee enses tuse ee 11 MACRO T O Gate LOCGHONS ei oce erste teats tenter ee uet eb i Ene NR dederit tuenda 11 MACRO Station I O Node Transfer Addresses eese netten nennen Il PMAC2 Ultralite VO Node Addresses ee ee ee Re GR GRA RA Ge ee ee ee Ee ee ee ee ee Re ee ee enne 12 PMAC2 Turbo Ultralite VO Node Addresses essere ene 12 MACRO W O Software Settings iic rettet pee LED EE OO EN 12 Reading and Writing to Node Addresses srernrnvvvnvvvnvvvnnvrrvvrrnrvenrveraveravernrnrrvrnsvrnevrnsnenvnessvesnvenvessvessvsse 18 ad EE 18 In DNI E 18 Active Nodes for Compact MACRO I O Station esee entente nennen 19 PMAC2 Ultralite Example M Variable Definitions eese 20 PMAC2 Turbo Ultralite Example M Variable Definitions esee 21 Example 1 48 Inputs
33. ee Example 3 This is because writing a value of 1 to a MACRO I O register makes that I O bit an output only bit Example Setup System Configuration 8 axis PWM System w 96 bit I O 48 inputs amp 48 outputs ACC 11E PMAC Ultralite Setup I996 FB33F activates nodes 1 2 3 4 5 8 9 12 and 13 at Ultralite TURBO PMAC Ultralite Setup 16841 SFB33F activates nodes 1 2 3 4 5 8 9 12 and 13 at Turbo Ultralite Macro Station Definitions MS0 MI69 20C0A130 8800 sets up macro to transfer data for ACC11E MS0 MI975 C enable node 2 and 3 for I O MSO MI19 4 sets interrupt period for data transfer MSSAVEO save to macro station MS 0 reset macro station to enable 18 MACRO Station I O Transfer Accessory 10E Active Nodes for Compact MACRO VO Station Option Node s Gate Addresses Node Transfer Addresses 48 Bit 2 8800 C0A1 C0A2 COA3 96 Bit 2 3 8800 COAI COA2 COA3 8802 C0A5 C0A6 COA7 144 Bit 2 3 6 8800 COAI COA2 COA3 8802 C0A5 C0A6 COA7 8804 C0A9 COA A SCOAB The data in this application will transfer 48 bits of data per node as specified by MI69 These memory locations could be utilized by pointing an M variable to the node locations In your PLC program these M variables would be considered the actual input words and actual output words or a combination of the two 8 inputs 8 outputs for 16 bit read write To efficiently read and write
34. es defined are inputs or outputs Each I O node has 72 bits of data to be transferred automatically to the Ultralite As stated previously there are three methods of transfer 3x16 bit 1x24 bit or 72 bit transfer There are several variables at the MACRO Station and PMAC2 Ultralite that enable the I O data transfer Once these variables are set to the appropriate values you can then process the data like a normal PMAC or PMAC2 The variables to be modified at the MACRO Station are MI19 MI69 MI70 MI71 MI169 MI170 MI171 MI172 MI173 MI975 and MI996 The Ultralite must have 1996 modified to enable the I O nodes used Can only be used with MACRO Station firmware version 1 112 or greater MI19 controls the data transfer period on a Compact MACRO Station between the MACRO node interface registers and the I O registers as specified by station MI variables MI20 through MI71 If MI19 is set to 0 this data transfer is disabled If MI19 is greater than 0 its value sets the period in Phase clock cycles the same as MACRO communications cycles at which the transfer is done MI975 permits the enabling of MACRO I O nodes on the Compact MACRO Station MI975 is a 16 bit value bits 0 to 15 with bit n controlling the enabling of MACRO node n If the bit is set to 0 the node is disabled if the bit is set to 1 the node is enabled The I O nodes on the Compact MACRO Station are nodes 2 3 6 7 10 and 11 which can be enabled by MI975 bits of
35. gister Enabling the output function does not prevent the use of any or all of the lines as inputs as long as the outputs are off non conducting A value of 1 in the control bit does not permit a write operation to the data register disabling the output reserving the register for inputs For example a value of 1 in Bit 3 disables the write function into the data register at address Base 3 ensuring that lines IO24 IO31 can always be used as inputs Register Select Control Bits Bits 6 and 7 of the control register together select which of 4 possible registers can be accessed at each of the addresses Base 0 through Base 5 They also select which of 2 possible registers can be selected at Base 6 The following table explains how these bits select registers Bit 7 Bit 6 Combined Base 0 to Base 5 Base 6 Register Value Register Selected Selected 0 0 0 Data Register Data Register 0 1 1 Setup Register 1 Setup Register 1 0 2 Setup Register 2 n a 1 1 3 Setup Register 3 n a In a typical application non zero combined values of Bits 6 and 7 are only used for initial configuration of the IC These values are used to access the setup registers at the other addresses After the configuration is finished zeros are written to both Bits 6 and 7 so the data registers at the other registers can be accessed Control Word Setup Example You need to set up the control words
36. gt Y 078C02 5 1 Output 21 8022 gt Y 078C02 6 1 Output 22 8023 gt Y 078C02 7 1 Output 23 P Sample E Stop PLC r f IF En IF En Cl 10 the motors when This PLC will abort all motion programs and kill the bus voltage to E stop is depressed When E Stop button in pulled out the motors will servo to actual position lt ctrl gt A command after allowing 5 seco P7000 used M7000 used M8000 used I5111 used EN PLC 5 CLI EAR M7000 1 a CMD A nd P7000 0 15111 500 8388608 110 WHILE 1511150 ENDWHILI CMD K M8000 0 P7000 1 dif ea M7000 0 and P7000 1 M8000 1 15111 5000 8388608 110 WHILE I5 CMD A P7000 0 dif ose REI 111 gt 0 ENDWHILI nds for proper bus voltage as a Latch variable Emergency Stop Input from ACC 9E as Main Contact for main AC for Bus Voltage as count down timer emergency stop condition global motion program abort 500 msec delay for deceleration kill all axes turn off BUS voltage latch input enable BUS voltage 5000 msec delay for bus voltage close loop for all servos latch input Using Acc 10E with UMAC Turbo Accessory 10E MACRO STATION I O TRANSFER A fundamental understanding of the MACRO Station I O transfer is needed to set up the MACRO I O family of accessories Typically the MACRO station will have up to eight axis nodes 0 1 4 5
37. his accomplished by writing to the control word of the IO gate Each IO gate has eight 8 bit words IO word 0 O bits 0 7 IO word 1 O bits 8 15 IO word 2 O bits 16 23 IO word 3 O bits 24 31 IO word 4 IO bits 32 39 IO word 5 TO bits 40 47 IO word 6 Data Word IO word 7 Control Word IO words 0 through 5 contain the actual IO data IO word 7 is the control word that allows us to turn any of the IO words into read only bits The lower 6 bits of the Control Word are used to tell the IO gate whether or not the data in the six IO word bytes are read only or read write registers For example if the user wanted to make IO word 0 IO word 1 and IO word 2 bits 0 23 read only they would have to set the IO control word equal to 7 binary 000111 As of MACRO firmware release 1 16 there are no MI variables to support direct access to the IO control words An easy method can be used to write directly to the control word of the IO gate using MI198 and MI199 place the register you want to read or write to into MI198 and the read or write to that value using MI199 This will usually be done in a one time read PLC at power up Base Address Control Word MI198 Setting Description from E2 Setting Location Y 8800 FFEO Y 58807 0 8 MI198 40 8807 Low word CS10 Y 58807 8 8 MI198 485 8807 Middle word CS10 Y 58807 16 8 MI198 50 88
38. ither current sourcing drivers default or with current sinking drivers The default configuration of this accessory board uses UDN2981 current sourcing drivers for the six 8 bit output groups With this configuration the current drawn from each output line should be limited to 100 mA at voltage levels between 12 and 24 volts Custom configurations are available for current sinking applications In current sinking configurations one ULN2803 driver is used per each 8 bit output group Each open collector output line can sink up to 100 mA when pulled up to a voltage level between 12 and 24 volts external pull up resistors are not supplied Sinking Outputs Sourcing Outputs OUTPUT CHIP EQUIVALENT OUTPUT CHIP EQUIVALENT CIRCUIT ULN2803 FOR SINKING CIRCUIT UDN2981 FOR SOURCING V V 2 lt a 4 lt 4 i Ji 4 2 3K INVERTING OPEN COLLECTOR SINKING 12 24V 14 S gt gt A b 15k NON INVERTING SOURCING 12 24V Introduction 1 Accessory 10E Introduction Accessory 10E HARDWARE SETUP The Accessory 10E must have several jumpers configured to work properly with other I O cards in the ring The jumpers used on this board will select the starting I O Gate Array transfer address and the MACRO Station I O Node to be transferred to E1 E4 VO Gate Transfer Jumpers Jumper UMAC MACRO UMAC Turbo El 8800 or FFEO 078C00 default E2 8840 or FFE8 078D00 E3 8880 or FFFO 078E0
39. king Sourcing Sinking Sourcing Sinking Sourcing Sinking Sourcing Sinking Sourcing 10 Sinking Sourcing 11 Sinking Sourcing 12 Sinking Sourcing This terminal block provide the inputs 37 48 for the ACC 10E Input Card For sinking outputs use ULN2803A and jumper E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 from 1 2 For sourcing outputs use UDN2981A and jumper E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 from 2 3 oo I AIM EIE o 30 I O Terminals Accessory 10E TB3 Bottom 3 Pin Terminal Block sla Top View 3 3 A Pin Symbol Function Description Notes 1 GND2 Reference Reference voltage 2 V2 Voltage 12 24V 3 GND2 Reference Reference voltage This terminal block can be used to provide the input reference for the ACC 10E for the second 24 outputs DB15 Style Connector J1 Top Outputs 1 through 12 J1 Top Connector Front View 0000000 200000 0 Pin Notes Sinking Sourcing Sinking Sourcing Sinking Sourcing Sinking Sourcing Sinking Sourcing Sinking Sourcing Sinking Sourcing 10 Sinking Sourcing 11 Sinking Sourcing 12 Sinking Sourcing 13 Sinking Sourcing 14 Sinking Sourcing 15 For sinking outputs use ULN2803A and jumper E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 from 1 2 For sourcing outputs use UDN2981A and jumper E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 fr
40. lectrical shorts When our products are used in an industrial environment install them into an industrial electrical cabinet or industrial PC to protect them from excessive or corrosive moisture abnormal ambient temperatures and conductive materials If Delta Tau Data Systems Inc products are directly exposed to hazardous or conductive materials and or environments we cannot guarantee their operation Accessory 10E Table of Contents INTRODUCTION T Output Drivers P Is EL 3C 04 M UJ LONE El E4 VO Gate Transfer JUMPe rs ccccssesccvessessevoscsonssonsseievevserssusosisenveauseasteassatevesterveusosegueveansabesee deu E5 VO Gate Data Clock Select its Rit esee etii icis Ode Ced esee eoe asco ede E6A E6H Node Select Jumpers sees se ese se ese ee ee ee ge ee nete nennen ede AA Ge Re Ge ee Ge ee ene E10 E21 Sinking or Sourcing Output Select sees se esse ese ee se ee se ee ee ee Ge Se Re Se ed Ged Gee Se ee ee Hardware Address Limitations OR ER ER EE ER NG Addressing Conflicts RE EE EE OR M Type A and Type B Example 1 ACC 10E and ACC 36E ees sesse see se ese ee esse see se ee se ee ee ee ee ee se ee Type A and Type B Example 2 ACC 10E and ACC 65E sess USING ACC 10E WITH UMAC TURBDO eee reete se Ee Be EE Be Ee GEE Be EE SEE suse tasse Be EG Gee Ge ee se UMAC Turbo Memory Mapping for ACC 10B nsrnnorvevnvrv
41. mage mirror word 1 1011 gt Y 0010F3 8 16 Old Image mirror word 2 1012 gt X S0010F4 8 16 Old Image mirror word 3 IO word 1 IO Word 2 IO Word 3 M800 gt X 0010F0 8 M801 gt X 0010F0 9 M802 gt X 0010F0 10 M803 gt X 0010F0 I 1 M804 gt X 0010F0 12 M805 gt X 0010F0 13 M806 gt X 0010F0 14 M807 gt X 0010F0 15 M808 gt X 0010F0 16 M809 gt X 0010F0 17 M810 gt X 0010F0 18 M811 gt X 0010F0 19 M812 gt X 0010F0 20 M813 gt X 0010F0 21 M814 gt X 0010F0 22 M815 gt X 0010F0 23 M816 gt Y 0010F0 8 M817 gt Y 0010F0 9 M818 gt Y 0010F0 10 M819 gt Y 0010F0 I I M820 gt Y 0010F0 12 M829 gt Y 0010F0 13 M822 gt Y 0010F0 14 M823 gt Y 0010F0 15 M824 gt Y 0010F0 16 M825 gt Y 0010F0 17 M826 gt Y 0010F0 18 M827 gt Y 0010F0 19 M828 gt Y 0010F0 20 M829 gt Y 0010F0 21 M830 gt Y 0010F0 22 M831 gt Y 0010F0 23 M832 gt X 0010F 1 8 M833 gt X 0010F1 9 M834 gt X 0010F1 10 M835 gt X 0010F1 I I M836 gt X 0010F1 12 M837 gt X 0010F1 13 M838 gt X 0010F1 14 M839 gt X 0010F1 15 M840 gt X 0010F1 16 M841 gt X 0010F1 17 M842 gt X 0010F1 18 M843 gt X 0010F1 19 M844 gt X 0010F1 20 M845 gt X 0010F1 21 M846 gt X 0010F1 22 M847 gt X 0010F1 23 IO word 4 IO Word 5 IO Word 6 M900 gt Y 0010F1 8 M901 gt Y 0010F1 9 M902 gt Y 0010F1 10 M903 gt Y 0010F1 11 M904 gt Y 0010F 1 12 M905 gt Y 0010F 1 13 M906 gt Y
42. om 2 3 OD II DI MIELIE o I O Terminals 31 Accessory 10E DB15 Style Connector J2 Top Outputs 12 through 24 J2 Top Connector Front View o ooooooco 0000000 18 Pin Notes Sinking Sourcing Sinking Sourcing Sinking Sourcing Sinking Sourcing Sinking Sourcing Sinking Sourcing 9 Sinking Sourcing 10 Sinking Sourcing 11 Sinking Sourcing 12 Sinking Sourcing 13 Sinking Sourcing 14 Sinking Sourcing 15 For sinking outputs use ULN2803A and jumper E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 from 1 2 For sourcing outputs use UDN2981A and jumper E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 from 2 3 DB15 Style Connector J1 Bottom Outputs 25 through 36 OJR IAU EI J1 Bottom Connector Front View 500000090 Pin Notes Sinking Sourcing Sinking Sourcing Sinking Sourcing Sinking Sourcing Sinking Sourcing Sinking Sourcing Sinking Sourcing 10 Sinking Sourcing 11 Sinking Sourcing 12 Sinking Sourcing 13 Sinking Sourcing 14 Sinking Sourcing 15 For sinking outputs use ULN2803A and jumper E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 from 1 2 For sourcing outputs use UDN2981A and jumper E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 from 2 3 oo LAMEER o 32 I O Terminals Accessory 10E DB15 Style Connector J2 Bottom Outputs 37 through
43. on I O Transfer Accessory 10E The individual digits are specified as follows Digit Possible Values Description 1 0 1 2 3 Number of MACRO I O nodes to use times 2 0 disables this should also match the number of 48 bit I O sets you intend to use see Digit 7 2 0 Reserved for future use 3 6 COAO Node 2 COA4 Node 3 MACRO Station X Address of MACRO I O node first of three COA8 Node 6 COAC Node 7 16 bit registers COBO Node 10 COB4 Node 11 7 0 1 2 Number of 24 bit I O sets to use 1x24 2x24 0 disables 8 1 Set to 1 for ACC 14E ACC 65E ACC 66E ACC 67E consecutive address read Base 1000 2000 9 12 FFCO FFC8 FFDO FFD8 MACRO Station Y Base Address of I O Board as set by Board Jumper E1 E4 ACC 3E board or E15 E18 ACC 4E board 8800 8840 8880 88CO MACRO Station Y Base Address of ACC 9E ACC 10E FFEO FFE8 FFFO ACC 11E ACC 12E and ACC 13E for legacy systems When this function is active the MACRO Station will copy values from the MACRO command input node registers to the I O board addresses it will copy values from the I O board addresses to the MACRO feedback output node registers Writing a 0 to a bit of the I O board enables it as an input letting the output pull high Writing a 1 to a bit of the I O board enables it as an output and pulls the output low Example 1 Two 24 bit I O transfers using nodes 2 and 3
44. ord 2 M1005 gt Y S50772 8 16 Output mirror word 3 M1010 gt X 50773 8 16 Old Image mirror word 1 M1011 gt Y 0773 8 16 Old Image mirror word 2 M1012 gt X 50774 8 16 Old Image mirror word 3 IO word 1 IO Word 2 IO Word 3 M800 gt X 770 8 M816 gt Y 770 8 M832 gt X 771 8 M801 gt X 770 9 M817 gt Y 770 9 M833 gt X 771 9 M802 gt X 770 10 M818 gt Y 770 10 M834 gt X 771 10 M803 gt X 770 11 M819 gt Y 770 11 M835 gt X 771 11 M804 gt X 770 12 M820 gt Y 770 12 M836 gt X 771 12 M805 gt X 770 13 M829 gt Y 770 13 M837 gt X 771 13 M806 gt X 770 14 M822 gt Y 770 14 M838 gt X 771 14 M807 gt X 770 15 M823 gt Y 770 15 M839 gt X 771 15 M808 gt X 770 16 M824 gt Y 770 16 M840 gt X 771 16 M809 gt X 770 17 M825 gt Y 770 17 M841 gt X 771 17 M810 gt X 770 18 M826 gt Y 770 18 M842 gt X 771 18 M811 gt X 770 19 M827 gt Y 770 19 M843 gt X 771 19 M812 gt X 770 20 M828 gt Y 770 20 M844 gt X 771 20 M813 gt X 770 21 M829 gt Y 770 21 M845 gt X 771 21 M814 gt X 770 22 M830 gt Y 770 22 M846 gt X 77 1 22 M815 gt X 770 23 M831 gt Y 770 23 M847 gt X 771 23 IO word 4 IO Word 5 IO Word 6 M900 gt Y 771 8 M916 gt X 772 8 M932 gt Y 772 8 M901 gt Y 771 9 M917 gt X 772 9 M933 gt Y 772 9 M902 gt Y 771 10 M918 gt X 772 10 M934 gt Y 772 10 M903 gt Y 771 11 M919 gt X 772 11 M935 gt Y 772 11 M904 gt Y 771 12 M920 gt X 772 12 M936 gt Y 772 12 M905 gt Y 771 1
45. resses 2 X C0A0 X COA1 X COA2 X COA3 3 X COA4 X C0A5 X COA6 X C0A7 6 X COA8 X C0A9 X COAA X COAB 7 X COBO X COBI X COB2 X COB3 10 X COB4 X COB5 X COB6 X COB7 11 X COB8 X COB9 X COBA X COBB MACRO Station I O Transfer 11 Accessory 10E PMAC2 Ultralite VO Node Addresses Node Node 24 bit Node 16 bit upper 16 bits Transfer Addresses Transfer Addresses 2 X C0A0 X COA1 X C0A2 X C0A3 3 X C0A4 X C0A5 X C0A6 X COA7 6 X COA8 X C0A9 X COAA X COAB 7 X C0B0 X C0B1 X C0B2 X C0B3 10 X C0B4 X C0B5 X C0B6 X C0B7 11 X COB8 X COB9 X COBA X COBB PMAC2 Turbo Ultralite VO Node Addresses MACRO User Node 24 bit Node 16 bit upper 16 bits IC Node Node Transfer Addresses Transfer Addresses ICO 2 2 X 078420 X 078421 X 078422 X 078423 ICO 3 3 X 078424 X 078425 X 078426 X 078427 ICO 6 6 X 078428 X 078429 X 07842A X 07842B ICO 7 7 X 07842C X 07842D X 07842E X 07842F ICO 10 10 X 078430 X 078431 X 078432 X 078433 ICO 11 11 X 078434 X 078435 X 078436 X 078437 IC1 2 18 X 079420 X 079421 X 079422 X 079423 IC1 3 19 X 079424 X 079425 X 079426 X 079427 IC1 6 22 X 079428 X 079429 X 07942A X 07942B IC1 7 23 X 07942C X 07942D X 07942E X 07942F IC1 10 26 X 079430 X 0794
46. s the MACRO I variables MI69 MI70 and MI71 were modified to read up to three consecutive base address cards in MACRO firmware version 1 16 26 MACRO Station I O Transfer Accessory 10E Chip Select MACRO Address Dip Switch SW1 Position 6 5 4 3 2 1 CS 10 FFEO OPEN OPEN OPEN OPEN CLOSE CLOSE CS 12 FFE8 OPEN OPEN OPEN OPEN CLOSE OPEN CS 14 FFFO OPEN OPEN OPEN OPEN OPEN CLOSE CS 16 Cannot Use OPEN OPEN OPEN OPEN OPEN OPEN To use the new IO cards with the older firmware systems the user can use each of the IO transfer variables MI69 MI70 MI71 to transfer 48 bits each The main problem is that the older systems did not have the new extended addressing and the user can only use three IO cards per MACRO station e For systems with only one IO card the user will not have to change anything e If any of these New IO cards are used with the ACC 9E ACC 10E ACC 11E or ACC 12E then the user should address the New IO card as the first card LOW byte in addressing scheme MACRO Station I O Transfer 27 Accessory 10E 28 MACRO Station I O Transfer Accessory 10E VO TERMINALS Pin Symbol OlLOINIT ND NASR IwWLNo re TB1 Top 12 Pin Terminal Block Top View This terminal block provide the inputs 1 12 for the ACC 9E Input Card Notes TB2 Top 12 Pin Terminal Block
47. sented as 12 hexadecimal digits The first 6 digits specify the number and address of 48 bit 3 x 16 real time MACRO node register sets to be MACRO Station I O Transfer 13 Accessory 10E used The second 6 digits specify the number and address of 16 bit I O sets on the MACRO Station I O accessory board to be used The individual digits are specified as follows Digit Possible Values Description 1 0 1 2 3 Number of MACRO I O nodes to use 0 disables this should also match the number of 48 bit I O sets you intend to use see Digit 7 2 0 Reserved for future use 3 6 COA1 Node 2 C0A5 Node 3 MACRO Station X Address of MACRO I O node first of three COA9 Node 6 COAD Node 7 16 bit registers COBI Node 10 COB5 Node 11 7 0 1 2 3 Number of 16 bit VO sets to use 1x16 2x16 3x16 0 disables 8 1 Set to 1 for ACC 14E ACC 65E ACC 66E ACC 67E consecutive address read Base 1000 2000 9 12 FFCO FFC8 FFDO FFD8 MACRO Station Y Base Address of I O Board as set by Board Jumper E1 E4 ACC 3E board or E15 E18 ACC 4E board 8800 8840 8880 88CO MACRO Station Y Base Address of ACC 9E ACC 10E ACC FFEO FFE8 FFFO 11E ACC 12E and ACC 13E for legacy systems When this function is active the MACRO Station will copy values from the MACRO command input node registers to the I O board addresses it will copy values from the I O board addresses to the MACRO feedb
48. these numbers Only bits 2 3 6 7 10 and 11 of MI975 should ever be set to 1 MI975 is used at the power on reset of the Compact MACRO Station in combination with rotary switch SW1 and MI976 to determine which MACRO nodes are to be enabled The net result can be read in Station variable MI996 To get a value of MI975 to take effect the value must be saved MSSAVE node and the Station reset MS node Example Set MI975 to enable nodes 2 and 3 MSO 1975 Set Number MACRO IO nodes to be enabled Bit 15 14 13 12 11 10 9 8 7 6 5 41 3 2 11 0 Value 010101010101010101010101 1 111010 MSO 1i975 000C MS0 MI975 4 Enable I O Node 2 alone MS0 MI975 C Enable I O Nodes 2 amp 3 MS0 MI975 4C Enable I O Nodes 2 3 amp 6 MS0 MI975 CC Enable I O Nodes 2 3 6 amp 7 MS0 MI975 4CC Enable I O Nodes 2 3 6 7 amp 10 MS0 MI975 CCC Enable I O Nodes 2 3 6 7 10 amp 11 MS4 MI975 40 Enable I O Node 6 alone MS4 MI975 CO Enable I O Nodes 6 amp 7 MS8 MI975 400 Enable I O Node 10 alone MS8 M1975 C00 Enable I O Nodes 10 amp 11 MI69 and MI70 specify the registers used in 16 bit I O transfers between MACRO node interface registers and I O registers on the MACRO Station I O accessory board They are used only if MI19 is greater than 0 MI69 and MI70 are 48 bit variables repre
49. to these memory locations Delta Tau suggests using image input words to read the actual input words and then write to the actual output word if the inputs have changed states The following block diagram shows the typical logic for PMAC s inputs and outputs input mirror input word in mirror old in mirror no Y yes old input mirror input word Process Inputs Build Output Word Perform Desired Actions output word out mirror dd N END S A EEN For this application we are using six 16 bit data transfers and will use the following M Variable definitions in our application MACRO Station I O Transfer 19 Accessory 10E PMAC2 Ultralite Example M Variable Definitions M980 gt X S C0A1 8 16 IO word 1 1st 16 bit word node M981 gt X S C0A2 8 16 IO word 2 2nd 16 bit word node 2 M982 gt X S C0A3 8 16 10 word 3 3rd 16 bit word node 2 M983 gt X S C0A5 8 16 IO word 1 1st 16 bit word node 3 M984 gt X S C0A6 8 16 IO word 2 2nd 16 bit word node 3 M985 gt X C0A7 8 16 IO word 3 3rd 16 bit word node 3 M1000 gt X 50770 8 16 Input mirror word 1 M1001 gt Y 50770 8 16 Input mirror word 2 M1002 gt X 5 0771 8 16 Input mirror word 3 M1003 gt Y S50771 8 16 Output mirror word 1 M1004 gt X 0772 8 16 Output mirror w
50. utputs Using 1X72 Bit Transfers The 72 bit transfer is unique because it allows you to transfer both the 3x16 bit and 1x24 bit transfer in one read write transfer This method can only be used with MACRO firmware version 1 112 or higher Using this method we only need to activate one node In this case we will use node 2 For this example the inputs and outputs are sharing the same Node Transfer Address You will notice address X COA1 has 12 bits of inputs and 4 bits of outputs To properly write to the 4 output bits Delta Tau recommends that you write the outputs to the entire word Ultralite 8 Axis Turbo Ultralite 8 Axis Description 1996 0FB337 1684 1 0FB337 Enable nodes 0 1 2 4 5 8 9 12 amp 13 at PMAC Ultralit e M970 gt X C0A0 0 24 M970 gt X 78420 0 24 IO word 1 24 bit word node2 M980 gt X C0A1 8 16 M971 gt X 78421 8 16 IO word 1 Ist 16 bit word node2 M981 gt X C0A2 8 16 M972 gt X 78422 8 16 IO word 2 2nd 16 bit word node 2 M982 gt X C0A3 8 16 M973 gt X 78423 8 16 IO word 3 3rd 16 bit word node 2 M1000 gt X 0770 0 24 M1000 gt X 0010F0 0 24 Input mirror word 1 M1001 gt Y 0770 8 12 M1001 gt Y 0010F0 8 12 I O mirror word 2 12 bits inputs only M1002 gt Y 0770 8 16 M1002 gt Y 0010F0 8 16 Output mirror word 1 12 bits inputs amp 4 bits outputs M1003 gt X 0771 8 16 M1003 gt X 001
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