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X5-RX User`s Manual

1. 94 TRUONG isc Trigger 5 Ad Trigger WOW mme SU Trigger Controls in SNAP 7 External Trigger Input 00 98 M ulti A D Sy nChromiZations ccsiccssssssussssenvasisssesessniscnsesssntascenessecassvevessnsnosceoassotendabeanacdeabass OO Frame Work Logic 2 2 JS Power Controls and Thermal 100 System Thermal tractu eee tain pai o Yea epa epica ipee Deua bae Pun eo ero Temperature Sensor and Over Temperature 100 Bir cc ELT OO VervVviQW 22 LOU TYPOS OF ALORS OL Alert Packet FOr at PC Software Support for Alerts ssccccccsscsisecssescvacsscasseeusedcsessvesousrenussteapucdenssoussadedsusastendseouteasgeceocsasacicssosuec L02 Tagging the Data RN 102 ML LOZ Updating the Calibration Coefficients
2. coup sequ dex Uu Bey 23 Prerequisites for Install AMON e P The Redistribution Package Group MalibuRed 4 lt 22 litige rU Other SOIEWAEO iuis calcat ende de tet Baseboard Package Installation 24 Board Packages T M Unpacking the uu cru cT T ROM 2 9 Creating Symbole Links Spe uode addu 25 Completing the Board Install 5 pono etta e nere ona revu pe uela ra Ee npe tein eret ev peu 20 Linux Directory Hardware d 26 Chapter 2 Hardware Installation 27 Compatible Host Cards 27 System 30 Power 1 8 m 31 Mechanical amp 1 Q 32 Chapter 1 About th X5 Modules sevc
3. a gen eaa 53 25 25 53 53 Siding TION I vd Eit a ot aia due 56 Handle Data ode 60 EPROM ACCESS caede Ame Oden ta dae NICO ie oes Vaso a spe Me 62 snap peius puse The Apphcationlo Class xi Site ote et eee ruta arat e heb et Mat vert Ip 63 User ioa e Sr a Vo eo suae Wave Em cca bite T Stream Initialization es choi s ue EDD 67 Data Required Event Eve 69 Ihe Wave Example for JE The App ication lo san ceat oa s etes au vetu edle 7 unio Eam oc urbe cues L Drarannpaihp editis IHUu Borland
4. 34 Table 6 X5 Computing Core 35 Table 7 PCI Express Standards eR ais Pesto Coe ida esi Gr a C GUT M 36 Table 8 Interfaces from PCI Express to Application 1 34 Table 9 X5 Modules Available BETA so o a 39 Table 10 I UsesDioPort Class PR pa ee d Oe e eL 39 Table 11 LVTTL Digital IO Bits Electrical Characteristics eee 41 Table 12 LVCMOS2 5 Digital IO Bits Electrical 42 Table L3 X SE DACPSCADE dau ud peer DUE 46 Table 14 Adapters and ier e etie egeo 47 Table 15 Development Tools for the Windows Snap 1 50 Table 16 X5 RX neve x red rane E eo Ha Ke ue NY SR ERE A EO AREE 84 Table 17 High Speed A D Conversion 86 Table 18 Secondary Low Speed A D Conversion Coding sse 86 Table 19 PLE Specification cane si ex e ab e ON de URN ERR ue TES 88 Table 1 Sample Rate Generation Parameters acted eere tec eene ke EG eg 90 Table 2 Steps to Configure the VCXO and PEL aede d te
5. EE E E EAEE E DKN eem Input Range and Conversion 85 DC and Low Frequency Band eee e rete eene OO Drivme tlie A D Inputs iei GER ee ES EC ERES RERO SET e ee EA TURAE Pape RAD EE Xa UR Oyerrange DCCC COM ERR T H A Sample Rate Generation and Clocking 5 2 1 1 1 1 e eee ee een seen esee 07 External Clock Refer nce In puttisis cccccscsecsscsesnssscansessseisseunseseesasecarsseeusqssonssssotersvonssevsbecsssessavenassateuass Sample Rate Gener atom itu Setting the Sample Rate the SNAP 2 1202 7 71 00 7 10000 sse OO Controlling ul IN peor M ER OF How To Set the Sample Rate Generator to a Specific 2 4 89 Using An External PEL 5 J Using An External Clock for Sample Clock e eee eene eren eene eoe ne sese seseaseeeeseeessseeseseseseses 92 vostos sisse J 72010 ec A O COA PLOR KIS cp VCXO BC Port 0xSOEP
6. 1 3Vp p Fs 200 MSPS X5 RX User s Manual 113 X5 RX Module ax BinView c projects x5 rx reva test dataVjason s test datalanalog quality reevaluation plot28 bdd GEBE 9 60 Time Frequency Text Summary Server 8 33 46 6 59 Amplitude vs Frequency a 3 50e 04 KHz 1 97dB m dB 30K 31K 32K 33K 34K 35K 36K 37K 38K 39K 40K KHz 41 Max S N 98 SYN dB SINAD 98 SFDR 98 THD Z dB Noise dB 981 69 0 647 105 78 6 0 022626 72 948 116148 Sample 989 Leap 55536 Analyze ChO 7 Samples 1048636 start visual Source sstB pdf Ad fi Analog qualit fim My Documents fj sig quality s P readme Not Figure 5 Narrowband Signal Quality Fin 165 MHz 1 3Vp p Fs 200 MSPS X5 RX User s Manual 114 X5 RX Module Connectors Front Panel Connectors J1 J6 J1 J2connectors are positioned on the front panel for analog input clock and trigger signals to be connected to the module Connector Type Number of Connections Connector Part Number Mating Connector Cable SMA 50 ohm 1 per signal Amphenol 901 143 Amphenol 901 9511 3 or equivalent Innovative part number 67048 SMA to BNC cable Connector Function A D channel 0 J2 A D channel 1 J3 A D channel 2 A D channel 3 J5 Trigger J6 Sample Reference Clock Input
7. J5 TRIGGER J6 EXT CLK M2 TH 6 PL Figure 11 X5 RX Mechanicals Top View mL 22 0 0 15 X5 RX User s Manual 123 X5 RX Module Figure 12 X5 RX Mechanicals Bottom View X5 RX User s Manual 124
8. Figure 6 Connectors J1 J6 Functions X5 RX User s Manual 115 X5 RX Module XMC P15 Connector P15 15 the PCI Express connector to the host XMC pin header 0 05 in pin spacing vertical mount Number of Connections 114 arranged as 6 rows of 19 pins each Connector Part Number Samtec ASP 105885 01 Figure 7 P15 XMC Connector Orientation X5 RX User s Manual 116 X5 RX Module Table 17 X5 RX XMC Connector P15 Pinout Note All unlabeled pins are not used by X5 modules but may defined in VITA42 and VITA42 3 specifications Column Row A B C D E F 1 PETOpO PETOnO 3 3V PETOp1 PETOn1 VPWR 2 GND GND GND GND MRSTI 3 PETOp2 PETOn2 3 3V PETOp3 PETOn3 VPWR 4 GND GND GND GND MRSTO S PETOp4 PETOn4 3 3V PETOpS PETOnS VPWR 6 GND GND GND GND 12V 7 PETOp6 PETOn6 3 3 PETOp7 PETOn7 VPWR 8 GND GND GND GND 12V 9 VPWR 10 GND GND GND GND GAO PEROpO PEROnO MBIST PEROpI VPWR 12 GND GND GND GND MPRESENT 13 PEROp2 PEROn2 3 3VAUX PEROp3 PEROn3 VPWR 14 GND GND GA2 GND GND MSDA 15 PEROp4 PEROn4 5 5 VPWR 16 GND GND MVMRO GND GND MSCL 17 PEROp6 PEROn6 PEROp7 PEROn7 18 GND GND GND GND 3 3V 19 PEX REFCLK PEX REFCLK one WAKE ROOT rane Note LED_N and FAN are special pur
9. FloatToString lo gt Settings AdcGain i 4 c str else AdcCoefGrid 0 i gt Value gcnew String NAN if isnan Io Settings AdcOffset i amp amp _finite Io gt Settings AdcOffset i AdcCoefGrid 1 i gt Value gcnew String Innovative FloatToString Io gt Settings AdcOffset i 4 c_str else AdcCoefGrid 1 i gt Value gcnew String NAN PllCorrectionEdit Text gcnew String Innovative FloatToString Io Settings PllCorrection 4 c str CalibratedCheckBox gt Checked Io gt Settings Calibrated ModuleNameEdit gt Text gcnew String Io gt Settings ModuleName c_str ModuleRevisionEdit gt Text gcnew String lo gt Settings ModuleRevision c_str The Linux Snap Example With the release of Linux support for Malibu and for Innovative products there are versions of the example programs for this platform This section discusses the Linux Snap example The ApplicationIo Class Because we designed the original examples to separate Malibu and Baseboard functionality into a portable class this code can move to the Linux example unchanged So the above discussion of the features of the Applicationlo class is directly applicable to the Linux example In fact the code itself is shared between the platforms X5 RX User s Manual 63 Writing Custom Applications User Interface The Linux OS supports a number of different windowing systems We have chosen WxWidge
10. Innovative x8 Lane PCI Express XMC 3 8x lanes adapter card P N 80173 0 29 Innovative Compact XMC 3 x4 lanes adapter card P N 80207 0 30 eInstrument Node cabled PCI Express adapter x1 lane for Modules II P N QU TS d eden d 30 Figure 14 eInstrument PC embedded PC Windows Linux hosts two modules II P N 30 Figure 15 X5 XMC Family Block 34 Figure 16 DIO Control Register BAR FOSSE Pep ian Sharan tee 40 Figure 17 Digital IO Port AdGressess wa NER rn 40 Figure 18 Virtex 5 Rocket Assignments for P16 signals 43 Figure 19 eInstrument Node Enclosure P N 90181 Supports Standalone Operation 48 Figure 20 eee tre eM EHE rtr a te UE Re aded pae s 49 Figure 21 X5 RX Module analog cover and heat sink installed sess 82 Figure 22 X5 RX Block Diagram oio ee eitis too Lope duis tie 83 Figure 23 X5 RX A D Channel Front En a o ee brevet OR Dt oen ae d eris 85 Figure 1 Sample Clock Generation and Distribution Block Diagram eee 87 Figure 2 Input Clock Reference Electri
11. Note Before installing the host development libraries VCL components or MFC classes you must have Microsoft MSVC Studio version 9 or later CodeGear RAD Studio 2007 2009 Embarcadero Rad Studio 2010 or QtCreator installed on your system depending on which of these IDEs you plan to use for Host development If you are planning on using these environments it is imperative that they are tested and known operational before proceeding with the library installation If these items are not installed prior to running the Innovative Integration install the installation program will not permit installation of the associated development libraries However drivers and DLLs may be installed to facilitate field deployment You must have Administrator Privileges to install and run the software hardware onto your system refer to the Windows documentation for details on how to get these privileges X5 RX User s Manual 15 Windows Installation Starting the Installation To begin the installation start Windows Shut down all running programs and disable anti virus software Insert the installation DVD If Autostart is enabled on your system the install program will launch If the DVD does not Autostart click on Start Run Enter the path to the Setup bat program located at the root of your DVD ROM drive 1 E Setup bat and click to launch the setup program SETUP BAT detects if the OS is 64 bit or 32 bit and runs the appropriate
12. ceres eee eene eene eere neenon esee ee esee eessssseeeees 103 USING GHG XD die CREE Where tostar M OS Getting Good Analog 1 1 e eese eerte e eere ese see sssee 104 Performance PS 109 Power COMSUMI POM er HY LES EE LOS Input utis nce e Fas OO 15 Front Panel Connectors 1 LIS 15 Connector 1 5 55 Deme Xilinix JTAG CONME COM 21 FLASH LEZ Mech aricals 122 List of Tables Table 1 X6 Bus Requiremetis ducto oce bt br AU rS pers be QR 27 Table 2 Required PCIe Resource ATloCcationg 31 Table 3 XMC Mo nting ETATQWAEG ga ea va EAS ana AEAT E a Te 32 Table 4 Family Ve PUR cepa e aE aA Cu 34 Tables AS XMC Peripherals de en n
13. scccsscsscssccsssccssccccsecsccscssssscssssscscssscscssscssssssssssesssosssseeees 44 Thermal gie eene c 45 Led LII LM mE 45 LEDs NOT Lit with FrameWork Logic Installed ceres ecce eere esee tette 45 JTAG Scan ii eec 46 l ciuta f M 46 Integrating with Host Cards and Systems 46 Standalone Oper atom st 48 Updating the logic Configuration 48 Rescuing the Card When the Logic Image is 49 Chapter 3 Writing Custom 018 111 set tn set ens sets ases aset esos esee 50 1 22 5 eye toU Coast EE MANO 50 Tools REG UIE em e n 50 RS 51 THE Host A bru mE 51 Us r TC PLAC ee 51 Configure 51 SARD N o D eT o NEERA 52 Stream E 52 Host Side Program Oro anni
14. 9 126 RXPI TXP7 AN6 126 TXNO TXN7 ANS MGT 126 TXPO RXP7 AP7 126 RXNO RXN7 AP6 126 Figure 18 Virtex 5 Rocket I O Assignments for P16 signals Note that the positive and negative polarities of the individual lanes are reversed between the polarity notation on the P16 connector versus the polarity notation on the Rocket I O pin pairs This was done to avoid vias on the PC board and thus optimize the layout for signal integrity purposes If needed by the application strict signal polarity can be reversed in the Virtex 5 logic design by using the Rocket I O polarity controls within each MGT tile X5 RX User s Manual 43 About the X5 Modules Reference clocks running at 125 MHz are connected to the reference clock input pins of 126 and 120 pins AL7 AMT EA and D4 respectively This clock is supplied by an LVPECL oscillator at location If a different frequency is required by the user s application this oscillator can be replaced by any 6 pin 2 5V LVPECL output device compatible with Pletronics LV7745DEW footprint Thermal Protection and Monitoring The Virtex 5 logic device includes a temperature and voltage monitoring subsystem called System Monitor The X5 design uses the System Monitor to check Virtex 5 device die temperature and control the enable disable feature on key board power supplies This allows logic to disable power on the card in the event of an over t
15. Compact PCI PCI Express 1 0a 3U CPCI XMC 3 Innovative 80207 adapter VPX VPX with PCI 3U VPX VPX3U Innovative Express adapter Air Cooled 80260 7 Slot Profiles Air or Conduction Cooled 80260 6RC SLT3 PAY 1D 14 2 6 conduction SLT3 PER 1F 14 3 2 pooled SLT3 PER 1U 14 3 3 Cabled PCI PCI Express 1 0a Cabled PCI Express Cable PCIe Innovative 90181 Express to remote IO Adapter and 3 carrier Embedded PCI Express to local 10 7 3 inches None Innovative 90200 or 90201 Host PC core Table 14 XMC Adapters and Hosts X5 RX User s Manual 47 About the X5 Modules Standalone Operation The X5 modules can be run standalone for embedded applications using a carrier card such as Innovative 90181 The host card provides power to the module and cooling Custom carrier cards have been created for specific applications that provide Ethernet ports Figure 19 eInstrument Node Enclosure P N 90181 Supports Standalone Operation The logic must be modified for standalone operation to remove the PCIe host interface and controls and substitute local controls and logic Other changes vital to system operation are detailed in the Framework Logic manuals Updating the XMC logic Configuration EEPROM Virtex 5 configuration data is stored in an onboard flash EEPROM which may be updated using software provided by Innovative Logic images may come as updates from Innovative or be generated by a user developing custom f
16. During the development cycle it is much more efficient to download and debug firmware using the Xilinx Bit Blaster JTAG cable To use the applet select the instance of the 400M module to be updated This will be target zero in single target installations Then click the browse button to select the logic bit file image containing the updated firmware image Typically this is located in the Innovative Wx5 moduleNHardwareNImages folder on your default drive The module is 400M 210M RX GSPS COM or TX Finally click the Write button to program the firmware into the on board FLASH rom Programming typically takes about five minutes After rebooting the PC the new firmware will take effect X5 RX User s Manual X5 400M Logic Loader File Help Target z Board Rev Sub Sec Update Logic orosApplets sProm Current Logic toro 2017 T Flash Prom Read Verify 80 Applets for the 5 Baseboard Finder The Finder is designed to help correlate board target numbers against PCI slot numbers in systems employing multiple boards Target Number 8i X5 400M Finder AR Select the Target number of the board you wish to identify Number using the Target Number combo box t Blink Set LED On Off Click the Blink button to blink the LED on the board for the specified target It will continue blinking until you click Stop On OFF Use the O
17. Standard features are provided as components that may be included in custom applications or further modified to meet specific design requirements Integrating with Host Cards and Systems The X5 XMCs may be directly integrated PCI Express systems that support VITA 42 3 XMC modules The host card must be both mechanically and electrically compatible or an adapter card must be used The XMC modules conform to IEEE 1386 specification for single width mezzanine cards This specification is common to both PMC and XMC modules and specifies the size mounting mating card requirements for spacing and clearances There are several adapter cards that are used to integrate the XMC modules into other form factor PCI Express systems such as desktop systems X5 RX User s Manual 46 About the X5 Modules There are also adapter cards to electrically adapter the PCI Express XMC modules in older PCI systems that use a bridge device between the two buses PCI is not electrical Host Type Bus Mechanical Form Adapter Example card factor Required XMC 3 module PCI Express 1 0a single width None Kontron CP6012 slot www kontron com Diversified Technology CPB4712 http www diversifiedtechnology com p roducts cpci cpb4712 html Desktop PC PCI Express 1 0a PCI Express Plug in PCle XMC 3 Innovative 80173 card x8 lane adapter Desktop PC PCI2 2 PCI Plug in card PCI XMC 3 Innovative 80167 adapter
18. 113 Figure 5 Narrowband Signal Quality Fin 165 MHz 1 3 Vp p Fs 200 8 6 114 Figure 6 Connectors J1 J6 Nd omen OR AE SETS ORS 115 Figure 7 Connector OrientattOti 116 Figure 8 P16 X MC Connector 119 Figure 9 5 JP1 Orientation board face view eee eerte 121 Figure 10 X5 RX JP1 Orientation board top edge 121 Figure 11 X5 RX Me chanieals e neue Cau ue ea e eens ties 123 Figure 12 X5 RX Mechanicals Bottom View essen emen eene nennen nnne 124 Introduction Chapter 1 Introduction Real Time Solutions Thank you for choosing Innovative Integration we appreciate your business Since 1988 Innovative Integration has grown to become one of the world s leading suppliers of DSP and data acquisition solutions Innovative offers a product portfolio unrivaled in its depth and its range of performance and I O capabilities Whether you are seeking a simple DSP development platform or a complex multiprocessor multichannel data acquisition system Innovative Integration has the solution To enhance your productivity our hardware products are supported by comprehensive software libraries and device drivers
19. 70K 80K 90K 100K KHz gl SAN KB ED 88 3 9 Sample Leap 65536 Analyze ChO 7 i i Samples 1048636 se Start 28 ModelSim_10_libs 5 Hardware odt x5 rx a pdf Adobe EE xilinx ISE C Proje Figure 1 Wideband Signal Quality Fin 70 MHz 1 4Vp p Fs 200 MSPS X5 RX User s Manual 110 X5 RX Module 2 BinView c projects x5 rx reva test dataVjason s test datalanalog quality reevaluation plot26 bdd co Time Frequency Text Summary Server 74 44 3 79 Amplitude vs Frequency a 7 00 04 KHz 2 89dB dB D 64 66 68K 70K 72K 74K 76K KHz AEN Max S N dB S N 98 SINAD 98 ENOB SFDR dB THD 4 Noise dB 98 1 711 68 9 112 861 0 007305 82 0dB 118 998 Sample 0 Leap 69936 _ Analyze ChO 7 Samples 1048636 start ModelSim_10_libs 5 Hardware odt x5 rx a pdf Adobe EE Xilinx c proje 5 File Vi Figure 2 Narrowband Signal Quality Fin 70 MHz 1 4Vp p Fs 200 MSPS X5 RX User s Manual 111 X5 RX Module 2 BinView c projects x5 rx reva test dataVjason s test datalanalog quality reevaluation plot31 bdd warm 9 Time Frequency Text Summary Server HU Amplitude vs Frequency 5 0 A 9 90 0
20. ADC1 ADC2 ADC3 Trigger Figure 22 X5 RX Block Diagram X5 RX User s Manual 83 X5 RX Module Hardware Features A D Converters The X5 RX has four channels of 16 bit A D sampling at up to 200 MSPS Minimum sample rate is 1 MHz below which severely degraded performance occurs The X5 RX implements an AC coupled input with a secondary channel for DC information 50 ohm terminated SMA connector based front end Feature Description Inputs 4 Input Range 1 5V to 1 5V single ended Maximum Input Current 30 mA Input Coupling AC with secondary DC level 0 to fs 8192 Input Impedance 50 ohm A D Devices Texas Instruments ADS5484 Output Format 2 s complement 16 bit Number of A D Devices 4 simultaneously sampling Sample Rate 200 MSPS Calibration Factory calibrated Gain and offset errors are digitally corrected in logic Non volatile EEPROM coefficient memory Table 16 X5 RX A D Features Conversion clocking is provided by either a low jitter programmable clock source or an external clock input The clock buffering is designed to minimize jitter and maximum acquired signal quality See the clock discussion for more details A D Front End Front end circuitry for the A D converters includes a 50 ohm terminated SMA input connector followed by a transformer into the A D inputs Impedance matching networks are used to provide the 50 ohm input The ADC input also drive
21. Configuration to Release Build add lib bcb10 release change Build Configuration to Debug Build add lib bcb10 debug change Build Configuration back to All Configurations Packages uncheck Build with runtime packages X5 RX User s Manual 74 Developing Host Applications Microsoft Visual Studio 2005 Microsoft Visual C 2005 version 8 Project Properties When creating a new application with File New Project with Widows Forms Application New Project Project types Templates Visual C ATL CLR General MFC Smart Device Win32 Other Languages Other Project Types Visual Studio installed templates ASP NET Web Service Console Application 83591 Server Project a Windows Forms Control Library My Templates _jJSearch Online Templates Class Library Empty Project EZ windows Forms Application H Windows Service project For creating an application with a Windows user interFace Mame Enter name Location Crlsome folder v Browse Solution Create new Solution X5 RX User s Manual Add to Source Control Create directory For solution 75 Developing Host Applications Project Properties Alt F7 Configuration Properties E Project Defaults Configuration Type Application exe Use of Use Standard Windows Libraries Use of ATL Not Using ATL Minimize CRT Use in
22. DRAM memory bank The pattern generation mode provides dynamic pattern generation using DRAM memory bank that is driven by control and data packets from the host This allows the DRAM to be used as an arbitrary waveform generator for applications such as communications testing RADAR stimulus generation and ultrasonic stimulus X5 RX User s Manual 37 About the X5 Modules Serial EEPROM Interface EEPROM A serial EEPROM on the X5 series is used to store configuration and calibration information The interface to the serial EEPROM I2C bus that 15 controlled by the PCI logic device The device is an Atmel 24 16 1051 a 16K bit device The I2C bus is slow and the calibration is read out of the EEPROM at initialization time by the application software and written into registers in the application logic for real time error correction The EEPROM also has a write cycle limit of 100K cycles so it should only be written to when calibration 15 performed or configuration information changes Once the write cycle duration limit is exceeded the device will not reliably store data any more As delivered from the factory this EEPROM contains the calibration coefficients used for the A D and D A error correction Caution the serial EEPROM contains the calibration coefficients for the analog and is preprogrammed at factory test Do not erase these coefficients or calibration will be lost Use the baseboard IdRom method to
23. Event Log Be sure to read the help file for info on this program located in the root of the this example folder 65 Writing Custom Applications Setup Tab This tab has a set of controls that hold the parameters for transmission These settings are delivered to the target and configure the target accordingly This tab has several sections The Clock section offers configurations and routing of the clock The clock for the FPGA can come from an external clock or from an internal crystal The selection can be made at upper right corner of this section The clock rate of the clock source is specified in the Output field in MHz The Communications section controls the Alert features and the input data packets size Checking the box next to an alert will allow the logic to generate an alert if the condition occurs This alert can then be left in the data stream or extracted to notify the application In the Channels section we can specify number of channels to activate Selecting a channel will flow data from that data source The Trigger selection box controls the way that data streaming is started It can be started by an external signal or by the lt SnapExample Configure Stream EEProm Debug Clock Communications Source Output Pkt Size Alerts External lox10000 Time Stamp 210 0 210 Temp Warning Active Channels Trigger Cho Source Frame Mode ETNH gt Exter
24. JTAG Scan Path X5 modules have a JTAG scan path for the Xilinx devices on the module This is used for logic development tools such as Xilinx ChipScope and System Generator and for initial programming of the PCI FPGA configuration FLASH ROM Nominally there are two devices in the scan chain the Virtex 5 device and the Coolrunner CPLD used to implement the configuration support Optionally the SRAM devices may be included in the scan chain if JTAG access is needed for debugging purposes Table 13 X5 JTAG Scan Path JTAG Device Device Function Number 0 Virtex 5 Application logic 1 Coolrunner II Configuration control FrameWork Logic Many of the standard X5 XMC features are implemented in the application logic This feature set includes a data flow triggering features and application specific features In many cases this logic provides the features needed for a standard data acquisition function and is supported by software tools for data analysis and logging In this manual the FrameWork Logic features for each card are described in in general to explain the standard hardware functionality The X5 FrameWork Logic User Guide provides developers with the tools and know how for developing custom logic applications See this manual and the supporting source code for more information The X5 modules are supported by the FrameWork Logic Development tools that allow designs to be developed in HDL or MATLAB Simulink
25. LoadFromRomButton Click System Object Io ReadRom Then test the information void ApplicationIo ReadRom Module IdRom LoadFromRom Settings ModuleName Module IdRom Name Settings ModuleRevision Module IdRom Revision for int ch 0 ch Channels ch Settings AdcGain ch Module Input Gain ch Settings AdcOffset ch Module Input Offset ch Settings Calibrated Module Input Calibrated There is also a mechanism to write to the on board EEPROM void ApplicationIo WriteRom Module IdRom Name Settings ModuleName Module IdRom Revision Settings ModuleRevision for int ch 0 ch Channels ch Module Input Gain ch Settings AdcGain ch X5 RX User s Manual Module Input Offset ch Settings AdcOffset ch sender System EventArgs e 62 Writing Custom Applications Module Input Calibrated Settings Calibrated Module IdRom StoreToRom The application code should test for NAN and in general for the validity of the received data Please see Form1 h for MSVC NET 2005 projects or Main cpp for Borland 10 projects private System Void LoadFromRomButton Click System Object sender System EventArgs e Io gt ReadRom for int i 0 i lt Io gt Channels i if isnan Io Settings AdcGain i 55 _finite Io gt Settings AdcGain i AdcCoefGrid 0 i gt Value gcnew String Innovative
26. Manual 27 Hardware Installation Preferred for X6 Modules Figure 7 Innovative x8 lane PCIe XMC 3 adapter card P N 80259 a Figure 8 Innovative 3U VPX XMC 3 adapter card P N 80260 Conduction cooled or Air cooled versions are offered gt 2 a lt a lt 2 5 gt x X5 RX User s 28 Hardware Installation Figure 9 Innovative Single lane PCIe XMC 3 adapter card P N 80172 Bees INNOVATI INTEGRATION T MADE INNOVATIVE 46162 NTEGRATION A XMCe PCle ADAPTER ASSY 80195 X5 RX User s Mz 29 Hardware Installation Figure 12 Innovative Compact PCI PXI XMC 3 x4 lanes adapter card P N 80207 0 Figure 13 eInstrument Node cabled PCI Express adapter x1 lane for Modules II P N 90181 einstrument PC Figure 14 eInstrument PC embedded PC Windows Linux hosts two XMC modules II P N 90199 XMC systems should be be compatible with VITA 42 3 specification for P15 The P16 interface can only be used when the PCI Express interface is present and active The P16 interface to the host may be customized in the Application Logic Host card support for P16 interfaces varies so this must be verified on a case by case basis to determine compatibility In the specific description of each module the P16 connection pinout is provided in this manual Innovative s adap
27. To FPGA J6 External A D 0 CLK Clock Ref Input M To A D 1 CLK ToA D2CLK M9 ToA D3CLK Y6 B Figure 1 Sample Clock Generation and Distribution Block Diagram Sample clocks are either generated by the PLL or are derived from an external input clock Specialized clock circuitry is used on the X5 RX for clock generation and distribution since these clocks must be extremely low noise to achieve the best digitizing accuracy This means that the clocks are NOT generated by the FPGA but rather the specialized clock circuitry The clocks are copied to the FPGA with separate copies go to each A D device Programmable controls for the clock circuitry are mapped to the host PCI Express bus through the FPGA X5 RX User s Manual 87 X5 RX Module Custom FPGA implementations can control the clocks without host involvement by commandeering these interfaces External Clock Reference Input The external clock reference input at connector J6 is on the front panel and has the following electrical requirements for the clock input Characteristic Description Input Impedance 50 ohm Input Coupling AC Input Connector SMA Minimum Input Amplitude 200mVp p 20 8 dBm Maximum Input Amplitude 2 0Vp p 0 8 dBm DC input range 20 max Maximum Frequency 500 MHz Input waveform Sine or square Figure 2 Input Clock Reference Electrical S
28. be limited to a voltage range between 0 and 3 3V referenced to ground on the digital I O port connector Exceeding these limits will cause damage to the X5 hardware X5 RX User s Manual 40 About the X5 Modules Digital IO Electrical Characteristics The digital IO pins 0 15 are LVTTL compatible pins driven by 3 3V logic The DIO port pins connect to the application FPGA via 100 ohm series resistors The X5 400M has additional pins that are LVCMOS 2 5V LVTTL Pins Warning the LVTTL DIO pins are NOT 5V compatible Input voltage must not exceed 4 05V during normal operation Undershoot and overshoot must be limited see the Xilinx Virtex 5 User Guide for details Parameter Value Notes Input Voltage Max 4 05V Exceeding these will damage Min 0 75V the FPGA Output Voltage gt 2 4 For load lt 12mA 0 lt 0 4V Output Current 12mA FPGA can be reconfigured for custom designs for other drive currents Input Logic 1 gt 2VDC Thresholds 0 lt 0 8VDC Input Impedance gt 1M ohm 15 pF Excludes cabling Table 11 LVTTL Digital IO Bits Electrical Characteristics LVCMOS 2 5 Pins Warning the LVCMOS 2 5 DIO pins are NOT 5V compatible Input voltage must not exceed 4 05V during normal operation Undershoot and overshoot must be limited see the Xilinx Virtex 5 User Guide for details Parameter Value Notes Input Voltage Max 2 7V Exceeding these will damage Min 0 75
29. consumption Allowance for decreased power supply efficiency due to heating can account for 1096 derating Also dynamic loads should be considered so that peak power is adequate In many cases a factor of 2 for derating is recommended Environmental The X5 RX 15 available for environmental rating levels from 1 0 office lab environment to L4 military and heavy industry Environment Rating L0 L1 L2 L3 L4 ER Environment Office controlled Outdoor stationary Industrial Vehicles Military and heavy lab industry Applications Lab instruments Outdoor monitoring Industrial Manned vehicles Unmanned vehicles X5 RX User s Manual 105 X5 RX Module research and controls applications with missiles oil and gas moderate vibration exploration Cooling Forced Air Forced Air Conduction Conduction Conduction 2 CFM 2 Operating Temperature 0 to 50C 40 to 85C 20 to 65C 40 to 70C 40 to 85C Storage Temperature 20 to 90C 40 to 100C 40 to 100C 40 to 100C 50 to 100C Vibration Sine 2g 5g 10g 20 500 Hz 20 2000 Hz 20 2000 Hz Random 0 04 g Hz 0 1 g Hz 0 1 g Hz 20 2000 Hz 20 2000 Hz 20 2000 Hz Shock 20g 11 ms 30g 11 ms 40g 11 ms Humidity 0 to 9595 0 to 10096 0 to 100 0 to 100 0 to 100 non condensing Conformal coating Conformal coating Conformal coating extended temperature range devices Conformal coating extended te
30. each capable of 500 MB s full duplex operation Timing and triggering Flexible clocking and synchronization features for I O Data buffering and Two 1Mx16 SRAM devices are used provide data buffering processor memory and computation X5 RX User s Manual 34 About the X5 Modules Peripheral Features Computational Memory memory for the Application FPGA Alert Log Monitors system events and error conditions to help manage the data acqusiton process X5 Computing Core The X5 XMC module family has an FPGA based computing core that controls the data acquisition process provides data buffing and host communications The computing core consists of a Xilinx Virtex 5 FPGA one bank of DDR2 DRAM 4Gbits in a x64 configuration and two banks of QDR2 SRAM 32Mbits total in two x32 dual ported banks The FPGA uses the memories for data buffering and computational workspace Table 6 X5 Computing Core Devices Feature Device Part Number Application Logic FPGA Xilinx Virtex 5 5 95 XC5VSX95T 1FFG1136C some cards use 2 Xilinx Virtex 5 LX155T XCSVLX155T 1FFG1136C some cards use 2 Computation memory QDR2 SRAM 2x Cypress CY7C1314BV18 167 Buffer memory DDR2 DRAM 4x Micron 47 64 16 37 As the focus of the module the X5 computing core connects the IO peripherals host communications and support features Each IO device directly connects to the applicatio
31. each source In the fragment above packets containing peripheral IDs greater than the number of enabled channels are discarded Consequently alert packets are not retained or processed Calculate transfer rate in KB s double Period Time Differential if Period FBlockRate Packet DG SizeInBytes Period 1 0e6 X5 RX User s Manual 60 Writing Custom Applications The code fragment above calculates the nominal block processing rate The AveragedRate object Time maintains a moving averaged filtered rate This rate 15 stored in FBlockRate for use by display method of the GUI if Settings LoggerEnable amp amp Logger Logged Start counter Clock Start std stringstream msg msg lt lt Packet size lt lt Packet Size lt lt samples UI Log msg str enabled log the data stream if Settings LoggerEnable Settings PlotEnable if FBlockCount BlocksToLog Logger LogWithHeader Packet Count the blocks gone by on each Channel FBlockCount In this example each received packet is logged to a disk file The packet header and the body are written into the file which implies that a post analysis tool such as BinView will be used to parse channelized data from the file Alternately custom applications may use the Innovative PacketDeviceMap object to conveniently extract channelized data from a packet data source Stop streaming when both Channels ha
32. flow The command channel provides the PCIe host direct access to the computing core logic for status control and initialization Since it is outside the packet system it is less complex to use and provides unimpeded access to the logic The application FPGA image is loaded at power up from onboard flash EEPROM storage Adding New Features to the FPGA X5 RX User s Manual 35 About the X5 Modules The functionality of the computing core can be modified using the FrameWork Logic tools for the X5 module family The tools support development in either VHDL or MATLAB Signal processing data analysis and unique functions can be added to the X5 modules to suit application specific requirements See the X5 FrameWork Logic User Guide for further information X5 PCI Express Interface The X5 module family has a PCI Express interface that provides a lane 2 5 Gbps full duplex link to the host computer The interface is compatible with industry standard PCI Express systems and may be used in a variety of host computers The following standards govern the PCI Express interface on the X5 XMC modules Table 7 PCI Express Standards Compliance Standard Describes Standards Group PCI Express 1 0a PCI Express electrical and protocol standards PCI SIG http www picmg com 2 5 Gbps data rate per lane per direction ANSI VITA 42 XMC module mechanicals and connectors VITA www vita org ANSI VITA 42 3 XMC modul
33. host because the packet is not complete It is best in most cases to just make the data frame that same as packet size so as to avoid this confusion X5 RX User s Manual 97 X5 RX Module External Trigger Input Requirements The external trigger input has the following requirements This signal 15 an AC coupled single ended input on connector J5 RO Table 9 External Trigger Input Requirements Uwe Multi A D Synchronization To synchronize multiple X5 RX cards there are several requirements e cards must receive a synchronous clock or reference clock that is low jitter e All cards must receive a trigger signal that is a precisely time aligned to the input clock e All cards must be ready to take data when the trigger is fired This means that all A D have completed timing calibration and ready to take data Provided that these requirements are met multiple cards can be synchronized for system expansion Achieving precise alignment of the clock and trigger can be difficult because of variations in the clock source and circuitry on the X5 RX Therefore the X5 RX Framework Logic provides programmable time delays on the trigger input relative to the A D sample clock so that the system can be calibrated for timing alignment The programmable timing alignment has a timing resolution of about 78 ps with a range of 5000 ps Bits Function 5 0 IDELAY tap setting 0 min d
34. integrated 4 channel IF digitizing and receivers DDC The X5 XMCs feature a Xilinx Virtex 5 SX95T LX155T core for signal processing and control In addition to the features in the Virtex 5 logic such as embedded multipliers and memory blocks the FPGA computing core has one bank of DDR2 DRAM and two banks of QDR2 SRAM for data buffering and computing memory There are also a number of support peripherals for IO control and system integration Each XMC may have additional application specific support peripherals Table 5 X5 XMC Family Peripherals Peripheral Features interface XMC 3 PCI Express The XMC 3 host interface integrates with PCI Express systems using eight lanes operating at 2 5 Gbps that provides up to 4 GBytes sec data rate on the bus full duplex This interface complies with VITA standard 42 3 which specifies PCI Express interface for the XMC module format The Velocia packet system provides fast and flexible communications with the host using a credit based flow control supporting packet transfers with the host A secondary command channel provides independent interface for control and status outside of the data channel that is extensible to custom applications XMC P16 Provides a bank of digital IO lines which may be used for general purpose bit I O or to implement a private link to cards featuring a parallel data bus Additionally eight independent rocket I O links VITA 42 0 are available
35. kinds of applications are possible with Innovative Integration hardware Data acquisition data logging stimulus response and signal processing jobs are easily solved with Innovative Integration baseboards using the Malibu software There are a wide selection of peripheral devices available in the Matador DSP product family for all types of signals from DC to RF frequency applications video or audio processing Additionally multiple Innovative Integration baseboards can be used for a large channel or mixed requirement systems and data acquisition cards from Innovative can be integrated with Innovative s other DSP or data acquisition baseboards for high performance signal processing Why do I need to use Malibu with my Baseboard One of the biggest issues in using the personal computer for data collection control and communications applications is the relatively poor real time performance associated with the system Despite the high computational power of the PC it cannot reliably respond to real time events at rates much faster than a few hundred hertz The PC is really best at processing data not collecting it In fact most modern operating systems like Windows are simply not focused on real time performance but rather on ease of use and convenience Word processing and spreadsheets are simply not high performance real time tasks The solution to this problem is to provide specialized hardware assistance responsible solely for real time tasks
36. obtain a reference to the internally managed IUsesPmcEeprom object as shown below Open the module Innovative X5 400M Module Module Target 0 Module Open Create a 50 32 bit word section at offset zero in ROM user space PmcIdromSection Sectionl Module IdRom Rom PmcIdrom waUser 0 50 Create a 50 32 bit word section at offset 50 in ROM user space PmcIdromSection Section2 Module IdRom Rom PmcIdrom waUser 50 50 Write to ROM for int i 0 i lt 50 i Sectionl AsInt i i 2 Sectionl StoreToRom for int i 50 i lt 100 i Section2 AsFloat i static_cast lt float gt i 2 Section2 StoreToRom Read from ROM Sectionl LoadFromRom for int i 0 i lt 50 i int x Sectionl AsInt i Section2 LoadFromRom for int i 50 i lt 100 i float x Section2 AsFloat i X5 RX User s Manual 38 About the X5 Modules Digital The X5 series has a digital I O port accessible over the P16 connector that provides bit I O These bits are direct connections to the FPGA and are used in many custom applications for controls communications and status signals The DIO port is presented on P16 See the connectors section of this chapter the connector pin out and information about the connector The Framework Logic User Guide details the FPGA pin connections for the bit I O Available Bit I O The X5 modules bit IO on P16 is shown here For pinout
37. ope e 90 Table 3 Effect of Sample Clock Jitter on Digitizing Accuracy Courtesy Analog Devices Inc 9 Table 4 External PLL Reference Additive Jitter and 22 9 Table 5 External PLL Reference 5 etae erp 9 Table 6 External Clock Input s a doen ttes thee atre tren ela Nee um 94 Table 7 PLL SPI interface esl taut tho Reed NA E 94 Table 8 VCXO control and register 0 801 95 Table 9 External Trigger Input soc eefte 98 Table 10 External Trigger IDELAY Control 98 Table Dl MICE D DOS ev eo A E toasts E d 101 Table 12 Alert Packet Formatar isdem umet ber aene rar NR dta bl ee VER p ea cen v a E ER UNDA 102 Table 13 X5 RX Power qe eb t eb dne Pe a eroe Qe Yt 105 Table 14 X5 RX Environmental DATAS sea cnet UTE DAE B Set PEDE PUR axe 106 Table 15 X5 RX Analog Performance Summary nee ette teen 107 Table 16 A D Signal Quality vs Input 2 108 Table 17 X5 RX XMC Connector P15 PIO Utes ass t rec Poeno aga 117 Table 18 P15 Signal 1 dn tr tdt eue su ee dede 118 Table 19 X5 RX Secondary Connector
38. out the host link From here the Velocia packet system controls the flow of data to the host Data packets flow into host memory for consumption by the host program The Board Basics and Host Communications chapters of this manual discuss the use of the packet data system used on the X5 module family The X5 RX module FrameWork Logic connects the data from A D interface to the packet system by forming the data into 32 bit words of consecutive enabled channels Status indicators for the A Ds are integrated with the alert log to provide host notifications of important events for monitoring the data acquisition process some of which are unique to the X5 RX The complete description of the FrameWork Logic is provided in the X5 RX FrameWork Logic User Guide including the memory mapping register definitions and functional behavior This logic is about 30 of the available logic in the application FPGA Virtex5 SX95T device In many custom applications unused logic functions can be deleted to free up gates for the new application X5 RX User s Manual 99 X5 RX Module Power Controls and Thermal Design The X5 RX module has temperature monitoring and power controls to aid in system integration Also the module has been designed to include conduction cooling to improve heat dissipation from the module These features can make the module more reliable in operation and also reduce power consumption System Thermal Design The X5 RX can d
39. reva test dataVjason s test datalanalog quality reevaluation plot25 bdd 4 Lures Time Frequency Text Summary Server 7872 8279 Amplitude vs Frequency 0 5 00 03 KHz 2 06dB 20 SFDR 86 9 dB NR 76 5 dB 40 NOB 12 0 bits THD 85 6 dB a Noise 121 dB 80 Fin 5 MHz 1 3Vp p Fs 200MSPS 100 FFT 64 120 140 0 10K 20K 30K 40K 50K 60K 70K 80K 90K 100K KHz az S N dB S N d8 SINAD 48 ENOB bits SFDR 48 THD 2 48 Noise 48 981 755 733 120 858 0 005245 85 123 698 0 Leap 55536 Analyze ChO Frequency domain data display Samples 1048636 T start visual Source T sstB pdf Ad fii Analog qualit fi amp My Documents 5 sig quality s E readme Not Figure 1 Wideband Signal Quality Fin 5 MHz 1 3Vp p Fs 200 MSPS X5 RX User s Manual 109 X5 RX Module 5 BinView c projects x5 rx reva test dataVjason s test datalanalog quality reevaluation plot26 bdd nxe 9 Time Frequency Text Summary Server Amplitude vs Frequency s 0 7 00 04 KHz 2 89dB SFDR 71 1 cho 20 SNR 71 1 dB ENOB 11 2 bits THD 82 0 dB 60 Noise 118 dB ls Fin 70 MHz 1 3Vp p 5 80 Fs 200MSPS Y y FFT 641 100 120 5 140 0 10 20 30K 40K 50K 60K
40. system fail If so this may indicate that a system problem must be solved If the module did overheat you should review the thermal design of the system What was the ambient tmeprature when failure occurred Is the air flow adequate Is air flow blocked to the card Did a fan fail If conduction cooling is being used what is the temperature of the surrounding components The heat must be dissipated either through conduction or convection for the module to keep from overheating You should also review application and be sure that you have taken advantage of any power saving features on the module Many of the X5 modules have power saving features that allow you to turn off unused channels reduce clock rates or stop data when the module is not in use Led Indicators The X5 modules have two LEDs available for use by application logic By default the Framework Logic image lights both LEDs light when the Virtex 5 finishes configuration Custom logic designs can use it for any purpose When using the stock firmware the state of user logic LEDs can be controlled using the Innovative X5 400M Led property LEDs NOT Lit with FrameWork Logic Installed If the two LEDs do not light up with the FrameWork Logic installed that means the PCI Express bus did not connect This is a bus error The card cannot communicate with the system Check installation and contact technical support X5 RX User s Manual 45 About the X5 Modules
41. the ConnectTo method Once connected the object is able to call into the baseboard for board specific operations during data streaming If an objects supports a stream type this call will be implemented Unsupported stream types will not compile Lastly we capture and display some information to the screen This includes the logic version bus informaiton and the number of input channels FHwPciClk Module Debug PciClockRate FHwBusWidth Module Debug PciBusWidth DisplayLogicVersion FChannels Module Input Info Channels Channels Similarly the Close method closes the hardware Inside this method first we logically detach the streaming subsystem from its associated baseboard using Disconnect method Malibu method Close 15 then used to detach the module from the hardware and release its resources Applicationlo Close Close Hardware amp set up callbacks void ApplicationIo Close Stream Disconnect StreamConnected false Opened false UI gt Status Stream Disconnected Starting Data flow After downloading interface logic user can setup clocking and triggering options The stream button then can be used to start streaming and thus data flow void ApplicationlIo StartStreaming X5 RX User s Manual 56 Writing Custom Applications if StreamConnected UI gt Log Stream not connected Open the boards return Make sure packets fit
42. the graphical block diagram Simulink environment with Xilinx System Generator Software tools for host development include libraries and drivers for Windows and Linux Application examples demonstrating the module features and use are provided What is Malibu Malibu is the Innovative Integration authored component suite which combines with the Borland Microsoft or GNU C compilers and IDEs to support programming of Innovative hardware products under Windows and Linux Malibu supports both high speed data streaming plus asynchronous mailbox communications between the DSP and the Host PC plus a wealth of Host functions to visualize and post process data received from or to be sent to the target DSP What is C Builder C Builder is a general purpose code authoring environment suitable for development of Windows applications of any type Armada extends the Builder IDE through the addition of functional blocks VCL components specifically tailored to perform real time data streaming functions What is DialogBlocks DialogBlocks is an easy to use dialog editor for your wxWidgets applications generating code and XRC resource files Using sizer based layout DialogBlocks helps you build dialogs and panels that look great on Windows Linux or any supported wxWidgets platform Add context sensitive help text tooltips images splitter windows and more What is wxWidgets wxWidgets was started in 1992 by Julian Smart at the Universi
43. the process 15 interrupted before completion for any reason the Virtex 5 may no longer configure properly or may not communicate properly on the PCIe bus If this occurs then the card can be booted from the backup image or can be programmed using a JTAG cable The backup image or golden image may be used to boot the X5 card by installing a jumper on JP3 This forces the logic loader to load the X5 logic with the backup image The card should boot with the backup image then allowing the primary image to be reprogrammed using the EEPROM applet If the backup image is bad or not available then the card can be programmed with a Xilinx JTAG using a known good image followed by warm boot of the host system to allow the host OS to recognize the X5 module on the PCIE bus Once this 15 accomplished a known good image may be reprogrammed into the EEPROM using the EEPROM exe tool X5 RX User s Manual 49 Writing Custom Applications Writing Custom Applications Most scientific and engineering applications require the acquisition and storage of data for analysis after the fact Even in cases where most data analysis is done in place there is usually a requirement that some data be saved to monitor the system In many cases a pure data that does no immediate processing is the most common application The X3 and X5 XMC card families are high bandwidth analog capture modules with an advanced architecture that provides ult
44. uncertainty for an asynchronous trigger input To guarantee exact triggering no triggering uncertainty the input trigger MUST be synchronous to the sample clock Trigger Source A software trigger or external trigger can be used by the trigger controls Software trigger can always be used but external triggering must be selected The trigger source 15 level sensitive for the continuous mode or edge triggered for the framed mode triggering The Malibu software tools provide trigger source configuration and methods for software triggering re triggering in framed mode and trigger mode controls Framed Trigger Mode Framed trigger mode is useful for collecting data sets of a fixed size each time the input trigger 1s fired In framed mode the trigger goes false once the programmed number of points N have been collected Start triggers that occur during a frame trigger are ignored The maximum number of points per frame 15 16 777 216 2 24 points while the minimum number of points 15 8 Frame size must be a multiple of 8 on the X5 RX Data flow to the host is independent of the framed triggering mode In most cases packet sizes to the host are selected to be integer sub multiples of the frame size to allow the entire data set to flow to the host That way the entire data frame can be moved immediately to the host without waiting for the next trigger frame Decimation The data may be decimated by a programmed ratio to reduce the data rate
45. 3 A4D4 X3 A4D4 LinuxPeriphLib ver rel 1586 rpm Board files and examples X3 SD X3 SD LinuxPeriphLib ver rel 1586 rpm Board files and examples X3 SDF X3 SDF LinuxPeriphLib ver rel 1586 rpm Board files and examples X3 Servo X3 Servo LinuxPeriphLib ver rel 1586 rpm Board files and examples SBC ComEx Sbc ComEx LinuxPeriphLib ver rel 1586 rpm Board files and examples Unpacking the Package As root type rpm i h X5 400 LinuxPeriphLib 1 1 4 i1586 rpm This extracts the X5 400 board files into the Innovative root directory Use the package for the particular board you are installing Creating Symbolic Links The example programs assume that the user has created symbolic links for the installed board packages A script file 1s provided to simplify this operation by the Malibu Red package In the MalibuRed KerPlug directory there is a script called quicklink quicklink X5 400 1 1 These commands will create a symbolic link x5 400 pointing to X5 400 1 1 This script can be moved to the user s bin directory to allow it to be run from any directory X5 RX User s Manual Completing the Board Install Completing the Board Install The normal board install is complete with the installation of the files The board driver install is already complete with the loading of the Malibu Red package If there are any board specific steps they will be listed at the end of this chapter Linux Directory Structure When a bo
46. 4 KHz 2 23dB Cho 3j SFDR 84 4 dB SNR 69 3 dB 40 ENOB 10 9 bits THD 80 2 dB 50 Noise 113 dB Fin 99 MHz 1 3Vp p Fs 200 MSPS 100 FT 64 120 a 140 0 10 20 30K 40K 50K 60K 70K 80K 90K 100K KHz il n S N dB S N dB SINAD 98 ENOB bits SFDR dB THD 48 Noise dB 981 B3 671 10 9 84 4 0 009774 80 298 113 498 Sample Leap 65536 Analze ChO Samples 1048636 start B Analog quality 5 Hardware x5 rx a pdf A ES 15 cap readme Notepad readme Notepad Figure 3 Wideband Signal Quality Fin 99 MHz 1 3 Vp p Fs 200 MSPS X5 RX User s Manual 112 X5 RX Module ax BinView c projects x5 rx reva test dataVjason s test datalanalog quality reevaluation plot28 bdd 9 Time Frequency Text Summary Server ipee Amplitude vs Frequency 5 0 3 50 04 KHz 1 97dB Cho 20 40 60 a 9 80 100 120 E 140 0 10K 20K 30K 40K 50K 60K 70K 80K 90K 100K KHz jl 2 Max S N 48 57848 SINAD 48 ENOB bits SFDR 48 THD 0798 Noise 48 98 1 69 0 647 105 78 6 0 022619 72 998 116 198 Sample 0 Leap 55536 Analyze ChO Samples 1048636 T start Visual Source T sstB pdf Ad fii Analog qualit My Documents Ss Hardw i sig quality s P readme 9 04 PM Figure 4 Wideband Signal Quality Fin 165
47. ATL No Character Set Use Unicode Character Set Common Language Runtime support Common Language Runtime Support Whole Program Optimization No Whole Program Optimization C General Additional Include Directories Malibu PlotLab Include for graph scope display Code Generation Run Time Library Multi threaded Debug DLL Precompiled Headers Create Use Precompile Headers Not Using Precompiled Headers Linker Additional Library Directories Innovative Lib Vc8 If anything appears to be missing view any of the example sample code Vc8 projects X5 RX User s Manual 76 Developing Host Applications DialogBlocks DialogB Locks Project Settings under Linux Project Options Configurations Compiler name Build mode Debug Unicode mode ANSI Shared mode Static Modularity Modular GUI mode GUI Toolkit your choice wxX11 wxGTK 2 etc Runtime linking Static or Dynamic we use Static to facilitate execution of programs out of the box Use exceptions Yes Use ODBC No Use OpenGL No Use wx config Yes Use insalled wxWidgets Yes Enable universal binaries No Debug flags ggdb DLINUX Library path INNOVATIVE Lib Gcc Debug WINDRIVER ib Linker flags AUTO PROJECTDIR Example lcf IncludePath I INNOVATIVE Malibu I INNOVATIVE Malibu LinuxSupport AUTO Paths INNOVATIVE usr Innovative WINDRIVER usr Innovative Wi
48. C Codegear Developers Studio Malibu Examples Snap Bcb11 Microsoft Visual Studio 2008 Examples Snap VC9 Common Host Code Examples Snap Common On the host side the Malibu library is provided in source form plus pre compiled Microsoft Borland or GCC libraries The application code that implements the entirety of the board specific functionality of example is factored into the ApplicationIo cpp h unit All User Interface aspects of the program are completely independent from the code in ApplicationIo which contains code portable to either compilation environment 1 e it is common code While each X5 RX User s Manual 50 Writing Custom Applications compiler implements the GUI differently each version of the example project uses the same file to interact with the hardware and acquire data Program Design The Snap example is designed to allow repeated data reception operations on command from the host As mentioned earlier received data can be saved as Host disk files When using modest sample rates data can be logged to standard disk files However full bandwidth storage of multiple A D channels can require up more capacity so a dedicated RAIDO drive array partitioned as NTFS for data storage may be required or data may have to be cached online and stored after stopping data flow The example application software is written to perform minimal processing of received data and is a suitable template for high bandwidth
49. C Queue Overflow The ADC data queue overflowed indicating the the host did not consume the data quickly enough ADC Trigger The ADC trigger went active ADC Overrange An ADC channel was overranged Alert Packet Format Alert data packets have a fixed format in the system The Peripheral Device Number PDN is programmable in the software and is included in the packet header thus identifying the alert data packets in the data stream The packet shows the timestamp in system time what alerts were signaled and a status word for each alert X5 RX User s Manual 101 X5 RX Module Dword Description 0 Header 1 PDN amp Total 4 of Dwords in packet e g Headers data payload 1 2 0 00000000 2 Alerts Signaled 3 Timestamp 4 0 5 Software Word 10 6 0 12 X 1303000 amp 000 amp mq overflow 0 35 13 unused Table 12 Alert Packet Format Since alert packets contain status words such as temperature for each packet a software alert can essentially be used to read temperature of the module and so that it can be recorded Software Support for Alerts Applications have different needs for alert processing Aside from the bulk movement of data most applications require some means of handling special conditions such as post processing upon receipt of a stop trigger or closing a driver when an acquisition 15 completed When the alert system is enabled the modu
50. FifoOverrunAlert Module Alerts OnInputTrigger SetEvent this amp ApplicationIo HandleInputTriggerAlert Module Alerts OnInputOverrange SetEvent this amp ApplicationIo HandleInputFifoOverrangeAlert This code attaches alert processing event handlers to their corresponding events Alerts are packets that the module generates and sends to the Host as packets containing out of band information concerning the state of the module For instance if the analog inputs were subjected to an input over range an alert packet would be sent to the Host interspersed into the data stream indicating the condition This information can be acted upon immediately or simply logged along with analog data for subsequent post analysis Configure Stream Event Handlers Stream OnDataAvailable SetEvent this amp Applicationlo HandleDataAvailable The Stream object manages communication between the application and a piece of hardware Separating the I O into a separate class clarifies the distinction between an I O protocol and the implementing hardware In Malibu high rate data flow 1s controlled by one of a number of streaming classes In this example we use the events of the PacketStream class to alert us when a packet arrives from the target When a data packet 1s delivered by the data streaming system OnDataAvailable event will be issued to process the incoming data This event is set to be handled by HandleDataAvailable After processing the data
51. I select HS DIV 4 5 6 7 9 or 11 1 to 128 even only so that 4850 lt Foco lt 5670 MHz HS DIV N1 gt 6 for 10 lt Fyco lt 280 MHz 3 Set the VCXO center frequency RFREQ Fpco 114 285 MHz Use 38 bit math with 10 decimal places and 28 fractional bits 4 Calculate PLL settings to generate the sample frequency Fs The PLL analog loop filter is set for a phase comparator frequency of 1 MHz Therefore select R P B and A to satisfy these equations Frrer R 1 MHz Fyco PB A 1 MHz where R 1 to 16383 P 1 2 2 3 4 5 8 9 16 17 32 33 or 3 A 0 to 63 Note R 100 for on card 100 MHz reference Table 2 Steps to Configure the VCXO and PLL Driver code in the Malibu support libraries implements these calculation steps to program the PLL and VCXO When these library functions are used the software checks to verify that all restrictions for VCXO and PLL programming are met and that the output frequency is as close as possible to the desired result Using An External PLL Reference The PLL can use an external clock input as its reference This allows the sample clocks to be synchronous with the external clock Many applications use this to synchronize multi channel systems to sample simultaneously Distributed applications can input time reference from GPS or other network time sources to synchronize systems The external clock must be low phase noise and stable to use as a PLL reference Phase noise on th
52. Innovative Integration X5 RX User s Manual X5 RX User s Manual The X5 RX User s Manual was prepared by the technical staff of Innovative Integration on August 8 2011 For further assistance contact Innovative Integration 2390 A Ward Ave Simi Valley California 93065 PH 805 578 4260 FAX 805 578 4225 email techsprt innovative dsp com Website www innovative dsp com This document is copyright 2011 by Innovative Integration All rights are reserved VSS Distributions X5 RX Documentation Manual X5 RXMaster odm XXXXXX Rev 1 1 Table of Contents MTSU Ot Teed By EMO 7 1 amp CT ET Real Time 1 R diger c P ccc ML Mats XS RS a ace HM Sun 11 W Bat ds E eoa cvs Qul RUD 11 Whats BUE sade E 11 What is 1 1 1 87 dut What is wxWidgets What is Microsoft MS VC a toad 12 What kinds of applicatio
53. Linux support for Malibu and for Innovative products there are versions of the example programs for this platform This section discusses the Linux Wave example The ApplicationIo Class Because we designed the original examples to separate Malibu and Baseboard functionality into a portable class this code can move to the Linux example unchanged So the above discussion of the features of the Applicationlo class is directly applicable to the Linux example In fact the code itself is shared between the platforms Configure Stream Eeprom Debug Analog A Clock D A Config Decimation Trigger p Source Freq MHz Channels O Stack _ Enable Auto External 200 0 Cho Interpolation Factor Delay s Source Mode Frame Count T External Framed Waveform Data Source FPGA Software Enable Type m Type Frequencies MHz a 1 000 Freq MHz Rom 0 000 Sine 95000 Amplitude FS Sine Square Ramp Communications Packet Size Alerts Data Checker 0 10000 Time Stamp C Enable Software Temp Warning Underflow C Trigger Event Log Be sure to read the help file for info on this program located in the root of the this example folder Logic Version 11 Variant 0 Revision 3 Type 0 Pci Express Lanes 8 Stream Connected User Interface Again much of the Wave example s interface is the same as that of the Snap examp
54. Much the same as a dedicated video subsystem 15 required for adequate display performance dedicated hardware for real time data collection and signal processing is needed This is precisely the focus of our baseboards a high performance state of the art dedicated digital signal processor coupled with real time data I O capable of flowing data via a 64 bit PCI bus interface The hardware is really only half the story The other half is the Malibu software tool set which uses state of the art software techniques to bring our baseboards to life in the Windows environment These software tools allow you to create applications for your baseboard that encompass the whole job from high speed data acquisition to the user interface Finding detailed information on Malibu Information on Malibu is available in a variety of forms e Data Sheet http www innovative dsp com products malibu htm X5 RX User s Manual 12 Introduction e On line Help nnovative Integration Technical Support Innovative Integration Web Site www innovative dsp com Online Help Help for Malibu is provided in a single file Malibu chm which is installed in the Innovative Documentation folder during the default installation It provides detailed information about the components contained in Malibu their Properties Methods Events and usage examples An equivalent version of this help file in HTML help format is also available online at http www innovat
55. P16 120 Table 20 P16 Sigal Descriptions asses ed alert a risa qe estes a ED Ehe xe Roos ela bo 120 Table 21 X5 RX JP1 Xilinx JTAG Connector 122 Table 22 X5 RX IPS Boot Image Select oed ede ade en i pete ase ipi edo do 122 List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Vista Verification DANO Oe cu oos eise etae e ss nra eder 16 Innovative Histall Programi ionge tie o eoa toga da E 17 Progress is shown for each SOCOM usos educated eee ipee ere Rear Re Ses 18 ToolSet registration us tto See rese eor tps PRAGA Der PUR epu VE aid 19 BusMaster HEAEIOTIR egeat co yea t fee dedii i EEG e un did une 20 Installatioti COMP eed a 20 Innovative x8 lane PCIe XMC 3 adapter card P N 80259 28 Innovative 30 VPX XMC 3 adapter card P N 80260 28 Innovative Single lane PCIe XMC 3 adapter card P N 80172 29 Innovative PCI 64 66 XMC 3 4x lanes adapter card P N 80167 0 29
56. P16 is also used for system integration including use as a dedicated data channel Compatible Host Cards X6 XMC cards are compatible with the VITA 42 3 PCI Express mezzanine module sites The card form factor is IEEE 1386 with connectors P15 and P16 P15 is used for PCI Express while P16 is used as digital IO unique to the modules The X6 modules mount 10mm from the host card and may use standoffs for mechanically securing the module to the host PCI Express Bus Type Requirement Standard PCI Express 1 0a Lanes 8 Bus Speed Genl 2 5 Gbps per lane per direction Gen2 5 Gbps per lane per direction Power Supplies 3 3V and VPWR 5V or 12V is required on all XMCs Table 1 X6 XMC Bus Requirements Note PCI Express interfaces supports 2 5 Gbps or Gen2 5 Gbps operation For Gen2 the host system must support Gen2 operation in the installed site For Gen2 x8 the X6 module must be ordered with 2 FPGA speed grade or better Adapter cards for XMC modules shown below allow X6 XMC modules to be used in a desktop PCs with PCI Express or PC slots To get out of the PC chassis consider using either the eInstrument Node The eInstrument node can host one XMC using cabled PCI Express using a cable as long as 5 meters For an intelligent computing node the eInstrument PC provides an embedded PC running Windows or Linux disk drives and other PC peripherals with two XMC module sites X5 RX User s
57. This mode 15 usually used when the data rate 15 less than the minimum master clock rate of the A D A D performance is not specified and will degrade sometimes with unpredictable results 1f the converter is operated below its minimum sample rate The decimation simply discards M points for every point kept no averaging or filtering is used When decimation 15 true the number of points captured in the framed mode is the number of decimated points in other words the discarded points do not count Maximum decimation rate is 1 4095 When decimation is used in the framed trigger mode the number of points captured is after decimation The frame count is always the actual number of points inserted into the FIFO X5 RX User s Manual 96 X5 RX Module Trigger Controls in SNAP Example The SNAP example application demonstrates the triggering modes and controls for the X5 RX The trigger controls on the SETUP tab select the trigger source mode and decimation X5 RX PCIe Module Snap Example E lol Configure Stream EEProm Debug Reference r Clock r Communications Source Source Alerts Ext Int C Ext Int PktSize L Time Stamp J Input Overrange _ Software feo mie Frequency 7 0 10000 Input Overrun MHz MHz Input Trigger Trigger Source Frame Mode Software Size Unfra
58. Turb S o rt Oth r CONSIA cuciriui Microsoft Visual 901010 2005 bip ac een Is rasa sc kac lesa oE Lu ES ep EDI a me un r na Chapter d ADDIGIS uii eri cae eh reis ee EHI ete nia Reo Common Vd e nA Registration Utility une e nae Lane coats Reserve Memory Applet 79 Data Analysis Pu ENED PR dedu 79 Binary File Viewer Utility BinView exe 4 cresce cete eere eese eee ee eene sesso sesso esee eee 79 Chapter 5 Applets for the X5 RX 80 Logic Update Utility eue aoro epe oras ot UE Reus bere iaa ken Vea eoru Igne TRUN 4 Chapter iii 9 Hardware PM
59. V the FPGA Output Voltage gt 1 3V For load lt 12mA 0 lt 0 4V Output Current 12mA FPGA can be reconfigured for custom designs for other drive currents X5 RX User s Manual 41 About the X5 Modules Parameter Value Notes Input Logic 1 gt 1 3VDC Thresholds 0 lt 0 8VDC Input Impedance gt 1M ohm 15 pF Excludes cabling Table 12 LVCMOS2 5 Digital IO Bits Electrical Characteristics Notes on Digital IO Use The digital I O on X5 modules as supported using the standard FrameWork Logic is intended for low speed bit I O controls and status The interface 1s capable of data rates exceeding 75 MHz and custom logic developers can implement much higher speed and sophisticated interfaces by modifying the logic Since the bit I O is not connected to the high speed data stream this limits the effective update or read rate to about 1 MHz Custom logic implementations can achieve much higher data rates by creating logic for data packets transfers to the Digital IO The X5 FrameWork Logic user Guide details logic supporting the digital IO port and gives the pin information for customization P16 SERDES The X5 series implements a high speed SERDES communication system on the XMC P16 connector to allow data to be exchanged with the host outside of the PCI Express bus P16 connections on the X5 are compatible with the VITA 42 0 secondary connector specification and pr
60. When streaming the status bar data is collected and X5 RX User s Manual 52 Writing Custom Applications displayed This includes a count of the data blocks received the data rate the measured temperature of the board logic and the digital I O value X5 400M Capture Application Configure Setup Stream Eeprom Debug Before Enable After m C Enable i Data Files Log Overwrite BDD Block Count Rate KB s Temp C Dig In Host Side Program Organization The Malibu library is designed to be rebuildable in each of three different host environments Codegear Developer s Studio C Microsoft Visual Studio 2008 and on Linux Because the library has a common interface in all environments the code that interacts with Malibu is separated out into a class Applicationlo in the files Applicationlo cpp and h This class acts identically in all the platforms The Main form of the application creates an ApplicationIo to perform the work of the example The UI can call the methods of the ApplicationIo to perform the work when for example a button is pressed or a control changed Sometimes however the ApplicationIo object needs to call back into the UI But since the code here is common it can t use a pointer to the main window or form as this would make ApplicationIo have to know details of Borland or the VC environment in use The standard solution to decouple th
61. X has single ended inputs that are 50 ohm terminated The 50 ohm termination is used to match the input cable and connector characteristic impedance The source signal must be able to drive this input impedance to achieve the best signal quality over the input voltage range The signal source must be able to drive 30mA for a full scale input DC current limit is 30 mA X5 RX User s Manual 86 X5 RX Module Overrange Detection The high speed A D detects when an analog overrange occurs and generates an overrange flag The logic receives this overrange detection and can trigger a system alert to notify the application when this error condition has occurred The alert message shows when the overrange occurred in system time and which channels overranged Overrange on the secondary channel is indicated by a full scale output 0x8000 or 7 The secondary channel can show an overrange due to DC signal level even when the high speed A D is within it range since it is AC coupled to the input Custom logic has access to the overrange bits in the A D interface component Each data sample indicates when an overrange occurs as part of its status byte appended to the data This allows implementation of automatic gain controls for auto ranging external front end signal conditioning Sample Rate Generation and Clocking Controls Conversion clock sources on the X5 RX are on card PLL or an external clock reference input gt
62. age File Names A package file name such as Malibu LinuxPeriphLib 1 1 3 1586 rpm encodes a lot of information Malibu Linux PeriphLib 1 1 3 1586 rpm Prerequisites for Installation In order to properly use the baseboard example programs and to develop software using the baseboard some packages need to be installed before the actual baseboard package The Redistribution Package Group MalibuRed This set of packages contain the libraries and drivers needed to run a program using Malibu This group is called MalibuRed because it contains the packages needed to allow running Malibu based programs a target non development machine Red is short for redistributable WinDriver 9 2 1 1586 rpm Installs WinDriver 9 2 release MalibuLinux Red ver rel 1586 rpm Installs Baseboard Driver Kernel Plugin intel ipp rti 5 3p x32 rpm Installs Intel IPP library redistributable files X5 RX User s Manual 23 The Redistribution Package Group MalibuRed The installation CD or the web site contains a file called LinuxNotes pdf giving instructions on how to load these packages and how to install the drivers onto your Linux machine This file is also loaded onto the target machine by the the Malibu LinuxRed RPM These procedures need to be completed for every target machine Malibu To develop software for a baseboard the Malibu packages also must be installed Malibu LinuxPeriphLib ver rel 1586 rpm In
63. al commercial temperature range of 0 to 70 C but this relies on sufficient forced air cooling for most installations and modules At the lower temperatures it is also required that the environment be non condensing for the standard commercial modules Extended temperature versions of many modules are available with conformal coating if the environment is more demanding During operation the module temperature should be monitored to prevent unexpected shutdown If the module temperature exceeds 85C LO rating the module will deactivate on board power supplies to avoid overheating Please refer to the section on thermal properties for more details PCI Express slots are rated for their power capability Each installation should be reviewed to verify that the host card plus the module do not exceed the rated power of the slot The power consumption for each module is provided in the specific discussion of that module Most slots support 15W in desktop systems and provide 3 3V and 12V Some XMC modules require 12V which must be provided by the host card X5 RX User s Manual 31 Hardware Installation Mechanical Considerations The X6 modules conform to IEEE1386 CMC specification and ANSI VITA 42 0 specifications except as specified on individual modules These specifications define the size of the module and mounting requirements In short the modules are 75 x 150 mm and mount 10 mm from the host card This allows the modules to fit i
64. applications The example uses various configuration commands to prepare the module for data flow Parametric information is obtained from a Host GUI application but the code 15 written to be GUI agnostic All board specific I O 15 performed within the ApplicationIo cpp hunit Data is transferred from the module to the Host as packets of Buffer class objects The Host Application The picture to the right shows the main window of an X5 example for the X5 400M This form 15 from the designer of the MSVC 9 0 version of the example but the Borland version is similar It shows the layout of the controls of the User Interface X5 400M Capture Application User Interface Corfigue Setup Steam Eeprom Debug Target tt This application has five tabs Each tab has its 0 own significance and usage though few are interrelated these tabs share a common area which displays messages and feedback throughout the operation of the program Configure Tab As soon as the application is launched the Configure tab is displayed In this tab a combo box 15 available to allow the selection of the Press F1 to see online help for this example device from those present in the system All X5 family devices of whatever type share a sequence of target number identifiers The first board found is Target 0 the second Target 1 and so on Click the Open button to open the driver To change targets click the Close button to clo
65. ard package is installed its files are placed under the usr Innovative folder The base directory is named after the board with a version number attached for example the version 2 0 X5 400 RPM extracts into usr Innovative X5 400 2 0 This allows multiple version of installs to coexist by using a symbolic link to point to a particular version Changing the symbolic link changes with version will be used Under the main directory there are a number of subdirectories Applets The applets subdirectory contains small application programs that aid in the use of the board For example there is a Finder program that allows the user to flash an LED on the board to determine which board is associated with a target number See the Applets chapter for a fuller description of the applets for a board Documentation This directory contains any documentation files for the project Open the index html file in the directory with a web browser to see the available files and a description of the contents Examples This directory and its subdirectories contain the projects source and example programs for the board Hardware This directory contains files associated with programming the board Logic and any logic images provided X5 RX User s Manual 26 Hardware Installation 2 Hardware Installation The X6 XMC cards may be used on a variety of host cards supporting an XMC 3 PCI Express VITA standard 42 3 compatible site
66. at the desired rate and keep only the data that is required On the X5 RX module all A D channels operate synchronously using the same clock and trigger The trigger controls allows data to be acquired continuously or during a specified time as triggered by either a software or external trigger Data can also be decimated to reduce data rates Trigger Mode Data Collected Played Back Start Trigger Stop Trigger Continuous enabled channel pairs Software or rising edge of Software or falling edge of external trigger external trigger Framed N sample points for each of Software or rising edge of Stops when N samples are the enabled channel pairs external trigger collected back Decimation M points are discarded for every point kept May be used with either trigger mode Table 1 Trigger Modes Fs Trigger Analog Input Samples are acquired when trigger is true on rising edges of Fs when trigger is true X5 RX User s Manual 95 X5 RX Module Figure 2 Analog Triggering Timing As shown in the diagram samples are captured on the rising edges of the sample clock when the trigger is true The trigger is true in continuous mode after a rising edge on the trigger input software or external until a falling edge is found The trigger is timed against the sample clock and may have 0 to 1 A D conversion clock
67. ating a new application with File New Forms Application C Builder Change the Project Options for the Compiler Project Options Compiler bcc32 Compatibility Check zero length empty base class Ve Check zero length empty class member functions In our example Host Applications 1f not checked an access violation will occur when attempting to enter any event function Le Access Violation OnLoadMsg Execute Load Message Event Because of statement Board gt OnLoadMsg SetEvent this amp ApplicationIo DoLoadMsg Change the Project Options for the Linker Project Options Linker ilink32 Linking uncheck Use Dynamic RTL In our example Host Applications if not unchecked this will cause the execution to fail before the Form is constructed Error First chance exception at xxxxxxxx Exception class EAccessViolation with message Access Violation Process exe nnnn X5 RX User s Manual 73 Developing Host Applications Other considerations Project Options Compiler bcc32 Output Settings check Specify output directory for object files n release build Release debug build Debug Paths and Defines add Malibu Pre compiled headers uncheck everything Linker ilink32 Output Settings check Final output directory release build Release debug build Debug Paths and Defines ensure that Build Configuration is set to All Configurations add Lib Bcb10 change Build
68. ation X5 RX User s Manual 119 X5 RX Module Table 19 X5 RX XMC Secondary Connector P16 Pinout Column Row A B 1 TXPO TXNO TXPI TXNI 2 DGND DGND DIOO DGND DGND DIOI 3 TXP2 TXN2 TXP3 TXN3 4 DGND DGND DIO2 DGND DGND DIO3 5 TXN4 5 5 6 DGND DGND DIO4 DGND DGND DIOS 7 TCP6 TXN6 TXP7 TXN7 8 DGND DGND DIO6 DGND DGND DIO7 9 10 DGND DGND DIO8 DGND DGND DIO9 11 RXNO RXPI RXNI 12 DGND DGND DIO10 DGND DGND DIOII 13 RXP2 RXN2 RXP3 RXN3 14 DGND DGND DIO12 DGND DGND DIO13 15 RXP4 RXN4 5 RXNS 16 DGND DGND DIO14 DGND DGND DIOI5 17 RXP6 RXN6 RXP7 RXN7 18 DGND DGND DGND DGND 19 Note All unlabeled pins are not used by X5 modules but may defined in VITA42 and VITA42 3 specifications Table 20 P16 Signal Descriptions Signal Description DIOO 15 Digital IO 0 15 TXPO 7 SERDES transmit positive TXNO 7 SERDES transmit negative RXPO0 7 SERDES receive positive RXNO 7 SERDES receive negative DGND Ground X5 RX User s Manual 120 X5 RX Module Xilinx JTAG Connector is used for the Xilinx JTAG chain It connects directly with Xilinx JTAG cables such as Parallel Cable IV or Platform USB Connector Types 14 pin dual row male header 2mm pin spacing right angle Number of Connections 14 arranged as 2 rows of 7 pins each Co
69. cal Specifications seen 88 Figure 3 SNAP Example Sample Clock Controls eth eec aue Rena Ones eee 89 Figure 1 Clock Path Using External Reference a duc bom ret sb 92 Figure 1 Clock Path Using External eerte oer e On rre tr pec deu HE 93 Fip te 2 Analog Triggering sac cod a e PER ore YA ER ERI IR ER QA eA RN 96 Figure 3 X5 RX SNAP Example Triggering Controls sess 97 Figure 4 X5 RX FrameWork Logic Data BON eee 99 Figure 5 Typical Performance Evaluation eo ero ed teet ue o d pe at ped dta 104 Figure 6 Frequency Response for 1 MHz to 1 2GHZz span emen 107 Figure 7 Frequency Response for 5 MHz to 400 MHZ span ener 108 Figure 8 A D Signal Quality vs Input uec erra etr dre dc seed da Seon rae oet 109 Figure 1 Wideband Signal Quality Fin 5 MHz 1 3Vp p Fs 200 5 109 Figure 1 Wideband Signal Quality Fin 70 MHz 1 4Vp p Fs 200 8 86 22 2 110 Figure 2 Narrowband Signal Quality Fin 70 MHz 1 4Vp p Fs 200 111 Figure 3 Wideband Signal Quality Fin 99 MHz 1 3 Vp p Fs 200 112 Figure 4 Wideband Signal Quality Fin 165 MHz 1 3Vp p Fs 200
70. ceding code fragment The logic has a decimation feature where samples are discarded to reduce the sample rate If used all but one of every N samples are discarded If no decimation 15 desired the default value of 1 should be used All channels trigger together Module Input ExternalTrigger Settings ExternalTrigger 1 Samples will not be acquired until the channels are triggered Triggering may be initiated by a software command or via an external input signal to the Trigger SMA connector The code fragment above selects the trigger mode Frame count in units of packet elements if Settings Framed Module Input Framed Settings FrameCount else Module Input Unframed The module supports framed triggering where a single trigger enables many data samples to be taken before rechecking the trigger This code enables framed mode or disables it depending on the settings enum IUsesX5Alerts AlertType Alert IUsesX5Alerts alertTimeStampRollover IUsesX5Alerts alertSoftware IUsesX5Alerts alertWarningTemperature IUsesX5Alerts alertInputFifoOverrun IUsesX5Alerts alertInputTrigger IUsesX5Alerts alertInputOverrange for unsigned int i 0 i lt Settings AlertEnable size 1 Module Alerts AlertEnable Alert i Settings AlertEnable i true false The fragment above enables alert generation by the module The GUI control includes check boxes for each of the types of alerts of which the module is ca
71. d whether the module is currently triggered These values are initialized prior to each streaming run Channel Enables Module Output Info Channels DisableAll X5 RX User s Manual 57 Writing Custom Applications Module Input Info Channels DisableAll for int i 0 i lt Channels i bool active Settings ActiveChannels i true false if active true Module Input Info Channels Enabled i true X5 400M IIClockSource src X5_400M csExternal X5 400M csInternal Module ClockSource src Settings SampleClockSource int ActiveChannels Module Input Info Channels ActiveChannels if lActiveChannels UI gt Log Error Must enable at least one channel UI gt AfterStreamAutoStop return The module supports up to 2 channels of simultaneous data The previous call to GetSettings populated the Settings object with the number of channels to be enabled on this run That information is used to enable the required channels via the Channels object within the Module Input Info object The clock source is also programmed using its property Packets scaled in units of events samples per each enabled channel int SamplesPerWord 1 Module ReturnPacketSize Settings PacketSize ActiveChannels SamplesPerWord 2 The size of the data packets sent from the module to the Host during streaming is programmable This is helpful during framed acquisition since the pac
72. e module They display feedback during the loading of the user logic and when script is used Configure Module Event Handlers Module OnBeforeStreamStart SetEvent this amp ApplicationIo HandleBeforeStreamStart Module OnBeforeStreamStart Synchronize Module OnAfterStreamStart SetEvent this amp ApplicationIlo HandleAfterStreamStart Module OnAfterStreamStart Synchronize Module OnAfterStreamStop SetEvent this amp ApplicationIo HandleAfterStreamStop Module OnAfterStreamStop Synchronize Similarly HandleBeforeStreamStart HandleAfterStreamStart and HandleAfterStreamStop handle events issued on before stream start after stream start and after stream stop respectively These handlers could be designed to perform multiple tasks as event occurs including displaying messages for user These events are tagged as Synchronized so Malibu will marshal the execution of the handlers for these events into the main thread context allowing the handlers to perform user interface operations X5 RX User s Manual 54 Writing Custom Applications Alerts Module Alerts OnTimeStampRolloverAlert SetEvent this amp ApplicationIo HandleTimestampRolloverAlert Module Alerts OnSoftwareAlert SetEvent this amp ApplicationIo HandleSoftwareAlert Module Alerts OnWarningTemperature SetEvent this amp Applicationlo HandleWarningTempAlert Module Alerts OnInputFifoOverrun SetEvent this amp ApplicationIo HandleInput
73. e Alert features and the input data packets size Checking the box next to an alert will allow the logic to generate an alert if the condition occurs This alert can then be left in the data stream or extracted to notify the application In the Channels section we can specify number of channels to activate Selecting a channel will flow data from that data source The Trigger selection box controls the way that data streaming is started It can be started by an external signal or by the software Data can also be collected into frames In this mode a trigger will collect multiple samples before checking the trigger again By default trigger source is set to software triggering though external trigger can be provided once selected The Digital field configures the onboard digital I O The Data Logging option determines if data streaming stops after collecting points a Snapshot of data or streams forever until manually stopped The module supports test mode for module debugging and system test The Test Counter Enable is used to turn on test mode and substitutes a ramp signal with channel number in the upper byte of the data The Decimation section sets up the decimation logic to discard data reducing the incoming data rate Stream Tab The two buttons in the button bar start and stop data streaming Press the running man button to start streaming data Press the stop button to stop streaming unless the stream has stopped itself
74. e Applicationlo from the form is to use an Interface class to hide the implementation An interface class is an abstract class that defines a set of methods that can be called by a client class here ApplicationIo The other class produces an implementation of the Interface by either multiple inheriting from the interface or by creating a separate helper class object that derives from the interface In either case the implementing class forwards the call to the UI form class to perform the action ApplicationIo only has to know how to deal with a pointer to a class that implements the interface and all UI dependencies are hidden The predefined UserInterface interface class is defined in Applicationlo h The constructor of ApplicationIo requires pointer to the interface which is saved and used to perform the actual updates to the UI inside of ApplicationIo s methods Applicationlo Initialization The main form creates an Applicationlo object in its constructor The object creates a number of Malibu objects at once as can be seen from this detail from the header Applicationlo h X5 RX User s Manual 53 Writing Custom Applications Member Data Innovative X5 400M Module IUserInterface UI Innovative PacketStream Stream IntArray _Rx unsigned int Cursor 1164 BlocksToLog bool Opened bool Stopped bool StreamConnected nnovative StopWatch Clock nnovative DataLogger Logger ntArray DataRead nnovat
75. e reference will directly result in phase noise on the generated clock This means that the phase noise must be very low typically less than 200 fS RMS to be clean enough not to influence the acquired signal The following graph shows the effect of jitter on the sample accuracy and noise level X5 RX User s Manual 90 X5 RX Module 100 16 BITS 90 is 14 BITS _ 80 m 5 z 12 BITS 70 10 BITS 60 B 50 10 100 1000 INPUT MHz 01399 005 Table 3 Effect of Sample Clock Jitter on Digitizing Accuracy Courtesy Analog Devices Inc The PLL reference clock multiplexer device also adds jitter to the input reference clock This noise must be root sum squared RSS with the reference clock jitter Parameter Worst Additive Jitter 50 fs Delay 1 15 ns typical 1 45 ns max Table 4 External PLL Reference Additive Jitter and Delay The external clock must also be stable within the tracking range of the PLL VCXO This requirement limits the amount of low frequency wander and drift that external clock can have without making the PLL lose lock External Reference Clock Parameter Limit Frequency Stability 3000 PPM Jitter 200 fs RMS recommended for analog input signals with lt 500 MHz bandwidth Table 5 External PLL Reference Requirements X5 RX User s Manual X5 RX Module The following diagram shows the clock path when an external
76. e with PCI Express Interface VITA www vita org The major interfaces to the application logic are the data link command channel and SelectMAP interface The data link provides a high performance channel for the application logic to communicate with the host computer while the Command Channel is a command and control interface from the host computer to the application logic The SelectMAP interface is the application FPGA configuration port for loading the logic image The data link is the primary data path for the data communications between the application FPGA and host computer When data packets are created by the application logic such as A D samples or required by the application logic for output devices such as DAC channels the data flows over the data link as packets The maximum transfer rate over the data link is 2000 MB s with 1200 MB s sustained rate half duplex The data packets contain a Peripheral Device Number PDN that identifies the peripheral associated with the this data packet In this way the packet system is extensible to other devices that may be added to the logic For example an FFT analysis can be added to the logic and its result sent to the host as a new PDN for display and further analysis while maintaining other data streams from A D channels Application Logic Max Data Rate Typical Use Interface Velocia Packet Interface 1000 MB s sustained to host memory Velocia packet system interface main pat
77. eaming First have UI get settings into our settings store UI GetSettings if Settings TestEnable Module Output TestEnable Settings TestEnable Module Output TestMode Settings TestMode Module Output TestFrequency Settings TestFrequency if SampleRate gt Module gt Output Info MaxRate UI gt Log Sample rate too high StopStreaming UI gt AfterStreamAutoStop return FBlockCount 0 FBlockRate 0 FTriggered 1 The first difference is that we configure the Output sub object instead of Input The X5 Family divides the interface functions for Input and Output devices into separate configuration sub objects This allows Input and Output to be independently configured Channel Enables Module Output Info Channels DisableAll for int i 0 i lt Channels i if Settings ActiveChannels i true Module Output Info Channels Enabled i true int ActiveChannels Module Output Info Channels ActiveChannels if lActiveChannels UI gt Log Error Must enable at least one channel UI gt AfterStreamAutoStop return FStreaming true Set Decimation Factor int factor Settings DecimationEnable Settings DecimationFactor X5 RX User s Manual 68 Writing Custom Applications Module Output Decimation factor All channels trigger together Module Output ExternalTrigger Settings E
78. elay 63 max delay 78 ps per tap 31 6 unused Table 10 External Trigger IDELAY Control 0x80A r w During system test the trigger delay 15 adjusted so that the data capture on all cards is synchronous This requires a precisely synchronized trigger clock and input signal so that the digitized signal can be used to tune the trigger timing FrameWork Logic Functionality The FrameWork Logic implements a data flow for the X5 RX that supports standard data acquisition functionality This data flow when used with the supporting software allows the X5 RX to act as a data acquisition card with 512MB of data X5 RX User s Manual 98 X5 RX Module buffering and high speed data streaming to the host PCI Express The example software for the X5 RX demonstrates data flow control logic loading and data logging Host Card Data Link 4 channels Ext Trigger Figure 4 X5 RX FrameWork Logic Data Flow The data flow 15 driven by the data acquisition process Data flows from the A D devices into the A D interface component in the FPGA as controlled by the triggering The data is then corrected for gain and offset errors associated with the analog inputs After error correction the enabled channels flow to the data buffer The data buffer implements a data queue in the DRAM The packetizer pulls data from the queue creates data packets of the programmed size and sends those to the PCIe interface logic or
79. emperature condition within the Virtex 5 device In the event of an over temperature condition the logic memory interface and analog power supplies are disabled shutting down power to most of the X5 module The host system power must be toggled in order to reset the module from this condition The Framework Logic implements this feature as standard Although it is possible for custom user logic to remove this feature it is not recommended as it would expose the hardware to potential damage from over temperature conditions should they occur The power enable signal is on Virtex 5 pin AF13 This pin must be held high to enable power Software support tools provide convenient access to the temperature and thermal controls These should be used in application programming configure and monitor the temperature as illustrated below Open the module Innovative X5 400M Module Module Target 0 Module Open Create reference to thermal management object on module const LogicTemperatureIntf amp Temp Module Thermal Read current temperature float t Module LogicTemperature Read write current warning temperature float t Module LogicWarningTemperature Module LogicWarningTemperature 70 0 Read current failure temperature float t Module LogicFailureTemperature S if the module is in thermal shutdown bool state Module Failed Xb amp RXUse rsManual About the X5 Modul
80. er up After completing the installation boot your system into Windows Innovative Integration boards are plug and play compliant allowing Windows to detect them and auto configure at start up Under rare circumstances Windows will fail to auto install the device drivers for the JTAG and baseboards If this happens please refer to the TroubleShooting section Installation on a Deployed System The above instructions install the complete development platform onto a system for the development of application software Often however a developed application needs to be installed on a system that will only be used to run the program In this instance installing the complete library is overkill To support this situation Innovative has a minimal installation program called MalibuRED This is short for Malibu Redistributable This install will install the driver software and support DLLs required to run a Malibu application Note Specific applications may have their own additional requirements that are not covered by MalibuRED For example NET applications require the NET libraries to be installed as well Installation programs for NET can be obtained from Microsoft over the Internet Running MalibuRed MalibuRED can be found on the installation CD in the Windows 32 Malibu subdirectory The name of the installation file is MalibuRED exe Running the program displays the setup screen for the installer Select your baseboa
81. es Thermal Failures The X5 modules will shut down if the Virtex 5 die temperature exceeds 85 degrees Celsius This means that something is wrong either with the module or with the system design Damage may occur if the module temperature exceeds this limit If your software was monitoring the alert packets you will receive a temperature warning alert prior to failure Otherwise the temperature reading in the application may provide information pointing to overheating The most important thing to do 15 to determine the root cause of the failure The module could have failed the system power is bad or the environment is too harsh The first thing to do is inspect the module Is anything discolored or do any ICs show evidence of damage This may be due to device failure system power problems or from overheating If damage is noticed the module is suspect and should be sent for repair If not test the module outside the system in a benign environment such as on an adapter card in a desktop PC with a small fan It should not overheat If it does this module is is now bad Now consider what may have caused the failure A bad module could be the cause but it could have went bad due to system failure or overheating The system power supply could cause a failure by not providing proper power to the module This could be too little power resulting in the module failing or power glitches causing the temp sensor to drop out Did other cards in the
82. eset method which performs a board reset to put the board into a known good state Note that reset will stop all data streaming through the busmaster interface and it should be called when data taking has been halted The size of the busmaster region 15 changeable by using the BusMasterSize property before opening the board Larger values allow more overlap between the board and application at the cost of slower allocation at startup time Open Devices FBusmasterSize 1 lt lt Settings BusmasterSize 22 Module BusMasterSize FBusmasterSize X5 RX User s Manual 55 Writing Custom Applications Module Target Settings Target Module Open Module Reset UI gt Status Module Device Opened Opened true This code shows how to open the device for streaming Each baseboard has a unique code given in a PC For instance if there are three boards in a system they will be targets 0 1 and 2 The order of the targets 15 determined by the location in the PCIe bus so it will remain unchanged from run to run Moving the board to a different PCIe slot may change the target identification The Led property can be use to associate a target number with a physical board in a configuration Connect Stream Stream ConnectTo amp Module StreamConnected true UI gt Status Stream Connected Once the object is attached to actual physical device the streaming controller associates with a baseboard by
83. functions for configuration of the CDCDE72010 device This software configures the device for the clock selection and programs the output dividers External Clock Requirements The external clock input has the following requirements This signal is an AC coupled input Larger input amplitudes usually result in better A D performance X5 RX User s Manual 93 X5 RX Module ESO UE pee m Input Frequency 500 MHz Input Amplitude 0 15 V ff BV Peak to peak Input Capacitance 15 pF PF Excludes cabling Table 6 External Clock Input Requirements CDCDE72010 SPI Port The CDCDE72010 PLL Buffer device is configured through its SPI serial port This port is mapped to the PCI Express bus as memory mapped register at address BAR1 0x801 Writes to this register transmit to the CDCDE72010 device reads from this address first transmit an address to the CDCDE72010 device then receive the current value Before any read write is performed the SPI READY bit should be read to and must be true 1 Bits Function 31 0 SPI write data Table 7 PLL SPI interface 0x801 r w The CDCDE72010 has an extensive set of registers in the device for configuration and status Consult the CDCDE72010 data sheet for details VCXO DC Port This register is an an I2C port that programs the VCXO for the PLL The VCXO is a Silicon Labs SI571 device offering a programmable center frequency controlled over its I2C port Sof
84. gration with your registration information you will receive The unlock code necessary for unrestricted use of the Host applets A WSC tech support service code enabling free software maintenance downloads of development kit software and telephone technical hot line support for a one year period X5 RX User s Manual Telephone Country Code Area Code Number Extension Fax pm pr p Company Name Innovative Integration Address Ciy State Country Postal Code p Product Board Vista 7 Access Code 35845148 22 Help Register Now Ok 78 Applets Reserve Memory Applet ReserveMemDsp exe Each Innovative PCI based DSP baseboard requires 2 to 8 MB of memory to be reserved for its use depending on the rates of bus master transfer traffic which each baseboard will generate Applications operating at transfer rates in excess of 20 MB sec should reserve additional contiguous busmaster memory to ensure gap free data acquisition To reserve this memory the registry must be updated using the ReserveMemDsp applet If at any time you change the number of or rearrange the baseboards in your system then you must invoke this applet to reserve the proper space for the busmaster region See the Help file ReserveMemDsp hlp for operational details Data Analysis Applets Reserve Memory for Dsp Baseboards f Number Installed Matador fam
85. h for data communications Wishbone SOC Bus 20 5 sustained System On Chip bus for command control and status This bus is used to connect logic components in the FPGA X5 RX User s Manual 36 About the X5 Modules Table 8 Interfaces from PCI Express to Application Logic Data Buffering and Memory Use There are two sets of memory devices attached to the application FPGA that provide data buffering and computational RAM for FPGA applications Computational SRAM The X5 modules have two banks of 2MB QDR SRAM dedicated as FPGA local memory Applications in the FPGA may use the SRAM as a local buffer memory if the data buffer is too large to fit in FPGA block RAMs or as memory for embedded processor in the FPGA The SRAM devices connected to the FPGA are 4 Mbytes total size organized as two banks of 16Mbitx32 dual ported memory This device is an Cypress CY7C1314 or equivalent which is a synchronous QDR2 SRAM and supports clock rates up to 167 MHz All SRAM control and data lines pins are directly connected to the FPGA allowing the SRAM memory control to be customized to the application The Framework Logic provides a simple SRAM interface that can be readily modified for many types of applications Detailed explanation of the interface control logic is described in the FrameWork Logic User Guide The SRAM has high performance FIFO interface that allows the logic to fully exploit the high data rates
86. he Modules In this chapter we will discuss the common features of the X5 module family Specifics on each module are covered in later chapters X5 XMC Architecture The X5 XMC modules share a common architecture and many features such as the PCI Express interface data buffering features the Application Logic and other system integration features This allows the X5 XMC modules to utilize common software and logic firmware while providing unique analog and digital features X5 Family Block Diagram Ext Clk Trigger X5 RX User s Manual 33 About the X5 Modules Figure 15 X5 XMC Family Block Diagram The X5 XMCs have a variety of analog and digital IO front ends suited to many applications Table 4 X5 XMC Family X5 XMC Features Applications X5 400M 2 A D channels 14 bit 400MHz 2 D A channels up to Software radio RADAR medical imaging 500M updates sec X5 210M 4 A D channels 14 bit 250 MHz Software radio RADAR X5 GSPS 2 A D channels 8 bit at 1 5GSPS IF RF receivers and test RADAR X5 COM 4 SFP ports at 3 125 Gbps Remote IO system expansion X5 TX 4 DAC channels 16 bit 500 MSPS each or dual channel Arbitrary waveform generation GSPS pattern generation mode for DRAM communications waveform generation X5 G12 2 A D channels 12 bit at 1GSPS integrated FFT engine RADAR communications receivers pulse digitizing X5 RX 4 A D channels 16bit 200 MHz
87. her wrong or the channel is damaged Using the X5 RX Where to start The best place to start with the X5 RX module is to install the module and use the SNAP example to acquire some data This program lets you log data from the module and use all the features like triggering clocks alerts and calibration ROM You can use this program to acquire some data and log it to disk This should let you verify that the module can acquire the data you want and give you a quick start on deciding what sample rates to use how to trigger the data acquisition best for your application and just get familiar with using the module The program also shows how to use BinView a data analysis and viewing program by Innovative that will let you see what you acquired in detail Both time domain and frequency domain data can be viewed and analyzed Data can also be exported to programs like Excel and MATLAB for further analysis Before you begin to write software taking a look at SNAP will allow you see everything working You can then look at the code for SNAP and modify it for your application or grab code from it that 1s useful X5 RX User s Manual 103 X5 RX Module Getting Good Analog Performance The X5 RX is capable of digitizing very high frequency signals To maximize signal to noise ratio and spur performance it 15 important to use do the following Use only low jitter clock sources The higher the input output frequency the more se
88. ily z Type System 2048 BM Region Size KB 2048 Rsv Region Size KB Configualim 1 Total physical memory MB 255 Non paged pool size 4 Status k Update Exit Ready Binary File Viewer Utility Bin View exe BinView is a data display tool specifically designed to 3 BinView c vista vistat 1 dump bin allow simplified viewing of binary data stored in data ZBROJ files or a resident in shared DSP memory Please see Time Frequency Text Summar Server Inl xl on line BinView help file in your Binview installation lt ZoomOut Zomlh gt gt gt directory Amplitude vs Offset Counts e9 e e 0 10 20 30 40 50 Offset KH Leap 10 60 70 80 90 100 Span 100 Analyze Cho Samples 4096 X5 RX User s Manual T9 Applets for the 5 Baseboard Chapters Applets for the X5 RX Baseboard These support applets are used by all X5 cards Logic Update Utility VsProm exe The Logic Update Utility applet is designed to allow field upgrades of the logic firmware on the X5 module The utility permits an embedded firmware logic update file to reprogrammed into the baseboard Flash ROM which stores the personality of the board Note that this utility should only be used after firmware development and debugging has been completed
89. imate flexibility and speed for the most advanced hardware assisted signal processing and ultrasonic signal capture The maximum data rate from these module are often above 250 Msamples s This means that a simple logger that saves all of the data to the host disk is not feasible using standard operating system disk I O calls as the slower disk writes eventually cause overflow and data loss in the streaming system Some modules support decimation so that long duration samples be taken without data Also quick snapshots of analog data can be taken without loss as long as the amount of data is less than the net capacity of system memory and what the baseboard holds The example program provided for nearly all cards is this limited capacity data logger called the Snap example The Snap Example The Snap example in each software distribution demonstrates this logging functionality It consists of a host program in Windows which works with the logic provided on the board s flash to stream data to the host It uses the Innovative Malibu software libraries to accomplish the tasks Tools Required In general writing applications for the X5 family requires development of host program This requires a development environment a debugger and a set of support libraries from Innovative Table 15 Development Tools for the Windows Snap Example Processor Development Environment Innovativ Project Directory e Toolset Host P
90. installation for each environment It is important that this script be run to launch an install When installing on a Vista OS the dialog below may pop up In each case select Install this driver software anyway to continue gt Don t install this driver software You should check your manufacturer s website for updated driver software for your device Install this driver software anyway Only install driver software obtained from your manufacturer s website or disc Unsigned software from other sources may harm your computer or steal information See details Figure 1 Vista Verification Dialog X5 RX User s Manual 16 Windows Installation The Installer Program After launching Setup you will be presented with the following screen product to install product to install hd FA DREA Innovative 3 Change Components to Install for Quadia Quadia Applets examples Docs and Pismo libraries Malibu Host libraries utilites Docs drivers amp DLLs BinView Data graphing and analysis tool CodeHammer JT G support for Code Composer Studio Innovative Components C Builder Support Product Registration ONE ONE Using this interface specify which product to install and where on your system to install it Figure 2 Innovative Install Program 1 Select the appropriate product from the Product Menu 2 Specify the path where the development package files are to be insta
91. issipate upwards of 25 watts depending on the features in use and details of the logic design such as the rate of data processing Forced air cooling may be required depending on the power dissipation and the ambient operating temperatures This requirement is highly application dependent and must be evaluated for each application and installation If forced air cooling 15 not used conduction cooling 15 another method of dissipating the module heat A thermal plane in the card 15 attached to thermal conduction surfaces on each side of the module The card can then be cooled by mounting the card on host card that supports conduction cooling per VITA specification 20 The conduction cooling method allows the module heat to be flowed out to the chassis The thermal plane has NO electrical connection in the module and cannot be used as a ground Temperature Sensor and Over Temperature Protection The Virtex 5 System Monitor temperature sensor 15 described in detail in the Board Basics chapter of this manual The temperature sensor 15 used to monitor the Virtex 5 junction temperature and deactivate board power supplies to protect the logic device from overheating Alert Log Overview X5 modules have an Alert Log that can be used to monitor the data acquisition process and other significant events Using alerts the application can create a time history of the data acquisition process that shows when important events occurred and mark the data stream
92. ive BinView Graph nnovative Scripter Script float ActualSampleRate std string Root nnovative AveragedRate Time double FBlockRate std string FVersion nnovative SoftwareTimer Timer In Malibu objects are defined to represent units of hardware as well as software units The X5 400M object represents the board The PacketStream object encapsulates supported board specific operations related to I O Streaming A Scripter object can be used to add a simple scripting language to the application for the purposes of performing hardware initialization during FPGA firmware development The Buffer class object is used to access buffer contents When the Open button 15 pressed the application io object begins the process of setting up the board for a run The first thing done is to link Malibu software events to callback functions in the applications by setting the handler functions Hook script event handlers Script OnCommand SetEvent this amp ApplicationIo HandleScriptCommand Script OnMessage SetEvent this amp ApplicationlIo HandleScriptMessage This code attaches script event handlers to their corresponding events Malibu has a method where functions can be plugged into the library to be called at certain times or in response to certain events detected Events allow a tight integration between an application and the library These events are informational messages issued by the scripting and logic loader feature of th
93. ive dsp com support onlinehelp Malibu Innovative Integration Technical Support Innovative includes a variety of technical support facilities as part of the Malibu toolset Telephone hotline supported is available via Hotline 805 578 4260 8 00AM 5 00 PM PST Alternately you may e mail your technical questions at any time to techsprt innovative dsp com Also feel free to register and browse our product forums at http forum iidsp com which are an excellent source of FAQs and information submitted by Innovative employees and customers Innovative Integration Web Site Additional information on Innovative Integration hardware and the Malibu Toolset is available via the Innovative Integration website at www innovative dsp com Typographic Conventions This manual uses the typefaces described below to indicate special text Typeface Meaning Text in this style represents text as it appears onscreen or in code It Source Listing also represents anything you must type Boldface Text in this style is used to strongly emphasize certain words X5 RX User s Manual 13 Introduction Emphasis Cpp Variable Cpp Symbol KEYCAPS Menu Command X5 RX User s Manual Text in this style is used to emphasize certain words such as new terms Text in this style represents variables Text in this style represents C identifiers such as class function or type names Text in this style indica
94. ket size can be tailored to match a multiple of the frame size providing application notification on each acquired frame In other applications such as when an FFT is embedded within the FPGA the packet size can be programmed to match the processing block size from the algorithm within the FPGA Start Loggers on active channels if Settings PlotEnable Graph Quit if Settings LoggerEnable Settings PlotEnable Logger Start BlocksToLog Settings SamplesToLog Settings PacketSize Settings SamplesToLog Settings PacketSize 1 0 Stopped false The example illustrates logging data to a disk file with post viewing of the acquired data using BinView The code fragment above closes any pending instance of BinView and logger data files Module Dio DioPortConfig Settings DioConfig The module supports programmable bit I O available on connector JP16 The code fragment above programs the direction of these DIO bits in accordance with the settings from the GUI X5 RX User s Manual 58 Writing Custom Applications Set test mode Module Input TestEnable Settings TestCounterEnable Set Decimation Factor int factor Settings DecimationEnable Settings DecimationFactor 0 Module Input Decimation factor For test purposes the FPGA firmware supports replacement of analog input samples with ascending ramp data If the test counter is enabled in the GUI it is applied to the hardware using the pre
95. l The secondary channel digitizes at rates up to fs 8192 resulting in a bandwidth of about DC to 60 kHz This does NOT overlap with the high speed channel which has negligible response below 500 kHz The low speed secondary channel are time synchronous with the the high speed channels using a sample clock derived from the high speed sample clock The data is available as a separate data source that is time aligned with the high speed data If the secondary channel is not used it can be simply ignored The secondary channel inputs are DC coupled copies of each input The secondary channel has very high input impedance 71M ohm to minimize signal loading Data output codes from the secondary low speed A D channels are 2 s complement 16 bits The following table gives the transfer function Input voltage V Secondary A D Conversion Code hex 1 5 Ox7FFF 0 75 Ox3FFF 0 0x0000 0 75 0 000 1 5 0 8000 Table 18 Secondary Low Speed A D Conversion Coding Note The A D converter inputs are DC coupled to the secondary input channel but are 50 ohm terminated for high speed signals You will observe that low frequency signals are NOT 50 ohm terminated because the transformer blocks the low frequency inputs Therefore if your 50ohm signal source is calibrated for a 50 ohm termination the signal will appear to be twice the magnitude that is expected for low frequency tests Driving the A D Inputs The X5 R
96. l I O configuration control and data register Port direction is controlled by the configuration control register Note that modules have differing number of digital IO bits so not all bits are available on all modules Bit Function 0 DIO bits 7 0 direction control 0 input default 1 DIO bits 15 8 direction control 0 input default 2 DIO bits 23 16 direction control 0 input default 3 DIO bits 31 24 direction control 0 input default 4 DIO bits 39 32 direction control 0 input default 31 6 Figure 16 DIO Control Register BAR1 0x14 Port Address DIO L BAR1 0x13 DIO H 1 0 16 Figure 17 Digital IO Port Addresses Data may be written to read from the digital I O port using the digital I O port data registers Data written to ports bits which are set for output mode will be latched and driven to the corresponding port pins while data written to input bits will be ignored The input DIO may be clocked externally by enabling the external digital clock bit in the appropriate configuration register If the internal clock is used the data is latched at the beginning of any read from the port Data read from output bits is equal to the last latched bit values 1 e the last data written to the port by the host Digital I O port pins are set to all inputs after logic configuration External signals connected to the digital I O port bits or timer input pins should
97. le described above An exception is the Waveform Data Source section that configures the output waveform There are two potential sources for a waveform The first is the FPGA can generate a test waveform internally that is either a ramp or the sum of two sine waves The FPGA group allows this to be configured If the Enable box is checked the logic generator will be used X5 RX User s Manual 71 Writing Custom Applications Alternatively the software can generate a waveform to be played This is configured by the Software section The frequency and amplitude of the wave can be controlled or the data can be read from a file A single block is pre calculated with this waveform and sent when data 15 needed This avoids issues with the speed of calculation of a buffer when data is required at the cost of some flexibility X5 RX User s Manual 72 Developing Host Applications Developing Host Applications Developing an application will more than likely involve using integrated development environment IDE also known as an integrated design environment or an integrated debugging environment This is a type of computer software that assists computer programmers in developing software The following sections will aid in the initial set up of these applications in describing what needs to be set in Project Options or Project Properties Borland Turbo BCB10 Borland Turbo C Project Settings When cre
98. le logic continuously monitors the status of the peripheral usually analog hardware present on the baseboard and generates an alert whenever an alert condition is detected It s also possible for application software to generate custom alert messages to tag the data stream with system information The Malibu software provides support for alert configuration and alert packet processing See the software manual for usage Tagging the Data Stream The Alert Log can be used to tag the data stream with system information by using software alerts This helps to provide system level correlation of events by creating alert packets in the data stream created by the host software Alert packets are then created by the X5 module and are in the stream of data packets from the module For example it is often interesting when something happens to the unit under test such as a change in engine speed or completion of test stimulus Calibration Each 5 is calibrated as part of the production testing The calibration results are provided on the production test report with each module The results of the calibration are stored in the on board EEPROM memory These calibration values are used by the logic to correct the analog errors for both the high speed and secondary channels Each input has a four calibration coefficients that are loaded by the software at initialization high speed offset and gain correction factors and secondary offset and gain correcti
99. lled You may type a path or click Change to browse for or create a directory If left unchanged the install will use the default location of C Innovative 3 Typically most users will perform a Full Install by leaving all items the Components to Install box checked If you do not wish to install a particular item simply uncheck it The Installer will alert you and automatically uncheck any item that requires a development environment that is not detected on your system 4 Click the Install button to begin the installation X5 RX User s Manual 17 Windows Installation Note The default Product Filter setting for the installer interface is Current Only as indicated by the combo box located at the top right of the screen If the install that you require does not appear in the Product Selection Box 1 Change the Product Filter to Current plus Legacy Each item of the checklist in the screen shown above has a sub install associated with it and will open a sub install screen if checked For example the first sub install for Quadia Applets Examples Docs and Pismo libraries is shown below The installation will display a progress window similar to the one shown below for each item checked Quadia Documentation Thank you for choosing Quadia Installing Documentation Figure 3 Progress is shown for each section X5 RX User s Manual 18 Windows Installation T
100. med cha C Ewemal 04000 Auto Retrigger Framed mDigital 1 0 DataLoggng p lestCounter Decimation ConfigMask Samples Sawtooth Enable 0 3 Enable 000000 Auto Stop i Analog 1 0 started a Stream Mode started Actual sampling rate 200 MHz Analog 1 0 Stopped Stream Mode Stopped automatically Elasped 5 0 000 stream Made started Figure 3 5 SNAP Example Triggering Controls The trigger source is either external or software External trigger input is the differential pair signal on J5 and J6 front panel connections Both inputs must be driven In external trigger mode the data collection begins on rising edges If you are in framed mode then the number of points collected is set by the Frame Size number you enter In unframed mode the data is collected until the trigger is false One often misunderstood point about framed mode triggering is that it is best if the data packet size is set to the same integer sub multiple packet size so that data will flow as expected If the packet size is equal to the frame size then the data packet will transfer to the system when the frame is complete When this is mismatched some or all of the data 15 stuck waiting for the packet to be completed If multiple triggers are expected then the next trigger may push the data out If you have only one trigger the data will not move to the
101. mp Event if Stopped return Static Buffer Packet Extract the packet from the Incoming Queue Event Sender gt Recv Packet IntegerDG Packet DG Packet PacketBufferHeader PktBufferHdr Packet When the event is signaled the data buffer must be copied from the system bus master pool into an application buffer The preceding code copies the packet into the local Buffer called Packet Since data sent from the hardware can be of arbitrary type integers floats or even a mix depending on the board and the source Buffer objects have no assumed data type and have no functions to access the data in them Instead a second class called a datagram wraps the buffer providing typed or specialized access to the data in the buffer The above code associates 2 datagram classes with the packet IntegerDG provides access to the data in the packet as if it were an array of 32 bit integers The PacketBufferHeader datagram class provides access to the header of the packet and defines access methods to the fields in the header of a Packet Stream buffer Process the data packet int Channel PktBufferHdr PeripheralId Discard packets from sources other than analog devices if Channel Channels return Each Packet Stream Buffer consists of a header and a body of data The header contains a field that specifies the source of the data packet This can be interrogated to provide different processing for packets from
102. mperature range devices Thermal conduction assembly Conformal coating extended temperature range devices Thermal conduction assembly Epoxy bonding for devices Testing Functional Temperature cycling Functional Temperature cycling Wide temperature testing Functional Temperature cycling Wide temperature testing Vibration Shock Functional Temperature cycling Wide temperature testing Vibration Shock Functional Testing per MIL STD 810G for vibration shock temperature humidity Table 14 X5 RX Environmental Limits Testing for each unit is performed to verify compliance with the specified requirements For levels above LO functional testing 15 performed over the specified temperature range and functional testing is verified during vibration tests Shock testing 1s non operation with post shock functional testing Analog Input A summary of the analog performance follows for the X5 RX module tests performed at room temperature with no forced air cooling unless noted Test environment was PCle adapter card in PC running testbed software using FrameWork Logic X5 RX User s Manual 106 X5 RX Module Table 15 X5 RX Analog Performance Summary Test Group Parameter Measured Units Test Conditions Analog Input Impedance 50 Ohms Input Range 3 Vp p Standard on X5 RX calib
103. n FPGA on the X5 modules providing tight coupling for high performance real time IO The FPGA logic implements an interface to each device that connects them to the controls and data communications features on the module Support features such as sample triggering and data analysis are implemented in the logic to provide precise real time control over the data acquisition process The X5 module architecture is really defined by the features in the logic that connect the IO devices to Velocia packet system For data from IO devices such as A Ds the data flows from the IO interface and is then enqueued in the multi queue buffer The packetizer then creates data packets from the data stream that are moved across the data link to the PCIe interface Packets to output devices travel in the opposite direction from the link to the de framer and into the multi queue data buffer The output IO such as a DAC then consumes the data from the queue as required The Alert Log monitors error conditions and important events for management of the data acquisition process The host interacts with the X5 computing core using the packet system for high speed data and over the command channel The packet system is the main data channel to the card and delivers the high performance real time data capability of moving data to and from the module Since it uses an efficient DMA system it 1s very efficient at moving data which leaves the host system unburdened by the data
104. n and Off buttons to activate or deactivate respectively the LED on the baseboard for the specified target When you exit the application the board s LED will remain in the state programmed by this applet X5 RX User s Manual 81 X5 RX Module XI RX Module Introduction The X5 RX is a member of the X5 XMC family that has four channels of 16 bit 200 MSPS A D conversion with wide bandwidth analog inputs The X5 RX has a high performance computing core for signal processing data buffering and system IO 15 built around a Virtex 5 FPGA Supporting peripherals include 512MBytes of DDR2 DRAM 4MBytes of QDR2 SRAM conversion timebase and triggering circuitry 16 bits of digital IO and a PCI Express interface The module format is a single slot XMC and is compatible with XMC 3 host sites Figure 21 X5 RX Module analog cover and heat sink installed Custom application logic development for the X5 RX is supported by the FrameWork Logic system from Innovative using VHDL and or MATLAB Simulink Signal processing data analysis and application specific algorithms may be developed for use in the X5 RX logic and integrated with the hardware using the FrameWork Logic X5 RX User s Manual 82 X5 RX Module Software support for the module includes host integration support including device drivers XMC control and data flow and support applets X5 RX Block Diagram Ext CIk ADCO
105. n one slot in desktop PC or compact PCI systems For ruggedness the modules should be mounted to a host card using the mounting screws and standoffs The host bracket should securely hold the XMC front bracket so that the module is snug in the bracket opening This reduces mechanical strain on the XMC connectors from the front panel cable attachments The card may be secured to the host card with two standoffs and four screws as shown The Digikey number is provided www digikey com for convenience many suppliers have these standard screw and standoff sizes For high vibration applications screws should be mounted with locking compound such as Loctite 222 Table 3 XMC Mounting Hardware Description Quantity Digikey Part Number Metric pan head screw M3X6 3mm x 5mm 5 H742 ND Threaded Standoff 10mm with 3mm thread 3 4391K During the logic and firmware design process some modules require access to JTAG connectors for use with the development tools This may require greater access space than the final installation A variety of engineering tools are available to assist the designer during the development process such as PCIe to adapters A cabled version allows the module to operate outside the chassis An open chassis may also be required to get access to the XMC during the development process so that the cables are easily accessible X5 RX User s Manual 32 About the X5 Modules chapter 1 About t
106. nDriver WXWIN usr wxWidgets 2 8 7 provided that this is the location where you have installed wx Widgets Summary Developing Host and target applications utilizing Innovative DSP products is straightforward when armed with the appropriate development tools and information X5 RX User s Manual 77 Applets Chapter 4 Applets The software release for a baseboard contains programs in addition to the example projects These are collectively called applets They provide a variety of services ranging from post analysis of acquired data to loading programs and logic to a full replacement host user interface The applets provided with this release are described in this chapter Shortcuts to these utilities are installed in Windows by the installation To invoke any of these utilities go to the Start Menu Programs Baseboard Name and double click the shortcut for the program you are interested in running Common Applets Registration Utility NewUser exe Some of the Host applets provided in the Developers Package are keyed to allow Innovative to obtain end user contact information These utilities allow unrestricted use during a 20 day trial period after which you are required to register your package with Innovative After the trial period operation will be disallowed until the unlock code provided as part of the registration is entered into the applet After using the NewUser exe applet to provide Innovative Inte
107. nal 0 4000 Auto ReTrigger Framed Digital Data Logging Test Counter y Decimation Config Mask Samples Enable 100000 Auto Stop Enable Event Log Be sure to read the help file for info on this program located in the root of the this example folder Logic Version 11 Variant 0 Revision 3 Type 0 Express Lanes 8 Stream Connected software Data can also be collected into frames In this mode a trigger will collect multiple samples before checking the trigger again By default trigger source is set to software triggering though external trigger can be provided once selected The Digital I O field configures the onboard digital I O The Data Logging option determines if data streaming stops after collecting points a Snapshot of data or streams forever until manually stopped The module supports a test mode for module debugging and system test The Test Counter Enable is used to turn on test mode and substitutes a ramp signal with channel number in the upper byte of the data The Decimation section sets up the decimation logic to discard data reducing the incoming data rate X5 RX User s Manual 66 Writing Custom Applications Stream Tab The two buttons in the button bar start and stop data streaming Press the running man button to start streaming data Press the stop button to stop streaming unless the stream has stopped itself When streaming the status bar data 1s collected a
108. nd displayed This includes a count of the data blocks received the data rate the measured temperature of the board logic and the digital I O value The Wave Example SnapExample Configure Setup Start Stream Stop Stream Start Scripts Before After Data Files Vi Log v Plot Overwrite BDD file Blocks Rate MB s Temp C Dig Event Log Be sure to read the help file for info on this program located in the root ofthe this example folder Logic Version 11 Variant 0 Revision 3 Type 0 PCI Express Lanes 8 Stream Connected The Wave example in the software distribution demonstrates output streaming It will only be included if the board supports streaming out to a DAC or similar device or devices In many ways the Wave example is similar to the Snap example Differences are highlighted in this section Stream Initialization Setup of the stream is much like the Snap example We have similar error checking code and rate guarding X5 RX User s Manual 67 Writing Custom Applications void ApplicationIo StartStreaming if FStreamConnected UI gt Log Stream not connected Open the boards return Make sure packets fit nicely in BM region if FBmSizeWords 8 lt unsigned int Settings StreamPacketSize UI gt Log Error Packet size is larger than recommended size return Set up Parameters for Data Str
109. ng Input Overrun 100 0 MHz 200 0 MHz Input Trigger Trigger Souce Frame Mode Software Size Untramed C Estemal 0 4000 Auto Retrigger C Framed mDigital 1 0 r Data Loggin Counter Decimation Config Mask Samples Sawtooth Enable 0 3 1000000 v Auto Stop Enable Stream Mode Stopped automatically Elasped 5 0 000 Stream started Figure 3 SNAP Example Sample Clock Controls Controlling the PLL How To Set the Sample Rate Generator to a Specific Frequency To generate the settings for a desired sample rate the PLL and VCXO are configured generate the closest possible frequency while meeting several restrictions PLL Parameter Constraint On card PLL reference Programmable 10 to 280 MHz 0 01 Hz resolution External Reference Input Range 10 to 250 MHz VCXO Center Frequency Ranges Programmable 0 001 Hz resolution 10 to 280 MHz X5 RX User s Manual X5 RX Module Phase Comparator Set point 100 kHz Table 1 Sample Rate Generation Parameters Step Calculation 1 Find integer multiple even numbers only of the desired sample rate that is within the tuning range of the VCXO where D 1 2 4 6 8 10 12 14 16 18 20 24 28 32 64 80 Fvco D Fs 2 Calculate the VCXO internal frequency to check operating mode HS DIV N
110. nicely in BM region if FBusmasterSize 16 lt unsigned int Settings PacketSize Log Error Packet size is larger than recommended size return Set up Parameters for Data Streaming First have UI get settings into our settings store UI 2GetSettings Before we start streaming all necessary parameters must be checked and loaded into option object UI gt GetSettings loads the settings information from the UI controls into the Settings structure in the Applicationlo class if SampleRate Module Input Info MaxRate UI gt Log Sample rate too high StopStreaming UI gt AfterStreamAutoStop return We insure that the sample rate specified by the GUI is within the capabilities of the module if Settings Framed if Settings FrameCount lt Settings PacketSize UI gt Log Error Frame count must exceed packet size UI AfterStreamAutoStop return The module supports both framed and continuous triggering In framed mode each trigger event whether external or software initiated results in the acquisition of a fixed number of samples In continuous mode data flow continues whenever the trigger is active and pauses while the trigger is inactive The code above issues a warning if the trigger mode is framed and ill formed FBlockCount 0 FBlockRate 0 FTriggered 1 The class variables above are used to maintain counts of blocks received reception rate an
111. nnector Part Number Samtec TMM 107 01 L D RA or equivalent Mating Connector AMP 111623 3 or equivalent Board edge c Board j Pin 139 Pin 147 phia JP1 1 Figure 9 5 1 Orientation board face view Figure 10 X5 RX JP1 Orientation board top edge view X5 RX User s Manual 121 X5 RX Module Pin Signal Direction 1 3 5 7 9 11 13 Digital Ground Power 2 1 8V Power 4 TMS I 6 TCK I 8 TDO 10 TDI I 12 14 No Connect Table 21 X5 RX JP1 Xilinx JTAG Connector Pinout FLASH Boot Image Select JP3 is used to select the logic image used to boot the module JP3 Strapping Boot Image None Application Logic Image 1 2 Backup Image Golden Image Table 22 X5 RX JP3 Boot Image Select Mechanicals The following diagrams show the X5 RX connectors and physical locations The XMC conforms to IEEE 1386 form factor 75mm x 150mm The spacing to the host card is 10 mm and consumes a single slot in desktop and Compact PCI PXI chassis An EMI shield over the analog section is normally installed Detailed drawings for mechanical design work are available through technical support X5 RX User s Manual 122 X5 RX Module 2 5 TH 3 PL _Jp3 Boot _ Image Select c Pe gt E 5 RX 71464 Rev ASSY 80222 um
112. ns are possible with Innovative Integration hardware 12 Why do I need to use Malibu with my 12 Finding detailed information on eerte nnns 12 hok eir pi olo os a Rasxs eei aeaieie torva Innovative Integration Technical 5 13 Innovative Integration Web SIEG aac estos vases ne vae Typographic C omvertlOns eei eus exta oso Ee epo C e LESS ERN e etae eere eol poeti sac Chapter 2 Windows Installation Host Hardware 026 oi De ei D OD Nin rigdibiriciri eet PE LD Starting the Installation o 9 LO Installer m 7 Tools ses iesse eoeta soo enoro o eose sses Bus Master Memory Reservation 1 19 hrsg eee DA PNE E FO WOT UD eM Rn TA Installation on a Deployed Systemisisic ccesssscessssccecssesevsccsestsesunssesnscsoessesesasevensiedcacaswonaddsdsseonucdsadesovensevedave 21 HM H Chapter 1 Installation bii eese c rcc trc ORA Package File NaTIeS
113. nsitive the system will be to clock jitter e Band limit input signals if possible This avoids noise contributions and aliasing caused by out of band energy in the input signal Scale your input signals to take advantage of the full scale input ad output ranges of the converters This will maximize signal to noise in most cases Custom input and output ranges can be ordered if necessary Use high coax cables at all times and terminate all signals to 50 ohms Cables should be RG 179 or better Reference input signals to the module ground Be sure not to introduce ground loops Provide sufficient signal strength to drive the input The X5 RX terminates its inputs to 50 ohms so signals sources must be able to drive the DC termination effectively If you decide to test the X5 RX to verify its performance be aware that most signal sources are not good enough without additional filtering and careful use Most single ended lab instruments are limited by their distortion especially at higher frequencies to about 70 dB It is usually necessary to bandpass filter lab signal sources to improve the quality of the test signal before the X5 RX input The filter reduces out of band noise and harmonic distortion from the signal source Figure 5 Typical Performance Evaluation Setup X5 RX User s Manual 104 X5 RX Module Performance Data Power Consumption The X5 RX requires the following power for typical operation with
114. on factors X5 RX User s Manual 102 X5 RX Module The calibration technique determines the high speed A D errors by first measuring with ground connected then a 1 4V 10 MHz source The measurements are the average of 64K samples at each test voltage From these three points across the input range the gain and offset errors are calculated The secondary channel is calibrated separately from the high speed channel The input is connected first to ground then to 1 4V DC and 1 4V From these measurements the gain and offset errors are calculated factory calibrations limit gain correction to 5 and offset to 2 mV test voltages are measured as part of the procedure with NIST traceable equipment Production calibration 1s performed at room temperature 24C with the module operating temperature at about 65C Under normal circumstances calibration is accurate for one year For recalibration the module can be sent to Innovative or re calibrated using a similar test procedure Updating the Calibration Coefficients A software applet for writing the calibration coefficients to the EEPROM 15 provided EEPROM exe New coefficients are simply typed into the offset and gain field for each channel Calibration coefficients for gain should not be outside the range of 0 95 to 1 05 and offset should not be outside the range of 1000 counts for the A Ds If the calculated coefficients are larger than this they are eit
115. ools Registration Registration Information User Name First Address Telephone Country Code Area Code Number Extension Fax Area Code Number Company Name Address City State Country Postal Code Product Board X Register Now Register Later Figure 4 ToolSet registration form Bus Master Memory Reservation Applet Reserve Memory for Dsp Combined DSP Board Usage Rsv Region Size Configuration Total physical memory MB 2047 Non paged pool size 256 Status Ok Update Help Exit Ready X5 RX User s Manual At the end of the installation process you will be prompted to register If you decide that you would like to register at a later time click Register Later When you are ready to register click Start All Programs Innovative Board Applets Open the New User folder and launch NewUser exe to start the registration application The registration form to the left will be displayed Before beginning DSP and Host software development you must register your installation with Innovative Integration Technical support will not be provided until registration is successfully completed Additionally some development applets will not operate until unlocked with a passcode provided during the registration process It is recommend that you completely fill out this form and return it
116. ovide eight transmit and receive pairs implemented using Virtex 5 Rocket I O links A clock reference is provided on board for use by the Rocket I O links Pinouts for the P16 connector showing the transmit and receive pair locations are given in the Connectors section The following table gives the Rocket I O pin allocations on the Virtex 5 which connect to each of the P16 signals P16 Signal Virtex 5 FG1136 Pin Number Virtex 5 MGT Signal Identifier TXPO B6 MGT 124 TXNI TXNO B5 124 7 124 RXNI RXNO A6 MGT 124 RXPI 9 124 TXNO TXNI 10 124 RXPI 8 124 RXNO RXNI A9 MGT 124 RXPO X5 RX User s Manual 42 About the X5 Modules P16 Signal Virtex 5 FG1136 Pin Number Virtex 5 MGT Signal Identifier TXP2 D2 MGT 120 TXNI TXN2 E2 120 2 120 RXNI RXN2 DI MGT 124 RXPI TXP3 B3 MGT 120 TXNO TXN3 B4 MGT 120 TXPO RXP3 A2 MGT 120 RXNO RXN3 A3 MGT 124 RXPO TXP4 2 116 TXNI TXN4 L2 116 TXPI RXP4 116 RXNI RXN4 116 5 G2 MGT 116 TXNO 5 2 116 5 116 RXNO RXNS5 Gl 116 6 AN9 MGT 126 TXNI TXN6 ANIO 126 RXP6 8 126 RXNI RXN6
117. pable The enabled state of the check boxes is copied into the Settings AlertEnable array This code fragment applies the state of each bit in that array to the Alerts sub object within the module During streaming an alert message will be sent to the Host tagged with a special alert packet ID PID to signify the alert condition Start Streaming Stream Start UI gt Log Stream Mode started UI gt Status Stream Mode started The Stream Start command applies all of the above configuration settings to the module then enables PCI data flow The software timer is then started as well FTicks 0 Timer Enabled true X5 RX User s Manual 59 Writing Custom Applications Handle Data Available Once streaming is enabled and the module is triggered data flow will commence Samples will be accumulated into the onboard FIFO then they are bus mastered to the Host PC into page locked driver allocated memory following a two word header data packets Upon receipt of a data packet Malibu signals the Stream OnDataAvailable event By hooking this event your application can perform processing on each acquired packet Note however that this event is signaled from within a background thread So you must not perform non reentrant OS system calls such as GUI updates from within your handler unless you marshal said processing into the foreground thread context void ApplicationIo HandleDataAvailable PacketStreamDataEvent a
118. pecifications This signal can be used as either a sample clock or as a PLL reference Sample Rate Generation The PLL is used to generate sample clocks on the X5 RX using either an on card programmable reference clock or an external reference input Parameter Specification PLL Clock Range 1 to 200 MHz PLL Output Clock Resolution 0 01 Hz PLL Output Jitter 200 fs RMS Table 19 PLL Specifications Setting the Sample Rate in the SNAP Example The example software for the X5 RX illustrates the use of the sample clock controls and features The clock is selected internal PLL or external input A frequency should be specified even when an external clock is used because the software uses this to estimate the data rate and size buffers appropriately The external clock must be input on front panel connector J6 X5 RX User s Manual 88 X5 RX Module The PLL reference is also selected to be internal 10 to 280 MHz reference or external For external reference the frequency must be exactly specified so that the PLL is programmed properly External reference connector is J6 on the front panel x 10 xl Reference 1 Clock mmunications Source Source Alerts C Ext Int C Ew Int Time Stamp L Input Overrange Software Frequency Frequency Temp Warni
119. pose pins that support Innovative adapter card functions These are reserved pins on the VITA42 3 specification X5 RX User s Manual 117 X5 RX Module Signal Description PETOpx PETOnx PCI Express Tx PEROpx PEROnx PCI Express Rx PEX REFCLK PCI Express reference clock 100 MHz MRSTI Master Reset Input active low MRSTO Master Reset Output active low GAO Geographic Address 0 GA1 Geographic Address 1 GA2 Geographic Address 2 MBIST Built in Self Test active low MPRESENT Present active low MSDA PCI Express Serial ROM data MSCL PCI Express Serial ROM clock MVMRO PCI Express Serial ROM write enable WAKE Wake indicator to upstream device active low ROOT Root device active low LED Host LED control output active low May be used with eInstruments FAN Host fan control May be used with eInstruments Table 18 P15 Signal Descriptions X5 RX User s Manual 118 X5 RX Module XMC P16 Connector P16 15 the secondary connector to the host and is used for digital IO data link and triggering functions Connector Types XMC pin header 0 05 in pin spacing vertical mount 114 arranged as 6 rows of 19 pins each Samtec ASP 105885 01 Mating Connector Samtec ASP 105884 01 Figure 8 16 Connector Orient
120. providing optimal performance and maximum portability Innovative Integration s products employ the latest digital signal processor technology thereby providing you the competitive edge so critical in today s global markets Using our powerful data acquisition and DSP products allows you to incorporate leading edge technology into your system without the risk normally associated with advanced product development Your efforts are channeled into the area you know best your application Vocabulary X5 RX User s Manual 10 Introduction What is X5 RX The X5 RX is a PCI Express XMC IO module featuring four TI ADS5485 providing 200 MSPS 16 bit A D data A Xilinx Virtex5 SX95T with 512 MByte DDR2 DRAM and 4MB QDR II memory provide a very high performance DSP core for demanding applications such as emerging wireless standards The close integration of the analog IO memory and host interface with the FPGA enables real time signal processing at extremely high rates exceeding 300 GMACS per second The X5 XMC modules couple Innovative s powerful Velocia architecture with a high performance 8 lane PCI Express interface that provides over 1 GB s sustained transfer rates to the host Private links to host cards with gt 1 6 GB s capacity using J16 are provided for system integration The X5 family can be fully customized using VHDL and MATLAB using the FrameWork Logic toolset The MATLAB BSP supports real time hardware in the loop development using
121. ration results may limit input range to 0 95 of full scale nominal Accuracy Offset lt 10 mV Factory calibration average of 64K samples Gain 0 02 Factory calibration average of 64K samples Analog Input Ground Noise 24 mVp p Input Grounded Fs 200 MSPS 128K samples Ground Noise 117 dB Input Grounded Fs 200 MSPS 64K sample FFT non Floor averaged Analog Input Crosstalk 95 dB Worst case Fin 70 1 MHz 2V p p input Analog Bandwidth 450 MHz 3 dB Response Amplitude 1 1 to 200 MHz Variation 2 Amplitude vs Frequency 0 2 0 20 600 800 1000 1200 4 6 a Amplitude dB 10 12 14 16 2 Figure 6 Frequency Response for 1 MHz to 1 2GHz span X5 RX User s Manual 107 X5 RX Module 2 0 5 0 4 4 40 0 5 2 2 Figure 7 Frequency Response for 5 MHz to 400 MHz span Fin MHz SNR dB SINAD dB SFDR dB 5 77 8 73 3 85 6 70 72 6 68 7 84 9 99 69 3 67 4 84 7 165 66 7 64 7 81 1 Table 16 A D Signal Quality vs Input Frequency X5 RX User s Manual Amplitude vs Frequency Amplitude dB 400 n THD dB 81 1 77 6 81 7 78 1 Noise dB 122 5 117 5 113 5 107 108 X5 RX Module 130 120 110 100 90 80 70 60 50 0 20 dB X5 RX Signal Quality SNR dB SINAD dB SFDR dB THD dB Noise dB 40 60 80 100 120 140 160 180 Fin MHz Figure 8 A D Signal Quality vs Input Frequency ax BinView c projects x5 rx
122. rd 5 404 Using the combo box select the appropriate baseboard to install support for In this case we are installing X3 A4D4 board If support for multiple cards 15 needed the program must be run to completion once for each type of board This is required because parts of the installation such as baseboard device drivers may be different for different board types After selecting the board press to begin installation The window changes to display the progress of the install X5 RX User s Manual 21 Windows Installation 0 Thank you for choosing X3 A4D4 Installing Malibu Redistributable Libraries After completing the installation reboot the system to allow Windows to recognize the new drivers Then proceed with the Hardware Installation as in the development system installation above X5 RX User s Manual 22 Installation on Linux chapter 1 Installation on Linux This chapter contains instruction on the installation of the baseboard software for Linux operating systems Software installation on Linux is performed by loading a number of packages A Package is a special kind of archive file that contains not only the files that are to be installed but also installation scripts and dependency information to allow a smooth fit into the system This information allows the package to be removed or patched Innovative uses RPM packages in its installs Pack
123. reference is used The reference clock multiplexer is configured to select the external clock input as the reference to the CDCE72010 device To FPGA J6 External e amp ToA DOCLK Clock or Ref Input M To A D 1 CLK ToA D2CLK gt ToA D3 CLK Y6 2 Figure 1 Clock Path Using External Reference Input To use the external clock input as a reference the CDCE72010 reference must be set to secondary input This can be done using either a Malibu library function in software from a script in the example programs or set by the FPGA in custom logic Using An External Clock for Sample Clock The external clock input on J4 front panel can be used as a sample clock In this mode the sample clock is buffered and distributed with an option for clock division to the DAC devices and FPGA X5 RX User s Manual 92 X5 RX Module 9 To FPGA J6 External ToA DOCLK Clock or Ref Input A D 1 CLK ToA D2CLK cM ToA D3CLK Y6 2 Figure 1 Clock Path Using External Clock Input Configure the CDCDE72010 device to use the auxiliary clock input then program the dividers for each output clock These controls are mapped to the CDCDE72010 SPI port mapped to the PCI Express bus in the Framework Logic Custom logic implementations can control the PLL directly from the FPGA as well The Malibu libraries provide software
124. rts System alerts include monitoring functions such as temperature time stamp rollover and PLL lost These alerts just monitor that the system is working properly The temperature warning should be used increase temperature monitor and to prepare to shut down if necessary because thermal overload may be coming Better to shut down than crash in most cases The temperature failure alert tells the system that the module actually shut itself down This usually requires that the module be restarted when conditions permit The data acquisition alerts including over ranges overflows and triggering tell the system that important events occurred in the data acquisition process Overflow is particularly bad data was lost and the system should try to alleviate the problem by unclogging the data pipe or just start over If you get an overrange alert then the data may just be bad for a while but acquisition can continue Modules with programmable input ranges can use this to trigger software range changes Software alerts are used to tag the data Any message can be made into an alert packet so that the data stream logged includes system information that 15 time correlated to the data Table 11 Alert Types Alert Purpose Timestamp rollover The 32 bit timestamp counter rolled over This can be used to extend the timestamp counter in software Software Alert The host software can create alerts to tag the data stream AD
125. s a high impedance input for digitizing the DC and low frequency band X5 RX User s Manual 84 X5 RX Module AGND AGND Figure 23 X5 RX A D Channel Front End CAM The other 3 analog inputs are identical H R332 51 1 PAIRS MAIUH TRACE LENGTH FOR EAC 0 030 ROU 5 MINIMIZE Vi VIAS IF REQ QU IRED 0 AINP Input bandwidth measurement is shown in the data section of this chapter Input Range and Conversion Codes AGND e t PDWNF 35 0 1 DC DITHER DO PDWNS 10K 33 AGND RA1 0 22 0 21 ufe 12 INM VCM REF DITHER PDWNS PDWNF LVDSB CLKP CLKM Each high speed A D input has 1 5 to 1 5V single ended input with 50 ohm input impedance Other input ranges may be custom ordered Data output codes from the high speed A D channels are 2 s complement 16 bits The following table gives the transfer function Input voltage V High Speed A D Conversion Code hex 1 5 Ox7FFF 0 75 Ox3FFF 0 0x0000 0 75 0 000 1 5 0 8000 X5 RX User s Manual 85 X5 RX Module Table 17 High Speed A D Conversion Coding DC and Low Frequency Band Digitizing The X5 RX has a secondary A D channel for each input that digitizes the DC and low frequencies information on the signa
126. s and IO standards see the hardware chapter Module Number Bit IO Notes X5 400M 33 Mixed 2 5V and 3 3V IO X5 210M 16 3 3V IO X5 GSPS 16 3 3V IO X5 TX 16 3 3V IO X5 G12 16 3 3V IO X5 RX 16 3 3V IO Table 9 X5 Modules Available Bit I O Software Support The Framework Logic configures these bit I O connections as a simple port that has programmable bit direction and data by the host The port is configured and accessed directly from the PCI Express host The digital I O hardware is controlled by the IUsesDioPort class Its properties Table 10 IUsesDioPort Class Operations DioPortConfig Configures banks of bits for input or output DioPortData Broadside Read Write to low order 32 bits of DIO Typical use of the digital IO port involves first configuring the port using the Config operator This sets the byte direction and the clock mode The port is then ready for read write configurations to each port For instance Open the module Innovative X5 400M Module Module Target 0 Module Open X5 RX User s Manual 39 About the X5 Modules All bits input Module Config 0x0 Read the state of the port volatile short x Module DioPortData All bits output Module Config 0x3 Toggle the state of all output bits while 1 Module DioPortData Module DioPortData Hardware Implementation Digital I O port activity is controlled by the digita
127. se the driver select the number of the desired target using the Target 4 combo box then click open to open communications with the specified target module The order of the targets is determined by the X5 RX User s Manual 51 Writing Custom Applications location in the PCI bus so it will remain unchanged from run to run unless the board is moved to a different slot or another target is installed Setup Tab 5 400M Capture Application This tab has a set of controls that hold EER MA Configure Setup Stream Eeprom Debug the parameters for transmission These settings are delivered to the target and Source Communications i Time St Input 0 configure the target accordingly This Externa PacketSize IE Input Tigger tab has several sections Uema IL 10 Input Overrange Channels Trigger Cho Source Frame Clock section offers configurations and 4 chi count oftware routing of the clock The clock for the External Auto Trigger Framed FPGA can come from an external clock or from an internal crystal The selection Coin be made at upper right corner ofthis Auto Stop section The clock rate of the clock source is specified in the Output field in MHz The Communications section controls th
128. ssvccciccscscsvonsscestscdcsassoncnssctesusscenasasesasicdedacdoeboansdacdeesvenenacasve 33 5 33 XS Computing COTE Pe 35 XS PCI Express RES ER IAES 36 Data Buffering Memory 056 37 Computational SRAM s e t Ad cielo a veta Be p AU leas ue 37 Buffer DRM st d 37 EEPROM itae het gen 38 EEPROM pe beds pe olo 38 AE 39 Available A FLORE 39 Software SUDDOELU aa dcc e tin tto core 39 Digital IO Electrical Characteristics eo eceeee eene eser erret ao tanen en rhone a Ee spen ur Seen re 41 LV LTD PIS ue eh i 41 EXCMOS 2 5 PHIS m aste aste s hee 41 Notes on Digital TO US 42 PIG SER DES e M 42 Thermal Protection and MOmMitoring
129. stalls Malibu Source Libraries and Examples Other Software Our examples use the DialogBlocks designer software and wxWidgets GUI library package for user interface code If you wish to rebuild the example programs you will have to install this software as well wxWidgets wxWidgets http www wxwidgets org DialogBlocks Anthemion http www anthemion co uk org dialogblocks Baseboard Package Installation Procedure Each baseboard installation for Linux consists of one or more package files containing self extracting packages of compressed files as listed in the table below Note that package version codes may vary from those listed in the table Each of these packages automatically extract files into the usr Innovative folder herein referred to as the Innovative root folder in the text that follows For example the X5 400 RPM extracts into usr Innovative X5 400 ver symbolic link named x5 400 is then created pointing to the version directory to allow a single name to apply to any version that 1s in use X5 RX User s Manual 24 Board Packages Board Packages X5 400M Malibu LinuxPeriphLib ver rel 1586 rpm Board files and examples X5 210M X5 210M LinuxPeriphL ib ver rel 1586 rpm Board files and examples X3 10M X3 10M LinuxPeriphLib ver rel 1586 rpm Board files and examples X3 25M X3 25M LinuxPeriphLib ver rel 1586 rpm Board files and examples X
130. t HeaderTagValuePostPacketizer 0x00000000 const int HeaderTagValueOriginal HeaderTagValuePostPacketizer void ApplicationIo SendOneBlock PacketStream PS static Buffer Packet ShortDG Packet DG Packet if FBlockCount Packet DG Resize Settings StreamPacketSize PacketBufferHeader PktBufferHdr Packet PktBufferHdr PacketSize Settings StreamPacketSize PktBufferHdr Peripheralld Module Output PacketId PktBufferHdr 1 HeaderTagValueOriginal Builds a one or 2 channel buffer BuildWave Packet Settings WaveType For speed the packet is created on the first call only After that the same data wave is sent to all channels Note that it is allowed to send more than one output packet per notification If no packets are sent however it is possible that further notifications may stop until the application starts sending data again This decoupling of notification from sending allows different models of data generation to exist Malibu An application may send packets asynchronously and not handle notifications at all Calculate transfer rate in kB s double Period Time Differential if Period FBlockRate Packet DG SizeInBytes Period 1 0e6 No matter what channels are enabled we have one packet type to send here PS gt Send Packet FBlockCount X5 RX User s Manual 70 Writing Custom Applications The Wave Example for Linux With the release of
131. ter cards provide access to P16 IO for system integration Contact technical support if you need any assistance in checking compatibility with the X6 P16 interface System Requirements X5 RX User s Manual 30 Hardware Installation The PCI Express slot must be PCI Express 1 0a compatible and be able to map the following resources Table 2 Required PCIe Resource Allocations Required PCIe Resources BARO IMB Memory BARI 64K B Memory 1 Interrupt When you first plug in the module it will then be found and the driver should be installed for the module The standard driver resides in the Innovative drivers directory after software installation The module may be used an any PCI Express slot supporting 1 or more lanes Innovative offers a line of adapters for use with the X6 series which allow the module to be used in PCI and cPCI environments These adapters may limit the number of lanes available to the X6 for host communication depending on their design Power Considerations Each XMC should be reviewed for its specific power cooling and any special mechanical considerations For each module the power consumption and required power supplies are shown in the specific discussion for that module For desktop applications you MUST provide forced air cooling with 5 10 CFM capability The air must blow directly on the Virtex 6 device The X6 XMCs are designed to operate over the typic
132. tes a key on your keyboard For example Press ESC to exit a menu Text in this style represents menu commands For example Click View Tools Customize 14 Windows Installation 2 Windows Installation This chapter describes the software and hardware installation procedure for the Windows platform WindowsXP Vista and Windows 7 Do NOT install the hardware card into your system at this time This will follow the software installation Host Hardware Requirements The software development tools require an or 100 compatible Pentium IV class or higher machine for proper operation An Intel brand processor CPU is strongly recommended since AMD and other clone processors not guaranteed to be compatible with the Intel MMX and SIMD instruction set extensions which the Armada and Malibu Host libraries utilize extensively to improve processing performance within a number of its components The host system must have at least 1 GB of memory 2 GB recommended 1 GB available hard disk space and a DVD ROM drive Most versions of Windows released after Win2000 including XP Vista or Windows 7 referred to herein simply as Windows or later 1s required to run the developer s package software and are the target operating systems for which host software development is supported Software Installation The development package installation program will guide you through the installation process
133. to Innovative Integration via email or fax Upon receipt Innovative Integration will provide access codes to enable technical support and unrestricted access to applets At the conclusion of the installation process ReserveMem exe will run except for SBC products This will allow you to set the memory size needed for the busmastering to occur properly This applet may be run from the start menu later if you need to change the parameters For optimum performance reserve at least 64 MB of memory for each Innovative board to be used simultaneously within the PC plus 32 MB for other system use For example if using two X5 400M modules reserve 2 64 32 MB 160 MB To reserve this memory the registry must be updated using the ReserveMem applet Simply type the desired size into the Rsv Region Size MB field click Update and the applet will update the registry for you If at any time you change the number of boards in your system then you must invoke this applet found in Start All Programs Innovative target board Applets Reserve Memory After updating the system exit the applet by clicking the exit button to resume the installation process 19 Windows Installation Figure 5 BusMaster configuration At the end of the install process the following screen will appear Installation The installation is complete Shut down your computer and install your board s then reboot your computer The drivers should load a
134. to correlate system events to the data This provides a precision timed log of all of the important events that occurred during the acquisition and playback for interpretation and correlation to other system level events Alerts for critical system events such as triggering data overruns analog overrange and thermal warnings provide the host system with information to manage the module The Alert Log creates an alert packet whenever an enabled alert is active The packet includes information on the alert when it occurred in system time and other status information The system time is kept in the logic using a 32 bit counter running at the sample clock rate Each alert packet 15 transmitted in the packet stream to the host marked with a Peripheral Device Number corresponding to the Alert Log The Alter Log allows X5 modules to provide the host system with time critical information about the data acquisition to allow better system performance System events such as over ranges can be acted on in real time to improve the data acquisition X5 RX User s Manual 100 X5 RX Module quality Monitoring functions can be created in custom logic that triggers only when the digitized data shows that something interesting happened Alerts make this type of application easier for the host to implement since they don t require host activity until the event occurs Types of Alerts Alerts can be broadly categorized into system IO and software ale
135. to the QDR SRAM by providing support for posted writes read address queue and read data queue MATLAB developers frequently use the SRAM as the real time data buffer during development Since the MATLAB Simulink tools operate over the FPGA JTAG during development at a low rate it is necessary to use the SRAM for real time high speed data buffering The MATLAB Simulink library for each X5 module demonstrates the use of the SRAM as a data capture buffer The SRAM captures real time high speed data that can then be read out into MATLAB for analysis or display as a snapshot This allows high speed real time to be captured and brought into MATLAB Simulink over the slow 10Mb sec JTAG link See the X5 FrameWork Logic User Guide for more details and examples Data Buffer DRAM The second set of memory provides a 512MByte DDR2 memory pool local to the FPGA The Framework Logic implements a data buffer with one or more queues for the A D and D A streams as appropriate for the particular X5 module In the Framework logic the SRAM use is demonstrated as a multiple queue FIFO memory that divides the 2 MB memory buffer into separate queues virtual FIFOs for input and output The logic component referred to as Multi Queue DRAM controls the DRAM to create the FIFO queue functionality Custom logic applications can use the Multi Queue DRAM buffer component to add additional queues for new devices The X5 TX has special support for pattern generation using the
136. ts and DialogBlocks as an inexpensive easy to use library and environment Again since the Applicationlo object holds all the program logic for an application porting to a new environment is relatively straightforward This application has five tabs Each tab has its own significance and usage though few are interrelated these tabs share common area which displays messages and feedback throughout the operation of the program X5 RX User s Manual 64 Writing Custom Applications Configure Tab As soon as the application is launched the Configure tab 15 displayed In this tab a combo box is available to allow the selection of the device from those present in the system All X5 family devices of whatever type share a sequence of target number identifiers The first board found is Target 0 the second Target 1 and so on Click the Open button to open the driver To change targets click the Close button to close the driver select the number of the desired target using the Target 4 combo box then click Open to open communications with the specified target module The order of the targets is determined by the location in the PCI bus so it will remain unchanged from run to run unless the board is moved to a different slot or another target is installed X5 RX User s Manual SnapExample Configure Setup Stream EEProm Debug Driver Busmaster Size MB Target 4 4 0
137. tware functions in Malibu tools provide support for programming this device including calculation of its register settings for use This I2C port is implemented using software controlled protocol This means that the I2C port SDA and SCL connections must be controlled with the software to implement the I2C interface timing and commands The control register is a simple pair of registers to control each signal and read back the pin All device addressing commands and data are read using the I2C software driver through the controls in this register VCXO DC Port 0x80F r w Bit Direction Definition 0 W SDA serial data bit 1 W SCK bit for serial clock 2 R Readback for I2C data pin 3 R Readback for I2C clock pin 6 4 Unused R W VCO output enable 0 disabled default X5 RX User s Manual 94 X5 RX Module 31 8 Unused Table 8 VCXO control and I2C register 0x801 r w The I2C SDA data output is set using bit 0 and the pin is readback on bit 2 The I2C SCL clock is set using bit 1 and the pin readback is on bit 3 These signals must emulate the I2C pin functions for the protocol Triggering The X5 RX has a trigger control component in the FPGA that controls the data acquisition process The sample clock specifies the instant in time when data is sampled whereas triggering specifies when data 15 kept This allows the application to collect data
138. ty of Edinburgh Initially started as a project for creating applications portable across Unix and Windows it has grown to support the Mac platform WinCE and many other toolkits X5 RX User s Manual 11 Introduction and platforms The number of developers contributing to the project is now in the dozens and the toolkit has a strong userbase that includes everyone from open source developers to corporations such as AOL So what is special about wxWidgets compared with other cross platform GUI toolkits wxWidgets gives you a single easy to use API for writing GUI applications on multiple platforms that still utilize the native platform s controls and utilities Link with the appropriate library for your platform Windows Unix Mac others coming shortly and compiler almost any popular C compiler and your application will adopt the look and feel appropriate to that platform On top of great GUI functionality wxWidgets gives you online help network programming streams clipboard and drag and drop multithreading image loading and saving in a variety of popular formats database support HTML viewing and printing and much more What is Microsoft MSVC MSVC is a general purpose code authoring environment suitable for development of Windows applications of any type Armada extends the MSVC IDE through the addition of dynamically created MSVC compatible classes specifically tailored to perform real time data streaming functions What
139. unctionality The applet provided by Innovative VsProm exe programs the FLASH using a bit or exo image file generated by the Xilinx toolset X5 RX User s Manual 48 About the X5 Modules 5 400 Logic Loader File Help Target Board Rev Sub Sec Update Logic C Mnnovative T oro Applets sProm Current Logictoro_flashB_2017 exo zu Flash Prom Read Verify Figure 20 XMC EEProm Programmer The EEPROM application is straightforward to use a Target board is selected then a BIT file is selected for reprogramming The Target number tells the software which XMC module to program If you have multiple XMC modules in the system each has a unique Target number assigned by the software If you don t know which card is which target you can use the Finder program to blink the LED on each Target Once you have selected the BIT file press the load button to begin programming The progress bar shows that the programming is underway and when it is completed Programming a few minutes due to the size of the configuration bitstreams used by the Virtex 5 device DO NOT TURN OFF THE HOST COMPUTER OR RESTART IT UNTIL PROGRAMMING IS SUCCESSFULLY COMPLETED Once the EEPROM is reprogrammed the X5 module must be power cycled for reconfiguration to take place and the new bitstream loaded into the Virtex 5 device Rescuing the Card When the Logic Image is Bad If an invalid image 15 programmed into the EEPROM or
140. utomatically and your board will become available Please refer to your Hardware Software Manual for instructions on hardware installation prior to powering the machine back on to make certain everything is plugged in correctly Thank you from Innovative Integration 1 805 578 4260 www innovative dsp com Shutdown Now Shutdown Later Figure 6 Installation complete Click the Shutdown Now button to shut down your computer Once the shutdown process is complete unplug the system power cord from the power outlet and proceed to the next section Hardware Installation Hardware Installation Now that the software components of the Development Package have been installed the next step is to configure and install your hardware Detailed instructions on board installation are given in the Hardware Installation chapter following this chapter IMPORTANT Many of our high speed cards especially the PMC and XMC Families require forced air from a fan on the board for cooling Operating the board without proper airflow may lead to improper functioning poor results and even permanent physical damage to the board These boards also have temperature monitoring features to check the operating temperature The board may also be designed to intentionally fail on over temperature to avoid permanent damage See the specific hardware information for airflow requirements X5 RX User s Manual 20 Windows Installation After Pow
141. ve passed their limit if Settings AutoStop amp amp IsDataLoggingCompleted amp amp Stopped Stop counter and display it double elapsed Clock Stop StopStreaming UI gt AfterStreamAutoStop UI gt Log Stream Mode Stopped automatically UI Log std string Elasped S FloatToString elapsed Auto analyze and retrigger in framed mode if Settings Framed return Packets are processed until a specified amount of data is logged or the GUI Stop button is pressed if Settings ExternalTrigger 0 amp amp Settings AutoTrigger int64 samples FBlockCount Settings PacketSize int triggers static cast int samples Settings FrameCount if triggers FTriggered SoftwareTrigger In the event that were operating in framed trigger mode the example code re asserts a software trigger each time a frames worth of data packets have been received If we re in continuous mode no action need be performed to sustain data flow X5 RX User s Manual 61 Writing Custom Applications EEProm Access Each PMC module contains an IDROM region that can be used to read or write information associated with the module In the next line of code we make a call to Malibu method IdRom which returns an object that acts as interface to that region We further can query the ROM for its contents Additional methods can be used to get more specific information private System Void
142. when using the FrameWork Logic This typical number assumes a 225 MHz system clock rate and 200 MSPS A D sample rates for the application logic Voltage Maximum Allowed Typical Current Typical Derived from Supplies these Devices Current A Required A Power W 3 3V 15 61 20 1 Direct connect to the FPGA clock controls and PCIe host analog power supplies 12V 4 0 7 8 4 Direct connect to the FPGA PCIe host VPWR pins Total 28 5 Power Table 13 X5 RX Power Consumption Surge currents occur initially at power on and after application logic initialization The power on surge current lasts for about 10 ms at several amperes on both 3 3V and 12V This surge is due primarily to charging the on card capacitors and the startup current of the FPGAs After initial power up the logic configuration will also result in a step change to the current consumption because the logic will begin to operate In our testing and measurements this has not been a surge current as much as a just a step change in the power consumption Power consumption varies and is primarily as a function ofthe logic design Logic designs with high utilization and fast clock rates require higher power Since calculating power consumption in the logic requires many details to be considered Xilinx tools such as XPower are used to get the best estimates It is important that any custom logic design have a substantial safety margin for the power
143. will be discarded unless saved in the handler Similarly OnDataRequired event is handled by HandleDataRequired In such a handler packets would be filled with data for output to the baseboard The Snap application does not generate output so the event 15 left unhandled Timer OnElapsed SetEvent this amp ApplicationIo HandleTimer Timer OnElapsed Thunk In this example a Malibu SoftwareTimer object has been added to the Applicationlo class to provide periodic status updates to the user interface The handler above serves this purpose An event is not necessarily called in the same thread as the UI If it is not and if you want to call a UI function in the handler you have to have the event synchronized with the UI thread A call to Synchronize directs the event to call the event handler in the main UI thread context This results in a slight performance penalty but allows us to call UI methods in the event handler freely The Timer uses a similar synchronization method Thunk Here the event is called in the main thread context but the issuing thread does not wait for the event to be handled before proceeding This method is useful for notification events Creating a hardware object does not attach it to the hardware The object has to be explicitly opened The Open method of the baseboard activates the board for use It opens the device driver for the baseboard and allocates internal resources for use The next step 1s to call R
144. xternalTrigger 1 Frame count in units of packet elements if Settings Framed Module gt Output Framed Settings FrameCount else Module gt Output Unframed Alerts and starting the Stream are the same as in Input only mode enum IUsesX5Alerts AlertType Alert IUsesX5Alerts alertTimeStampRollover IUsesX5Alerts alertSoftware IUsesX5Alerts alertWarningTemperature IUsesX5Alerts alertOutputFifoUnderrun IUsesX5Alerts alertOutputTrigger for unsigned int 0 lt Settings AlertEnable size 1 Module Alerts AlertEnable Alert i Settings AlertEnable i true false Start Streaming Stream Start UI gt Log Stream Mode started UI gt Status Stream Mode started FTicks 0 Timer Enabled true void ApplicationIo StopStreaming if FStreaming return if FStreamConnected UI gt Log Stream not connected Open the boards return Stop Streaming Stream gt Stop FStreaming false Timer Enabled false Data Required Event Handler When the output stream needs additional data the Data Required event is signalled The Wave application uses this call to generate new blocks for each channel and send them to the output via the SendOneBlock method X5 RX User s Manual Writing Custom Applications void Applicationlo HandleDataRequired PacketStreamDataEvent amp Event SendOneBlock Event Sender const in

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