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DE2 User Manual v1.4 - La Sierra University

1. T e i DLY1 ie i Delay TV DLY2 Video Decoder E 77 wx A DAC 7181B i 7123 TD HS To Control the Detector Sequence o seik YUV 4 2 2 E I2C AV to Config YUV 4 44 i Figure 5 1 Block diagram of the TV box demonstration Demonstration Setup File Locations and Instructions e Project directory DE2 TV e Bit stream used DE2 TV sof or DE2_TV pof e Connect a DVD player s composite video output yellow plug to the Video in RCA jack of the DE2 board The DVD player has to be configured to provide NTSC output o 60 Hz refresh rate o 4 3 aspect ratio e Non progressive video e Connect the VGA output of the DE2 board to a VGA monitor both LCD and CRT type of monitors should work 56 8YA DE2 User Manual e Connect the audio output of the DVD player to the line in port of the DE2 board and connect a speaker to the line out port If the audio output jacks from the DVD player are of RCA type then an adaptor will be needed to convert to the mini stereo plug supported on the DE2 board this 1s the same type of plug supported on most computers Load the bit stream into FPGA Press KEYO on the DE2 board to reset the circuit Figure 5 2 illustrates the setup for this demonstration Video In os Lu FEF T TATT DVD Player Ba boba bo bn a bofa ofa lalalalalalala E 5 4 VGA LCD CRT Monitor ITU R 656 YUV 4 2 2 Decoder Figure
2. a USB command controller and a multi port SRAM SDRAM Flash controller USB Blaster Hardware USB Link DE Board PC Side DE Control Panel JTAG Link Serial to Parallel Conversion Command Controller 1 kHz Sine Wave Look up Table 7 SEG LUT Controller LCD Controller Host Port b User Port 3 Async 3 4 User Port 2 Async 2 4 Controller User Port 1 Async 1 4 Host Port SRAM User Port 2 Async 2 4 Controller User Port 1 Async 1 User Port 3 Async 3 4 VGA DAC Controller FPGA Memory Host Port UserPort 3 Async 3 4 Flash UserPort2 Async 2 Controller User Port1 Async 1 Audio DAC Controller bii T SEG PS 2 Keyboard 16x2 LCD Module SDRAM Memory SRAM Memory s dH VGA LCD CRT DAC Monitor Flash Memory EH Figure 3 7 The DE2 Control Panel block diagram Users can connect circuits of their own design to one of the User Ports of the SRAM SDRAM Flash controller Then they can download binary data into the SRAM SDRAM Flash Once the data is downloaded to the SDRAM Flash users can configure the memory controllers so that their circuits can read write the SDRAM Flash via the User Ports connected Boy DE2 User Manual 3 6 TOOLS Multi Port SRAM SDRAM Flash Controller The TOOLS page of the Control Panel GUI allows selection of the User Ports We will illustrate a typica
3. 0 1U 01U 10U VGND VGND VGND Figure 4 19 TV Decoder schematic Table 4 13 TV Decoder pin assignments 45 oN OT A DE2 User Manual 4 13 Implementing a TV Encoder Although the DE2 board does not include a TV encoder chip the ADV7123 10 bit high speed triple ADCs can be used to implement a professional quality TV encoder with the digital processing part implemented in the Cyclone II FPGA Figure 4 20 shows a block diagram of a TV encoder implemented in this manner TV Encoder Block Cyclone 235 0 Composite ta sie z Y U cos V sin Clock BESTE Calculate or Y S Video Timing Meth EUM lor RCA Y C U cos V sin S Video SIN or RCA Pb g COS Y U V Tables RCA_Pr Figure 4 20 A TV Encoder that uses the Cyclone II FPGA and the ADV7123 4 14 Using USB Host and Device The DE2 board provides both USB host and device interfaces using the Philips ISP1362 single chip USB controller The host and device controllers are compliant with the Universal Serial Bus Specification Rev 2 0 supporting data transfer at full speed 12 Mbit s and low speed 1 5 Mbit s Figure 4 21 shows the schematic diagram of the USB circuitry the pin assignments for the associated interface are listed in Table 4 14 Detailed information for using the ISP1362 device is available in its datasheet and programming guide both documents can be found on the manufacturer s web site and from the Datasheet folder o
4. Table 4 16 SDRAM pin assignments 51 DE2 User Manual SRAM ADDR 16 PIN AB8 SRAM Address 16 SRAM ADDR 17 PIN AC8 SRAM Address 1 7 SRAM DQ O PIN AD8 SRAM Data 0 SRAM DQ 1 PIN SRAM Data 1 SRAM 2 PIN AF6 SRAM Data SRAM DQI3 PIN AA9 SRAM Data 3 SRAM DQ 7 PIN Y11 SRAM Data 7 Table 4 17 SRAM pin assignments 52 DE2 User Manual FL ADDR 10 PIN AE17 FLASH Address 10 FL ADDR 11 PIN AF17 FLASH Address 11 FL ADDR 12 PIN W16 FLASH Address 12 FL ADDR 13 PIN W15 FLASH Address 13 FL ADDR 14 PIN AC16 FLASH Address 14 FL ADDR 15 PIN AD16 FLASH Address 15 FL ADDR 19 PIN AA15 FLASH Address 19 Table 4 18 Flash pin assignments 53 D V A DE2 User Manual Chapter 5 Examples of Advanced Demonstrations This chapter provides a number of examples of advanced circuits implemented on the DE2 board These circuits provide demonstrations of the major features on the board such as its audio and video capabilities and USB and Ethernet connectivity For each demonstration the Cyclone II FPGA or EPCS16 serial EEPROM configuration file 15 provided as well as the full source code in Verilog HDL code All of the associated files can be found in the DE2 demonstrations folder from the DE2 System CD ROM For each of demonstrations described in the following sections we give the name of the project directory for its files which are subdirectories of the
5. USB Blaster US B L klade TAG Pragress 0 T FAR eem L DE2 system DE2 control panel DE2 USB APlsof EP2C3SFEr2 mm Auto Detect Delete Gas Add File li Change File G Add Device Figure 3 1 Quartus II Programmer window IE DE Control Panel Open Help About FLASH SDRAM SRAM VGA PS2 amp 7 SEG Lepetcp Toor 7 SEG HEX 7 HEXB HEX5 HEX 4 i 4 0 4 0 HEX 3 HEX 2 HEX 1 HEX lo v p FS2 Keyboard Figure 3 2 The DE2 Control Panel The concept of the DE2 Control Panel 1s illustrated 1n Figure 3 3 The IP that performs the control functions is implemented in the FPGA device It communicates with the Control Panel window which is active on the host computer via the USB Blaster link The graphical interface 1s used to issue commands to the control circuitry The provided IP handles all requests and performs data transfers between the computer and the DE2 board 12 DE2 User Manual T SEG Display r Bep Abeer PS E 7 5EG LED amp LCD TOOLS FLASH SORAM SRAM TGA SDRAM Fandom cca ss Address 7 wOATA Inn DATA omn USB SDRAM i Blaster Flash SRAM Figure 3 3 The DE2 Control Panel concept The DE2 Control Panel can be used to change the values displayed on 7 segment displays light up LEDs talk to the PS 2 keyboard read write the SRAM Flash Memory and SDRAM load an image patter
6. 2 JP2 el TR m WEM die Altera USB Blaster Controller Chipset E pag rt Expansion Header 1 JP4 Altera EPCS16 Configuration Device a Altera Cyclone Il FPGA RUN PROG Switch for JTAG AS Modes NU r m 16x2 LCD Module p omm NE SD Card Slot 7 Segment Displays 8 Green LEDs 18 Red LEDs ESE IrDA Transceiver 18 Toaale Switch mimiuininimimininiuiuiu lui 1 1 SMA External Clock oggle Switches eja ye ye ye 15 pA 1 d i I z 4 Debounced Pushbutton Switches 50 MHz Oscillator 8 MB SDRAM 512 KB SRAM 4 MB Flash Memory Figure 2 1 The DE2 board The DE2 board has many features that allow the user to implement a wide range of designed circuits from simple circuits to various multimedia projects The following hardware is provided on the DE2 board e Altera Cyclone II 2C35 FPGA device e Altera Serial Configuration device EPCS16 e USB Blaster on board for programming and user API control both JTAG and Active Serial AS programming modes are supported 512 Kbyte SRAM e 8 Mbyte SDRAM INDE 5 A DE2 User Manual e 4 Mbyte Flash memory 1 Mbyte on some boards e SD Card socket e 4 pushbutton switches e 18 toggle switches 18 red user LEDs 9 green user LEDs 50 MHz oscillator and 27 MHz oscillator for clock sources e 24 bit CD quality audio CODEC with line in line out and microphone in jacks e VGA DAC 10 bit high speed
7. A6 DRAM AZ an DRAM AS DRAM A3 E g DRAM AA R_VCC33 GND SDRAM 1Mx16x4 DIP54 TSOP Figure 4 23 SDRAM schematic SRAM AQ SRAM A17 SRAM A1 4 SRAM A16 SRAM A2 47 SRAM A15 SRAM A3 41 SRAM OE SRAM A4 40 SRAM UB SRAM x SRAM LB SRAM DD i SRAM D15 SRAM D1 B SRAM D14 SRAM D2 a SRAM D13 SRAM_DS3 SRAM D12 R_VOC33 E GND GND R VCC33 SRAM D4 7 SRAM D11 SRAM SRAM D10 SRAM SRAM SRAM D7 b x SRAM D8 SRAM WE B SRAM A5 SRAM A14 SRAM AG a B SRAM A13 SRAM A7 20 SRAM A12 SRAM A8 A SRAM A11 SRAM AS K SRAM A10 I561LV 25616 DIPA4 TSOP Figure 4 24 SRAM schematic 49 N DTE SYN DE2 User Manual u20 FLASH A16 FLASH A17 FLASH A15 FLASH A14 GND FLASH A13 FLASH AO GND FLASH A12 FLASH D7 FLASH A11 FLASH A10 FLASH D6 FLASH A9 FLASH A20 Q 4n FLASH D5 FLASH A21 1 Q FLASH WE FLASH D4 W C FLASH RESET 4 F VCC33 LE FLASH D3 FLASH A19 FLASH D2 FLASH A18 FLASH A8 FLASH D1 FLASH A7 Q FLASH A6 FLASH DO FLASH A5 FLASH OE FLASH A4 FLASH A3 FLASH CE IONO FLASH A2 FLASH A1 R43 4 7K S29AL032DTFN TSOP 48 FLASH OE Figure 4 25 Flash schematic 50 DE2 User Manual DRAM DQ 9 PIN AB2 SDRAM Data 9 DRAM DQ 10 PIN AB1 SDRAM Data 10 DRAM_DQ 11 PIN_AA4 SDRAM Data 1 1 DRAM DQ 12 PIN AA3 SDRAM Data 12 DRAM DQ 13 PIN AC2 SDRAM Data 13 DRAM DQ 14 PIN SDRAM Data 14 DRAM LDQM PIN AD2 SDRAM Low byte Data Mask
8. Asynchronous Port 1 and clicked the Configure button the Audio DAC Controller will communicate with the Flash memory directly In our example the 19 INDE oY DE2 User Manual AUDIO_DAC Verilog module defines a circuit that reads the contents of the Flash memory and sends it to the external audio chip 3 7 VGA Display Control The Control Panel provides a tool with the associated IP that allows the user to display an image via the VGA output port To illustrate this feature we will show how an image can be displayed on a VGA monitor Perform the following steps to display a default image e Select the VGA tab in the Control Panel to reach the window in Figure 3 9 IE DE2 Control Panel Open Help About PS amp 7 SEG LED amp LCD FLASH SDRAM SRAM DE2 Board iv Default Image Figure 3 9 Displayed image and the cursor controlled by the scroll bars e Make sure that the checkboxes Default Image and Cursor Enable are checked e Connect a VGA monitor to the DE2 board and you should see on the screen the default image shown in Figure 3 9 The image includes a cursor which can be controlled by means of the X Y axes scroll bars on the DE2 Control Panel The image in Figure 3 9 is stored in an M4K memory block in the Cyclone II FPGA It is loaded into the M4K block in the MIF Hex Intel format during the default bit stream configuration stage We will next describe how you can display other i
9. FIELD e Applications DVD recorders LCD TV Set top boxes Digital TV Portable video devices 10 100 Ethernet controller e Integrated MAC and PHY with a general processor interface e Supports 100Base T and IOBase T applications e Supports full duplex operation at 10 Mb s and 100 Mb s with auto MDIX e Fully compliant with the IEEE 802 3u Specification e Supports IP TCP UDP checksum generation and checking e Supports back pressure mode for half duplex mode flow control USB Host Slave controller e Complies fully with Universal Serial Bus Specification Rev 2 0 e Supports data transfer at full speed and low speed e Supports both USB host and device e Two USB ports one type A for a host and one type B for a device e Provides a high speed parallel interface to most available processors supports Nios II with a Terasic driver INDE 5 A DE2 User Manual e Supports Programmed I O PIO and Direct Memory Access DMA Serial ports One RS 232 port One PS 2 port e DB 9 serial connector for the RS 232 port e PS 2 connector for connecting a PS2 mouse or keyboard to the DE2 board IrDA transceiver e Contains a 115 2 kb s infrared transceiver e 32mALED drive current e Integrated EMI shield e EC825 1 Class 1 eye safe e Edge detection input Two 40 pin expansion headers 72 Cyclone II I O pins as well as 8 power and ground lines are brought out to two 40 pin expansion connectors e 40 pin header is designed to accept a standard 4
10. IOR 722 1 p VGA B R95 0 VGA G5 5 VGA G6 ADV7123 VGA G7 R9672 R97 R98 VGA G8 VGA G9 1 75 75 75 OOCHERE d D am VGA HS R99 47 VGA VS R100 47 Li VGA VCC5 i Figure 4 11 WGA circuit schematic The timing specification for VGA synchronization and RGB red green blue data can be found on various educational web sites for example search for VGA signal timing Figure 4 12 illustrates the basic timing requirements for each row horizontal that is displayed on a VGA monitor An active low pulse of specific duration time a in the figure is applied to the horizontal synchronization Async input of the monitor which signifies the end of one row of data and the start of the next The data RGB inputs on the monitor must be off driven to 0 V for a time period called the back porch b after the hsync pulse occurs which is followed by the display interval c During the data display interval the RGB data drives each pixel in turn across the row being displayed Finally there 15 a time period called the front porch d where the RGB signals must again be off before the next sync pulse can occur The timing of the vertical synchronization vsync is the same as shown in Figure 4 12 except that a vsync pulse signifies the end of one frame and the start of the next and the data refers to the set of rows in the frame horizontal timing Figures 4 13 and 4 14 show for different resolutions the durations of ti
11. VGA DAC o VGA Lepicr Controller DAC Monitor Figure 3 11 Multi Port Controller configured to display an image from the SRAM User Port 3 Asyne 3 4 LI 2f Pa ri 2 As yn c User Porti Async 1 2 USB Command Controller 21 DE2 User Manual Figure 3 12 A displayed image You can display any image file by loading it into the SRAM chip or into an M4K memory block in the Cyclone II chip This requires generating a bitmap file which may be done as follows l 2 Load the desired image into an image processing tool such as Corel PhotoPaint Resample the original image to have a 640 x 480 resolution Save the modified image in the Windows Bitmap format Execute DE2 control paneNmgConv exe an image conversion tool developed for the DE2 board to reach the window in Figure 3 13 Click on the Open Bitmap button and select the 640 x 480 Grayscale photo for conversion When the processing of the file is completed click on the Save Raw Data button and a file named Raw Data Gray dat will be generated and stored in the same directory as the original image file You can change the file name prefix from Raw Data to another name by changing the File Name field in the displayed window Raw Data Gray dat is the raw data that can be downloaded directly into the SRAM on the DE2 board and displayed on the VGA monitor using the VGA controller IP described in the DE2 USB API project The mgConv tool will
12. be used to e Frase the entire Flash memory e Write one byte to the memory e Read one byte from the memory e Write a binary file to the memory e Load the contents of the Flash memory into a file Note the following characteristics of the Flash memory e The Flash memory chip is organized as 4 M or 1 M on some boards x 8 bits e You must erase the entire Flash memory before you can write into it Be aware that the number of times a Flash memory can be erased 1s limited e The time required to erase the entire Flash memory is about 20 seconds Do not close the DE2 Control Panel in the middle of the operation To open the Flash memory control window shown in Figure 3 6 select the FLASH tab in the Control Panel I DE2 Control Panel BEES Open Help About LED amp LCD TOOLS SDRAM SRAM VGA Random Access Address 0 wDATA 00 DATA 00 Chip Erase fe4 Sec Write Head sequential write Address 0 Length 0 File Length Write a File to FLASH sequential Read Address 0 Length 0 Entire Flash Load FLASH Content to a File Figure 3 6 Flash memory control window A byte of data can be written into a random location on the Flash chip as follows 1 Click on the Chip Erase button The button and the window frame title will prompt you to wait until the operation is finished which takes about 20 seconds 16 5 DE2 User Manual 2 Enter the desired address into the Addr
13. card socket e Provides SPI mode for SD Card access e Accessible as memory for the Nios II processor with the DE2 SD Card Driver Pushbutton switches e 4 pushbutton switches e Debounced by a Schmitt trigger circuit e Normally high generates one active low pulse when the switch is pressed Toggle switches e 18 toggle switches for user inputs e Aswitch causes logic 0 when in the DOWN closest to the edge of the DE2 board position and logic 1 when in the UP position Clock inputs 50 MHz oscillator 27 MHz oscillator e SMA external clock input 5 DE2 User Manual Audio CODEC Wolfson WM8731 24 bit sigma delta audio CODEC ine level input line level output and microphone input jacks e Sampling frequency 8 to 96 KHz e Applications for MP3 players and recorders PDAs smart phones voice recorders etc VGA output e Uses the ADV7123 240 MHz triple 10 bit high speed video DAC e With 15 pin high density D sub connector e Supports up to 1600 x 1200 at 100 Hz refresh rate e Can be used with the Cyclone II FPGA to implement a high performance TV Encoder NTSC PAL TV decoder circuit e Uses ADV7181B Multi format SDTV Video Decoder Supports NTSC M J 4 43 PAL B D G H I M N SECAM e Integrates three 54 MHz 9 bit ADCs e Clocked from a single 27 MHz oscillator input e Supports Composite Video CVBS RCA jack input e Supports digital output formats 8 bit 16 bit ITU R BT 656 YCrCb 4 2 2 output HS VS and
14. image shown in Figure 2 3 Set the toggle switch SW17 to the DOWN position you should hear a 1 kHz sound Set the toggle switch SW17 to the UP position and connect the output of an audio player to the Line in connector on the DE2 board on your headset you should hear the music played from the audio player MP3 PC iPod or the like You can also connect a microphone to the Microphone in connector on the DE2 board your voice will be mixed with the music played from the audio player EUN a PALE www terasic com Figure 2 3 The default VGA output pattern Chapter 3 10 ANU DE2 User Manual DE2 Control Panel The DE2 board comes with a Control Panel facility that allows a user to access various components on the board through a USB connection from a host computer This chapter first presents some basic functions of the Control Panel then describes its structure in block diagram form and finally describes its capabilities 3 1 Control Panel Setup To run the Control Panel application it is first necessary to configure a corresponding circuit in the Cyclone II FPGA This is done by downloading the configuration file DE2_USB_API sof into the FPGA The downloading procedure is described in Section 4 1 In addition to the DE2 USB APL sof file it is necessary to execute on the host computer the program DE2 control panel exe Both of these files are available on the DE2 System CD ROM that accompanies the DE2 boar
15. that runs the Microsoft Windows software 1 1 Package Contents Figure 1 1 shows a photograph of the DE2 package Figure 1 1 The DE2 package contents DE2 User Manual The DE2 package includes 1 2 DE2 board USB Cable for FPGA programming and control CD ROM containing the DE2 documentation and supporting materials including the User Manual the Control Panel utility reference designs and demonstrations device datasheets tutorials and a set of laboratory exercises CD ROMs containing Altera s Quartus II Web Edition and the Nios II Embedded Design Suit Evaluation Edition software Bag of six rubber silicon covers for the DE2 board stands The bag also contains some extender pins which can be used to facilitate easier probing with testing equipment of the board s I O expansion headers Clear plastic cover for the board 9V DC wall mount power supply The DE2 Board Assembly To assemble the included stands for the DE2 board Assemble a rubber silicon cover as shown in Figure 1 2 for each of the six copper stands on the DE2 board The clear plastic cover provides extra protection and 1s mounted over the top of the board by using additional stands and screws r Figure 1 2 The feet for the DE2 board 1 3 Here are the addresses where you can get help if you encounter problems Getting Help Altera Corporation 101 Innovation Drive San Jose California 95134 USA Email university altera com
16. 0 100 Ethernet P hy MAC SD Card Cyclone FPGA 2035 IrDA Transceiver Flash 1 Mbyte User Green LEDs 8 SDRAM 8 Mbytes 16 bit Audio CODEC VGA 10 bit Video DAC PS2 amp RS 232 Ports Toggle Switches 18 User Red LEDs 18 16x 2 LCD Module SRAM 512 Kbytes 7T SegmentDisplay 8 f Expansion Headers 2 Pushbutton Switches 4 EPCS16 Config Device USB Blaster Figure 2 2 Block diagram of the DE2 board Following is more detailed information about the blocks in Figure 2 2 Cyclone II 2C35 FPGA e 33 216 LEs e 105 M4K RAM blocks e 483 840 total RAM bits e 35 embedded multipliers e 4PLLs e 475 user I O pins e FineLine BGA 672 pin package Serial Configuration device and USB Blaster circuit Altera s EPCS16 Serial Configuration device On board USB Blaster for programming and user API control JTAG and AS programming modes are supported DVA DE2 User Manual SRAM 512 Kbyte Static RAM memory chip e Organized as 256K x 16 bits e Accessible as memory for the Nios II processor and by the DE2 Control Panel SDRAM 8 Mbyte Single Data Rate Synchronous Dynamic RAM memory chip e Organized as 1M x 16 bits x 4 banks e Accessible as memory for the Nios II processor and by the DE2 Control Panel Flash memory 4 Mbyte NOR Flash memory 1 Mbyte on some boards e 8 bit data bus e Accessible as memory for the Nios II processor and by the DE2 Control Panel SD
17. 0 pin ribbon cable used for IDE hard drives e Diode and resistor protection is provided 2 3 Power up the DE2 Board The DE2 board comes with a preloaded configuration bit stream to demonstrate some features of the board This bit stream also allows users to see quickly if the board is working properly To power up the board perform the following steps 1 Connect the provided USB cable from the host computer to the USB Blaster connector on the DE2 board For communication between the host and the DE2 board it 1s necessary to install the Altera USB Blaster driver software If this driver is not already installed on the host computer it can be installed as explained in the tutorial Getting Started with Altera s DE2 Board This tutorial is available on the DEZ System CD ROM and from the Altera DE2 web pages Connect the 9V adapter to the DE2 board Connect a VGA monitor to the VGA port on the DE2 board Connect your headset to the Line out audio port on the DE2 board Turn the RUN PROG switch on the left edge of the DE2 board to RUN position the PROG position is used only for the AS Mode programming js ge i I9 9 DVA DE2 User Manual 6 Turn the power on by pressing the ON OFF switch on the DE2 board At this point you should observe the following All user LEDs are flashing All 7 segment displays are cycling through the numbers 0 to F The LCD display shows Welcome to the Altera DE2 Board The VGA monitor displays the
18. 3 Using the 7 segment edere 20 4 4 eissiniicm 22 4 5 RUST Te EC DONTOOU G vue 33 ZO Uoi mer Pim on Hoad tttm E SN OEedESEM S iRM eMe 35 4 7 i60 37 4S Using Te Fit GIO COD QE 4 4 9 Genes T 42 NI MEER PASO NUUS mE 42 4 11 Fast Ethernet Network Controller s cncscseusticvecactussounscnareendonswaueustenesacdusveseidnatecnlensvaeuctenesaceni 43 PM EDI eamm 44 oou 46 AN MEUS USB HB mU 46 E 45 4 16 Usme SDRAMSRAMIFIa 40 Chapter 5 Examples of Advanced Demonstrations ccc 9 2 eee eee 2222000 54 5 1 DE Fcon Coni E EEEo 54 Altera DE2 Board 3 2 5 3 5 4 5 5 5 6 I 5 8 TV Bor Demon miO esa EE 53 CSBP OMD S PENNE E E 57 E E E 50 PTR AG AOR CV PAC DTI uos 61 Ethernet Packet Sendmp ROCODVIDE 62 DESC i MT 64 Music Synthesizer D monstration secret taREL pue bred ea ava rue rbbEP 66 ANDE DAN DE2 User Manual Chapter 1 DE2 Package The DE2 package contains all components needed to use the DE2 board in conjunction with a computer
19. 4 2 and 4 3 respectively KEYO Roco gREIE TUEN ov G KEY1 i LLL a ee ee X in L 14 5 KEY2 KEY3 C16 C17 C18 C18 iU 1U qu 1U zu VECJO SW5 SWE SW SwuW13 SW14 SW15 SW16 SW17 4 GND 4 GND 4 GND 4 GND VCC33 VCC33 1 VCC33 VCC33 RN27 El B ls IU Swit ND IND ND JND a W16 GND GND GND GND a La al a SWS SLIDE SW SLIDE SW SLIDE SW SLIDE SW Figure 4 4 Schematic diagram of the pushbutton and toggle switches ed DE2 User Manual LEDRO LEDR LEDRA LEDR LEDG Tad JA LEDRS LEDR 3 as E r LEDR LEDR LEDRB LEDR ae LEDR LEDR E xm UH LEDR10 LEDR as LEDIR 14 LEDR AF Figure 4 5 Schematic diagram of the LEDs Table 4 1 Pin assignments for the toggle switches 28 DE2 User Manual PIN 426 Pushbutton 0 PIN N23 Pushbutton 1 KEY 2 PIN P23 Pushbutton 2 KEY 3 PIN W26 Pushbutton 3 Table 4 2 Pin assignments for the pushbutton switches LEDRI3 PIN AC22 LED Red 3 Table 4 3 Pin assignments for the LEDs 29 INDE SYN DE2 User Manual 4 3 Using the 7 segment Displays The DE2 Board has eight 7 segment displays These displays are arranged into two pairs and a group of four with the intent of displaying numbers of various sizes As indicated in the schematic in Figure 4 6 the seven segments are connected to pins on the
20. 5 2 The setup for the TV box demonstration 5 3 USB Paintbrush USB is a popular communication method used in many multimedia products The DE2 board provides a complete USB solution for both host and device applications In this demonstration we implement a Paintbrush application by using a USB mouse as the input device This demonstration uses the device port of the Philips ISP1362 chip and the Nios II processor to implement a USB mouse movement detector We also implemented a video frame buffer with a VGA controller to perform the real time image storage and display Figure 5 3 shows the block diagram of the circuit which allows the user to draw lines on the VGA display screen using the USB mouse The VGA Controller block is integrated into the Altera Avalon bus so that it can be controlled by the Nios II processor Once the program running on the Nios II processor is started it will detect the existence of the USB mouse connected to DE2 board Once the mouse is moved the Nios II processor is able to keep track of the movement and record it in a frame buffer memory The VGA Controller will overlap the 57 DE2 User Manual data stored in the frame buffer with a default image pattern and display the overlapped image on the VGA display Philips ISP1362 Host Altera Avalon Figure 5 3 Block diagram of the USB paintbrush demonstration Demonstration Setup File Locations and Instructions Project directory DE2_NIOS_HO
21. Altera DE2 Board JAN DTE RYAN DE2 Development and Education Board User Manual Version 1 4 Copyright 2006 Altera Corporation Altera DE2 Board ACK 1 1 1 PAC AS l 1 2 e DE E E A S 2 1 3 ruis E E R 3 Doar hoen anon 4 24 Lavourtaud OM OMT ati IE cIO NER E E 4 2 2 Block DuIaProTELOL the DE Board S pue MAN DIMUS MAUI M OM 5 2 9 POW er up The JE HEU PEU 9 Chapter 3 DE2 10 SN GTB OL 0 11 2 2 Controlling the LEDs 7 Segment Displays and LCD 13 3 3 SDRAM SRAM Controller and Programmer esses nnne 14 DA AS PO ceo 16 3 5 Overall Structure of the DE2 Control 17 3 6 TOOLS Multi Port SRAM SDRAM Flash Controller eese 19 3 7 VG ay NER E 20 Chapter 4 Usine the DEZ Board iexiecivindii roni Eee N EEN EEE NOA EE Eana o Pelr 24 4 1 Sonate the Cyclone dC T EN EE 24 22 che EDS VOL DIOS quat qim 26 4
22. Cyclone II FPGA Applying a low logic level to a segment causes it to light up and applying a high logic level turns it off Each segment in a display is identified by an index from 0 to 6 with the positions given in Figure 4 7 Note that the dot in each display is unconnected and cannot be used Table 4 4 shows the assignments of FPGA pins to the 7 segment displays Figure 4 7 Position and index of each segment in a 7 segment display 30 HEXO 0 PIN AF10 Seven Segment Digit O O HEXO 1 PIN AB12 Seven Segment Digit O 1 HEXO 2 PIN AC12 Seven Segment Digit O 2 HEXO 3 PIN Seven Segment Digit O 3 HEX1 0 PIN V20 Seven Segment Digit 1 0 31 DE2 User Manual INDE 5 A DE2 User Manual HEX5 1 PIN P6 Seven Segment Digit 5 1 HEX5 2 PIN P7 Seven Segment Digit 5 2 HEX5 3 PIN T9 Seven Segment Digit 5 3 HEX5 4 PIN R5 Seven Segment Digit 5 4 HEX5 5 PIN R4 Seven Segment Digit 5 5 HEX5 6 PIN R3 Seven Segment Digit 5 6 HEX6 0 PIN R2 Seven Segment Digit 6 0 HEX6 1 PIN P4 Seven Segment Digit 6 1 HEX6 2 PIN P3 Seven Segment Digit 6 2 HEX6 3 PIN M2 Seven Segment Digit 6 3 HEX6 4 PIN M3 Seven Segment Digit 6 4 HEX6 5 PIN M5 Seven Segment Digit 6 5 HEX6 6 PIN M4 Seven Segment Digit 6 6 HEX7 0 PIN L3 Seven Segment Digit 7 0 HEX7 1 PIN L2 Seven Segment Digit 7 1 HEX7 2 PIN L9 Seven Segment Digit 7 2 HEX7 3 PIN L6 Seven Segment Digit 7 3 HEX7 4 PIN L7 Seven Segment Digit 7 4 HEX7 5 P
23. D card into FAT 6 format e To play a music file with this demonstration the file must use the 46KHz sample rate and 16 bit sample resolution WAV format Copy one or more such WAV files onto the FAT16 formatted SD Card Due to a limitation in the software used for this demonstration it is necessary to reformat the whole SD Card if any WAV file that has been copied onto the card needs to be later removed from the SD Card Load the bit stream into the FPGA Run the Nios II IDE under the workspace DE2 SD Card Audio e Connect a headset or speaker to the DE2 board and you should be able to hear the music played from the SD Card Figure 5 12 illustrates the setup for this demonstration 65 DE2 User Manual Speaker SD Card Driver CODEC XE Controller On Chip Audio PCM Buffer Figure 5 12 The setup for the SD music player demonstration 5 8 Music Synthesizer Demonstration This demonstration shows how to implement a Multi tone Electronic Keyboard using DE2 board with a PS 2 Keyboard and a speaker PS 2 Keyboard is used as the piano keyboard for input The Cyclone II FPGA on the DE2 board serves as the Music Synthesizer SOC to generate music and tones The VGA connected to the DE2 board is used to show which key is pressed during the playing of the music Figure 5 13 shows the block diagram of the design of the Music Synthesizer There are four major blocks in the circuit DEMO SOUND PS2 KEYBOARD STAFF and TONE GENERA
24. DE2 demonstrations folder Installing the Demonstrations To install the demonstrations on your computer perform the following 1 Copy the directory DE2 demonstrations into a local directory of your choice It is important to ensure that the path to your local directory contains no spaces otherwise the Nios II software will not work 2 In the directory DE2 demonstrations go to the subdirectory fixpaths 3 Run the DE2 fixpaths bat batch file In the dialog box that pops up select the directory DE2 demonstrations in your local directory where you copied the files to Click OK 4 When fixpaths 1s finished press any key to complete the process 5 1 DE2 Factory Configuration The DE2 board is shipped from the factory with a default configuration that demonstrates some of the basic features of the board The setup required for this demonstration and the locations of its files are shown below Demonstration Setup File Locations and Instructions e Project directory DE2 Default e Bit stream used DE2 Default sof or DE2 Default pof 54 INDE 5 A DE2 User Manual e Power on the DE2 board with the USB cable connected to the USB Blaster port If necessary that is if the default factory configuration of the DE2 board is not currently stored in EPCS16 device download the bit stream to the board by using either JTAG or AS programming e You should now be able to observe that the 7 segment displays are displaying a sequence of chara
25. GA This configuration data 1s automatically loaded from the EEPROM chip into the FPGA each time power is applied to the board Using the Quartus II software it is possible to reprogram the FPGA at any time and it is also possible to change the non volatile data that is stored in the serial EEPROM chip Both types of programming methods are described below 1 JTAG programming In this method of programming named after the IEEE standards Joint Test Action Group the configuration bit stream is downloaded directly into the Cyclone II FPGA The FPGA will retain this configuration as long as power is applied to the board the configuration is lost when the power is turned off 2 AS programming In this method called Active Serial programming the configuration bit stream is downloaded into the Altera EPCSIO serial EEPROM chip It provides non volatile storage of the bit stream so that the information is retained even when the power supply to the DE2 board is turned off When the board s power is turned on the configuration data in the EPCS16 device is automatically loaded into the Cyclone II FPGA The sections below describe the steps used to perform both JTAG and AS programming For both methods the DE2 board 15 connected to a host computer via a USB cable Using this connection the board will be identified by the host computer as an Altera USB Blaster device The process for installing on the host computer the necessary software device driver that
26. IN P9 Seven Segment Digit 7 5 HEX7 6 PIN N9 Seven Segment Digit 7 6 Table 4 4 Pin assignments for the 7 segment displays 4 4 Clock Inputs The DE2 board includes two oscillators that produce 27 MHz and 50 MHz clock signals The board also includes an SMA connector which can be used to connect an external clock source to the board The schematic of the clock circuitry is shown in Figure 4 8 and the associated pin assignments appear in Table 4 5 The 27 MHz clock is fed to the FPGA from the TV decoder chip The chip has an active low reset signal that inhibits the clock when it 1s asserted to a low logic level To get the 27 MHz clock to appear on the input pin the TV decoder chip s reset signal TD RESET PIN CA on the FPGA must be asserted to a high logic level 32 INDE oY DE2 User Manual VCC33 oO BC4B8 0 1U EN VEC GND OUT V VCC33 50MHZ EN VEC 50MHZ S EXT CLOCK 1 our j PIN 518 27 MHz clock input PIN N2 50 MHz clock input PIN P26 External SMA clock input Table 4 5 Pin assignments for the clock inputs 4 5 Using the LCD Module The LCD module has built in fonts and can be used to display text by sending appropriate commands to the display controller which 1s called HD44780 Detailed information for using the display 15 available in its datasheet which can be found on the manufacturer s web site and from the Datasheet folder on the DEZ System CD ROM A schematic diagr
27. If the entire file 1s to be loaded then a checkmark may be placed in the File Length box instead of giving the number of bytes 3 To initiate the writing of data click on the Write a File to SDRAM button 4 When the Control Panel responds with the standard Windows dialog box asking for the source file specify the desired file in the usual manner The Control Panel also supports loading files with a hex extension Files with a hex extension are ASCII text files that specify memory values using ASCII characters to represent hexadecimal values For example a file containing the line 0123456789ABCDEF defines four 16 bit values 0123 4567 89AB CDEF These values will be loaded consecutively into the memory The Sequential Read function is used to read the contents of the SDRAM and place them into a file as follows 1 Specify the starting address in the Address box 2 Specify the number of bytes to be copied into the file in the Length box If the entire contents of the SDRAM are to be copied which involves all 8 Mbytes then place a checkmark in the Entire SDRAM box 3 Press Load SDRAM Content to a File button 4 When the Control Panel responds with the standard Windows dialog box asking for the destination file specify the desired file in the usual manner 15 INDE DAN DE2 User Manual 3 4 Flash Memory Programmer The Control Panel can be used to write read data to from the Flash memory chip on the DE2 board It can
28. SH SDRAM SRAM PS amp 7 SEG LED amp LCD LED LCD Text for display Clear ow Figure 3 4 Controlling LEDs and the LCD display 3 3 SDRAM SRAM Controller and Programmer The Control Panel can be used to write read data to from the SDRAM and SRAM chips on the DE2 board We will describe how the SDRAM may be accessed the same approach is used to access the SRAM Click on the SDRAM tab to reach the window in Figure 3 5 IE DE2 Control Panel Open Help About P52 amp 7 SEG LED amp LCD TOOLS FLASH SDRAM sRAM SORAM Random Access Address 200 wDATA ECA DATA Write sequential Write Address 0 Length 0 File Length Write a File to SDRAM sequential Read Address 0 Length 0 Entire Sdram Load SDRAM Contentto a File Figure 3 5 Accessing the SDRAM 14 5 DE2 User Manual A 16 bit word can be written into the SDRAM by entering the address of the desired location specifying the data to be written and pressing the Write button Contents of the location can be read by pressing the Read button Figure 3 5 depicts the result of writing the hexadecimal value 6CA into location 200 followed by reading the same location The Sequential Write function of the Control Panel is used to write the contents of a file into the SDRAM as follows 1 Specify the starting address in the Address box 2 Specify the number of bytes to be written in the Length box
29. ST_MOUSE_VGA Bit stream used DE2_NIOS_HOST_MOUSE_VGA sof Nios II Workspace DE2_NIOS_HOST_MOUSE_VGA e Connect a USB Mouse to the USB Host Connector type A of the DE2 board e Connect the VGA output of the DE2 board to a VGA monitor both LCD and CRT type of monitors should work Load the bit stream into FPGA e Run the Nios II and choose DE2_NIOS_HOST_MOUSE_VGA as the workspace Click on the Compile and Run button e You should now be able to observe a blue background with an Altera logo on the VGA display e Move the USB mouse and observe the corresponding movements of the cursor on the screen Left click mouse to draw white dots lines and right click the mouse to draw blue dots lines on the screen 58 DE2 User Manual Figure 5 4 illustrates the setup for this demonstration VGA Out USB Device USB VGA Controller IP On Chip Video FrameBuffer B 4 Board www terasic com VGA Monitor Figure 5 4 The setup for the USB paintbrush demonstration 5 4 USB Device Most USB applications and products operate as USB devices rather than USB hosts In this demonstration we show how the DE2 board can operate as a USB device that can be connected to a host computer As indicated in the block diagram in Figure 5 5 the Nios II processor is used to communicate with the host computer via the host port on the DE2 board s Philips ISP1362 device After connecting the DE2 board to a USB port on
30. TOR The DEMO SOUND block stores a demo sound for user to play PS2 KEYBOARD handles the users input from PS 2 keyboard The STAFF block draws the corresponding keyboard diagram on VGA monitor when key s are pressed The TONE GENERATOR 1s the core of music synthesizer SOC User can switch the music source either from 52 or the DEMO SOUND block using SW9 To repeat the demo sound users can press KEY I The TONE GENERATOR has two tones 1 String 2 Brass which can be controlled by SWO The audio codec used on the DE2 board has two channels which can be turned ON OFF using SW1 and SW2 Figure 5 14 illustrates the setup for this demonstration 66 oy DE2 User Manual ADER CYCLONE II 2C20 VGA VS VGA CLOCK VGA R 3 VGA G 3 VGA B 3 1 CODE DEMO DEMO2 CODE PS2KB KEY2 CODE i SW 9 SOUND2 CODE SW 2 1 Figure 5 13 Block diagram of the Music Synthesizer design Demonstration Setup File Locations and Instructions e Project directory DE2 Synthesizer e Bit stream used DE2 Synthesizer sof or DE2_Synthesizer pof e Connect a PS 2 Keyboard to the DE2 board e Connect the VGA output of the DE2 board to a VGA monitor both LCD and CRT type of monitors should work e Connect the Lineout of the DE2 board to a speaker e Load the bit stream into FPGA e Make sure all the switches SW 9 0 are set to 0 Down Position e Press KEYI on the DE2 board to start th
31. Terasic Technologies No 356 Sec 1 Fusing E Rd Jhubei City HsinChu County Taiwan 302 Email support terasic com Web DE2 terasic com Arches Computing Unit 708 222 Spadina Ave Toronto Ontario Canada MST3A2 Email DE2supportQ archescomputing com Web DE2 archescomputing com DE2 User Manual A BBS Bulletin Board System Forum for the DE2 board has been created at the address shown below This Forum is meant to serve as a repository for information about the DE2 board and to provide a resource through which users can ask questions and share design examples BBS forum http www terasic com english discuss htm INDIE SYAN DE2 User Manual Chapter 2 Altera DE2 Board This chapter presents the features and design characteristics of the DE2 board 2 1 Layout and Components A photograph of the DE2 board is shown in Figure 2 1 It depicts the layout of the board and indicates the location of the connectors and key components USB USB USB Ethernet Blaster Device Host Mic Line Line Video VGAVideo 10 100M Port Port Port in in Out In Pot RS 232 Port FE T tot DC Power Supply Connector 1 27 MHz Oscillator 24 bit Audio Codec l r A Bm tE p P52 Keyboard Mouse Port Power ON OFF Switch ma NAM UE sud m BUSES PE VGA 10 bit DAC USB Host Slave Controller TV Decoder NTSCIPAL FO eral Aa U Ethernet 10 100M Controller sS EM im 3 Expansion Header
32. also generate Raw Data BW dat and its corresponding TXT format for the black and white version of the image the threshold for judging black or white level is defined in the BW Threshold 22 DE2 User Manual Terasic Image Converter Bw Threshold 128 Band of RGB Hed Processed Line fo File Hame Raw D ata Figure 3 13 The image converter window Image Source R G B Band B amp W Output Result Filter Threshold 640x480 Filter Color Picture N A Raw_Data_Gray Color Picture R G B BW Threshold Raw_Data BW optional Raw Data BW txt Grayscale N A N A Data Gray Picture Grayscale N A BW Threshold Raw Data BW Picture Raw Data BW txt Note Raw Data BW txt is used to fill in the MIF Intel Hex format for M4K SRAM 23 D V A DE2 User Manual Chapter 4 Using the DE2 Board This chapter gives instructions for using the DE2 board and describes each of its I O devices 4 1 Configuring the Cyclone II FPGA The procedure for downloading a circuit from a host computer to the DE2 board is described in the tutorial Quartus II Introduction This tutorial is found in the DE2 tutorials folder on the DE2 System CD ROM and it is also available on the Altera DE2 web pages The user is encouraged to read the tutorial first and to treat the information below as a short reference The DE2 board contains a serial EEPROM chip that stores configuration data for the Cyclone II FP
33. am of the LCD module showing connections to the Cyclone II FPGA is given in Figure 4 9 The associated pin assignments appear in Table 4 6 33 DE2 User Manual Q1 8050 Q2 8550 E VECS o R12 1U VCC43Q e gt LCD ON R13 680 Q3 VCCA3 Q4 8550 VCCA3Q R16 1K R15 C gt 680 dzlo BOR AIGIAIS ems Ye ass LCD BLON R14 680 K as Saliasisiasis dae uaa 47 Ls 8050 Sisi zi 15 Lco BL aT eb D ma D rs a 2 zl Sm D 2 X 16 DIGIT LCD LCD 2x18 Figure 4 9 Schematic diagram of the LCD module Table 4 6 Pin assignments for the LCD module 34 INDE D n DE2 User Manual e n amp 4 6 Using the Expansion Header The DE2 Board provides two 40 pin expansion headers Each header connects directly to 36 pins on the Cyclone II FPGA and also provides DC 45V VCC5 DC 3 3V VCC33 and two GND pins Figure 4 10 shows the related schematics Each pin on the expansion headers is connected to two diodes and a resistor that provide protection from high and low voltages The figure shows the protection circuitry for only four of the pins on each header but this circuitry is included for all 72 data pins Table 4 7 gives the pin assignments IO AO I 1 AG ID AS 7 A AS IO Ab ID Ar Wa AB H I Au Veces o mm g GND IO Ale ID ATi 1 AT I ID ATO i IO Al D GNb v s TEL 5 WEVE I AM ID AD protection resistors and
34. ate supported is 115 2 Kbit s and both the TX and RX sides have to use the same transmission rate Figure 4 22 shows the schematic of the IrDA communication link Please refer to the following website for detailed information on how to send and receive data using the IrDA Hink http techtrain microchip com webseminars documents IrDA The pin assignment of the associated interface are listed 1n Table 4 15 IRDA RXD IRDA TXD R28 Figure 4 22 IrDA schematic IRDA TXD PIN AE24 IRDA Transmitter IRDA RXD PIN AE25 IRDA Receiver Table 4 15 IrDA pin assignments 48 INDE SYN DE2 User Manual 4 16 Using SDRAM SRAM Flash The DE2 board provides an 8 Mbyte SDRAM 512 Kbyte SRAM and 4 Mbyte 1 Mbyte on some boards Flash memory Figures 4 23 4 24 and 4 25 show the schematics of the memory chips The pin assignments for each device are listed in Tables 4 16 4 17 and 4 18 The datasheets for the memory chips are provided in the Datasheet folder on the DE2 System CD ROM U17 R_VCC33 d GND DRAM DO 5 DRAM D15 R VCC33 GND DRAM D1 5 DRAM D14 DRAM D2 50 DRAM D13 GND E A R VCC33 DRAM D3 DRAM D12 DRAM D4 a A DRAM D11 R_VCC33 j AG GND DRAM D5 DRAM D10 DRAM D6 E DRAM D9 GND R VCC33 DRAM D7 4 DRAM Da R VCC33 4 GND DRAM LDZM AD DRAM WE g DRAM UDCGM DRAM CAS 3 DRAM CLK DRAM RAS 2 DRAM CKE DRAM CS j E DRAM D DRAM A11 DRAM BA1 DRAM A39 DRAM A10 DRAM DRAM AQ DRAM A7 DRAM A1 DRAM
35. automatically detects and converts a standard analog baseband television signal NTSC PAL and SECAM into 4 2 2 component video data compatible with 16 bit 8 bit CCIR601 CCIR656 The ADV7181 15 compatible with a broad range of video devices including DVD players tape based sources broadcast sources and security surveillance cameras The registers in the TV decoder can be programmed by a serial I2C bus which is connected to the Cyclone II FPGA as indicated in Figure 4 19 The pin assignments are listed in Table 4 13 Detailed information on the ADV7181 is available on the manufacturer s web site and from the Datasheet folder on the DE2 System CD ROM 44 DE2 User Manual V VCC18V VCC33 VCC33 PV VCC18 E AV VCC33 ed C40 C41 u33 E I a Oo 0 01U 0 1U S aa as AA D D n REE 1 7K eo CVBS IN C44 0 1U ag RCA JACK 3 ET RN52 mum TD DO C45 jiou CAT 10U A al 7 TD Di ze eee aod TD D 246 o 1U TAN TD D3 Ig AT C49 100 a2 oy RN53 _ ADVT181B PI2 eC DS an a co De LAAs D zZTMHz 47 R88 120 TD VS R90 V 120 TD HS TD RESET gt RESET on TD CLK27 V VCC33Q 2 PWROVWN ai 4 13 ALSB 21 33 I2C SCLK e 33 D _ A BC SDAT SCLK 50 25 E L Z S EC SDAT 53 spa 5 0 1U 0 1U 111 10U 56 VGND VGND i i I2C ADDRESS WRITE IS Ox4l VCC33 VCC33 12 B VGND L13 EAD BC103 BC104 Bc105 C52 0 1U
36. circuit that 1s instantiated in the Cyclone II FPGA This circuit is specified in Verilog code which makes it possible for a knowledgeable user to change the functionality of the Control Panel The code is located inside the DE2 demonstrations directory on the DE2 System CD ROM To run the Control Panel the user must first set it up as explained in Section 3 1 Figure 3 7 depicts the structure of the Control Panel Each input output device 1s controlled by a controller instantiated in the FPGA chip The communication with the PC is done via the USB Blaster link A Command Controller circuit interprets the commands received from the PC and performs the appropriate actions The SDRAM SRAM and Flash Memory controllers have three user selectable asynchronous ports in addition to the Host port that provides a link with the Command Controller The connection between the VGA DAC Controller and the FPGA memory allows displaying of the default image shown on the left side of the figure which is stored in an M4K block in the Cyclone 17 DE2 User Manual II chip The connection between the Audio DAC Controller and a lookup table in the FPGA is used to produce a test audio signal of 1 kHz To let users implement and test their IP cores written in Verilog without requiring them to implement complex API Host control software and memory SRAM SDRAM Flash controllers we provide an integrated control environment consisting of a software controller in C
37. communicates with the USB Blaster is described in the tutorial Getting Started with Altera s DE2 Board This tutorial is available on the DE2 System CD ROM and from the Altera DE2 web pages 24 DE2 User Manual Configuring the FPGA in JTAG Mode Figure 4 1 illustrates the JTAG configuration setup To download a configuration bit stream into the Cyclone II FPGA perform the following steps Ensure that power 15 applied to the DE2 board Connect the supplied USB cable to the USB Blaster port on the DE2 board see Figure 2 1 Configure the JTAG programming circuit by setting the RUN PROG switch on the left side of the board to the RUN position The FPGA can now be programmed by using the Quartus II Programmer module to select a configuration bit stream file with the sof filename extension USB Blaster Circuit PROG RUN g agne Quartus Il JTAG Config Sign ini te Ps UART JTAG Config Port Power on Config EPCS16 Serial Configuration Device Figure 4 1 The JTAG configuration scheme Configuring the EPCS16 in AS Mode Figure 4 2 illustrates the AS configuration set up To download a configuration bit stream into the EPCS16 serial EEPROM device perform the following steps Ensure that power 15 applied to the DE2 board Connect the supplied USB cable to the USB Blaster port on the DE2 board see Figure 2 1 Configure the JTAG programming circuit by setting the RUN PROG switch on the left side of the b
38. cters and the red and green LEDs are flashing Also Welcome to the Altera DE2 Board is shown on the LCD display e Optionally connect a VGA display to the VGA D SUB connector When connected the VGA display should show a pattern of colors e Optionally connect a powered speaker to the stereo audio out jack e Place toggle switch SW17 in the UP position to hear a 1 kHz humming sound from the audio out port Alternatively if switch SW17 is DOWN the microphone in port can be connected to a microphone to hear voice sounds or the line in port can be used to play audio from an appropriate sound source The Verilog source code for this demonstration is provided in the DE2_Default folder which also includes the necessary files for the corresponding Quartus II project The top level Verilog file called DE2_Default v can be used as a template for other projects because it defines ports that correspond to all of the user accessible pins on the Cyclone II FPGA 5 2 TV Box Demonstration This demonstration plays video and audio input from a DVD player using the VGA output and audio CODEC on the DE2 board Figure 5 1 shows the block diagram of the design There are two major blocks in the circuit called 126 AV Config and TV to VGA The TV_to_VGA block consists of the TU R 656 Decoder SDRAM Frame Buffer YUV422 to YUV444 YCrCb to RGB and VGA Controller The figure also shows the TV Decoder ADV7181 and the VGA DAC ADV7123 chips used As soo
39. d in the directory DE2 control panel Of course these files may already have been installed to some other location on your computer system To activate the Control Panel perform the following steps 1 Connect the supplied USB cable to the USB Blaster port connect the 9V power supply and turn the power switch ON Set the RUN PROG switch to the RUN position 3 Start the Quartus II software Select Tools gt Programmer to reach the window in Figure 3 1 Click on Add File and in the pop up window that appears select the DE2 USB API sof file Next click on the Program Configure box which results in the 1mage displayed in the figure Now click Start to download the configuration file into the FPGA 5 Start the executable DE2 control panel exe on the host computer The Control Panel user interface shown in Figure 3 2 will appear 6 Open the USB port by clicking Open Open USB Port 0 The DE2 Control Panel application will list all the USB ports that connect to DE2 boards The DE2 Control Panel can control up to 4 DE2 boards using the USB links The Control Panel will occupy the USB port until you close that port you cannot use Quartus II to download a configuration file into the FPGA until you close the USB port 7 The Control Panel is now ready for use experiment by setting the value of some 7 segment display and observing the result on the DE2 board UR NBrs SYN DE2 User Manual Chain1 cdf fx EA Hardware Setup
40. diodes DA not shown for other ports gs ME 0 BJ Bi Ia Be ER HOT Wwe Dm Gal protection resistors and diodes s a xs not shown for other ports DE Xs Figure 4 10 Schematic diagram of the expansion headers 35 DE2 User Manual GPIO_0 10 PIN N18 GPIO Connection O 10 GPIO O 11 PIN P18 GPIO Connection O 11 GPIO 0 12 PIN G23 GPIO Connection O 12 GPIO 0 13 PIN G24 GPIO Connection O 13 GPIO 0 14 PIN K22 GPIO Connection 0 14 GPIO 0 19 PIN J24 GPIO Connection O 19 36 D V A DE2 User Manual GPIO 1 11 PIN P24 GPIO Connection 1 11 GPIO 1 12 PIN R25 GPIO Connection 1 12 GPIO 1 13 PIN R24 GPIO Connection 1 13 GPIO 1 14 PIN R20 GPIO Connection 1 14 GPIO 1 15 PIN T22 GPIO Connection 1 15 GPIO 1 20 PIN T21 GPIO Connection 1 20 Table 4 7 Pin assignments for the expansion headers 4 7 Using VGA The DE2 board includes a 16 pin D SUB connector for VGA output The VGA synchronization signals are provided directly from the Cyclone II FPGA and the Analog Devices ADV7123 triple 10 bit high speed video DAC is used to produce the analog data signals red green and blue The associated schematic 15 given in Figure 4 11 and can support resolutions of up to 1600 x 1200 pixels at 100 MHz 37 DE2 User Manual VGA VCC5 R91 4 7K RSET R92 560 BC106 BC107 0 1U 0 1U VGA GO VGA VG G2 4 VGA R R93 0 VG G3 IOR VGA G R94 0 VGA G4
41. e 5 9 Packet sending and receiving using the Nios II processor Demonstration Setup File Locations and Instructions e Project directory DE2 NET e Bit stream used DE2 NET sof e Nios II Workspace DE2 NET Plug aCAT5 loop back cable into the Ethernet connector of DE2 e Load the bit stream into the FPGA Run the Nios IL IDE under the workspace DE2 NET e Click on the Compile and Run button e You should now be able to observe the contents of the packets received 64 byte packets sent 68 byte packets received because of the extra checksum bytes Figure 5 10 illustrates the setup for this demonstration 63 DE2 User Manual 10 100Mbps CAT 5 Cable Loopback Device DEM NET WE 3 Ethernet Driver EN Figure 5 10 The setup for the Ethernet demonstration 5 7 SD Card Music Player Many commercial media audio players use a large external storage device such as an SD card or CF card to store music or video files Such players may also include high quality DAC devices so that good audio quality 1s produced The DE2 board provides the hardware and software needed for SD card access and professional audio performance so that it 1s possible to design advanced multimedia products using the DE2 board In this demonstration we show how to implement an SD Card Music Player on the DE2 board in which the music files are stored in an SD card and the board can play the music files via
42. e music demo e Press KEYO on the DE2 board to reset the circuit Table 5 1 and 5 2 illustrate the usage of the switches pushbuttons KEYs PS 2 Keyboard 67 DE2 User Manual Reset Circuit KEY 1 Repeat the Demo Music SWIO lor BRASS ON STRING SWI9 OFF DEMO ON PS2 KEYBOARD SW 1 Channel 1 ON OFF SWI2 Channel 2 ON OFF Table 5 1 Usage of the switches pushbuttons KEYs PS 2 Keyboard Table 5 2 Usage of the PS 2 Keyboard s keys 68 INDE SYN DE2 User Manual Speaker Line Out VGA Out Keyboard Input ALII CDEFGAB DEFGAB A a LU Te mmu mu x A D i ad al ad lad al be La ol SI E VGA LCD CRT Monitor Music Synthesizer Figure 5 14 The Setup of the Music Synthesizer Demonstration Copyright 2005 Altera Corporation All rights reserved Altera The Programmable Solutions Company the stylized Altera logo specific device designations and all other words and logos that are identified as trademarks and or service marks are unless noted otherwise the trademarks and service marks of Altera Corporation in the U S and other countries All other product or service names are the property of their respective holders Altera products are protected under numerous U S and foreign patents and pending applications mask work rights and copyrights Altera warrants performance of its semiconductor products to current sp
43. ecifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Corporation Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or Services This document is being provided on an as is basis and as an accommodation and therefore all watranties representations or guarantees of any kind whether express implied or statutory including without limitation warranties of merchantability non infringement or fitness for a particular purpose are specifically disclaimed 69
44. ess box and the data byte into the wDATA box Then click on the Write button To read a byte of data from a random location enter the address of the location and click on the Read button The rDATA box will display the data read back from the address specified The Sequential Write function 1s used to load a file into the Flash chip as follows 1 Specify the starting address and the length of data in bytes to be written into the Flash memory You can click on the File Length checkbox to indicate that you want to load the entire file Click on the Write a File to Flash button to activate the writing process 3 When the Control Panel responds with the standard Windows dialog box asking for the source file specify the desired file in the usual manner The Sequential Read function is used to read the data stored in the Flash memory and write this data into a file as follows 1 Specify the starting address and the length of data in bytes to be read from the Flash memory You can click on the Entire Flash checkbox to indicate that you want to copy the entire contents of the Flash memory into a specified file Click on the Load Flash Content to a File button to activate the reading process 3 When the Control Panel responds with the standard Windows dialog box asking for the destination file specify the desired file in the usual manner 3 5 Overall Structure of the DE2 Control Panel The DE2 Control Panel facility communicates with a
45. gain of the CODEC are set in this manner and the data input from the line in port is then mixed with the microphone in port and the result is sent to the line out port For this demonstration the sample rate is set to 48 kHz Pressing the pushbutton KEYO reconfigures the gain of the audio CODEC via the I2C bus cycling through one of the ten predefined gains volume levels provided by the device I2C Audio Line out Configuration Audio line Push Button CODEC Ine poss Mic in ADC to DAC Figure 5 7 Block diagram of the Karaoke Machine demonstration 61 DE2 User Manual Demonstration Setup File Locations and Instructions e Project directory DE2_i2sound e Bit stream used DE2 i2sound sof or DE2 i2sound pof e Connect a microphone to the microphone in port pink color on the DE2 board e Connect the audio output of a music player such as an MP3 player or computer to the line in port blue color on the DE2 board e Connect a headset speaker to the line out port green color on the DE2 board e Load the bit stream into the FPGA e You should be able to hear a mixture of the microphone sound and the sound from the music player e Press KEYO to adjust the volume it cycles between volume levels 0 to 9 Figure 5 8 illustrates the setup for this demonstration MP3 Any Audio Output Speaker Microphone Lu sh SEE Men 1 E S a Ta Ta a
46. is available on the manufacturer s web site and from the Datasheet folder on the DE2 System CD ROM Figure 4 16 shows the related schematics and Table 4 10 lists the Cyclone II FPGA pin assignments UART RXD A 3 RXD LEDR VCC330 TXD LEDG gt UART_TXD Figure 4 16 MAX232 RS 232 chip schematic UART_RXD PIN C25 UART Receiver UART TXD PIN B25 UART Transmitter Table 4 10 RS 232 pin assignments 4 10 PS 2 Serial Port The DE2 board includes a standard PS 2 interface and a connector for a PS 2 keyboard or mouse Figure 4 17 shows the schematic of the PS 2 circuit Instructions for using a PS 2 mouse or keyboard can be found by performing an appropriate search on various educational web sites The pin assignments for the associated interface are shown in Table 4 11 VECS VOCs 8 R31 R32 2K 17 PS2 DAT R33 120 PS2DAT lt gt ps2 CLK ED AA NN LJ VECS re 9 j a n D1 D2 Go 545 BAT54S 50 jd PS2 0 1U 8 VCC33 VCC33 F d Figure 4 17 PS 2 schematic 42 INDE DAN DE2 User Manual PS2 CLK PIN D26 PS 2 Clock PS2 DAT PIN C24 PS 2 Data Table 4 11 PS 2 pin assignments 4 11 Fast Ethernet Network Controller The DE2 board provides Ethernet support via the Davicom DM9OOOA Fast Ethernet controller chip The DM9000A includes a general processor interface 16 Kbytes SRAM a media access control MAC unit and a 10 100M PHY transceiver Figure 4 18 show
47. its CD quality audio DAC circuits We use the Nios II processor to read the music data stored in the SD Card and use the Wolfson WM 8731 audio CODEC to play the music The audio CODEC is configured in the slave mode where external circuitry must provide the ADC DAC serial bit clock BCK and left right channel clock LRCK to the audio CODEC As shown in Figure 5 11 we provide an Audio DAC Controller to achieve the clock generation and the data flow control The Audio DAC Controller 1s integrated 1nto the Avalon bus architecture so that the Nios II processor can control the application 64 INDE DA DE2 User Manual During operation the Nios II processor will check if the FIFO memory of the Audio DAC Controller becomes full If the FIFO is not full the processor will read a 512 byte sector and send the data to the FIFO of the Audio DAC Controller via the Avalon bus The Audio DAC Controller uses a 48 kHz sample rate to send the data and clock signals to the audio CODEC The design also mixes the data from microphone in with line in for the Karaoke style effects Audio reout Configuration Nios Audio DAC Audio TS CPU Controller CODEC i nis Mic in ADC to DAC Figure 5 11 Block diagram of the SD music player demonstration Demonstration Setup File Locations and Instructions e Project directory DE2 SD Card Audio e Bit stream used DE2 SD Card Audio sof e Nios II Workspace DE2 SD Card Audio e Format your S
48. l process by implementing a Flash Music Player The music data is loaded into the Flash memory User Port 1 1n the Flash Controller is used to send the music data to the Audio DAC Controller and hence to the audio output jack You can implement this application as follows JB Erase the Flash memory as explained in Section 3 4 Then write a music file into the Flash memory You can use the file music wav in the directory DE2_demonstrations nusic on the DE2 System CD ROM In the DE2 Control Panel select the TOOLS tab to reach the window in Figure 3 8 IE DE2 Control Panel Open Help About FLASH SDRAM SRAM wGA PS2 amp 7 SEG LED amp LCD TOOLS SDRAM Multiplexer Host USB Port FLASH Multiplexer Asynchronous 1 SRAM Multiplexer Host USB Port Board Test Figure 3 8 TOOLS window of the DE2 Control Panel Select the Asynchronous port for the Flash Multiplexer and then click on the Configure button to activate the port You need to click the Configure button to enable the connection from the Flash Memory to the Asynchronous Port 1 of the Flash Controller indicated in Figure 3 7 Set toggle switches SW1 and SWO to OFF DOWN position and ON UP position respectively Plug your headset or a speaker into the audio output jack and you should hear the music played from the Audio DAC circuit Note that the Asynchronous Port is connected to the Audio DAC part as shown in Figure 3 7 Once you selected
49. lalalalslalala t Eha a i i i ied fed lea lem ia dn Figure 5 8 The setup for the Karaoke Machine 5 6 Ethernet Packet Sending Receiving In this demonstration we will show how to send and receive Ethernet packets using the Fast Ethernet controller on DE2 board As illustrated in Figure 5 9 we use the Nios II processor to send and receive Ethernet packets using the DM9000A Ethernet PHY MAC Controller The demonstration can be set up to use either a loop back connection from one board to itself or two DE2 boards connected together 62 INDE oY DE2 User Manual On the transmitting side the Nios II processor sends 64 byte packets every 0 5 seconds to the DM9000A After receiving the packet the DM9000A appends a four byte checksum to the packet and sends it to the Ethernet port On the receiving side the DM9000A checks every packet received to see if the destination MAC address in the packet is identical to the MAC address of the DE2 board If the packet received does have the same MAC address or 1s a broadcast packet the DM9000A will accept the packet and send an interrupt to the Nios II processor The processor will then display the packet contents in the Nios II IDE console window 64 Bytes Data ag 64 Bytes Data 4 Bytes Checksum 64 Bytes Data 4 Bytes Checksum Nios ll Interrupt Davicom CPU 4 DM9000A Read Data Ethernet 64 Bytes Data 4 Bytes Checksum a Figur
50. mages and use your own images to generate the binary data patterns that can be displayed on the VGA monitor Another image is provided in the file picture dat in the folder DE2_demonstrations pictures on the DE2 System CD ROM You can display this image as follows e Select the SRAM page of the Control Panel and load the file picture dat into the SRAM 20 DE2 User Manual e Select the TOOLS page and choose Asynchronous 1 for the SRAM multiplexer port as shown in Figure 3 10 Click on the Configure button to activate the multi port setup IE DE2 Control Panel Open Help About FLASH SDRAM SRAM PS2 amp 7 SEG LED amp LCD SDRAM Multiplexer Host USB Port FLASH Multiplexer Host USB Port SRAM Multiplexer asynchronous 1 Board Test Figure 3 10 Use the Asynchronous Port 1 to access the image data in the SRAM e The FPGA is now configured as indicated in Figure 3 11 e Select the VGA page and deselect the checkbox Default Image e The VGA monitor should display the picture dat image from the SRAM as depicted in Figure 3 12 You can turn off the cursor by deselecting the Cursor Enable checkbox Host Port User Port 1 Async 1 SDRAM SDRAM User Port 2 Async 2 Controller User Port 3 Async 3 Host Port USB Blaster User Port 1 Async 1 Flash User Port 2 Async 2 Controller Usar Port 3 Async 3 Host Port DE2 Control Panel SRAM Controller
51. me periods a b c and d for both horizontal and vertical timing Detailed information for using the ADV7123 video DAC is available in its datasheet which can be found on the manufacturer s web site and from the Datasheet folder on the DE2 System CD ROM The pin assignments between the Cyclone II FPGA and the ADV7123 are listed in Table 4 8 An example of code that drives a VGA display is described in Sections 5 2 and 5 3 38 DE2 User Manual Back porch b Front porch d Display interval HSYNC Sync a Figure 4 12 VGA horizontal timing specification DATA SVGA 60Hz 800x600 Dmm men nme Cms ma s er wa on moms Figure 4 13 VGA horizontal timing specification wow emm m om 1 www mem 5 m om 1 oe ewm www s me 9 xw wwe s mee wem s wm Figure 4 14 VGA vertical timing specification 39 DE2 User Manual VGA PIN C8 VGA Red 0 PIN F10 VGA Red 1 VGA RI 2 PIN G10 VGA Red 2 VGA R 3 PIN D9 VGA Red 3 VGA R 7 PIN H12 VGA Red 7 Table 4 8 ADV7123 pin assignments 40 DE2 User Manual 4 8 Using the 24 bit Audio CODEC The DE2 board provides high quality 24 bit audio via the Wolfson WMS 8731 audio CODEC enCOder DECoder This chip supports microphone in line in and line out ports with a sample rate adjustable from 8 kHz to 96 kH
52. n as the bit stream is downloaded into the FPGA the register values of the TV Decoder chip are used to configure the TV decoder via the 26 AV Config block which uses the I2C protocol to communicate with the TV Decoder chip Following the power on sequence the TV Decoder chip will be unstable for a time period the Lock Detector 1s responsible for detecting this instability The ITU R 656 Decoder block extracts YCrCb 4 2 2 YUV 4 2 2 video signals from the ITU R 656 data stream sent from the TV Decoder It also generates a data valid control signal indicating the valid period of data output Because the video signal from the TV Decoder is interlaced we need to perform de interlacing on the data source We used the SDRAM Frame Buffer and a field selection multiplexer MU X which is controled by the VGA controller to perform the de interlacing operation 55 JAN DE2 User Manual Internally the VGA Controller generates data request and odd even selected signals to the SDRAM Frame Buffer and filed selection multiplexer MUX The YUV422 to YUV444 block converts the selected YCrCb 4 2 2 YUV 4 2 2 video data to the YCrCb 4 4 4 YUV 4 4 4 video data format Finally the YCrCb to RGB block converts the YCrCb data into RGB output The VGA Controller block generates standard VGA sync signals HS and VGA_VS to enable the display on a VGA monitor TUR 65 B Decoder Data Valid i i i i i DLYO a
53. n the DE2 System CD ROM The most challenging part of a USB application is in the design of the software driver needed Two complete examples of USB drivers for both host and device applications can be found in Sections 5 3 and 5 4 These demonstrations provide examples of software drivers for the Nios II processor 46 INDE 5 DE2 User Manual USB A TYPE OU VCC33 OTG FSPEED H54 1 5K T OD RABEEB n2 gt Uu vCC33 H_VCCS O vCC5 12 Res 42 C39 BC91 BC92 BC93 BC94 BC95 BCL BC97 BC98 TC12 TC13 47P 0 1U 0 tU 0 1U 01U 0 1U 0 1 01U 100u av 0 1U Figure 4 21 USB ISP1362 host and device schematic 47 D V A DE2 User Manual OTG WR N PIN G1 ISP1362 Write OTG RST N PIN G5 ISP1362 Reset OTG INTO PIN B3 ISP1362 Interrupt 0 OTG_INT1 PIN C3 ISP1362 Interrupt 1 OTG_DACKO_N PIN C2 ISP1362 DMA Acknowledge 0 OTG DACK1 N PIN B2 ISP1362 DMA Acknowledge 1 OTG DREQO PIN F6 ISP1362 DMA Request 0 OTG _DREQ1 PIN E5 ISP1362 DMA Request 1 OTG FSPEED PIN F3 USB Full Speed 0 Enable Z Disable OTG_LSPEED PIN G6 USB Low Speed 0 Enable Z Disable Table 4 14 USB 15813262 pin assignments 4 15 Using IrDA The DE2 board provides a simple wireless communication media using the Agilent HSDL 3201 low power infrared transceiver The datasheet for this device 15 provided in the DatasheetNrDA folder on the DEZ System CD ROM Note that the highest transmission r
54. n to display as VGA output load music to the memory and play music via the audio DAC The feature of reading writing a byte or an entire file from to the Flash Memory allows the user to develop multimedia applications Flash Audio Player Flash Picture Viewer without worrying about how to build a Flash Memory Programmer 3 2 Controlling the LEDs 7 Segment Displays and LCD Display A simple function of the Control Panel is to allow setting the values displayed on LEDs 7 segment displays and the LCD character display In the window shown in Figure 3 2 the values to be displayed by the 7 segment displays which are named HEX7 0 can be entered into the corresponding boxes and displayed by pressing the Set button A keyboard connected to the PS 2 port can be used to type text that will be displayed on the LCD display Choosing the LED amp LCD tab leads to the window in Figure 3 4 Here you can turn the individual LEDs on by selecting them and pressing the Set button Text can be written to the LCD display by typing it in the LCD box and pressing the corresponding Set button The ability to set arbitrary values into simple display devices is not needed in typical design activities However it gives the user a simple mechanism for verifying that these devices are functioning correctly in case a malfunction is suspected Thus it can be used for troubleshooting purposes 13 DE2 User Manual IE DE2 Control Panel Open Help About FLA
55. oard to the PROG position The EPCS16 chip can now be programmed by using the Quartus II Programmer module to select a configuration bit stream file with the pof filename extension Once the programming operation is finished set the RUN PROG switch back to the RUN position and then reset the board by turning the power switch off and back on this action causes the new configuration data in the EPCS16 device to be loaded into the FPGA chip 25 JAN DE2 User Manual USB Blaster Circuit RUN PROG Quartus II AS Mode Programmer Config AS Mode JTAG Config Port Power on Config EPCS16 Serial Configuration Device Figure 4 2 The AS configuration scheme In addition to its use for JTAG and AS programming the USB Blaster port on the DE2 board can also be used to control some of the board s features remotely from a host computer Details that describe this method of using the USB Blaster port are given in Chapter 3 4 2 Using the LEDs and Switches The DE2 board provides four pushbutton switches Each of these switches is debounced using a Schmitt Trigger circuit as indicated in Figure 4 3 The four outputs called KEYO KEY3 of the Schmitt Trigger device are connected directly to the Cyclone II FPGA Each switch provides a high logic level 3 3 volts when it is not pressed and provides a low logic level O volts when depressed Since the pushbutton switches are debounced they are ap
56. propriate for use as clock or reset inputs in a circuit Pushbutton depressed Pushbutton released Before Debouncing Schmitt Trigger Debounced Figure 4 3 Switch debouncing There are also 18 toggle switches sliders on the DE2 board These switches are not debounced and are intended for use as level sensitive data inputs to a circuit Each switch is connected directly to a pin on the Cyclone II FPGA When a switch is in the DOWN position closest to the edge of the board it provides a low logic level 0 volts to the FPGA and when the switch is in the UP position it provides a high logic level 3 3 volts 26 DE2 User Manual There are 27 user controllable LEDs on the DE2 board Eighteen red LEDs are situated above the 18 toggle switches and eight green LEDs are found above the pushbutton switches the 9 green LED is in the middle of the 7 segment displays Each LED is driven directly by a pin on the Cyclone II FPGA driving its associated pin to a high logic level turns the LED on and driving the pin low turns it off A schematic diagram that shows the pushbutton and toggle switches 15 given in Figure 4 4 A schematic diagram that shows the LED circuitry appears in Figure 4 5 A list of the pin names on the Cyclone II FPGA that are connected to the toggle switches 1s given in Table 4 1 Similarly the pins used to connect to the pushbutton switches and LEDs are displayed in Tables
57. s the schematic for the Fast Ethernet interface and the associated pin assignments are listed in Table 4 12 For detailed information on how to use the DM9000A refer to its datasheet and application note which are available on the manufacturer s web site and from the Datasheet folder on the DE2 System CD ROM N VECA NH VOCX3 TK 25MHZ ELL eT eT SPEED ACT 3 __ BEAD eR M o N vCC33 R20 ENET IOAN d i3 E t id E Yan bex i3 Er x a a Lun amp TA RX n GAD E NNNN ENET CMD vVCC330 mut RD XGND GENADE a E388 TT H 5 WDO VOC T RD 58 B rkvpozs jas y c 1 WOO Tos ENET 525 Xp 5g E TE OPUSTI 1 NET DI H VEGIG Figure 4 18 Fast Ethernet schematic PIN_D17 DM9000A DATA 0 PIN_C17 DM9000A DATA 1 PIN_B18 DM9000A DATA 2 PIN A18 DM9000A DATA 3 PIN B17 DM9000A DATAI4 43 INDE 5 A DE2 User Manual ENET 17 DM9000A DATA 5 ENET DATA 6 PIN B16 DM9000A DATA 6 7 PIN B15 DM9000A DATA 7 ENET DATA 8 PIN B20 DM9000A DATA 8 ENET DATA 9 PIN A20 DM9000A DATA 9 ENET DATA 14 PIN E18 DM9000A DATA 14 ENET DATA 15 PIN D18 DM9000A DATA 15 Table 4 12 Fast Ethernet pin assignments 4 12 TV Decoder The DE2 board is equipped with an Analog Devices ADV7181 TV decoder chip The ADV7181 is an integrated video decoder that
58. the host computer a software program has to be executed on the Nios II processor to initialize the Philips ISP1362 chip Once the software program is successfully executed the host computer will identify the new device in its USB device list and ask for the associated driver the device will be identified as a Philips PDIUSBDI2 SMART Evaluation Board After completion of the driver installation on the host computer the next step is to run a software program on the host computer called JSP 1362DcUsb exe this program communicates with the DE2 board In the JSP1362DcUsb program clicking on the Add button in the window panel of the software causes the host computer to send a particular USB packet to the DE2 board the packet will be received by the Nios II processor and will increment the value of a hardware counter The value of the counter is displayed on one of the board s 7 segment displays and also on the green LEDs If the user clicks on the Clear button in the window panel of the software driver the host computer sends a different USB packet to the board which causes the Nios II processor to clear the hardware counter to zero 59 DE2 User Manual Link to Host PC Setup Package p u Philips Enumeration Information Device Port Communication Figure 5 5 Block diagram of the USB device demonstration Demonstration Setup File Locations and Instructions e Project directory DE2_NIOS_DEVICE_LED HW e Bit stream
59. triple DACs with VGA out connector e TV Decoder NTSC PAL and TV in connector e 10 100 Ethernet Controller with a connector e USB Host Slave Controller with USB type A and type B connectors e RS 232 transceiver and 9 pin connector e PS 2 mouse keyboard connector IrDA transceiver e Two 40 pin Expansion Headers with diode protection In addition to these hardware features the DE2 board has software support for standard I O interfaces and a control panel facility for accessing various components Also software is provided for a number of demonstrations that illustrate the advanced capabilities of the DE2 board In order to use the DE2 board the user has to be familiar with the Quartus II software The necessary knowledge can be acquired by reading the tutorials Getting Started with Altera s DE2 Board and Quartus II Introduction which exists in three versions based on the design entry method used namely Verilog VHDL or schematic entry These tutorials are provided in the directory DE2 tutorials on the DEZ System CD ROM that accompanies the DE2 board and can also be found on Altera s DE2 web pages 2 3 Block Diagram of the DE2 Board Figure 2 2 gives the block diagram of the DE2 board To provide maximum flexibility for the user all connections are made through the Cyclone II FPGA device Thus the user can configure the FPGA to implement any system design DE2 User Manual 50 Mhz 27 Mhz Extin USB 2 0 Host Device 1
60. used DE2 NIOS DEVICE LED sof Nios II Workspace DE2 NIOS DEVICE LEDNIW e Borland BC Software Driver DE2 NIOS DEVICE LEDNSW e Load the bit stream into FPGA e Run Nios IL IDE with HW as the workspace Click on Compile and Run e Connect the USB Device connector of the DE2 board to the host computer using a USB cable type A gt B Anew USB hardware device will be detected e Specify the location of the driver as DE2_NIOS_DEVICE_LED D12test inf Philips PDIUSBD12 SMART Evaluation Board Ignore any warning messages produced during installation e The host computer should report that a Philips PDIUSBDI2 SMART Evaluation Board is now installed e Execute the software DE2 NIOS DEVICE LED SW ISP1362DcUsb exe on the host computer Then experiment with the software by clicking on the ADD and Clear buttons Figure 5 6 illustrates the setup for this demonstration 60 DE2 User Manual D 4444444 4444 Figure 5 6 The setup for the USB paintbrush demonstration 5 5 A Karaoke Machine This demonstration uses the microphone in line in and line out ports on the DE2 board to create a Karaoke Machine application The Wolfson WM8731 audio CODEC is configured in the master mode where the audio CODEC generates AD DA serial bit clock BCK and the left right channel clock LRCK automatically As indicated in Figure 5 7 the I2C interface is used to configure the Audio CODEC The sample rate and
61. z The WM8731 is controlled by a serial I2C bus interface which is connected to pins on the Cyclone II FPGA A schematic diagram of the audio circuitry is shown in Figure 4 15 and the FPGA pin assignments are listed in Table 4 9 Detailed information for using the WM8731 codec is available in its datasheet which can be found on the manufacturer s web site and from the Datasheet folder on the DE2 System CD ROM J2 LINE IN C1 1U PHONE JACK B VCC33VCC33 O O R1 R2 wA AGND 2K 2K VA AGND AGND I2C SDAT Ji MIC IN n SCLK R7 330 22 a o i Q 2 DRES EI I v ci C3 zu0zuo DRESS W S 0x35 U1 l PHONE JACK P R8 680 4 5 10U ur Mmo Fae I aco C4 AND VCC33 1000P 47K J3 LINE OUT a A AGND AGND AGND ADCDAT ADCLRCK HPVDD LHPOUT RHPOUT PHONE JACK G 8 DACDAT DACLRCK AUD XCK TC1 AUD DACLRCK AUD ADCDAT AUD ADCLRCK 2 A VCC33 4 4 AGND AGND Figure 4 15 Audio CODEC schematic AUD_ADCLRCK PIN_C5 Audio CODEC ADC LR Clock AUD_ADCDAT PIN_B5 Audio CODEC ADC Data AUD DACLRCK PIN C6 Audio CODEC DAC LR Clock AUD DACDAT PIN A4 Audio CODEC DAC Data tio SoBe OAC Table 4 9 Audio CODEC pin assignments 41 DE2 User Manual 4 9 RS 232 Serial Port The DE2 board uses the MAX232 transceiver chip and a 9 pin D SUB connector for RS 232 communications For detailed information on how to use the transceiver refer to the datasheet which

DE2 User Manual v1.4 - La Sierra University

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