SuperHTM Family E10A-USB Emulator Additional
Contents
1. Register Name Usage Register WTCSR W Write Watchdog timer control status register WTCNT W Write Watchdog timer counter WTCSR R Read Watchdog timer control status register WTCNT R Read Watchdog timer counter e The watchdog timer operates only when the user program is executed Do not change the value of the frequency change register in the IO window or Memory window RENESAS e The internal I O registers can be accessed from the IO window However note the following when accessing the SDMR register of the bus state controller Before accessing the SDMR register specify addresses to be accessed in the I O register definition file SH7721 10 and then activate the High performance Embedded Workshop After the I O register definition file is created the MPU s specification may be changed If each I O register in the I O register definition file differs from addresses described in the hardware manual change the I O register definition file according to the description in the hardware manual The I O register definition file can be customized depending on its format Note that however the emulator does not support the bit field function e Verify In the IO window the verify function of the input value is disabled 14 Illegal Instructions If illegal instructions are executed by STEP type commands the emulator cannot go to the next program counter RENESAS 2 2 Specific Functions for the Emulator when Using the SH77212. Branch trace Supported eight branches Supported Range memory access trace Not supported Supported Software trace Not supported Supported Table 2 7 shows the type numbers that the AUD function can be used Table 2 7 Type Number and AUD Function Type Number AUD Function HS0005KCU01H Not supported HS0005KCU02H Supported 22 RENESAS AUD Trace Functions This function is operational when the AUD pin of the device is connected to the emulator Table 2 8 shows the AUD trace acquisition mode that can be set in each trace function Table 2 3 AUD Trace Acquisition Mode Type Continuous trace occurs Mode Realtime trace Description When the next branch occurs while the trace information is being output all the information may not be output The user program can be executed in realtime but some trace information will be lost Non realtime trace When the next branch occurs while the trace information is being output the CPU stops operations until the information is output The user program is not executed in realtime Trace buffer full Trace continue This function overwrites the latest trace information to store the oldest trace information Trace stop After the trace buffer becomes full the trace information is no longer acquired The user program is continuously executed 23 RENESAS To set the AUD trace acquisition mode click the Trace window with the right mouse button and select Setti
3. Condition 2 are disabled Break Condition 2 is disabled when an instruction to which a BREAKPOINT has been set is executed Accordingly do not seta BREAKPOINT to an instruction which satisfies Break Condition 2 When a Break Condition is satisfied emulation may stop after two or more instructions have been executed If a PC break address condition is set to the slot instruction after a delayed branch instruction user program execution cannot be terminated before the slot instruction execution execution stops before the branch destination instruction Break Condition 1 2 is used as the measurement range in the performance measurement function when PA 1 start point and PA 1 end point are displayed on the Action part in the Break condition sheet of the Eventpoint window This applies when the Break Condition is displayed with the BREAKCONDITION_DISPLAY command in the command line function In this case a break does not occur when Break Condition 1 2 is satisfied A break will not occur with the execution counts specified on the execution of the multi step instruction 2 2 6 Note on Setting the UBC_MODE Command In the Configuration dialog box if User is set while the UBC mode list box has been set the STEP type commands that use Break Condition 2 for implementation cannot be used 30 RENESAS 2 2 7 Performance Measurement Function The emulator supports the performance measurement function 1 Setting the performance m
4. Series In the SH7721 series a reset must be input when the emulator is activated Do not use the activation method described in section 3 11 in the SuperH Family EIOA USB Emulator User s Manual 2 2 1 Break Condition Functions In addition to BREAKPOINT functions the emulator has Break Condition functions Three types of conditions can be set under Break Condition 1 2 3 Table 2 4 lists these conditions of Break Condition 20 RENESAS Table 2 4 Types of Break Conditions Break Condition Type Address bus condition Address Description Breaks when the SH7721 address bus value or the program counter value matches the specified value Data bus condition Data Breaks when the SH7721 data bus value matches the specified value Byte word or longword can be specified as the access data size X Bus or Y Bus condition Address and data Breaks when the X Bus or Y Bus address bus or data bus matches the specified value Bus state condition Bus State There are two bus state condition settings Read Write condition Breaks when the SH7721 RD or RDWR signal level matches the specified condition Bus state condition Breaks when the operating state in an SH7721 bus cycle matches the specified condition Types of buses that can be specified are listed below e L bus CPU ALL Indicates an instruction fetch and data access including a hit to the cache memory e L bus CPU Data Indicates a data access
5. The window trace function is also supported for acquiring memory access in the specified range memory access address or memory access data by tracing 2 14 pin type without AUD function The AUD trace function cannot be used because only the H UDI function is supported For tracing only the internal trace function is supported Since the 14 pin type connector is smaller than the 36 pin type 1 2 5 the area where the connector is installed on the user system can be reduced RENESAS 1 3 Installing the H UDI Port Connector on the User System Table 1 3 shows the recommended H UDI port connectors for the emulator Table 1 3 Recommended H UDI Port Connectors Connector Type Number Manufacturer Specifications 36 pin connector DX10M 36S Hirose Electric Co Ltd Screw type DX10M 36SE Lock pin type DX10G1M 36SE 14 pin connector 2514 6002 Minnesota Mining amp 14 pin straight type Manufacturing Ltd Note When designing the 36 pin connector layout on the user board do not connect any components under the H UDI connector When designing the 14 pin connector layout on the user board do not place any components within 3 mm of the H UDI port connector 1 4 Pin Assignments of the H UDI Port Connector Figures 1 1 and 1 2 show the pin assignments of the 36 pin and 14 pin H UDI port connectors respectively Note Note that the pin number assignments of the H UDI port connector shown on the following pages differ from those of th
6. UDI Port Connector 14 Pins RENESAS 1 5 1 5 1 Recommended Circuit between the H UDI Port Connector and the MPU Recommended Circuit 36 Pin Type Figure 1 3 shows a recommended circuit for connection between the H UDI and AUD port connectors 36 pins and the MPU when the emulator is in use Figure 1 4 shows a circuit for connection when UVCC is not connected Notes 1 Do not connect anything to the N C pins of the H UDI port connector Ze The ASEMDO pin must be 0 when the emulator is connected and 1 when the emulator is not connected respectively 1 When the emulator is used ASEMDO 0 ASE mode 2 When the emulator is not used ASEMDO 1 normal mode Figures 1 3 and 1 4 show examples of circuits that allow the ASEMDO pin to be GND 0 whenever the emulator is connected by using the user system interface cable When the ASEMDO pin is changed by switches etc ground pin 22 Do not connect this pin to the ASEMDO pin When a network resistance is used for pull up it may be affected by a noise Separate TCK from other resistances The pattern between the H UDI port connector and the MPU must be as short as possible Do not connect the signal lines to other components on the board When the power supply of the user system is turned off supplying VccQ of the user system to the UVCC pin reduces the leakage current from the emulator to the user system A level shifter that is activated by the internal power sup
7. are only valid during emulation started with clicking the GO or STEP type button If these signals are enabled on the user system in command input wait state they are not sent to the SH7721 Note Do not break the user program when the RESETP BREQ or WAIT signal is being low 5 A TIMEOUT error will occur If the WAIT or BREQ signal is fixed to low during break a TIMEOUT error will occur at memory access Direct Memory Access Controller DMAC The DMAC operates even when the emulator is used When a data transfer request is generated the DMAC executes DMA transfer Memory Access during User Program Execution When a memory is accessed from the memory window etc during user program execution the user program is resumed after it has stopped in the emulator to access the memory Therefore realtime emulation cannot be performed The stopping time of the user program is as follows Environment Host computer 800 MHz Pentium ID SH7721 60 MHz CPU clock JTAG clock 10 MHz TCK clock When a one byte memory is read from the command line window the stopping time will be about 45 ms Memory Access during User Program Break The emulator can download the program for the flash memory area refer to section 6 22 Download Function to the Flash Memory Area in the SuperH Family EIOA USB Emulator User s Manual Other memory write operations are enabled for the RAM area Therefore an Operation such as memory write or BREAK
8. is not used refer to the hardware manual of the related MPU RENESAS When the circuit is connected as shown in figure 1 5 the switches of the emulator are set as SW2 1 and SW3 1 For details refer to section 3 8 Setting the DIP Switches in the SuperH Family El0A USB Emulator User s Manual VccQ 3 3 V I O power supply Pulled up at 4 7 kQ or more all VccQ VecQ VccQ VccQ VccQ VccQ H UDI port connector 14 pin type SH7721 User system Figure 1 5 Recommended Circuit for Connection between the H UDI Port Connector and MPU when the Emulator is in Use 14 Pin Type UVCC Connected 12 RENESAS When the circuit is connected as shown in figure 1 6 the switches of the emulator are set as SW2 0 and SW3 1 For details refer to section 3 8 Setting the DIP Switches in the SuperH Family El0A USB Emulator User s Manual VccQ 3 3 V I O power supply Pulled up at 4 7 kQ or more all VecQ VccQ VccQ VccQ VccQ H UDI port connector 14 pin type SH7721 TCK TRST TDO ASEBRKAK TMS User system Figure 1 6 Circuit for Connection between the H UDI Port Connector and MPU when the Emulator is in Use 14 Pin Type UVCC Not Connected Note When UVCC is not connected and the user system is turned off note that the leakage current flows from the emulator to the user system 13 RENESAS RENESAS Section 2 Software Specifications when Using the SH7721 2 1 Differences between the SH7721 and
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10. the Emulator Series 1 When the emulator system is initiated it initializes the general registers and part of the control registers as shown in table 2 1 The initial values of the actual SH7721 registers are undefined When the emulator is initiated from the workspace a value to be entered is saved in a session Table 2 1 Register Initial Values at Emulator Link Up Register Emulator at Link Up RO to R14 H 00000000 R15 SP H A0000000 RO_BANK to R7_BANK H 00000000 PC H A0000000 SR H 700000F0 GBR H 00000000 VBR H 00000000 MACH H 00000000 MACL H 00000000 PR H 00000000 SPC H 00000000 SSR H 000000FO RS H 00000000 RE H 00000000 MOD H 00000000 AOG A1G H 00000000 AO A1 H 00000000 XO X1 H 00000000 Yo Y1 H 00000000 MO M1 H 00000000 DSR H 00000000 2 The emulator uses the H UDI do not access the H UDI RENESAS 3 Low Power States Sleep Software Standby and Module Standby For low power consumption the SH7721 has sleep software standby and module standby States The sleep software standby and module standby states are switched using the SLEEP instruction When the emulator is used only the sleep state can be cleared with either the normal clearing function or with the STOP button and a break will occur Note The memory must not be accessed or modified in low power state using the SLEEP 4 instruction Reset Signals The SH7721 reset signals
11. to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges Although Renesas endeavors to improve the quality and reliability of its products IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Please be sure to implement safety measures to guard against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other applicable measures Among others since the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed the risk of accident such as swallowing by infants and small children is very high You should implement safety measures so that Renesas products may not be easily detached from your products Renesas shall have no liability for damages arising out of such detachme
12. 00 dd 3 Pin 1 mark 1 27 M2 6 x 0 45 21 59 37 61 43 51 mM Pattern inhibited area H UDI port connector top view H UDI port connector front view Figure 1 1 Pin Assignments of the H UDI Port Connector 36 Pins RENESAS Input SH7721 Pin No Signal Output BP 256H BP 256C Note 1 TCK Input T18 T18 2 TRST Input R19 R18 3 TDO Output U20 W20 4 ASEBRKAK 2 Output T20 V18 5 TMS Input T17 U20 6 TDI Input U18 T21 ES RESETP 2 Output V18 V17 User reset 8 N C 9 GND 5 11 UVCC 4 Output 10 12 GND and 13 14 GND 3 Output Notes 1 Input to or output from the user system 2 The slash means that the signal is active low 3 The emulator monitors the GND signal of the user system and detects whether or not the user system is connected 4 If the VccQ pin is not connected to the UVCC the I O voltage of the user system interface will be fixed to 3 3 V 5 The ASEMDO pin must be O when the emulator is connected and 1 when the emulator is not connected respectively 1 When the emulator is used ASEMDO 0 ASE mode 2 When the emulator is not used ASEMDO 1 normal mode To allow the ASEMDO pin to be GND by connecting the user system interface cable connect pin 9 directly to the ASEMDO pin Do not ground the pin Pin 1 mark H UDI port connector top view H UDI port connector top view a Pin 1 mark Unit mm Figure 1 2 Pin Assignments of the H
13. 32 One of the following ranges can be specified This depends on the item selected for Mode in the Performance Analysis dialog box 1 From the start to the end of the user program execution When Normal Break is selected for Mode 2 From the satisfaction of the condition set in Break Condition 1 to the satisfaction of the condition set in Break Condition 2 When Break condition 1 gt 2 is selected for Mode 3 From the satisfaction of the condition set in Break Condition 2 to the satisfaction of the condition set in Break Condition 1 When Break condition 2 gt 1 is selected for Mode In the second and third ranges PA 1 start point and PA 1 end point are displayed on the Action part in the Break condition sheet of the Eventpoint window For measurement tolerance The measured value includes tolerance Tolerance will be generated before or after a break For details see table 2 11 RENESAS Notes 1 When the second and third ranges are specified execute the user program after the measurement start condition is set to Break Condition 1 or Break Condition 2 and the measurement end condition to Break Condition 2 or Break Condition 1 2 Step operation is not possible when Break condition 1 gt 2 or Break condition 2 gt 1 is selected for the PERFORMANCE_SET command or in Mode of the Performance Analysis dialog box 3 When Break condition 1 gt 2 or Break condition 2 gt 1 is selected in Mode of the
14. I bus must be selected 2 Address setting when X Y bus is selected To trace both the X Y bus when the X Y bus is accessed at the same time the X bus condition must be set in channel A and the Y bus condition must be set in channel B 26 RENESAS c Software Trace Function Note This function can be supported with SHC C compiler manufactured by Renesas Technology Corp including OEM and bundle products V7 0 or later When a specific instruction is executed the PC value at execution and the contents of one general register are acquired by trace Describe the Trace x function x is a variable name to be compiled and linked beforehand For details refer to the SHC manual When the load module is downloaded on the target system and is executed while a software trace function is valid the PC value that has executed the Trace x function the general register value for x and the source lines are displayed To activate the software trace function select the Software trace check box in the AUD function group box of the Trace mode page Notes on AUD Trace 1 When the trace display is performed during user program execution the mnemonics operands or source is not displayed The AUD trace function outputs the differences between newly output branch source addresses and previously output branch source addresses The window trace function outputs the differences between newly output addresses and previously output addresse
15. POINT should be set only for the RAM area RENESAS 8 Cache Operation during User Program Break When cache is enabled the emulator accesses the memory by the following methods e At memory write Writes through the cache then writes to the memory e At memory read Does not change the cache write mode that has been set Therefore when memory read or write is performed during user program break the cache state will be changed 9 Ports JandL The AUD and H UDI pins are multiplexed as shown in table 2 2 Table 2 2 Multiplexed Functions Port Function 1 Function 2 J PTJ6 input output port AUDCK AUD J PTJ5 input output port ASEBRKAK H UDI J PTJ4 input output port AUDATAS AUD J PTJ3 input output port AUDATA2 AUD J PTJ2 input output port AUDATA1 AUD J PTJ1 input output port AUDATAO AUD J PTJO input output port AUDSYNC AUD L PTL7 input output port TRST H UDI L PTL6 input output port TMS H UDI L PTL5 input output port TDO H UDI L PTL4 input output port TDI H UDI L PTL3 input output port TCK H UDI Notes 1 Function 1 cannot be used when the emulator is used 2 When the AUD trace is enabled the emulator changes settings so that function 2 is forcibly used 10 UBC When User is specified in the UBC mode list box in the Configuration dialog box the UBC can be used in the user program Do no
16. Performance Analysis dialog box specify one or more items for measurement When there is no item the error message Measurement item does not have specification Please set up a measurement item will be displayed When no item is specified for the PERFORMANCE_SET command the settings of Break condition 1 gt 2 or Break condition 2 gt 1 will be an error c Measurement item Items are measured with Channel 1 to 4 in the Performance Analysis dialog box Maximum four conditions can be specified at the same time Table 2 10 shows the measurement items Options in table 2 10 are parameters for lt mode gt of the PERFORMANCE_SET command They are displayed for CONDITION in the Performance Analysis window 33 RENESAS Table 2 10 Measurement Item Selected Name Option Disabled None Elapsed time AC Number of execution states VS Branch instruction counts BT Number of execution instructions DSP instruction execution counts DI Devices incorporating the DSP function can only be measured Instruction data conflict cycle MAC Other conflict cycles than instruction data OC Exception interrupt counts EA Data TLB miss cycle MTS Devices incorporating the MMU function can only be measured Instruction TLB miss cycle ITS Devices incorporating the MMU function can only be measured Interrupt counts INT Number of BL 1 instructions BL1 Number of MD 1 instru
17. REJ10J1750 0100 Everywhere you imagine y 2 E N ESAS SuperH Family E10A USB Emulator Additional Document for User s Manual Supplementary Information on Using the SH7721 Series Renesas Microcomputer Development Environment System SuperH Family SH7700 Series E10A USB for SH7721 Series HS7721KCU01HE Rev 1 00 Renesas Technology Revision Date Nov 19 2007 www renesas com Notes regarding these materials This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document including but not limited to product data diagrams charts programs algorithms and application circuit examples You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use When exporting the products or technology described herein you should follow the applicable export c
18. aces and displays the branch instructions The branch source address and branch destination address for the eight latest branch instructions are displayed See figure 2 1 Trace mode Page Notes 1 If an interrupt is generated at the program execution start or end including a step operation the emulator address may be acquired In such a case the following message will be displayed Ignore this address because it is not a user program address 2 Ifa completion type exception occurs during exception branch acquisition the next address to the address in which an exception occurs is acquired 3 Trace information cannot be acquired for the following branch instructions e The BF and BT instructions whose displacement value is 0 e Branch to H A0000000 by reset 4 The internal trace acquisition is not available when User is selected in the UBC mode list box of the Configuration dialog box In this case close the Trace window 2 2 3 Notes on Using the JTAG H UDI Clock TCK and AUD Clock AUDCK Set the JTAG clock TCK frequency to lower than the frequency of the SH7721 peripheral module clock CKP Set the AUD clock AUDCK frequency to 50 MHz or lower If the frequency is higher than 50 MHz the emulator will not operate normally 2 2 4 Notes on Setting the Breakpoint Dialog Box 1 When an odd address is set the next lowest even address is used 28 A BREAKPOINT is accomplished by replacing instructions of
19. by the CPU including a hit to the cache memory e bus CPU DMA Indicates a CPU cycle when the cache memory is not hit and a data access by the DMA Internal I O break condition Breaks when the SH7721 accesses the internal I O LDTLB instruction break condition Breaks when the SH7721 executes the LDTLB instruction Count Breaks when the conditions set are satisfied the specified number of times Note When U RAM or X Y RAM is accessed from the PO space the I bus must be selected and when accessed from the P2 space the L bus must be selected When cache fill cycle is acquired the I bus must be selected 21 RENESAS Table 2 5 lists the combinations of conditions that can be set under Break Condition 1 2 3 Table 2 5 Dialog Boxes for Setting Break Conditions Type Bus Address Data State Bus Bus ASID Condition Count Internal LDTLB Condition Condition Condition Bus Condition I O Instruction Dialog Box Address Data ASID Status Count Break Break Break Condition 1 O O O O O X X dialog box Break Condition 2 O X O O X X X dialog box Break Condition 3 X X X X X O O dialog box Notes 1 O Can be set in the dialog box X Cannot be set in the dialog box 2 For Break Condition 2 X bus and Y bus conditions cannot be specified 2 2 2 Trace Functions The emulator supports the trace functions listed in table 2 6 Table 2 6 Trace Functions Function Internal Trace AUD Trace
20. ctions MD1 Instruction cache miss counts IC Data cache miss counts DC Instruction fetch stall IF Data access stall DA Instruction cache miss stall ICS Data cache miss stall DCS Cacheable access stall CS X Y RAM access stall XYS Devices incorporating the X Y memory can only be measured URAM access stall US Devices incorporating the U memory can only be measured Instruction data access stall cycle MA Other access cycles than instruction data NMA Non cacheable area access cycle NCC Non cacheable area instruction access cycle NCI 34 RENESAS Table 2 10 Measurement Item cont Selected Name Option Non cacheable area data access cycle NCD Cacheable area access cycle CC Cacheable area instruction access cycle CIC Cacheable area data access cycle CDC Access counts other than instruction data NAM Non cacheable area access counts NCN Non cacheable area instruction access counts NCIN Non cacheable area data access counts NCDN Cacheable area access counts CN Cacheable area instruction access counts CIN Cacheable area data access counts CDN Each measurement condition is also counted when conditions in table 2 11 are generated Table 2 11 Performance Measurement Conditions to be Counted Measurement Condition Notes No caching due to the Counted for accessing the cacheable area settings of TLB cacheable bit Cache on counting Accessing the non cacheable area is coun
21. e connector manufacturer RENESAS Inpuy _SH7721 PinNo Inpu __SH7721 Pin No _ Output BP 256H BP 256C Note Signal Output BP 256H BP 256C Note Output P19 P18 TMS Input T17 U20 GND Output TRST Input GND Output TDI Input GND _ Output TDO Output GND ojo xjoja BI w r Output ASEBRKAK Output GND o N Output UVCC Output GND N wo RESETP Output User reset GND GND Output GND GND gt gt a o S TCK Input NC 18 GND GND Notes 1 Input to or output from the user system 2 The slash means that the signal is active low 3 The emulator monitors the GND signal of the user system and detects whether or not the user system is connected 4 If the VccQ pin is not connected to the UVCC the I O voltage of the user system interface will be fixed to 3 3 V 5 The ASEMDO pin must be O when the emulator is connected and 1 when the emulator is not connected respectively 1 When the emulator is used ASEMDO 0 ASE mode 2 When the emulator is not used ASEMDO 1 normal mode To allow the ASEMDO pin to be GND by connecting the user system interface cable connect pin 22 directly to the ASEMDO pin Do not ground the pin Edge of the board H UDI port connector top view connected to the connector v 90 721 36 00000000 07 000000000 0000000
22. easurement conditions To set the performance measurement conditions use the Performance Analysis dialog box and the PERFORMANCE_SET command When any line on the Performance Analysis window is clicked with the right mouse button the popup menu is displayed and the Performance Analysis dialog box is displayed by selecting Setting Note For the command line syntax refer to the online help a Specifying the measurement start end conditions The measurement start end conditions are specified in the Mode drop down list box in the Performance Analysis dialog box Three conditions can be set as shown in table 2 9 Table 2 9 Conditions Specified in Mode Item Description Normal break Measurement is started by executing a program and ended when a break condition is satisfied Break Condition 1 gt 2 Measurement is started from the satisfaction of the condition set in Break Condition 1 to the satisfaction of the condition set in Break Condition 2 Break Condition 2 gt 1 Measurement is started from the satisfaction of the condition set in Break Condition 2 to the satisfaction of the condition set in Break Condition 1 RENESAS 31 Perfomance Analysis Condition Mode Normal Break ss lt sC Channel 1 Elapsed time Channel 2 Number of execution states tts Channel 3 Branch instruction counts ef Channel 4 Disabled O XY Figure 2 4 Performance Analysis Dialog Box b Measurement range
23. ected RENESAS When the circuit is connected as shown in figure 1 4 the switches of the emulator are set as SW2 0 and SW3 1 For details refer to section 3 8 Setting the DIP Switches in the SuperH Family El0A USB Emulator User s Manual VccQ 3 3 V I O power supply Pulled up at 4 7 kQ or more all VecQ VecQ VecQ VccQ H UDI port connector 36 pin type AUDATA2 AUDATA3 User system SH7721 AUDATAO AUDATA1 AUDATA2 AUDATA3 AUDSYNC TCK TMS TAST TD TDO ASEBRKAK RESETP ASEMDO Figure 1 4 Circuit for Connection between the H UDI Port Connector and MPU when the Emulator is in Use 36 Pin Type UVCC Not Connected RENESAS Note When UVCC is not connected and the user system is turned off note that the leakage current flows from the emulator to the user system RENESAS 1 5 2 Recommended Circuit 14 Pin Type Figure 1 5 shows a recommended circuit for connection between the H UDI and AUD port connectors 14 pins and the MPU when the emulator is in use Figure 1 6 shows a circuit for connection when UVCC is not connected Notes 1 Do not connect anything to the N C pins of the H UDI port connector 2 The ASEMDO pin must be 0 when the emulator is connected and 1 when the emulator is not connected respectively 1 When the emulator is used ASEMDO 0 ASE mode 2 When the emulator is not used ASEMDO 1 normal mode Figures 1 5 and 1 6 show examples of circui
24. gram execution After setting the MMU is returned to the original state When an ASID value is specified the BREAKPOINT is set to the virtual address corresponding to the ASID value The emulator sets the BREAKPOINT after rewriting the ASID value to the specified value and returns the ASID value to its original value after setting When no ASID value is specified the BREAKPOINT is set to a virtual address corresponding to the ASID value at command input 12 An address physical address to which a BREAKPOINT is set is determined when the BREAKPOINT is set Accordingly even 1f the VP_MAP table is modified after BREAKPOINT setting the BREAKPOINT address remains unchanged When a 1 jean 29 RENESAS 13 BREAKPOINT is satisfied with the modified address in the VP_MAP table the cause of termination displayed in the status bar and the Output window is ILLEGAL INSTRUCTION not BREAKPOINT If an address of a BREAKPOINT cannot be correctly set in the ROM or flash memory area a mark will be displayed in the BP area of the address on the Source or Disassembly window by refreshing the Memory window etc after Go execution However no break will occur at this address When the program halts with the break condition the mark disappears 2 2 5 Notes on Setting the Break Condition Dialog Box and the BREAKCONDITION_ SET Command When Go to cursor Step In Step Over or Step Out is selected the settings of Break
25. le applications Renesas products are not designed manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems or equipment or systems for transportation and traffic healthcare combustion control aerospace and aeronautics nuclear power or undersea communication transmission If you are considering the use of our products for such purposes please contact a Renesas sales office beforehand Renesas shall have no liability for damages arising out of the uses set forth above Notwithstanding the preceding paragraph you should not use Renesas products for the purposes listed below 1 artificial life support devices or systems 2 surgical implantations 3 healthcare intervention e g excision administration of medication etc 4 any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp its affiliated companies and their officers directors and employees against any and all damages arising out of such applications You should use the products described herein within the range specified by Renesas especially with respect
26. lected in the Memory area group box in the General page of the Configuration dialog box aBREAKPOINT is set to a physical address or a virtual address according to the SH7721 MMU status during command input when the VPMAP_SET command setting is disabled The ASID value of the SH7721 PTEH register during command input is used When VPMAP_SET command setting is enabled a BREAKPOINT is set to a physical address into which address translation is made according to the VP_MAP table However for addresses out of the range of the VP_MAP table the address to which a BREAKPOINT is set depends on the SH7721 MMU status during command input Even when the VP_MAP table is modified after BREAKPOINT setting the address translated when the BREAKPOINT is set valid 10 When the Physical option is selected in the Memory area group box in the General page of the Configuration dialog box a BREAKPOINT is set to a physical address A BREAKPOINT is set after disabling the SH7721 MMU upon program execution After setting the MMU is returned to the original state When a break occurs at the corresponding virtual address the cause of termination displayed in the status bar and the Output window is ILLEGAL INSTRUCTION not BREAKPOINT When the Virtual option is selected in the Memory area group box in the General page of the Configuration dialog box a BREAKPOINT is set to a virtual address A BREAKPOINT is set after enabling the SH7721 MMU upon pro
27. nd B The read write or read write cycle can be selected as the bus cycle for trace acquisition Setting Method 1 Select the Channel A and Channel B check boxes in the AUD function group box of the Trace mode page Each channel will become valid 11 Open the Window trace page and specify the bus cycle and memory range that are to be set for each channel 25 RENESAS Acquisition Trace mode Window trace AUD Branch trace Channel A Read Write C Read Write Read Write Start address Ho End address Ho Bus state e L bus bus Y bus I bus Channel B Read Write C Read C Write Read Write Start address Ho End address Ho Bus state e L bus Cobus Y bus Fbus ac Figure 2 3 Window trace Page Notes 1 When the L bus or I bus radio button is selected the following bus cycles will be traced e L bus A bus cycle generated by the CPU is acquired A bus cycle is also acquired when the cache has been hit e I bus A bus cycle generated by the CPU or DMA is acquired A bus cycle is not acquired when the cache has been hit The address information acquired by the I bus is 28 bits and the upper 4 bits are displayed as The source cannot be displayed in the Trace window When X Y RAM is accessed from the PO space the I bus must be selected and when accessed from the P2 space the L bus must be selected When a cache fill cycle is acquired
28. ng from the pop up menu to display the Acquisition dialog box The AUD trace acquisition mode can be set in the AUD model or AUD mode2 group box in the Trace mode page of the Acquisition dialog box Acquisition Trace mode Window trace AUD Branch trace Trace type AUD function IV Branch trace Y Window trace Y Channel A Channel B Software trace C Internal trace AUD mode AUD model Realtime trace Non realtime trace AUD mode2 Trace continue Trace stop AUD trace display range Start pointer 0 255 End pointer po Figure 2 1 Trace mode Page When the AUD trace function is used select the AUD function radio button in the Trace type group box of the Trace mode page 24 RENESAS a Branch Trace Function The branch source and destination addresses and their source lines are displayed Branch trace can be acquired by selecting the Branch trace check box in the AUD function group box of the Trace mode page The branch type can be selected in the AUD Branch trace page Acquisition Trace mode Window trace AUD Branch trace IV Acquire subroutine branch instruction trace IV Acquire exception branch instruction trace Cancel Figure 2 2 AUD Branch trace Page b Window Trace Function Memory access in the specified range can be acquired by trace Two memory ranges can be specified for channels A a
29. nt This document may not be reproduced or duplicated in any form in whole or in part without prior written approval from Renesas Please contact a Renesas sales office if you have any questions regarding the information contained in this document Renesas semiconductor products or if you have any other inquiries Contents Section 1 Connecting the Emulator with the User System 1 1 1 Components of the Emulator oonnonncnnonnnonnnoncnnncnnnconnnonnnnnonnonononn cnn c cnn nono crac ioiei ariii 1 1 2 Connecting the Emulator with the User System oooncnnnninnnonnnonnnononononancnn conan nano nnnonanonn conos 3 1 3 Installing the H UDI Port Connector on the User System ooooncnnonnnoninonononcnnnnancnanonanonnncnos 4 1 4 Pin Assignments of the H UDI Port Connector oocccoconocnnonononcnnnconnnononononncnnncnnn nono nono nenonnos 4 1 5 Recommended Circuit between the H UDI Port Connector and the MPU 7 1 5 1 Recommended Circuit 36 Pin Type ooooonccnnccnonononcnnncnnnconcnonananono nono nona nana nnnncnnnons 7 1 5 2 Recommended Circuit 14 Pin Type ooooocnnnnnonononononcnononenonenono nono cono nonncnnncnnncnnnos 11 Section 2 Software Specifications when Using the SH7721 Series 15 2 1 Differences between the SH7721 and the Emulator ooonnnnnnnnnnnnonnnonnnononononncnnncnnccancrnnonnss 15 2 2 Specific Functions for the Emulator when Using the SH7721 Series eee 20 2 2 1 Break Condition Func
30. ontrol laws and regulations and procedures required by such laws and regulations All information included in this document such as product data diagrams charts programs algorithms and application circuit examples is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas products listed in this document please confirm the latest product information with a Renesas sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website http www renesas com Renesas has used reasonable care in compiling the information included in this document but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document When using or otherwise relying on the information in this document you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application Renesas makes no representations warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products With the exception of products specified by Renesas as suitable for automobi
31. ply or user power supply changed by the switch is installed in the interface circuit of the emulator If the user power is supplied to the UVCC pin the level shifter is not activated as long as no user power is supplied When the power supply of the user system is turned off no current flows from the user interface The I O voltage level of the user system interface can be the same as that of the VccQ To operate the emulator with low voltage lower than 3 3 V the VccQ must be supplied to the UVCC pin Make the emulator s switch settings so that the VccQ will be supplied SW2 1 and SW3 1 as shown in figure 1 3 The resistance values shown in the figures are recommended For the pin processing in cases where the emulator is not used refer to the hardware manual of the related MPU RENESAS When the circuit is connected as shown in figure 1 3 the switches of the emulator are set as SW2 1 and SW3 1 For details refer to section 3 8 Setting the DIP Switches in the SuperH Family El0A USB Emulator User s Manual VecQ 3 3 V I O power supply Pulled up at 4 7 kQ or more all VccQ VecQ VccQ VccQ VccQ H UDI port connector 36 pin type SH7721 AUDCK AUDATAO AUDATA1 AUDATA2 AUDATA3 E A 7 lu AUDSYNC N C N C ASEBRKAK UVCC RESET N C User system Figure 1 3 Recommended Circuit for Connection between the H UDI Port Connector and MPU when the Emulator is in Use 36 Pin Type UVCC Conn
32. s If the previous branch source address is the same as the upper 16 bits the lower 16 bits are output If it matches the upper 24 bits the lower 8 bits are output If it matches the upper 28 bits the lower 4 bits are output The emulator regenerates the 32 bit address from these differences and displays it in the Trace window If the emulator cannot display the 32 bit address it displays the difference from the previously displayed 32 bit address If the 32 bit address cannot be displayed the source line is not displayed In the emulator when multiple loops are performed to reduce the number of AUD trace displays only the IP counts up In the emulator the maximum number of trace displays is 65534 lines 32767 branches However the maximum number of trace displays differs according to the AUD trace information to be output Therefore the above pointers cannot be always acquired The AUD trace acquisition is not available when User is selected in the UBC mode list box of the Configuration dialog box In this case close the Trace window Do not use the AUD full trace mode for the VIO function If a completion type exception occurs during exception branch acquisition the next address to the address in which an exception occurs is acquired 27 RENESAS Internal Trace Function This function is activated by selecting the Internal trace radio button in the Trace type group box of the Trace mode page This function tr
33. t 2 796 3115 Fax lt 82 gt 2 796 2145 Renesas Technology Malaysia Sdn Bhd Unit 906 Block B Menara Amcorp Amcorp Trade Centre No 18 Jalan Persiaran Barat 46050 Petaling Jaya Selangor Darul Ehsan Malaysia Tel lt 603 gt 7955 9390 Fax lt 603 gt 7955 9510 Colophon 6 0 SuperH Family E10A USB Emulator Additional Document for User s Manual Supplementary Information on Using the SH7721 Series ENESAS RenesasTechnology Corp 2 6 2 Ote machi Chiyoda ku Tokyo 100 0004 Japan
34. t use the UBC in the user program because it is used by the emulator when EML is specified in the UBC mode list box in the Configuration dialog box RENESAS 11 Memory Access during Break In the enabled MMU when a memory is accessed and a TLB error occurs during break it can be selected whether the TLB exception is controlled or the program jumps to the user exception handler in TLB Mode in the Configuration dialog box When TLB miss exception is enable is selected a Communication Timeout error will occur if the TLB exception handler does not operate correctly When TLB miss exception is disable is selected the program does not jump to the TLB exception handler even if a TLB exception occurs Therefore if the TLB exception handler does not operate correctly aCommunication Timeout error will not occur but the memory contents may not be correctly displayed 12 Loading Sessions Information in JTAG clock of the Configuration dialog box cannot be recovered by loading sessions Thus the TCK value will be as follows e When HS0005KCU01H or HS0005KCU02H is used TCK 5 MHz 13 IO Window e Display and modification Do not change values of the User Break Controller because it is used by the emulator when EML is specified in the UBC mode list box in the Configuration dialog box For each watchdog timer register there are two registers to be separately used for write and read operations Table 2 3 Watchdog Timer Register
35. ted less than the actual number of cycles and counts Accessing the cacheable X Y RAM and U RAM areas is counted more than the actual number of cycles and counts Branch count The counter value is incremented by 2 This means that two cycles are valid for one branch Notes 1 In the non realtime trace mode of the AUD trace normal counting cannot be performed because the generation state of the stall or the execution cycle is changed 2 Since the clock source of the counter is the CPU clock counting also stops when the clock halts in the sleep mode 2 Displaying the measured result The measured result is displayed in the Performance Analysis window or the PERFORMANCE_ANALYSIS command with hexadecimal 32 bits 35 RENESAS Note Ifa performance counter overflows as a result of measurement will be displayed 3 Initializing the measured result To initialize the measured result select Initialize from the popup menu in the Performance Analysis window or specify INIT with the PERFORMANCE_ANALYSIS command 36 RENESAS SuperH Family E10A USB Emulator Additional Document for User s Manual Supplementary Information on Using the SH7721 Series Publication Date Rev 1 00 November 19 2007 Published by Sales Strategic Planning Div Renesas Technology Corp Edited by Customer Support Department Global Strategic Communication Div Renesas Solutions Corp 2007 Renesas Technology Corp All
36. the specified address Accordingly 1t can be set only to the internal RAM area However a BREAKPOINT cannot be set to the following addresses e An area other than CSO to CS6 and the internal RAM e An instruction in which Break Condition 2 is satisfied e A slot instruction of a delayed branch instruction e An area that can be only read by MMU During step operation BREAKPOINTs are disabled Conditions set at Break Condition 2 are disabled when an instruction to which a BREAKPOINT has been set is executed Do not set a BREAKPOINT to an instruction in which Break Condition 2 is satisfied RENESAS 5 When execution resumes from the address where aBREAKPOINT is specified single step operation is performed at the address before execution resumes Therefore realtime operation cannot be performed 6 When a BREAKPOINT is set to the slot instruction of a delayed branch instruction the PC value becomes an illegal value Accordingly do not set a BREAKPOINT to the slot instruction of a delayed branch instruction 7 When a BREAKPOINT is set to the cacheable area the cache block containing the BREAKPOINT address is filled immediately before and after user program execution 8 Note on DSP repeat loop A BREAKPOINT is equal to a branch instruction In some DSP repeat loops branch instructions cannot be set For these cases do not set BREAKPOINTs Refer to the hardware manual of the target MPU for details 9 When the Normal option is se
37. tions ocoococcnonnnonononononononcnnncnnccnno nono nono rnnonnncnnn cnn cnn cnn conan cnn 20 2 2 2 Trace Functions tia ansen Benin 22 2 2 3 Notes on Using the JTAG H UDI Clock TCK and AUD Clock AUDCK 28 2 2 4 Notes on Setting the Breakpoint Dialog Box oooonnccnnnnnnnnoninoccnoncnnnnannnananancnnnos 28 2 2 5 Notes on Setting the Break Condition Dialog Box and the BREAKCONDITION_ SET Command eccoccccnccnccnococonononnnoncnncnnonononcnnncnncnncnnos 30 2 2 6 Note on Setting the UBC_MODE Command ursssssssesssnessnnensennnsnnensnnennnnn 30 2 2 7 Performance Measurement Function zuesssessnesnnennnennennnennnennnnnnnnnnnnnnnnnnnnnnnannn 31 RENESAS ENESAS Section 1 Connecting the Emulator with the User System 1 1 Components of the Emulator The E10A USB emulator supports the SH7721 series Table 1 1 lists the components of the emulator RENESAS Table 1 1 Components of the Emulator Classi Quan fication Component Appearance tity Remarks Hard Emulator box HS0005KCU01H ware Depth 65 0 mm Width 97 0 mm Height 20 0 mm Mass 72 9 g or HS0005KCU02H Depth 65 0 mm Width 97 0 mm Height 20 0 mm Mass 73 7 g User system interface 1 14 pin type cable Length 20 cm Mass 33 1 g User system interface 1 36 pin type cable Length 20 cm Mass 49 2 g only for HS0005KCUO2H USB cable 1 Length 150 cm Mass 50 6 g Soft SH7721 Series E10A 1 HS0005KCUO01SR ware USB emulator se
38. ts that allow the ASEMDO pin to be GND 0 whenever the emulator is connected by using the user system interface cable When the ASEMDO pin is changed by switches etc ground pin 9 Do not connect this pin to the ASEMDO pin When a network resistance is used for pull up it may be affected by a noise Separate TCK from other resistances The pattern between the H UDI port connector and the MPU must be as short as possible Do not connect the signal lines to other components on the board When the power supply of the user system is turned off supplying VccQ of the user system to the UVCC pin reduces the leakage current from the emulator to the user system A level shifter that is activated by the internal power supply or user power supply changed by the switch is installed in the interface circuit of the emulator If the user power is supplied to the UVCC pin the level shifter is not activated as long as no user power is supplied When the power supply of the user system is turned off no current flows from the user interface The I O voltage level of the user system interface can be the same as that of the VccQ To operate the emulator with low voltage lower than 3 3 V the VccQ must be supplied to the UVCC pin Make the emulator s switch settings so that the VccQ will be supplied SW2 1 and SW3 1 as shown in figure 1 5 The resistance values shown in the figures are recommended For the pin processing in cases where the emulator
39. tup CS gt program SuperH Family HS0005KCUO1HJ E10A USB Emulator HSOOO5KCU01HE User s Manual Supplementary HS7721KCUO1HJ Information on Using HS7721KCUO1HE the SH7721 Series and Test program manual HS0005TM01HJ and for HS0005KCUO1H HSO0005TMO1HE and HSO0005KCU02H provided on a CD R Note Additional document for the MPUs supported by the emulator is included Check the target MPU and refer to its additional document RENESAS 1 2 Connecting the Emulator with the User System To connect the EIOA USB emulator hereinafter referred to as the emulator the H UDI port connector must be installed on the user system to connect the user system interface cable When designing the user system refer to the recommended circuit between the H UDI port connector and the MPU In addition read the EIOA USB emulator user s manual and hardware manual for the related device Table 1 2 shows the type number of the emulator the corresponding connector type and the use of AUD function Table 1 2 Type Number AUD Function and Connector Type Type Number Connector AUD Function HS0005KCU02H 36 pin connector Available HS0005KCU01H HS0005KCU0O2H 14 pin connector Not available The H UDI port connector has the 36 pin and 14 pin types as described below Use them according to the purpose of the usage 1 36 pin type with AUD function The AUD trace function is supported A large amount of trace information can be acquired in realtime
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