Lab 1 – Introduction to Quartus II
Contents
1. gt Assignment Editor 2 From the drop down menu at the top for Category select Pin Category rs Fal B timing gt Loge options ix Haj epoxy 4 in PLL Comb cell Register cell Embedded multiplier block Clock control block Clock delay control block 3 Double click lt lt new gt gt in the To column and select input0 0 1 10 Double click the adjacent cell under Location and type PIN_AF14 Continue to assign the pins as seen in the table below To Location DE2 Board Description _ 6 ilnput1 1 PINNI SW10 8 finmputi 3 PINP2 SW12 9 input2 0 PINUS SW14 Note A complete list of pin assignments for the DE2 Development Board can be found here http www terasic com tw attachment archive 30 DE2 Pin Table pd All e Check All Uncheck All Delete All Save the pin assignments by selecting File gt Save from the Menu Bar or by clicking the Save button on the toolbar View the Pin Assignments Select Assignments gt Pin Planner to open the Pin Planner window Here you can view which pins have been assigned 6 Select View gt Pin Legend Window to display the pin legend Close the Pin Planner 7 Export Pin Assignments With the Assignment Editor selected select Assignments gt Export Assignments to create a qsf file containing your pin assignments This qsf file can be used for other projects by selecting Assignments gt Import Assignments when assigni2. and a Period of 20 ns Double Click Read SDC File in the Tasks window to read in an SDC file Click the ellipses l to select the Targets which opens up the Name Finder window Click List in the Matches field and select clk Click the single right arrow E add it to the list of selected names and then click OK Click Run in the Create Clock dialog box to create the clock Name Finder Collection get_ports hd Filter Options M Case insensitive Matches List clk k inputO 0 inputO 1 inputO 2 inputO 3 inputt 0 inputl 1 input 2 input 3 input2 0 input2 1 input2 2 input2 3 output 0 SDC command get_ports iclk OK Cancel Help 1 12 6 Select Constraints gt Set Input Delay from the Menu Bar 1 13 For Clock name select clk Make a Delay value of 20 ns Click the ellipses to select the Targets Click List in the Matches field and select all of the input and sel names Click the single right arrow to add them to the list of selected names and then click OK Click Run in the Set Input Delay window to create the input timing constraints Name Finder Collection get_ports Filter f Options Case insensitive Matches List 19 matches found 14 selected names input 0 inputO 0 input t input 2 input 3 input2 0 mputz 1 inpute 2 input2z 3 output 0 output 1 output 2 3 SDC command inputO 1 inputO 2 inputO 3 inpu
3. of the USB Cable into the computer Plug the 9v power supply into the 9V DC Power Supply Connector on the DE2 board and plug the other end into a 120v wall socket Press the Power ON OFF Switch to power on the DE2 board Make sure that the RUN PROG Switch for JTAG AS Modes is in the RUN position USB USB USB Ethernet Blaster Device Host Mic Line Line Video VGAVideo 10 100M Port Port Port in in Out In Port Port RS 232 Port 9V DC Power socom Ft CPC it f ft f 27 MHz Oscillator amp iia is j val t rf Burren i f au Ld lt twe um i i g i i 24 bit Audio Codec i j Wi 0 oF ne lt p PS 2 Keyboard Mouse Port Power ON OFF Switch f rm Ett ie ji a e i a p VGA 10 bit DAC USB Host Slave Controller TV Decoder NTSC PAL in ce Ethernet 10 100M Controller hiili i Expansion Header 2 JP2 Altera USB Blaster Controller Chipset Expansion Header 1 JP1 Altera EPCS16 Configuration Device WEEE EEPEEOEDHIY m S PER Altera Cyclone II FPGA RUN PROG Switch for JTAG AS Modes a 16x2 LCD Module SD Card Slot 7 Segment Displays 8 Green LEDs diei IrDA Transceiver SMA External Clock 18 Toggle Switches 4 Debounced Pushbutton Switches 50 MHz Oscillator 8 MB SDRAM 512 KB SRAM 4 MB Flash Memory Image Source DE2 Development and Education Board User Manual version 1 42 Altera Corperation 2008 1 17 2 Inthe Quartus II window click the Programmer button on the Toolbar to open the Programmer w
4. Lab 1 Introduction to Quartus II Lab 1 Introduction to Quartus II This lab is designed to familiarize you with using many of the common aspects of the Quartus II software through a complete design phase You will create a new project create a new vhdl file use the MegaWizard Plug In Manager compile the design plan and manage I O assignments apply timing analysis using the TimeQuest Timing Analyzer write Synopsys Design Contraint SDC files and program a design onto the Altera DE2 Development Board 1 1 Task 1 Create a New Project 1 Start the Quartus II software From the Windows Start Menu select All Programs gt Other Apps gt Altera gt Quartus II9 1 gt Quartus II 9 1 32 Bit 2 Start the New Project Wizard If the opening splash screen is displayed select Create a New Project New Project Wizard otherwise from the Quartus II Menu Bar select File gt New Project Wizard 3 Select the Working Directory and Project Name Working Directory H Altera_Training Lab1 Click Next to advance to page 2 of the New Project Wizard Note A window may pop up stating that the chosen working directory does not exist Click Yes to create it New Project Wizard Directory Name Top Level Entity page 1 of 5 fx What is the working directory for this project H Altera_TrainingLab1 ae What is the name of this project What is the name of the top level design entity for this project This name is case se
5. alysis Summary 1 15 15 In the Files section of the Project Navigator double click on Lab1 out sdc to directly edit the SDC file Project Navigator a x SY Files F poy abl out ede 5 pos Labl vhd B Mux3x1 gip i 8D Mux3x1 vhd WHO B F 16 Scroll down in the Lab1 out sdc file to find the Set Input Delay and Set Output Delay sections These should be starting on lines 63 and 83 for this example For each input line that reads similar to set_input_delay add_delay clock get_clocks clk 20 000 get_ports input0 0 Change the 20 000 ns delay to 2 000 ns Repeat this process for all the input and delays 62 E i i a a a a a a a a e e 63 Set Input Delay 64 F A a a a a a a a a a a a e a a a a a a a a a a a a a a a a a a a a a a a e 65 66 Set input delay add delay clock get_clocks c1k f2 get ports input0 0 67 set input delay add delay clock get clocks clk f2 get ports input0 1 65 set input delay add delay clock get clocks iclk f2 get ports input z 69 set input delay add delay clock get clocks c1k f2 get ports input0 3 70 set input delay add delay clock get clocks iclk A get ports inputi 0 71 Set input delay add delay clock get clocks i clk f2 get ports inputi 1 72 Set input delay add delay clock get clocks iclk zA get ports inputi z 73 set input delay add delay clock get clocks iclk f2 ge
6. ect the Lab1 out sdc file and click Open Click Add and then OK in the Settings window Settings Lab1 Category General Files Libraries Select the design files you want to include in the project Click Add All to add all design files in the Device project directory to the project Operating Settings and Conditions Compilation Process Settings File name Lab1 out sde Add Early Timing Estimate Incremental Compilation HDL version Add All Physical Synthesis Optimizations Lab1 out sde Synopsys De lt None gt EDA Tool Settings Labl vhd VHDL File lt None gt Analysis amp Synthesis Settings E Mux3s1 gip IP Yariation File lt None gt Fitter Settings Mux3x1 vhd VHDL File lt None gt 12 Compile your design by clicking the Start Compilation button on the toolbar 13 Click the Critical Warning tab in the Messages window to see that the timing requirements have not been met This is because of the long input and output delays specified 14 Expand the TimeQuest Timing Analyzer category in the Compilation Report and note that the Slow Model Fast Model and Multicorner Timing Analysis Summary reports are in red indicating that they have failed the timing analysis Expanding each of the red submenus will show the failures in more detail g amp n TimeQuest Timing Analyzer summary Eg Parallel Compilation B SDc File List F Clocks G9 Slow Model 9 Fast Model F Multicorner Timing An
7. elow 84 Installed Plug Ins 7 A Altera SOPC Builder h Arithmetic Communications LPM_AND LPM_BUSTRI LPM_CLSHIFT LPM_CONSTANT LPM_DECODE LPM_INV A MoR LPM_XOR arat Compiler Storage MegaStore Which device family will you be Cyclone II r using Which type of output file do you want to create C AHDL f VHDL C Verilog HDL What name do you want for the output file Browse H Altera_TrainingsLabs Labt1 Mux3s1 f Return to this page for another create operation Note To compile a project successfully in the Quartus software your design files must be in the project directory in the global user libraries specified in the Options dialog box Tools menu or a user library specified in the User Libraries page of the Settings dialog box Assignments menu Your current user library directories are Cancel lt Back Next gt 5 Select 3 for the number of data inputs from the drop down box Select 4 bits for the width of the data input and result output buses from the drop down box Under Do you want to pipeline the multiplexer Select Yes and set the output latency to 1 clock cycle Click Next MegaWizard Plug In Manager LPM_MUX page 3 of 5 LPM_MUX about Documentation Parameter settings Currently selected device Family Mux3x1 a Cyclone I v W Match project default How many data inputs do you want How wide should the data input and the re
8. indow The Hardware Setup must be USB Blaster USB 0 If not click the Hardware Setup button and select USB Blaster USB 0 from the drop down menu for Currently selected hardware Mode should be set to JTAG Make sure that the File is Lab1 sof Device is EP2C35F672 and the Program Configure box is checked W Quartus II H Altera_Training Labs Lab1 Lab1 Lab1 Lab1 cdf File Edit Processing Tools Window 2 Hardware Setup USB Blaster USB 0 Enable real time ISP to allow background programming for MAX II devices posit rie ever Checksum usercode hesk Eramne SSB Erase olap E 2 re Auto Detect Cab Add File C amp P Add Device Po Pom For Help press F1 Then click the Start button to program the DE2 board When the progress bar reaches 100 programming is complete 3 You can now test the program on the DE2 board by using the toggle switches located along the bottom of the board SWO and SW1 are the selector inputs to the multiplexer SW4 through SW7 are the four bits of data for input0 SW9 through SW11 are the four bits of data for input1 SW13 through SW17 are the four bits of data for inputz The output of the multiplexer is displayed on the first four green LEDs located above the blue push buttons on the DE2 board Their pattern will correspond to the four bits of the selected data stream 1 18
9. l be created with the following settings Project directory H Altera_Training Labs Lab 1 Project name Lab Top level design entity Lab Number of files added 0 Number of user libraries added O Device assignments Family name Cyclone Device EP2C35F672C6 EDA tools Design entry synthesis lt None gt Simulation lt None gt Timing analysis lt None gt Operating conditions Core voltage 1 2 Junction temperature range 0 85 C Cancel Task 2 Create Add and Compile Design Files 1 Create a new Design File Select File gt New from the Menu Bar Select VHDL File from the Design Files list and click OK SOPC Builder System Design Files AHDL File Block Diagram Schematic File EDIF File State Machine File System Yerilog HDL File Tel Script File Verilog HDL File VHDL File Memory Files Hexadecimal Intel Format File Memory Initialization File Verification Debugaging Files In System Sources and Probes File Logic Analyzer Interface File SignalT ap Il Logic Analyzer File Vector Waveform File Other Files AHDL Include File Block Symbol File Chain Description File Synopsys Design Constraints File Text File Cancel Sa 1 6 2 Copy and paste the following code into your new VHDL file then save it by selecting File gt Save Keep the default file name and click Save in the Save As dialog box Lab 1 Introduc
10. ng pins Task 4 Using the TimeQuest Timing Analyzer 1 Select Assignments gt Settings Click the Timing Analysis Settings and verify that Use TimeQuest Timing Analyzer during compilation is selected for Timing analysis processing Click OK Early Timing Estimate Timing analysis processing Incremental Compilation f Use TimeQuest Timing Analyzer during compilation Physical Synthesis Optimizations EDA Tool Settings Analysis amp Synthesis Settings Fitter Settings Se ming Snalysis Settings A it C Use Classic Timing Analyzer during compilation 2 Synthesize the Design ee Select the Start Analysis amp Synthesis button from the Toolbar Z Click OK to continue when the analysis and synthesis is complete 3 Open the TimeQuest Timing Analzyer Select Tools gt TimeQuest Timing Analyzer or use the Toolbar button o Click No when the dialog box pops up asking if you would like to generate an SDC file from the Quartus Settings File 1 11 4 Create a Timing Netlist In the TimeQuest Timing Analyzer window select Netlist gt Create Timing Netlist Set the Input netlist type to Post map and click OK Create liming Netlist Input netlist Delay model C Post fit Slow corer Speed grade Post map C Fast corner lv Zero C delays Tel command create_timing_netlist post_map model slow zero_ic_del cow Heb 5 Select Constraints Create Clock from the Menu Bar Type clk for the Clock name
11. nsitive and must exactly match the entity name in the design file Labi a Use Existing Project Settings Next gt Finish Cancel L Next gt 1 2 4 Click Next again as we will not be adding any preexisting design files at this time 5 Select the family and Device Settings From the pull down menu labeled Family select Cyclone II In the list of available devices select EPC235F672C6 Click Next New Project Wizard Family amp Device Settings page 3 of 5 Select the family and device you want to target for compilation Device family Show in Available device list Family Cyclone II v Package Any Devices All v Pin count Any y Speed grade Any v Auto device selected by the Fitter MV Show advanced devices Specific device selected in Available devices list F HardCopy compatible only Available devices Nee ore ita es Beer Meme Einbe IA EP2C200240C8 EP2C35F484C6 EP2C35F484C7 EP2C35F484C8 EP2CI6F 48418 ABER FO EPO EC EP2C35F672C8 COO BECCA lt 239616 483840 483840 483840 483840 1 27 a ev a ev eee es a E Cd Companion device l al dE opp vd Limit DSP 6 Click Next again amp ASM to Hardcopy device resources Finish Cancel as we will not be using any third party EDA tools 7 Click Finish to complete the New Project Wizard New Project Wizard Summary page 5 of 5 When you click Finish the project wil
12. sult output buses be bits Do you want to pipeline the multiplexer No Yes I want an output latency of Clock cycles _ Create an asynchronous Clear input 6 On page 4 of the MegaWizard Plug In Manager click Next 7 Verify that Mux3x1 vhd Mux3x1 cmp and Mux3x1_inst vhd are selected to be created and click Finish A dialog box may appear about the creation of a Quartus II Ip File If so simply click Yes MegaWizard Plug In Manager LPM_MUX page 5 of 5 Summary 3 fx a About Documentation 1 Parameter Settings Turn on the files you wish to generate 4 gray checkmark indicates a file that is automatically generated and a red checkmark indicates an optional file Click Finish to generate the selected files The state of each checkbox is maintained in subsequent MegaWizard Plug In Manager sessions The Megawizard Plug In Manager creates the selected files in the Following directory H Altera_Training Labs Lab1 4 Mux3x1 vhd Variation file O Mux3x1 inc AHDL Include file E Mux3x1 cmp VHDL component declaration file O Mux3x1 bst Quartus symbol file MM Mux31_inst vhd Instantiation template file 8 Compile the Design To perform a full compilation select Processing gt Start Compilation ae Alternatively select the Start Compilation button on the toolbar gt You may ignore any warnings that may appear at this time Task 3 Assign Pins 1 From the Menu Bar select Assignments
13. t 0 inputi 1 inputl 2 inputi 3 input2 0 input2 1 input2 2 input2 3 sel 0 sel 1 get_ports inputO 0 inputO 1 inputO 2 inputO 3 inputl 0 input 1 inputt 2 input 3 input2 0 input2 OK Cancel Help 7 Select Constraints gt Set Output Delay from the Menu Bar For Clock name select clk Make a Delay value of 20 ns 8 Click the ellipses to select the Targets Click List in the Matches field and select all of the output names Click the single right arrow to add it to the list of selected names and then click OK Click Run in the Set Output Delay window to create the output timing constraints Set Output Delay Clock name clk Use falling clock edge Output delay options C Minimum C Maximum f Both Delay value 20 ns M Add delay Targets get_ports output O output 1 output 2 output 3 E SDC command set_output_delay clock clk 20 get_ports output 0 output 1 outpu Run Cancel Help 9 Select Constraints gt Write SDC File from the Menu Bar to save the SDC file Click Save in the Save As dialog box 10 Close the TimeQuest Timing Analyzer 1 14 11 Add the SDC File to Your Project In the Quartus II window select Project gt Add Remove Files in Project from the Menu Bar Click the ellipses next to File name in the Settings window that popped up Select Script Files in the drop down box for Files of type in the Select File window Sel
14. t ports inputi 3 74 set input delay add delay clock get clocks clk f2 get ports input2z O 75 set input delay add delay clock get clocks iclk arn get ports input2 1 76 set input delay add delay clock get clocks clk f2 get ports inputz z 7 Set input delay add delay clock get clocks iclk a get ports input2z 3 75 set input delay add delay clock get clocks c1k f2 get ports sel 0 79 set input delay add delay clock get clocks clk J2 get ports sel 1 50 51 82 E i i i a a a a a a a a a a a a 83 Set Output Delay 64 REHEAT HKAKTAKTEKTEKTAKEAKHEHKEATEKTEKTEKTEKEEKEEKEAHS 55 56 set output delay add delay clock get clocks clk get ports output 0 o7 set output delay add delay clock get clocks j clk get ports output 1 88 set output delay add delay clock get clocks clk get ports output z2 59 set output delay add delay clock get clocks i cl1k get ports output 3 Save the Lab1 out sdc file by clicking on the Save button on the Menu Bar w a o gt 17 Compile the design again by clicking the Start Compilation button on the toolbar and check the TimeQuest Timing Analyzer reports again to see that the design has now passed the timing analysis Ignore any warnings at this time 1 16 Task 5 Program the DE2 Development Board 1 On the Altera DE2 Development board plug the USB Cable into the USB Blaster Port Plug the other end
15. tion to Quartus I VHDL Code LIBRARY 1eee USE 1eee std_logic_1164 al1 ENTITY Labl IS PORT clk IN STD_LOGIC iInputO inputl input2 IN STD_LOGIC_VECTOR 3 DOWNTO 0 sel IN STD_LOGIC_VECTOR 1 DOWNTO 0 output OUT STD_LOGIC_VECTOR 3 DOWNTO 0O END Lab1 ARCHITECTURE Structure OF Labl1 IS COMPONENT Mux3x1 IS PORT clock IN STD_LOGIC dataOx datalx data2x IN STD_LOGIC_VECTOR 3 DOWNTO 0 sel IN STD_LOGIC_VECTOR 1 DOWNTO 0 result OUT STD_LOGIC_VECTOR 3 DOWNTO 0O END COMPONENT BEGIN MuxOut Mux3x1 PORT MAP clk input0O inputi input2 sel output END Structure 3 Create an 4 Bit 3x1 Multiplexer using the MegaWizard Plug in Manager Select Tools gt MegaWizard Plug In Manager Select the radio button for Create a new custom megafunction variation and click Next MegaWizard Plug In Manager page 1 The MegaWizard Plug In Manager helps you create or modify design files that contain custom variations of megafunctions Which action do you want to perform Create a new custom megafunction variation Edit an existing custom megafunction variation Copy an existing custom megafunction variation Copyright C 1991 2009 Altera Corporation Cancel I Next gt ist 4 From the Gates menu select the LPM MUX subitem and name the file Mux3x1 and click Next MegaWizard Plug In Manager page Za Which megafunction would you like to customize Select a megafunction from the list b
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