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1. 3 10 Max 0 38 Max 2 90 Min 0 28 Min lt 0 65 REF lt lt i 1 A AO O 0 23 Max SN rai 0 13 Min a y 0 27 REFS 3 10Max 5 08 Max 2 90 Min 4 67 Min BUDA e y Y GAUGE PLANE 1 2 1 0 38 Max fea 0 40 Min 0 28 Min DETAIL A DETAIL A t a 0 95 Max 1 10 Max 0 75 Min ff f le y J y SEATING PLANE JJ a J 0 15 Max AO 0 10 Max 0 05 Min 0 23 max 0 13 Min NOTE 1 PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH PROTRUSIONS OR GATE BURRS 2 PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTUSIONS 3 CONTROLLING DIMENSION IN MILIMETERS 4 THIS PART IS COMPLIANT WITH JEDEC MO 187 VARIATIONS AA 5 LEAD SPAN STAND OFF HEIGHT COPLANARITY ARE CONSIDERED AS SPECIAL CHARACTERISTIC Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low power small size analog intensive mixed signal solutions Silicon Labs extensive patent portfolio is a testament to our unique approach and world class engineering team The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice Silicon Laboratories assumes no respon
2. TS7001 S LICON LABs O A Micropower 2 channel 187 5 ksps Serial Output 12 bit SAR ADC FEATURES Pin for pin 1 5x Faster Upgrade to AD7887 Single supply Operation 2 7V to 3 6V INL 1LSB One or Two Single ended Analog Inputs Internal Wide bandwidth Track and Hold Integrated 2 5 V Reference Flexible Power Throughput Rate Management 0 85mA at 187 5ksps Internal VREF ON 0 7mA at 187 5ksps Internal VREF OFF Shutdown mode Supply Current 1uA max SPI QSPI MICROWIRE DSP Compatible Serial Interfaces Operating Temperature Range 40 C to 85 C 8 pin MSOP Packaging APPLICATIONS Instrumentation and Control Systems High Speed Modems Battery powered systems Personal Digital Assistants Medical Instruments Mobile Communications i di di di a ad gt o DESCRIPTION The TS7001 a pin for pin 1 5x faster alternate to the AD7887 is a self contained 2 channel high speed micropower 12 bit analog to digital converter ADC that operates from a single 2 7V to 3 6V power supply The TS7001 is capable of a 187 5 ksps throughput rate with an external 3 MHz serial clock and draws 0 85mA supply current The wideband input track and hold acquires signals in 500ns and features a single ended sampling topology Output data coding is straight binary and the ADC is capable of converting full power signals up to 10 MHz The ADC also contains an integrated 2 5V reference or the VREF pin can be over
3. Total Harmonic Distortion THD 80 dB typ fu 10kHzsine wave fsamere 187 5ksps Peak Harmonic or Spurious Noise 80 db typ fin 10 kHz sine wave fsampLe 187 5ksps Intermodulation Distortion IMD Second Order Terms 1 9 983 kHz f2 10 05 kHz fsxupLe 187 5ksps Third Order Terms 1 9 983 kHz f2 10 05 kHz fsampre 187 5ksps Channel to Channel Isolation typ fin 25 kHz Full Power Bandwidth 0 MHz typ Measured at 3 dB down DC ACCURACY Any channel Q UJ Resoun OO o ooo i o oBs S VDD 3V Guaranteed no missing codes to 11 bits o e Offset Error OfselEmorMan S os ISBimaj S Single channel mode external reference Ganenn 2 1SBimy ANALOG INPUT 010 VREF 0 to VDD leakage Curen 5 pmo Input Capacitance 10 Fw REFERENCE INPUT OUTPUT 2 488 2 513 Initial accuracy 0 5 _REFOUT Temperature Coefficient 30 ppm typ LOGIC INPUTS inputlowVoltage Wu os vma TVS Typically 10nA V OV or VDD input Capacitance G 10 mo LOGIC OUTPUTS lsn 200 pA _Floating State Leakage Current tt pA mag o _Floating State Output Capacitance 10 pFimaxh o Output Coding Natural Binary CONVERSION RATE Conversion time plus acquisition time is 187 5ksps Throughput Time SCLK cycles with 3 MHz Clock Track and Hold Acquisition Time SOLKoydes OOS S y SO SCLK cycles 4 883 ps 3 MHz Clock TS7001 Rev 1 0 Page 3 TS7001 ELECTRICAL SPECIFICATIONS c
4. Z J AIN1 VREF zZ O PIN 1 Page 8 TS7001 Rev 1 0 SILICON LAB TS7001 TS7001 CONTROL REGISTER DESCRIPTION The TS7001 s write only control register is 8 bits wide Serial ADC configuration data is uploaded from the host processor at the TS7001 s DIN pin on low to high SCLK transitions Serial input data is uploaded to the TS7001 simultaneously as the conversion result is transferred out of the TS7001 All serial data transfers require 16 serial clocks serial data available on the first eight low to high SCLK transitions is transferred into the control register The first bit in the serial data stream is always interpreted as the MSB Upon initial power up the TS7001 s default control register bit is cleared to all zeros all 0 s Table 1 lists the functions of the Control Register s 8 bits transitions After a high to low CS transition signal Table 1 TS7001 s 8 Bit Control Register Content Description DB7 MSB DB6 DB5 DB4_ DB3 DB2 DB1 DBO LSB DONTC ZERO SIN DUAL ZERO Label DONTC Control Register DB7 Bit status of DB7 is Don t Care In other words the DB7 bit can be a 0 or a 1 Control Register DB6 To ensure correct TS7887 operation Control Register DB6 status must always be a zero O Control Register DB5 Internal Voltage Reference Configuration The status of DB5 determines whether the TS7001 s internal voltage reference is
5. 2 7V 3 6V 20 187 5ksps Sampling Rate i REFIN External 2 488V m 10kHz Fundamental 5 100mVPP Sine Wave on VDD 40 O 02 LJ 60 LL te gt LI m 77 a n gt Lu 100 U oc Lu 120 O A 140 FREQUENCY kHz FREQUENCY kHz Signal to Noise Ratio vs Frequency Integral Nonlinearity n VDD 3V D REFIN External 3V AAi H lt cc m 7 are ny 2 2 N lt i i iL ia M zi l lt Z O U 0 7 15 5 30 5 45 60 2 75 90 FREQUENCY kHz DIGITAL OUTPUT CODE Differential Nonlinearity Offset Error vs Temperature m U a m Ea wiji TTi ap fap TU s a MJ VIA pra Tn re T cc Lu z N TA PA E AN LL LL O 0 1k 2k 3k 4 DIGITAL OUTPUT CODE TEMPERATURE C Page 6 TS7001 Rev 1 0 TS7001 TYPICAL PERFORMANCE CHARACTERISTICS Vop 8V fscLK 3MHz Ta 25 C unless otherwise noted REFERENCE OUTPUT V GAIN ERROR LSB SUPPLY CURENT mA 2 505 Gain Error vs Temperature TEMPERATURE C Internal Reference Output vs Temperature TEMPERATURE C Power Supply Current vs Temperature 0 55 0 50 0 45 0 40 0 35 TEMPERATURE C REFERENCE OUTPUT V SUPPLY CURENT mA SILICON LABS Internal Reference Output vs Supply Voltage 2 502 2 500 2 498 2 496 2 494 2 7 2 93 3 15 3 38 3 6 POWER SUPPLY VOLTAGE Volt Power Supply Current vs Power Supply Voltage 0 6 CODE 111111111111 cae E E E ee CONVERTING SCLK 3M
6. AND PMO 1 IS LOADED TO KEEP THE TS57001 IN THIS MODE Figure 13 TS7001 s Power Management Mode 4 Operation Diagram sampled on the second low to high SCLK transition following the high to low CS transition At the end of conversion after the last low to high SCLK transition the ADC is powered down automatically back into its standby mode The TS7001 s Serial Interface Description Figure 14 shows the detailed timing diagram for TS7001 s serial interface The serial clock provides the conversion clock and also controls the transfer of data to from the TS7001 during conversion The CS signal initiates the serial data transfer and controls the TS7001 s conversion process In PM Modes 1 3 and 4 a high to low CS transition powers up the ADC In all cases the CS signal gates SCLK to the TS7001 and sets the ADC s internal track and hold into track mode The analog input signal is then sampled on the second low to high SCLK transition following the high to low CS transition Thus the analog input signal is acquired during the first 1 5 SCLK clock cycles taca after the taca CS ty t SCLK 1 i 1 2 3 4 t t e FOUR LEADING ZEROS DOUT high to low CS transition In modes where the high to low CS transition powers up the ADC the acquisition time must include a 5 us power up delay The ADC s internal track and hold moves from track mode to hold mode on the second low to high SCLK transition and a c
7. DBS is a one a 1 the AIN1 input is selected DB3 should be a zero 0 when the TS7001 is configured for single channel operation ZERO Control Register DB2 To ensure correct TS7887 operation Control Register DB2 status must always be a zero Control Register DB1 and DBO Power Management Operating Modes DB1 and DBO are decoded to configure the 0 PMO TS7001 into one of four operating modes as shown in Table 2 ZERO SIN DUAL Table 2 TS7001 s Power Management Operating Modes PM Mode 1 In this operating mode the TS7001 s power down mode is enabled if its CS input is a one a 1 and is operating in full power mode when its CS input is a zero a O Thus the TS7001 is powered down on a low to high CS transition and is powered up on a high to low CS transition PM Mode 2 In this operating mode and regardless of the status of any of the logic inputs the TS7001 is always fully powered up PM Mode 3 In this operating mode the TS7001 is automatically powered down at the end of each conversion regardless of the state of the CS input ADC wake up time from full shutdown is 5us and system design should ensure that at least 5us have elapsed before attempting to perform a conversion in this mode otherwise an invalid conversion result may PM Mode 4 In this operating mode the TS7001 is configured for standby operation after conversion Sections of the TS7001 are powered dow
8. Serial data programmed into the TS7001 at the DIN input during the first eight clock cycles of data transfer are loaded to the control register For the TS7001 to remain in PM Mode 2 system timing design must always write PM1 PMO 0 1 into the control register on every serial input data transfer A high to low CS transition initiates the conversion sequence and the analog input signal is sampled on the second low to high SCLK transition Sixteen serial clock cycles are required to complete the conversion and to transfer the conversion result to the host processor Another conversion can be initiated immediately by toggling the CS pin low again once data transfer is complete that is once the CS signal is toggled high Power Management Mode 3 Operation PM1 PMO 1 0 In this mode the TS7001 is automatically powered down at the end of every conversion It is similar to PM Mode 1 except that the status of the CS signal in PM Mode 3 does not have any effect on the power down status of the TS7001 Figure 11 shows the general operating diagram of the TS7001 in PM Mode 3 On the first high to low SCLK transition after CS is toggled low all TS7001 s internal circuitry starts to power up Similarly to PM Mode 1 it can take as long as 5us for the TS7001 s internal circuitry to power up completely As a result any conversion start sequence should not be Initiated during this initial 5 us power up delay The analog input sig
9. example consider an ADSP 2111 that has been chosen as the host processor Since it has a 16 MHz master clock frequency a SCLKDIV value of 3 is necessary to program its SPORT serial clock output to operate at 2MHz for the TS7001 16MHz 2 2MHz thus eight master clock periods will elapse for every one TS7001 SCLK period If the ADSP 2111 s timer registers are loaded with a value of 803 100 5 SCLKs will occur between interrupts and subsequently between transmit instructions Because the transmit instruction occurs on an SCLK edge non equidistant sampling is the result The DSP will implement equidistant sampling only if the number of SCLKs between interrupts is a whole integer number A TS7001 to DSP56xxx DSP Interface Connecting the TS7001 for use with Freescale s nee Motorola s DSP56xxx family of DSPs is shown in Figure 17 where an inverter is used between the DSP56xxx s SCK output and the TS7001 s SCLK input The DSP56xxx s SSI synchronous serial interface is configured in synchronous mode SYN bit 1 in CRB with an internally generated 1 bit clock period frame sync for both Tx and Rx Bits FSL1 1 and FSLO 0 in CRB Word length is set to 16 by setting bits WL1 1 and WLO 0 in CRA Page 18 TS7001 DSP56xxx Additonal pins omitted for clarity Figure 17 Interfacing the TS7001 to DSP56xxx type DSPs A TS7001 to 68HC11 Microcontroller Interface Connecting the TS7001 to Freescale s 68HC11
10. has a continuous serial clock and frame synchronization signals to time the data transfer operations A single logic inverter is the only glue logic required between the TMS320C5x s CLKX output and the TS7001 SCLK input and is illustrated in the connection diagram of Figure 15 The TMS320C5x s_ serial port is configured to operate in burst mode using the TMS320C5x s internal CLKX serial clock transmit T57001 Additional pins omitted for clarity Figure 15 Interfacing the TS7001 to TMS320C5x type DSPs and FSX frame sync transmit programmed as the TS7001 s CS input The TMS320C5x s serial port control register SPC must be configured in the following manner Table 3 TMS320C5x Serial Port Control Register Setup FO FSM MCM TXM m e To e TL ee A TS7001 to ADSP 21xx DSP Interface The TS7001 is easily interfaced to the ADSP 21xx or equivalent family of DSPs using an inverter between the ADSP 21xx s serial clock and the TS7001 as shown in Figure 16 The ADSP 21xx s SPORT control register should be configured in Alternate Framing mode as shown in Table 4 and the ADSP 21xx s serial clock frequency is set in its SCLKDIV register T57001 ADSP 21xx Additional pins omitted for clarity Figure 16 Interfacing the TS7001 to ADSP 21 xx type DSPs Table 4 SPORTO Control Register Setup Setting W 1 INVRFS INVTFS 1 1 mE DTYPE 00 mir BRINE Description Alternative framing
11. s t O AIN2 DIN m CI ANALOG INPUT ov TO VDD Figure 4 TS7001 s Typical Application Circuit input range on either analog input is OV to VDD It is always considered good engineering practice to bypass the ADC s VDD with good quality capacitors with short leads surface mount components are preferred and located a very short distance from the ADC The conversion result at the DOUT pin is a 16 bit word with four leading zeros followed by the MSB of the 12 bit conversion result In low power applications automatic power down at the end of conversion modes PM Modes 3 or 4 should be used to improve the ADC s power consumption versus throughput rate performance For additional information on the TS7001 s four power management operating modes please consult the Operating Modes section of the datasheet Analog Input Details An equivalent circuit of the analog input structure of the TS7001 is illustrated in Figure 5 where diodes D1 and D2 serve as ESD clamp protection for the analog inputs Since there are diodes from the analog input to both VDD and GND it is important any forward conduction of current in D1 or D2 is VDD Ri ce 10002 10pF TO TRACK HOLD atte AMPLIFIER INPUT Sw me CONVERSION PHASE SWITCH SW1 OPEN TRACK PHASE SWITCH SW1 CLOSED Figure 5 TS7001 s Analog Input Equivalent Circuit avoided Thus the analog input signal should never exceed the either VDD or GND by more than 200m
12. 1 1ANDPMO 0 1 B 16 1 8 16 1 B 16 SCLE HVAGSIMESINA obe JULI AT PAT Ate AU a FOUR LEADING ZEROS CONVERSION RESULT DIN CONTROL REGISTER DATA IS LOADED ON FOUR LEADING ZEROS CONVERSION RESULT DATA IM PM1 0 AND FMO 1 15 LOADED THE FIRST EIGHT CLOCKS WITH PM1 1 AND PMO 0 TO PLACE THE T57001 IN NORMAL MODE TO PLACE THE T57001 BACK INTO MODE 3 FOUR LEADING ZEROS CONVERSION RESULT DATA IN M1 1 AND PMO 0 15 LOADED Figure 12 TS7001 s Power Management Mode 3 Operation Diagram for Fast SCLK Microcontrollers and DSPs In microcontroller applications or in systems with a slow serial clock ihe system timing design can be devised to accommodate this timing alignment by assigning the CS signal to one of the port lines and then adjusting the timing such that the serial data read from the microcontroller s serial port is not initiated for at least 5us However in systems with higher speed serial clocks not unlike high speed __ serial clock DSP applications it may not be possible to insert a 5us delay between ADC power up and the first low to high SCLK transition Therefore system timing design should incorporate a WRITE to the TS7001 s control register to terminate the ADC s PM Mode 3 operation and program the TS7001 into PM Mode 2 that is by writing PM1 PMO 0 1 into the TS7001 s control register To get a valid conversion result a second conversion must be initiat
13. 15 SCC Seinrtierunancanesemncunesicntan nenn rana kanaa Ea 220 C Operating Temperature Range kaaa 40 C to 125 C Pb Free Temperature Soldering Reflow 0 260 0 C Storage Temperature Range akan 65 C to 150 C memoare 4kV Junction Temperature aaa 150 C Electrical and thermal stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not implied Exposure to any absolute maximum rating conditions for extended periods may affect device reliability and lifetime PACKAGE ORDERING INFORMATION TOP VIEW AIN1 VREF 4 8 pin MSOP M8 Package ORDER NUMBER PART MARKING CARRIER QUANTITY TADF TS7001IM8T Tape amp Reel 2900 Lead free Program Silicon Labs supplies only lead free packaging Consult Silicon Labs for products specified with wider operating temperature ranges Page 2 TS7001 Rev 1 0 TS7001 SILICON LABS gt ELECTRICAL CHARACTERISTICS Vop 2 7V to 3 6V Veer 2 5V External internal reference unless otherwise noted fscrk 3 MHz Ta Tmn to Tmax unless otherwise noted Parameter Limit Unt Test Conditions Comments DYNAMIC PERFORMANCE Signal to Noise Distortion Ratio SNR dB typ fn 10 kHz sine wave fsampLe 187 5ksps
14. Active low frame signal Right justified data SLEN 1111 1 ISCLK 1111 6 bit data word nternal serial clock TFSR RFSR Frame every word a IRFS ITFS TS7001 Rev 1 0 Page 17 TS7001 icon LABS With the ADSP 21xx s TFS and RFS pins of its SPORT connected together the TFS is configured as an output and RFS configured as an input The frame synchronization signal generated on the TFS output serves as the TS7001 s CS input In this example however since a timer interrupt is used to control the sampling rate of the ADC it may not be possible to perform equidistant sampling a required criterion in all signal processing applications under certain application conditions The ADSP 21xx s timer registers are configured in such a manner that an interrupt is generated internally at the required sample interval When the timer interrupt is received an ADC control word is transmitted at the DT output with TFS The TFS signal is then used to control the RFS and hence the data read from the TS7001 When the instruction to transmit with TFS is executed that is AXO TXO the state of the SCLK is checked The DSP waits until the SCLK has toggled high to low to high before a transmission will commence If the timer and SCLK values are set such that the instruction to transmit occurs on or near the low to high SCLK transition data may be transmitted or the DSP may wait to transmit data until the next clock edge For
15. Description SOS C towen Srta Omesonim _ _ _ C eo isete Throughput Time toowear rico 16 tsa on 60 os max Delay rom OS until DOUT three state disabled as min 0 smag OS rising edge to DOUTHigh2 Note 1 Timing specifications are sample tested at 25 C to ensure compliance All input signals are specified with tr tf 5 ns 10 to 90 of VDD and timed relative to a voltage level of 1 6V Note 2 The mark space ratio for the SCLK input is 40 60 to 60 40 See Serial Interface section for additional details Note 3 Measured with the load circuit as shown below and defined as the time required for the output to cross 0 8V or 2 0V Note 4 Timing specification tg is derived from the measured time taken by the data outputs to change 0 5V when loaded with the circuit shown below The measured result is then extrapolated back to remove the effects of charging or discharging the 50pF capacitor This means that the time ts quoted in the timing characteristics is the true bus relinquish time of the TS7001 and is independent of bus loading TO OUTPUT PIN 1 6V Load Circuit Used for TS7001 s Digital Output Timing Specifications TS7001 Rev 1 0 Page 5 TS7001 TYPICAL PERFORMANCE CHARACTERISTICS Vop 8V fscLK 3MHz Ta 25 C unless otherwise noted ILICON LABS Dynamic Performance vs Frequency Power Supply Rejection vs Frequency 0 4096 point FFT m VDD
16. Hz 0 3 STATIC 2 2 93 3 15 3 38 3 6 0 2 0 1 POWER SUPPLY VOLTAGE Voli TS7001 Rev 1 0 TS7001 PIN FUNCTIONS LABEL Chip Select As an active low logic input signal the CS input provides the dual function of initiating TS7001 conversions as well as framing the serial data transfer When the TS7001 is operated in Mode 1 its default power management mode the CS pin also acts as the shutdown pin in that the TS7001 is powered down when the CS pin is logic high Power Supply Voltage The TS7001 s Vpop range 2 7V to 3 6V In two channel operation the VDD pin also serves as the TS7001 s voltage reference source during conversions For optimal performance the VDD pin should be bypassed to GND with a 10 uF tantalum capacitor in parallel with a 0 1uF ceramic capacitor Analog Ground Pin The GND pin is the ground reference point for all TS7001 internal circuitry In systems with separate AGND and DGND planes the TS7001 s GND pin should be connected to the AGND plane Analog Input Channel 1 External VREF Input In single channel mode the AIN1 VREF pin is configured as VREFIN OUT In this mode the TS7001 s internal 2 5V reference can be accessed or an external reference can be applied to this pin thereby overriding the internal reference The reference voltage range for an externally applied reference is 1 2V to VDD In two channel mode the AIN1 VREF pin operates as a second analog input channel AIN1 The input
17. IC 16 PIC 17 Microcontroller User Manual TS7001 PIC16C6x Pa bem PIC16C7x DA Goi En es Additional pins omitted for clarity Figure 20 Interfacing the TS7001 to PIC16C6x PIC16C7x type Microcontrollers Even though the TS7001 s exhibits excellent supply rejection as shown in th Typical Operating Characteristics it is always considered good engineering practice to prevent high frequency noise on the TS7001 s VDD power supply from affecting the ADC s high speed comparator Therefore the VDD supply pin should be bypassed to the star ground with 0 1uF and 10uF capacitors in parallel and placed close to the ADC s Pin 2 as was shown in Figure 4 Component lead lengths should be very short for optimal supply noise rejection If the power supply is very noisy an optional 10 Q resistor inserted in series with the TS7001 s VDD pin can be used in conjunction with the bypass capacitors to form a low pass filter Evaluating the TS7001 s Dynamic Performance The recommended layout for the TS7001 is outlined in the demo board manual for the TS7001 The demo board kit includes a fully assembled tested demo board and documentation describing how to evaluate the TS7001 s dynamic performance using Silicon Labs proprietary TSDA VB data acquisition capture kit Page 19 TS7001 SILICON LABS PACKAGE OUTLINE DRAWING 8 Pin MSOP Package Outline Drawing N B Drawings are not to scale
18. TS7001 s control logic and the charge redistribution DAC work together to add or subtract fixed packets of charge from the sampling capacitor to balance once again the comparator input terminals At the time when the comparator is rebalanced the conversion process is complete and the ADC s control logic generates the ADC serial output conversion data Figure 3 illustrates the ideal transfer function for the TS7001 where the output data is coded straight binary Thus the designed code transitions occur at successive integer LSB values that is at 1 LSB at 2 LSBs etc where the LSB size is VREF 4096 FULL SCALE 111 111 TRANSITION h 111 110 111 101 LU w 8 E 5 l gs lt CY O f FS Veer lt 000 011 V 1LSB JE 000 010 4096 000 001 000 000 H gt 012 3 Fs INPUT VOLTAGE LSBs FS 3 2LSB Figure 3 TS7001 s Unipolar Transfer Function for Straight Binary Digital Data TS7001 Rev 1 0 TS7001 SILICON LA S A MMM Typical Application Circuit Figure 4 shows a typical application circuit for the TS7001 where the ADC s GND pin is connected to the analog ground plane of the system In this application circuit the TS7001 has been configured for two channel operation so the ADC s VREF is internally connected to VDD as a result the analog SUPPLY VOLTAGE n 2 7W TO 3 6V 3 WIRE SERIAL INTERFACE DOUT TS7001 Tie a Ke sa
19. V Even though the maximum current these diodes can conduct without causing irreversible damage to the ADC is 20mA any small amount of forward diode current into the substrate because of an overvoltage condition on an unselected channel can cause inaccurate conversion results on the selected channel Attributed to parasitic package pin capacitance capacitor C1 in Figure 5 is typically about 1 pF Resistor R1 is the equivalent series resistance of the TS7001 s input multiplexer and input sampling switch and is approximately 100Q Capacitor C2 is the ADC sampling capacitor and has a typical capacitance of 10 pF In signal acquisition or ac applications the use of an external R C low pass filter on either or both analog inputs can be useful in removing out of band high frequency components from the analog input signal In applications where harmonic distortion and signal to noise ratio performance are important the analog input s should be driven from a low impedance source Large source impedances will affect significantly the TS7001 s ac performance To lower the driving point impedance level it may be necessary to use an input buffer amplifier The optimal choice for the external drive op amp will be determined by application requirements as well as the TS7001 s dynamic performance When the analog input is not driven by an external amplifier the driving point source impedance should be low The maximum source impedance will depe
20. and PMO bits of the Control Register Also mentioned previously the TS7001 can be configured as a read only ADC by forcing an all zeros 0 s condition in the control register This can be easily done by applying a logic LOW at all times to the DIN pin or hard wiring the DIN pin directly to GND Power Management Mode 1 Operation PM1 PMO 0 0 Power Management Operating Mode 1 is used to control the TS7001 s power down using the CS pin Whenever the CSpin is low the TS7001 is fully powered up whenever the CSpin is high the TS7001 is completely powered down When the CS pin is toggled high to low all internal circuitry starts to power up where it can take as long as 5us for the TS7001 s internal circuitry to power up completely As a result any conversion start sequence should not be initiated during this initial 5us power up delay Figure 9 shows a general operating diagram of the TS7001 in PM Mode 1 The analog input signal is sampled on the second low to high SCLK transition following the initial high to low CS transition System timing design should incorporate a 5 us delay between the high to low CS transition and the second low to high SCLK transition In microcontroller applications this is achieved by TS7001 POWERS DOWN ON GS RISING EDGE FOR PM1 AND PMO 0 CONTROL REGISTER DATA IS LOADED ON THE FIRST EIGHT CLOCKS PM1 AND PMO 0 TO KEEP THE TS57001 IN MODE 1 Figure 9 TS7001 s Power Management Mode 1 Ope
21. data from the TS7001 In applications where the first serial clock transition following a high to low CS transition is a high to low SCLK transition DOUT transitions from a high Z state to a first leading zero thus the first low to high SCLK transition generates the first leading zero on DOUT In applications where the first serial clock transition following a high to low CS transition is a low to high SCLK transition the first leading zero may not be set up in time for the host processor to read it correctly However subsequent DOUT bits are transferred out on high to low SCLK transitions so that they are ready for the host processor on the following low to high SCLK transition Thus the second leading zero is transferred out on the high to low SCLK transition subsequent to the first low to high SCLK transition Therefore DOUT s final bit in the data transfer is valid on the 16th low to high SCLK transition having been transferred out of the ADC on the previous high to low SCLK transition Interfacing the TS7001 to Industry Standard Microprocessors and DSPs The serial interface on the TS7001 allows the ADC to be directly connected to a number of many microprocessors and DSPs How to interface the TS7001 with some of the more common microcontroller and DSP serial interface protocols is covered in this section A TS7001 to TMS320C5x DSP Interface With peripheral serial devices like the TS7001 the TMS320C5x s serial interface
22. driven by an external reference The TS7001 s provides one or two analog inputs each with an analog input range from 0 to Vrer In two channel operation the analog input range is OV to VDD Efficient circuit design ensures low power consumption of 2mW typical for normal operation and 3uW in power down operation The TS7001 is fully specified from 40 C to 85 C and is available in 8 pin MSOP package FUNCTIONAL BLOCK DIAGRAM oo AIN1 VREF SOFTWARE CONTROL LATCH TS7001 CHARGE REDISTRIBUTION DAC CONTROL LOGIC SAR ADC SERIAL INTERFACE NEE _ cs SPI and QSPI are trademarks of Motorola Inc MICROWIRE is a trademark of National Semiconductor Corporation SCLK DIN DOUT Page 1 2014 Silicon Laboratories Inc All rights reserved TS7001 ABSOLUTE MAXIMUM RATINGS VoD TO AGNO srs seers a vn 0 3V to 7V MSOP Package Power Dissipation ceseeeeeeeeeees 450mW Analog Input Voltage AINO AIN1 to AGND 0 3V to Vpp 0 3V Oja Thermal Impedance aaa kaaa 205 9 C W Digital Input Voltage to AGND aaa 0 3V to Vpp 0 3V Bic Thermal Impedance ea 43 74 2C W Digital Output Voltage to AGND aa 0 3V to Vpp 0 3V Lead Temperature Soldering REFIN REFOUT to AGND c0ccceeeeeeeees 0 3V to Vpp 0 3V Vapor Phase 60 SeC aaaaaaa aaa aaa 215 C Input Current to Any Pin Except Supplies cccceee 10mA Inirared
23. ed when the ADC is powered up see Figure 19 A WRITE operation that takes place with this second conversion can program the ADC back into PM Mode 3 where the power down operation is enabled when the conversion sequence terminates Power Management Mode 4 Operation PM1 PMO 1 1 In PM Mode 4 the TS7001 is automatically placed in standby or sleep mode at the end of every conversion In this mode all internal circuitry is powered down except for the internal 2 5 V reference PM Mode 4 is similar to PM Mode 3 in this case the power up delay time is much shorter 1us vs 5us because the internal reference remains powered up at all times Figure 13 shows the general operating diagram of the TS7001 in PM Mode 4 On the first high to low SCLK transition after the CS pin is toggled low the TS7001 is powered up out of its standby mode Since the TS7001 s power up delay time PM Mode 4 is very short powering up the ADC and executing a conversion with valid results in the same read write operation is feasible The analog input signal is TS7001 Rev 1 0 Page 15 TS7001 icon LABS THE T57001 ENTERS STANDBY AT THE END OF CONVERSION SINCE PM1 1 AND PMO 1 SCLK i THE T57001 POWERS UP FROM STANDBY ON SCLK FALLING EDGE SINCE PM1 1 AND PMO 1 FOUR LEADING ZEROS CONVERSION RESULT oN DATA IN CONTROL REGISTER DATA IS LOADED ON THE FIRST EIGHT CLOCKS WITH PM1 1 AND PMO 1 PM1 1
24. enabled or disabled A 0 in the DBS location will enable the TS7001 s internal voltage reference default condition To disable the TS7001 s internal voltage reference a 1 must be written into DBS s register location Control Register DB4 Single Channel Dual Channel Configuration Control Register DB4 configures the TS7001 as a single channel or two channel ADC Loading a zero 0 into this register location configures the TS7001 for single channel operation with the AIN1 VREF pin configured to for internal VREF operation default configuration In this case the analog input signal range is OV to VREF Loading a one 1 into this register location configures the TS7001 for two channel operation with the AIN1 VREF pin configured to its AIN1 function as the second analog input In addition the conversion process s reference voltage is internally connected to VDD In this case the analog input signal range is OV to VDD To obtain best performance from the TS7001 in two channel operation the ADC s internal reference should be disabled that is a 1 should be loaded into DB5 s register location Control Register DB3 Channel Select Bit The bit status of DB3 determines on which channel the TS7001 is converting When the ADC is configured for dual channel operation DB3 determines which channel is converted on the next conversion cycle When DBS is a zero a O the AINO input is selected and when
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26. ing a logic LOW at all times to the DIN pin Pin 6 or by hard wiring the DIN pin permanently to GND For maximum flexibility to address multiple configurations based on the application the DIN input can be used to load ADC configuration data from a host processor into the TS7001 s 8 bit Control Register TS7001 Operation and Transfer Function The TS7001 is a successive approximation ADC the core of which is a charge redistribution DAC Figure 1 illustrates an equivalent circuit for the TS7001 in signal acquisition phase Here Switch SW1 is in Position A and Switch SW2 is closed With the sampling capacitor s terminals connected to the ACQUISITION PHASE SAMPLING CAPACITOR A SW ANALOG i INPUT is AGND REF IN REF OUT 2 COMPARATOR Figure 1 1S7001 s Acquisition Phase Equivalent Circuit Page 10 ILICON LABS analog input on one side and REF on the other the analog signal is acquired During the acquisition phase the inputs to the comparator are balanced since both inputs are connected to REF During the conversion phase as shown in the equivalent circuit in Figure 2 Switch SW1 is moved from Position A to GND at Position B and Switch SW2 is opened At this point in time the inputs to CONVERSION PHASE SAMPLING CAPACITOR ANALOG Po pital INPUT E AGND COMPARATOR REF IN REF OUT 2 Figure 2 TS7001 s Conversion Phase Equivalent Circuit the comparator become unbalanced The
27. lowing 1TS7001 application configuration a the ADC is powered from VDD 8V and is configured for PM Mode 3 that is PM1 PMO 1 0 where the ADC s internal reference is enabled and the ADC automatically powers down after the conversion is completed and b the ADC operates at a throughput rate of 10 ksps with a 3 MHz SCLK Given the above configuration the TS7001 s power consumption during normal operation is 2 1mW at VDD 3 V 0 7mA x 3V Since its power up delay time is 5us and its conversion plus acquisition time is 5 2US tconvert taca 14 5 X tscLK 1 5 X tscLk 15 5 x tscik the TS7001 consumes 3 5mW for 10 2us during each conversion cycle Since the conversion cycle time 100us is the reciprocal of the ADC s throughput rate 10ksps the average power consumed by the TS7001 during each conversion cycle is 10 2 100 x 2 1mW or 214 2uW The TS7001 s power consumption vs throughput rate when configured for automatic shutdown post conversion and operating on a SV supply is illustrated in Figure 8 Power Management Operating Modes Designed to provide flexible power consumption profiles the TS7001 incorporates four different operating modes to optimize the ADC s power consumption throughput rate ratio As previously described in Table 6 the four different modes of operation in the TS7001 are controlled by the PM1 TS7001 POWERS UP ON CS CS FALLING EDGE FOR PM1 AND PMO 0 DOUT DIN DATA IN
28. n however the internal 2 5 V reference voltage remains powered up While PM Mode 4 is similar to PM Mode 3 PM Mode 4 operation allows the TS7001 to power up much faster For optimal performance the Control Register s REF bit DB5 should be a zero 0 to ensure the internal reference is enabled remains enabled TS7001 Rev 1 0 Page 9 TS7001 DESCRIPTION OF OPERATION The TS7001 is a single supply low power single dual channel 12 bit successive approximation ADC with an easy to use serial interface The ADC can be operated from a 3V supply 2 7V to 3 6V When operated from either a 3V the TS7001 can operate at throughput rates up to 187 5ksps when an external 3 MHz clock is applied In a 8 pin MSOP package the TS7001 integrates a 2 5 V reference a high speed _ track hold a successive approximation ADC and a serial digital interface An external serial clock is used to transfer data to from the ADC and controls the TS7001 s conversion process The TS7001 can be configured for single or two channel operation When configured as a single channel ADC the analog input range is O to VREF where an externally applied VREF if used can range between 1 2 V and VDD When the TS7001 is configured for two channel applications the analog input range on each channel is set internally from OV to VDD If the TS7001 is configured for single channel operation the TS7001 can be operated in a read only mode by apply
29. nal is sampled on the second low to high SCLK transition following the high to low CS transition As shown in Figure 18 system timing design should incorporate a 5 us delay between the first high to low SCLK transition and the second low to high SCLK transition after the high to low CS transition THE 13 001 REMAINS POWERED UP AT ALL TIMES FOR PM1 0 AND PMO 1 SCLK LI DOUT FOUR LEADING ZEROS CONVERSION RESULT gt DIN DATA IN EARLEN E REGISTER DATA I5 LOADED ON THE FIRST EIGHT CLOCKS M1 0 AND PMO 1 TO KEEP THE TS7001 IN MODE 2 Figure 10 TS7001 s Power Management Mode 2 Operation Diagram Page 14 TS7001 Rev 1 0 THE T57001 ENTERS SHUTDOWN AT THE END OF CONVERSION SINCE PM1 1 AND PMO DOUT FOUR LEADING ZEROS CONVERSION RESULT DIN DATA IN CONTROL REGISTER DATA IS LOADED ON THE FIRST EIGHT CLOCKS PM1 1 AND PMO 0 TS7001 THE T57001 POWERS UP FROM SHUTDOWN ON SCLK FALLING EDGE s SINCE PM1 1 AND PMO 0 ti 5s FOUR LEADING ZEROS CONVERSION RESULT DATA IN PM1 1 AND PMO 015 LOADED TO KEEP THE TS7001 IN THIS MODE Figure 11 TS7001 s Power Management Mode 3 Operation Diagram for Slow SCLK Microcontrollers THE T57001 ENTERS SHUTDOWN AT THE END OF CONVERSION SINCE PM1 1AND PMO 0 THE TS7001 BEGINS TO POWER UP FROM SHUTDOWN THE TS 7001 REMAINS POWERED UP SINCE PM1 0 AND PMO 1 THE TS7001 ENTERS SHUTDOWN AT THE END OF CONVERSION SINCE PMI
30. nd upon the amount of total harmonic distortion THD that can be tolerated in the application THD will increase as the source impedance increases Figure 6 TS7001 THD vs Analog Input Frequency O 60 m O Z 6 65 fr O 70 U Q O 15 Z O 80 RIN 100 CIN 10nF z 85 5 RIN 500 CIN 2 2nF an 90 0 2 10 20 30 40 50 60 70 80 90 INPUT FREQUENCY kHz TS7001 Rev 1 0 Page 11 TS7001 SILICON LABS and performance will degrade Figure 6 illustrates how the TS7001 s harmonic performance as a function of frequency is affected by different source impedances The TS7001 s Internal 2 5 V Reference Using the REF bit the DB5 bit in the TS7001 s Control Register the TS7001 s_ internal 2 5 V reference can be enabled DBS cleared to O or disabled DB5 set to 1 If enabled the default condition the internal voltage reference can be used in applications for other purposes and if this is desired the reference should be buffered by an external precision op amp If an external precision voltage reference is used instead of the TS7001 s internal reference the internal reference is automatically overdriven In this case the TS7001 s internal reference should be disabled by setting the REF bit in the control register When the internal reference is disabled switch SW1 as shown in Figure 7 opens and the input impedance seen at the AIN1 VREF pin is the reference buffer
31. nee Motorola s MC68HC11 is shown in Figure 18 The microcontrollers serial peripheral interface SPI is configured for Master Mode MSTR 1 with its Clock Polarity Bit CPOL set to 1 and Clock Phase Bit CPHA set to 1 Serial data transfer from the TS7001 to the 68HC11 requires two 8 bit transfers and the 68HC11 s SPI is configured by writing to the SPI Control Register GPCR consult the 68HC11 User Manual for more information TS7001 MC68HC11 MOSIPD3 Additional pins omitted for clarity Figure 18 Interfacing the TS7001 to 68HC11 type Microcontrollers A TS7001 to 8051 Microcontroller Interface Using the parallel port of legacy 8051 type or equivalent microcontrollers a serial interface to the TS7001 can be designed as shown in Figure 19 As a result full duplex serial transfer to be T57001 Additional pins omitted for clarity Figure 19 Interfacing the TS7001 to Legacy 8051 type Microcontrollers implemented The technique involves bit banging one of the the microcontrollers I O ports for TS7001 Rev 1 0 TS7001 SILICON LA S _A example P1 0 to generate a serial clock and using two other I O ports for example P1 1 for DOUT and operation two consecutive read write operations are required For additional information please consult P1 2 for DIN to transfer data from to the TS7001 A TS7001 to PIC16C6x PIC16C7x Microcontroller Interface As shown in Figure 20
32. ontinued Vop 2 7V to 3 6V Vrer 2 5V External internal reference unless otherwise noted fscixk 3 MHz Ta Tmn to Tmax unless otherwise noted Parameter Limit Umit Test Conditions Comments POWER REQUIREMENTS VDD 2736 Vmin OOOO Normal Mode PM Mode 2 e Pog S T l 0 85 A typ Internal reference enabled Operational f 187 5 ksps 085 2 IsAMPLE ps Nam A typ Internal reference disabled A A A SILICON LABS Using Shutdown Mode fsnupie 10 ksps PM Modes 1 and 3 0 7 0 012 SAMPLE ksps Standby Mode mA max VDD 2 7V to 3 6V Shutdown Mode VDD 2 7V to 3 6V Normal Mode Power Dissipation VDD W _ m m Using Standby Mode PM Mode 4 fsampLe 50 ksps l m Shutdown Power Dissipation uW max Standby Power Dissipation VDD Note 1 The TS7001 s temperature range is 40 C to 85 C Note 2 SNR calculation includes distortion and noise components Note 3 Sample tested at T 25 C to ensure compliance Note 4 All digital inputs at GND except for CS at Vpp All digital outputs are unloaded Analog inputs are connected to GND Note 5 SCLK is at GND when SCLK is off All digital inputs are at GND except for CS at VDD All digital outputs are unloaded Analog inputs are connected to GND Page 4 TS7001 Rev 1 0 TS7001 SILICON LABs EOE TIMING SPECIFICATIONS Vop 2 7V to 3 6V Ta Twin to Tmax unless otherwise noted Parameter timi um J
33. onversion is also initiated on ihis transition The conversion process takes an additional 14 5 SCLK cycles to complete After the conversion is completed a subsequent low to high CS transition sets the serial data bus back into a high Z or three state condition A new conversion can be initiated if the CS signal is left low In dual channel operation the current conversion result is associated to the selected analog channel programmed during the previous write cycle to the control register Therefore in dual channel operation the system code design must perform a channel address write for the next conversion while the current conversion is in progress Writing serial data to the Control Register always takes place and occurs on the first eight low to high teonvERT HIGH Z Figure 14 TS7001 s Detailed Serial Interface Timing Diagram Page 16 TS7001 Rev 1 0 TS7001 SILICON mm SCLK transitions However the TS7001 can be configured as a read only device by physically loading all zeros 0 s into the Control Register every time by applying a logic LOW to the DIN pin at all times or by hard wiring the DIN pin to GND When the TS7001 is configured in WRITE READ modes system code design must be designed always to load the correct data onto the DIN line when reading data from the TS7001 Sixteen serial clock cycles are required to perform the conversion process and to transfer data to access
34. ration Diagram TS7001 Rev 1 0 Page 13 TS7001 icon LABS driving the CS pin from one of the host processor s port lines and ensuring that the serial data read from the microcontroller s serial port is not initiated for at least 5us In DSP applications where the CS signal is derived typically from the DSP s serial frame synchronization port it is usually not possible to separate a high to low CS transition and a second low to high SCLK transition by up to 5us without affecting the DSP system serial clock speed Therefore system timing design should incorporate a WRITE to the TS7001 s control register to terminate PM Mode 1 operation and program the ADC into PM Mode 2 that is by writing PM1 PMO 0 1 into the TS7001 s control register To get a valid conversion result a second conversion must be initiated when the ADC is powered up A WRITE operation that takes place with this second conversion can program the ADC back into PM Mode 1 where the power down operation is enabled when the CS pin is toggled high Power Management Mode 2 Operation PM1 PMO 0 1 Regardless of the status of the CS signal the TS7001 remains fully powered up in this mode of operation PM Mode 2 should be used for fastest throughput rate performance because the system timing design does not need to incorporate the TS7001 s 5 us power up delay time Figure 10 shows the general operating diagram for the TS7001 in PM Mode 2
35. s input AINT VREF TO CDAC Figure 7 TS7001 s Integrated 2 5 V VREF Circuitry impedance approximately in the gigaohm range GQ When the internal reference is enabled the input impedance at the AIN1 VREF pin is typically 10kQ When the TS7001 is configured for two channel operation the TS7001 s reference is set internally to VDD TS7001 s Power Down Operating Modes The TS7001 provides flexible power management to allow the user to achieve the best power performance for a given throughput rate The four power management options are selected by programming the TS7001 s power management bits PM Bits PM1 and PMO in the control register as summarized in Table 6 When the PM bits are programmed for either of the auto power down modes PM Mode 3 or 4 the TS7001 is powered down on the 16th low to high SCLK transition after a high to low CS transition The first high to low SCLK transition after a high to low CS transition powers Page 12 up the 1TS7001 again When the TS7001 is programmed in PM Mode 1 i e PM1 PMO 0 0 the default condition the TS7001 is powered down on a low to high CS transition and powers up from shutdown on a high to low CS transition If the CS pin is toggled low to high during the conversion in this operating mode the ADC is immediately powered down Cold Start and Standby Power Up Delay Times When VDD is first applied to the TS7001 in other words from cold
36. sibility for errors and omissions and disclaims responsibility for any consequences resulting from the use of information included herein Additionally Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters Silicon Laboratories reserves the right to make changes without further notice Silicon Laboratories makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Silicon Laboratories products are not designed intended or authorized for use in applications intended to support or sustain life or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders Page 20 Silicon Laboratories Inc TS7001 Rev 1 0 400 West Cesar Chavez Au
37. start up the ADC powers up in PM Mode 1 PM1 PMO 0 0 Upon a subsequent high to low CS transition the TS7001 s power up delay time is approximately 5us When using an external voltage reference in single channel operation or when the TS7001 is powered up from standby mode PM Mode 4 its power up delay time is approximately 1us because the internal reference has been either disabled refer to Control Register DB5 or the internal reference has remained powered up via PM Mode 4 Since the TS7001 s power up delay time PM Mode 4 is very short powering up the ADC and executing a conversion with valid results in the same read write operation is feasible TS7001 Power Consumption vs Throughput Rate Considerations In operating the TS7001 in auto shutdown mode PM Mode 3 in auto standby mode PM Mode 4 or in PM Mode 1 the average power drawn by the TS7001 decreases at lower throughput rates As shown in Figure 8 the average power drawn from Figure 8 TS7001 Power Consumption vs Throughput Rate 10 n Se ee ee ee OI T T T T E 5 Fri 2 2 VDD 3V O BR SCLK 3MHz O LJ u q S a ad oe O P P a O J J T oo tt O 20 40 60 80 100 120 140 160180 THROUGHPUT RATE ksps TS7001 Rev 1 0 TS7001 SILICON LA S_ AA the supplies by the ADC is commensurately reduced the longer the TS7001 remains in a powered down state For example consider the fol
38. stin TX 78701 1 512 416 8500 www silabs com SILICON LABS About Pre eni Bei simpy Do you have an innovative idea to lt S keep the world lle Mi connected gt id Explore Our Featured Products Energy friendly solut for a Smarter mor Microcontrollers Wireless amp RF Pomer i vein energy fre Smart Connected Energy Friendly Products Quality Support and Community www silabs com products www silabs com quality community silabs com Disclaimer Silicon Laboratories intends to provide customers with the latest accurate and in depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products Characterization data available modules and peripherals memory sizes and memory addresses refer to each specific device and Typical parameters provided can and do vary in different applications Application examples described herein are for illustrative purposes only Silicon Laboratories reserves the right to make changes without further notice and limitation to product information specifications and descriptions herein and does not give warranties as to the accuracy or completeness of the included information Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein This document does not imply or express copyright licenses granted hereunder to design or fabr
39. the connection between the TS7001 and the PIC16C6x PIC16C7x is simple and does not require any glue logic circuits The PIC16C6x synchronous serial port SSP is configured as an SPI master with its clock polarity bit set to 1 by writing to the synchronous serial port control register SSPCON In this example I O port RA1 is being used to generate the TS7001 s CS signal Since this microcontroller family only transfers eight bits of data during each serial transfer APPLICATIONS INFORMATION Ground Plane Management and Layout For best performance printed circuit boards should always be used and wire wrap boards are not recommended Good PC board layout techniques ensure that digital and analog signal lines are kept separate from each other analog and digital especially clock lines are not routed parallel to one another and high speed digital lines are not routed underneath the ADC package A contiguous analog ground plane should be routed under the TS7001 to avoid digital noise coupling A single point analog ground star ground point should be created at the ADC s GND and separate from any digital logic ground All analog grounds as well as the ADC s GND pin should be connected to the star ground No other digital system ground should be made to this ground connection For lowest noise operation the ground return to the star ground s power supply should be low impedance and as short as possible TS7001 Rev 1 0 the P
40. voltage range on AIN1 is 0 to VDD Analog Input Channel 0 In single channel operation AINO is the TS7001 s analog input with an input voltage range of OV to VREF In two channel operation the AINO pin exhibits an analog input range of OV to VDD Serial Data Input Serial data to be loaded into the TS7001 s control register is applied at the DIN pin Serial data is loaded into the ADC from the host processor on low to high SCLK transitions see the Control Register section for additional information Configuring the TS7001 as a single channel read only ADC can be achieved by hard wiring the DIN pin to GND or by applying a logic LOW at all times at the DIN pin Serial Data Output The TS7001 s conversion result is available on this pin Serial data is transferred out of the TS7887 on high to low transitions of SCLK The 12 bit conversion result is comprised of four leading zeros followed by the 12 bits of conversion data formatted MSB first Thus a total of 16 SCLK high to low transitions transfers the conversion result to the host processor as shown in the corresponding timing diagram of Figure 14 Serial Clock Input SCLK is used for 3 purposes a to load serial data from the host processor into the TS7001 s control register on low to high SCLK transitions b to transfer the 12 bit conversion result to the host processor on high to low SCLK transitions and c to control the TS7001 s conversion process ILICON LABS O e

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