Home

MIPS32™ 4KE™ Processor Cores Software User`s Manual

1. opcode bits 13 11 0 1 2 3 4 5 6 7 bits 15 14 000 001 010 011 101 111 0 00 ADDIUSP ADDIUPC B JAL X 6 BNEZ SHIFT 6 p 1 Ol RRI A 6 ADDIU8 SLTI SLTIU I8 LI CMPI B 2 10 LB LH Lwsp LW LBU LHU LWPC p 3 11 SB SH SWSP SW RRR A RR6 EXTEND 6 p 1 The ADDIUSP opcode is used by the ADDIU rx sp immediate instruction 2 The ADDIUPC opcode is used by the ADDIU rx pc immediate instruction 3 The ADDIUS opcode is used by the ADDIU rx immediate instruction 4 The LWSP opcode is used by the LW rx offset sp instruction 5 The LWPC opcode is used by the LW rx offset pc instruction 6 The SWSP opcode is used by the SW rx offset sp instruction Table 12 3 MIPS16 JAL X Encoding of the x Field Table 12 4 MIPS16 SHIFT Encoding of the f Field f bits 1 0 1 The ADDIU function is used by the AD DIU ry rx immediate instruction Table 12 6 MIPS16 I8 Encoding of the funct Field funct bits 10 8 7 000 001 010 011 100 101 110 111 BTEQZ BTNEZ SWRASP ADJSP SVRS8 MOV32R MOVR32 1 The SWRASP function is used by the SW ra offset sp instruction 2 The ADJSP function is used by the ADDIU sp immediate instruction 3 The MOV32R function is used by the MOVE r32 rz instruction 4 The MOVR32 function is used by the MOVE ry r32 instruction MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies In
2. i A sE Bun i Instruction Decode M sE Bypass i Register file read 7 l Instruction Address Calculation stage 1 and 2 Cache heor Alon Arithmetic Logic and Shift operations i L Align RegW Data Address Calculation D Cache Tag and Data read l l g i 1 act 1 aca l i Load data aligner l A gt E Bypass i Register file write mu MDU Res RegWl l MUL instruction i i i i Multiply Multiply Acc And Divide l l Result can be read from MDU i Multiply Div MDU Res i i l i One or more cycles i l 1 i Figure 2 3 4KEp Core Pipeline Stages 12 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 2 1 Pipeline Stages 2 1 1 I Stage Instruction Fetch During the Instruction fetch stage e An instruction is fetched from the instruction cache The I TLB performs a virtual to physical address translation 4KEc core only e MIPS16e instructions are converted into MIPS32 like instructions 2 1 2 E Stage Execution During the Execution stage Operands are fetched from the register file Operands from the M and A stage are bypassed to this stage The Arithmetic Logic Unit ALU begins the arithmetic or logical operation for register to register instructions The ALU calculates the data virtual address for load and store ins
3. sess 17 Figure 2 7 MDU Pipeline Flow During a 32x16 Multiply Operation essere nennen enne 18 Figure 2 8 MDU Pipeline Flow During a 32x32 Multiply Operation essere 18 Figure 2 9 MDU Pipeline Flow During a 8 bit Divide DIV Operation seen 19 Figure 2 10 MDU Pipeline Flow During a 16 bit Divide DIV Operation eene 19 Figure 2 11 MDU Pipeline Flow During a 24 bit Divide DIV Operation eene 19 Figure 2 12 MDU Pipeline Flow During a 32 bit Divide DIV Operation eene 20 Figure 2 13 4KEp MDU Pipeline Flow During a Multiply Operation sese 21 Figure 2 14 4KEp MDU Pipeline Flow During a Multiply Accumulate Operation esee 21 Figure 2 15 4KEp MDU Pipeline Flow During a Divide DIV Operation eene 22 Figure 2 16 IU Pipeline Branch Delay AAA 22 Figure 2 172 10 Pipeline Data bypass tt ettet ete sues ee Rn e e bete epson teet eee eec 23 Figure 2 18 IU Pipeline M to E bypass eene en nete Sr SEEEN entre tren tente ero nete nennt ene enne tne ene 23 Figure 2 197 IU Pipeline A to E Data bypass iere ete iren pen eee dp eere ns 24 Figure 2 20 IU Pipeline Slip after a MEDIA 24 Figure 2 21 Coprocessor 2 Interface Transactong eene enne E enne aE RaR tentent e kia 25 Figure 2 22 Instruction Cache Miss Sim 27 Figure 3 1 Address Translation During a Cache Access in the 4KEC come 34 Fig
4. Fields ss RM Read Name Bit s Description Write Reset State Res 31 Must be written as zero returns zero on read R 0 Indicates that ASID compares are supported in data breakpoints AKEc core 1 ASID 30 R 0 Not supported 4KEm p cores 0 1 Supported Res 29 28 Must be written as zero returns zero on read R 0 BCN 27 24 Number of data breakpoints implemented R 2 or 1 Res 23 2 Must be written as zero returns zero on read R 0 Break status for breakpoint n is at BS n with n from 0 BS 1 0 to 1 The bit is set to 1 when the condition for the R WO Undefined corresponding breakpoint has matched Note a Based on actual hardware implemented Note b In case of only 1 data breakpoint bit 1 become reserved MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 2 Hardware Breakpoints 9 2 9 2 Data Breakpoint Address n DBAn Register Compliance Level Implemented only for implemented data breakpoints The Data Breakpoint Address n DBAn register has the address used in the condition for data breakpoint n DBAn Register Format 31 0 DBA Table 9 14 DBAn Register Field Descriptions Fields Read Name Description Write Reset State DBA 31 0 Data breakpoint address for condition R W Undefined MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 181 Copyright 2000 200
5. 123 Table 7 2 Instruction and Data Cache Sizes Cache Size bytes Way Organization Options OK No cache 1K One 1K way One 2K way 2K Two 1K ways 3K Three 1K ways One 4K way 4K Two 2K ways Four 1K ways 6K Three 2K ways One 8K way 8K Two 4K ways Four 2K ways 12K Three 4K ways One 16K way 16K Two 8K ways Four 4K ways 24K Three 8K ways Two 16K ways 32K Four 8K ways 48K Three 16K ways 64K Four 16K ways 154 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 7 2 Cache Protocols 7 2 Cache Protocols This section describes cache organization attributes and cache line replacement for the instruction and data caches This section also discusses issues relating to virtual aliasing 7 2 1 Cache Organization The instruction and data caches each consist of three arrays tag data and way select The caches are virtually indexed since a virtual address is used to select the appropriate line within each of the three arrays The caches are physically tagged as the tag array contains a physical not virtual address The tag and data arrays hold n ways of information per set corresponding to the n way set associativity of the cache where n can be between 1 and 4 for a cache in a 4KE core The way select array holds information to choose the way to be filled as well as dirty bits in the case of the data cache Figure 7 1 on page 155
6. Table 5 22 Cause Register Field Descriptions Fields Read Name Bits Description Write Reset State Indicates whether the last exception taken occurred in a branch delay slot BD 31 Not in delay slot R Undefined In delay slot The processor updates BD only if Statusgy was zero when the exception occurred Timer Interrupt This bit denotes whether a timer interrupt is pending analogous to the IP bits for other interrupt types Meaning TI 30 R Undefined No timer interrupt is pending Timer interrupt is pending The state of the TI bit is available on the external core interface as the S7 Timerlnt signal Coprocessor unit number referenced when a Coprocessor Unusable exception is taken This field CE 29 28 is loaded by hardware on every exception but is R Undefined UNPREDICTABLE for all exceptions except for Coprocessor Unusable 116 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Fields Name Bits Table 5 22 Cause Register Field Descriptions Description Read Write Reset State DC PCI IV 27 26 23 Disable Count register In some power sensitive applications the Count register is not used and is the source of meaningful power dissipation This bit allows the Count register to be stopped in such si
7. Fields Read Name Bits Description Write Reset State This bit is set if a TCBCONFIGI register exists In this CFI 31 revision TCBCONFIG1 does not exist and this bit always R 0 reads zero 0 30 25 Reserved Must be written as zero returns zero on read R 0 Number of triggers implemented This also indicates the Legal values TRIG SE number of TCBTRIGx registers that exist R are 0 8 On chip trace memory size This field holds the encoded size of the on chip trace memory SZ 20 17 The size in bytes is given by 2 SZ 8 implying that the R Preset minimum size is 256 bytes and the largest is 8Mb This bit is reserved if on chip memory is not implemented Off chip Maximum Clock Ratio This field indicates the maximum ratio of the core clock to the CRMax 16 14 off chip trace memory interface clock The clock ratio R Preset encoding is shown in Table 9 31 on page 216 This bit is reserved if off chip trace option is not implemented Off chip Minimum Clock Ratio This field indicates the minimum ratio of the core clock to the CRMin 13 11 off chip trace memory interface clock The clock ratio R Preset encoding is shown in Table 9 31 on page 216 This bit is reserved if off chip trace option is not implemented MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 217 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support Table 9 33 TCBCONF
8. Extensible Mnemonic Instruction Instruction ADDIU Add Immediate Unsigned Yes CMPI Compare Immediate Yes LI Load Immediate Yes SLTI Set on Less Than Immediate Yes SLTIU Set on Less Than Immediate Unsigned Yes Table 12 15 MIPS16 Arithmetic Two or Three Operand Register Instructions Extensible Mnemonic Instruction Instruction AND Compare Move Negate 276 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 12 2 Instruction Listing Table 12 15 MIPS16 Arithmetic Two or Three Operand Register Instructions Extensible Mnemonic Instruction Instruction SLT Set on Less Than No SLTU Set on Less Than Unsigned SUBU Subtract Unsigned Exclusive OR ZEB Zero Extend Byte No ZEH Zero Extend Halfword No Table 12 16 MIPS16 Special Instructions Extensible Mnemonic Instruction Instruction SDBBP Software Debug Breakpoint EXTEND Extend No Table 12 17 MIPS16 Multiply and Divide Instructions Extensible Mnemonic Instruction Instruction DVU Divide Unsigned Move From HI Move From LO Multiply Multiply Unsigned Table 12 18 MIPS16 Jump and Branch Instructions Extensible Mnemonic Instruction Instruction B Branch Unconditional Yes Branch on Equal to Zero Yes Branch on Not Equal to Zero Yes BTEQZ Branch on T
9. 0x12 TCBDATA Section 9 9 3 TCBDATA Register on page 216 Table 9 28 Registers selected by TCBCONTROLB ggG TCBCONTROLB REG field Name Reference Implemented 0 TCBCONFIG Section 9 9 4 TCBCONFIG Register Reg 0 on page 217 4 Section 9 9 5 TCBTW Register Reg 4 on page 218 5 Section 9 9 6 TCBRDP Register Reg 5 on page 219 if on chip memory exists 6 TCBWRP Section 9 9 7 TCBWRP Register Reg 6 on page 219 Otherwise No 7 TCBSTP Section 9 9 8 TCBSTP Register Reg 7 on page 219 Only the number e indicated b 16 23 TCBTRIGx Section 9 9 9 TCBTRIGx Register Reg 16 23 25 ni y gister Reg 16 23 on page 220 TCBCONFIG4 amp G are implemented 9 9 1 TCBCONTROLA Register The TCB is responsible for asserting or de asserting the trace input control signals on the PDtrace interface to the core s tracing logic Most of the control is done using the TCBCONTROLA register The TCBCONTROLA register is written by an EJTAG TAP controller instruction TCBCONTROLA 0x10 The format of the TCBCONTROLA register is shown below and the fields are described in Table 9 29 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 209 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support TCBCONTROLA Register Format 31 26 25 24 23 22 20 19 18 17 16 15 14 13 12 5 4 3 1 0 0 VModes ADW SyP TB IIOJD EJO K U ASID G Mode On Table 9 29 TCBCONTRO
10. 48 3 4 2 Memory Space To assist in controlling both the amount of mapped space and the replacement characteristics of various memory regions the 4KEc core provides two mechanisms 3 4 2 1 Page Sizes First the page size can be configured on a per entry basis to map different page sizes ranging from 4 KByte to 256 MByte in multiples of 4 optionally the 4KEc core can also support a smaller page size of 1 KByte The CPO PageMask register is loaded with the desired page size which is then entered into the TLB when a new entry is written Thus operating systems can provide special purpose maps For example a typical frame buffer can be memory mapped with only one TLB entry The 4KEc core implements the following page sizes optionally 1K 4K 16K 64K 256K 1M 4M 16M 64M 256M Software may determine which page sizes are supported by writing all ones to the CPO PageMask register then reading the value back For additional information see Section 5 2 5 PageMask Register CPO Register 5 Select 0 on page 96 To enable support of 1 KByte pages in the 4KEc core a few steps must be taken First check that small pages are implemented by reading the CPO Configsp bit If set small page sizes can be enabled by setting the ESP bit of the CPO PageGrain register See Section 5 2 6 PageGrain Register CPO Register 5 Select 1 on page 98 for more information 3 4 2 2 Replacement Algorithm The second mechanism controls th
11. shadow sets Wi Process interrupt here Get restart address Save in memory Get Status value Save in memory Save SRSCtl if changing shadow sets Get Im bits to clear for this interrupt this must include at least the IM bit for the current interrupt and may include others Clear bits in copy of Status write new value to SRSCtlpgg here W_StatusKSU W_StatusERL W_StatusEXL Clear KSU ERL EXL bits in k0 Modify mask switch to kernel mode re enable interrupts clear only KSU above write target cute an eret to clear EXL switch and jump to routine including clearing device interrupt To complete interrupt processing the saved values must be restored and the original interrupted code restarted di lw lw mtcO lw mtcO mtcO ehb eret kO k1 kO kO k1 kO StatusSave EPCSave CO Status SRSCtlSave CO EPC CO SRSCt1 4 3 1 3 External Interrupt Controller Mode Disable interrupts may not be required Get saved Status including EXL set and EPC Restore the original value Get saved SRSCtl and EPC Restore shadow sets Clear hazard Dismiss the interrupt External Internal Interrupt Controller Mode redefines the way that the processor interrupt logic is configured to provide support for an external interrupt control
12. ASID DBASIDnasip L all 1 s DBMnyggy ADDR DBAnppa amp amp all 0 s BAI amp BYTELANE The size of DBCngA and BYTELANE is 4 bits Data value compare is included in the match condition for the data breakpoint depending on the bytes BYTELANE as described above accessed by the transaction and the contents of breakpoint registers The DB no value compare is shown below DB no value compare all 1 s gt DBCngj4 DBCnga BYTELANE The size of DBCnpy y DC uer and BYTELANE is 4 bits MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 2 Hardware Breakpoints In case a data value compare is required DB no value compare is false then the data value from the data bus DATA is compared and masked with the registers for the data breakpoint The endianess is not considered in these match equations for value as the compare uses the data bus value directly thus debug software is responsible for setup of the breakpoint corresponding with endianess DB value match DATA 7 0 DBVnpgy 9 BYTELANE 0 DBCngiw o DBCngaijo amp amp DATA 15 8 DBV pavpis a L BYTELANE 1 DBChgnan 00 DBCNnparji amp amp DATA 23 16 DBVnpgv 23 16 BYTELANE 2 DBCngryjo
13. EJTAGBOOT EjtagBrk Res DM 11 4 EJTAG Break Setting this bit to 1 causes a debug exception to the processor unless the CPU was in debug mode or another debug exception occurred When the debug exception occurs the processor core clock is restarted if the CPU was in low power mode This bit is cleared by hardware when the debug exception is taken The reset value of the bit depends on whether the EJTAGBOOT indication is given or not No EJTAGBOOT indication given 0 EJTAGBOOT indication given 1 reserved Debug Mode This bit indicates the debug or non debug mode 0 Processor is in non debug mode 1 Processor is in debug mode The bit is sampled in the Capture DR state of the TAP controller Oor 1 from EJTAGBOOT Res 2 0 reserved 9 4 3 Processor Access Address Register The Processor Access Address PAA register is used to provide the address of the processor access in the dmseg and the register is only valid when a processor access is pending The length of the Address register is 32 bits and this register is selected by shifting in the ADDRESS instruction 200 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 4 EJTAG TAP Registers 9 4 3 1 Processor Access Data Register The Processor Access Data PAD register is used to provide data value to and from a processor access
14. PC of instruction Compute vector offsets as a function of the type of exception NewShadowSet lt SRSCtlygss if ExceptionType TLBRefill then vectorOffset lt 16 000 elseif ExceptionType Interrupt then if Cause y 0 then vectorOffset 1614180 else if Statuspgy 1 or Assume exception Release 2 only IntCtlyg 0 then MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 67 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 4 Exceptions and Interrupts vectorOffset c 16 200 else if Config3ygi o 1 then VecNum Causemgripir NewShadowSet lt SRSCtlreicss else VecNum VIntPriorityEncoder NewShadowSet SRSMapzipiX4i3 ru endif vectorOffset lt 164200 VecNum x IntCtlys 2 00000 endif if StatusSppy 1 or IntCtlyg 0 then endif if Cause 0 then endif elseif ExceptionType Interrupt then Update the shadow set information for an implementation of Release 2 of the architecture if ArchitectureRevision 2 2 and SRSCtlygg gt 0 and Statusgrg 0 and Statusggy 0 then SRSCtlpgg SRSCtloges SRSCtlegg NewShadowSet endif endif if Statusgy 1 then Causecg FaultingCoprocessorNumber CauSegi ccoqe ExceptionType Statuspy amp 1 Calculate the vector base address if StatuSpry 1 then vectorBase lt 164BFC0 02
15. Table A 1 Revision History Continued Revision Description Added MIPS16 bit in EJTAG Implementation register Added missing footnote in Table 2 6 on page 29 Fixed typo in LSNM field description in Table 5 34 on page 133 Correct name of ASIDsup field in description of IBS Table July 16 2001 9 7 on page 174 and DBS Table 9 13 on page 180 registers Correct name of ASIDuse field in description of IBCn Table 9 11 on page 178 and DBCn Table 9 17 on page 184 registers Added definitions of UNDEFINED and UNPREDICTABLE Added definitions of precise and imprecise exception Chapter 4 Exceptions and Interrupts on page 53 Removed common instruction descriptions Instructions with processor specific behavior are included here refer to architecture documents for others Noted that interrupts are not prioritized by the HW Changed example for long interrupt latency instruction from SYNC to uncached load August 30 2001 Added CPO PDtrace register in Chapter 5 CPO Registers Added EJTAG Trace sections in Chapter 9 EJTAG Debug Support Added FastData description to Section 9 3 Test Access Port TAP on page 187 Changed EJTAGver field from 1 gt 2 version 2 5 to 2 6 in Section 9 4 2 3 Implementation Register on page 195 Added SDDBP MIPS16 instruction to Table 12 16 Special Instructions Marked unused J AL R C encodings as reserved 01 06 October 4 2001 Removed
16. The TCBWRP register is the address pointer to on chip trace memory It points to the location where the next new TW for on chip trace will be written This register is reserved if on chip trace memory is not implemented The format of the TCBWRP register is shown below and the fields are described in Table 9 36 The value of n depends on the size of the on chip trace memory As the address points to a 64 bit TW the lower three bits are always zero TCBWRP Register Format 31 nil n 0 Address Table 9 36 TCBWRP Register Field Descriptions Fields Description Data 31 n 1 Reserved Must be written zero reads back zero 0 0 Address n 0 Byte address of on chip trace memory word R W 0 9 9 8 TCBSTP Register Reg 7 The TCBSTP register is the start pointer register This register points to the on chip trace memory address at which the oldest TW is located This pointer is reset to zero when the TCBCONTROLB 7p bit is written to 1 If a continuous trace to on chip memory wraps around the on chip memory TSBSTP will have the same value as TCBWRP MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 219 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support This register is reserved if on chip trace memory is not implemented The format of the TCBSTP register is shown below and the fields are described in Table 9 37 The value of n depends on the
17. This bit denotes to which trace buffer the trace is currently being written and is used to select the appropriate interpretation of the TraceControl2gyp field Encoding Meaning Undefined 0 Trace data is being sent to an on chip trace buffer Trace Data is being sent to an off chip trace buffer Used to indicate the synchronization period The period in cycles between which the periodic synchronization information is to be sent is defined as shown below for both when the trace buffer is on chip and off chip SyP Off chip 000 Undefined The On chip column value is used when the trace data is being written to an on chip trace buffer e g TraceControl2ypy 0 Conversely the Off chip column is used when the trace data is being written to an off chip trace buffer e g TraceControl2ypy 1 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions 5 2 31 User Trace Data Register CP0 Register 23 Select 3 A software write to any bits in the UserTraceData register will trigger a trace record to be written indicating a type 1 or type 2 user format The type is based on the UT bit in the TraceControl register This register cannot be written in consecutive cycles The trace output data is UNPREDICTABLE if this register is written in consecut
18. Vector For Release 2 Implementations assumes that EBase retains its reset Exception Statusgry Statuspyxy state and that IntCtlys 0 Reset Soft Reset NMI D X 16 BFCO 0000 EJTAG Debug D x 16 BFCO 0480 EJTAG Debug D D 164 FF20 0200 TLB Refill 0 0 16 8000 0000 TLB Refill 0 1 16 8000 0180 TLB Refill 1 0 16 BFCO 0200 TLB Refill 1 1 16 BFCO 0380 Interrupt 0 0 16 8000 0180 Interrupt 0 0 16 8000 0200 Interrupt 1 0 16 BFCO 0380 Interrupt 1 0 1 x 16 BFCO 0400 All others 0 x D D 16 8000 0180 All others 1 x x x 16 BFCO 0380 x denotes don t care 22 on page 116 The value loaded into Copyright 2000 2002 MIPS Technologies Inc All rights reserved 4 6 General Exception Processing in the delay slot of a branch or jump which has delay slots Table 4 8 shows the value stored in each of the CPO PC registers including EPC For implementations of Release 2 of the Architecture if Statusggy 0 the CSS field in the SRSCtl register is copied to the PSS field and the CSS value is loaded from the appropriate source If the EXL bit in the Status register is set the EPC register is not loaded and the BD bit is not changed in the Cause register For implementations of Release 2 of the Architecture the SRSCtl register is not changed Table 4 8 Value Stored in EPC ErrorEPC or DEPC on an Exception MIPS16 In Branch Jump Implemented Delay Slot Value stored in EPC ErrorEPC DEPC No No Address of the instruction
19. When the bit is set to 1 then it is only guaranteed that this setting has taken effect in the system when the read value of this bit is also 1 This is to ensure that the setting from the TCK clock domain gets effect in the CPU clock domain and in peripherals When the bit is written to 0 then the bit must also be read as 0 before it is guaranteed that the indication is cleared in the CPU clock domain also This bit controls the EI PrRst signal If the signal is used in the system then it must be ensured that both the processor and all devices required for a reset are properly reset Otherwise the system may fail or hang The bit resets itself since the EJTAG Control register is reset by hard or soft reset Probe Enable This bit indicates to the CPU if the EJTAG memory is handled by the probe so processor accesses are answered 0 The probe does not handle EJTAG memory transactions 1 The probe does handle EJTAG memory transactions It is an error by the software controlling the probe if it sets the ProbTrap bit to 1 but resets the ProbEn to 0 The operation of the processor is UNDEFINED in this case The ProbEn bit is reflected as a read only bit in the The read value indicates the effective value in the DCR due to synchronization issues between TCK and CPU clock domains however it is ensured that change of the ProbEn prior to setting the EjtagBrk bit will have effect for the debug handler executed due to the debug
20. ndex Writeback Invalidate Least recently used Index Load Tag No update Index Store Tag WST 0 Most recently used if valid bit is set in TagLo CPO register Least recently used if valid bit is cleared in TagLo CPO register Index Store Tag WST 1 Update the field with the contents of the TagLo CPO register refer to Table 7 5 Table 7 6 or Table 7 7 for the valid values of this field Index Store Data No update Hit Invalidate Least recently used if a hit is generated otherwise unchanged Fill Most recently used Hit Writeback Invalidate Least recently used if a hit is generated otherwise unchanged Hit Writeback No update Fetch and Lock Most recently used If all ways are valid then any locked ways will be excluded from consideration for replacement For the unlocked ways the LRU bits are used to identify the way which has been used least recently and that way is selected for replacement If all ways are locked Fill data will not fill into the cache and Write back stores turn into Write through Write allocate stores If the way selected for replacement has its dirty bit asserted in the way select array then that 16 byte line will be written back to memory before the new fill can occur 7 2 4 Virtual Aliasing Since the caches are virtually indexed and physically tagged a potential issue referred to as virtual aliasing might exist Virtual aliasing occurs if the virtual bits used to index a cache array
21. 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions 5 2 3 EntryLo0 and EntryLol1 Registers CPO Registers 2 and 3 Select 0 The pair of EntryLo registers act as the interface between the TLB and the TLBR TLBWI and TLBWR instructions For a TLB based MMU EntryLo0 holds the entries for even pages and EntryLo holds the entries for odd pages The contents of the EntryLoO and EntryLol registers are undefined after an address error TLB invalid TLB modified or TLB refill exception These registers are only valid with the TLB 4KEc core They are reserved if the FM is implemented 4KEm and 4KEp Figure 5 3 EntryLo0 EntryLol Register Format 31 30 29 26 25 6 5 3210 R 0 PFN C D V G Table 5 5 EntryLo0 EntryLol Register Field Descriptions Read Description Write Reset State Reserved Should be ignored on writes returns zero on reads These 4 bits are normally part of the PFN however since the core supports only 32 bits of physical address the PEN R W is only 20 bits wide therefore bits 29 26 of this register must be written with zeros Page Frame Number Contributes to the definition of the high order bits of the physical address If the processor is enabled to support 1KB pages Config3sp 1 and PageGraingsp 1 the PFN field corresponds to bits 29 10 of the physical address the field is shifted left by 2 bits relative to the Release 1 definition Undefined to
22. 4KE Processor Cores Software User s Manual Revision 02 00 53 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 4 Exceptions and Interrupts execution It also ensures that exceptions are taken in the order of execution an instruction taking an exception may itself be killed by an instruction further down the pipeline that takes an exception in a later cycle 4 2 Exception Priority Table 4 1 lists all possible exceptions and the relative priority of each highest to lowest Several of these exceptions can happen simultaneously in that event the exception with the highest priority is the one taken Table 4 1 Priority of Exceptions Exception Description Reset Assertion of SI ColdReset signal Soft Reset DSS DINT Assertion of SI Reset signal EJTAG Debug Single Step EJTAG Debug Interrupt Caused by the assertion of the external EJ DINT input or by setting the EjtagBrk bit in the ECR register NMI Machine Check Interrupt Deferred Watch Asserting edge of SI NMI signal TLB write that conflicts with an existing entry 4KEc core Assertion of unmasked hardware or software interrupt signal Deferred Watch unmasked by KIDM gt KIDM transition DIB EJTAG debug hardware instruction break matched WATCH A reference to an address in one of the watch registers fetch Fetch address alignment error AdEL User mode fetch reference to kernel addres
23. Chapter 6 Hardware and Software Initialization 152 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 7 Caches This chapter describes the caches present in a MIPS32 4KE processor core It contains the following sections Section 7 1 Cache Configurations Section 7 2 Cache Protocols Section 7 3 Instruction Cache Section 7 4 Data Cache Section 7 5 CACHE Instruction Section 7 6 Software Cache Testing Section 7 7 Memory Coherence Issues 7 1 Cache Configurations A 4KE processor core supports separate instruction and data caches which may be flexibly configured at build time for various sizes organizations and set associativities The use of separate caches allows instruction and data references to proceed simultaneously Both caches are virtually indexed and physically tagged allowing cache access to occur in parallel with virtual to physical address translation The instruction and data caches are independently configured For example the data cache can be 2 KB in size and 2 way set associative while the instruction cache can be 8 KB in size and 4 way set associative Each cache is accessed in a single processor cycle Cache refills are performed using a 4 word fill buffer which holds data returned from memory during a 4 beat burst transaction The critical miss word is always returned first
24. Copyright 2000 2002 MIPS Technologies Inc All rights reserved 183 Chapter 9 EJTAG Debug Support 9 2 9 5 Data Breakpoint Control n DBCn Register Compliance Level Implemented only for implemented data breakpoints The Data Breakpoint Control n DBCn register controls the setup of data breakpoint n DBCn Register Format 24 23 22 18 17 14 13 12 11 4 3 2 1 Table 9 17 DBCn Register Field Descriptions Fields Name Bits Description Read Write Reset State Res 31 24 Must be written as zero returns zero on reads R 0 Use ASID value in compare for data breakpoint n 4Kc core R W ASIDuse 23 0 Don t use ASID value in compare 4Km 4Kp Undefined 1 Use ASID value in compare cores 0 Res 22 18 Must be written as zero returns zero on reads R 0 Byte access ignore controls ignore of access to a specific byte BAI 0 ignores access to byte at bits 7 0 of the data bus BAI 1 ignores access to byte at bits BAI 017514 5 8 etc R W Undefined 0 Condition depends on access to corresponding byte 1 Access for corresponding byte is ignored Controls if condition for data breakpoint is not fulfilled on a store transaction Nose p 0 Condition may be fulfilled on store transaction Undefined 1 Condition is never fulfilled on store transaction Controls if condition for data breakpoint is not fulfilled on a load transaction NO 12 0 Condition may be fulfilled on load transaction Ry Undefined 1 Condi
25. No Yes Address of the branch or jump instruction PC 4 Yes No Upper 31 bits of the address of the instruction combined with the ISA Mode bit Upper 31 bits of the branch or jump instruction PC 2 in Yes Yes the MIPS16 ISA Mode and PC 4 in the 32 bit ISA Mode combined with the SA Mode bit The CE and ExcCode fields of the Cause registers are loaded with the values appropriate to the exception The CE field is loaded but not defined for any exception type other than a coprocessor unusable exception The EXL bit is set in the Status register The processor is started at the exception vector The value loaded into EPC represents the restart address for the exception and need not be modified by exception handler software in the normal case Software need not look at the BD bit in the Cause register unless it wishes to identify the address of the instruction that actually caused the exception Note that individual exception types may load additional information into other registers This is noted in the description of each exception type below Operation If Statusgy is 1 all exceptions go through the general exception vector and neither if Statuspy 1 then vectorOffset 1614180 else EPC nor Causegp nor SRSCtl are modified if InstructionInBranchDelaySlot then else EPC restartPC Causegp amp 0 endif EPC restartPC PC of branch jump Causegp amp 1
26. mfcO k0 CO_EPC Get restart address sw k0 EPCSave Save in memory mfcO k0 CO Status Get Status value SW k0 StatusSave Save in memory li kl IMbitsToClear Get Im bits to clear for this interrupt this must include at least the IM bit for the current interrupt and may include fe others and k0 k0 k1 Clear bits in copy of Status ins k0 zero S StatusEXL W_StatusKSU W_StatusERL W_StatusEXL Processor Cores Software User s Manual Revision 02 00 57 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 4 Exceptions and Interrupts Clear KSU ERL EXL bits in k0 mtcO0 k0 CO Status Modify mask switch to kernel mode re enable interrupts Process interrupt here including clearing device interrupt In some environments this may be done with a thread running in kernel or user mode Such an environment is well beyond the scope of this example To complete interrupt processing the saved values must be restored and the original interrupted code restarted di Disable interrupts may not be required lw k0 StatusSave Get saved Status including EXL set lw k1 EPCSave pE and EPC mtco k0 CO Status Restore the original value mtcO0 k1 CO EPC and EPC Restore GPRs and software state eret Dismiss the interrupt 4 3 1 2 Vectored Interrupt Mode
27. tette ERO qoe i Seege e 4 1 21 Required Logie Blocks coa ee ege EE 5 1 22 Optional Eogic EE 8 Chapter 2 Pipeline aen ee eee e eei Ure RR peu 11 24 Pipeline Stages inside tee elie Ne aie eO eon y Rae NE Raa eb tedio ad 11 2 1 T Stage Instruction Fetch 2 or ete et e eter al ee 13 2 1 2 E Stage EXECU O i ede peel ees 13 2 1 3 Mi Stage Memory bech iiu eter etum conten ten Eee eredi enu tee eb CENE 13 2 14 A Stage Align EE 13 2 1 5 W Stage Wirtteback 5i eR tri e ee aret et e etes 14 2 2 Instruction Cache Miss roto d crite eee ee a tei E ee Sie den alee eae 14 2 3 Data Cache MiSS 32 uidi Eaedem ire e ore I AEN 14 2 4 Multiply Divide Operations oer e uree ee nennen nenne tnnt innen eren nen nete ettet tren nennen EE ESETET E 15 2 3 MDU Pipeline 4KEC and AK Em Cores pemanenan evs eet P toute urere deer vcasth este eeh edd v eue 15 2 5 1 32x16 Multiply 4KEc amp 4KEm Cores essere nennen nennen nennen nennen etre treni 18 2 35 2 32x32 Multiply AK Ec AKEM Cores sett eter te reme e d eee edito eive eve tot 18 2 5 3 Divide 4KEc amp AKEm Cores tecti tte teede i erect bleed eene dedic eie e Dese eec eos Pee e eo aede 19 2 6 MDU Pipehne AKEp Core 5 eor ire ent ete deed eck SE ed eis Me SE 20 2 6 1 Multiply A4KEp Core ener ode re San Siva ie ER e ase pee e a indes 21 2 6 2 Multiply Accumulate AK Ep Cote erre teer tare m SEENEN seres oe uen e 21 2 6 5 Divide
28. 2 010 COPO 3011 Special2 4 100 5 101 6 110 7 111 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 237 Chapter 11 MIPS32 4KE Processor Core Instructions 238 Table 11 2 Special Opcode encoding of Function Field function bits 2 0 0 1 2 3 4 5 6 7 bits 5 3 010 m 0 000 SLLV ores OES 1 001 SYSCALL a SYNC 2 Toro MFLO mio e a 3 pon pv pw e a 4 100 AND XOR NOR 5 101 o o 6 110 TNE o 7 111 o n function bits 2 0 bits 5 3 0 000 1 001 2 010 1 UDI or o 3 O11 4 100 5 101 6 110 7 111 1 CorExtend instructions are a build time option of the 4KE Pro cores if not implemented this instructions space will cause a reserved instruction exception If assembler support exists the mnemonics for CorExtend instructions are most likely UDIO UDI UDII5 function Table 11 4 Special3 Opcode Encoding of Function Field bits 2 0 ALD A Ww N R o MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 11 2 MIPS32 4KE Opcode Map Table 11 5 RegImm Encoding of rt Field 7 010 011 100 101 111 1501 T
29. ADDI Integer Add Immediate Rt Rs Immed ADDIU Unsigned Integer Add Immediate Rt Rs y Immed ADDU Unsigned Integer Add Rd Rs y Rt AND Logical AND Rd Rs amp Rt ANDI Logical AND Immediate Rt Rs amp 046 Il Immed Unconditional Branch Ls B Assembler idiom for BEQ r0 rO offset PC intoffset BAL Branch and Link GPR 31 PC 8 Assembler idiom for BGEZAL 10 offset PC int offset BC2F Branch On COP2 Condition False Ce n if COP2Condition cc BC2FL Branch On COP2 Condition False Likely P rag Ignore Next Instruction x if COP2Condition cc BC2T Branch On COP2 Condition True PC int offset if COP2Condition cc BC2TL Branch On COP2 Condition True Likely Pm Ignore Next Instruction if Rs Rt BEQ Branch On Equal PC int offset Copyright 2000 2002 MIPS Technologies Inc All rights reserved 11 3 MIPS32 Instruction Set for the 4KE core Instruction Table 11 10 Instruction Set Continued Description Function BEQL BGEZ BGEZAL BGEZALL BGEZL BGTZ Branch On Equal Likely Branch on Greater Than or Equal To Zero Branch on Greater Than or Equal To Zero And Link Branch on Greater Than or Equal To Zero And Link Likely Branch on Greater Than or Equal To Zero Likely Branch on Greater Than Zero if Rs Rt PC int offset else Ignore Next Instruction if Rs 31 PC int offset GPR 31 PC 8 if Rs 31 PC int offset GPR 31 PC 8 if Rs 31
30. AK Bp Core EE 21 PAM Branche SM cog ehsesdecestasutiens tege EE cue chestvess au Edge A EE EEEE 22 2 8 Data Bypassing i eee Ph ode sS 22 2 82 1 Load Delay E EE 23 2 8 2 Move from HI LO and CPO Delay essent een enne entre menn neeneetn retener tree nennen 24 2 9 C OpFOCesSSOE2 ee EE 24 2 10 Interlock Handlimg 4 root ein eai een eee ea ROS 25 SST pelt terre eeh ee temi iei ten e Reo et me ie pire iR rede 26 2 12 Instruction Interlocks ete pereo idee Eae etg ette iiie tee 27 2 13 Hazards 3 oct e te rp de nee peret t nente tede 28 2 13 T Types Of Hazatds 2 2 S DC ea m ee odo e ee 28 2 13 2 Instruction EE 30 2 13 3 Eliminating Hazards sjoen eue HS og cole Ses EURO Deam neu 31 Chapter 3 Memory Management scine mien EERSTEN 33 3 1 Introduction i tr oe e Op ee bp e e e PED UR PEU IR te RR DE EE 33 3 2 Modes of Operation ui Ee DEELER EE EENS e ert rig e b e ees 34 32 1 Virtual Memory Segment ete e dpt RT eo RUE p dr Re 35 3 222 USer Mode niei RUE Bam UTERE ERE 37 3 2 3 Kernel Mode iuuat ea teda ete ORE d ede d RE 38 3 2 4 Debug Mode in ea et RE RU RI RI RAPERE D IEEE RE dec RE ESA EH 40 3 3 Translation Lookaside Buffer 4KEc Core Only oo eee ee eeeecsseecssecenceceeeesneeesecessecececueecsaeceaeeceeeseneeeeeeenaeeeseeeeees 42 3 3 le le RE EE 42 3 3 2 Instruction TEB 22 erede REO e EENS E EC IO OE eh 45 3 3 3 Data TLB 3 2 ec ih heh I reet tee rh Bis d es eid Pete E oec A
31. CO SRSCtl1 Save SRSCtl if changing shadow sets sw kl SRSCtlSave MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 4 3 Interrupts If switching shadow sets write new value to SRSCtlpgs here ins k0 zero S StatusEXL W StatusKSU W StatusERL W StatusEXL Clear KSU ERL EXL bits in k0 mtcO0 KO CO Status Modify IPL switch to kernel mode re enable interrupts If switching shadow sets clear only KSU above write target address to EPC and do execute an eret to clear EXL switch shadow sets and jump to routine Ki Process interrupt here including clearing device interrupt The interrupt completion code is identical to that shown for VI mode above Wi 4 3 2 Generation of Exception Vector Offsets for Vectored Interrupts For vectored interrupts in either VI or EIC interrupt mode a vector number is produced by the interrupt control logic This number is combined with IntCtlys to create the interrupt offset which is added to 16452200 to create the exception vector offset For VI interrupt mode the vector number is in the range 0 7 inclusive For EIC interrupt mode the vector number is in the range 1 63 inclusive 0 being the encoding for no interrupt The IntCtlys field specifies the spacing between vector locations If this value is zero the
32. DBCngai 2j amp amp DATA 31 24 DBVnpgy 31 24 BYTELANE 3 DBCngi3 DBCngai s The match for a data breakpoint is always precise since the match expression is fully evaluated at the time the load store instruction is executed A true DB match can thereby be indicated on the very same instruction causing the DB match to be true 9 2 6 Debug Exceptions from Breakpoints Instruction and data breakpoints may be set up to generate a debug exception when the match condition is true as described below 9 2 6 1 Debug Exception by Instruction Breakpoint If the breakpoint is enabled by BE bit in the BCn register then a debug instruction break exception occurs if the IB match equation is true The corresponding BS n bit in the BS register is set when the breakpoint generates the debug exception The debug instruction break exception is always precise so the DEPC register and DBD bit in the Debug register point to the instruction that caused the IB match equation to be true The instruction receiving the debug exception does not update any registers due to the instruction nor does any load or store by that instruction occur Thus a debug exception from a data breakpoint can not occur for instructions receiving a debug instruction break exception The debug handler usually returns to the instruction causing the debug instruction break exception whereby the instruction is executed Debug software is responsible
33. Kernel Space 3 kseg3 In Kernel mode when the most significant three bits of the 32 bit virtual address are 111 the kseg3 virtual address space is selected In the 4AKEm and 4KEp processor cores this 229 byte 512 MByte Kernel virtual space is located at physical addresses OXEO000 0000 OXFFFF_FFFF In the 4KEc processor core this space is mapped through the TLB 3 2 4 Debug Mode Debug mode address space is identical to Kernel mode address space with respect to mapped and unmapped areas except for kseg3 In kseg3 a debug segment dseg co exists in the virtual address range 0xFF20_0000 to OxFF3F_FFFF The layout is shown in Figure 3 6 on page 41 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 3 2 Modes of Operation OxFFFF FFFF OxFFA40 0000 OxFF20 0000 dseg 0x0000 0000 kseg1 ksegO Unmapped Figure 3 6 Debug Mode Virtual Address Space Mapped if mapped in Kernel Mode The deeg is sub divided into the dmseg segment at OXFF20 0000 to OxFF2F_FFFF which is used when the probe services the memory segment and the drseg segment at 0xFF30_0000 to OXFF3F FFFF which is used when memory mapped debug registers are accessed The subdivision and attributes for the segments are shown in Table 3 3 Accesses to memory that would normally cause an exception if tried from kernel mode cause the core to re ent
34. MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 4 EJTAG TAP Registers Table 9 23 EJTAG Control Register Descriptions Name Fields Read Write Description Reset State Rocc Reset Occurred The bit indicates if a hard or soft reset has occurred 0 No reset occurred since bit last cleared 1 Reset occurred since bit last cleared The Rocc bit will keep the 1 value as long as a hard or soft reset is applied R W This bit must be cleared by the probe to acknowledge that the incident was detected The EJTAG Control register is not updated in the Update DR state unless Rocc is 0 or written to 0 This is in order to ensure proper handling of processor access Psz 1 0 Processor Access Transfer Size These bits are used in combination with the lower two address bits of the Address register to determine the size of a processor access transaction The bits are only valid when processor access is pending PAA 1 0 Psz 1 0 Transfer Size Byte LE byte 0 BE byte 3 Byte LE byte 1 BE byte 2 Byte LE byte 2 BE byte 1 Byte LE byte 3 BE byte 0 Halfword LE bytes 1 0 BE bytes 3 2 Halfword LE bytes 3 2 BE bytes 1 0 Word LE BE bytes 3 2 1 0 Triple LE bytes 2 1 0 BE bytes 3 2 1 11 Triple LE bytes 3 2 1 BE bytes 2 1 0 All others Rese
35. Relative Interrupt Interrupt Calculated Generated by Priority Type Source From Priority Encoder Highest Priority IP7 and IM7 IP6 and IM6 IP5 and IM5 Hardware IP4 and IM4 IP3 and IM3 IP2 and IM2 IP1 and IMI Software Lowest Priority IPO and IMO The priority order places a relative priority on each hardware interrupt and places the software interrupts at a priority lower than all hardware interrupts When the priority encoder finds the highest priority pending interrupt it outputs an encoded vector number that is used in the calculation of the handler for that interrupt as described below This is shown pictorially in Figure 4 1 Latch Mask Encode Generate m gt IntCth pry P Any Ge Interrupt Request L Requesty Eu Statuspg 2 o ds i 3 IntCtlys HW2 3 3 ni E Exception Vector 5 E a z E Vector Offset OS el Causey SRSMap Shadow Set Number Figure 4 1 Interrupt Generation for Vectored Interrupt Mode A typical software handler for vectored interrupt mode bypasses the entire sequence of code following the IVexception label shown for the compatibility mode handler above Instead the hardware performs the prioritization dispatching directly to the interrupt processing routine Unlike the compatibility mode examples a vectored interrupt handler may take advantage of a dedica
36. Revision 02 00 205 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support Load instructions are indicated with a load flag Store instructions are indicated with a store flag Taken branches are indicated with a branch taken flag on the target instruction New PC information for a branch is only traced if the branch target is unpredictable from the static program image When branch targets are unpredictable only the delta value from current PC is traced if it is dynamically determined to reduce the number of bits necessary to indicate the new PC Otherwise the full PC value is traced When a completing instruction is executed in a different processor mode from the previous one the new processor mode is traced The first instruction is always traced as a branch target with processor mode and full PC Periodic synchronization instructions are identified with a sync flag and traced with the processor mode and full PC All the instruction flags above are combined into one 3 bit value to minimize the bit information to trace The possible processor modes are explained in Section 9 7 1 Processor Modes on page 205 The target address is statically predictable for all branch and all jump immediate instructions If the branch is taken then the branch taken flag will indicate this All jump register instructions and ERET DERET are instructions which have an unpredictable tar
37. The length of the Data register is 32 bits and this register is selected by shifting in the DATA instruction The register has the written value for a processor access write due to a CPU store to the dmseg and the output from this register is only valid when a processor access write is pending The register is used to provide the data value fora processor access read due to a CPU load or fetch from the dmseg and the register should only be updated with a new value when a processor access write is pending The PAD register is 32 bits wide Data alignment is not used for this register so the value in the PAD register matches data on the internal bus The undefined bytes for a PA write are undefined and for a PAD read then 0 zero must be shifted in for the unused bytes The organization of bytes in the PAD register depends on the endianess of the core as shown in Figure 9 4 on page 201 The endian mode for debug kernel mode is determined by the state of the S7 Endian input at power up MSB LSB bit 31 24 23 16 15 BIG ENDIAN Lait 5 Lx A n2 1 Amopo A n 2 0 Most significant byte is at lowest address Word is addressed by byte address of most significant byte MSB LSB bit 31 24 23 16 15 LITTLE ENDIAN Ain 0 7 E SS A n 2 1 A n 0 3 A n 2 0 Least significant byte is at lowest address Word is addressed by byte address of least significant byte Figure 9 4 Endian Formats for the PAD Register The si
38. This means that if a simultaneous About trigger action on the TCBCONTROLB gy bit n 2 Trace Words after the trigger and a Start trigger hit the same cycle then the About trigger wins regardless of which trigger number it is The oldest trigger takes precedence However if an About trigger has started the count down from n 2 but not yet reached zero then a new About trigger will NOT be executed Only one About trigger can have the cycle counter This second About trigger will store 11 in the TCBTRIGxy field But if the TCBTRIGXy ac bit is set a TF6 trace information will still go in the trace 9 11 5 2 OR ed trigger actions The simple trigger actions CHTro and PDTro from each trigger unit are effectively OR ed together to produce the final trigger One or more expected trigger strobes on i e TC ChipTrigOut can thus disappear External logic should not rely on counting of strobes to predict a specific event unless simultaneous triggers are known not to occur 9 12 EJTAG Trace cycle by cycle behavior A key reason for using trace and not single stepping to debug a software problem is often to get a picture of the real time behavior However the trace logic itself can when enabled affect the exact cycle by cycle behavior 9 12 1 Fifo logic in PDtrace and TCB modules Both the PDtrace module and the TCB module contain a fifo This might seem like extra overhead but there are good reasons for this The vast majority of the infor
39. Vectored Interrupt mode builds on the interrupt compatibility mode by adding a priority encoder to prioritize pending interrupts and to generate a vector with which each interrupt can be directed to a dedicated handler routine This mode also allows each interrupt to be mapped to a GPR shadow set for use by the interrupt handler Vectored Interrupt mode is in effect if all of the following conditions are true e Configyg 1 Config3 ypc 0 IntCtlys 0 e Causezy 1 Statusggy 0 In VI interrupt mode the six hardware interrupts are interpreted as individual hardware interrupt requests The timer interrupt is combined in a system dependent way external to the core with the hardware interrupts the interrupt with which they are combined is indicated by the ntCtl p7 field to provide the appropriate relative priority of the timer interrupt with that of the hardware interrupts The processor interrupt logic ANDs each of the Cause p bits with the corresponding Status bits If any of these values is 1 and if interrupts are enabled Statusyg 1 Statusgy 0 and Statusppy 0 an interrupt is signaled and a priority encoder scans the values in the order shown in Table 4 3 58 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 4 3 Interrupts Table 4 3 Relative Interrupt Priority for Vectored Interrupt Mode Interrupt Request Vector Number
40. and the PrAcc bit is unchanged Shifting out a one indicates that the access would have been successful if allowed to complete and a zero indicates the access would not have successfully completed R W Undefined processor An upload is defined as a sequence of processor loads from target memory and stores to dmseg A download is a sequence of processor loads from dmseg and stores to target memory The Fastdata area specifies the legal range of dmseg addresses OxFF20 0000 OxFF20 000F that can be used for uploads and downloads The Data Fastdata registers selected with the FASTDATA instruction allow efficient completion of pending Fastdata area accesses During Fastdata uploads and downloads the processor will stall on accesses to the Fastdata area The PrAcc processor access pending bit will be 1 indicating the probe is required to complete the access Both upload and download accesses are attempted by shifting in a zero SPrAcc value to request access completion and shifting out SPrAcc to see if the attempt will be successful Oe there was an access pending and a legal Fastdata area address was used Downloads will also shift in the data to be used to satisfy the load from dmseg s Fastdata area while uploads will shift out the data being stored to dmseg s Fastdata area As noted above two conditions must be true for the Fastdata access to succeed These are PrAcc must be 1 i e there must be
41. or otherwise MIPS Technologies does not assume any liability arising out of the application or use of this information or of any error or omission in such information Any warranties whether express statutory implied or otherwise including but not limited to the implied warranties of merchantability or fitness for a particular purpose are excluded Except as expressly provided in any written license agreement from MIPS Technologies or an authorized third party the furnishing of this document does not give recipient any license to any intellectual property rights including any patent rights that cover the information in this document The information contained in this document shall not be exported or transferred for the purpose of reexporting in violation of any U S or non U S regulation treaty Executive Order law statute amendment or supplement thereto The information contained in this document constitutes one or more of the following commercial computer software commercial computer software documentation or other commercial items If the user of this information or any related documentation of any kind including related technical data or manuals is an agency department or other entity of the United States government Government the use duplication reproduction release modification disclosure or transfer of this information or any related documentation of any kind is restricted in accordance with Federal Acquisition Reg
42. see Section 5 2 21 Config Register CPO Register 16 Select 0 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 3 2 Modes of Operation 3 2 1 2 Mapped Segments A mapped segment does use the TLB 4KEc core or the FM 4KEm and 4KEp cores to translate from virtual to physical addresses For the 4KEc core the translation of mapped segments is handled on a per page basis Included in this translation is information defining whether the page is cacheable or not and the protection attributes that apply to the page For the 4KEm and 4KEp cores the mapped segments have a fixed translation from virtual to physical address The cacheability of the segment is defined in the CPO register Config fields K23 and KU see Section 5 2 21 Config Register CPO Register 16 Select 0 Write protection of segments is not possible during FM translation 3 2 2 User Mode In user mode a single 2 GByte p bytes uniform virtual address space called the user segment useg is available Figure 3 4 on page 37 shows the location of user mode virtual address space 32 bit OxFFFF FFFF Address Error 0x8000 0000 Ox7FFF FFFF 2GB Mapped useg 0x0000 0000 Figure 3 4 User Mode Virtual Address Space The user segment starts at address 0x0000 0000 and ends at address 0x7FFF_FFFF Accesses to all other addresses cause an address error exception The p
43. since no TLB is present SP 4 R Preset Meaning Small page support is not implemented 1 Small page support is implemented 128 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Table 5 30 Config3 Register Field Descriptions Read Description Write Trace Logic implemented This bit indicates whether PC or data trace is implemented Encoding Meaning 0 Trace logic is not implemented Trace logic is implemented SmartMIPSTM ASE implemented This bit indicates whether the SmartMIPS ASE is implemented Since SmartMIPS is not present on the 4KE core this bit will always be 0 Meaning SmartMIPS ASE is not implemented SmartMIPS ASE is implemented MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 129 Chapter 5 CPO Registers 5 2 25 Load Linked Address CP0 Register 17 Select 0 The LLAddr register contains the physical address read by the most recent Load Linked LL instruction This register is for diagnostic purposes only and serves no function during normal operation Figure 5 27 LLAddr Register Format 31 28 27 0 0 PAddr 31 4 Table 5 31 LLAddr Register Field Descriptions Fields Description Reset State Must be written as zeros returns
44. the intervening branch delay slot is utilized This avoids bubbles being injected into the pipeline on branch instructions Both the address calculation and the branch condition check are performed in the E stage The pipeline begins the fetch of either the branch path or the fall through path in the cycle following the delay slot After the branch decision is made the processor continues with the fetch of either the branch path for a taken branch or the fall through path for the non taken branch The branch delay means that the instruction immediately following a branch is always executed regardless of the branch direction If no useful instruction can be placed after the branch then the compiler or assembler must insert a NOP instruction in the delay slot Figure 2 16 illustrates the branch delay One Cycle One Cycle One Cycle One Cycle One Cycle One Cycle Delay Slot Instruction Jump Target Instruction l E M A One Clock Branch Delay Figure 2 16 IU Pipeline Branch Delay 2 8 Data Bypassing 22 Most MIPS32 instructions use one or two register values as source operands These operands are fetched from the register file in the first part of E stage The ALU straddles the E to M boundary and can present the result early in M stage The result is not written to the register file before the W stage however If no precautions were made it would take 3 cycles before the re
45. 0 Interrupt request disabled 1 Interrupt request enabled In implementations of Release 2 of the Architecture in which EIC interrupt mode is enabled Config3ygc 1 these bits take on a different meaning and are interpreted as the IPL field described below Interrupt Priority Level In implementations of Release 2 of the Architecture in which EIC interrupt mode is enabled Config3ypyc 1 this field is the encoded 0 63 value of the current IPL An interrupt will be signaled only if the requested IPL is higher than this value If EIC interrupt mode is not enabled Config3yg c 0 these bits take on a different meaning and are interpreted as the IM7 IM2 bits described above 1 for NMI 0 otherwise Undefined Undefined IMI IMO 9 8 Interrupt Mask Controls the enabling of each of the software interrupts Refer to Section lt lt NEED CROSSREF for a complete discussion of enabled interrupts Meaning Interrupt request disabled Interrupt request enabled In implementations of Release 2 of the Architecture in which EIC interrupt mode is enabled Config3ypyc 1 these bits are writable but have no effect on the interrupt system Undefined MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 107 Chapter 5 CPO Registers Table 5 17 Status Register Field Descriptions Fi
46. 0 to 1 transition If such a transition is caused by software it is UNPREDICTABLE whether hardware ignores the write accepts the write with no side effects or accepts the write and initiates a watch exception once Statusgxr and Statusgery are both zero MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Undefined Copyright 2000 2002 MIPS Technologies Inc All rights reserved 117 Chapter 5 CPO Registers Table 5 22 Cause Register Field Descriptions Fields Read Name Bits Description Write Reset State Indicates an interrupt is pending IP7 Hardware interrupt 5 E 12 IP4 Hardware interrupt 2 l IP7 1P2 15 10 10 R Undefined If EIC interrupt mode is not enabled Config3ypyc 0 timer interrupts are combined in a system dependent way with any hardware interrupt If EIC interrupt mode is enabled Config3ypyc 1 these bits take on a different meaning and are interpreted as the RIPL field described below See Section 4 3 Interrupts on page 55 for a general description of interrupt processing Requested Interrupt Priority Level If EIC interrupt mode is enabled Config3ypyc 1 this field is the encoded 0 63 value of the requested interrupt A value of zero indicates that no interrupt RIPL 15 10 is requested R Undefined If EIC interrupt mode is not enabled Config3ygrc 0 these bits take on a different meaning and are inte
47. 0000 0000 000110 6 1 19 6 Format TLBWR MIPS32 Purpose To write a TLB entry indexed by the Random register Description The TLB entry pointed to by the Random register is written from the contents of the EntryHi EntryLoO EntryLol and PageMask registers The information written to the TLB entry may be different from that in the EntryHi EntryLo0 and EntryLol registers in that e The single G bit in the TLB entry is set from the logical AND of the G bits in the EntryLoO and EntryLol registers Restrictions If access to Coprocessor 0 is not enabled a Coprocessor Unusable Exception is signaled MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 269 Write Random TLB Entry 270 Operation i lt Random Mask 7 PageMaskyas vpn2 EntryHiypw as p EntryHiasip c EntryLolg and EntryLoOg Pru amp EntryLolppy TLB TLB TLB TLB TLB TLB TLB TLB TLB TLB TLB TLB Exceptions H H H H H H bb H H H H cj Entry TLBWR Olc pj amp Entry yj amp Entry Olp oly prno lt EntryLoOpry co Entry po amp Entry 006 OD vo Entry Coprocessor Unusable OD MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Enter S
48. 16bx32b 1 E stage 4KEc and 4KEm cores Non Consumer of target data 32bx32b 2 E stage MFHI MFLO Consumer of target data 1 E stage MULTx MADDx MSUBx 16bx32b oL E stage 4KEc and 4KEm cores MULT MUL MADD MSUB 32bx32b ETHENGEEOIDIV ru E stage MUL MULTx MADDx Until DIV DIV MSUBx MTHI MTLO compl t s E stage MFHI MFLO DIV P MULT MUL MADD MSUB MTHI MTLO MEHPMELO DIV MULT MUL MADD MSUB MTHIMTLO MFHIMFL Until Ist MDU op E 4KEp core completes stage EDD O DIV P MUL Until MUL 4KEp core Any Instruction completes E stage MFCO MFC2 CFC2 Consumer of target data 1 E stage EER Ry Load Store PREF CACHE S E stage TLBR COPO op 1 E stage 2 13 Hazards 28 In general the 4KE core ensures that instructions are executed following a fully sequential program model Each instruction in the program sees the results of the previous instruction There are some deviations to this model These deviations are referred to as hazards Prior to Release 2 of the MIPS32 Architecture hazards primarily CPO hazards were relegated to implementation dependent cycle based solutions primarily based on the SSNOP instruction This has been an insufficient and error prone practice that must be addressed with a firm compact between hardware and software As such new instructions have been added to Release 2 of the architecture which act as explicit barriers that eliminate hazards To the extent that it was possible to do so the new instructions have
49. 17 16 15 14 13 12 11 10 8 7 6 3 2 1 0 WE 0 REG WR 0 RM TR IBF TM 0 CR Cal 0 CA OfC EN Table 9 30 TCBCONTROLB Register Field Descriptions Fields Read Name Bits Description Write Reset State Write Enable Only when set to 1 will the other bits be written in NE 3l TCBCONTROLB R 9 This bit will always read 0 212 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 9 Trace Control Block TCB Registers hardware control Table 9 30 TCBCONTROLB Register Field Descriptions Continued Fields Read Name Bits Description Write Reset State 0 30 26 Reserved Must be written as zero returns zero on read R 0 Register select This field select the registers accessible REG 25 21 through the TCBDATA register Legal values are shown in R W 0 Table 9 28 Write Registers When set the register selected by REG field WR 20 is read and written when TCBDATA is accessed Otherwise the R W 0 selected register is only read 0 19 17 Reserved Must be written as zero returns zero on read R 0 Read on chip trace memory When written to 1 the read address pointer of the on chip memory is set to point to the oldest memory location written since the last reset of pointers Subsequent access to the TCBTW register through the TCBDATA register will automatically increment the read pointer TCBRDP regis
50. 29 28 13 12 11 10 0 0 Mask MaskX 0 Table 5 8 PageMask Register Field Descriptions Read Description Write Reset State The Mask field is a bit mask in which a 1 bit indicates Mask 28 13 that the corresponding bit of the virtual address should R W Undefined not participate in the TLB match In Release 2 of the Architecture the MaskX field is an extension to the Mask field to support 1KB pages with definition and action analogous to that of the Mask field defined above If IKB pages are enabled Config3sp 1 and PageGraingsp 1 these bits are writable and readable and their values are copied to and from the TLB entry 0 MaskX 12 11 on a TLB write or read respectivly See If 1KB pages are not enabled Config3sp 0 or Description PageGraingsp 0 these bits are not writable return zero on read and the effect on the TLB entry on a write is as if they were written with the value 2 11 In Release 1 of the Architecture these bits must be Written as zero return zero on read and have no effect on the virtual address translation ov E 0 E Ignored on write returns zero on read EMEN Table 5 9 Values for the Mask and MaskX Fields of the PageMask Register Page Size mur vPIPIIESIESIESISISISISI ISI IIIS NC SESENESESEXESEREJEZEHETESESESESEHENES ee DEER EE E EE EE EE EN 64 KBytes 0 0 1 1 256 KBytes 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 96 MIPS32 4KE Processor Cores
51. 5 33 User Trace Data Register Format 141 Figure 5 34 Trace BPC Register Format 142 Figure 5 35 DEPC Register Format pem p Rte ee ir espere i RU ede f iO ederent eoe d 143 Figure 5 36 ErrCtl Register Format esee eerte nne en nen nn entren eteee teste e tette ne terere enne S enne 144 Figure 5237 Tago Register Format rne n pte e Rm n eter ne Poe en 145 Figure 5 38 DataLo Register Format enne ener EE IEE EN ET SEE aaoo AAE TNES e 146 Figure 5 39 ErrorEPC Register Format oen et cr RE e bec EE A 147 Figure 5 40 DeSave Register Format enne ener en nen teen tente ES E EEE eSEE EEE IEE RENE eren ennt 148 Figure 7 1 Cache Array Formats eerte pans epa re eti deed deg re ee dee 155 Figure 9 1 TAP Controller State Diagram isese renee kieo enne nennen nennen nennen nennen nr oee oa trente treni trennen 189 Figure 9 2 Concatenation of the EJTAG Address Data and Control Registers sese 193 Figure 9 3 TDI to TDO Path when in Shift DR State and FASTDATA Instruction is Selected 193 Figure 9 4 Endian Formats for the PAD Register sese enne tee trnt teret trennen retenti 201 Figure 9 5 EJTAG Trace modules in the 4KE vote 205 Figure 9 6 TCB Trigger processing overview neonne oisean i oee EE enne nee nen nen nennen ESEE tee enne t nein ne trenes nennen 226 Figure 10 1 Instruction bormats teen ener een net retener e ettet tren nente ete nenne tene
52. 8 2 Soft Reset Exception step ehe aem iem eee Ras Go Baa Rs eas 70 4 8 3 Debus Single Step ExCeption i eoe eee fen p e pie i ree edens 71 4 8 4 Debug Interrupt Exception EEN 72 4 8 5 Non Maskable Interrupt NMI Exception 72 4 8 6 Machine Check Exception 4KECc core o eeeesceececsseceseeceeeecsseeecceeseeeeneceseecsaeceaceceeeesaeseneeseeeeaeceeeecaeeeaeecee 73 4 8 7 Interrupt Exception rr rtr m Rr Pre e eH P e nee HER rernm 73 4 8 8 Debug Instruction Break Exception sesseseeseeeseeseeeee eene nennen teen en nee nene tee tenter treten ennt rennen 73 4 8 9 Watch Exception Instruction Fetch or Data Access eene ene 74 4 8 10 Address Error Exception Instruction Fetch Data Access eene 74 4 8 11 TLB Refill Exception Instruction Fetch or Data Access 4KEc core only sees 75 4 8 12 TLB Invalid Exception Instruction Fetch or Data Access 4KEc core only sees 76 4 8 13 Bus Error Exception Instruction Fetch or Data Access sess 76 4 8 14 Debug Software Breakpoint Exception TI 4 8 15 Execution Exception System Call esee senten enne enne three tenter tenen entente TI 4 8 16 Execution Exception Breakpoint neret nennen nennen tentent nennen eene ennt nenne TI 4 8 17 Execution Exception Reserved Instruction esee eere TI 4 8 18 Execution Exception Coprocessor Unusable seen
53. 9 6 show the functional overview of the trigger flow in the TCB Trigger sources Trigger Source Unit Trigger strobes Trigger control Unit 1 to 7 are optional when trigger logic is implemented Trigger Control Unit 7 Trigger Control Unit 1 Trigger Control Unit 0 Priority i OR function Depending on the trigger action the Action strobes must pass through a priority function or an OR gate Priority OR function Trigger Action Unit Figure 9 6 TCB Trigger processing overview 9 11 2 Trigger Source Unit The TCB has three trigger sources 1 Chip level trigger input TC ChipTrigIn 2 Probe trigger input TR TRIGIN 3 Debug Mode DM entry indication from the processor core The input triggers are all rising edge triggers and the Trigger Source Units convert the edge into a single cycle strobe to the Trigger Control Units 226 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 11 TCB Trigger logic 9 11 3 Trigger Control Units Up to eight Trigger Control Units are possible Each of them has it s own Trigger Control Register TCBTRIGx x 0 7 Each of these registers controls the trigger fire mechanism for the unit Each unit has all of the Trigger Sources as possible trigger event and they can fire one or more of the Trigger Actions This is all defined in the Trigger Contr
54. About triggers then the trace mode in TCBCONTROLB yyy should be set to Trace To mode 9 13 1 On Chip Trace Memory size The supported On chip trace memory size can range from 256 byte to 8Mbytes in powers of 2 The actual size is shown in the TCBCONFIGs field 9 13 2 Trace From Mode In the Trace From mode tracing begins when the processor enters into a processor mode ASID value which is defined to be traced or when an EJTAG hardware breakpoint trace trigger turns on tracing Trace collection is stopped when the buffer is full The TCB then signals buffer full using ZCBCONTROLBgp When external software polling this register finds the TCBCONTROLBy bit set it can then read out the internal trace memory Saving the trace into the internal buffer will re commence again only when the TCBCONTROLBpg bit is reset and if the core is sending valid trace data i e PDO lamTracing not equal 0 9 13 3 Trace To Mode In the Trace To mode the TCB keeps writing into the internal trace memory wrapping over and overwriting the oldest information until the processor is reaches an end of trace condition End of trace is reached by leaving the processor mode ASID value which is traced or when an EJTAG hardware breakpoint trace trigger turns tracing off At this point the on chip trace buffer is then dumped out in a manner similar to that described above in Section 9 13 2 Trace From Mode 230 MIPS32 4KE Processor Cores Software User s Manual Rev
55. An address error exception occurs on an instruction or data access when an attempt is made to execute one of the following Fetch an instruction load a word or store a word that is not aligned on a word boundary Load or store a halfword that is not aligned on a halfword boundary Reference the kernel address space from user mode Note that in the case of an instruction fetch that is not aligned on a word boundary PC is updated before the condition is detected Therefore both EPC and BadVAddr point to the unaligned instruction address In the case of a data access the exception is taken if either an unaligned address or an address that was inaccessible in the current processor mode was referenced by a load or store instruction MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 4 8 Exceptions Cause Register ExcCode Value ADEL Reference was a load or an instruction fetch ADES Reference was a store Additional State Saved Table 4 12 CPO Register States on an Address Exception Error Register State Value BadVAddr failing address Contextypyy UNPREDICTABLE EntryHiypy UNPREDICTABLE EntryLoO UNPREDICTABLE EntryLol UNPREDICTABLE Entry Vector Used General exception vector offset 0x180 4 8 11 TLB Refill Exception Instruction Fetch or Data Access 4KEc core only During an instruction fetch or d
56. Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 9 Trace Control Block TCB Registers hardware control Table 9 29 TCBCONTROLA Register Field Descriptions Continued Read Description Write Reset State Inhibit Overflow This bit is used to indicate to the core trace logic that slow but complete tracing is desired Hence the core tracing logic must not allow a FIFO overflow and discard trace data This is achieved by stalling the pipeline when the R W FIFO is nearly full so that no trace records are ever lost EES This field defines the value on the PDI InhibitOverflow signal When set to one this enables tracing in Debug mode i e when the DM bit is one in the Debug register For trace to be enabled in Debug mode the On bit must be one and either the G bit must be one or the current process must match the ASID field in this register R W Undefined When set to zero trace is disabled in Debug mode irrespective of other bits This field defines the value on the PDI DM signal This controls when tracing is enabled When set tracing is enabled when either of the EXL or ERL bits in the Status register is one provided that the On bit bit 0 is also set and either the G bit is set or the current process ASID matches the R W Undefined ASID field in this register This field defines the value on the PDI E signal Reserved Must be written as zero returns zero on read R W
57. DEPC register is set to the instruction where execution should continue after the debug handler is through The DBD bit is set based on whether the interrupted instruction was executing in the delay slot of a branch Debug Register Debug Status Bit Set DINT Additional State Saved None Entry Vector Used Debug exception vector 4 8 5 Non Maskable Interrupt NMI Exception A non maskable interrupt exception occurs when the SI NMI signal is asserted to the processor S NMI is an edge sensitive signal only one NMI exception will be taken each time it is asserted An NMI exception occurs only at instruction boundaries so it does not cause any reset or other hardware initialization The state of the cache memory and other processor states are consistent and all registers are preserved with the following exceptions The BEV TS SR NMI and ERL fields of the Status register are initialized to a specified state The ErrorEPC register is loaded with PC 4 if the state of the processor indicates that it was executing an instruction in the delay slot of a branch Otherwise the ErrorEPC register is loaded with PC PC is loaded with OXBFCO 0000 Cause Register ExcCode Value None Additional State Saved None Entry Vector Used Reset OXBFCO 0000 Operation Statuspggy amp 1 Statusrs amp 0 StatuSsp 0 Statusymr amp 1 StatuSpp amp 1 if InstructionInBranchDelaySlot then ErrorEPC amp PC 4 e
58. EE EEREN a eits 232 Figure 11 1 Usage of Address Fields to Select Index and Way 248 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All right reserved List of Tables Table 2 1 4KEc and 4KEm Core MDU Instruction Latencies rennen ennt ene 16 Table 2 2 4KEc Core MDU Instruction Repeat Rates esses ener nennen nenne tnnt teretes 17 Table 2 3 4KEp Core Instruction caten Cres ot ettet P e RR E EH Pte pee tte eee 20 Table 2 4 Pipeline Interlocks eene te ege eee eere eec etie epe t dpi eed e et bec e ree des 26 Table 2 5 Tnstruction Interlocks 3 oo Pene tra e ete eR per ope d beg egre deines 27 Table 2 6 Execution Hazards soi eite eet eoi dete e Hit ee HR He a ede terere ree RE e ee Eres 29 Table2 7 Instruction EE 30 Table 2 8 Hazard Instruction Listing eene enne ene enne trennen nr etr entre tret tente etn nete nenne tne entren enne 30 Table 3 J User Mode Segiments EE 38 Table 3 2 Kernel Mode Segments gie erede red tede eee Eed 39 Table 3 3 Physical Address and Cache Attributes for dseg dmseg and drseg Address Spaces eeeseeeesseeeerseeeseeeeens 41 Table 3 4 CPU Access to drseg Address Range ooo cee ceceseescessessceseeseceseeeeecaeecsecaeesaecaaesaecaecsaeceecsseeeseeeseaseaeseaecaasenesaes 41 Table 3 5 CPU Access to dmseg Address Range sese rennen trennen nennen retener nennen teretes 42 Table 3 6 TLB Tag Entry Fields sss oo I
59. Field Descriptions Fields Description Reset State DBV 31 0 Data breakpoint value for condition R W Undefined 186 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 3 Test Access Port TAP 9 3 Test Access Port TAP The following main features are supported by the TAP module 5 pin industry standard JTAG Test Access Port TCK TMS TDI TDO TRST N interface which is compatible with IEEE Std 1149 1 Target chip and EJTAG feature identification available through the Test Access Port TAP controller The processor can access external memory on the EJTAG Probe serially through the EJTAG pins This is achieved through Processor Access PA and is used to eliminate the use of the system memory for debug routines Support for both ROM based debugger and debugging both through TAP 9 3 1 EJTAG Internal and External Interfaces The external interface of the EJTAG module consists of the 5 signals defined by the IEEE standard Table 9 19 EJTAG Interface Pins Pin Type Description Test Clock Input Input clock used to shift data into or out of the Instruction or data TCK registers The TCK clock is independent of the processor clock so the EJTAG probe can drive TCK independently of the processor clock frequency The core signal for this is called EJ TCK Test Mode Select Input TMS The TMS input
60. Fields Read Description Write Reset State The trace select bit is used to select between the a hardware and the software trace control bits A value of Undefined 0 zero selects the external hardware trace block signals R W and a value of one selects the trace control bits in this software control register This bit is used to indicate the type of user triggered trace record A value of zero implies a user type 1 and a value of one implies a user type 2 R W The actual triggering of a user trace record happens on a write to the UserTraceData register 0 Trace All Branch When set to one this tells the processor to trace the PC value for all taken branches R W not just the ones whose branch target address is Undefined statically unpredictable Inhibit Overflow This signal is used to indicate to the core trace logic that slow but complete tracing is IO 26 desired When set to one the core tracing logic does not R W allow a FIFO overflow or discard trace data This is achieved by stalling the pipeline when the FIFO is nearly full so that no trace records are ever lost Reserved for future use Must be written as zero returns zero on read Undefined When set to one this enables tracing in Debug Mode see Section 9 7 1 Processor Modes on page 205 For trace to be enabled in Debug mode the On bit must be one and either the G bit must be one or the current D 25 process ASID must match the ASID field in thi
61. IG Register Field Descriptions Continued Fields Read Name Bits Description Write Reset State Probe Width Number of bits available on the off chip trace interface TR DATA pins The number of TR DATA pins is encoded as shown in the table PW Number of bits used on TR DATA 00 4 bits 01 8 bits PW 10 9 R Preset 10 16 bits 11 reserved This field is preset based on input signals to the TCB and the actual capability of the TCB This bit is reserved if off chip trace option is not implemented Pipe number PiN 8 6 R 0 Indicates the number of execution pipelines When set this bit indicates that on chip trace memory is OnT 5 present This bit is preset based on the selected option when R Preset the TCB is implemented When set this bit indicates that off chip trace interface is present This bit is preset based on the selected option when SS 4 the TCB is implemented and on the existence of a PIB module i Preset TC PibPresent asserted REV 3 0 Revision of TCB An implementation that conforms to the R 0 described architecture in this document must have revision 0 9 9 5 TCBTW Register Reg 4 The TCBTW register is used to read Trace Words from the on chip trace memory The TW read is the one pointed to by the TCBRDP register A side effect of reading the TCBTW register is that the TCBRDP register increments to the next TW in the on chip trace memory If TCBRDP is at the max size
62. IP7 IPO HW5 HWO SW1 SWO Location Offset 0x200 from exception base IVexception mfcO k0 CO Cause Read Cause register for IP bits mfcO k1 CO Status and Status register for IM bits 56 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 4 3 Interrupts 0X 0X 0X F X F X X F F F F X X F F kO kO kO kO kO kO Kl kO kO kO andi and beq elz xori sll la kO kO kO kO zero VectorBase Keep only IP bits from Cause and mask with IM bits no bits set spurious interrupt Find first bit set IP7 1IP0 kO 16 23 gt 7 0 Shift to emulate software IntCtlyg Get base of 8 interrupt vectors Compute target from base and offset M CauseIM k1 Dismiss L6 29 Hy 0x17 VS n k1 addu jr nop kO Jump to specific exception routine Each interrupt processing routine processes a specific interrupt analogous to those reached in VI or EIC interrupt mode Since each processing routine is dedicated to a particular interrupt line it has the context to know which line was asserted Each processing routine may need to look further to determine the actual source of the interrupt if multiple interrupt requests are ORed together on a single IP line Once that task is performed the interrupt may be processed in one of two
63. Inc All rights reserved Chapter 9 EJTAG Debug Support 9 2 8 3 Instruction Breakpoint Address Mask n IBMn Register Compliance Level Implemented only for implemented instruction breakpoints The Instruction Breakpoint Address Mask n UBMn register has the mask for the address compare used in the condition for instruction breakpoint n IBMn Register Format 31 0 IBM Table 9 9 IBMn Register Field Descriptions Fields Read Name Bit s Description Write Reset State Instruction breakpoint address mask for condition IBM 31 0 0 Corresponding address bit not masked Undefined 1 Corresponding address bit masked 176 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 2 Hardware Breakpoints 9 2 8 4 Instruction Breakpoint ASID n BASIDn Register Compliance Level Implemented only for implemented instruction breakpoints The Instruction Breakpoint ASID n JBASIDn register has the ASID value used in the compare for instruction breakpoint n The number of bits in the ASID field is 8 to match the ASID size in the TLB This register is only valid for the 4KEc core IBASIDn Register Format 31 8 7 0 Res ASID Table 9 10 IBASIDn Register Field Descriptions Fields Read Name Bit s Description Write Reset State Res 31 8 Must be written as zero returns zero on read R 0 ASID 7 0 Instructio
64. PC int offset else Ignore Next Instruction if Rs 31 PC int offset else Ignore Next Instruction if Rs 31 amp amp Rs 0 PC int offset BGTZL BLEZ BLEZL Branch on Greater Than Zero Likely Branch on Less Than or Equal to Zero Branch on Less Than or Equal to Zero Likely if Rs 31 amp amp Rs 0 PC int offset else Ignore Next Instruction if Rs 31 ll Rs 0 PC int offset if Rs 31 ll Rs PC int offset else Ignore Next Instruction BLTZ BLTZAL Branch on Less Than Zero Branch on Less Than Zero And Link if Rs 31 PC int offset GPR 31 PC 8 if Rs 31 PC int offset BLTZALL Branch on Less Than Zero And Link Likely GPR 31 PC 8 if Rs 31 PC int offset else Ignore Next Instruction BLTZL BNE BNEL Branch on Less Than Zero Likely Branch on Not Equal Branch on Not Equal Likely if Rs 31 PC int offset else Ignore Next Instruction if Rs Rt PC int offset if Rs Rt PC int offset else Ignore Next Instruction BREAK Breakpoint Break Exception MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 241 Chapter 11 MIPS32 4KE Processor Core Instructions Table 11 10 Instruction Set Continued Instruction Description Functio
65. ProbEn and ProbTrap to 0 as reset value OxOE FASTDATA Selects the Data and Fastdata registers 0x10 TCBCONTROLA Selects the TCBTCONTROLA register in the Trace Control Block 0x11 TCBCONTROLB Selects the TCBTCONTROLB register in the Trace Control Block 0x12 TCBDATA Selects the TCBDATA register in the Trace Control Block Ox1F BYPASS Bypass mode 9 3 3 1 BYPASS Instruction The required BYPASS instruction allows the processor to remain in a functional mode and selects the Bypass register to be connected between TDI and TDO The BYPASS instruction allows serial data to be transferred through the processor from TDI to TDO without affecting its operation The bit code of this instruction is defined to be all ones by the IEEE 1149 1 standard Any unused instruction is defaulted to the BYPASS instruction 9 3 3 2 IDCODE Instruction The IDCODE instruction allows the processor to remain in its functional mode and selects the Device Identification ID register to be connected between TDI and TDO The Device ID register is a 32 bit shift register containing information regarding the IC manufacturer device type and version code Accessing the Identification Register does not interfere with the operation of the processor Also access to the Identification Register is immediately available via a TAP data scan operation after power up when the TAP has been reset with on chip power on or through the optional TRST_N pin 9 3 3 3 IMP
66. RIPL for the interrupt to be serviced The interrupt controller passes this value on the 6 hardware interrupt line which are treated as an encoded value in EIC interrupt mode Statut which overlays Status y7 jw is interpreted as the Interrupt Priority Level IPL at which the processor is currently operating with a value of zero indicating that no interrupt is currently being serviced When the interrupt controller requests service for an interrupt the processor compares RIPL with Statusjp to determine if the requested interrupt has higher priority than the current IPL If RIPL is strictly greater than Statusjp and interrupts are enabled Status 1 Statusgy 0 and Statuspp 0 an interrupt request is signaled to the pipeline When the processor starts the interrupt exception it loads RIPL into Cause which overlays Causejp jp and signals the external interrupt controller to notify it that the request is being serviced The interrupt exception uses the value of Cause as the vector number Because Causepypy is only loaded by the processor when an interrupt exception is signaled it is available to software during interrupt processing In EIC interrupt mode the external interrupt controller is also responsible for supplying the GPR shadow set number to use when servicing the interrupt As such the SRSMap register is not used in this mode and the mapping of the vectored interrupt to a GPR shadow set is done by programming or desi
67. Register Format 31 24 23 16 15 8 7 5 4 2 1 0 R Company ID Processor ID Revision Table 5 25 PRId Register Field Descriptions Fields Read Name Bit s Description Write Reset State R 31 24 Reserved Must be ignored on write and read as zero R 0 Conan Identifies the company that designed or manufactured the 1D y 23 16 processor In the 4KE this field contains a value of 1 to R 1 indicate MIPS Technologies Inc 4KEc Proesssof Identifies the type of processor This field allows software core 0x90 15 8 to distinguish between the various types of MIPS R ID Technolosi 4KEm amp echnologies processors 4KEp cores 0x91 Specifies the revision number of the processor This field allows software to distinguish between one revision and Revision 7 0 another of the same processor type R Preset This field is broken up into the following three subfields Major 7 5 This number is increased on major revisions of the R Preset Revision processor core Minor This number is increased on each incremental revision of oar 4 2 GE R Preset Revision the processor and reset on each new major revision Patch Level 1 0 If a patch is made to modify an older revision of the R Preset processor this field will be incremented MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 121 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers 5 2 20 EBase Register CPO Reg
68. Register Porm at 5 ette ea ned ete e pause tree pee rte eer copes pene 115 Figure 5 18 Cause Register Format esses ener enne eera trennen tr etene terere terere tne entente ennt 116 Figure 5 19 EPC Register Format 5e epe p tec dvo in eee eie ote eb dee ies itecto eee onn 120 Figure 5 20 PRId Register Form t esses ener enr e e entren nen teete entr stent Se terere enne treten enne 121 Figure 5 21 EBase Register EOorm t 4 eie epe e Pei mee tr nre ntis 122 Figure 5 22 Config Register Format Select OU 123 Figure 5 23 Config Register Field Descriptions sees nenne enne treten ennt 123 Figure 5 24 Config1 Register Format Select 1 sse nennen nne trennen rennen eene 125 Figure 5 25 Config2 Register Format Select 2 nennen nennen nennen nennen terere trennen reet 127 Figure 5 26 Config3 Register Format 128 Figure 5 27 EFAddr Register Format ederent ee dech AE EE Eed Seed 130 Figure 5 28 WatchLo Register bomat trennen ennt nennen nen treteee trennt tee tene terere terii treten enne 131 Figure 5 29 Watch Hi Register Format e ene rn rete te npe o eei 132 Figure 5 30 Debug Register Format esses eene EVE EE IE PEN EN SEE SeSe e tereti tne SEE V E enne 133 Figur 5 31 Trace Control Register Formiat 4 e E ette He e E EA N E eee ere io cie EER 136 Figure 5 32 Trace Control Register Format sessi nennen nennen neenenetee enne terere t rennen rene enr ennt 139 Figure
69. Sign Adjust MDU Res Rdy Early In Figure 2 12 MDU Pipeline Flow During a 32 bit Divide DIV Operation 2 6 MDU Pipeline 4KEp Core 20 The multiply divide unit MDU is a separate autonomous block for multiply and divide operations The MDU is not pipelined but rather performs the computations iteratively in parallel with the integer unit IU pipeline It does not stall when the IU pipeline stalls This allows the long running MDU operations to be partially masked by system stalls and or other integer unit instructions The MDU consists of one 32 bit adder result accumulate registers HI and LO a combined multiply divide state machine and all multiplexers and control logic A simple 1 bit per clock recursive algorithm is used for both multiply and divide operations Using booth s algorithm all multiply operations complete in 32 clocks Two extra clocks are needed for multiply accumulate The non restoring algorithm used for divide operations will not work with negative numbers Adjustment before and after are thus required depending on the sign of the operands All divide operations complete in 33 to 35 clocks Table 2 3 lists the latencies number of cycles until a result is available for multiply and divide instructions The latencies are listed in terms of pipeline clocks In this table latency refers to the number of cycles necessary for the second instruction to use the results of the first Table 2 3 4KEp Core I
70. State This is a temporary controller state in which all test data registers selected by the current instruction retain their previous state If TMS is sampled LOW at the rising edge of TCK the controller transitions to the Pause DR state A HIGH on TMS causes the controller to transition to the Update DR state which terminates the scanning process The instruction cannot change while the TAP controller is in this state 9 3 2 8 Pause DR State The Pause DR state allows the controller to temporarily halt the shifting of data through the test data register in the serial path between TDI and TDO All test data registers selected by the current instruction retain their previous state If TMS is sampled LOW on the rising edge of TCK the controller remains in the Pause DR state A HIGH on TMS causes the controller to transition to the Exit2 DR state The instruction cannot change while the TAP controller is in this state 9 3 2 9 Exit2 DR State This is a temporary controller state in which all test data registers selected by the current instruction retain their previous state If TMS is sampled LOW at the rising edge of TCK the controller transitions to the Shift DR state to allow another serial shift of data A HIGH on TMS causes the controller to transition to the Update DR state which terminates the scanning process The instruction cannot change while the TAP controller is in this state 9 3 2 10 Update DR State When the TAP controller is in thi
71. The 4KE core includes optional support for the MIPS16e ASE This ASE improves code density through the use of 16 bit encodings of MIPS32 instructions plus some MIPS16e specific instructions PC relative loads allow quick access to constants Save Restore macro instructions provide for single instruction stack frame setup teardown for efficient subroutine entry exit Sign and zero extend instructions improve handling of 8bit and 16bit datatypes A decompressor converts the MIPS16e 16 bit instructions fetched from the instruction cache or external interface back into 32 bit instructions for execution by the core 1 2 2 2 Instruction Cache The instruction cache is an optional on chip memory array of up to 64 Kbytes The cache is virtually indexed and physically tagged allowing the virtual to physical address translation to occur in parallel with the cache access rather than having to wait for the physical address translation The tag holds 22 bits of the physical address a valid bit and a lock bit There is a separate tag array which holds data used in the Least Recently Used LRU replacement scheme The LRU array ranges from 0 6 bits depending on associativity 8 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 1 2 4KE Block Diagram All cores support instruction cache locking Cache locking allows critical code to be locked into the cache on a per l
72. The caches are blocking until the critical word is returned but the pipeline may proceed while the other 3 beats of the burst are still active on the bus Table 7 1 lists the instruction and data cache attributes Table 7 1 Instruction and Data Cache Attributes Parameter Instruction Data Number of Cache Sets 0 64 128 256 512 and 1024 0 64 128 256 512 and 1024 Lines Per Set Associativity 1 4 way set associative 1 4 way set associative Line Size 16 Bytes 16 Bytes Read Unit 32 bits 32 bits Minimum Write Unit 32 bits MIPS32 AKETM Processor Cores Software User s Manual Revision 02 00 153 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 7 Caches Table 7 1 Instruction and Data Cache Attributes Continued Parameter Instruction Data Software selectable options write back with write allocate Write Policy write through with write allocate write through without write allocate Miss restart after transfer of miss word miss word Cache Locking per line per line Table 7 2 shows the cache size and organization options note that the same total cache size may be achieved with several different set associativities Software can identify the instruction or data cache configuration on a 4KE core by reading the appropriate bits of the Config register see Section 5 2 22 Configl Register CPO Register 16 Select 1 on page
73. The processor is running in Kernel Mode nterrupts are disabled TLB Refill exceptions use the general exception vector instead of the TLB Refill vector EPC Causepgy and SRSCtl implementations of Release 2 of the Architecture only will not be updated if another exception is taken 108 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Fields Name Bits Table 5 17 Status Register Field Descriptions Description Read Write Reset State IE Interrupt Enable Acts as the master enable for software and hardware interrupts Encoding Meaning 0 Interrupts are disabled 1 Interrupts are enabled In Release 2 of the Architecture this bit may be modified separately via the DI and EI instructions Undefined MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 109 Chapter 5 CPO Registers 5 2 14 IntCtl Register CPO Register 12 Select 1 The ntCtl register controls the expanded interrupt capability added in Release 2 of the Architecture including vectored interrupts and support for an external interrupt controller This register does not exist in implementations of Release 1 of the Architecture Figure 5 15 shows the format of
74. With the exclusions noted in the next paragraph this field is updated with a new value on any interrupt or exception and restored from the PSS field on an ERET Table 5 20 describes the various sources from which the CSS field is updated on an exception or interrupt This field is not updated on any exception which sets CSS 3 0 Statusppy to 1 i e Reset Soft Reset NMI cache R 0 error an entry into EJTAG Debug mode or any exception or interrupt that occurs with Statusgx 1 or Statuspgy 1 Neither is it updated on an ERET with Statusgpy 1 or Statusggy 1 This field is not updated on an exception that occurs while Statusgpy The value of CSS can be changed directly by software only by writing the PSS field and executing an ERET instruction Table 5 20 Sources for new SRSCtlcgg on an Exception or Interrupt Exception Type Condition SRSCtlcgg Source Comment Non Vectored E i MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 113 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers Table 5 20 Sources for new SRSCtl ss on an Exception or Interrupt Exception Type Condition SRSCtlcss Source Comment Causeyy 1 and Source is internal map register Vectored Interrupt Config3 ypc 0 and SRSMapyecrnum Config3yjnt 1 for VECTNUM see Table 4 3 Vectored EIC Causeyy 1 and Source is external interrupt Interrupt Config3yg c 1 SRSC
75. a cacheability attribute field associated with that region of memory See Chapter 3 Memory Management on page 33 for further details 7 2 3 Replacement Policy 156 The replacement policy refers to how a way is chosen to hold an incoming cache line on a miss which will result in a cache fill when a cache is at least two way set associative In a direct mapped cache one way set associative the replacement policy is irrelevant since there is only one way available The replacement policy is least recently used LRU but excluding any locked ways The LRU bit s in the way select array encode the order in which ways on that line have been accessed On a cache miss the lock and LRU bits for the tag and way select entries of the selected line may be used to determine the way which will be chosen The number of lock bits and the number of LRU bits depend on the set associativity of the cache The LRU field in the way select array is updated as follows MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 7 2 Cache Protocols e On a cache hit the associated way is updated to be the most recently used The order of the other ways relative to each another is unchanged Ona cache refill the filled way is updated to be the most recently used On CACHE instructions the update of the LRU bits depends on the type of operation to be performed
76. always read as 0 21 20 1 0 0 EN Data access Bus Error exception Pending Covers B imprecise bus errors on data access similar to behavior ES EN MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Table 5 34 Debug Register Field Descriptions Continued Description Reset State EJTAG version 010 Indicates the cause of the latest exception in debug mode The field is encoded as the ExcCode field in the DExcCode Cause register for those normal exceptions that may Undefined occur in debug mode Value is undefined after a debug exception Indicates whether the single step feature controllable by the SSt bit is available in this implementation 0 Single step feature available 1 No single step feature available Controls if debug single step exception is enabled SSt 8 0 No debug single step exception enabled R W 0 1 Debug single step exception enabled R 7 6 Reserved Must be written as zeros returns zeros on R 0 reads Indicates that a debug interrupt exception occurred Cleared on exception in debug mode DINT 5 R W Undefined 0 No debug interrupt exception 1 Debug interrupt exception Indicates that a debug instruction break exception occurred Cleared on exception in debug mode DIB 4 R Undefined 0 No debug instruction exception 1 Debug instruction excepti
77. and Link instructions both of which are J type instructions In J type format the 26 bit target address shifts left 2 bits and combines with the high order 4 bits of the current program counter to form an absolute address Returns dispatches and large cross page jumps are usually implemented with the Jump Register or Jump and Link Register instructions Both are R type instructions that take the 32 bit byte address contained in one of the general purpose registers For more information about jump instructions refer to the individual instructions in Section 11 3 MIPS32 Instruction Set for the 4KE core on page 240 10 4 2 Overview of Branch Instructions All branch instruction target addresses are computed by adding the address of the instruction in the delay slot to the 16 bit offset shifted left 2 bits and sign extended to 32 bits All branches occur with a delay of one instruction If a conditional branch likely is not taken the instruction in the delay slot is nullified Branches jumps ERET and DERET instructions should not be placed in the delay slot of a branch or jump 10 5 Control Instructions Control instructions allow the software to initiate traps they are always R type 10 6 Coprocessor Instructions 234 CPO instructions perform operations on the System Control Coprocessor registers to manipulate the memory management and exception handling facilities of the processor Refer to Chapter 11 MIPS32 4KE Pro
78. are not consistent with the overlapping physical bits after the virtual address has been translated to a physical address The possibility of virtual aliasing only occurs in address regions which are mapped through a TLB based memory management unit so it is only relevant for the 4KEc core and cannot occur in the 4KEm or 4KEp cores which contain a fixed memory management unit In TLB mapped address regions virtual aliasing may occur if the cache size per way is greater than the page size For example consider a 16 KB cache organized as 2 way set associative The size per way is then 8 KB so virtual address bits 12 0 are used to index the array If the address is in a translated region with a page size of 4 KB then address bits 11 0 are untranslated but address bits 31 12 will be mapped and for these bits the virtual and physical addresses may be different In this example bit 12 could pose a potential problem due to virtual aliasing Imagine two virtual addresses VAO and VA1 whose only difference is the value of bit 12 which map to the same physical address These two virtual addresses would be indexed to two different lines by the cache even though they were intended to represent the same physical address Then if a program does a load using VAO and a store using VAT or vice versa the cache may not return the expected data Table 7 4 shows the overlapped virtual physical address bits which could potentially be involved in virtual alia
79. are skipped if they are not needed The rule is if both operands were positive or if this is an unsigned division both of the sign adjust cycles are skipped If the rs operand was negative one of the sign adjust cycles is skipped If only the rs operand was negative none of the sign adjust cycles are skipped Register writeback to HI and LO are done in the A stage Figure 2 15 shows the pipeline flow for a divide operation The repeat rate is either 34 35 or 36 cycles depending on how many sign adjust cycles are skipped as a second divide can be in the E stage when the first divide is in the last Mypyu Stage MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 21 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 2 Pipeline Clock 1 2 3 34 35 36 37 38 EStage E mupu gt I mupu PI mupu gt muu FI Ampu PI wupu gt RS Adjust Add Subtract Sign Adjust 1 Sign Adjust 2 HI LO Write Figure 2 15 4KEp MDU Pipeline Flow During a Divide DIV Operation 2 7 Branch Delay The pipeline has a branch delay of one cycle The one cycle branch delay is a result of the branch decision logic operating during the E pipeline stage This allows the branch target address to be used in the I stage of the instruction following 2 cycles after the branch instruction By executing the 1st instruction following the branch instruction sequentially before switching to the branch target
80. based implementation used in the 4KEc core A pipelined MDU like the 4KEc core is used The 4KEp core contains the same FMT based MMU like the 4KEm core but a smaller non pipelined MDU The term 4KE core as used in this document generally refers to all cores in the 4KE family When referring to characteristics unique to an individual family member the specific core type 4KEc 4KEm or 4KEp core will be identified On a 4KE core instruction and data caches are optional and fully programmable from 0 64 Kbytes in size In addition each cache can be organized as direct mapped 2 way 3 way or 4 way set associative On a cache miss loads are blocked only until the first critical word becomes available The pipeline resumes execution while the remaining words are being written to the cache Both caches are virtually indexed and physically tagged Virtual indexing allows the cache to be indexed in the same clock in which the address is generated rather than waiting for the virtual to physical address translation in the TLB The core implements the MIPS32 Release 2 Instruction Set Architecture ISA and may optionally support the MIPS16e Application Specific Extension ASE for code compression The MMU of the 4KEc core contains a 4 entry instruction TLB ITLB a 4 entry data TLB DTLB and a 16 dual entry joint TLB JTLB with variable page sizes The 4AKEm and 4KEp cores contain a simplified fixed mapping translation FMT mechanism for ap
81. compatibility with existing MIPS implementations including many which pre date the MIPS32 architecture Because a pipeline flush clears hazards on most early implementations the JALR HB or JR HB instructions can be included in existing software for backward and forward compatibility See the JALR HB and JR HB instructions for additional information 30 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 2 13 Hazards The SYNCI instruction is encoded using a new encoding of the REGIMM opcode This encoding was chosen because it causes a Reserved Instruction exception on all Release 1 implementations As such kernel software running on processors that don t implement Release 2 can emulate the function using the CACHE instruction 2 13 3 Eliminating Hazards The Spacing column shown in Table 2 6 and Table 2 7 indicates the number of unrelated instructions such as NOPs or SSNOPs that prior to the capabilities of Release 2 would need to be placed between the producer and consumer of the hazard in order to ensure that the effects of the first instruction are seen by the second instruction Entries in the table that are listed as 0 are traditional MIPS hazards which are not hazards on the 4KE core With the hazard elimination instructions available in Release 2 the preferred method to eliminate hazards is to place one of the instructions listed in Table 2 8
82. exception The reset value of the bit depends on whether the EJTAGBOOT indication is given or not No EJTAGBOOT indication given 0 EJTAGBOOT indication given 1 ProbEn bit bit 0 in the Debug Control Register DCR Oor 1 from EJTAGBOOT MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 199 Chapter 9 EJTAG Debug Support Fields Table 9 23 EJTAG Control Register Descriptions Continued Name Bit s Description Read Write Reset State ProbTrap Res Probe Trap This bit controls the location of the debug exception vector 0 In normal memory OxBFCO 0480 1 In EITAG memory at OxFF20 0200 in dmseg Valid setting of the ProbTrap bit depends on the setting of the ProbEn bit see comment under ProbEn bit The ProbTrap should not be set to 1 for debug exception vector in EJTAG memory unless the ProbEn bit is also set to 1 to indicate that the EJTAG memory may be accessed The read value indicates the effective value to the CPU due to synchronization issues between TCK and CPU clock domains however it is ensured that change of the ProbTrap bit prior to setting the EjtagBrk bit will have effect for the EjtagBrk The reset value of the bit depends on whether the EJTAGBOOT indication is given or not No EJTAGBOOT indication given 0 EJTAGBOOT indication given 1 reserved Oor1 from
83. for the 4KEm and 4KEp cores In the 4KEm and 4KEp cores note that the FM MMU replaces the ITLB DTLB and JTLB found in the 4KEc core MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 33 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 3 Memory Management Instruction Virtual Address IVA Data Virtual Address DVA e Instruction Cache RAM Tag IPA Instruction Physical Address IPA Comparator Instruction Hit Miss Data Physical Data Address gt Hit Miss DPA DTLB Comparator A Data Tag DPA Cache RAM Figure 3 1 Address Translation During a Cache Access in the 4KEc core Instruction Virtual Address IVA Data Virtual Address DVA Instruction Tag IPA Cache RAM Instruction Physical Address IPA FM MMU Comparator Instruction Hit Miss Data Physical Data DPA Comparator Data Cache RAM Tag DPA Figure 3 2 Address Translation During a Cache Access in the 4KEm and 4KEp Cores 3 2 Modes of Operation A 4KE processor core supports three modes of operation 34 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 3 2 Modes of Operation User mode Kernel mode Debug mode User mode is most often
84. held static In the 4KE processor core all interlocks are handled as slips 2 11 Slip Conditions On every clock internal logic determines whether each pipe stage is allowed to advance These slip conditions propagate backwards down the pipe For example if the M stage does not advance neither does the E or I stage Slipped instructions are retried on subsequent cycles until they issue The back end of the pipeline advances normally during slips This resolves the conflict when the slip was caused by a missing result NOPs are inserted into the bubble in the pipeline Figure 2 22 on page 27 shows an instruction cache miss 26 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 2 12 Instruction Interlocks Clock 1 2 3 4 5 6 Stage 4 de de 1 Le ud s s i E I hil ly l4 Is M SJ ee Wate te A vlui l lofo D Cache miss detected Critical word received Execute E stage Figure 2 22 Instruction Cache Miss Slip Figure 2 22 on page 27 shows a diagram of a two cycle slip In the first clock cycle the pipeline is full and the cache miss is detected Instruction IO is in the A stage instruction I1 is in the M stage instruction I2 is in the E stage and instruction I3 is in the I stage The cache miss occurs in clock 2 when the I4 instruction fetch is attempted I4 advances to the E stage and waits for the instruction to be fet
85. in implementation 0 No ASID in implementation 1 6 bit ASID 2 8 bit ASID 3 Reserved EJ_DINTsup 4KEc core 2 4KEm 4KEp cores 0 reserved reserved MIPS 16 Indicates whether MIPS 16 is implemented 0 No MIPS 16 support 1 MIPS16 implemented Preset reserved reserved NoDMA No EJTAG DMA Support reserved reserved 9 4 2 4 EJTAG Control Register This 32 bit register controls the various operations of the TAP modules This register is selected by shifting in the CONTROL instruction Bits in the EJTAG Control register can be set cleared by shifting in data status is read by shifting out the contents of this register This EJTAG Control register can only be accessed by the TAP interface The EJTAG Control register is not updated in the Update DR state unless the Reset occurred Rocc bit 31 is either 0 or written to 0 This is in order to ensure prober handling of processor accesses The value used for reset indicated in the table below takes effect on both hard and soft CPU resets but not on TAP controller resets by e g TRST_N TCK clock is not required when the hard or soft CPU reset occurs but the bits are still updated to the reset value when the TCK applies The first 5 TCK clocks after hard or soft CPU resets may result in reset of the bits due to synchronization between clock domains 31 30 29 28 EJTAG Control Register Format 23 22 21 20 19 18 17 16 15 14 196
86. interpreting the instruction and returning the virtualized value For example if it is not desirable to provide direct access to the Count register access to that register may be individually disabled and the return value can be virtualized by the operating system 100 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions 5 2 9 BadVAddr Register CPO Register 8 Select 0 The BadVAdar register is a read only register that captures the most recent virtual address that caused one of the following exceptions Address error AdEL or AdES TLB Refill 4KEc core TLB Invalid 4KEc core TLB Modified 4KEc core The BadVAddr register does not capture address information for cache or bus errors since they are not addressing errors Figure 5 10 BadVAddr Register Format 31 0 BadVAddr Table 5 13 BadVAddr Register Field Description Fields Name Description Reset State Bad virtual address oR Undefined BadVAddr MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 101 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers 5 2 10 Count Register CPO Register 9 Select 0 The Count register acts as a timer incrementing at a constant rate whether or not an instruction is executed retired or any forward progress is
87. is written by hardware on a TLB R W 0 exception or on a TLB read and is by software before a TLB write If writes are not enabled and in implementations of Release 1 of the Architecture this field must be written with zero and returns zeros on read 9 ma URS Written SE E Lei re Address space identifier This field is written by hardware on a TLB read and by software to establish the Eh 750 current ASID value for TLB write and against which ES Undefined TLB references match each entry s TLB ASID field MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 103 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers 5 2 12 Compare Register CP0 Register 11 Select 0 The Compare register acts in conjunction with the Count register to implement a timer and timer interrupt function The timer interrupt is an output of the cores The Compare register maintains a stable value and does not change on its own When the value of the Count register equals the value of the Compare register the SI_TimerInt pin is asserted This pin will remain asserted until the Compare register is written The SI TimerInt pin can be fed back into the core on one of the interrupt pins to generate an interrupt Traditionally this has been done by multiplexing it with hardware interrupt 5 to set interrupt bit IP 7 in the Cause register For diagnostic purposes the Compare register is
88. must be one or the current U 21 process ASID must match the ASID field in this R W Undefined register When set to zero trace is disabled in User Mode irrespective of other bits This is a mask value applied to the ASID comparison done when the G bit is zero A 1 in any bit in this field inhibits the corresponding ASID bit from participating in the match As such a value of zero in this field compares all bits of ASID Note that the ASID M 20 13 ability to mask the ASID value is not available in the R W Undefined hardware signal bit it is only available via the software control register In the 4KEm and 4KEp cores where ASID is not supported this field is ignored on write and returns zero on read R W R W The ASID field to match when the G bit is zero When the G bit is one this field is ignored ASID 12 5 In the 4KEm and 4KEp cores where ASID is not supported this field is ignored on write and returns zero on read Global bit When set to one tracing is to be enabled for all processes provided that other enabling functions like U S etc are also true G 4 In the 4KEm and 4KEp cores where ASID is not supported this field is ignored on write and returns 1 on read This causes all match equations to work correctly in the absence of an ASID MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 137 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers
89. nene en enne en treten nennen 149 6 1 Hardware Initialized Processor State esee eeo neei ekaa teet nennen nennen tenere tree nete ennt etes 149 6 LJ Coprocessor 0 State 55 5 sce aa ee ete trees te bete eins 149 6 1 2 TLB Initialization 4KBc core only Annae aieiaa ea REE ENEE E EE E E A EEE R 150 6 1 3 Bus State Machines tentent aee eee ee ip ba e Ba el aa atin 150 6 14 Static Configuration Inp ts 3 ettet redet der tt eee pere p een eene p erp eee ts 150 6 L5 Retchr Address 5 eei Reap e en mere P qi 150 6 2 Software Imtialized Processor State ele eege EE E ife te e REESEN 150 6 2 T Register Elle ns BGG eG EURO bereit taedet iere se 150 622 TEB AKEc Core E WEE 150 6 2 3 Caches i si eS etd d erm Oe Ne ee m eet 151 6 24 Coprocessor OS tate 3 undae ER e Ded e n ete le RE eei dene de teet 151 Chapter 7 Caches iiie edes eae t RR DP OH OH OH EEDE ESES rE ESER eao SERRET Saht 153 7 1 Cache Config ratiOns egene eege AE RE ORE DERE t E RUE E E HERE NE ERE SEELEN 153 4 2 Cache Protocols 5 nti rap Pr ed ee ENEE A re Or Rcge 155 7 2 Cache Organization 5 5 ente n ee tee tete e am eie iet a eerte 155 7 2 2 Cacheability Attributes ette e t casgeecasshawebaeeseyescouadsvessseasdsosessaaberens 156 7 2 3 Replacement Policy ai diac eee HRS ee eege eege E Seege EES 156 T24 Virtual Aliasing a ee ERO LO e RP D Oed Ld eis 157 1 3 Instruction Cache eene IRSE RABIA eR aS Se ees I Es 158 TA Data Cache uices DU eene eredi RU CHEN
90. obsolete references to 2 bit ISA mode field Corrected the heading format in Section 10 2 1 Scheduling a Load Delay Slot on page 232 Changed confidentiality level to commercial 01 07 December 5 2001 Clarified handling of all locked cache ways EJTAG Version field in Debug register is set to 010 Added description for constant fields in Debug register 01 08 January 30 2002 NoDCR NoSSt MCheckP CacheEP DDBSImpr DDBLImpr Major update for addition of MIPS32 Release 2 features Added support for 64MB and 256MB pages in TLB 4KEc core only 02 00 November 8 2002 Wrong bit of MM field in Config register was being used Describe as 2b field now Address region for DSEG was wrong in figure in memory management chapter 280 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved
91. of 32x16 represents the rt operand The core only checks the latter rt operand value to determine how many times the operation must pass through the multiplier array The 16x16 and 32x16 operations pass through the multiplier array once A 32x32 operation passes through the multiplier array twice The MDU supports execution of a 16x16 or 32x16 multiply operation every clock cycle 32x32 multiply operations can be issued every other clock cycle Appropriate interlocks are implemented to stall the issue of back to back 32x32 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 15 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 2 Pipeline 16 multiply operations Multiply operand size is automatically determined by logic built into the MDU Divide operations are implemented with a simple 1 bit per clock iterative algorithm with an early in detection of sign extension on the dividend rs Any attempt to issue a subsequent MDU instruction while a divide is still active causes an IU pipeline stall until the divide operation is completed Table 2 1 lists the latencies number of cycles until a result is available for multiply and divide instructions The latencies are listed in terms of pipeline clocks In this table latency refers to the number of cycles necessary for the first instruction to produce the result needed by the second instruction Table 2 1 4KEc and 4KEm Core MDU Instruction Lat
92. of the ERL bit causes the assertion of the 7 ERL signal on the external bus indicating to the external agent that an error has occurred At this time the external agent can choose to either speed up the clocks and service the error or let it be serviced at the lower clock speed Similarly the EJ DebugM signal indicates that the processor is in debug mode Debug mode is entered when the processor takes a debug exception If fast handling of this is desired the external agent can speed up the clocks The core provides four power down signals that are part of the system interface Three of the pins change state as the corresponding bits in the CPO Status register are set or cleared The fourth pin indicates that the processor is in debug mode The S7 RP signal represents the state of the RP bit 27 in the CPO Status register The S7 EXL signal represents the state of the EXL bit 1 in the CPO Status register The ai ERL signal represents the state of the ERL bit 2 in the CPO Status register The EJ DebugM signal indicates that the processor has entered debug mode MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 163 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 8 Power Management 8 2 Instruction Controlled Power Management The second mechanism for invoking power down mode is through execution of the WAIT instruction If the bus is idle at the time the WAIT instruction reaches
93. of the on chip trace memory the increment wraps back to address zero This register is reserved if on chip trace memory is not implemented The format of the TCBTW register is shown below and the field is described in Table 9 34 TCBTW Register Format 63 0 Data Table 9 34 TCBTW Register Field Descriptions Fields Read Reset Names Bits Description Write State me Pao mene 218 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 9 Trace Control Block TCB Registers hardware control 9 9 6 TCBRDP Register Reg 5 The TCBRDP register is the address pointer to on chip trace memory It points to the TW read when reading the TCBTW register When writing the TCBCONTROLBpy bit to 1 this pointer is reset to the current value of TCBSTP This register is reserved if on chip trace memory is not implemented The format of the TCBRDP register is shown below and the field is described in Table 9 35 The value of n depends on the size of the on chip trace memory As the address points to a 64 bit TW lower three bits are always zero TCBRDP Register Format 31 nil n 0 Address Table 9 35 TCBRDP Register Field Descriptions Fields Description Data 31 n 1 Reserved Must be written zero reads back zero 0 0 Address n 0 Byte address of on chip trace memory word R W 0 9 9 7 TCBWRP Register Reg 6
94. operate without slips provided that all control and data information from the Coprocessor 2 is transferred in the M stage 2 10 Interlock Handling Smooth pipeline flow is interrupted when cache misses occur or when data dependencies are detected Interruptions handled entirely in hardware such as cache misses are referred to as interlocks At each cycle interlock conditions are checked for all active instructions Table 2 4 lists the types of pipeline interlocks for the 4KE processor cores MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 25 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 2 Pipeline Table 2 4 Pipeline Interlocks Interlock Type Sources Slip Stage ITLB Miss Instruction TLB Producer consumer hazards Instruction Hardware Dependencies MDU TLB BC2 waiting for COP2 Condition Check DTLB Miss Data TLB Load that misses in data cache Multi cycle cache Op Sync Data Cache Miss Store when write thru buffer full EJTAG breakpoint on store VA match needing data value comparison Store hitting in fill buffer Coprocessor 2 control and or data delay Coprocessor 2 completion slip from coprocessor A Stage In general MIPS processors support two types of hardware interlocks Stalls which are resolved by halting the pipeline Slips which allow one part of the pipeline to advance while another part of the pipeline is
95. processor operates in Kernel mode when the DM bit in the Debug register is O and the Status register contains one or more of the following values e UM 0 ERL 1 EXL 1 When a non debug exception is detected EXL or ERL will be set and the processor will enter Kernel mode At the end of the exception handler routine an Exception Return ERET instruction is generally executed The ERET instruction jumps to the Exception PC clears ERL and clears EXL if ERL O This may return the processor to User mode Kernel mode virtual address space is divided into regions differentiated by the high order bits of the virtual address as shown in Figure 3 5 on page 39 Also Table 3 2 lists the characteristics of the Kernel mode segments MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 3 2 Modes of Operation OxFFFF FFFF 0xE000_0000 Kernel virtual address space Mapped 512MB kseg3 OxDFFF FFFF 0xC0O00 0000 Kernel virtual address space Mapped 512MB kseg2 OxBFFF FFFE 0xA000_0000 Ox9FFF FFFF 0x8000 0000 Kernel virtual address space Unmapped Uncached 512MB Kernel virtual address space Unmapped 512MB kseg1 ksegO Ox7FFE_FFFF 0x0000_0000 Mapped 2048MB kuseg Figure 3 5 Kernel Mode Virtual Address Space Table 3 2 Kernel Mode Segments Status Register Is One of These Va
96. referred to as the 4KE Pro core When licensed 16 instructions in the opcode map are available for UDI and each instruction can have single or multi cycle latency A UDI instruction can operate on any one or two general purpose registers or immediate data contained within the instruction and must always write the result of each instruction back to a general purpose register Implementation details for UDI can be found in other documents available from MIPS Refer to Section 11 3 Special2 Opcode Encoding of Function Field for a specification of the opcode map available for user defined instructions MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 2 Pipeline The MIPS32 4KE processor core implements a 5 stage pipeline similar to the original R3000 pipeline The pipeline allows the processor to achieve high frequency while minimizing device complexity reducing both cost and power consumption This chapter contains the following sections Section 2 1 Pipeline Stages Section 2 2 Instruction Cache Miss Section 2 3 Data Cache Miss Section 2 4 Multiply Divide Operations Section 2 5 MDU Pipeline 4KEc and 4KEm Cores Section 2 6 MDU Pipeline 4KEp Core Section 2 7 Branch Delay Section 2 8 Data Bypassing Section 2 10 Interlock Handling Section 2 11 Slip Conditions Section 2 12 I
97. respectively The repeat rate is either 11 19 27 or 35 cycles one less if the sign adjust stage is skipped as a second divide can be in the RS Adjust stage when the first divide is in the Reg WR stage Clock 1 2 3 4 10 i1 12 13 Estage P E Muu Stage P Mun Stage Mun Stage P Mun Stage P Ampu Stage P Wun Stage P RS Adjust Add Subtract Add Subtract Rem Adjust Sign Adjust Early In Figure 2 9 MDU Pipeline Flow During a 8 bit Divide DIV Operation Clock 1 2 3 4 18 19 20 21 KN E Stage Mun Stage Mun Stage Mypu Stage Mypu Stage Ampu Stage Wun Stage gt LI LI LI LI LI LI LJ RS Adjust Add Subtract Add Subtract Rem Adjust Sign Adjust MDU Res Rdy Early In Figure 2 10 MDU Pipeline Flow During a 16 bit Divide DIV Operation Clock 1 2 3 4 26 27 28 29 Estage P E Mun Stage P Mun Stage P Mun Stage P Mun Stage P Ampu Stage P Wun Stage P rer RS Adjust Add Subtract Add Subtract Rem Adjust Sign Adjust MDU Res Rdy Early In Figure 2 11 MDU Pipeline Flow During a 24 bit Divide DIV Operation MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 19 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 2 Pipeline Clock 1 2 3 4 34 35 36 37 Estage P E Munu Stage P Mapu Stage P Mun Stage Mun Stage P Ampu Stage P Wunu Stage P RS Adjust Add Subtract Add Subtract Rem Adjust
98. rights reserved Chapter 4 Exceptions and Interrupts Entry Vector Used General exception vector offset 0x180 4 8 24 Debug Data Break Exception A debug data break exception occurs when a data hardware breakpoint matches the load store transaction of an executed load store instruction The DEPC register and DBD bit in the Debug register will indicate the load store instruction that caused the data hardware breakpoint to match The load store instruction that caused the debug exception has not completed e g not updated the register file and the instruction can be re executed after returning from the debug handler Debug Register Debug Status Bit Set DDBL for a load instruction or DDBS for a store instruction Additional State Saved None Entry Vector Used Debug exception vector 4 8 25 TLB Modified Exception Data Access 4KEc core only During a data access a TLB modified exception occurs on a store reference to a mapped address if the following condition is true The matching TLB entry is valid but not dirty Cause Register ExcCode Value Mod Additional State Saved Table 4 16 Register States on a TLB Modified Exception Register State Value BadVAddr failing address The Bad VPN field contains VA3 5 of the failing Context address The VPN2 field contains VA31 13 of the failing address EntryHi the ASID field contains the ASID of the reference that missed EntryLoO UNPREDICTABL
99. sequence atomically the following occur The 32 bit word of GPR rt is stored into memory at the location specified by the aligned effective address e A l indicating success is written into GPR rt Otherwise memory is not modified and a 0 indicating failure is written into GPR rt If the following event occurs between the execution of LL and SC the SC fails An ERET instruction is executed If either of the following events occurs between the execution of LL and SC the SC may succeed or it may fail the success or failure is not predictable Portable programs should not cause one of these events A memory access instruction load store or prefetch is executed on the processor executing the LL SC The instructions executed starting with the LL and ending with the SC do not lie in a 2048 byte contiguous region of virtual memory The region does not have to be aligned other than the alignment required for instruction words The following conditions must be true or the result of the SC is UNPREDICTABLE Execution of SC must have been preceded by execution of an LL instruction An RMW sequence executed without intervening events that would cause the SC to fail must use the same address in the LL and SC The address is the same if the virtual address physical address and cache coherence algorithm are identical 260 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Techno
100. set watch exceptions are enabled for loads that 0 for Cold match the address Reset only If this bitis set watch exceptions are enabled for stores that 0 for Cold match the address Reset only MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 131 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers 5 2 27 WatchHi Register CPO Register 19 Select 0 The WatchLo and WatchHi registers together provide the interface to a watchpoint debug facility that initiates a watch exception if an instruction or data access matches the address specified in the registers As such they duplicate some functions of the EJTAG debug solution Watch exceptions are taken only if the EXL and ERL bits are zero in the Status register If either bit is a one then the WP bit is set in the Cause register and the watch exception is deferred until both the EXL and ERL bits are zero The WatchHi register contains information that qualifies the virtual address specified in the WatchLo register an ASID a Global G bit and an optional address mask If the G bit is 1 then any virtual address reference that matches the specified address will cause a watch exception If the G bit is a 0 only those virtual address references for which the ASID value in the WatchHi register matches the ASID value in the EntryHi register cause a watch exception The optional mask field provides address masking to q
101. signal is decoded by the TAP controller to control test operation TMS is sampled on the rising edge of TCK The core signal for this is called EJ TMS Test Data Input Serial input data TDI is shifted into the Instruction register or data TDI registers on the rising edge of the TCK clock depending on the TAP controller state The core signal for this is called EJ TDI Test Data Output Serial output data is shifted from the Instruction or data register to the TDO o TDO pin on the falling edge of the TCK clock When no data is shifted out the TDO is 3 stated The core signal for this is called EJ TDO with output enable controlled by EJ TDOsstate MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 187 Chapter 9 EJTAG Debug Support Table 9 19 EJTAG Interface Pins Continued Pin Type Description Test Reset Input Optional pin The TRST_N pin is an active low signal for asynchronous reset of the TAP controller and instruction in the TAP module independent of the processor logic The processor is not reset by the assertion of TRST N TRST_N I The core signal for this is called EJ TRST N This signal is optional but power on reset must apply a low pulse on this signal at power on and then leave it high in case the signal is not available as a pin on the chip If available on the chip then it must be low on the board when the EJ
102. size of the on chip trace memory As the address points to a 64 bit TW lower three bits are always zero TCBSTP Register Format 31 n l n 0 Address Table 9 37 TCBSTP Register Field Descriptions Fields Description Data 31 n 1 Reserved Must be written zero reads back zero 0 0 Address n 0 Byte address of on chip trace memory word R W 0 9 9 9 TCBTRIGx Register Reg 16 23 Up to eight Trigger Control registers are possible Each register is named TCBTRIGx where x is a single digit number from 0 to 7 TCBTRIGO is Reg 16 The actual number of trigger registers implemented is defined in the TCBCONFIG pig field An unimplemented register will read all zeros and writes are ignored Each Trigger Control register controls when an associated trigger is fired and the action to be taken when the trigger occurs Please also read Chapter 9 EJTAG Debug Support on page 225 for detailed description of trigger logic issues The format of the TCBTRIGx register is shown below and the fields are described in Table 9 38 TCBTRIGx Register Format 31 24 23 22 17 16 15 14 13 7 6 5 4 3 2 1 0 TCBinfo Tra 0 CHI PD 0 DM CH PD Type FO TR ce Tro Troj Tri Tri Table 9 38 TCBTRIGx Register Field Descriptions Fields Read Reset Names Bits Description Write State TCBinfo to be used in a possible TF6 trace format when this R W 0 TCBinfo 31 24 trigger fires When set generate TF6 trace information
103. software in the usual case Debug software need not look at the DBD bit in the Debug register unless it wishes to identify the address of the instruction that actually caused the debug exception A unique debug exception is indicated through the DSS DBp DDBL DDBS DIB and DINT bits D bits at 5 0 in the Debug register No other CPO registers or fields are changed due to the debug exception thus no additional state is saved Operation if InstructionInBranchDelaySlot then DEPC PC 4 Debugpgp amp 1 else DEPC lt PC Debugpgp amp 0 endif Debugp pits at at 5 0 DebugExceptionType Debugyait HaltStatusAtDebugException Debugpoze DozeStatusAtDebugException Debugpy 1 ZE EJTAGControlRegisterp oprrap 1 then PC OxFF20 0200 else PC lt OxBFCO 0480 endif The same debug exception vector location is used for all debug exceptions The location is determined by the ProbTrap bit in the EJTAG Control register ECR as shown in Table 4 9 Table 4 9 Debug Exception Vector Addresses ProbTrap bit in ECR Register Debug Exception Vector Address 0 OxBFCO 0480 1 OxFF20_0200 in dmseg 4 8 Exceptions The following subsections describe each of the exceptions listed in the same sequence as shown in Table 4 1 4 8 1 Reset Exception A reset exception occurs when the S7_ColdReset signal is asserted to the processor This exception is not maskable When a Reset exception occurs
104. soon as it arrives as opposed to having the entire cache line written to the instruction cache then reading out the required word Figure 2 4 on page 14 shows a timing diagram of an instruction cache miss 1 L 1 MEM E e j E Le l 8 i l i e i i l Cache l i RegRd ALU Op FTLB ILR B ASel Bus IC Bypass Dec i i r i FAT LA Contains all of the cycles that address and data are utilizing the bus Figure 2 4 Data Cache Miss Timing 2 3 Data Cache Miss 14 When the data cache is indexed the data address is translated to determine if the required data resides in the cache A data cache miss occurs when the requested data address does not reside in the data cache When a data cache miss is detected in the M stage D TLB the core transitions to the A stage The pipeline stalls in the A stage until the miss is resolved requested data is returned The bus interface unit arbitrates between multiple requests and selects the correct address to be driven onto the bus B ASel in Figure 2 5 on page 15 The core drives the selected address onto the bus The number of clocks before data is returned is then determined by the array containing the data Once the data is returned to the core the critical word of data passes through the aligner before being forwarded to the execution unit The bypass mechanism allows the core to use the data as soon as it arrives as opposed to having the entire c
105. store address is traced When load data tracing is on the full load data read by each load instruction is traced indicated by the load flag Only actual read bytes are traced When store data tracing is on the full store data written by each store instruction is traced indicated by the store flag Only written bytes are traced After each synchronization instruction the first load address and the first store address following this are both traced with the full address if load store address tracing is enabled A SC Store Conditional instruction is not flagged as a store instruction if the load locked bit prevented the actual store MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 7 EJTAG Trace 9 7 5 Programmable processor trace mode options To enable tracing a global Trace On signal must be set When trace is on it is possible to enable tracing in any combination of the processor modes described in Section 9 7 1 Processor Modes on page 205 In addition to this trace can be turned on globally for all process or only for specific processes by tracing only specific masked values of the ASID found in EntryHi Asp 4KEc cores only Additionally an EJTAG Simple Break trigger point can override the processor mode and ASID selection and turn them all on Another trigger point can disable this override again 9 7 6 Programma
106. the Bad VPN2 field of the Context register The PTEBase field is written and used by the operating system The Bad VPN2 field of the Context register is not defined after an address error exception Figure 5 4 Context Register Format 31 23 22 43 21 0 PTEBase BadVPN2 0 Table 5 7 Context Register Field Descriptions Fields Name Description Reset State This field is for use by the operating system and is PTEBase normally written with a value that allows the operating Undefined system to use the Context Register as a pointer into the current PTE array in memory This field is written by hardware on a TLB miss It Undefined EE contains bits VA5 5 of the virtual address that missed 0 Must be written as zero returns zero on reads 0 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 95 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers 5 2 5 PageMask Register CP0 Register 5 Select 0 The PageMask register is a read write register used for reading from and writing to the TLB It holds a comparison mask that sets the variable page size for each TLB entry as shown in Table 5 9 Figure 5 5 shows the format of the PageMask register Table 5 8 describes the PageMask register fields This register is only valid with the TLB 4KEc core It is reserved if the FM is implemented 4KEm and 4KEp Figure 5 5 PageMask Register Format 31
107. the M stage of the pipeline the internal clocks are suspended and the pipeline is frozen However the internal timer and some of the input pins S7 Int 5 0 S NMI SI Reset SI ColdReset and EJ DINT continue to run If the bus is not idle at the time the WAIT instruction reaches the M stage the pipeline stalls until the bus becomes idle at which time the clocks are stopped Once the CPU is in instruction controlled power management mode any enabled interrupt NMI debug interrupt or reset condition causes the CPU to exit this mode and resume normal operation While the part is in this low power mode the 7 SLEEP signal is asserted to indicate to external agents what the state of the chip is 164 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support The EJTAG debug logic in the MIPS32 4KE processor cores provide three optional modules 1 Hardware breakpoints 2 Test Access Port TAP for a dedicated connection to a debug host 3 EJTAG Trace for program counter data address data value trace to On chip memory or to Trace probe This chapter contains the following sections Section 9 1 Debug Control Register on page 166 Section 9 2 Hardware Breakpoints on page 168 Section 9 3 Test Access Port TAP on page 187 Section 9 4 EJTAG TAP Registers on page 194 Section 9 5 TAP Processor Acc
108. the Status register e A TLB entry matches a reference to a mapped address space but the matched entry has the valid bit off The virtual address is greater than or equal to the bounds address in a FM based MMU Cause Register ExcCode Value TLBL Reference was a load or an instruction fetch TLBS Reference was a store Additional State Saved Table 4 14 CPO Register States on a TLB Invalid Exception Register State Value BadVAddr failing address The BadVPN2 field contains V 3 15 of the failing Context address The VPN2 field contains VA31 13 of the failing address EntryHi the ASID field contains the ASID of the reference that missed EntryLoO UNPREDICTABLE EntryLol UNPREDICTABLE Entry Vector Used General exception vector offset 0x180 4 8 13 Bus Error Exception Instruction Fetch or Data Access A bus error exception occurs when an instruction or data access makes a bus request due to a cache miss or an uncacheable reference and that request terminates in an error The bus error exception can occur on either an instruction fetch or a data access Bus error exceptions that occur on an instruction fetch have a higher priority than bus error exceptions that occur on a data access Bus errors taken on the requested critical word of an instruction fetch or data load are precise Other bus errors such as stores or non critical words of a burst read can be imprecise These errors are taken whe
109. the data to be returned MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Prefetch cont Table 11 16 Values of the hint Field for the PREF Instruction Value Name Data Use and Desired Prefetch Action load Use Prefetched data is expected to be read not modified Action Fetch data as if for a load store Reserved load_streamed Use Prefetched data is expected to be stored or modified Action Fetch data as if for a store Reserved treated as a NOP Use Prefetched data is expected to be read not modified but not reused extensively it streams through cache Action Fetch data as if for a load and place it in the cache so that it does not displace data prefetched as retained store_streamed load_retained store_retained Use Prefetched data is expected to be stored or modified but not reused extensively it streams through cache Action Fetch data as if for a store and place it in the cache so that it does not displace data prefetched as retained Use Prefetched data is expected to be read not modified and reused extensively it should be retained in the cache Action Fetch data as if for a load and place it in the cache so that it is not displaced by data prefetched as streamed Use Prefetched data is expected to be stored or modified and reused
110. to produce a trace on the probe or to on chip memory when trace information is sent on the PDtrace interface The main switch for this is the TCBCONTROLBygw bit When set the TCB will send trace information to either on chip trace memory or to the Trace Probe controlled by the setting of the TCBCONTROLB ofc bit The TCB can optionally include trigger logic which can control the TCBCONTROLB gy bit Please see Section 9 11 TCB Trigger logic for details 9 10 5 Tracing a reset exception Tracing a reset exception is possible However the TraceControlTs bit is reset to 0 at core reset so all the trace control must be from the TCB using TCBCONTROLA and TCBCONTROLD The PDtrace fifo and the entire TCB are reset based on an EJTAG reset It is thus possible to set up the trace modes etc using the TAP controller and then reset the processor core 9 11 TCB Trigger logic The TCB is optionally implemented with trigger unit If this is the case then the TCBCONFIGTRIG field is non zero This section will explain some of the issues around triggers in the TCB 9 11 1 Trigger units overview A TCB trigger logic features three main parts MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 225 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support 1 Acommon Trigger Source detection unit 2 ltoS8 separate Trigger Control units 3 Acommon Trigger Action unit Figure
111. to provide specified processor modes with the same capability This is done by introducing multiple copies of the GPRs called shadow sets and allowing privileged software to associate a shadow set with entry to kernel mode via an interrupt vector or exception The normal GPRs are logically considered shadow set zero The number of GPR shadow sets is a build time option on the 4KE core Although Release 2 of the Architecture defines a maximum of 16 shadow sets the core allows one the normal GPRs two or four shadow sets The highest number actually implemented is indicated by the SRSCtlygg field If this field is zero only the normal GPRs are implemented Shadow sets are new copies of the GPRs that can be substituted for the normal GPRs on entry to kernel mode via an interrupt or exception Once a shadow set is bound to a kernel mode entry condition reference to GPRs work exactly as one would expect but they are redirected to registers that are dedicated to that condition Privileged software may need to reference all GPRs in the register file even specific shadow registers that are not visible in the current mode The RDPGPR and WRPGPR instructions are used for this purpose The CSS field of the SRSCtl register provides the number of the current shadow register set and the PSS field of the SRSCtl register provides the number of the previous shadow register set that which was current before the last exception or interrupt occurred If the proce
112. true 9 2 5 2 Conditions for Matching Data Breakpoints When a data breakpoint is enabled that breakpoint is evaluated for every data transaction due to a load store instruction executed in non debug mode including load store for coprocessor and transactions causing an address error on data access The breakpoint is not evaluated due to a PREF instruction or other transactions which are not part of explicit load store transactions in the execution flow nor for addresses which are not the explicit load store source or destination address A breakpoint match depends on the transaction type TYPE as load or store the address and optionally the data value of a transaction The registers for each data breakpoint have the values and mask used in the compare and the equation that determines the match is shown below in C like notation The overall match equation is the DB match DB match TYPE load amp amp DBCnyozp TYPE store amp amp DBCnyosp amp amp DB addr match amp amp DB no value compare DB value match The match on the address part DB addr match depends on the virtual address of the transaction ADDR the ASID value and the accessed bytes BYTELANE where BYTELANE 0 is only if the byte at bits 7 0 on the bus is accessed and BYTELANE 1 is only if the byte at bits 15 8 is accessed etc The DB addr match is shown below DB addr match DBCnasipuse
113. used for application programs Kernel mode is typically used for handling exceptions and privileged operating system functions including CPO management and I O device accesses Debug mode is used for software debugging and most likely occurs within a software development tool The address translation performed by the MMU depends on the mode in which the processor is operating 3 2 1 Virtual Memory Segments The Virtual memory segments are different depending on the mode of operation Figure 3 3 on page 36 shows the segmentation for the 4 GByte 23 bytes virtual memory space addressed by a 32 bit virtual address for the three modes of operation The core enters Kernel mode both at reset and when an exception is recognized While in Kernel mode software has access to the entire address space as well as all CPO registers User mode accesses are limited to a subset of the virtual address space 0x0000_0000 to 0x7FFF_FFFF and can be inhibited from accessing CPO functions In User mode virtual addresses 0x8000_0000 to OXFFFF FFFF are invalid and cause an exception if accessed Debug mode is entered on a debug exception While in Debug mode the debug software has access to the same address space and CPO registers as for Kernel mode In addition while in Debug mode the core has access to the debug segment dseg This area overlays part of the kernel segment kseg3 dseg access in Debug mode can be turned on or off allowing full access to the entir
114. when this trigger fires Use TCBinfo field for the TCBinfo of TF6 and use Type field for the two MSB of the TCBtype of TF6 The two LSB of TCBtype are 00 The write value of this bit always controls the behavior of this Trace 23 trigger R W 0 When this trigger fires the read value will change to indicate if the TF6 format was ever suppressed by a simultaneous trigger If so the read value will be 0 If the write value was 0 the read value is always 0 This special read value is valid until the TCBTRIGx register is written 220 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 9 Trace Control Block TCB Registers hardware control Table 9 38 TCBTRIGx Register Field Descriptions Continued Fields Read Reset Names Bits Description Write State 0 22 16 Reserved Must be written as zero returns zero on read R 0 15 When set generate a single cycle strobe on TC ChipTrigOut when CHTro this trigger fires R W 0 PDTro 14 When set generate a single cycle strobe on TC_ProbeTrigOut R W 0 when this trigger fires 0 13 7 Reserved Must be written as zero returns zero on read R 0 When set this Trigger will fire when a rising edge on the Debug mode indication from the core is detected The write value of this bit always controls the behavior of this trigger DM 6 R W 0 When this trigger fire
115. zeros on reads f This field encodes the physical address read by the most PAddr 31 4 27 0 recent Load Linked instruction R Undefined 130 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions 5 2 26 WatchLo Register CPO Register 18 Select 0 The WatchLo and WatchHi registers together provide the interface to a watchpoint debug facility that initiates a watch exception if an instruction or data access matches the address specified in the registers As such they duplicate some functions of the EJTAG debug solution Watch exceptions are taken only if the EXL and ERL bits are both zero in the Status register If either bit is a one the WP bit is set in the Cause register and the watch exception is deferred until both the EXL and ERL bits are zero The WatchLo register specifies the base virtual address and the type of reference instruction fetch load store to match Figure 5 28 WatchLo Register Format 31 3 2 10 VAddr I RW Table 5 32 WatchLo Register Field Descriptions Description Reset State This field specifies the virtual address to match Note that this is a doubleword address since bits 2 0 are used to Undefined control the type of match If this bit is set watch exceptions are enabled for 0 for Cold instruction fetches that match the address Reset only If this bitis
116. 0 Wired Table 5 11 Wired Register Field Descriptions Fields Read Description Write Reset State MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 99 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers 5 2 8 HWREna Register CPO Register 7 Select 0 The HWREna register contains a bit mask that determines which hardware registers are accessible via the RDHWR instruction Figure 5 9 shows the format of the HWREna Register Table 5 12 describes the HWREna register fields Figure 5 9 HWREna Register Format 0 0000 0000 0000 0000 0000 0000 0000 Mask Table 5 12 HWREna Register Field Descriptions Fields Read Description Write Reset State o9 314 Must be written with zero returns zero on read be written with zero returns zero on read Each bit in this Hie eminem sist enables access by the RDHWR instruction to a particular hardware register which may not be an actual register If bit n in this field is a 1 access is enabled to hardware register n If R W Mask an bit n of this field is a 0 access is disabled 0 See the RDHWR instruction for a list of valid hardware registers Privileged software may determine which of the hardware registers are accessible by the RDHWR instruction In doing so a register may be virtualized at the cost of handling a Reserved Instruction Exception
117. 00 else if ArchitectureRevision 2 2 then The fixed value of EBasea4 an forces the base to be in kseg0 or ksegl vectorBase lt EBasesg 4 5 164000 else vectorBase 16 8000 0000 endif endif Exception PC is the sum of vectorBase and vectorOffset PC lt vectorBases4 39 vectorBasez9 9 vectorOffsety9 9 No carry between bits 29 and 30 4 7 Debug Exception Processing All debug exceptions have the same basic processing flow The DEPC register is loaded with the program counter PC value at which execution will be restarted and the DBD bit is set appropriately in the Debug register The value loaded into the DEPC register is the current PC if the instruction is not in the delay slot of a branch or the PC 4 of the branch if the instruction is in the delay slot of a branch The DSS DBp DDBL DDBS DIB and DINT bits D bits at 5 0 in the Debug register are updated appropriately depending on the debug exception type Halt and Doze bits in the Debug register are updated appropriately DM bit in the Debug register is set to 1 68 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 4 8 Exceptions The processor is started at the debug exception vector The value loaded into DEPC represents the restart address for the debug exception and need not be modified by the debug exception handler
118. 11 1203 100100 011101 1230 101100 3120 111101 1302 001101 3201 111011 1320 101101 3210 111111 1 The order is indicated by listing the least recently used way to the left and the most recently used way to the right etc Table 7 6 Way Selection Encoding 3 Ways Selection Order WS 5 0 Selection Order WS 5 0 012 Oxx00x 120 1xx10x 021 Oxx01x 201 1xx01x 1 The order is indicated by listing the least recently used way to the left and the most recently used way to the right etc 2 A indicates a don t care when written and unpredictable when read MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 159 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 7 Caches Table 7 7 Way Selection Encoding 2 Ways Selection Order WS 5 0 Selection Order WS 5 0 01 XxxO xx 10 xxx1xx 1 The order is indicated by listing the least recently used way to the left and the most recently used way to the right etc 2 A indicates a don t care when written and unpredictable when read 7 6 Software Cache Testing Typically the cache RAM arrays will be tested using BIST Itis however possible for software running on the processor to test all of the arrays Of course testing of the I cache arrays should be done from an uncacheable space with interrupts disabled in order to maintain the cache contents There are multiple me
119. 11 of the virtual address The virtual address translation algorithm is modified to reflect the smaller page size If Config3sp 0 IKB pages are not implemented and this bit is ignored on write and returns zero on read MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions 5 2 7 Wired Register CP0 Register 6 Select 0 The Wired register is a read write register that specifies the boundary between the wired and random entries in the TLB as shown in Figure 5 7 on page 99 The width of the Wired field is calculated in the same manner as that described for the Index register above Wired entries are fixed non replaceable entries that are not overwritten by a TLBWR instruction Wired entries can be overwritten by a TLBWI instruction The Wired register is reset to zero by a Reset exception Writing the Wired register causes the Random register to reset to its upper bound The operation of the processor is undefined if a value greater than or equal to the number of TLB entries is written to the Wired register This register is only valid with a TLB 4KEc core It is reserved if the FM is implemented 4KEm and 4KEp cores Entry n 1 A E o ge c oO is Wired Register v A o 2 Entry 0 v Figure 5 7 Wired and Random Entries in the TLB Figure 5 8 Wired Register Format 31 4 3 0
120. 158 T CACHE Instr ctions 2 nm p ERION ERU ORI URL RUN RESH SERRE ONE REESE 159 7 6 Software Cache Testing 5 ce ttr tg E OR RE EE e RESI PEEL SERRE EFE EDE Tope EEEE EEES 160 7 6 T J Cache D cache TaS Arrays 3225 etch t mete ee ee eee tee tat etti eie een 160 7 6 2 Cache Data Array EENS NEE e ne t E eee pH REIR 160 7 6 3 Cache WS Array uoo dutenee Denuo ure eei 160 7 6 4 D Cache Data Array 1 teo etin dete de ne AER it deste ir E S akg ES 160 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All right reserved 7 6 5 D cache WS ATTAY oe coats HER TRO ER ERE HEREDI 160 Tp Memory Cobhetrence ISSues e aeg epe tm ted rettet He edel ec E e eoe Pe E pee ee e er 161 Chapter 3 Power Management s Eed e peste eeh eter te gere tese tre aepo gx dere 163 8 1 Register Controlled Power Management sess nennen nennen neret inneren en nre en treten trennen 163 8 2 Instruction Controlled Power Management oo eee esee nennen neeneneneeeenen netter et en eret en reete nennen 164 Chapter 9 EJTAG Debug Support 2 2 n ee Setter pibe ne E oO ERU HR ERU ce E ru Se te et 165 9 1 Debug Control Register 5s rh e e UE RE Re e Re Sa ees ES hs 166 92 Hardware Breakpoints estem e eH e RT Ure UE REOR 168 9 2 1 Features of Instruction Breakpoint esee enne etre en EE EOE Eo E entretenir treten ene 168 9 2 2 Features of Data Breakpoin
121. 2 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 7 5 CACHE Instruction 7 5 CACHE Instruction Both caches support the CACHE instructions which allow users to manipulate the contents of the Data and Tag arrays including the locking of individual cache lines Note that before the CACHE instructions are allowed to execute all initiated refills are completed and stores are sent to the write buffer The CACHE instructions are described in detail in Chapter 11 MIPS32 4KE Processor Core Instructions on page 237 The CACHE Index Load Tag and Index Store Tag instructions can be used to read and write the WS RAM by setting the WST bit in the ErrCtl register The ErrCtl register is described in Section 5 2 34 ErrCtl Register CPO Register 26 Select 0 on page 144 Note that when the WST bit is zero the CACHE index instructions access the cache Tag array Not all values of the WS field are valid for defining the order in which the ways are selected This is only an issue however if the WS RAM is written after the initialization invalidation of the Tag array Valid WS field encodings for way selection order is shown in Table 7 5 Table 7 6 and Table 7 7 Table 7 5 Way Selection Encoding 4 Ways Selection Order WS 5 0 Selection Order WS 5 0 010010 101110 010001 111010 010011 111110 000100 011001 1032 000101 0110
122. 2 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support 182 9 2 9 3 Data Breakpoint Address Mask n DBMn Register Compliance Level Implemented only for implemented data breakpoints The Data Breakpoint Address Mask n DBMn register has the mask for the address compare used in the condition for data breakpoint n DBMn Register Format 31 0 DBM Table 9 15 DBMn Register Field Descriptions Fields pp Read Name Bit s Description Write Reset State Data breakpoint address mask for condition DBM 31 0 0 Corresponding address bit not masked R W Undefined 1 Corresponding address bit masked MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 2 Hardware Breakpoints 9 2 9 4 Data Breakpoint ASID n DBASIDn Register Compliance Level Implemented only for implemented data breakpoints The Data Breakpoint ASID n DBASIDn register has the ASID value used in the compare for data breakpoint n This register is only valid in the 4Kc core DBASIDn Register Format 31 8 7 Res ASID Table 9 16 DBASIDn Register Field Descriptions Fields Description Reset State Res 31 8 Must be written as zero returns zero on read R 0 ASID 7 0 Data breakpoint ASID value for compares R W Undefined MIPS32 4KE Processor Cores Software User s Manual Revision 02 00
123. 212 9 9 3 TCBDATA Register eine DR erede M gne ghe 216 9 9 4 TCBCONFIG Register Reg Q osses irtiri e rtp ttp bec deer e tet 217 9 9 5 TCBTW Register Reg 4 ni ee EENEG Ze ALATA LARA Ie 218 9 9 6 TCBRDP Register Reg S iios nten ete oe eR ERU PEE e Er eb ce Eo t tope IRR 219 9 0 T TCBWRP Register Reg 6 i eco er UI UU ERE NER DURUM Eres 219 9 9 8 TCBSTP Register Reg 7 3o reo eei ee e P ERROR RO RR I ELE RES 219 9 9 9 TCBTRIGx Register Reg 16 23 cene e ee ee federe tle ed esse ni e seca e ce rendere 220 9 9 10 Register Reset State sion eepeeo tene peo Ret Ee e e EP RUPES ER get 222 9 TO EJTAG Tr ce Enabling eR qr Ru e EEEE E E EEE EE PR te un 223 9 10 1 Trace Trigger from EJTAG Hardware Instruction Data Breakpoints 223 vi MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All right reserved 9 10 2 Turning On PDtrace Trace eii e nete teen et rerit entren nente AEE Ea eter tenere ene 223 910 3 Tutmng Off PDtrace M Trace ine een e e oie ro e ie eer ep pos 224 9510 4 TCB Trace Enabling e Ere aet erre ries e eot Eu 225 9 10 5 Tracing Re EE 225 OVI TCB Ingeetrdlogie s cs Sah ches seats el ae sep Wate NT ee BIO naher mn ee a eas 225 9 41 1 Tngger UNITS OVerVIeW Lai ee mere ei de e e onde eet tes 225 9 112 Tngeer source Unit eS Ed eee et ed nre er ete eene 226 9 HE 3 Trigger Control Units iier teet niter e e RU Ie n Ee E EE eee eere 227 9 11
124. 24 Tngger Acton Unit iuis cian dig Ge RnB eene iba eme eS 227 SE SumultaneoUS trig BER 7 sso ey ged copay reete sede suse o e p t e re pere pete ener de ir Pus 227 9 12 EJTAG Trace cycle by cycle behavior ssssssssssseeseesee eee nennen nennen tenere tre ennt innen ennes 228 9 12 1 Fifo logic in PDtrace and TCB modules essere nennen nennen nennen trennen 228 9 12 2 Handling of Fifo overflow in the PDtrace module essent 228 9 12 3 Handling of Fifo overflow in the TCB e e aaar aeaaeae apan Ee oeo eene nennen enne enne enne nen nene 229 9 12 4 Adding cycle accurate information to the trace eee nee nenneene 230 9 13 TGB Elon Trace Memory etim teet recte e ire eee b eec dee tee neiges 230 9 13 1 On Chip Trace Memory Size soiien eiin eei nennen nne etre et en trennen EENE Er Eae Eai 230 9 13 2 Trace From Mode nee ant eed te e te ver pe n Pre e Rr eee pos 230 9 13 3 Trace To Mode orae t eer rte T Dt dee PIER P I eie ERR RUE TERRY 230 Chapter 10 Instruction Set Overview sssssseeseeeeeeeeeenee ennt tertie enne teer etr etr et nente senese ete nett tenete tenen ene 231 10 1 CPU Instruction Formats 5t ep en Pe E Pee e rre n ee EP Pee 231 10 2 Load and Store Instructions eet eee deberet te Delete bee Tee de ENEE 232 10 2 1 Scheduling a Load Delay Slots citer ted rete eee en Ue E vere Eeer 232 10 2 2 Defining Access Types xen epp EE Ob e nne 232 10 3 Computational ns
125. 3 1 Introduction The MMU in a 4KE processor core will translate any virtual address to a physical address before a request is sent to the cache controllers for tag comparison or to the bus interface unit for an external memory reference This translation is a very useful feature for operating systems when trying to manage physical memory to accommodate multiple tasks active in the same memory possibly on the same virtual address but of course in different locations in physical memory 4KEc core only Other features handled by the MMU are protection of memory areas and defining the cache protocol In the 4KEc processor core the MMU is TLB based The TLB consists of three address translation buffers a 16 dual entry fully associative Joint TLB JTLB a 4 entry instruction micro TLB ITLB and a 4 entry data micro TLB DTLB When an address is translated the appropriate micro TLB ITLB or DTLB is accessed first If the translation is not found in the micro TLB the JTLB is accessed If there is a miss in the JTLB an exception is taken In the 4KEm and 4KEp processor cores the MMU is based on a simple algorithm to translate virtual addresses into physical addresses via a Fixed Mapping FM mechanism These translations are different for various regions of the virtual address space useg kuseg kseg0 ksegl kseg2 3 Figure 3 1 shows how the memory management unit interacts with cache accesses in the 4KEc core while Figure 3 2 shows the equivalent
126. 3 CPA MDU Fes Sign Adjust Last stage of Divide is a sign adjust i MDU Res Result can be read from MDU i i Divide yfi Sign Adjust MDU Res T i i l l 1 One or more cycles Figure 2 1 4KE Core Pipeline Stages Figure 2 2 shows the operations performed in each pipeline stage of the 4KEm processor core I Cachd Cache Tag and Data read 1 Dec Instruction Decode Register file read RegR I AC1 Tac Instruction Address Calculation stage 1 and 2 ALU Op Arithmetic Logic and Shift operations l l l l Cache o l l Ee W BE AC Data Address Calculation EV D Cache Tag and Data read I o D Cache H d i fT Alian Load data aligner l A gt E Bypass re I ul Register file wri i x yp l WE RegW Gre ee MUL MDU Res RegW d fm MUL instruciuon i i l g CPA Carry Propagate Adder Mult 16x16 CPA MDU Res Mult Macc dS Sie GE Accumulate instructions l l 4 Divide Divide instruc ions i i Mu _ axa CPA MDU Res A Sign Adjust Last stage of Divide is a sign adjust MDU Res Result can be read from MDU m i Divide JI Sign Adjust MDU Res One or more cycles I l Figure 2 2 4KEm Core Pipeline Stages Figure 2 3 shows the operations performed in each pipeline stage of the 4KEp processor core l Cache Tag and Data read
127. 35 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 10 Instruction Set Overview 10 7 6 MSUBU Multiply and Subtract Unsigned Word The MSUBU instruction multiplies two unsigned words and subtracts the result from the HI LO register pair The 32 bit word value in the GPR rs is multiplied by the 32 bit value in the GPR rt treating both operands as unsigned values to produce a 64 bit result The product is subtracted from the 64 bit concatenated values in the HI and LO register pair The resulting value is then written back to the HI and LO registers No arithmetic exception occurs under any circumstances 10 7 7 MUL Multiply Word The MUL instruction multiplies two words and writes the result to a GPR The 32 bit word value in the GPR rs is multiplied by the 32 bit value in the GPR rf treating both operands as signed values to produce a 64 bit result The least significant 32 bits of the product are written to the GPR rd The contents of the HI and LO register pair are not defined after the operation No arithmetic exception occurs under any circumstances 10 7 8 SSNOP Superscalar Inhibit NOP The MIPS32 4KE processor cores treat this instruction as a regular NOP 236 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 11 MIPS321M AKETM Processor Core Instructions This chapter supplements the MIPS32 Arc
128. 4 13 CPO Register States on a TLB Refill Exception esses ener nennen nennen nennen nne ene 75 Table 4 14 CPO Register States on a TLB Invalid Exception rennen ener ene 76 Table 4 15 Register States on a Coprocessor Unusable Exception sese 78 Table 4 16 Register States on a TLB Modified Exception essere nennen nennen nennen nennen trees 80 fip MEMOIRE 88 Table 5 2 CPO Register Field Types a R ennt rennen rennen nente en tente EE R enne s 90 Table 5 3 Index Register Field Descriptions eect ceseeeeceseeeeceseeseceseeeeecaeeeaecaeesaecsaesaecascsaecuecsseeseseaeseaseaeseaeenaseaesaes 91 Table 5 4 Random Register Field Descriptions 0 00 0 eee ceeeeccesseeeceseeeeceseeeeecaeeesecaeesaecsaesaecnecssecueesseseeeseseaseaeseaesaaseaesaee 92 Table 5 5 EntryLoO EntryLol Register Field Descriptions nennen nennen nennen retener trente 93 Table 5 6 Cache Coherency Attributes sno n a ian ee Ea erae E eaaa SVE RAE eene innen Eon entren entente ESETE tnnt teretes 94 Table 5 7 Context Register Field Descriptions sosie moorei eposie enere apen p rh eee Ee poe EEOSE OE E EOTS OESR raipen N RESE espre EES 95 Table 5 8 PageMask Register Field Descrppong esses ener nennen nennen nennen retener trees 96 Table 5 9 Values for the Mask and MaskX Fields of the PageMask Register aue eie eite t 96 Table 5 10 PageGrain Register Field Descriptions e
129. 4KEc core Store TLB hit to page with V 0 4KEc core TLB Mod Store to TLB page with D 0 4KEc core DBE Load or store bus error DDBL EJTAG data hardware breakpoint matched in load data compare 4 3 Interrupts Older 32 bit cores available from MIPS that implemented Release 1 of the Architecture included support for two software interrupts six hardware interrupts and a special purpose timer interrupt Note that the Architecture also defines a performance counter interrupt but this is not implemented on the 4KE core The timer interrupt was provided external to the core and typically combined with hardware interrupt 5 in an system dependent manner Interrupts were handled either through the general exception vector offset 16 180 or the special interrupt vector 1685200 based on the value of Causeyy Software was required to prioritize interrupts as a function of the Cause bits in the interrupt handler prologue Release 2 of the Architecture implemented by the 4KE core adds an upward compatible extension to the Release 1 interrupt architecture that supports vectored interrupts In addition Release 2 adds a new interrupt mode that supports the use of an external interrupt controller by changing the interrupt architecture 4 3 1 Interrupt Modes The 4KE core includes support for three interrupt modes as defined by Release 2 of the Architecture nterrupt compatibility mode which acts identically to that in an implementat
130. 7 11 2 MIPS32 4KB Opcode Map sears 5 It ert te eee Ie er he eee Maus a i e de edits 237 11 3 MIPS32 Instruction Set for the 4KE core eeeeeeeeeeeeeeeeeeeeeeeeeee neenon teen tentent treten tente nenne tenete 240 Chapter 12 MIPS16 Application Specific Extension to the MIPS32 Instruction Set esse 273 12 1 Instruction Bit Encoding iser ettet tete tere etr em de e b eee rideo He lue 273 12 2 Instruction Lasting tee Reeg Ee AEN peel 275 Appendix A Revision History vue Pere asia 279 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All right reserved vii viii List of Figures Figure 1 1 4KE Processor Core Block Diagram 5 5 dett ern re EH eet e Re ie tei deed 5 Figure 1 2 Address Translation During a Cache ACCESS essere ener nem entree nennen trennen 7 Figure 2 1 AK E Core Pipeline Stages eee tee t de tei oe ete sues ee Rn e e ideo eb SEE ec eoe 12 Figure 2 2 4KEm Core Pipeline Stages esses enne ener en nen eene sn trennen tente OENE etre nnne IT 12 Figure 2 3 AKEp Core Pipeline Stages s ete Ih eee ete Ep qu te e eec Pe canes 12 Figure 2 4 Data Cache Miss Timing eene ener ennet rennen ne etr entre trennen tenen retener rene ETET 14 Figure 2 5 Load Store Cache Mass Timing ioco temp tee e eR cess ag Weeds E EERE 15 Figure 2 6 MDU Pipeline Behavior During Multiply Operations 4KEc amp 4KEm Processors
131. 7 16 Must be written as zeros returns zero on read 0 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Table 5 19 SRSCt Register Field Descriptions Reset Description State Exception Shadow Set This field specifies the shadow set to use on entry to Kernel Mode caused by any exception other than a vectored interrupt The operation of the processor is UNDEFINED if 0 software writes a value into this field that is greater than the value in the HSS field Must be written as zeros returns zero on read 0 Previous Shadow Set If GPR shadow registers are implemented and with the exclusions noted in the next paragraph this field is copied from the CSS field when an exception or interrupt occurs An ERET instruction copies this value back into the CSS field if Statuspgy 0 This field is not updated on any exception which sets Statusppy to 1 i e Reset Soft Reset NMI cache 0 error an entry into EJTAG Debug mode or any exception or interrupt that occurs with Statusgx 1 or Statuspgy 1 This field is not updated on an exception that occurs while Statusgry 1 The operation of the processor is UNDEFINED if software writes a value into this field that is greater than the value in the HSS field Must be written as zeros returns zero on read 0 Current Shadow Set If GPR shadow registers are implemented this field is the number of the current GPR set
132. CODE Instruction This instruction selects the Implementation register for output which is always 32 bits 9 3 3 4 ADDRESS Instruction This instruction is used to select the Address register to be connected between TDI and TDO The EJTAG Probe shifts 32 bits through the TDI pin into the Address register and shifts out the captured address via the TDO pin 9 3 3 5 DATA Instruction This instruction is used to select the Data register to be connected between TDI and TDO The EJTAG Probe shifts 32 bits of TDI data into the Data register and shifts out the captured data via the TDO pin 9 3 3 6 CONTROL Instruction This instruction is used to select the EJTAG Control register to be connected between TDI and TDO The EJTAG Probe shifts 32 bits of TDI data into the EJTAG Control register and shifts out the EJTAG Control register bits via TDO MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 3 Test Access Port TAP 9 3 3 7 ALL Instruction This instruction is used to select the concatenation of the Address and Data register and the EJTAG Control register between TDI and TDO It can be used in particular if switching instructions in the instruction register takes too many TCK cycles The first bit shifted out is bit 0 TDI Address 0 SS L Data 0 m L EJTAG Control oL TDO Figure 9 2 Concatenation of the EJTAG Address Data and Co
133. D compare is supported in instruction breakpoints 0 No ASID compare 1 ASID compare IBASIDn register implemented 4KEc core ASIDsup 30 P 8 P i R 4KEm p cores 0 1 Supported 0 Not supported Res 29 28 Must be written as zero returns zero on read R 0 BCN 27 24 Number of instruction breakpoints implemented R 4 or 2 Res 23 4 Must be written as zero returns zero on read R 0 Break status for breakpoint n is at BS n with n from 0 BS 3 0 to 39 The bit is set to 1 when the condition for the R W Undefined corresponding breakpoint has matched Note a Based on actual hardware implemented Note b In case of only 2 Instruction breakpoints bit 2 and 3 become reserved MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 2 Hardware Breakpoints 9 2 8 2 Instruction Breakpoint Address n IBAn Register Compliance Level Implemented only for implemented instruction breakpoints The Instruction Breakpoint Address n JBAn register has the address used in the condition for instruction breakpoint n IBAn Register Format 31 0 IBA Table 9 8 IBAn Register Field Descriptions Fields Read Name Description Write Reset State IBA 31 0 Instruction breakpoint address for condition R W Undefined MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 175 Copyright 2000 2002 MIPS Technologies
134. E EntryLol UNPREDICTABLE Entry Vector Used General exception vector offset 0x180 80 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 4 9 Exception Handling and Servicing Flowcharts 4 9 Exception Handling and Servicing Flowcharts The remainder of this chapter contains flowcharts for the following exceptions and guidelines for their handlers General exceptions and their exception handler TLB miss exception and their exception handler Reset soft reset and NMI exceptions and a guideline to their handler Debug exceptions Generally speaking the exceptions are handled by hardware the exceptions are then serviced by software Note that unexpected debug exceptions to the debug exception vector at OXBFCO 0200 may be viewed as a reserved instruction since uncontrolled execution of an SDBBP instruction caused the exception The DERET instruction must be used at return from the debug exception handler in order to leave debug mode and return to non debug mode The DERET instruction returns to the address in the DEPC register MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 81 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 4 Exceptions and Interrupts Exceptions other than Reset Soft Reset NMI or first level TLB missNote Interrupts can be masked by IE or IMs and
135. EITAG hardware data breakpoints that may be implemented For example bit 16 corresponds to the first data breakpoint If 2 data breakpoints are present in the EJTAG implementation then they correspond to bits 16 and 17 The rest are always ignored by the tracing logic R W since they will never be triggered A value of one for each bit implies that a trigger from the corresponding data breakpoint should start tracing And a value of zero implies that tracing should be turned off with the trigger signal Used to specify whether the trigger signal from EJTAG instruction breakpoint should trigger tracing functions or not R W 0 disables trigger signals from instruction breakpoints 1 enables trigger signals from instruction breakpoints Reserved 0 Each of the 4 bits corresponds to the 4 possible EITAG hardware instruction breakpoints that may be implemented Bit 0 corresponds to the first instruction breakpoint and so on If only 2 instruction breakpoints are present in the EJTAG implementation then only IBPOn 3 0 bits 0 and 1 are used The rest are always ignored by the R W 0 tracing logic since they will never be triggered A value of one for each bit implies that a trigger from the corresponding instruction breakpoint should start tracing And a value of zero implies that tracing should be turned off with the trigger signal 142 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MI
136. Equal to Zero BTNEZ Branch on T Not Equal to Zero JAL Jump and Link No MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 277 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 12 MIPS16 Application Specific Extension to the MIPS32 Instruction Set Table 12 18 MIPS16 Jump and Branch Instructions Extensible Mnemonic Instruction Instruction JALR Jump and Link Register No JALRC Jump and Link Register Compact EAUX Jump and Link Exchange JRC Jump Register Compact No Table 12 19 MIPS16 Shift Instructions Extensible Mnemonic Instruction Instruction SRA Shift Right Arithmetic Yes tan Shift Right Arithmetic Variable Shift Left Logical SLLV Shift Left Logical Variable No SRL Shift Right Logical Yes SRLV Shift Right Logical Variable No 278 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Appendix A Revision History Table A 1 Revision History Revision Date Description 0 90 November 13 2000 First preliminary version Changes for this revision Added LWC2 and SWC2 to opcode map Table 11 1 on page 237 Updated TagLo CPO register format for new handling of LRU November 17 2000 bits Added ErrCtl CPO register Added more details to WS description in cache chapter Added description of how to test the cache arrays
137. GEI TGEIU TLTI TLTIU TEQI a TNEI a 2 10 BLTZAL BGEZAL BLTZALL BGEZALL a a a a 3 11 a a of vi a a vi SYNCI bits 23 21 1 The core will treat the entire row as a BC2 instruction However compiler and assembler support only exists for the first one Some compiler and assembler products may allow the user to add new instructions Table 11 7 COP2 Encoding of rt Field When rs BC2 rt bits 16 bits 17 0 1 0 BC2F BC2T 1 BC2FL BC2TL bits 23 21 WRPGPR MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 239 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 11 MIPS32 4KE Processor Core Instructions function bits 2 0 Table 11 9 COP0 Encoding of Function Field When rs CO 11 3 MIPS32 Instruction Set for the 4KE core 240 This section describes the MIPS32 instructions for the 4KE cores Table 11 10 lists the instructions in alphabetical order Instructions that have implementation dependent behavior are described afterwards The descriptions for other instructions exist in the architecture reference manual and are not duplicated here Table 11 10 Instruction Set MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Instruction Description Function ADD Integer Add Rd Rs Rt
138. II register if the exception is an interrupt Causejy 1 and Config3yg c 1 These are the conditions for a vectored EIC interrupt e The ESS field of the SRSCII register in any other case This is the condition for a non interrupt exception or a non vectored interrupt Similarly the rules for updating the fields in the SRSCtl register at the end of an exception or interrupt are as follows 64 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 4 5 Exception Vector Locations 1 No field in the SRSCII register is updated if any of the following conditions is true In this case step 2 is skipped A DERET is executed e An ERFT is executed with Statusgpy 1 2 SRSCtlpgg is copied to SRSCtlogs These rules have the effect of preserving the SRSCtl register in any case of a nested exception or one which occurs before the processor has been fully initialize Statusppy 1 Privileged software may switch the current shadow set by writing a new value into SRSCtlpss loading EPC with a target address and doing an ERET 4 5 Exception Vector Locations The Reset Soft Reset and NMI exceptions are always vectored to location 164 BFCO 0000 EJTAG Debug exceptions are vectored to location 164BFC0 0480 or to location 16 FF20 0200 if the ProbTrap bit is zero or one respectively in the EJTAG_Control_register Addresses for all other exceptio
139. In processors that implement the MIPS16 ASE a read of the EPC register via MFCO returns the following value in the destination GPR GPR rt lt ExceptionPCs4 4 ISAMode That is the upper 31 bits of the exception PC are combined with the lower bit of the ISAMode field and written to the GPR Similarly a write to the EPC register via MTCO takes the value from the GPR and distributes that value to the exception PC and the ISAMode field as follows ExceptionPC lt GPR rt 3 0 ISAMode 2 0 GPR rt That is the upper 31 bits of the GPR are written to the upper 31 bits of the exception PC and the lower bit of the exception PC is cleared The upper bit of the ISAMode field is cleared and the lower bit is loaded from the lower bit of the GPR Figure 5 19 EPC Register Format 31 0 EPC Table 5 24 EPC Register Field Description Fields Name Description Reset State EA Exception Program Counter RW Undefined Undefined MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions 5 2 19 Processor Identification CP0 Register 15 Select 0 The Processor Identification PRId register is a 32 bit read only register that contains information identifying the manufacturer manufacturer options processor identification and revision level of the processor Figure 5 20 PRId
140. Instruction Cache The instruction cache I cache is an optional on chip memory block of up to 64 KB The virtually indexed physically tagged cache allows the virtual to physical address translation to occur in parallel with the cache access rather than having to wait for the physical address translation The core supports instruction cache locking Cache locking allows critical code or data segments to be locked into the cache on a per line basis enabling the system programmer to maximize the efficiency of the system cache The cache locking function is always enabled on all instruction cache entries Entries can then be marked as locked or unlocked on a per entry basis using the CACHE instruction 7 4 Data Cache 158 The data cache D cache is an optional on chip memory block of up to 64 KB The virtually indexed physically tagged cache allows the virtual to physical address translation to occur in parallel with the cache access rather than having to wait for the physical address translation The core also supports a data cache locking mechanism identical to the instruction cache Critical data segments to be locked into the cache on a per line basis The locked contents can be updated on a store hit but cannot be selected for replacement on a miss The cache locking function is always enabled on all data cache entries Entries can then be marked as locked or unlocked on a per entry basis using the CACHE instruction MIPS3
141. LA Repgister Field Descriptions Fields Read Name Bits Description Write Reset State Reserved Must be written as zero returns zero on read 0 This field specifies the type of tracing that is supported by the processor as follows Encoding Meaning 00 PC tracing only VModes 01 PC and Load and store address tracing only 10 PC load and store address and load and store data 10 11 Reserved This field is preset to the value of PDO_ValidModes PDO AD bus width ADW 0 The PDC AD bus is 16 bits wide 0 1 The PDO AD bus is 32 bits wide Used to indicate the synchronization period The period in cycles between which the periodic synchronization information is to be sent is defined as shown in the table below when the trace buffer is either on chip or off chip as determined by the TCBCONTROLB Qc bit SyP On chip Off chip 000 2 27 001 2 28 010 24 2 011 25 210 100 26 2H 101 27 2E 110 25 27 111 EN 25 SyP 22 20 R W 100 This field defines the value on the PDI SyncPeriod signal Trace All Branches When set to one this field indicates that the core must trace either full or incremental PC values for all branches When set to zero only the unpredictable branches TB 19 are traced R W Undefined This field defines the value on the PDI TraceAllBranch signal 210 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00
142. MFCO EntryLol 0 PageMask TLBP gt MFCO Index 0 TLBR MTCO gt TLBWI EntryHi 1 TLBWR TLBP MTCO me Load store affected by new state EntryHiasip l TLBWI EntryLoO MICO gt TLBWR EntryLol TLBWI MTCO gt TLBWR Index 1 RDPGPR MTCO gt WRPGPR SRSCtlpss 1 Compare MTCO gt Instruction not seeing a Timer Interrupt update that 4 clears Timer Interrupt MTCO gt Instruction affected by change Ay orie 2 y 8 CPO register MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 29 Chapter 2 Pipeline 1 This is the minimum value Actual value is system dependent since it is a function of the sequential logic between the SI Timerlnt output and the external logic which feeds SI TimerlInt back into one of the S7 Int inputs or a function of the method for handling ST Timerlnt in an external interrupt controller 2 13 1 2 Instruction Hazards Instruction hazards are those created by the execution of one instruction and seen by the instruction fetch of another instruction Table 2 7 lists instruction hazards Table 2 7 Instruction Hazards Producer gt Consumer Hazard Spacing On Instructions TLBWR TLBWI gt Instruction fetch using new TLB entry TLB entry Instruction fetch seeing the new value including a change to ERL followed by an instruction fetch from the useg segment PENIS Instruction fetch seeing the new value Entr
143. MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Perform Cache Operation CACHE 31 26 25 21 20 16 15 0 CACHE base op offset 101111 6 5 5 16 Format CACHE op offset base MIPS32 Purpose To perform the cache operation specified by op Description The 16 bit offset is sign extended and added to the contents of the base register to form an effective address The effective address is used in one of the following ways based on the operation to be performed and the type of cache as described in the following table Table 11 11 Usage of Effective Address Operation Type of Requires an Cache Usage of Effective Address The effective address is translated by the MMU to a physical address The physical Bude Physical address is then used to address the cache Assuming that the total cache size in bytes is CS the associativity is A and the number of bytes per tag is BPT the following calculations give the fields of the address which specify the way and the index OffsetBit Log2 BPT IndexBit lt Log2 CS A WayBit lt IndexBit Ceiling Log2 A Way e Addrwaypit 1 IndexBit Index AddYingexpit 1 0ffsetBit For a direct mapped cache the Way calculation is ignored and the Index value fully specifies the cache tag This is shown symbolically in the figure below MIPS32 4KE Process
144. MIPS32 Purpose 254 To load a word from memory for an atomic read modify write Description rt lt memory basetoffset The LL and SC instructions provide the primitives to implement atomic read modify write RMW operations for synchronizable memory locations The contents of the 32 bit word at the memory location specified by the aligned effective address are fetched and written into GPR rt The 16 bit signed offset is added to the contents of GPR base to form an effective address This begins a RMW sequence on the current processor There can be only one active RMW sequence per processor When an LL is executed it starts an active RMW sequence replacing any other sequence that was active The RMW sequence is completed by a subsequent SC instruction that either completes the RMW sequence atomically and suc ceeds or does not and fails Executing LL on one processor does not cause an action that by itself causes an SC for the same block to fail on another processor An execution of LL does not have to be followed by execution of SC a program is free to abandon the RMW sequence without attempting a write Restrictions The addressed location must be synchronizable by all processors and I O devices sharing the location if it is not the result in UNPREDICTABLE Which storage is synchronizable is a function of both CPU and system implementa tions See the documentation of the SC instruction for the formal definition The effe
145. MS causes the controller to transition to the Exit IR state 9 3 2 13 Exit1 IR State This is a temporary controller state in which all registers retain their previous state If TMS is sampled LOW at the rising edge of TCK the controller transitions to the Pause IR state A HIGH on TMS causes the controller to transition to the Update IR state which terminates the scanning process The instruction cannot change while the TAP controller is in this state and the instruction register retains its previous state 9 3 2 14 Pause IR State The Pause IR state allows the controller to temporarily halt the shifting of data through the instruction register in the serial path between TDI and TDO If TMS is sampled LOW at the rising edge of TCK the controller remains in the Pause IR state A HIGH on TMS causes the controller to transition to the Exit2 IR state The instruction cannot change while the TAP controller is in this state 9 3 2 15 Exit2 IR State This is a temporary controller state in which the instruction register retains its previous state If TMS is sampled LOW at the rising edge of TCK then the controller transitions to the Shift_IR state to allow another serial shift of data A HIGH on TMS causes the controller to transition to the Update IR state which terminates the scanning process The instruction cannot change while the TAP controller is in this state 9 3 2 16 Update IR State The instruction shifted into the instruction register tak
146. Mis TECHNOLOGIES MIPS32 4KE Processor Cores Software User s Manual Document Number MD00103 Revision 02 00 November 8 2002 MIPS Technologies Inc 1225 Charleston Road Mountain View CA 94043 1353 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Copyright 2000 2002 MIPS Technologies Inc All rights reserved Unpublished rights if any reserved under the copyright laws of the United States of America and other countries This document contains information that is proprietary to MIPS Technologies Inc MIPS Technologies Any copying reproducing modifying or use of this information in whole or in part that is not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly prohibited At a minimum this information is protected under unfair competition and copyright laws Violations thereof may result in criminal penalties and fines Any document provided in source format i e in a modifiable form such as in FrameMaker or Microsoft Word format is subject to use and distribution restrictions that are independent of and supplemental to any and all confidentiality restrictions UNDER NO CIRCUMSTANCES MAY A DOCUMENT PROVIDED IN SOURCE FORMAT BE DISTRIBUTED TO A THIRD PARTY IN SOURCE FORMAT WITHOUT THE EXPRESS WRITTEN PERMISSION OF MIPS TECHNOLOGIES INC MIPS Technologies reserves the right to change the information contained in this document to improve function design
147. Mn Instruction Breakpoint Address Mask n 0x1110 n 0x100 IBASIDn Instruction Breakpoint ASID n 172 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 2 Hardware Breakpoints Table 9 6 Addresses for Instruction Breakpoint Registers Register Offset in drseg Mnemonic Register Name and Description 0x1118 n 0x100 IBCn Instruction Breakpoint Control n Note n is breakpoint number in range 0 to 3 or 0 to 1 depending on the implemented hardware An example of some of the registers JBAO is at offset 0x1100 and JBC72 is at offset 0x1318 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 173 Chapter 9 EJTAG Debug Support 174 9 2 8 1 Instruction Breakpoint Status IBS Register Compliance Level Implemented only if instruction breakpoints are implemented The Instruction Breakpoint Status BS register holds implementation and status information about the instruction breakpoints The ASID applies to all the instruction breakpoints IBS Register Format 31 30 29 28 27 24 23 4 3 0 Res ASID Res BCN Res BS sup Table 9 7 IBS Register Field Descriptions Fields Read Name Bit s Description Write Reset State Res 31 Must be written as zero returns zero on read R 0 Indicates that ASI
148. No MIPS 16 present 1 MIPS16 is implemented EP 1 EJTAG present This bit is always set to indicate that the core implements EJTAG FPU implemented This bit is always zero since the core FP 0 d A oes not contain a floating point unit 126 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions 5 2 23 Config2 Register CP0 Register 16 Select 2 The Config2 register is an adjunct to the Config register and is reserved to encode additional capabilities information Config2 is allocated for showing the configuration of level 2 3 caches These fields are reset to 0 because L2 L3 caches are not supported by the 4KE core All fields in the Config2 register are read only Figure 5 25 Config2 Register Format Select 2 31 30 0 wn OSE Table 5 29 Config1 Register Field Descriptions Select 1 Fields Description Reset State This bit is hardwired to 1 to indicate the presence of the M 31 R 1 Config3 register 0 30 0 These bits are reserved R 0 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 127 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers 5 2 24 Config3 Register CPO Register 16 Select 3 The Config3 register encodes additional capabilities All fields in the Config3 register are read
149. OO00 0000 ksegO 0x8000 0000 useg kuseg 0x0000 0000 Physical Address kseg3 OxEOO00 0000 kseg2 SCHU 0000 useg kuseg 0x4000 0000 reserved 0x2000 0000 kseg0 kseg1 0x0000 0000 Figure 3 11 FM Memory Map ERL 0 in the 4KEm and 4KEp Processor Cores MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 51 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 3 Memory Management Virtual Address Physical Address useg kuseg 0x0000 0000 kseg3 kseg3 OxEOO 0 0 000 OxEOO00 0000 keen kseg2 0xC000 0000 0xCOO0 0000 kseg1 0xA000 0000 reserved ksegO 0x8000 0000 useg kuseg kseg0 kseg1 0x0000 0000 Figure 3 12 FM Memory Map ERL 1 in the 4KEm and 4KEp Processor Cores 3 6 System Control Coprocessor The System Control Coprocessor CPO is implemented as an integral part of the 4KE processor cores and supports memory management address translation exception handling and other privileged operations Certain CPO registers are used to support memory management Refer to Chapter 5 CPO Registers on page 87 for more information on the CPO register set 52 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 4 Exceptions an
150. OOT option is used to boot into DebugMode see Chapter 9 EJTAG Debug Support for details MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 149 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 6 Hardware and Software Initialization Debug suy cleared to 0 on Reset SoftReset e Debug ipysep Cleared to 0 on Reset SoftReset Debugppgy sgp cleared to 0 on Reset SoftReset Debug sry cleared to 0 on Reset SoftReset Debugss cleared to 0 on Reset SoftReset 6 1 2 TLB Initialization 4KEc core only Each 4KEc TLB entry has a hidden state bit which is set by Reset SoftReset and is cleared when the TLB entry is written This bit disables matches and prevents TLB Shutdown conditions from being generated by the power up values in the TLB array when two or more TLB entries match on a single address This bit is not visible to software 6 1 3 Bus State Machines All pending bus transactions are aborted and the state machines in the bus interface unit are reset when a Reset or SoftReset exception is taken 6 1 4 Static Configuration Inputs All static configuration inputs defining the bus mode and cache size for example should only be changed during Reset 6 1 5 Fetch Address Upon Reset SoftReset unless the EJTAGBOOT option is used the fetch is directed to VA OXBFCO00000 PA Ox1FC00000 This address is in KSeg1 which is unmapped and uncached so that the TLB and c
151. P2 Interface The Instruction is presented on the instructions bus in E stage The coprocessor 2 can do a decode in the same cycle 2 The Instruction is validated from the core in M stage From this point the core will accept control and data signals back from coprocessor 2 All control and data signals from the coprocessor 2 is captured on input latches to the core 24 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 2 10 Interlock Handling 3 Ifall the expected control and data signals was presented to the core in the previous M stage the core will proceed executing the A stage If some return information is missing the A stage will not advance and cause a slip on all I E and M stage see Section 2 11 Slip Conditions on page 26 If this instruction involved sending data from the core to the coprocessor 2 then this data is send in A stage 4 The instruction completion is signaled to the coprocessor 2 in the W stage Potential data from the coprocessor is written in the register file Figure 2 21 on page 25 Show the timing relationship between the 4KE core and the coprocessor 2 for all coprocessor 2 instruction One Cycle One Cycle One Cycle One Cycle One Cycle COP2 inst gt E M A Ww Core internal Fetch Decode and Get ToData Capture e f Control amp operations instruc
152. PS Technologies Inc All rights reserved 5 2 CPO Register Descriptions 5 2 33 Debug Exception Program Counter Register CP0 Register 24 Select 0 The Debug Exception Program Counter DEPC register is a read write register that contains the address at which processing resumes after a debug exception or debug mode exception has been serviced For synchronous precise debug and debug mode exceptions the DEPC contains either The virtual address of the instruction that was the direct cause of the debug exception or The virtual address of the immediately preceding branch or jump instruction when the debug exception causing instruction is in a branch delay slot and the Debug Branch Delay DBD bit in the Debug register is set For asynchronous debug exceptions debug interrupt the DEPC contains the virtual address of the instruction where execution should resume after the debug handler code is executed In processors that implement the MIPS16 ASE a read of the DEPC register via MFCO returns the following value in the destination GPR GPR rt ec DebugExceptionPCsa4 ISAModeo That is the upper 31 bits of the debug exception PC are combined with the lower bit of the ISAMode field and written to the GPR Similarly a write to the DEPC register via MTCO takes the value from the GPR and distributes that value to the debug exception PC and the ISAMode field as follows DebugExceptionPC lt GPR rt 3 0 ISAMo
153. R 00 is always 00 to indicate the MIPS32 architecture Architecture revision level This field is always 001 to indicate MIPS32 Release 2 AR R 001 0 Release 1 1 Release2 2 7 Reserved MMU Type MT 1 Standard TLB 4KEc core R Preset 3 Fixed Mapping 4KEp 4KEm cores 0 2 4 7 Reserved 0 Must be written as zeros returns zeros on reads 0 0 Kseg0 coherency algorithm Refer to Table 5 27 for the R W 010 KO 2 0 field encoding Table 5 27 Cache Coherency Attributes C 2 0 Value Cache Coherency Attribute Cacheable noncoherent write through no write allocate Cacheable noncoherent write through write allocate 3 4 5 6 Cacheable noncoherent write back write allocate 2 7 Uncached Note These two values are required by the MIPS32 architecture In the 4KE processor core only values 0 1 2 and 3 are used For example values 4 5 and 6 are not used and are mapped to 3 The value 7 is not used and is mapped to 2 Note that these values do have meaning in other MIPS Technologies processor implementations Refer to the MIPS32 specification for more information MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions 5 2 22 Config Register CP0 Register 16 Select 1 The Config register is an adjunct to the Config register and encodes addition
154. RR rie ear tui teret a 43 Table 3 7 TEB D ta Entry Fields rt Gee rr ptem e RI pe e ee mehrere e rb P iuc 44 Table 3 8 TEB Instructions Hee ote eter e ei Ae OR Ia ARE SE oh heii LAG aaa 49 Table 3 9 Cache Coher ncy Attributes EE 50 Table 3 10 Cacheability of Segments with Block Address Translation eene 50 Table 4 1 Priority of EXCeptions eer ttd te eet P ee Rn e e idee eb pee teet e ee ES 54 Table 4 2 Interrupt Modes ete nee hte te RA GE RIP Bash has RU alg dna 56 Table 4 3 Relative Interrupt Priority for Vectored Interrupt Mode essere enne nennen 59 Table 4 4 Exception Vector Offsets for Vectored Interrupts eese nennen trennen ene 63 Table 4 5 Exception Vector Base Addresses 3 eee debt e pee e S Ite eH en recie peer erbe e 65 Table 4 6 Exception Vector Offset 66 Table 4 7 Exception Vectors s bein o rmt bb e Re rti eet te nette nts 66 Table 4 8 Value Stored in EPC ErrorEPC or DEPC on an Exception eese nennen enne 67 Table 4 9 Debug Exception Vector Addresses 4 cte detegere ree e C e EE EH gre e pete tede SS DURCH 69 Table 4 10 Register States an Interrupt Exception esses eterne nene en neenren nennen neret nete ener tne tne 73 Table 4 11 Register States on a Watch Exception 00 0 cece ceseecceeeeeeceseeeeecaeeeaecaeesaecsaesaecneceseceecsesseeeaeseeseaeseeecaaeeaesaes 74 Table 4 12 CPO Register States on an Address Exception Error 75 Table
155. Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Table 5 9 Values for the Mask and MaskX Fields of the PageMask Register Page Size SE e a Ac CS EE EE E E EE 16 MByte 1 1 64 MByte oe 8 elit eae type ya ee oe ae a ee a 1 256 MByte 1 1 1 1 1 27 1 1 27 1 1757 1 14 1 I 1 1 PageMask 11 PaskMaskmaskx exists only on implementations of Release 2 of the architecture and are treated as if they had the value 2 11 if IK pages are not enabled Config3sp 0 or PageGraingsp 0 It is implementation dependent how many of the encodings described in Table 5 9 are implemented All processors must implement the 4KB page size If a particular page size encoding is not implemented by a processor a read of the PageMask register must return zeros in all bits that correspond to encodings that are not implemented thereby poten tially returning a value different than that written by software Software may determine which page sizes are supported by writing all ones to the PageMask register then reading the value back If a pair of bits reads back as ones the processor implements that page size The operation of the proces sor is UNDEFINED if software loads the Mask field with a value other than one of those listed in Table 5 9 even if the hardware returns a different value on read Hardware may depend on this r
156. TAG debug features are unused by the probe 9 3 2 Test Access Port Operation The TAP controller is controlled by the Test Clock TCK and Test Mode Select TMS inputs These two inputs determine whether an the Instruction register scan or data register scan is performed The TAP consists of a small controller driven by the TCK input which responds to the TMS input as shown in the state diagram in Figure 9 1 on page 189 The TAP uses both clock edges of TCK TMS and TDI are sampled on the rising edge of TCK while TDO changes on the falling edge of TCK At power up the TAP is forced into the Test Logic Reset by low value on TRST N The TAP instruction register is thereby reset to IDCODE No other parts of the EJTAG hardware are reset through the Test Logic Reset state When test access is required a protocol is applied via the TMS and TCK inputs causing the TAP to exit the Test Logic Reset state and move through the appropriate states From the Run Test Idle state an Instruction register scan or a data register scan can be issued to transition the TAP through the appropriate states shown in Figure 9 1 on page 189 The states of the data and instruction register scan blocks are mirror images of each other adding symmetry to the protocol sequences The first action that occurs when either block is entered is a capture operation For the data registers the Capture DR state is used to capture or parallel load the data into the selected se
157. TCBCONTROLA Register Field Descriptions Continued Read Description Write Reset State When tracing is turned on this signal specifies what information is to be traced by the core Mode Trace Mode 000 Trace PC 001 Trace PC and load address 010 Trace PC and store address 011 Trace PC and both load store addresses 100 Currentl impl ted urrently un 1mpiemente R W Undefined 101 Trace PC and load address and data 110 Trace PC and store address and data 111 Trace PC and both load store address and data The VModes field determines which of these encodings are supported by the processor The operation of the processor is UNPREDICTABLE if Mode is set to a value which is not supported by the processor This field defines the value on the PDI TraceMode signal This field defines the value on the PDI TraceOn signal This is the global trace enable switch to the core When zero tracing from the core is always disabled unless enabled by core internal software override of the PDI input pins When set to one tracing is enabled whenever the other enabling functions are also true 9 9 2 TCBCONTROLB Register The TCB includes a second control register TCBCONTROLB 0x11 This register generally controls what to do with the trace information received The format of the TCBCONTROLB register is shown below and the fields are described in Table 9 30 TCBCONTROLB Register Format 31 30 26 25 21 20 19
158. TROLBgygg eme ee nen een nennen eene 209 Table 9 29 TCBCONTROLA Register Field Descriptions seeesseeseseeeeeeeee eene nennen netten ennene ene 210 Table 9 30 TCBCONTROLB Register Field Descriptions ssesessseeeesseeeeeee eene nennen eret rennen rene 212 Table 9 31 Clock Ratio encoding of the CR field esses nennen nennen ener 216 Table 9 32 TCBDATA Register Field Descriptions tre nnne innen S 217 Table 9 33 TCBCONFIG Register Field Descriptions eese nennen nennen entere nete enne trennen 217 Table 9 34 TCBTW Register Field Descriptions essent nretene nee pe s terere trennen rennen 218 Table 9 35 TCBRDP Register Field Descriptions essere nennen nennen nennen tente teneret enne trennen 219 Table 9 36 TCBWRP Register Field Descriptions nennen nennen nenne tenerent RER 219 Table 9 37 TCBSTP Register Field Descriptions sesssseeseeeeseeeeee ener ener tente treten rennen rennen 220 Table 9 38 TCBTRIGx Register Field Descriptions sese ener enne trennen enne 220 Table 10 1 Byte Access Within a Word 233 Table LEI Encoding of the Opcode Field uin eri cre reete m ER RU at ee rE eee eei entes 237 Table 11 2 Special Opcode encoding of Function Feld 238 Table 11 3 Special2 Opcode Encoding of Function Field AAA 238 Table 11 4 Special3 Opcode Encoding of Function Field AAA 238 Table 11 5 ReeImm Encodimg of EE 239
159. Table 11 6 COP2 Encoding of rs Peld eene nennen nennen nennen teneret RERE en rennen 239 Table 11 7 COP2 Encoding of rt Field When ro BC 239 Table 11 8 COPO Encoding of rs Peld eene nennen nennen tnnt terere terere treten enne 239 Table 11 9 COPO Encoding of Function Field When rs 240 Table 11 10 zInstruction Set 25 ere ette eG he ien ener Nees dp etai ene 240 Table 11 11 Usage of Effective Address ette eer temi m e eet re n oot oe et 247 Table 11 12 Encoding of Bits 17 16 of CACHE Instruction nennen nennen nennen ner en nennt ene 248 Table 11 13 Encoding of Bits 20 18 of the CACHE Instruction ErrCtl WST SPR Cleared 249 Table 11 14 Encoding of Bits 20 18 of the CACHE Instruction ErrCtl WST Set ErrCtl SPR Cleared 252 Table 11 15 Encoding of Bits 20 18 of the CACHE Instruction ErrCtl SPR Set 252 Table 11 16 Values of the hint Field for the PREF Instruction o eee ce ceseceeceseeeeceseeeeeeseeseeeseseeesaeeeaecaeesaessaeaeenees 257 Table 12 1 Symbols Used in the Instruction Encoding Tables AAA 273 Table 12 2 MIPS16 Encoding of the Opcode Feld 274 Table 12 3 MIPS16 JAL X Encoding of the x bel 274 Table 12 4 MIPS16 SHIFT Encoding of the f Field sese net rere rennen 274 Table 12 5 MIPS16 RRI A Encoding of the f Field oo eee seen 274 Table 12 6 MIPS16 I8 Encoding of the funct Feld 274 Table 12 7 MIPS16 RRR Encoding of the f F
160. Table 5 35 TraceControl Register Field Descriptions Continued Read Description Write Reset State These three bits control the trace mode function Mode Trace Mode 000 Trace PC 001 Trace PC and load address Trace PC and store address 011 Trace PC and both load store addresses Trace PC and load data 101 Trace PC and load address and data Undefined 110 Trace PC and store address and data 111 Trace PC and both load store address and data The TraceControl2 y4jawoges field determines which of these encodings are supported by the processor The operation of the processor is UNPREDICTABLE if this field is set to a value which is not supported by the processor This is the master trace enable switch in software control When zero tracing is always disabled When set to one tracing is enabled whenever the other enabling functions are also true 138 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions 5 2 30 Trace Control2 Register CP0 Register 23 Select 2 The TraceControl2 register provides additional control and status information Note that some fields in the TraceControl2 register are read only but have a reset state of Undefined This is because these values are loaded from the Trace Control Block TCB see Section 9 9 Trace Control Block TCB Registers hard
161. UECSS controller 114 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions 5 2 16 SRSMap Register CPO Register 12 Select 3 The SRSMap register contains 8 4 bit fields that provide the mapping from an vector number to the shadow set number to use when servicing such an interrupt The values from this register are not used for a non interrupt exception or a non vectored interrupt Causeyy 0 or IntCtlys 0 In such cases the shadow set number comes from SRSCtlggs If SRSCtlyg is zero the results of a software read or write of this register are UNPREDICTABLE The operation of the processor is UNDEFINED if a value is written to any field in this register that is greater than the value of SRSCtlygs The SRSMap register contains the shadow register set numbers for vector numbers 7 0 The same shadow set number can be established for multiple interrupt vectors creating a many to one mapping from a vector to a single shadow register set number Figure 5 17 shows the format of the SRSMap register Table 5 21 describes the SRSMap register fields Figure 5 17 SRSMap Register Format 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 SSV7 SSV6 SSV5 SSV4 SSV3 SSV2 SSV1 SSVO Table 5 21 SRSMap Register Field Descriptions Fields Read Description Reset State Shadow register set number
162. WREna Enables access via the RDHWR instruction to selected hardware registers in non privileged mode BadVAddr Reports the address for the most recent address related exception EntrvHi High order portion of the TLB entry 4KEc core This register y is reserved in the 4KEp and 4KEm cores Compare Timer interrupt control Status IntCtl Processor status and control interrupt control and shadow set SRSCtl i control SRSMap Cause Cause of last exception EPC Program counter at last exception PRId P ificati TO d EBase rocessor identification and revision exception base address MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 1 CPO Register Summary Table 5 1 CPO Registers Continued Register Number Register Name Function Config Configl Config2 Config3 LLAddr Configuration registers Load linked address WatchLo Low order watchpoint address WatchHi High order watchpoint address Reserved TraceControl TraceControl2 UserTraceData TraceBPC2 Reserved Reserved Debug control exception status and EJTAG trace control Reserved ErrCtl TagLo DataLo Software test enable of way select and Data RAM arrays for I Cache and D Cache Low order portion of cache tag interface Reserved Reserved ErrorEPC Program counter at last
163. Watch is masked if EXL 1 Comments EnHi and Context are set only for TLB Invalid Modified amp Refill EntryHi VPN2 ASID Context VPN2 exceptions BadVA is set only for Set Cause EXCCode CE TLB Invalid Modified Refill and BadVA VA VCED I exceptions Note not set if it is a Bus Error Check if exception within another exception EPC lt PC 4 EPC PC Cause BD lt 1 Cause BD 0 Processor forced to Kernel Mode amp interrupt disabled 0 normal 1 bootstrap PC lt 0x8000_0000 180 PC OxBFCO 0200 180 unmapped cached unmapped uncached T To General Exception Servicing Guidelines Figure 4 3 General Exception Handler HW 82 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 4 9 Exception Handling and Servicing Flowcharts Comments Unmapped vector so TLBMod TLBInv or TLB Refill exceptions not possible EXL 1 so Watch Interrupt exceptions disabled OS System to avoid all other exceptions Only Reset Soft Reset NMI exceptions MFCO Context EPC Status Cause A possible MTCO Set Status bits Optional only to enable Interrupts while keeping UM lt 0 EXL lt 0 Kernel Mode IE 1 Check Cause value amp Jump to After EXL 0 all i I K appropriate Service Code ter ual excppiians allowed
164. Wired register Thus TLB entries below the Wired value cannot be replaced by a TLBWR allowing important mappings to be preserved In order to reduce the possibility for a livelock situation the Random register includes a 10 bit LFSR that introduces a pseudo random perturbation into the decrement The 4KEc core implements a TLB write compare mechanism to ensure that multiple TLB matches do not occur On the TLB write operation the VPN2 field to be written is compared with all other entries in the TLB If a match occurs the 4KEc core takes a machine check exception sets the TS bit in the CPO Status register and aborts the write operation For further details on exceptions please refer to Chapter 4 Exceptions and Interrupts on page 53 There is a hidden bit in each TLB entry that is cleared on a ColdReset This bit is set once the TLB entry is written and is included in the match detection Therefore uninitialized TLB entries will not cause a TLB shutdown Note This hidden initialization bit leaves the entire JTLB invalid after a ColdReset eliminating the need to flush the TLB But to be compatible with other MIPS processors it is recommended that software initialize all TLB entries with unique tag values and V bits cleared before the first access to a mapped location MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 47 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 3 Memory Management
165. a pending processor access The Fastdata operation must use a valid Fastdata area address in dmseg OxFF20 0000 to OxFF20 000F Table 9 25 shows the values of the PrAcc and SPrAcc bits and the results of a Fastdata access Table 9 25 Operation of the FASTDATA access PrAccin Address the LSB LSB Probe Match Control SPrAcc Action in the PrAcc shifted Data shifted Operation check Register shifted in Data Register changes to out out Fails x X none unchanged 0 invalid 1 1 none unchanged 1 invalid Download using valid FASTDATA Passes 1 0 write data 0 SPrAcc 1 previous data 0 D none unchanged 0 invalid MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 5 TAP Processor Accesses Table 9 25 Operation of the FASTDATA access Continued PrAccin Address the LSB LSB Probe Match Control SPrAcc Action in the PrAcc shifted Data shifted Operation check Register shifted in Data Register changes to out out Fails X X none unchanged 0 invalid Upload 1 1 none unchanged 1 invalid using J FASTDATA Passes 1 0 read data 0 SPrAcc 1 valid data 0 X none unchanged 0 invalid There is no restriction on the contents of the Data register It is expected that the transfer size is negotiated between the download upload transfer code and the probe software Note th
166. a read write register In normal use however the Compare register is write only Writing a value to the Compare register as a side effect clears the timer interrupt Figure 5 13 Compare Register Format Compare Table 5 16 Compare Register Field Description Read Description Write Reset State Compare 31 0 EN 1 0 Interval count compare Interval count compare value Interval count compare value RW Undefined 104 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions 5 2 13 Status Register CPO Register 12 Select 0 The Status register is a read write register that contains the operating mode interrupt enabling and the diagnostic states of the processor Fields of this register combine to create operating modes for the processor Refer to NEED CROSSREF gt gt for a discussion of operating modes and Section NEED CROSSREF gt gt for a discussion of interrupt modes Interrupt Enable Interrupts are enabled when all of the following conditions are true e Ez 1 e EXL 0 ERL 0 DM 0 If these conditions are met then the settings of the IM and IE bits enable the interrupts Operating Modes If the DM bit in the Debug register is 1 then the processor is in debug mode otherwise the processor is in either kernel or user mode The following CPU Status register bit sett
167. ability of Segments with Block Address Translation Virtual Address Segment Range Cacheability E SN 0x0000_0000 Controlled by the KU field bits 27 25 of the Config register Refer to 8 8 0x7FFF_FFFF Table 3 9 for the encoding kseg0 0x8000_0000 Controlled by the KO field bits 2 0 of the Config register See Table Ox9FFF FFFF 3 0 for the encoding 0xA000 0000 ksegl Always uncacheable OxBFFF FFFF liess OxCO00 0000 Controlled by the K23 field bits 30 28 of the Config register Refer to 8 OxDFFF FFFF Table 3 9 for the encoding ten OxE000_0000 Controlled by K23 field bits 30 28 of the Config register Refer to 8 OxFFFF FFFF Table 3 9 for the encoding The FM performs a simple translation to map from virtual addresses to physical addresses This mapping is shown in Figure 3 11 on page 51 When ERL 1 useg and kuseg become unmapped and uncached The ERL behavior is the same as if there was a TLB The ERL mapping is shown in Figure 3 12 on page 52 50 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 3 5 Fixed Mapping MMU 4KEm amp 4KEp Cores The ERL bit is usually never asserted by software It is asserted by hardware after a Reset SoftReset or NMI See Section 4 8 Exceptions on page 69 for further information on exceptions Virtual Address kseg3 OxEOO00 0000 kseg2 0xCOO0 0000 kseg1 0xA
168. aceBPC Register Field Descriptions seseseeeseeeseeeeee eene nennen nennen tnter enne treten 142 Table 5 39 DEPC Register Formats enne etre en nenne EE AN O EE tet tene oeae EE rennen 143 Table 5 40 ErrCtl Register Field Descriptions eessesssseeeeeeeeeeeeee e nennen nennen tentent terere tereti treten enne 144 Table 5 41 TagLo Register Field Descriptions eese nne nennen ene neetn nenne enne tre enne treten enne 145 Table 5 42 DataLo Register Field Description sees nennen nennen nennen terere vekse Pepeye posip 146 Table 5 43 ErrorEPC Register Field Descppon nennen nennen nennen nete tnter innen rennen rennen 147 Table 5 44 DeSave Register Field Description eet eter ete Ee Pope tee ere ie eee oe ee ti i need 148 Table 7 1 Instruction and Data Cache Attributes sess nennen trennen net eere ene 153 Table 7 2 Instruction and Data Cache Sizes sese nentn retener enne treten enne 154 Table 7 3 LRU and Dirty Width in Way Select Array sseseeeeeseeeeeeeee eren nenne enne treten ene 155 Table 7 4 Potential Virtual Aliasing Bats eer ctt rect eit ee e bereit he geo eee 158 Table 7 5 Way Selection Encoding 4 Ways sessesessesseseeeeseeeee enne eene nennen nennen nete nenne tereti tne enne trenes enne 159 Table 7 6 Way Selection Encoding 3 Ways eei tcrtio i pause ten er eee eo dee roce rep e pee 159 Table 7 7 Way Selection Enc
169. ache line written to the data cache then reading out the required word Figure 2 5 on page 15 shows a timing diagram of a data cache miss MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 2 4 Multiply Divide Operations RegR ALUI D Cache l i l i D TLB l l i B ASel Bus DC Bypass Align RegW Contains all of the time that address and data are utilizing the bus Figure 2 5 Load Store Cache Miss Timing 2 4 Multiply Divide Operations The 4KE core implement the standard MIPS IITM multiply and divide instructions Additionally several new instructions were standardized in the MIPS32 architecture for enhanced performance The targeted multiply instruction MUL specifies that multiply results be placed in the general purpose register file instead of the HI LO register pair By avoiding the explicit MFLO instruction required when using the LO register and by supporting multiple destination registers the throughput of multiply intensive operations is increased Four instructions multiply add MADD multiply add unsigned MADDU multiply subtract MSUB and multiply subtract unsigned MSUBU are used to perform the multiply accumulate and multiply subtract operations The MADD MADDU instruction multiplies two numbers and then adds the product to the current contents of the HI and LO register
170. aches do not require hardware initialization 6 2 Software Initialized Processor State Software is required to initialize the following parts of the device 6 2 1 Register File The register file powers up in an unknown state with the exception of rO which is always 0 Initializing the rest of the register file is not required for proper operation Good code will generally not read a register before writing to it but the boot code can initialize the register file for added safety 6 2 2 TLB 4KEc Core Only Because of the hidden bit indicating initialization the 4KEc core does not require TLB initialization upon ColdReset This is an implementation specific feature of the 4KEc core and cannot be relied upon if writing generic code for MIPS32 64 processors When initializing the TLB care must be taken to avoid creating a TLB Shutdown condition where two TLB entries could match on a single address Unique virtual addresses should be written to each TLB entry to avoid this 150 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 6 2 Software Initialized Processor State 6 2 3 Caches The cache tag and data arrays power up to an unknown state and are not affected by reset Every tag in the cache arrays should be initialized to an invalid state using the CACHE instruction typically the Index Invalidate function This can be a long process especia
171. acts as the interface to the cache data array and is intended for diagnostic operations only The Index Load Tag operation of the CACHE instruction reads the corresponding data values into the DataLo register If the WST bit in the ErrCtl register is set then the contents of DataLo can be written to the cache data array by doing an Index Store Data CACHE instruction Note that the 4KE core does not implement the DataHi register Figure 5 38 DataLo Register Format 31 0 DATA Table 5 42 DataLo Register Field Description Fields Read W Reset Description rite State DATA 31 0 Low order data read from the cache data array Undefined 146 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions 5 2 37 ErrorEPC CP0 Register 30 Select 0 The ErrorEPC register is a read write register similar to the EPC register except that ErrorEPC is used on error exceptions AII bits of the ErrorEPC register are significant and must be writable It is also used to store the program counter on Reset Soft Reset and nonmaskable interrupt NMI exceptions The ErrorEPC register contains the virtual address at which instruction processing can resume after servicing an error This address can be The virtual address of the instruction that caused the exception The virtual address of the immediately preceding branch or j
172. ads or debug software should alternatively avoid setting data breakpoints with data value compares on such I O devices Debug software is responsible for disabling breakpoints when returning to the instruction otherwise the debug data break exception will reoccur 9 2 7 Breakpoint used as TriggerPoint Both instruction and data hardware breakpoints can be setup by software so a matching breakpoint does not generate a debug exception but only an indication through the BS n bit The TE bit in the JBCn or DBCn register controls if an instruction or data breakpoint is used as a so called triggerpoint The triggerpoints are like breakpoints only compared for instructions executed in non debug mode The BS n bit in the BS or DBS register is set when the respective IB match or DB match bit is true The triggerpoint feature can be used to start and stop tracing See Section 9 10 EJTAG Trace Enabling for details 9 2 8 Instruction Breakpoint Registers The registers for instruction breakpoints are described below These registers have implementation information and are used to set up the instruction breakpoints All registers are in drseg and the addresses are shown in Table 9 6 Table 9 6 Addresses for Instruction Breakpoint Registers Register Offset in drseg Mnemonic Register Name and Description 0x1000 IBS Instruction Breakpoint Status 0x1100 n 0x100 IBAn Instruction Breakpoint Address n 0x1108 n 0x100 IB
173. age 8 The Mult operation completes and is written to the HI LO registers pair the Wy stage while the Sub instruction write to the register file in the W stage 2 5 1 32x16 Multiply 4KEc amp 4KEm Cores The 32x16 multiply operation begins in the last phase of the E stage which is shared between the integer and MDU pipelines In the latter phase of the E stage the rs and rt operands arrive and the booth recoding function occurs at this time The multiply calculation requires one clock and occurs in the Mur stage In the Ampu stage the carry propagate add CPA function occurs and the operation is completed The result is ready to be read from the HI LO registers in the Wun stage Figure 2 7 shows a diagram of a 32x16 multiply operation Clock 1 2 3 4 E Muu gt Amu Kg Wu gt Booth Array CPA Res Rdy Figure 2 7 MDU Pipeline Flow During a 32x16 Multiply Operation 2 5 2 32x32 Multiply 4KEc amp 4KEm Cores The 32x32 multiply operation begins in the last phase of the E stage which is shared between the integer and MDU pipelines In the latter phase of the E stage the rs and rt operands arrive and the booth recoding function occurs at this time The multiply calculation requires two clocks and occurs in the Mypy stage In the Ampu stage the CPA function occurs and the operation is completed Figure 2 8 shows a diagram of a 32x32 multiply operation Clock 1 2 3 4 5 E kl Muu Manu Am
174. akpoints can also be set based on the value of the load store operation Finally masks can be applied to both the virtual address and the load store value Data breakpoints compare the transaction type TYPE which may be load or store the virtual address of the transaction ADDR the ASID accessed bytes B YTELANE and data value DATA with the registers for each data breakpoint including masking or qualification on the transaction properties When a data breakpoint matches a debug exception and or a trigger is generated and an internal bit in the data breakpoint registers is set to indicate that the match occurred The match is precise in that the debug exception or trigger occurs on the instruction that caused the breakpoint to match 9 2 3 Instruction Breakpoint Registers Overview The register with implementation indication and status for instruction breakpoints in general is shown in Table 9 2 Table 9 2 Overview of Status Register for Instruction Breakpoints Register Mnemonic Register Name and Description IBS Instruction Breakpoint Status 168 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 2 Hardware Breakpoints The four instruction breakpoints are numbered 0 to 3 for registers and breakpoints and the number is indicated by n The registers for each breakpoint are shown in Table 9 3 Table 9 3 Overview of Register
175. al information about capabilities present on the core All fields in the Config register are read only The instruction and data cache configuration parameters include encodings for the number of sets per way the line size and the associativity The total cache size for a cache is therefore Associativity Line Size Sets Per Way If the line size is zero there is no cache implemented Figure 5 24 Config Register Format Select 1 31 30 2524 2221 19 18 16 15 1312 109 76 5 4 3 2 10 M MMU Size IS IL IA DS DL DA C2 MD PC WR CA EP FP Table 5 28 Config Register Field Descriptions Select 1 Fields Description Reset State This bit is hardwired to 1 to indicate the presence of the Config register This field contains the number of entries in the TLB minus one The field is read as 15 decimal in the 4KEc core The P field is read as 0 decimal in the 4KEp and 4KEm cores fetch since no TLB is present MMU Size This field contains the number of instruction cache sets per way Five options are available in the 4KE core All others values are reserved 0x0 64 0x1 128 0x2 256 0x3 512 0x4 1024 0x5 0x7 Reserved This field contains the instruction cache line size If an instruction cache is present it must contain a fixed line size of 16 bytes Preset 0x0 No Icache present 0x3 16 bytes 0x1 0x2 0x4 0x7 Reserved This field contains the level of instruction cache a
176. andling of Fifo overflow in the TCB The TCB also holds a fifo used to buffer the TW s which are sent off chip through the Trace Probe The data width of the probe can be either 4 8 or 16 pins and the speed of these data pins can be from 16 times the core clock to 1 4 of the core clock the trace probe clock always runs at a double data rate multiple to the core clock See Section 9 12 3 1 Probe width and Clock ratio settings for a description of probe width and clock ratio options The combination between the probe width 4 8 or 16 and the data speed allows for data rates through the trace probe from 256 bits per core clock cycle down to only 1 bit per core clock cycle The high extreme is not likely to be supported in any implementation but the low one might be The data rate is an important figure when the likelihood of a TCB fifo overflow is considered The TCB will at maximum produce one full 64 bit TW per core clock cycle This is true for any selection of trace mode in TraceControlyopg or TCBCONTROLAwopg The PDtrace module will guarantee the limited amount of data If the TCB data rate cannot be matched by the off chip probe width and data speed then the TCB fifo can possibly overflow There is only one way to handle this 1 Prevent the overflow by asserting a stall signal back to the core PDI_StallSending This will in turn stall the core pipeline There is no way to guarantee that this back stall from the TCB is never asserted u
177. apability operating mode selection kernel vs user mode and the enabling disabling of interrupts Configuration information such as cache size set associativity and presence of build time options are available by accessing the CPO registers Refer to Chapter 5 CPO Registers on page 87 for more information on the CPO registers Refer to Chapter 9 EJTAG Debug Support on page 165 for more information on EJTAG debug registers 1 2 1 4 Memory Management Unit MMU The 4KE core contains an MMU that interfaces between the execution unit and the cache controller shown in Figure 1 2 on page 7 Although the 4KEc core implements a 32 bit architecture the Memory Management Unit MMU is modeled after the MMU found in the 64 bit R4000 family as defined by the MIPS32 architecture The 4KEc core implements its MMU based on a Translation Lookaside Buffer TLB The TLB consists of three translation buffers a 16 dual entry fully associative Joint TLB JTLB a 4 entry fully associative Instruction TLB ITLB and a 4 entry fully associative data TLB DTLB The ITLB and DTLB also referred to as the micro TLBs are managed by the hardware and are not software visible The micro TLBs contain subsets of the JTLB When translating addresses the corresponding micro TLB I or D is accessed first If there is not a matching entry the JTLB is used to translate the address and refill the micro TLB If the entry is not found in the JTLB then an exceptio
178. at the most efficient transfer size is a 32 bit word The Rocc bit of the Control register is not used for the FASTDATA operation 9 5 TAP Processor Accesses The TAP modules support handling of fetches loads and stores from the CPU through the dmseg segment whereby the TAP module can operate like a s ave unit connected to the on chip bus The core can then execute code taken from the EJTAG Probe and it can access data via a load or store which is located on the EJTAG Probe This occurs in a serial way through the EJTAG interface the core can thus execute instructions e g debug monitor code without occupying the memory Accessing the dmseg segment EJTAG memory can only occur when the processor accesses an address in the range from OxFF20 0000 to OXFF2F FFFF the ProbEn bit is set and the processor is in debug mode DM 1 In addition the LSNM bit in the CPO Debug register controls transactions to from the dmseg When a debug exception is taken while the ProbTrap bit is set the processor will start fetching instructions from address OxFF20 0200 A pending processor access can only finish if the probe writes 0 to PrAcc or by a soft or hard reset 9 6 Fetch Load and Store from to the EJTAG Probe through dmseg 1 The internal hardware latches the requested address into the PA Address register in case of the Debug exception OxFF20 0200 2 The internal hardware sets the following bits in the EJTAG Control register PrAcc 1 sele
179. ata ScratchPad is present 1 Data ScratchPad is present This bit indicates that CorExtend User Defined Instructions have been implemented UDI R Preset 0 No User Defined Instructions are implemented 1 User Defined Instructions are implemented Indicates whether SimpleBE bus mode is enabled Set via SI SimpleBE 0 input pin SB R Externally Set 0 No reserved byte enables on EC interface 1 Only simple byte enables allowed on EC interface This bit indicates the type of Multiply Divide Unit present MDU 0 Fast high performance MDU 4KEc and 4KEm cores R Preset 1 Iterative area efficient MDU 4KEp cores MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 123 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers 124 Figure 5 23 Config Register Field Descriptions Continued Fields Read W Name Description rite Reset State This bit indicates whether merging is enabled in the 32 byte collapsing write buffer Set via SI MergeMode 1 0 input pins MM R Externally Set 00 2 No Merging 10 Merging allowed x1 Reserved Burst order Set via EB_SBlock input pin BM R Externally Set 0 Sequential 1 SubBlock Indicates the endian mode in which the processor is running Set via SI Endian input pin BE R Externally Set 0 Little endian 1 Big endian AT Architecture type implemented by the processor This field
180. ata access a TLB refill exception occurs when no TLB entry matches a reference to a mapped address space and the EXL bit is 0 in the Status register Note that this is distinct from the case in which an entry matches but has the valid bit off In that case a TLB Invalid exception occurs Cause Register ExcCode Value TLBL Reference was a load or an instruction fetch TLBS Reference was a store Additional State Saved Table 4 13 CPO Register States on a TLB Refill Exception Register State Value BadVAddr failing address The BadVPN2 field contains V 3 15 of the failing Context address The VPN field contains VA3 15 of the failing address EntryHi the ASID field contains the ASID of the reference that missed EntryLoO UNPREDICTABLE EntryLol UNPREDICTABLE Entry Vector Used TLB refill vector offset 0x000 if Statusgxr 0 at the time of exception general exception vector offset 0x 180 if Statusgy 1 at the time of exception MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 75 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 4 Exceptions and Interrupts 76 4 8 12 TLB Invalid Exception Instruction Fetch or Data Access 4KEc core only During an instruction fetch or data access a TLB invalid exception occurs in one of the following cases No TLB entry matches a reference to a mapped address space and the EXL bit is 1 in
181. ay slot Undefined 0 Not in delay slot 1 In delay slot Indicates that the processor is operating in debug mode 0 Processor is operating in non debug mode 1 Processor is operating in debug mode Indicates whether the dseg memory segment is present NoDCR 29 0 dseg is present R 0 1 No dseg present MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 133 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers 134 Table 5 34 Debug Register Field Descriptions Continued CountDM Read Description Write Reset State Controls access of load store between dseg and main memory 0 Load stores in dseg address range goes to dseg R W 0 1 Load stores in dseg address range goes to main memory Undefined Undefined Indicates that the processor was in any kind of low power mode when a debug exception occurred 0 Processor not in low power mode when debug exception occurred 1 Processor in low power mode when debug exception occurred Indicates that the internal system bus clock was stopped when the debug exception occurred 0 Internal system bus clock stopped 1 Internal system bus clock running IBusEP MCheckP CacheEP DBusEP Indicates that an imprecise Cache Error is pending Cache Errors cannot be taken by the 4KE cores so this bit will always read as 0 R WI of IBusEP for imprecise bus errors on an instruction fet
182. been added in such a way that they are backward compatible with existing MIPS processors 2 13 1 Types of Hazards With one exception all hazards were eliminated in Release 1 of the Architecture for unprivileged software The exception occurs when unprivileged software writes a new instruction sequence and then wishes to jump to it Such an operation remained a hazard and is addressed by the capabilities of Release 2 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 2 13 Hazards In privileged software there are two different types of hazards execution hazards and instruction hazards Both are defined below 2 13 1 1 Execution Hazards Execution hazards are those created by the execution of one instruction and seen by the execution of another instruction Table 2 6 lists execution hazards Table 2 6 Execution Hazards Producer gt Consumer Hazard On Spacing Instructions TLBP TLBR TLB entry 0 TLBWR TLBWI gt Load store using new TLB entry TLB entry 0 WatchHi MTCO gt Load store affected by new state WatchLo 0 LL gt MFCO LLAddr 1 MTCO ee instruction execution depends on the new value of Statuscy 1 tatuscy EPC MTCO gt ERET DEPC 1 ErrorEPC MTCO gt ERET Status 0 MTCO EI DI gt Interrupted Instruction Statusyp 1 MTCO gt Interrupted Instruction Cause 3 EntryHi EntryLoO TLBR gt
183. before it is guaranteed that the indication is cleared in the CPU clock domain also This bit controls the EI PerRst signal on the core Processor Access Read and Write This bit indicates if the pending processor access is for a PRnW read or write transaction and the bit is only valid while Undefined PrAcc is set 0 Read transaction 1 Write transaction Processor Access PA Read value of this bit indicates if a Processor Access PA to the EJTAG memory is pending 0 No pending processor access 1 Pending processor access The probe s software must clear this bit to 0 to indicate the end of the PA Write of 1 is ignored PrAce A pending Processor Access is cleared when Rocc is set but another PA may occur just after the reset if a debug exception occurs Finishing a Processor Access is not accepted while the Rocc bit is set This is to avoid that a Processor Access occurring after the reset is finished due to indication of a Processor Access that occurred before the reset The FASTDATA access can clear this bit Res reserved 0 198 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 4 EJTAG TAP Registers Table 9 23 EJTAG Control Register Descriptions Continued Name Description Read Write Reset State PrRst ProbEn 15 Processor Reset Implementation dependent behavior
184. bes these modes The terminology is then used elsewhere in the document DebugMode Debugpy 1 ExceptionMode not DebugMode and Statusgy 1 or Statusgg 1 KernelMode lt not DebugMode or ExceptionMode and Statusyy 0 UserMode amp not DebugMode or ExceptionMode and Statusyy 1 9 7 2 Software versus Hardware control In some of the specifications and in this text the terms software control and hardware control are used to refer to the method for how trace is controlled Software control is when the CPO register TraceControl is used to select the modes to trace etc Hardware control is when the EJTAG register TCBCONTROLA in the TCB via the PDtrace interface is used to select the trace modes The TraceControl TS bit determines whether software or hardware control is active 9 7 3 Trace information The main object of trace is to show the exact program flow from a specific program execution or just a small window of the execution In EJTAG Trace this is done by providing the minimal cycle by cycle information necessary on the PDtrace interface for trace regeneration software to reproduce the trace The following is a summary of the type of information traced Only instructions which complete at the end of the pipeline are traced and indicated with a completion flag The PC is implicitly pointing to the next instruction MIPS32 4KE Processor Cores Software User s Manual
185. between the producer and consumer of the hazard Execution hazards can be removed by using the EHB JALR HB or JR HB instructions Instruction hazards can be removed by using the JALR HB or JR HB instructions in conjunction with the SYNCI instruction Since the 4KE core does not contain caches the SYNCI instruction is not strictly necessary but is still recommended to create portable code that can be run on other MIPS processors that may contain caches MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 31 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 2 Pipeline 32 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 3 Memory Management The MIPS32 4KE processor core includes a Memory Management Unit MMU that interfaces between the execution unit and the cache controller The MIPS32 4KEc core contains a Translation Lookaside Buffer TLB while the MIPS32 4KEm and MIPS32 4KEp cores implement a simpler Fixed Mapping FM style MMU This chapter contains the following sections Section 3 1 Introduction Section 3 2 Modes of Operation Section 3 3 Translation Lookaside Buffer 4KEc Core Only Section 3 4 Virtual to Physical Address Translation 4KEc Core Section 3 5 Fixed Mapping MMU 4KEm amp 4KEp Cores Section 3 6 System Control Coprocessor
186. ble 9 38 TCBTRIGx Register Field Descriptions Continued Fields Read Reset Names Bits Description Write State Trigger Type The Type indicates the action to take when this trigger fires The table below show the Type values and the Trigger action Type Trigger action 00 Trigger Start Trigger start point of trace 01 Trigger End Trigger end point of trace 10 Trigger About Trigger center point of trace Trigger Info No action trigger only for trace H info The actual action is to set or clear the TCBCONTROLBgy bit A Start trigger will set TCBCONTROLBpy a End trigger will clear TCBCONTROLBygy The About trigger will clear TCBCONTROLBygy half way through the trace memory from the trigger The size determined by the TCBCONFIGs field for on chip memory Or from the TCBCONTROLAgyp field for off chip trace Type 3 2 If Trace is set then a TF6 format is added to the trace words For Start and Info triggers this is done before any other TF s in that same cycle For End and About triggers the TF6 format is added after any other TF s in that same cycle If the TCBCONTROLBq1y field is implemented it must be set to Trace To mode 00 for the Type field to control on chip trace fill The write value of this bit always controls the behavior of this trigger When this trigger fires the read value will change to indicate if the trigger action was ever suppressed If so the read value wi
187. ble for writeback The actual register writeback is performed in the W stage all 4KE cores From this stage load data or a result from the MDU are available in the E stage for bypassing MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 13 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 2 Pipeline 2 1 5 W Stage Writeback During the Writeback stage For register to register or load instructions the result is written back to the register file 2 2 Instruction Cache Miss When the instruction cache is indexed the instruction address is translated to determine if the required instruction resides in the cache An instruction cache miss occurs when the requested instruction address does not reside in the instruction cache When a cache miss is detected in the I stage the core transitions to the E stage The pipeline stalls in the E stage until the miss is resolved The bus interface unit must select the address from multiple sources If the address bus is busy the request will remain in this arbitration stage B ASel in Figure 2 4 on page 14 until the bus is available The core drives the selected address onto the bus The number of clocks before data is returned is then determined by the array containing the data Once the data is returned to the core the critical word is written to the instruction register for immediate use The bypass mechanism allows the core to use the data as
188. ble trace information options The processor mode changes are always traced On the first instruction On any synchronization instruction When the mode changes and either the previous or the current processor mode is selected for trace The amount of extra information traced is programmable to include PC information only PC and load address PC and store address PC and load and store address PC and load address and load data PC and store address and store data PC and load and store address and load and store data PC and load data only The last option is helpful when used together with instruction accurate simulators If the full internal state of the processor is known prior to trace start PC and load data are the only information needed to recreate all register values on an instruction by instruction basis 9 7 6 1 User Data Trace In addition to the above a special CPO register UserTraceData can generate a data trace When this register is written and the global Trace On is set then the 32 bit data written is put in the trace as special User Data information Remark The User Data is sent even if the processor is operating in an un traced processor mode 9 7 7 Enable trace to probe on chip memory When trace is On based on the options listed in Section 9 7 5 Programmable processor trace mode options the trace information is continuously sent on the PDtrace interface to the TCB The TCB must
189. c All rights reserved 12 2 Instruction Listing Table 12 7 MIPS16 RRR Encoding of the f Field f bits 1 0 7 111 SRAV NOT p p Table 12 10 MIPS16 RR Encoding of the ry Field when funct J AL R C ry bits 7 5 0 1 2 3 4 6 7 110 111 000 001 010 011 100 Table 12 11 MIPS16 RR Encoding of the ry Field when funct CNVT bits 7 5 0 000 ZEB 12 2 Instruction Listing Table 12 12 through 12 19 list the MIPS16 instruction set Table 12 12 MIPS16 Load and Store Instructions Extensible Mnemonic Instruction Instruction LB Load Byte Yes LBU Load Byte Unsigned Yes LH Load Halfword Yes MIPS32 AKETM Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 275 Chapter 12 MIPS16 Application Specific Extension to the MIPS32 Instruction Set Table 12 12 MIPS16 Load and Store Instructions Extensible Mnemonic Instruction Instruction LHU Load Halfword Unsigned Yes LW Load Word Yes SB Store Byte Yes SH Store Halfword Yes SW Store Word Yes Table 12 13 MIPS16 Save and Restore Instructions Extensible Mnemonic Instruction Instruction RESTORE Restore Registers and Deallocate Stack Frame Yes Save Registers and Setup Stack Frame Table 12 14 MIPS16 ALU Immediate Instructions
190. can be sent to either on chip trace memory or to the trace probe The exact definition of the TW s is proprietary and will not be released at this time 9 8 PDtrace Registers software control The CPO registers associated with PDtrace are listed in Table 9 26 and described in Chapter 5 CPO Registers 208 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 9 Trace Control Block TCB Registers hardware control Table 9 26 A List of Coprocessor 0 Trace Registers Register Register Number Sel Name Reference 23 1 TraceControl Section 5 2 29 Trace Control Register CPO Register 23 Select 1 on page 136 23 2 TraceControl2 Section 5 2 30 Trace Control2 Register CPO Register 23 Select 2 on page 139 23 3 UserTraceData Section 5 2 31 User Trace Data Register CPO Register 23 Select 3 on page 141 23 4 TraceBPC Section 5 2 32 TraceBPC Register CPO Register 23 Select 4 on page 142 9 9 Trace Control Block TCB Registers hardware control The TCB registers used to control its operation are listed in Table 9 27 and Table 9 28 These registers are accessed via the EJTAG TAP interface Table 9 27 TCB EJTAG registers EJTAG Register Name Reference Implemented 0x10 TCBCONTROLA Section 9 9 1 TCBCONTROLA Register on page 209 0x11 TCBCONTROLB Section 9 9 2 TCBCONTROLB Register on page 212
191. ce a 0 1 transition Indicates that the entry through the reset exception vector was due to a Soft Reset Encoding Meaning 1 for Soft SR 20 0 Not Soft Reset NMI or Reset R W Reset 0 1 Soft Reset otherwise Software can only write a 0 to this bit to clear it and cannot force a 0 1 transition 106 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Fields Name Bits Table 5 17 Status Register Field Descriptions Description Read Write Reset State NMI 19 R 17 16 IM7 IM2 15 10 IPL 15 10 Indicates that the entry through the reset exception vector was due to an NMI Encoding Meaning 0 Not NMI Soft Reset or Reset Software can only write a 0 to this bit to clear it and cannot force a 0 1 transition Must be written as zero returns zero on read Reserved Ignored on write and read as zero Interrupt Mask Controls the enabling of each of the hardware interrupts Refer to Section 4 3 Interrupts on page 55 for a complete discussion of enabled interrupts An interrupt is taken if interrupts are enabled and the corresponding bits are set in both the Interrupt Mask field of the Status register and the Interrupt Pending field of the Cause register and the IE bit is set in the Status register Encoding Meaning
192. ception Handling and Servicing Guidelines ees 86 Figure 5 1 Index Register Format entente pete testet nietos ecd enis 91 Figute 5 2 Random Register Format e eee erret dan gates EUR nim pt ep pee Pede 92 Figure 5 3 EntryLo0 EntryLol Register Format A 93 Figure 5 74 Context Register Borger ee o Oei rr teme I De He ree ie ier tp 95 Figure 5 5 PageMask Register Format seeseseseeseeeeeeeeeeneeenee a REE rennen Eos EENE EESE S tentent nter oaia ene 96 Figure 5 6 PageGrain Register Format occ scopre e ee etre pre de ee E det Ee ene 98 Figure 5 7 Wired and Random Entries in the TLB eterne entente nen nennen nennen enne ene 99 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All right reserved Figure 5 8 Wired Register Format 99 Figure 5 9 HWREna Resister Format n eee etes e cete vues EP ree ent ee costs savas d e ERAS 100 Figure 5 10 BadVAddr Register Format 101 Figure S ll Count Register Format eu ete et eR dech ee E een Seat 102 Figure 5 12 EntryHi Register Format seien a ee e o E enr A nen nh E EA EEE nennt enne teet ne trennen renes trennen 103 Figure 5 13 Compare Register Format ent eene tete nee o ees 104 Figure 5 14 Status Register Format 105 Figure 5 15 IntCtL Register Format ace tope etr erecto UH e Ee eb te E deve o cie ete eet 110 Figure 5 16 SRSCt Register Format 112 Figure 5 17 SRSMap
193. cessor Core Instructions on page 237 for a listing of CPO instructions MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 10 7 Enhancements to the MIPS Architecture 10 7 Enhancements to the MIPS Architecture The core execution unit implements the MIPS32 architecture which includes the following instructions CLOCount Leading Ones CLZCount Leading Zeros MADDMultiply and Add Word MADDUMultiply and Add Unsigned Word MSUBMultiply and Subtract Word MSUBUMultiply and Subtract Unsigned Word MULMultiply Word to Register SSNOPSuperscalar Inhibit NOP 10 7 1 CLO Count Leading Ones The CLO instruction counts the number of leading ones in a word The 32 bit word in the GPR rs is scanned from most significant to least significant bit The number of leading ones is counted and the result is written to the GPR rd If all 32 bits are set in the GPR rs the result written to the GPR rd is 32 10 7 2 CLZ Count Leading Zeros The CLZ instruction counts the number of leading zeros in a word The 32 bit word in the GPR rs is scanned from most significant to least significant bit The number of leading zeros is counted and the result is written to the GPR rd If all 32 bits are cleared in the GPR rs the result written to the GPR rd is 32 10 7 3 MADD Multiply and Add Word The MADD instruction multiplies two words and adds the result to the HI LO re
194. ch DDBSImpr DDBLImpr Imprecise Error eXception Inhibit controls exceptions taken due to imprecise error indications Set when the processor takes a debug exception or exception in debug mode Cleared by execution of the DERET instruction otherwise modifiable by debug mode software When IEXI is set the imprecise error exception from a bus error on an instruction fetch or data access cache error or machine check is inhibited and deferred until the bit is cleared Indicates that an imprecise Debug Data Break Store exception was taken AII data breaks are precise on the 4KE cores so this bit will always read as 0 Indicates that an imprecise Debug Data Break Load exception was taken AII data breaks are precise on the 4KE cores so this bit will always read as 0 H D Indicates the Count register behavior in debug mode 25 0 Count register stopped in debug mode RW 1 Count register is running in debug mode Instruction fetch Bus Error exception Pending Set when an instruction fetch bus error event occurs or if a 1 is written to the bit by software Cleared when a Bus 24 Error exception on instruction fetch is taken by the R W processor and by reset If IBusEP is set when IEXI is cleared a Bus Error exception on instruction fetch is taken by the processor and IBusFP is cleared Indicates that an imprecise Machine Check exception is 23 pending All Machine Check exceptions are precise on R the 4KE processors so this bit will
195. che only supports reads hence only LRU entries are stored in the instruction way select array Table 7 3 LRU and Dirty Width in Way Select Array Dirty Bits data Associativity n LRU Bits cache only 1 0 1 2 1 2 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 155 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 7 Caches Table 7 3 LRU and Dirty Width in Way Select Array Dirty Bits data Associativity n LRU Bits cache only 3 3 3 4 6 4 7 2 2 Cacheability Attributes A 4KE core supports the following cacheability attributes Uncached Addresses in a memory area indicated as uncached are not read from the cache Stores to such addresses are written directly to main memory without changing cache contents Write back with write allocation Loads and instruction fetches first search the cache reading main memory only if the desired data does not reside in the cache On data store operations the cache is first searched to see if the target address is cache resident If it is resident the cache contents are updated but main memory is not written If the cache lookup misses on a store main memory is read to bring the line into the cache and merge it with the new store data Hence the allocation policy on a cache miss is read or write allocate Data stores will update the appropriate dirty bit in the way select array to indicate that t
196. ched from main memory In this example it takes two clocks 3 and 4 to fetch the I4 instruction from memory Once the cache miss is resolved in clock 4 and the instruction is bypassed to the E stage the pipeline is restarted causing the I4 instruction to finally execute it s E stage operations 2 12 Instruction Interlocks Most instructions can be issued at a rate of one per clock cycle In order to adhere to the sequential programming model the issue of an instruction must sometimes be delayed This to ensure that the result of a prior instruction is available Table 2 5 details the instruction interactions that prevent an instruction from advancing in the processor pipeline Table 2 5 Instruction Interlocks Instruction Interlocks Issue Delay in First Instruction Second Instruction Clock Cycles Slip Stage LB LBU LH LHU LL LW LWL LWR Consumer of load data 1 E stage MFCO Consumer of destination 1 E stage register MULTx MADDx MSUBx 16bx32b 0 4KEc and 4KEm cores MFLO MFHI 32bx32b 1 M stage MUL 16bx32b 2 E stage 4KEc and 4KEm cores Consumer of target data 32bx32b 3 E stage MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 27 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 2 Pipeline Table 2 5 Instruction Interlocks Instruction Interlocks Issue Delay in First Instruction Second Instruction Clock Cycles Slip Stage MUL
197. clock The minimum possible value for TCBCONFIGcppin is 1 8 TR CLK is running at one eighth of the core clock See Table 9 31 on page 216 for a description of the encoding of the clock ratio fields MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 229 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support 9 12 4 Adding cycle accurate information to the trace Depending on the trace regeneration software it is possible to obtain the exact cycle time relationship between each instruction in the trace This information is added to the trace when the TCBCONTROLB bit is set The overhead on the trace information is a little more than one extra bit per core clock cycle This setting only affects the TCB module and not the PDtrace module The extra bit therefore only affects the likelihood of the TCB fifo overflowing 9 13 TCB On Chip Trace Memory When on chip trace memory is available CCBCONFIG Qj is set the memory is typically of smaller size than if it were external in a trace probe The assumption is that it is of some value to trace a smaller piece of the program With on chip trace memory the TCB can work in three possible modes l Trace From mode 2 Trace To mode 3 Under Trigger unit control Software can select this mode using the TCBCONTROLB py field If one or more trigger control registers TCBTRIGx are implemented and they are using Start End or
198. ctive address must be naturally aligned If either of the 2 least significant bits of the effective address is non zero an Address Error exception occurs Operation vAddr lt sign extend offset GPR base if vAdd 5 0 then SignalException AddressError endif pAddr CCA lt AddressTranslation vAddr DATA LOAD memword lt LoadMemory CCA WORD pAddr vAddr DATA GPR rt lt memword LLbit cl MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Load Linked Word cont Exceptions TLB Refill TLB Invalid Address Error Reserved Instruction Watch Programming Notes There is no Load Linked Word Unsigned operation corresponding to Load Word Unsigned MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved LL 255 Prefetch PREF 256 31 26 25 21 20 16 15 0 PREF base hint offset 110011 6 5 5 16 Format PREF hint offset base MIPS32 Purpose To move data between memory and cache Description prefetch memory base offset PREF adds the 16 bit signed offset to the contents of GPR base to form an effective byte address The hint field sup plies information about the way that the data is expected to be used PREF is an advisory instruction that may change the performance of the program H
199. cts Processor Access operation PRnW 0 selects processor read operation Psz 1 0 value depending on the transfer size 3 The EJTAG Probe selects the EJTAG Control register shifts out this control register s data and tests the PrAcc status bit Processor Access when the PrAcc bit is found 1 it means that the requested address is available and can be shifted out 4 The EJTAG Probe checks the PRnW bit to determine the required access 5 The EJTAG Probe selects the PA Address register and shifts out the requested address 6 The EJTAG Probe selects the PA Data register and shifts in the instruction corresponding to this address MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 203 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support 7 The EJTAG Probe selects the EJTAG Control register and shifts a PrAcc 0 bit into this register to indicate to the processor that the instruction is available 8 The instruction becomes available in the instruction register and the processor starts executing 9 The processor increments the program counter and outputs an instruction read request for the next instruction This starts the whole sequence again Using the same protocol the processor can also execute a load instruction to access the EJTAG Probe s memory For this to happen the processor must execute a load instruction e g a LW LH LB with the target address in t
200. d Interrupts The MIPS32 4KE processor core receives exceptions from a number of sources including translation lookaside buffer TLB misses arithmetic overflows I O interrupts and system calls When the CPU detects one of these exceptions the normal sequence of instruction execution is suspended and the processor enters kernel mode In kernel mode the core disables interrupts and forces execution of a software exception processor called a handler located at a specific address The handler saves the context of the processor including the contents of the program counter the current operating mode and the status of the interrupts enabled or disabled This context is saved so it can be restored when the exception has been serviced When an exception occurs the core loads the Exception Program Counter EPC register with a location where execution can restart after the exception has been serviced Most exceptions are precise which mean that EPC can be used to identify the instruction that caused the exception For precise exceptions the restart location in the EPC register is the address of the instruction that caused the exception or if the instruction was executing in a branch delay slot the address of the branch instruction immediately preceding the delay slot To distinguish between the two software must read the BD bit in the CPO Cause register Bus error exceptions and CP2 exceptions may be imprecise For imprecise exceptions the in
201. de 2 0 GPR rt That is the upper 31 bits of the GPR are written to the upper 31 bits of the debug exception PC and the lower bit of the debug exception PC is cleared The upper bit of the ISAMode field is cleared and the lower bit is loaded from the lower bit of the GPR Figure 5 35 DEPC Register Format 31 0 DEPC Table 5 39 DEPC Register Formats Fields Read Name Bit s Description Write Reset The DEPC register is updated with the virtual address of the instruction that caused the debug exception If the instruction is in the branch delay slot then the virtual DEPC 31 0 address of the immediately preceding branch or jump R W Undefined instruction is placed in this register Execution of the DERET instruction causes a jump to the address in the DEPC MIPS32 AKETM Processor Cores Software User s Manual Revision 02 00 143 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers 5 2 34 ErrCtl Register CPO Register 26 Select 0 The ErrCtl register provides a mechanism for enabling software testing of the way select and data RAM arrays for both the ICache and DCache The way selection RAM test mode is enabled by setting the WST bit It modifies the functionality of the CACHE Index Load Tag and Index Store Tag operations so that they modify the way selection RAM and leave the Tag RAMs untouched When this bit is set the lower 6 bits of the PA field in t
202. default reset state the vector spacing is zero and the processor reverts to Interrupt Compatibility Mode A non zero value enables vectored interrupts and Table 4 4 shows the exception vector offset for a representative subset of the vector numbers and values of the IntCtlyg field Table 4 4 Exception Vector Offsets for Vectored Interrupts Value of IntCtlys Field Vector Number 2800001 2400010 2 00100 2501000 2510000 0 1650200 1650200 1650200 1650200 1650200 1 16 0220 16 0240 16 0280 16 0300 16 0400 2 16 0240 16 0280 16 0300 16 0400 16 0600 3 16 0260 16 02C0 16 0380 16 0500 16 0800 4 16 0280 16 0300 16 0400 16 0600 16 0A00 5 16 02A0 16 0340 16 0480 16 0700 16 0C00 6 16 02C0 16 0380 16 0500 16 0800 16 0E00 7 16 02E0 16 03C0 16 0580 16 0900 16 1000 i e 61 16 09A0 16 1140 16 2080 16 3F00 16 7C00 62 16 09CO 16 1180 16 2100 16 4000 16 7E00 63 16 09E0 16 11C0 16 2180 16 4100 16 8000 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 63 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 4 Exceptions and Interrupts The general equation for the exception vector offset for a vectored interrupt is vectorOffset lt 164200 vectorNumber X IntCtlyg 2 00000 4 4 GPR Shadow Registers Release 2 of the Architecture optionally removes the need to save and restore GPRs on entry to high priority interrupts or exceptions and
203. ds must be initialized by software in the Reset exception handler if the reset value is not desired Figure 5 22 Config Register Format Select 0 3130 2827 2524 23 22 21 20 1918 17 16 15 14 13 12 10 9 7 6 3 2 0 M K23 KU ISPDSPUDI SB MDU 0 MM BM BE AT AR MT 0 KO Figure 5 23 Config Register Field Descriptions Fields Read W Name Description rite Reset State M This bit is hardwired to 1 to indicate the presence of the R 1 Config register This field controls the cacheability of the kseg2 and kseg3 address segments in FM implementations This field is K23 valid in the 4AKEp and 4KEm processor and is reserved in the 4KEc processor TLB R TLB 000 Refer to Table 5 27 for the field encoding FM R W FM 010 This field controls the cacheability of the kuseg and useg address segments in FM implementations This field is R W KU valid in the 4KEp and 4KEm processor and is reserved in EM ENE O18 the 4KEc processor TLB R TLB 000 Refer to Table 5 27 for the field encoding Indicates whether Instruction ScratchPad RAM is present Set by the JSP_Present static input pin if scratchpad was ISP enabled when the core was built R Externally Set 0 No Instruction ScratchPad is present 1 Instruction ScratchPad is present Indicates whether Data ScratchPad RAM is present Set by the DSP_Present static input pin if scratchpad was DSP enabled when the core was built R Externally Set 0 No D
204. duce the frequency of TLB flushing on a context switch The existence of the ASID allows multiple processes to exist in both the TLB and instruction caches The ASID value is stored in the EntryHi register and is compared to the ASID value of each entry 3 3 2 Instruction TLB The ITLB is a small 4 entry fully associative TLB dedicated to perform translations for the instruction stream The ITLB only maps 4 Kbyte pages sub pages or 1 Kbyte pages sub pages if Config3 sp 1 and PageGraingsp 1 The ITLB is managed by hardware and is transparent to software If a fetch address cannot be translated by the ITLB the JTLB is accessed trying to translate it in the following clock cycle If successful the translation information is copied into the ITLB The ITLB is then re accessed and the address will be successfully translated This results in an ITLB miss penalty of at least 2 cycles If the JTLB is busy with other operations it may take additional cycles 3 3 3 Data TLB The DTLB is a small 4 entry fully associative TLB which provides a faster translation for Load Store addresses than is possible with the JTLB The DTLB only maps 4 Kbyte pages sub pages or 1 Kbyte pages sub pages if Config3sp 1 and PageGraingsp 1 Like the ITLB the DTLB is managed by hardware and is transparent to software Unlike the ITLB an access to the DTLB starts a parallel access to the JTLB If there is a DTLB miss and a JTLB hit the DTLB can be reloaded that cycle The DTLB
205. e 9 15 DBMn Register Field Descnppong rennen nnne nenne nenne eve tnter enne treten enne 182 Table 9 16 DBASIDn Register Field Descriptions nennen nennen nennen neret treten enne trennen 183 Table 9 17 DBCn Register Field Descriptions aet er eem REP eb dee re ee epe i een 184 Table 9 18 DBVn Register Field Descriptions neret nnne nennen ne teetn tener enne terere treten enne 186 Table 9 19 EJTAG Interface EE 187 Table 9 20 Implemented EJTAG Instructions seeeeeeeseeeseeeeneneenne nennen nennen nennen nete nenne terere enne treten enne 191 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All right reserved Xi xii Table 9 21 Device Identification Register A 195 Table 9 22 Implementation Register Descriptions eese enne nennen nnnm nente tenter enne enne trennen 196 Table 9 23 EJTAG Control Register Descriptions esessesssseeeeeeeeee ener nennen tentent tentent treten rennen enne 197 Table 9 24 Fastdata Register Field Description sees eene nennen nente ener ESKE NEE E 202 Table 9 25 Operation of the FASTDATA access eene nennen nennen retener eterne t rennen ene en rennen 202 Table 9 26 A List of Coprocessor 0 Trace Registers sssseseeeeeeeeeeeeeen nennen nennen nennen tne nne enne treten ene 209 Table 9 27 TCB BJEAG registers tee een ee e e e eade eter e eire Ee 209 Table 9 28 Registers selected by TCBCON
206. e Cycle One Cycle ADD l E M A W R3 R2 R1 M to E bypass A to E bypass R4 R3 R7 M to E bypass ADD R5 R3 R4 Figure 2 18 IU Pipeline M to E bypass 2 8 1 Load Delay Load delay refers to the fact that data fetched by a load instruction is not available in the integer pipeline until after the load aligner in A stage All instructions need the source operands available in the E stage An instruction immediately following a load instruction will if it has the same source register as was the target of the load cause an instruction interlock pipeline slip in the E stage see Section 2 12 Instruction Interlocks on page 27 If an instruction following the load by 1 or 2 cycles uses the data from the load the A to E bypass see Figure 2 17 serves to reduce or avoid stall cycles An instruction flow of this is shown in Figure 2 19 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 23 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 2 Pipeline One Cycle One Cycle One Cycle One Cycle One Cycle Load Instruction E M A W Data bypass from A toE One Cycle M A Consumer of Load Data Instruction One Clock Load Delay Figure 2 19 IU Pipeline A to E Data bypass 2 8 2 Move
207. e Description Write Reset State Version 4 bits Version This field identifies the version number of the R EJ Version 3 0 processor derivative Part Number 16 bits PartNumber This field identifies the part number of the processor R EJ PartNumber 15 0 derivative Manufacturer Identity 11 bits ManufID Accordingly to IEEE 1149 1 1990 the manufacturer R EJ_ManufID 10 0 identity code shall be a compressed form of the JEDEC Publications 106 A 9 4 2 3 Implementation Register This 32 bit read only register is used to identify the features of the EJTAG implementation Some of the reset values are set by inputs to the core The register is selected when the Instruction register is loaded with the IMPCODE instruction Implementation Register Format 31 29 28 25 24 23 21 20 17 16 15 14 13 0 EJTAGver reserved DINTsup ASIDsize reserved MIPSI6 0 NDMA reserved MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 195 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support Table 9 22 Implementation Register Descriptions Fields Description Reset State EJTAG Version EJTAGver 31 29 2 Version 2 6 R 2 DINTsup ASIDsize DINT Signal Supported from Probe This bit indicates if the DINT signal from the probe is supported 0 DINT signal from the probe is not supported 1 Probe can use DINT signal to make debug interrupt Size of ASID field
208. e G bit in the TLB entry Recall that this bit was set from the logical AND of the two G bits in EntryLo0 and EntryLol when the TLB was written Restrictions The operation is UNDEFINED if the contents of the Index register are greater than or equal to the number of TLB entries in the processor If access to Coprocessor 0 is not enabled a Coprocessor Unusable Exception is signaled MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 265 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Read Indexed TLB Entry TLBR Operation i Index if i TLBEntries 1 then UNDEFINED endif PageMaskyasy TLB ilywagx EntryHi TLB i vpw 0 TLBlilasrp EntryLol 0 TLB il peu TLB ile TLB ilp TLBLily TLB ilg EntryLoO lt 0 TLB i prewo TLB i eg TLB ilpg TLB il yg TLB ilg Exceptions Coprocessor Unusable 266 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Write Indexed TLB Entry TLBWI 31 26 25 24 6 COPO CO 0 TLBWI 010000 1 000 0000 0000 0000 0000 000010 6 1 19 6 Format TLBWI MIPS32 Purpose To write a TLB entry indexed by the Index register Description The TLB entry pointed to by the Index register is written from the contents of the EntryHi EntryLoO Ent
209. e No beso ie kon 203 9 6 Fetch Load and Store from to the EJTAG Probe through dmseg eene 203 O9 BUD AG ER 2r ree REGI IIS IM RE nud 204 9 7 Processor Modes epa EO pc irr ee ar e HR Ri pne E ERE ep sheet 205 9 7 2 Software versus Hardware control esses eene ene neen nen nHeneee tee tnne trennen ene 205 9 7 3 Trace anformation 2 deett nap ee ro e OR ERU PR EUER SE E Hp i Ri ER 205 9 7 4 Load Store address and data trace information sss eene 206 9 7 5 Programmable processor trace mode options ssssssssssseseeeee eene ene neen nennen nretnnetre tenere 207 9 7 6 Programmable trace information options essent ener nennen nemen nennen treten en 207 9 7 7 Enable trace to probe on chip memory sese etre en en neen nennen ee tret tee tenere 207 9T S CB Trgger ec gp Pneu DE gi 208 9 7 9 Cycle by cycle anformation n nne gente ctt er e e pi tt idet ers ite ah 208 9 7 10 Trace Message Format SEENEN eh i E e tet el iet o i IE ee 208 9 7 11 Trace Word Format o eiie ne teer ee e HERE iR ERES 208 9 8 PDtrace Registers software control niieoee nekeer a EEEE E EA EE EE EE EN EEKE S 208 9 9 Trace Control Block TCB Registers hardware control eese eene nennen nere nennen 209 9 9 TCBCONTROLA Register 41e eo Ee eie e ite e eR hg EESE EEEE Eia 209 9 9 2 TCBCONTROLB Register osito bb ue er nid te eer bi tree n Henn
210. e basic EJTAG support with debug mode run control single step and software breakpoint instruction SDBBP as part of the core These features allow for the basic software debug of user and kernel code Optional EJTAG features include hardware breakpoints A 4KE core may have four instruction breakpoints and two data breakpoints two instruction breakpoints and one data breakpoint or no breakpoints The hardware instruction breakpoints can be configured to generate a debug exception when an instruction is executed anywhere in the virtual address space Bit mask and Address Space Identifier ASID values may apply in the address compare These breakpoints are not limited to code in RAM like the software instruction breakpoint SDBBP The data breakpoints can be configured to generate a debug exception on a data transaction The data transaction may be qualified with both virtual address data value size and load store transaction type Bit mask and ASID values may apply in the address compare and byte mask may apply in the value compare An optional TAP enabling communication between an EJTAG probe and the CPU through a dedicated port may also be applied to the core This provides the possibility for debugging without debug code in the application and for download of application code to the system Another optional block is EJTAG Trace which enables real time tracing capability The trace information can be stored to either an on chip trace memory
211. e i e AD b ERR 45 3 4 Virtual to Physical Address Translation AKEc Core sssseseesseseeeee eene nennt enne tenen nennen 45 3 4 1 Hits Misses and Multiple Matches AA 47 3 4 2 Memory Space 5 ceat ee REPE Dre aio ea Ud emite dete ei n en 48 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All right reserved 3 43 RE ur tere EE 49 3 5 Fixed Mapping MMU 4KEm amp 4KEp Cores esses ener enne en nennen nennen nennen 50 3 6 System Control COprOCessOr e tee eene p re ir obest er e ete eot deer e E etr Te ee pete re eres eoe Hiro Eden 52 Chapter 4 Exceptions and Interrupts esee ei een esere nnne tee EINE SE SESS peie reani PE CEs EE aioi terne 53 4 1 Exception Conditions eer ec a Ree eru EE e ed nes 53 42 Exception Priory EE 54 4 3 Interrupts e eebe EES ec 55 4 3 Interrupt Modes Ae i ee p semel os PR inq Ae en 55 4 3 2 Generation of Exception Vector Offsets for Vectored Interrupts 63 AAGPR Shadow Registers eere eee tee ree ev Un EN 64 4 5 Exception Vector Locations x eiicetoe tier eere teet aem eege ee 65 4 6 General Exception Processing eneret i nennen E E EE EO enne etr se tente ee tente nenne EE etre nene 66 4 7 Debus Exception PLOCESSING see t o e e a Rr reete terere e n Re eek se lees 68 4 8 BXCeptonDs care eee dor dirt eee S 69 4 8 T Reset BXCception ier Ute i etse e mU eL ee eee pe e E d 69 4
212. e kseg3 in Debug mode if so desired MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 35 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 3 Memory Management 36 Virtual Address User Mode Kernel Mode Debug Mode kseg3 2e kseg3 E at kseg2 e 1 0 F xE000 000 E kseg1 xO9FFF FFFF ksegO x8000_0000 x7FFF FFFF useg kuseg 0x0000 0000 Figure 3 3 4KE processor core Virtual Memory Map Each of the segments shown in Figure 3 3 on page 36 are either mapped or unmapped The following two sub sections explain the distinction Then sections Section 3 2 2 User Mode Section 3 2 3 Kernel Mode and Section 3 2 4 Debug Mode specify which segments are actually mapped and unmapped 3 2 1 1 Unmapped Segments An unmapped segment does not use the TLB 4KEc core or the FM 4KEm and 4KEp cores to translate from virtual to physical addresses Especially after reset it is important to have unmapped memory segments because the TLB is not yet programmed to perform the translation Unmapped segments have a fixed simple translation from virtual to physical address This is much like the translations the FM provides for the 4KEm and 4KEp cores but we will still make the distinction Except for kseg0 unmapped segments are always uncached The cacheability of ksegO is set in the KO field of the CPO register Config
213. e replacement algorithm when a TLB miss occurs To select a TLB entry to be written with a new mapping the 4KEc core provides a random replacement algorithm However the processor also provides a mechanism whereby a programmable number of mappings can be locked into the TLB via the CPO Wired register thus avoiding random replacement Please refer to Section 5 2 7 Wired Register CPO Register 6 Select 0 on page 99 for further details MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 3 4 Virtual to Physical Address Translation 4KEc Core For valid address Virtual Address Input space see the section describing Modes of operation in this chapter User Address Exception kseg0 kseg Address No No Yes TLB Noncacheable TLB TLB Modified Invalid Refill Physical Address Output Figure 3 10 TLB Address Translation Flow in the 4KE Processor Core 3 4 3 TLB Instructions Table 3 8 lists the 4KEc core s TLB related instructions Refer to Chapter 11 MIPS32 4KE Processor Core Instructions on page 237 for more information on these instructions Table 3 8 TLB Instructions Op Code Description of Instruction TLBP Translation Lookaside Buffer Probe TLBR Translation Lookaside Buffer Read TLBWI Translation Lookaside Buffer Write Index MIPS32 4KE Proces
214. e setting of TraceControlyg bit The first option is free of any cycle by cycle change whether trace is turned on or not This is achieved at the cost of potentially losing trace information After an overflow the fifo is completely emptied and the next instruction is traced as if it was the start of the trace processor mode and full PC are traced This guarantees that only the un traced fifo information is lost MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 12 EJTAG Trace cycle by cycle behavior The second option guarantees that all the trace information is traced to the TCB In some cases this is then achieved by back stalling the core pipeline giving the PDtrace fifo time to empty enough room in the fifo to accept new trace information from a new instruction This option can obviously change the real time behavior of the core when tracing is turned on If PC trace information is the only thing enabled in TraceControlyopg or TCBCONTROLA wopyg depending on the setting of TraceControl ys and Trace of all branches is turned off via TraceControlyg or TCBCONTROLAT5 depending on the setting of TraceControlTs then the fifo is unlikely to overflow very often if at all This is of course very dependent on the code executed and the frequency of exception handler jumps but with this setting there is very little information overhead 9 12 3 H
215. e the block back to the memory address specified by the cache tag After that operation is completed set the state of the cache block to invalid If the block is valid but not dirty set the state of the block to invalid This encoding may be used by software to invalidate the entire data cache by stepping through all valid indices Note that Index Store Tag should be used to initialize the cache at powerup No 2 001 LD Index Load Tag 2 010 LD Index Store Tag Index Read the tag for the cache block at the specified index into the TagLo Coprocessor 0 register Also read the data corresponding to the byte index into the DataLo register Write the tag for the cache block at the specified index from the TagLo Coprocessor 0 register This encoding may be used by software to initialize the entire instruction or data caches by stepping through all valid indices Doing so requires that the TagLo and TagHi registers associated with the cache be initialized first 256011 All Reserved Unspecified Executed as a no op No MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 249 Table 11 13 Encoding of Bits 20 18 of the CACHE Instruction ErrCtl WST SPR Cleared Effective Address Operand Name Type Operation Implemented Hit Invalidate Address If the cache block contains the specified address set the
216. ector so TLBMod TLBInv or TLB Refill exceptions not possible EXL 1 so Watch Interrupt exceptions disabled OS System to avoid all other exceptions Only Reset Soft Reset NMI exceptions possible Load the mapping of the virtual address in Context Reg Move it to EntryLo and write into the TLB There could be a TLB miss again during the mapping of the data or instruction address The processor will jump to the general exception vector since the EXL is 1 Option to complete the first level refill in the general exception handler or ERET to the original instruction and take the exception again ERET is not allowed in the branch delay slot of another Jump Instruction Processor does not execute the instruction which is in the ERET s branch delay slot PC EPC EXL 0 LLbit 0 Figure 4 6 TLB Exception Servicing Guidelines SW 4KEc Core MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 85 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 4 Exceptions and Interrupts Reset Exception Random TLBENTRIES 1 Soft Reset or NMI Exception Wired 0 Config Reset state Status TS lt 0 RP lt 0O SR e 1 0 BEV lt 1 NMI lt 0 1 TS lt 0 ERL lt 1 SR lt 0O NMI 0 ERL lt 1 WatchLo LI RWc 0 ErrorEPC PC PC OxBFCO 0000 Reset Soft Reset amp NMI Exception Handling HW Gu
217. ed reducing system power consumption during idle periods The core provides two mechanisms for system level low power support discussed in the following sections Section 8 1 Register Controlled Power Management Section 8 2 Instruction Controlled Power Management 8 1 Register Controlled Power Management The RP bit in the CPO Status register enables a standard software mechanism for placing the system into a low power state The state of the RP bit is available externally via the Af RP output signal Three additional pins AT EXL S ERL and EJ DebugM support the power management function by allowing the user to change the power state if an exception or error occurs while the core is in a low power state Setting the RP bit of the CPO Status register causes the core to assert the AT RP signal The external agent can then decide whether to reduce the clock frequency and place the core into power down mode If an interrupt is taken while the device is in power down mode that interrupt may need to be serviced depending on the needs of the application The interrupt causes an exception which in turn causes the EXL bit to be set The setting of the EXL bit causes the assertion of the SZ EXL signal on the external bus indicating to the external agent that an interrupt has occurred At this time the external agent can choose to either speed up the clocks and service the interrupt or let it be serviced at the lower clock speed The setting
218. ed when using the simple break control in the PDtrace interface to start or stop trace TM Trace Mode Trace To Trace From Reserved Reserved TM 13 12 In Trace To mode the on chip trace memory is filled R W 0 continuously wrapping around and overwriting older Trace Words as long as there is trace data coming from the core In Trace From mode the on chip trace memory is filled from the point that PDO_lamTracing is asserted and until the on chip trace memory is full In both cases de asserting the EN bit in this register will also stop fill to the trace memory If a TCBTRIGx trigger control register is used to start stop tracing then this field should be set to Trace To mode This bit is reserved if on chip memory is not implemented 0 11 Reserved Must be written as zero returns zero on read R 0 Off chip Clock Ratio Writing this field sets the ratio of the core clock to the off chip trace memory interface clock The clock ratio encoding is shown in Table 9 31 on page 216 CR 10 8 Remark As the Probe interface works in double data rate R W 100 DDR mode a 1 2 ratio indicates one data packet sent per core clock rising edge This bit is reserved if off chip trace option is not implemented 214 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 9 Trace Control Block TCB Registers hardware c
219. eeesseeseeeeeeeeeeeneenenen rennen rennen rennen nennen nennen 98 Table 5 11 Wired Register Field Descriptions essent nenne ennt erint trennen trennen trennen 99 Table 5 12 HWREna Register Field Descriptions sees nennen nenne enne een nene en rennen 100 Table 5 13 BadVAddr Register Field Description eeeeeeeeseeeeee eene nennen nennen enne ener ennen rennen 101 Table 5 14 Count Register Field Descpton eee nne nen nete tnne terere treten enne 102 Table 5 15 EntryHi Register Field Descriptions essere eene enne treten enne 103 Table 5 16 Compare Register Field Description sess nennen nter treten nete ennen rennen 104 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All right reserved Table 5 17 Status Register Field Descriptions sesessesssseeeeeseeeeeene ener nennen trennen neetene trennen rennen etre 105 Table 5 18 IntCtl Register Field Descriptions esessesssseeeeeeeseeeener enne nennen nemen nennen trennen enin N VEEN peeo 110 Table 5 19 SRSCtl Register Field Descriptions ener ener eee tente ne treten rennen enr enne enne 112 Table 5 20 Sources for new SRSCtlcss on an Exception or Interupt nnne 113 Table 5 21 SRSMap Register Field Descriptions eesesseeeeeeeeeeeeeeeeeee nennen nennen nenne treten rennen rerit ennt 115 Table 5 22 Cause Register Field Descptons enne nennen tnne tereti
220. eene 78 4 8 19 Execution Exception Coprocessor 2 Exception 78 4 8 20 Execution Exception Implementation Specific 1 exception sess 78 4 8 21 Execution Exception Implementation Specific 2 exception sese 79 4 8 22 Execution Exception Integer Overflow sesssesseeeseee eene nennen nennen nennen nete trennen nenne 79 4 8 23 Execution Exception Trap E 79 4 8 24 Debug Data Break Exception irosen a ener nee nennen teen entente e Aa e E nenne 80 4 8 25 TLB Modified Exception Data Access 4KEc core Only essere 80 4 9 Exception Handling and Servicing Flowcharts sees eene en enne en emnes 81 Chapters CPO Re9gISters nep g rp UE E E SERIE UU NI AI EUR RO UHR 87 3 CPO Register SUMM TY rere rer beret e RC hy EP EO CURE E D EE POE EEE EEEa EES kr EEES 88 3 2 CPO Register Descriptions inerte ee ha el e i tete iter pest i acaba gates 90 5 2 1 Index Register CPO Register OD Select O iscissi see tee netten ettet Ret E RR soaeseseness 91 5 2 2 Random Register CPO Register 1 Select 0 eene 92 5 2 3 EntryLoO and EntryLol Registers CPO Registers 2 and 3 Select 0 esse 93 5 2 4 Context Register CPO Register 4 Select 0 sess ene 95 5 2 5 PageMask Register CPO Register 5 Select 0 sss eene nennen eene eene tree 96 5 2 6 PageGrain Register CPO Register 5 Select II 98 5 2 7 Wired Register CPO Register 6 Select O stisnes s
221. ees erines orosei aa rare i tpe tici ree rete e EEE ben 99 5 2 8 HWREna Register CPO Register 7 Select 0 eene eterne ne etrenneeneen 100 5 2 9 BadVAddr Register CPO Register 8 Select 0 sesssssessssseseseeeeeeeeer ener nennen nennen 101 5 2 10 Count Register CPO Register 9 Select 0 essent eterne rennen trennen 102 5 2 11 EntryHi Register CPO Register 10 Select 0 sees enne nennt en nee entree 103 iv MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All right reserved 5 2 12 Compare Register CPO Register 11 Select 0 eene 104 5 2 13 Status Register CPO Register 12 Select 0 sessi en Sp SERE OE pen nee 105 5 2 14 IntCtl Register CPO Register 12 Select 1 tenere ener en enne nennen 110 5 2 15 SRSCII Register CPO Register 12 Select 2 essere eren retener nennen 112 5 2 16 SRSMap Register CPO Register 12 Select 3 ener nee entree 115 5 2 17 Cause Register CPO Register 13 Select 0 sess eee en enne nennen 116 5 2 18 Exception Program Counter CPO Register 14 Select 0 sess enne 120 5 2 19 Processor Identification CPO Register 15 Select 0 esses nennen enne nene 121 5 2 20 EBase Register CPO Register 15 Select Ji 122 5 2 21 Config Register CPO Register 16 Select 0 sse enne eren rennen trennen 123 5 2 22 Config1 Register CPO Regist
222. eld Descriptions Fields Reset Description State nu 21 20 Must be written as zeros returns zero on read 0 Highest Shadow Set This field contains the highest shadow set number that is implemented by this processor A value of zero in this field indicates that only the normal GPRs are implemented Possible values of this field for the 4KE processor Meaning One shadow set normal GPR set is present Two shadow sets are present Preset Four shadow sets are present Reserved The value in this field also represents the highest value that can be written to the ESS EICSS PSS and CSS fields of this register or to any of the fields of the SRSMap register The operation of the processor is UNDEFINED if a value larger than the one in this field is written to any of these other fields Must be written as zeros returns zero on read 0 EIC interrupt mode shadow set If Config3ygjc is 1 EIC interrupt mode is enabled this field is loaded from the external interrupt controller for each interrupt request and is used in place of the SRSMap register to select the current shadow set for the 21 18 interrupt Undefined See Section 4 3 1 3 External Interrupt Controller Mode on page 60 for a discussion of EIC interrupt mode If Config3yg c is 0 this field must be written as Zero and returns zero on read 0 EICSS 112 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 1
223. elds Read Name Bits Description Write Reset State R 7 5 Reserved This field is ignored on write and read as 0 R 0 This bit denotes the base operating mode of the processor See Section 3 2 Modes of Operation on page 34 for a full discussion of operating modes The encoding of this bit is Encoding Meaning UM 4 R W Undefined 1 Base mode is User Mode Note that the processor can also be in kernel mode if ERL or EXL is set regardless of the state of the UM bit R 3 This bit is reserved This bit is ignored on write and read R 0 as Zero Error Level Set by the processor when a Reset Soft Reset NMI or Cache Error exception are taken Normal level Error level When ERL is set The processor is running in kernel mode ERL 2 Interrupts are disabled R W l The ERET instruction will use the return address held in ErrorEPC instead of EPC The lower 27 bytes of kuseg are treated as an unmapped and uncached region See Chapter 3 Memory Management on page 34 This allows main memory to be accessed in the presence of cache errors The operation of the processor is UNDEFINED if the ERL bit is set while the processor is executing instructions from kuseg Exception Level Set by the processor when any exception other than Reset Soft Reset or NMI exceptions is taken Encoding Meaning 0 Normal level 1 Exception level EXL 1 When EXL is set R W Undefined
224. encies Instruction Sequence Size of Operand Latency 1st Instruction 1st Instruction 2nd Instruction Clocks MULT MULTU MADD MADDU 16 bit MADD MADDU or MSUB MSUBU or 1 MSUB MSUBU MFHI MFLO MULT MULTU MADD MADDU 32 bit MADD MADDU or MSUB MSUBU or 2 MSUB MSUBU MFHI MFLO 16 bit MUL Integer operation 2131 32 bit Integer operation 25 8 bit MFHI MFLO 9 16 bit MFHI MFLO 17 24 bit MFHI MFLO 25 32 bit DIVU MFHI MFLO 33 8 bit DIV MFHI MFLO 10141 16 bit DIV MFHI MFLO 18 4 24 bit DIV MFHI MFLO 264 32 bit DIV MFHI MFLO 34 4 any MFHI MFLO Integer operation 2 MADD MADDU or any MTHI MTLO MSUB MSUBU 1 Note 1 For multiply operations this is the rt operand For divide operations this is the rs operand Note 2 Integer Operation refers to any integer instruction that uses the result of a previous MDU operation Note 3 This does not include the 1 or 2 IU pipeline stalls 16 bit or 32 bit that the MUL operation causes irrespective of the following instruction These stalls do not add to the latency of 2 Note 4 If both operands are positive then the Sign Adjust stage is bypassed Latency is then the same as for DIVU In Table 2 1 a latency of one means that the first and second instructions can be issued back to back in the code without the MDU causing any stalls in the IU pipeline A latency of two means that if issued back to back the IU pipeline will be stalled fo
225. equirement in implementing hardware structures MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 97 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers 98 5 2 6 PageGrain Register CPO Register 5 Select 1 The PageGrain register is a read write register used for enabling 1KB page support It is used for reading from and writing to the TLB The contents of the PageGrain register are not reflected in the contents of the TLB therefore the TLB must be flushed before any change to the PageGrain register is made Behavior is UNDEFINED if a value other than those listed is used This register is only valid with the TLB 4KEc core It is reserved if the FM is implemented 4KEm and 4KEp Figure 5 6 PageGrain Register Format 31 29 28 27 0 0 ESP 0 Table 5 10 PageGrain Register Field Descriptions Reset State Meaning 1KB page support is not enabled 1KB page support is enabled If this bit is a 1 the following changes occur to coprocessor 0 registers The PFN field of the EntryLo0 and EntryLol registers holds the physical address down to bit 10 the field is ESP shifted left by 2 bits from the Release 1 definition 0 The MaskX field of the PageMask register is writable and is concatenated to the right of the Mask field to form the don t care mask for the TLB entry The VPN2X field of the EntryHi register is writable and bits 12
226. er 16 Select II 125 5 2 23 Config2 Register CPO Register 16 Select 2 enne ener enne nennen 127 5 2 24 Config3 Register CPO Register 16 Select 3 sese enne ener enne entree 128 5 2 25 Load Linked Address CPO Register 17 Select 0 essent nennen nennen 130 5 2 26 WatchLo Register CPO Register 18 Select 0 nennen nennen nennen 131 5 2 27 WatchHi Register CPO Register 19 Select O trennen ener nennen trennen 132 5 2 28 Debug Register CPO Register 23 Select 0 sessi eene retener nennen 133 5 2 29 Trace Control Register CPO Register 23 Select II 136 5 2 30 Trace Control2 Register CPO Register 23 Select 2 esses eene enne neeneee 139 5 2 31 User Trace Data Register CPO Register 23 Select 3 sss 141 5 2 32 TraceBPC Register CPO Register 23 Select 4 sse eene een enne 142 5 2 33 Debug Exception Program Counter Register CPO Register 24 Select 0 sess 143 5 2 34 ErrCtl Register CPO Register 26 Select 0 sss enne enne enne 144 5 2 35 TagLo Register CPO Register 28 Select 0 enne enne en enr nennen 145 5 2 36 DataLo Register CPO Register 28 Select 1 ener eene rete nreneen 146 5 2 37 ErrorEPC CPO Register 30 Select 0 eere ed ene erii petere p erred dete Pre ee e 147 5 2 38 DeSave Register CPO Register 31 Select 0 ener nennen nennen 148 Chapter 6 Hardware and Software Initialization eese eene nene
227. er debug mode via a debug mode exception This includes accesses usually causing a TLB exception 4KEc core only with the result that such accesses are not handled by the usual memory management routines The unmapped kseg0 and kseg1 segments from kernel mode address space are available from debug mode which allows the debug handler to be executed from uncached and unmapped memory Table 3 3 Physical Address and Cache Attributes for dseg dmseg and drseg Address Spaces Segment Sub Segment Name Virtual Address Generates Physical Address Name Cache Attribute OxFF20 0000 dmseg maps to addresses ae 0x0 0000 OxF FFFF in EJTAG OxFF2F FFFF probe memory space OxFF30 0000 drseg maps to the breakpoint through registers 0x0_0000 0xF_FFFF OxFF3F FFFF 3 2 4 1 Conditions and Behavior for Access to drseg EJTAG Registers Uncached The behavior of CPU access to the drseg address range at OXFF30 0000 to OXFF3F FFFF is determined as shown in Table 3 4 Table 3 4 CPU Access to drseg Address Range LSNM bit in Debug Transaction register Access Load Store 1 Kernel mode address space kseg3 Fetch Don t care drseg see comments below Load Store 0 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 41 Chapter 3 Memory Management Debug software is expected to read the debug control reg
228. er fields that can affect the mode Table 4 2 Interrupt Modes Statuspry Causeyy IntCtlys Config3yinr Config3ygic Interrupt Mode Compatibly n E gt lt Pal gt lt x 0 x x x Compatibility x x 0 x x Compatibility O 1 40 1 O Vectored Interrupt O 1 40 x 1 External Interrupt Controller Can t happen IntCtlys can not be non zero if neither O 1 40 O O Vectored Interrupt nor External Interrupt Controller mode is implemented x denotes don t care 4 3 1 1 Interrupt Compatibility Mode This is the default interrupt mode for the processor and is entered when a Reset exception occurs In this mode interrupts are non vectored and dispatched though exception vector offset 16 180 if Causeyy 0 or vector offset 1642200 if Causeyy 1 This mode is in effect if any of the following conditions are true e Causeqy 0 Statuspry l IntCtlys 0 which would be the case if vectored interrupts are not implemented or have been disabled A typical software handler for interrupt compatibility mode might look as follows Assumptions Cause 1 if it were zero the interrupt be isolated from the general exception vector before getting xception would have to here GPRs kO and kl are available no shadow register switches invoked in B compatibility mode The software priority is
229. eries of bits arranged to form a single scan path between TDI and TDO During an Instruction register scan operations the TAP controls the register to capture status information and shift data from TDI to TDO Both the capture and shift operations occur on the rising edge of TCK However the data shifted out from the TDO occurs on the falling edge of TCK In the Test Logic Reset and Capture IR state the instruction shift register is set to 00001 as for the IDCODE instruction This forces the device into the functional mode and selects the Device ID register The Instruction register is 5 bits wide The instruction shifted in takes effect for the following data register scan operation A list of the implemented instructions are listed in Table 9 20 9 4 2 Data Registers Overview The EJTAG uses several data registers which are arranged in parallel from the primary TDI input to the primary TDO output The Instruction register supplies the address that allows one of the data registers to be accessed during a data register scan operation During a data register scan operation the addressed scan register receives TAP control signals to capture the register and shift data from TDI to TDO During a data register scan operation the TAP selects the output of the data register to drive the TDO pin The register is updated in the Update DR state with respect to the write bits This description applies in general to the following data registers Bypass Regis
230. error DeSAVE2 Debug handler scratchpad register Note 1 Registers used in exception processing Note 2 Registers used in debug Note 3 Registers used in memory management MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 89 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers 5 2 CP0 Register Descriptions The CPO registers provide the interface between the ISA and the architecture Each register is discussed below with the registers presented in numerical order first by register number then by select field number For each register described below field descriptions include the read write properties of the field and the reset state of the field For the read write properties of the field the following notation is used Table 5 2 CPO Register Field Types Read Write Notation Hardware Interpretation Software Interpretation A field in which all bits are readable and writable by software and potentially by hardware Hardware updates of this field are visible by software reads Software updates of this field are R W visible by hardware reads If the reset state of this field is Undefined either software or hardware must initialize the value before the first read will return a predictable value This should not be confused with the formal definition of UNDEFINED behavior A field that is either static or is updated only by A f
231. es effect on the rising edge of TCK If TMS is sampled LOW at the rising edge of TCK the controller transitions to the Run Test Idle state A HIGH on TMS causes the controller to transition to the Select DR Scan state 9 3 3 Test Access Port TAP Instructions The TAP Instruction register allows instructions to be serially input into the device when TAP controller is in the Shift IR state Instructions are decoded and define the serial test data register path that is used to shift data between TDI and TDO during data register scanning The Instruction register is a 5 bit register In the current EJTAG implementation only some instructions have been decoded the unused instructions default to the BYPASS instruction Table 9 20 Implemented EJTAG Instructions Value Instruction Function 0x01 IDCODE Select Chip Identification data register 0x03 IMPCODE Select Implementation register 0x08 ADDRESS Select Address register 0x09 DATA Select Data register MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 191 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support 192 Table 9 20 Implemented EJTAG Instructions Continued Value Instruction Function 0x0A CONTROL Select EJTAG Control register 0x0B ALL Select the Address Data and EJTAG Control registers 0x0C EJTAGBOOT Set EjtagBrk ProbEn and ProbTrap to 1 as reset value 0x0D NORMALBOOT Set EjtagBrk
232. es in a short period of time The write buffer is organized as two 16 byte buffers Each buffer contains data from a single 16 byte aligned block of memory One buffer contains the data currently being transferred on the external interface while the other buffer contains accumulating data from the core 1 2 1 7 Power Management The core offers a number of power management features including low power design active power management and power down modes of operation The core is a static design that supports a WAIT instruction designed to signal the rest of the device that execution and clocking should be halted hence reducing system power consumption during idle periods The core provides two mechanisms for system level low power support Register controlled power management nstruction controlled power management In register controlled power management mode the core provides three bits in the CPO Status register for software control of the power management function and allows interrupts to be serviced even when the core is in power down mode In instruction controlled power down mode execution of the WAIT instruction is used to invoke low power mode Refer to Chapter 8 Power Management on page 163 for more information on power management 1 2 2 Optional Logic Blocks The core consists of the following optional logic blocks as shown in the block diagram in Figure 1 1 on page 5 1 2 2 1 MIPS16e Application Specific Extension
233. eserved 11 3 MIPS32 Instruction Set for the 4KE core Table 11 10 Instruction Set Continued MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc Instruction Description Function PC Rs JR HB Jump Register with Hazard Barrier Stall until all execution and instruction hazards are cleared LB Load Byte Rt byte Mem Rs offset LBU Unsigned Load Byte Rt ubyte Mem Rs offset LH Load Halfword Rt half Mem Rs offset LHU Unsigned Load Halfword Rt uhalf Mem Rs offset Rt Mem Rs offset LL Load Linked Word LL 1 LLAdr Rs offset LUI Load Upper Immediate Rt immediate lt lt 16 LW Load Word Rt Mem Rs offset LWC2 Load Word To Coprocessor 2 CPR 2 n 0 Mem Rs offset LWL Load Word Left See LWL instruction below LWR Load Word Right See LWR instruction below MADD Multiply Add HI LO int Rs int Rt MADDU Multiply Add Unsigned HI LO uns Rs uns Rt MFCO Move From Coprocessor 0 Rt CPR O n sel MFC2 Move From Coprocessor 2 Rt CPR 2 n sels ol MFHC2 Move From High Word Coprocessor2 Rt CPR 2 n sel ga 55 MFHI Move From HI Rd HI MFLO Move From LO Rd LO MOVN Move Conditional on Not Zero E T GERD s MOVZ Move Conditional on Zero GERI PRI s MSUB Multiply Subtract HI LO int Rs int Rt MSUBU Multiply Subtract Unsigned HI LO uns Rs uns Rt MTCO Move To Copr
234. esses on page 203 Section 9 7 EJTAG Trace on page 204 Section 9 8 PDtrace Registers software control on page 208 Section 9 9 Trace Control Block TCB Registers hardware control on page 209 Section 9 10 EJTAG Trace Enabling on page 223 Section 9 11 TCB Trigger logic on page 225 Section 9 12 EJTAG Trace cycle by cycle behavior on page 228 Section 9 13 TCB On Chip Trace Memory on page 230 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 165 Chapter 9 EJTAG Debug Support 9 1 Debug Control Register 166 The Debug Control Register DCR register controls and provides information about debug issues and is always provided with the CPU core The register is memory mapped in drseg at offset 0x0 The DataBrk and InstBrk bits indicate if hardware breakpoints are included in the implementation and debug software is expected to read hardware breakpoint registers for additional information Hardware and software interrupts are maskable for non debug mode with the INTE bit which works in addition to the other mechanisms for interrupt masking and enabling NMI is maskable in non debug mode with the NMIE bit and a pending NMI is indicated through the NMIP bit The SRE bit allows implementation dependent masking of none some or all sources for soft reset The soft reset masking may only be applied to a soft reset source if t
235. except interrupt if masked by IE EPC STATUS ERET is not allowed in the branch delay slot of another Jump Instruction Processor does not execute the instruction ERET which is in the ERET s branch delay slot PC EPC EXL 0 LLbit 0 Figure 4 4 General Exception Servicing Guidelines SW MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 83 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 4 Exceptions and Interrupts 84 EntryHi VPN2 ASID Context VPN2 Set Cause EXCCode CE BadVA VA Check if exception within another exception EPC PC EPC lt PC 4 Cause BD 0 Cause BD lt 1 Vec Off 0x000 Vec Off 0x180 Points to General Exception Processor forced to Kernel Mode amp interrupt disabled 0 normal 1 bootstrap PC OxBFC0_0200 Vec Off unmapped uncached PC lt 0x8000_0000 Vec Off unmapped cached To TLB Exception Servicing Guidelines Figure 4 5 TLB Miss Exception Handler HW 4KEc Core MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 4 9 Exception Handling and Servicing Flowcharts MFCO CONTEXT l Service Code l ERET Comments Unmapped v
236. exists either off chip or on chip only MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Preset 215 Chapter 9 EJTAG Debug Support Fields Table 9 30 TCBCONTROLB Register Field Descriptions Continued Name Bits Description Read Write Reset State EN Enable trace This is the master enable for trace to be generated from the TCB This bit can be set or cleared either by writing this register or from a start stop about trigger When set to 1 trace information is sampled on the PDO pins Trace Words are generated and sent to either on chip memory or to the Trace Probe The target of the trace is selected by the OfC bit When set to 0 trace information on the PDO_ pins is ignored A potential TF6 stop from a stop trigger is generated as the last information the TCB pipe line is flushed and trace output is stopped Table 9 31 Clock Ratio encoding of the CR field CR CRMin CRMax Clock Ratio 000 001 010 2 1 Trace clock is double that of core clock 8 1 Trace clock is eight times that of core clock 4 1 Trace clock is four times that of core clock 011 1 1 Trace clock is same as core clock 100 1 2 Trace clock is one half of core clock 101 110 111 9 9 3 TCBDATA Register 1 4 Trace clock is one fourth of core cloc
237. extensively it should be retained in the cache Action Fetch data as if for a store and place it in the cache so that it is not displaced by data prefetched as streamed MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved PREF 257 258 Table 11 16 Values of the hint Field for the PREF Instruction 8 24 Reserved Reserved treated as a NOP Use Data is no longer expected to be used 25 E cu iae Si Action Schedule a writeback of any dirty data The cache line is are nov Tides nuage marked as invalid upon completion of the writeback If cache line is clean or locked no action is taken 26 29 Reserved Reserved treated as a NOP EE Use Prepare the cache for writing an entire line without the 30 P overhead involved in filling the line from memory Reserved treated as a NOP 31 Reserved Reserved treated as a NOP MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Prefetch cont PREF Restrictions None Operation vAddr GPR base sign extend offset pAddr CCA zc AddressTranslation vAddr DATA LOAD Prefetch CCA pAddr vAddr DATA hint Exceptions Prefetch does not take any TLB related or address related exceptions under any circumstances Programming Notes Prefetch cann
238. ffers however there could be a delay in how long it takes for the write to memory to actually occur If another memory master updates cacheable memory which could also be in the 4KE caches then those locations may need to be flushed from the cache The only way to accomplish this invalidation is by use of the CACHE instruction In write back mode data writes only go to the cache and not to memory So the processor cache may contain the only copy of data in the system until that data is written to main memory Dirty lines are only written to memory when displaced from the cache as a new line is filled or if explicitly forced by certain flavors of the CACHE or PREF instructions The SYNC instruction may also be useful to software enforcing memory coherence as it flushes the 4KE core s write buffers MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 161 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 7 Caches 162 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 8 Power Management A MIPS32 4KE processor core offers a number of power management features including low power design active power management and power down modes of operation The core is a static design that supports a WAIT instruction designed to signal the rest of the device that execution and clocking should be halt
239. for Vector Number 7 Shadow register set number for Vector Number 6 Shadow register set number for Vector Number 5 0 Shadow register set number for Vector Number 4 0 SSV3 15 12 Shadow register set number for Vector Number 3 nu 0 SSV2 Shadow register set number for Vector Number 2 1 8 SSVI 7 4 Shadow register set number for Vector Number 1 dE SSVO 3 0 Shadow register set number for Vector Number 0 0 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 115 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers 5 2 17 Cause Register CPO Register 13 Select 0 The Cause register primarily describes the cause of the most recent exception In addition fields also control software interrupt requests and the vector through which interrupts are dispatched With the exception of the IP 9 DC IV and WP fields all fields in the Cause register are read only Release 2 of the Architecture added optional support for an External Interrupt Controller EIC interrupt mode in which IP are interpreted as the Requested Interrupt Priority Level RIPL Figure 5 18 shows the format of the Cause register Table 5 22 describes the Cause register fields Figure 5 18 Cause Register Format 3130 29 2827 26 25 24 23 22 21 16 15 10 9 8 7 6 2 1 0 BDTI CE DCPCY 0 IV WP 0 IP7 IP2 IP1 IPO 0 Exc Code 0 RIPL
240. for disabling the breakpoint when returning to the instruction otherwise the debug instruction break exception reoccurs 9 2 6 2 Debug Exception by Data Breakpoint If the breakpoint is enabled by BE bit in the DBCn register then a debug exception occurs when the DB match condition is true The corresponding BS n bit in the DBS register is set when the breakpoint generates the debug exception A debug data break exception occurs when a data breakpoint indicates a match In this case the DEPC register and DBD bit in the Debug register points to the instruction that caused the DB match equation to be true The instruction causing the debug data break exception does not update any registers due to the instruction and the following applies to the load or store transaction causing the debug exception A store transaction is not allowed to complete the store to the memory system e A load transaction with no data value compare i e where the DB no value compare is true for the match is not allowed to complete the load A load transaction for a breakpoint with data value compare must occur from the memory system since the value is required in order to evaluate the breakpoint MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 171 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support The result of this is that the load or store instruction causing the debug data break exce
241. from HI LO and CP0 Delay As indicated in Figure 2 17 not only load data but also data moved from the HI or LO registers MFHI MFLO and data moved from CPO MFCO enters the IU Pipeline in the A stage That is data is not available in the integer pipeline until early in the A stage The A to E bypass is available for this data But as for Loads an instruction following immediately after one of these move instructions must be paused for one cycle if the target of the move is among the sources of that following instruction This then causes an interlock slip in the E stage see Section 2 12 Instruction Interlocks on page 27 An interlock slip after a MFHI is illustrated in Figure 2 20 One Cycle MFHI to R3 One Cycle E One Cycle M One Cycle A One Cycle W One Cycle ADD R4 R3 R5 Figure 2 20 IU Pipeline Slip after a MFHI 2 9 Coprocessor 2 instructions E slip Data bypass from A to E One Cycle If a coprocessor 2 is attached to the 4KE core a number of transactions has to take place on the CP2 Interface for each coprocessor 2 instruction First of all if the CU 2 bit in the CPO Status register is not set then no coprocessor 2 related instruction will start a transaction on the CP2 Interface Rather a Coprocessor Unusable exception will signaled If the CU 2 bit is set and a coprocessor 2 instruction is fetched the following transactions will occur on the C
242. ft Multiply Divide These operations fit in the following four categories of computational instructions ALU Immediate instructions Three operand Register type Instructions Shift Instructions Multiply And Divide Instructions MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 233 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 10 Instruction Set Overview 10 3 1 Cycle Timing for Multiply and Divide Instructions Any multiply instruction in the integer pipeline is transferred to the multiplier as remaining instructions continue through the pipeline the product of the multiply instruction is saved in the HI and LO registers If the multiply instruction is followed by an MFHI or MFLO before the product is available the pipeline interlocks until this product does become available Refer to Chapter 2 Pipeline on page 11 for more information on instruction latency and repeat rates 10 4 Jump and Branch Instructions Jump and branch instructions change the control flow of a program All jump and branch instructions occur with a delay of one instruction that is the instruction immediately following the jump or branch this is known as the instruction in the delay slot always executes while the target instruction is being fetched from storage 10 4 1 Overview of Jump Instructions Subroutine calls in high level languages are usually implemented with Jump or Jump
243. ft HI LO Write Reo wR Figure 2 13 4KEp MDU Pipeline Flow During a Multiply Operation 2 6 2 Multiply Accumulate 4KEp Core Multiply accumulate operations use the same multiply machine as used for multiply only Two extra stages are needed to perform the addition subtraction The operations uses 34 cycles in Mun stage to complete the multiply accumulate The register writeback to HI and LO are done in the A stage Figure 2 14 shows the latency for a multiply accumulate operation The repeat rate is 35 cycles as a second multiply accumulate can be in the E stage when the first multiply is in the last Mur stage Clock 1 2 33 34 35 36 37 KN E Stage J Mypy Stage lt Munu Stage lt Mypy Stage Ka Ampu Stage Wun Stage gt per gu e cp qp he Add Subtract Shift Accumulate LO Accumulate HI HI LO Write Figure 2 14 4KEp MDU Pipeline Flow During a Multiply Accumulate Operation 2 6 3 Divide 4KEp Core Divide operations also implement a simple non restoring algorithm This algorithm works only for positive operands hence the first cycle of the Mun stage is used to negate the rs operand RS Adjust if needed Note that this cycle is executed even if negation is not needed The next 32 cycle 3 34 executes an interactive add subtract shift function Two sign adjust Sign Adjust 1 2 cycles are used to change the sign of one or both the quotient and the remainder Note that one or both of these cycles
244. g to the byte index into the DataLo register Yes Update the SPRAM tag at the specified index Indes Store Tag from the TagLo Coprocessor 0 register Xes Write the DataLo Coprocessor 0 register Index Store Data contents into the SPRAM at the word index Yes specified All All All of the other codes behave the same as when Others ErrCtl SPR is cleared 252 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Perform Cache Operation cont CACHE Restrictions The operation of this instruction is UNDEFINED for any operation cache combination that is not implemented The operation of this instruction is UNDEFINED if the operaation requires an address and that address is uncache able If access to Coprocessor 0 is not enabled a Coprocessor Unusable Exception is signaled Operation vAddr GPR base sign extend offset pAddr uncached lt AddressTranslation vAddr DataReadReference CacheOp op vAddr pAddr Exceptions TLB Refill Exception TLB Invalid Exception Coprocessor Unusable Exception Address Error Exception Bus Error Exception MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 253 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Load Linked Word LL 31 26 25 21 20 16 15 0 LL base rt offset 110000 6 5 5 16 Format LL rt offset base
245. get address These will have full delta PC values included in the trace information Also treated as unpredictable are PC changes which occur due to exceptions such as an interrupt reset etc Trace regeneration software is required to know the static program image in memory in order to reproduce the dynamic flow with the above information But this is usually not a problem Only the virtual value of the PC is used Physical memory location will typically differ Itis possible to turn on PC delta full information for all branches but this should not normally be necessary As a safety check for trace regeneration software a periodic synchronization with a full PC is sent The period of this synchronization is cycle based and programmable 9 7 4 Load Store address and data trace information 206 In addition to PC flow itis possible to get information on the load store addresses as well as the data read written When enabled the following information is optionally added to the trace When load address tracing is on the full load address of the first load instruction is traced indicated by the load flag For subsequent loads a dynamically determined delta to the previous load address is traced to compress the information which must be sent When store address tracing is on the full store address of the first store instruction is traced indicated by the store flag For subsequent stores a dynamically determined delta to the previous
246. ght 2000 2002 MIPS Technologies Inc All rights reserved 3 3 Translation Lookaside Buffer 4KEc Core Only The JTLB is organized in pairs of page entries to minimize its overall size Each virtual tag entry corresponds to two physical data entries an even page entry and an odd page entry The highest order virtual address bit not participating in the tag comparison is used to determine which of the two data entries is used Since page size can vary on a page pair basis the determination of which address bits participate in the comparison and which bit is used to make the even odd selection must be done dynamically during the TLB lookup Figure 3 7 on page 43 shows the contents of one of the 16 dual entries in the JTLB The bit range indication in the figure serves to clarify which address bits are or may be affected during the translation process PageMask 28 11 Tag Entry VPN2 31 13 VPN2X 12 11 ASID 7 0 19 1 8 PFNO 31 12 or 29 10 CO 2 0 po Data Entries PFN1 31 12 or 29 10 C1 2 0 20 3 1 1 Figure 3 7 JTLB Entry Tag and Data Table 3 6 and Table 3 7 explain each of the fields in a JTLB entry Table 3 6 TLB Tag Entry Fields Field Name Description Page Mask Value The Page Mask defines the page size by masking the appropriate VPN2 bits from being involved in a comparison It is also used to determine which address bit is used to make the even odd page PFNO PFN1 determinatio
247. gister CPO Register 31 Select 0 The Debug Exception Save DeSave register is a read write register that functions as a simple memory location This register is used by the debug exception handler to save one of the GPRs that is then used to save the rest of the context to a pre determined memory area such as in the EJTAG Probe This register allows the safe debugging of exception handlers and other types of code where the existence of a valid stack for context saving cannot be assumed Figure 5 40 DeSave Register Format 31 0 DESAVE Table 5 44 DeSave Register Field Description Fields Name Bit s Description Reset State DESAVE 31 0 Debug exception save contents Undefined 148 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 6 Hardware and Software Initialization A MIPS32 4KE processor core contains only a minimal amount of hardware initialization and relies on software to fully initialize the device This chapter contains the following sections Section 6 1 Hardware Initialized Processor State Section 6 2 Software Initialized Processor State 6 1 Hardware Initialized Processor State A 4KE processor core like most other MIPS processors is not fully initialized by hardware reset Only a minimal subset of the processor state is cleared This is enough to bring the core up while runn
248. gister ExcCode Value Bp Additional State Saved None Entry Vector Used General exception vector offset 0x180 4 8 17 Execution Exception Reserved Instruction The reserved instruction exception is one of the nine execution exceptions All of these exceptions have the same priority A reserved instruction exception occurs when a reserved or undefined major opcode or function field is executed This includes Coprocessor 2 instructions which are decoded reserved in the Coprocessor 2 Cause Register ExcCode Value RI MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 77 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 4 Exceptions and Interrupts Additional State Saved None Entry Vector Used General exception vector offset 0x180 4 8 18 Execution Exception Coprocessor Unusable The coprocessor unusable exception is one of the nine execution exceptions All of these exceptions have the same priority A coprocessor unusable exception occurs when an attempt is made to execute a coprocessor instruction for one of the following e a corresponding coprocessor unit that has not been marked usable by setting its CU bit in the Status register CPO instructions when the unit has not been marked usable and the processor is executing in user mode Cause Register ExcCode Value CpU Additional State Saved Table 4 15 Register States on a Coprocessor Unusable Exceptio
249. gister pair The 32 bit word value in the GPR rs is multiplied by the 32 bit value in the GPR rt treating both operands as signed values to produce a 64 bit result The product is added to the 64 bit concatenated values in the HI and LO register pair The resulting value is then written back to the HI and LO registers No arithmetic exception occurs under any circumstances 10 7 4 MADDU Multiply and Add Unsigned Word The MADDU instruction multiplies two unsigned words and adds the result to the HI LO register pair The 32 bit word value in the GPR rs is multiplied by the 32 bit value in the GPR rt treating both operands as unsigned values to produce a 64 bit result The product is added to the 64 bit concatenated values in the HI and LO register pair The resulting value is then written back to the HI and LO registers No arithmetic exception occurs under any conditions 10 7 5 MSUB Multiply and Subtract Word The MSUB instruction multiplies two words and subtracts the result from the HI LO register pair The 32 bit word value in the GPR rs is multiplied by the 32 bit value in the GPR rt treating both operands as signed values to produce a 64 bit result The product is subtracted from the 64 bit concatenated values in the HI and LO register pair The resulting value is then written back to the HI and LO registers No arithmetic exception occurs under any circumstances MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 2
250. gnals Tracing can be controlled via software with the TraceControl register in a similar manner 9 10 3 Turning Off PDtrace Trace 224 Trace is turned off when the following expression evaluates true TIraceControl g and not TraceControlg and not TraceControlg s and not TCBCONTROLAg not MatchEnable and not TriggerEnable and MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 11 TCB Trigger logic TriggerDisable where TriggerDisable lt DBCizg and DBSps 1 and TraceBPCpg and IraceBPCpgpon 9 or IBCirg and IBSps i and TraceBPCy and TraceBPCrpponti 9 Tracing can be unconditionally turned off by de asserting the TraceControlo bit or the TCBCONTROLAg signal When either of these are asserted tracing can be turned off if all of the enables are de asserted irrespective of the TraceControlg bit T CBCONTROLAG and TraceControl om TCBCONTROLA a sjp values EJTAG hardware breakpoints can be used to trigger trace off as well Note that if simultaneous triggers are generated and even one of them turns on tracing then even if all of the others attempt to trigger trace off then tracing will still be turned on This condition is reflected in presence of the not TriggerEnable term in the expression above 9 10 4 TCB Trace Enabling The TCB must be enabled in order
251. gning the interrupt controller to provide the correct GPR shadow set number when an interrupt is requested When the processor loads an interrupt request into Cause it also loads the GPR shadow set number into SRSCtlgjcss which is copied to SRSCtlcgg when the interrupt is serviced The operation of EIC interrupt mode is shown pictorially in Figure 4 2 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 61 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 4 Exceptions and Interrupts 62 Encode Latch Compare Any Causey Request Causepcy E RIPL 2 Statusp IPL Statusgg Statuspypg Generator Generate Interrupt je gt EE Requgst nterrupt Exception Exception Vector Offset ite Shadow Set S Interrupt Service P CS Started E a Load IntCtl o ntCt Y O Gen 9 3 Requested z Vector 2 2 IPL amp Number 9 5 2 p Es 3 5 5 z S S 5 E x E S 2 z a x S 0d a Number zl 7 Ki n Figure 4 2 Interrupt Generation for External Interrupt Controller Interrupt Mode A typical software handler for EIC interrupt mode bypasses the entire sequence of code following the IVexception label shown for the compatibility mode handler above Instead the hardware performs the prioritization dispatching directly to the interrupt proce
252. hat source can be efficiently masked in the system thus resulting in no reset at all If that is not possible then that soft reset source should not be masked since a partial soft reset may cause the system to fail or hang There is no automatic indication of whether the SRE is effective so the user must consult system documentation The PE bit reflects the ProbEn bit from the EJTAG Control register ECR whereby the probe can indicate to the debug software running on the CPU if the probe expects to service dmseg accesses The reset value in the table below takes effect on both hard and soft resets Debug Control Register 3130 29 28 18 17 16 15 5 4 3 2 1 0 Res ENM Res DB IB Res INTE NMIE NMIP SRE PE Table 9 1 Debug Control Register Field Descriptions Fields Name Reset State Res 0 Endianess in Kernel and Debug mode ENM 29 0 Little Endian Preset 1 Big Endian Res 28 18 Reserved 0 Data Break Implemented DB 17 0 No Data Break feature implemented Preset 1 Data Break feature is implemented Instruction Break Implemented is 16 0 No Instruction Break feature implemented Preset 1 Instruction Break feature is implemented Res 15 5 Reserved 0 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 1 Debug Control Register Table 9 1 Debug Control Register Field Descriptions Continued Fields Name Desc
253. he Multiply Divide unit performs multiply and divide operations In the 4KEc and 4KEm processors the MDU consists of a 32x16 booth encoded multiplier result accumulation registers HI and LO multiply and divide state machines and MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 5 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 1 Introduction to the MIPS32 4KE Processor Core Family all multiplexers and control logic required to perform these functions This pipelined MDU supports execution of a 16x16 or 32x16 multiply operation every clock cycle 32x32 multiply operations can be issued every other clock cycle Appropriate interlocks are implemented to stall the issue of back to back 32x32 multiply operations Divide operations are implemented with a simple 1 bit per clock iterative algorithm and require 35 clock cycles in worst case to complete Early in to the algorithm detects sign extension of the dividend if it is actual size is 24 16 or 8 bit the divider will skip 7 15 or 23 of the 32 iterations An attempt to issue a subsequent MDU instruction while a divide is still active causes a pipeline stall until the divide operation is completed The area efficient non pipelined MDU in the 4KEp core consists of a 32 bit full adder result accumulation registers HI and LO a combined multiply divide state machine and all multiplexers and control logic required to perform these functio
254. he TagLo register are used as the source and destination for Index Load Tag and Index Store Tag CACHE operations The WST bit also enables the data RAM test mode When this bit is set the Index Store Data CACHE instruction is enabled This CACHE operation writes the contents of the DataLo register to the word in the data array that is indicated by the index and byte address The SPR bit enables CACHE accesses to the optional Scratchpad RAMs When this bit is set Index Load Tag Index Store Tag and Index Store Data CACHE instructions will send reads or writes to the Scratchpad RAM port The effects of these operations are dependent on the particular Scratchpad implementation Figure 5 36 ErrCtl Register Format 3130 29 28 27 0 R WST SPR R Table 5 40 ErrCtl Register Field Descriptions Fields Name Description Reset State Indicates whether the tag array or the way select array should be read written on Index Load Store Tag CACHE instructions Also enables the Index Store Data CACHE instruction which writes the contents of DataLo to the data array Forces indexed CACHE instructions to operate on the ScratchPad RAM instead of the cache R p Must be written as zero returns zero on reads 0 0 144 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions 5 2 35 TagLo Register CP0 Regi
255. he appropriate range Almost the same protocol is used to execute a store instruction to the EJTAG Probe s memory through dmseg The store address must be in the range 0xFF20 0000 to OxFF2F FFFF the ProbEn bit must be set and the processor has to be in debug mode DM 1 The sequence of actions is found below 1 The internal hardware latches the requested address into the PA Address register 2 The internal hardware latches the data to be written into the PA Data register 3 The internal hardware sets the following bits in the EJTAG Control register PrAcc 1 selects Processor Access operation PRnW 1 selects processor write operation Psz 1 0 value depending on the transfer size 4 The EJTAG Probe selects the EJTAG Control register shifts out this control register s data and tests the PrAcc status bit Processor Access when the PrAcc bit is found 1 it means that the requested address is available and can be shifted out The EJTAG Probe checks the PRnW bit to determine the required access The EJTAG Probe selects the PA Address register and shifts out the requested address The EJTAG Probe selects the PA Data register and shifts out the data to be written 9o zl Iv 0A The EJTAG Probe selects the EJTAG Control register and shifts a PrAcc 0 bit into this register to indicate to the processor that the write access is finished 9 The EJTAG Probe writes the data to the requested address in its memory 10 The processor de
256. he line contains modified data When a line with dirty data is displaced from the cache it is written back to memory Write through with no write allocation Loads and instruction fetches first search the cache reading main memory only if the desired data does not reside in the cache On data store operations the cache is first searched to see if the target address is cache resident If it is resident the cache contents are updated and main memory is also written If the cache lookup misses on a store only main memory is written Hence the allocation policy on a cache miss is read allocate only Write through with write allocation Loads and instruction fetches first search the cache reading main memory only if the desired data does not reside in the cache On data store operations the cache is first searched to see if the target address is cache resident If it is resident the cache contents are updated and main memory is also written If the cache lookup misses on a store main memory is read to bring the line into the cache and merge it with the new store data In addition the store data is also written to main memory Hence the allocation policy on a cache miss is read or write allocate Some segments of memory employ a fixed caching policy for example the kseg1 is always uncacheable Other segments of memory allow the caching policy to be selected by software Generally the cache policy for these programmable regions is defined by
257. hen set this enables tracing when the On bit is set and the core is in Kernel mode Unlike the usual definition of Kernel Mode this bit enables tracing only when the ERL and EXL bits in the Status register are zero This is provided the On bit R W E i bit 0 is also set and either the G bit is set or the current Undefined process ASID matches the ASID field in this register This field defines the value on the PDI K signal When set this enables tracing when the core is in User mode as defined in the MIPS32 or MIPS64 architecture specification This is provided the On bit bit 0 is also set and U 13 either the G bit is set or the current process ASID matches the R W Undefined ASID field in this register This field defines the value on the PDI U signal The ASID field to match when the G bit is zero When the G bit is one this field is ignored ASID 12 5 R W Undefined On 4KEm and 4KEp cores this field is ignored This field defines the value on the PDI ASID signal When set this implies that tracing is to be enabled for all processes provided that other enabling functions like U S etc are also true G 4 On 4KEm and 4KEp cores this field is ignored R W Undefined This field defines the value on the PDI G signal MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 211 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support Table 9 29
258. his section should help clarify the enabling of trace 9 10 1 Trace Trigger from EJTAG Hardware Instruction Data Breakpoints If hardware instruction data simple breakpoints are implemented in the 4KE core then these breakpoint can be used as triggers to start stop trace When used for this the breakpoints need not also generate a debug exception but are capable of only generating an internal trigger to the trace logic This is done by only setting the TE bit and not the BE bit in the Breakpoint Control register Please see Section 9 2 8 5 Instruction Breakpoint Control n IBCn Register on page 178 and Section 9 2 9 5 Data Breakpoint Control n DBCn Register on page 184 for details on breakpoint control In connection with the breakpoints the Trace BreakPoint Control TraceBPC register is used to define the trace action when a trigger happens When a breakpoint is enabled as a trigger TE 1 it can be selected to be either a start or a stop trigger to the trace logic Please see Section 5 2 32 TraceBPC Register CPO Register 23 Select 4 on page 142 for detail in how to define a start stop trigger 9 10 2 Turning On PDtrace Trace Trace enabling and disabling from software is similar to the hardware method with the exception that the bits in the control register are used instead of the input enable signals from the TCB The TraceControlTs bit controls whether hardware via the TCB or software via the TraceControl register co
259. hitecture Reference Manual by describing instruction behavior that is specific to a MIPS32 4KE processor core The chapter is divided into the following sections Section 11 1 Understanding the Instruction Descriptions on page 237 Section 11 2 MIPS32 4KE Opcode Map on page 237 e Section 11 3 MIPS32 Instruction Set for the 4KE core on page 240 The 4KE processor core also supports the MIPS16 ASE to the MIPS32 architecture The MIPS16 ASE instruction set is described in Chapter 12 MIPS16 Application Specific Extension to the MIPS32 Instruction Set on page 273 11 1 Understanding the Instruction Descriptions Refer to Volume II of the MIPS32 Architecture Reference Manual for more information about the instruction descriptions There is a description of the instruction fields definition of terms and a description function notation available in that document 11 2 MIPS32 4KE Opcode Map Key CAPITALIZED text indicates an opcode mnemonic Italicized text indicates to look at the specified opcode submap for further instruction bit decode Entries containing the amp symbol indicate that a reserved instruction fault occurs if the core executes this instruction Entries containing the D symbol indicate that a coprocessor unusable exception occurs if the core executes this instruction Table 11 1 Encoding of the Opcode Field opcode bits 28 26 bits 31 29 0 000 Special 1 001 ADDI
260. however be enabled to transmit the trace information to the Trace probe or to on chip trace memory by having the TCBCONTROLB gy bit set It is possible to enable and disable the TCB in two ways Set clear the TCBCONTROLByw bit via an EJTAG TAP operation Initialize a TCB trigger to set clear the TCBCONTROLBgn bit MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 207 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support 9 7 8 TCB Trigger The TCB can optionally include 0 to 8 triggers A TCB trigger can be programmed to fire from any combination of Probe Trigger Input to the TCB Chip level Trigger Input to the TCB Processor entry into DebugMode When a trigger fires it can be programmed to have any combination of actions Create Probe Trigger Output from TCB Create Chip level Trigger Output from TCB Set clear or start countdown to clear the TCBCONTROLB gy bit start end about trigger e Put an information byte into the trace stream 9 7 9 Cycle by cycle information All of the trace information listed in Section 9 7 3 Trace information and Section 9 7 4 Load Store address and data trace information will be collected from the PDtrace interface by the TCB The trace will then be compressed and aligned to fit in 64 bit trace words with no loss of information It is possible to exclude include the exact cycle by cycle relationship betwee
261. idelines SW Soft Reset Service Code Reset Service Code i l Reset Soft Reset amp NMI Servicing aa UE ee S65 45S Se Sa Ane eee ae Se ee Optional Figure 4 7 Reset Soft Reset and NMI Exception Handling and Servicing Guidelines 86 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers The System Control Coprocessor CPO provides the register interface to the MIPS32 4KE processor core and supports memory management address translation exception handling and other privileged operations Each CPO register has a unique number that identifies it this number is referred to as the register number For instance the PageMask register is register number 5 For more information on the EJTAG registers refer to Chapter 9 EJTAG Debug Support After updating a CPO register there is a hazard period of zero or more instructions from the update instruction MTCO and until the effect of the update has taken place in the core Refer to Chapter 11 MIPS32TM 4KE Processor Core Instructions for further details on CPO hazards The current chapter contains the following sections Section 5 1 CPO Register Summary on page 88 Section 5 2 CPO Register Descriptions on page 90 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 87 Copyright 2000 2002 MIPS Technologies Inc A
262. ield seeeeeeseseseeeee nennen nne nennen eere ene 275 Table 12 8 MIPS16 RR Encoding of the Funct bel 275 Table 12 9 MIPS16 I8 Encoding of the s Field when funct SVRS A 275 Table 12 10 MIPS16 RR Encoding of the ry Field when funct J AL R C esee enne 275 Table 12 11 Table 12 12 Table 12 13 Table 12 14 Table 12 15 Table 12 16 Table 12 17 Table 12 18 Table 12 19 MIPS16 RR Encoding of the ry Field when funct CNVT sees nne nnne enne 275 MIPS16 Load and Store Instructions eeseseseseeeeeeeeeeeeeeene enne ennt netten E netten nennen nnne 275 MIPS16 Save and Restore Instructnong a a tenen tenente terere nnne 276 MIPS16 ALU Immediate Instructions 0 eee eeseeenceesreesseceseecesecesaececceceaeeenceeseeeeseceseeceueeenaeceneeceeeeneeees 276 MIPS16 Arithmetic Two or Three Operand Register Instructions eee ceseeeeseeesceeeeeeeeeeeeeseneeeeeeneeaee 276 MIPS16 Special Instructions creed rte ente ceret Ter ertet eee ete Ie eee eS Eae Eo ee ESEE EE AUERS 277 MIPS16 Multiply and Divide Instructons sees ener 277 MIPS16 Jump and Branch Instructions 20 00 eee ee eeeeceeeeeseescecseescecsecsaecsecsaesecseseeceseeeseeeeseseaeeseseneeags 277 ZzMIPBSI6 Shift InstF CtiODS x 4er case eee e e e Pcr E a a Re dete pete d euh degt 278 Table A I Revision History t eee ede tre eiii te tee dete leo ied 279 MIPS32 4KE Processor Cores Softwa
263. ield to which the value written by software hardware is ignored by hardware Software may write If the Reset State of this field is either 0 or any value to this field without affecting Preset hardware initializes this field to zero hardware behavior Software reads of this field return the last value updated by hardware R or to the appropriate state respectively on BEE If the Reset State of this field is Undefined If the Reset State of this field is Undefined software reads of this field result in an hardware updates this field only under those UNPREDICTABLE value except after a ei ad e hardware update done under the conditions M specified in the description of the specified in the description of the field A field that can be written by software but which can not be read by software Software reads of this field will return an UNDEFINED value A field to which the value written by software must be zero Software writes of non zero values to this field may resultin UNDEFINED behavior of the hardware Software reads of 0 A field that hardware does not update and for this field return zero as long as all previous which hardware can assume a zero value software writes are zero If the Reset State of this field is Undefined software must write this field with zero before it is guaranteed to read as zero 90 MIPS32 4KE Processor Cores Software User s Manual Revisi
264. ified and so on The second way to turn on tracing the TriggerEnable expression is from the processor side using the EJTAG hardware breakpoint triggers If EJTAG is implemented and hardware breakpoints can be set then using this method enables finer grain tracing control It is possible to send a trigger signal that turns on tracing at a particular instruction For example it would be possible to trace a single procedure in a program by triggering on trace at the first instruction and triggering off trace at the last instruction The easiest way to unconditionally turn on trace is to assert either hardware or software tracing and the corresponding trace on signal with other enables For example with TraceControlys 0 i e hardware controlled tracing assert TCBCONTROLAQ TCBCONTROLAg and all the other signals in the second part of expression MatchEnable To only trace when a particular process with a known ASID is executing assert TCBCONTROLAo the correct TCBCONTROLA ggyp Value and all of TCBCONTROLAy TCBCONTROLA TCBCONTROLAg and TCBCONTROLApy If it is known that the particular process is a user level process then it would be sufficient to only assert TCBCONTROLAy for example When using the EJTAG hardware triggers to turn trace on and off it is best if TCBCONTROLAg is asserted and all the other processor mode selection bits in TCBCONTROLA are turned off This would be the least confusing way to control tracing with the trigger si
265. in software Instruction and data micro TLBs in the 4KEc are now 4 entries previously 3 Added support for 64KB maximum cache sizes February 16 2001 Added support for write through with write allocate cache policy Enhanced description of PrID revision field Added discussion about virtual aliasing in the caches Removed extraneous reference to Supervisor mode in Table 11 1 on page 191 since Supervisor mode is not supported Standardized links to major sections in each chapter Added SimpleBE amp UDI config bits Cleaned up description March 27 2001 of Config registers Added note about ASID field in EntryHi not being updated on an exception Updated descriptions of CACHE PREF and SYNC to include processor specific information Added note that it is invalid to have all ways locked in the data 01 01 April 2 2001 cache no longer invalid superseded by revision 1 07 01 02 May 16 2001 Added WST 1 table to CACHE instruction description Minor changes in the instruction decode tables Added details on new mechanism for CACHE access to ScratchPad RAMs 01 03 June 12 2001 Removed support for MIPS16 ASMACRO Modified text and reset state for CU2 bit in Status register and updated text on C2 bit in Configl MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 279 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Appendix A Revision History
266. ine basis enabling the system designer to maximize the efficiency of the system cache Cache locking is always available on all instruction cache entries Entries can be marked as locked or unlocked by setting or clearing the lock bit on a per entry basis using the CACHE instruction The LRU array must be bit writable The tag and data arrays only need to be word writable 1 2 2 3 Data Cache The data cache is an optional on chip memory array of up to 64 Kbytes The cache is virtually indexed and physically tagged allowing the virtual to physical address translation to occur in parallel with the cache access The tag holds 22 bits of the physical address a valid bit and a lock bit A separate array holds the dirty and LRU bits this array ranges from 0 10 bits depending on the associativity In addition to instruction cache locking all cores also support a data cache locking mechanism identical to the instruction cache with critical data segments to be locked into the cache on a per line basis The locked contents cannot be selected for replacement on a cache miss but can be updated on a store hit Cache locking is always available on all data cache entries Entries can be marked as locked or unlocked on a per entry basis using the CACHE instruction The physical data cache memory must be byte writable to support sub word store operations The LRU dirty bit array must be bit writable 1 2 2 4 EJTAG Controller All cores provid
267. ing in unmapped and uncached code space All other processor state can then be initialized by software AT ColdReset is asserted after power up to bring the device into a known state Soft reset can be forced by asserting the A Reset pin This distinction is made for compatibility with other MIPS processors In practice both resets are handled identically with the exception of the setting of Status sp 6 1 1 Coprocessor 0 State Much of the hardware initialization occurs in Coprocessor 0 Random 4KEc core only cleared to maximum value on Reset SoftReset Wired 4KEc core only cleared to 0 on Reset SoftReset Status pry cleared to 1 on Reset SoftReset Statusrs cleared to 0 on Reset SoftReset Status sp cleared to 0 on Reset set to 1 on SoftReset Status yyy cleared to 0 on Reset SoftReset Status pry set to 1 on Reset SoftReset Statusgp cleared to 0 on Reset SoftReset Watch ou g w cleared to 0 on Reset SoftReset Config fields related to static inputs set to input value by Reset SoftReset Config go set to 010 uncached on Reset SoftReset Config ki set to 010 uncached on Reset SoftReset 4KEm and 4KEp cores only Config x23 set to 010 uncached on Reset SoftReset 4KEm and 4KEp cores only ContextConfig set to 0x007ffff0 on Reset SoftReset MIPS32 configuration PageGrainyyask set to 11 on Reset SoftReset MIPS32 compatibility mode DebugDM cleared to 0 on Reset SoftReset unless EITAGB
268. ing the multiply operation Mult 3 In cycle 3 a 32x32 multiply operation Mult enters the I stage and is fetched from the instruction cache Since the Add operation has not yet reached the M stage by cycle 3 there is no activity in the M stage of the integer pipeline at this time MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 17 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 2 Pipeline 4 Incycle4 the Subtract instruction enters I stage The second multiply operation Mult enters the E stage And the Add operation enters M stage of the integer pipe Since the Mult multiply is a 32x16 operation only one clock is required for the Mur stage hence the Mult operation passes to the Awun stage of the MDU pipeline 5 In cycle 5 the Subtract instruction enters E stage The Mult multiply enters the Mun stage The Add operation enters the A stage of the integer pipeline The Mult operation completes and is written back in to the HI LO register pair in the Wun stage D Since a 32x32 multiply requires two passes through the multiplier with each pass requiring one clock the 32x32 Mult remains in the Mun stage in cycle 6 The Sub instruction enters M stage in the integer pipeline The Add operation completes and is written to the register file in the W stage of the integer pipeline 7 The Mult multiply operation progresses to the Aur stage and the Sub instruction progress to the A st
269. ingle step exception enabled are taken even though debug single step was enabled For a normal exception other than reset a debug single step exception is then taken on the first instruction in the normal exception handler Debug exceptions are unaffected by single step mode e g returning to a SDBBP instruction with debug single step exceptions enabled causes a debug software breakpoint exception and the DEPC will point to the SDBBP instruction However returning to an instruction not jump branch just before the SDBBP instruction causes a debug single step exception with the DEPC pointing to the SDBBP instruction To ensure proper functionality of single step the debug single step exception has priority over all other exceptions except reset and soft reset Debug Register Debug Status Bit Set DSS Additional State Saved None Entry Vector Used Debug exception vector MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 71 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 4 Exceptions and Interrupts 72 4 8 4 Debug Interrupt Exception A debug interrupt exception is either caused by the EjtagBrk bit in the EJTAG Control register controlled through the TAP or caused by the debug interrupt request signal to the CPU The debug interrupt exception is an asynchronous debug exception which is taken as soon as possible but with no specific relation to the executed instructions The
270. ings determine user or kernel mode User mode UM 1 EXL 0 and ERL 0 Kernel mode UM 0 or EXL 1 or ERL 1 Coprocessor Accessibility The Status register CU bits control coprocessor accessibility If any coprocessor is unusable then an instruction that accesses it generates an exception Figure 5 14 shows the format of the Status register Table 5 17 describes the Status register fields Figure 5 14 Status Register Format 31 28 27 26 25 24 23 22 21 20 19 18 17 16 15 10 9 8 7 65 4 3 2 1 0 CU3 CUO RP FR RE R BEV TS SR NMI 0 R IM7 IM2 IMI IMO R UM R ERL EXL IE IPL Table 5 17 Status Register Field Descriptions Fields Read Name Bits Description Write Reset State CU3 31 Controls access to coprocessor 3 COP3 is not supported R 0 This bit cannot be written and will read as 0 Controls access to coprocessor 2 This bit can only be written if coprocessor is attached to the COP2 interface cue 30 C2 bit in Configl is set This bit will read as 0 if no RM g coprocessor is present CUI 29 Controls access to Coprocessor 1 COPI is not supported R 0 This bit cannot be written and will read as 0 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 105 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers Table 5 17 Status Register Field Descriptions Field
271. ins both required and optional blocks as shown in the block diagram in Figure 1 1 on page 5 Required blocks are the lightly shaded areas of the block diagram and are always present in any core implementation Optional blocks may be added to the base core depending on the needs of a specific implementation The required blocks are as follows Execution Unit Multiply Divide Unit MDU System Control Coprocessor CPO Memory Management Unit MMU Cache Controller Bus Interface Unit BIU Power Management Optional blocks include nstruction Cache I cache Data Cache D cache Enhanced JTAG EJTAG Controller e MIPS16e support Coprocessor 2 Interface CP2 CorExtend M User Defined Instructions UDI Figure 1 1 shows a block diagram of a 4KE core The MMU can be implemented using either a translation lookaside buffer in the case of the 4KEc core or a fixed mapping FMT in the case of the 4KEm and 4KEp cores Refer to Chapter 3 Memory Management on page 33 for more information 4 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 1 2 4KE Block Diagram Off On Chip Trace I F e Trace oe cache ff Chip TAP Debug I F T UDI Execution Unit E RF ALU Shift MMU Cache E Controller a re 5 CP2 Y EE GN E System i Coprocessor TB or FMT D cache Sa m F
272. ion setup valid from memor P P y FromData id to CP2 Instrucion Validate inst ToData Complete CP2 to Core Control Read info Z y FromDatal CP2 internal Get ready for Decode amp get See Capture Complete operations new inst FromData Valid ToData instruction Figure 2 21 Coprocessor 2 Interface Transactions As can be seen all control and data from the coprocessor must occur in the M stage If this is not the case the A stage will start slipping in the following cycle and thus stall the I E M and A pipeline stages but if all expected control and data is available in the M stage a Coprocessor 2 instructions can execute with no stalls on the pipeline There is only one exception to this and that is the Branch on Coprocessor conditions BC2 instruction All branch instructions including the regular BEQ BNE etc must be resolved in E stage The 4KE core does not have branch prediction logic and thus the target address must be available before the end of E stage The BC2 instruction has to follow the same protocol as all other coprocessor 2 instructions on the CP2 Interface All core interface operations belonging to the E M and A stages will have to occur in the E stage for BC2 instructions This means that a BC2 instructions always slips for a minimum of 2 cycles in E stage Any delay in return of branch information from the Coprocessor 2 will add to the number of slip cycles All other Coprocessor 2 instructions can
273. ion of Release 1 of the Architecture Vectored Interrupt VI mode which adds the ability to prioritize and vector interrupts to a handler dedicated to that interrupt and to assign a GPR shadow set for use during interrupt processing The presence of this mode is denoted by the VInt bit in the Config3 register This mode is architecturally optional but it is always present on the 4KE core so the VInt bit will always read as a 1 for the 4KE core External Interrupt Controller EIC mode which redefines the way in which interrupts are handled to provide full support for an external interrupt controller handling prioritization and vectoring of interrupts This presence of this mode denoted by the VEIC bit in the Config3 register Again this mode is architecturally optional On the 4KE core MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 55 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 4 Exceptions and Interrupts the VEIC bit is set externally by the static input SI EICPresent to allow system logic to indicate the presence of an external interrupt controller The reset state of the processor is to interrupt compatibility mode such that a processor supporting Release 2 of the Architecture like the 4KE core is fully compatible with implementations of Release 1 of the Architecture Table 4 2 shows the current interrupt mode of the processor as a function of the coprocessor 0 regist
274. ipeline stage to complete The 32x32 multiply operation requires two clocks in the Maan pipe stage The MDU pipeline is shown as the shaded areas of Figure 2 6 and always starts a computation in the final phase of the E stage As shown in the figure the Mun pipe stage of the MDU pipeline occurs in parallel with the M stage of the IU pipeline the Aypy stage occurs in parallel with the A stage and the Wun stage occurs in parallel with the W stage In general this need not be the case Following the Ist cycle of the M stages the two pipelines need not be synchronized This does not present a problem because results in the MDU pipeline are written to the HI and LO registers while the integer pipeline results are written to the register file cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 l i gt l i l Mult I E Mmpu Ampu Wwpu l l l l Add l T E M A W l Mult I E Maan Mmpu AMDU Wypu Sub l l I E M A W l Figure 2 6 MDU Pipeline Behavior During Multiply Operations 4KEc amp 4KEm Processors The following is a cycle by cycle analysis of Figure 2 6 1 The first 32x16 multiply operation Mult is fetched from the instruction cache and enters the I stage 2 An Add operation enters the I stage The Mult operation enters the E stage The integer and MDU pipelines share the I and E pipeline stages At the end of the E stage in cycle 2 the MDU pipeline starts process
275. is is a temporary controller state in which all test data registers selected by the current instruction retain their previous state If TMS is sampled LOW on the rising edge of TCK the controller transitions to the Capture IR state A HIGH on TMS causes the controller to transition to the Test Reset Logic state The instruction cannot change while the TAP controller is in this state MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 189 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support 190 9 3 2 5 Capture DR State In this state the boundary scan register captures the value of the register addressed by the Instruction register and the value is then shifted out in the Shift DR If TMS is sampled LOW at the rising edge of TCK the controller transitions to the Shift DR state A HIGH on TMS causes the controller to transition to the Exit DR state The instruction cannot change while the TAP controller is in this state 9 3 2 6 Shift DR State In this state the test data register connected between TDI and TDO as a result of the current instruction shifts data one stage toward its serial output on the rising edge of TCK If TMS is sampled LOW on the rising edge of TCK the controller remains in the Shift DR state A HIGH on TMS causes the controller to transition to the Exit DR state The instruction cannot change while the TAP controller is in this state 9 3 2 7 Exit1 DR
276. is then re accessed and the translation will be successful This parallel access reduces the DTLB miss penalty to 1 cycle 3 4 Virtual to Physical Address Translation 4KEc Core Converting a virtual address to a physical address begins by comparing the virtual address from the processor with the virtual addresses in the TLB There is a match when the VPN of the address is the same as the VPN field of the entry and either The Global G bit of both the even and odd pages of the TLB entry are set or The ASID field of the virtual address is the same as the ASID field of the TLB entry This match is referred to as a TLB hit If there is no match a TLB miss exception is taken by the processor and software is allowed to refill the TLB from a page table of virtual physical addresses in memory Figure 3 8 on page 46 shows the logical translation of a virtual address into a physical address In this figure the virtual address is extended with an 8 bit ASID which reduces the frequency of TLB flushing during a context switch This 8 bit ASID contains the number assigned to that process and is stored in the CPO EntryHi register MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 45 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 3 Memory Management 46 Virtual Address 1 Virtual address VA represented by the virtual page number VPN is compared with tag in TLB 2 If there i
277. ision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 10 Instruction Set Overview This chapter provides a general overview on the three CPU instruction set formats of the MIPS architecture Immediate Jump and Register Refer to Chapter 11 MIPS32 4KE Processor Core Instructions for a complete listing and description of instructions This chapter discusses the following topics Section 10 1 CPU Instruction Formats on page 231 Section 10 2 Load and Store Instructions on page 232 Section 10 3 Computational Instructions on page 233 Section 10 4 Jump and Branch Instructions on page 234 Section 10 5 Control Instructions on page 234 Section 10 6 Coprocessor Instructions on page 234 Section 10 7 Enhancements to the MIPS Architecture on page 235 10 1 CPU Instruction Formats Each CPU instruction consists of a single 32 bit word aligned on a word boundary There are three instruction formats immediate I type jump J type and register R type as shown in Figure 10 1 on page 232 The use of a small number of instruction formats simplifies instruction decoding allowing the compiler to synthesize more complicated and less frequently used operations and addressing modes from these three formats as needed MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 231 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Cha
278. ister DCR to determine which other memory mapped registers exist in drseg The value returned in response to a read of any unimplemented memory mapped register is unpredictable and writes are ignored to any unimplemented register in the drseg Refer to Chapter 9 EJTAG Debug Support for more information on the DCR The allowed access size is limited for the drseg Only word size transactions are allowed Operation of the processor is undefined for other transaction sizes 3 2 4 2 Conditions and Behavior for Access to dmseg EJTAG Memory The behavior of CPU access to the dmseg address range at OXFF20 0000 to OXFF2F FFFF is determined by the table shown in Table 3 5 Table 3 5 CPU Access to dmseg Address Range ProbEn bit in LSNM bit in Transaction DCR register Debug register Access Load Store Don t care 1 Kernel mode address space kseg3 Fetch 1 Don t care dmseg Load Store 1 0 Fetch 0 Don t care See comments below Load Store 0 0 The case with access to the dmseg when the ProbEn bit in the DCR register is 0 is not expected to happen Debug software is expected to check the state of the ProbEn bit in DCR register before attempting to reference dmseg If such a reference does happen the reference hangs until it is satisfied by the probe The probe can not assume that there will never be a reference to dmseg if the ProbEn bit in the DCR register is 0 because there is an inherent race between the deb
279. ister 15 Select 1 122 The EBase register is a read write register containing the base address of the exception vectors used when Statusgry equals 0 and a read only CPU number value that may be used by software to distinguish different processors in a multi processor system The EBase register provides the ability for software to identify the specific processor within a multi processor system and allows the exception vectors for each processor to be different especially in systems composed of heterogeneous processors Bits 31 12 of the EBase register are concatenated with zeros to form the base of the exception vectors when Statuspgy is 0 The exception vector base address comes from the fixed defaults see Section 4 5 Exception Vector Locations on page 65 when Statuspgy is 1 or for any EJTAG Debug exception The reset state of bits 31 12 of the EBase register initialize the exception base register to 164 8000 0000 providing backward compatibility with Release 1 implementations Bits 31 30 of the EBase Register are fixed with the value 23 10 to force the exception base address to be in the ksegO or kseg unmapped virtual address segments If the value of the exception base register is to be changed this must be done with Statusgpy equal 1 The operation of the processor is UNDEFINED if the Exception Base field is written with a different value when Statusppy is 0 Combining bits 31 20 with the Exception Base field allows the base add
280. iteback if required and set the state to valid and locked If the cache already contains the specified address set the state to locked The way selected on fill from memory is the least 28H11 LD Fetch and Lock Address recently used Yes The lock state is cleared by executing an Index Invalidate Index Writeback Invalidate Hit Invalidate or Hit Writeback Invalidate operation to the locked line or via an Index Store Tag operation with the lock bit reset in the TagLo register MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 251 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Table 11 14 Encoding of Bits 20 18 of the CACHE Instruction ErrCtl WST Set ErrCt SPR Cleared Effective Address Operand Type Operation Implemented Read the WS RAM at the specified index into Indez L ad WS the TagLo Coprocessor 0 register Update the WS RAM at the specified index E from the TagLo Coprocessor 0 register Write the DataLo Coprocessor 0 register Index Store Data contents at the way and byte index specified All All of the other codes behave the same as when Others ErrCtl WST is cleared Table 11 15 Encoding of Bits 20 18 of the CACHE Instruction ErrCtl SPR Set Effective Address Operand Code Name Type Operation Implemented Read the SPRAM tag at the specified index into the TagLo Coprocessor 0 register Also SE bs Tides oud Tag Index read the data correspondin
281. ive cycles This register is only implemented if the EJTAG Trace capability is present Figure 5 33 User Trace Data Register Format 31 0 Data Table 5 37 UserTraceData Register Field Descriptions Read Description Write Reset State Software readable writable data When written this triggers a user format trace record out of the PDtrace R W interface that transmits the Data field to trace memory MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 141 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers 5 2 32 TraceBPC Register CP0 Register 23 Select 4 This register is used to control start and stop of tracing using an EJTAG Hardware breakpoint The Hardware breakpoint would then be set as a trigger source and optionally also as a Debug exception breakpoint This register is only implemented if both Hardware breakpoints and the EJTAG Trace capability are present Figure 5 34 Trace BPC Register Format 31 30 18 17 16 15 14 4 3 0 bg 9 E E 9 99 Table 5 38 TraceBPC Register Field Descriptions Fields Read Description Write Reset State Used to specify whether the trigger signal from EJTAG data breakpoint should trigger tracing functions or not 0 disables trigger signals from data breakpoints 1 enables trigger signals from data breakpoints Reserved 0 Each of the 2 bits corresponds to the 2 possible
282. ixed Reguired a Coprocessor 2 ixed Required Optiona Figure 1 1 4KE Processor Core Block Diagram 1 2 1 Required Logic Blocks The following subsections describe the various required logic blocks of the 4KE processor core 1 2 1 1 Execution Unit The core execution unit implements a load store architecture with single cycle Arithmetic Logic Unit ALU operations logical shift add subtract and an autonomous multiply divide unit The core contains thirty two 32 bit general purpose registers GPRs used for scalar integer operations and address calculation Optionally one or three additional register file shadow sets each containing thirty two registers can be added to minimize context switching overhead during interrupt exception processing The register file consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline The execution unit includes 32 bit adder used for calculating the data address Address unit for calculating the next instruction address Logic for branch determination and branch target address calculation Load aligner Bypass multiplexers used to avoid stalls when executing instruction streams where data producing instructions are followed closely by consumers of their results Zero One detect unit for implementing the CLZ and CLO instructions ALU for performing bitwise logical operations Shifter and Store aligner 1 2 1 2 Multiply Divide Unit MDU T
283. ization operations As such software should never use a non zero value of the stype field as this may inadvertently cause future failures if non zero values remove synchronization operations The SYNC instruction stalls until all loads stores refills are completed and all write buffers are empty MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 263 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Synchronize Shared Memory cont SYNC Restrictions The effect of SYNC on the global order of loads and stores for memory access types other than uncached and cached coherent is UNPREDICTABLE Operation SyncOperation stype Exceptions None 264 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Read Indexed TLB Entry TLBR 31 26 25 24 6 5 0 COPO CO 0 TLBR 010000 1 000 0000 0000 0000 0000 000001 6 1 19 6 Format TLBR MIPS32 Purpose To read an entry from the TLB Description The EntryHi EntryLoO EntryLol and PageMask registers are loaded with the contents of the TLB entry pointed to by the Index register Note that the value written to the EntryHi EntryLoO and EntryLol registers may be different from that originally written to the TLB via these registers in that The value returned in the G bit in both the EntryLoO and EntryLol registers comes from the singl
284. k 1 6 Trace clock is one sixth of core clock 1 8 Trace clock is one eighth of core clock The TCBDATA register 0x12 is used to access the registers defined by the TCBCONTROLBpgg field see Table 9 28 Regardless of which register or data entry is accessed through TCBDATA the register is only written if the TCBCONTROLBwp bit is set For read only registers the TCBCONTROLBwm is a don t care The format of the TCBDATA register is shown below and the field is described in Table 9 32 The width of TCBDATA is 64 bits when on chip trace words TWs are accessed TCBTW access 31 63 TCBDATA Register Format 0 Data 216 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 9 Trace Control Block TCB Registers hardware control Table 9 32 TCBDATA Register Field Descriptions Description Read Write Only writable if 31 0 Register fields or data as defined by the Data 63 0 TCBCONTROLBgygg field POA CONTR OLR a 0 9 9 4 TCBCONFIG Register Reg 0 The TCBCONFIG register holds information about the hardware configuration of the TCB The format of the TCBCONFIG register is shown below and the field is described in Table 9 33 TCBCONFIG Register Format 31 30 25 24 21 20 17 16 14 13 1110 9 8 6 5 4 3 0 CFI 0 TRIG SZ CRMax CRMin PW DN JOnT OfT REV Table 9 33 TCBCONFIG Register Field Descriptions
285. ldest trigger when it de asserts TCBCONTROLBgy An About trigger will not start the countdown if an even older About trigger is using the Trace Word counter Triggers which produce TF6 trace information in the trace flow Trace bit is set Regardless of priority the TCBTRIGxTg bit is set when the trigger fires This is so even if a trigger action is suppressed by a higher priority trigger action If the trigger is set to only fire once the TCBTRIGxgo bit is set then the suppressed trigger action will not happen until after TCBTRIGxTg is written 0 If a Trigger action is suppressed by a higher priority trigger then the read value when the TCBTRIGxg bit is set for the TCBTRIGXTrace field will be 0 for suppressed TF6 trace information actions The read value in the TCBTRIGXqyp field for suppressed Start End About triggers will be 11 This indication of a suppressed action is sticky If any of the two actions Trace and Type are ever suppressed for a multi fire trigger the TCBTRIGxxo bit is zero then the read values in Trace and or Type are set to indicate any suppressed action MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 227 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support About trigger The About triggers delayed de assertion of the TCBCONTROLBgn bit is always executed regardless of priority from another Start trigger at the time of the TCBCONTROLBgy change
286. ler The interrupt controller is responsible for prioritizing all interrupts including 60 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 4 3 Interrupts hardware software timer and performance counter interrupts and directly supplying to the processor the vector number of the highest priority interrupt EIC interrupt mode is in effect if all of the following conditions are true Config3ygc 1 IntCtlys 0 e Causezy 1 Statusggy 0 In EIC interrupt mode the processor sends the state of the software interrupt requests Cause pg and the timer interrupt request Cause y to the external interrupt controller where it prioritizes these interrupts in a system dependent way with other hardware interrupts The interrupt controller can be a hard wired logic block or it can be configurable based on control and status registers This allows the interrupt controller to be more specific or more general as a function of the system environment and needs The external interrupt controller prioritizes its interrupt requests and produces the vector number of the highest priority interrupt to be serviced The vector number called the Requested Interrupt Priority Level RIPL is a 6 bit encoded value in the range 0 63 inclusive A value of 0 indicates that no interrupt requests are pending The values 1 63 represent the lowest 1 to highest 63
287. lers The data and instruction cache controllers support caches of various sizes organizations and set associativities For example the data cache can be 2 Kbytes in size and 2 way set associative while the instruction cache can be 8 Kbytes in size and 4 way set associative There is a separate cache controller for the instruction cache and the data cache Each cache controller contains and manages a one line fill buffer Besides accumulating data to be written to the cache the fill buffer is accessed in parallel with the cache and data can be bypassed back to the core Refer to Chapter 7 Caches on page 153 for more information on the instruction and data cache controllers MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 7 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 1 Introduction to the MIPS32 4KE Processor Core Family 1 2 1 6 Bus Interface Unit BIU The Bus Interface Unit BIU controls the external interface signals Additionally it contains the implementation of a 32 byte collapsing write buffer The purpose of this buffer is to hold and combine write transactions before issuing them to the external interface Since the data caches for all cores follow a write through cache policy the write buffer significantly reduces the number of write transactions on the external interface as well as reducing the amount of stalling in the core due to issuance of multiple writ
288. ll be 11 If the write value was 11 the read value is always 11 This special read value is valid until the TCBTRIGx register is written Fire Once When set this trigger will not re fire until the TR bit is FO 1 de asserted When de asserted this trigger will fire each time one R W 0 of the trigger sources indicates trigger Trigger happened When set this trigger fired since the TR bit was last written 0 This bit is used to inspect whether the trigger fired since this bit was last written zero When set all the trigger source bits bit 4 to 13 will change their IR 0 read value to indicate if the particular bit was the source to fire this R WO 0 trigger Only enabled trigger sources can set the read value but more than one is possible Also when set the Type field and the Trace field will have read values which indicate if the trigger action was ever suppressed by a higher priority trigger 9 9 10 Register Reset State Reset state for all register fields is entered when either of the following occur 1 TAP controller enters is in Test Logic Reset state 2 EJ_TRST_N input is asserted low 222 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 10 EJTAG Trace Enabling 9 10 EJTAG Trace Enabling As there are several ways to enable tracing it can be quite confusing to figure out how to turn tracing on and off T
289. ll rights reserved Chapter 12 MIPS16 Application Specific Extension to the MIPS32 Instruction Set This chapter describes the MIPS16 ASE as implemented in the 4KE core Refer to Volume IV a of the MIPS32 Architecture Reference Manual for a general description of the MIPS16 ASE as well as instruction descriptions This chapter covers the following topics Section 12 1 Instruction Bit Encoding on page 273 Section 12 2 Instruction Listing on page 275 12 1 Instruction Bit Encoding Table 12 2 through Table 12 9 describe the encoding used for the MIPS16 ASE Table 12 1 describes the meaning of the symbols used in the tables Table 12 1 Symbols Used in the Instruction Encoding Tables Symbol Meaning Operation or field codes marked with this symbol are reserved for future use Executing such an instruction cause a Reserved Instruction Exception Also italic field name Operation or field codes marked with this symbol denotes a field class The instruction word must be further decoded by examining additional tables that show values for another instruction field Operation or field codes marked with this symbol represent a valid encoding for a higher order MIPS ISA level Executing such an instruction cause a Reserved Instruction Exception Operation or field codes marked with this symbol are available to licensed MIPS partners To avoid multiple conflicting instruction definitions the partner must
290. ll rights reserved Chapter 5 CPO Registers 5 1 CP0 Register Summary 88 Table 5 1 lists the CPO registers in numerical order The individual registers are described throughout this chapter Where more than one registers shares the same register number at different values of the sel field of the instruction their names are listed using a slash as separator Table 5 1 CPO Registers Register Number Register Name Function Index into the TLB array 4KEc core This register is reserved 3 BOSE in the 4KEp and 4KEm cores Randomly generated index into the TLB array 4KEc core This 3 Random register is reserved in the 4KEp and 4KEm cores Low order portion of the TLB entry for even numbered virtual EntryLo0 pages 4KEc core This register is reserved in the 4KEp and 4KEm cores Low order portion of the TLB entry for odd numbered virtual EntryLo1 pages 4KEc core This register is reserved in the 4KEp and 4KEm cores Pointer to page table entry in memory 4KEc core This register Context is reserved in the 4KEp and 4KEm cores PageMask controls the variable page sizes in TLB entries PageMask PageGrain enables support of 1KB pages in the TLB These PageGrain registers are defined for the 4KEc core only and reserved in the 4KEp and 4KEm cores 6 7 Wired Controls the number of fixed wired TLB entries 4KEc core This register is reserved in the 4KEp and 4KEm cores H
291. lly since the instruction cache initialization needs to be run in an uncached address region 6 2 4 Coprocessor 0 State Miscellaneous COPO states need to be initialized prior to leaving the boot code There are various exceptions which are blocked by ERL 1 or EXL 1 and which are not cleared by Reset These can be cleared to avoid taking spurious exceptions when leaving the boot code Cause WP Watch Pending SW0 1 Software Interrupts should be cleared Config KO should be set to the desired Cache Coherency Algorithm CCA prior to accessing Kseg0 Config 4KEm and 4KEp cores only KU and K23 should be set to the desired CCA for USeg KUSeg and KSeg2 3 respectively prior to accessing those regions Count Should be set to a known value if Timer Interrupts are used Compare Should be set to a known value if Timer Interrupts are used The write to compare will also clear any pending Timer Interrupts Thus Count should be set before Compare to avoid any unexpected interrupts Status Desired state of the device should be set Other COPO state Other registers should be written before they are read Some registers are not explicitly writeable and are only updated as a by product of instruction execution or a taken exception Uninitialized bits should be masked off after reading these registers MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 151 Copyright 2000 2002 MIPS Technologies Inc All rights reserved
292. logies Inc All rights reserved Store Conditional Word cont SC Restrictions The effective address must be naturally aligned If either of the 2 least significant bits of the address is non zero an Address Error exception occurs Operation vAddr lt sign extend offset GPR base if vAddr 9 0 then SignalException AddressError endif pAddr CCA AddressTranslation vAddr DATA STORE dataword GPR rt if LLbit then StoreMemory CCA WORD dataword pAddr vAddr DATA endif GPR rt e 0 LLbit MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 261 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Store Conditional Word cont 262 Exceptions SC TLB Refill TLB Invalid TLB Modified Address Error Watch Programming Notes LL and SC are used to atomically update memory locations as shown below Lily LL 1 TO ADDI I2 Il X3 SC 2 TO t BEQ 2 0 L1 NOP load counter increment try to store checking for atomicity if not atomic 0 try again branch delay slot Exceptions between the LL and SC cause SC to fail so persistent exceptions must be avoided Some examples of these are arithmetic operations that trap system calls and floating point operations that trap or require software emu lation assistance LL and SC function on a single processor for cached noncoherent memory so that parallel program
293. lse ErrorEPC PC endif PC OxBFCO 0000 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 4 8 Exceptions 4 8 6 Machine Check Exception 4KEc core A machine check exception occurs when the processor detects an internal inconsistency The following condition causes a machine check exception The detection of multiple matching entries in the TLB 4KEc core only The core detects this condition on a TLB write and prevents the write from being completed The TS bit in the Status register is set to indicate this condition This bit is only a status flag and does not affect the operation of the device Software clears this bit at the appropriate time This condition is resolved by flushing the conflicting TLB entries The TLB write can then be completed Cause Register ExcCode Value MCheck Additional State Saved None Entry Vector Used General exception vector offset 0x180 4 8 7 Interrupt Exception The interrupt exception occurs when one or more of the six hardware two software or timer interrupt requests is enabled by the Status register and the interrupt input is asserted See Section 4 3 Interrupts on page 55 for more details about the processing of interrupts XXX Is this paragraph still relevant XXX The delay from assertion of an unmasked interrupt to the fetch of the first instructions at the exce
294. lue Cache Coherency Attribute 0 Cacheable noncoherent write through no write allocate 1 Cacheable noncoherent write through write allocate 3 4 5 6 Cacheable noncoherent write back write allocate 2 7 Uncached Note These two values are required by the MIPS32 architecture Only values 0 1 2 and 3 are used in a 4KE core For example values 4 5 and 6 are not used and are mapped to 3 The value 7 is not used and is mapped to 2 Note that these values do have meaning in other MIPS Technologies processor implementations Refer to the MIPS32 specification for more information 94 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions 5 2 4 Context Register CPO Register 4 Select 0 The Context register is a read write register containing a pointer to an entry in the page table entry PTE array This array is an operating system data structure that stores virtual to physical translations During a TLB miss the operating system loads the TLB with the missing translation from the PTE array The Context register duplicates some of the information provided in the BadVAddr register but is organized in such a way that the operating system can directly reference an 8 byte page table entry PTE in memory A TLB exception TLB Refill TLB Invalid or TLB Modified causes bits VA31 3 of the virtual address to be written into
295. lues Address Bit Segment Segment Values UM Name Address Range Size 0x0000 0000 A 31 20 through 2 GBytes A 31 29 1005 Ox7FFF_FFFF 2 bytes UM 0 or A 31 29 101 A 31 29 110 A 31 29 111 EXL 1 0x8000_0000 through Ox9FFF FFFF 512 MBytes 27 bytes or ERL 1 and DM 0 kseg3 0xA000_0000 through OxBFFF_FFFF 0xC000_0000 through OxDFFF FFFF O0xE000 0000 through OxFFFF FFFF 512 MBytes 27 bytes 512 MBytes 27 bytes 512 MBytes 27 bytes Copyright 2000 2002 MIPS Technologies Inc All rights reserved MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 39 Chapter 3 Memory Management 40 3 2 3 1 Kernel Mode User Space kuseg In Kernel mode when the most significant bit of the virtual address A31 is cleared the 32 bit kuseg virtual address space is selected and covers the full 2 bytes 2 GBytes of the current user address space mapped to addresses 0x0000 0000 0x7FFF_FFFF For the 4KEc core the virtual address is extended with the contents of the 8 bit ASID field to form a unique virtual address When ERL 1 in the Status register the user address region becomes a 2 byte unmapped and uncached address space While in this setting the kuseg virtual address maps directly to the same physical address and does not include the ASID field 3 2 3 2 Kernel Mode Kernel Space 0 kseg0 In Ker
296. made through the pipeline The counter increments every other clock if the DC bit in the Cause register is 0 The Count register can be written for functional or diagnostic purposes including at reset or to synchronize processors By writing the CountDM bit in the Debug register it is possible to control whether the Count register continues incrementing while the processor is in debug mode Figure 5 11 Count Register Format 31 0 Count Table 5 14 Count Register Field Description Fields Read Description Write Reset State Com 310 EUN 1 0 Interval counter counter Interval counter W Undefined 102 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions 5 2 11 EntryHi Register CPO Register 10 Select 0 The EntryHi register contains the virtual address match information used for TLB read write and access operations A TLB exception TLB Refill TLB Invalid or TLB Modified causes bits VA3 13 of the virtual address to be written into the VPN2 field of the EntryHi register An implementation of Release 2 of the Architecture which supports 1KB pages also writes VAj gt 1 into the VPN2X field of the EntryHi register A TLBR instruction writes the EntryHi register with the corresponding fields from the selected TLB entry The ASID field is written by software with the current address s
297. make room for PA 10 If the processor is not enabled to support 1KB pages Config3sp 0 or PageGraingsp 0 the PFN field corresponds to bits 31 12 of the physical address Coherency attribute of the page See Table 5 6 Undefined Dirty or write enable bit indicating that the page has been written and or is writable If this bit is a one then stores to the page are permitted If this bit is a zero then stores to the page cause a TLB Modified exception Valid bit indicating that the TLB entry and thus the virtual page mapping are valid If this bit is a one then accesses to the page are permitted If this bit is a zero then accesses to RW Undefined the page cause a TLB Invalid exception Undefined Global bit On a TLB write the logical AND of the G bits in both the EntryLoO and EntryLol register becomes the G bit in the TLB entry If the TLB entry G bit is a one then S 0 the ASID comparisons are ignored during TLB matches R W Undefined On a read from a TLB entry the G bits of both EntryLoO and EntryLol reflect the state of the TLB G bit MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 93 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers Table 5 6 lists the encoding of the C field of the EntryLo0 and EntryLo registers and the KO field of the Config register Table 5 6 Cache Coherency Attributes C 5 3 Va
298. mation compression happens in the PDtrace module Any data information like PC and load store address values delta or full load store data and processor mode changes are all sent on the same 16 data bus to the TCB on the PDtrace M interface When an instruction requires more than 16 bits of information to be traced properly the PDtrace fifo will buffer the information and send it on subsequent clock cycles In the TCB the on chip trace memory is defined as a 64 bit wide synchronous memory running at core clock speed In this case the fifo is not needed For off chip trace through the Trace Probe the fifo comes into play because only a limited number of pins 4 8 or 16 exist Also the speed of the Trace Probe interface can be different either faster or slower from that of the 4KE core So for off chip tracing a specific TCB TW fifo is needed 9 12 2 Handling of Fifo overflow in the PDtrace module 228 Depending on the amount of trace information selected for trace and the frequency with which the 16 bit data interface is needed it is possible for the PDtrace fifo overflow from time to time There are two ways to handle this case 1 Allow the overflow to happen and thereby lose some information from the trace data 2 Prevent the overflow by back stalling the core until the fifo has enough empty slots to accept new trace data The PDtrace fifo option is controlled by either the TraceControljg or the TCBCONTROLA o bit depending on th
299. mpatibility 10 2 2 Defining Access Types Access type indicates the size of a core data item to be loaded or stored set by the load or store instruction opcode 232 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 10 3 Computational Instructions Regardless of access type or byte ordering endianness the address given specifies the low order byte in the addressed field For a big endian configuration the low order byte is the most significant byte for a little endian configuration the low order byte is the least significant byte The access type together with the three low order bits of the address define the bytes accessed within the addressed word as shown in Table 10 1 Only the combinations shown in Table 10 1 are permissible other combinations cause address error exceptions Table 10 1 Byte Access Within a Word Bytes Accessed Low Order Big Endian Little Endian Address Bits 31 0 31 0 Access Type Triplebyte Halfword 10 3 Computational Instructions Computational instructions can be either in register R type format in which both operands are registers or in immediate I type format in which one operand is a 16 bit immediate Computational instructions perform the following operations on register values Arithmetic Logical Shi
300. n Register State Value unit number of the coprocessor being referenced Entry Vector Used General exception vector offset 0x180 4 8 19 Execution Exception Coprocessor 2 Exception The Coprocessor 2 exception is one of the nine execution exceptions All of these exceptions have the same priority A Coprocessor 2 exception occurs when a valid Coprocessor 2 instruction cause a general exception in the Coprocessor 2 Cause Register ExcCode Value C2E Additional State Saved Depending on the Coprocessor 2 implementation additional state information of the exception can be saved in a Coprocessor 2 control register Entry Vector Used General exception vector offset 0x180 4 8 20 Execution Exception Implementation Specific 1 exception The Implementation Specific 1 exception is one of the nine execution exceptions All of these exceptions have the same priority An implementation specific 1 exception occurs when a valid coprocessor 2 instruction cause an implementation specific 1 exception in the Coprocessor 2 78 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 4 8 Exceptions Cause Register ExcCode Value IS1 Additional State Saved Depending on the coprocessor 2 implementation additional state information of the exception can be saved in a coprocessor 2 control register Entry Vector Used General exceptio
301. n CACHE Cache Operation See Cache Description CFC2 Move Control Word From Coprocessor 2 Rt CCR 2 n CLO Count Leading Ones Rd NumLeadingOnes Rs CLZ Count Leading Zeroes Rd NumLeadingZeroes Rs COPO Coprocessor 0 Operation See Coprocessor Description COP2 Coprocessor 2 Operation See Coprocessor 2 Description CTC2 Move Control Word To Coprocessor 2 CCR 2 n Rt d PC DEPC DERET Return from Debug Exception Exit Debug Mode Rt Status DI Disable Interrupts Statusyp 0 LO int Rs int Rt DIV Divide HI int Rs int Rt nM LO z uns Rs uns Rt DIVU Unsigned Divide HI uns Rs uns Rt EHB Ex cution Hazard Barter Stall until execution hazards are cleared Rt Status EI Enable Interrupts Status p 1 if SR 2 PC ErrorEPC else ERET Return from Exception PC EPC SR 1 0 SR 2 0 LL 0 EXT Extract Bit Field Rt ExtractField Rs msbd sb IACK Interrupt Acknowledge Signal External Interrupt Controller INS Insert Bit Field Rt InsertField Rt Rs msb sb J Unconditional Jump PC PC 31 28 Il offset lt lt 2 GPR 31 Z2 PC 8 JAL Jump and Link PC PC 31 28 Il offset lt lt 2 Rd PC 8 JALR Jump and Link Register PC Rs Rd PC 8 PC Rs JALR HB Jump and Link Register with Hazard Barrier Stall until all execution and instruction hazards are cleared JR Jump Register PC Rs 242 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights r
302. n See the table below PageMask Page Size Even Odd Bank Select Bit 00 0000 0000 0000 0000 IKB VAddr 10 00 0000 0000 0000 0011 4KB 00 0000 0000 0000 1111 16KB VAddr 14 00 0000 0000 0011 1111 64KB 00 0000 0000 1111 1111 256KB 00 0000 0011 1111 1111 1MB VAddr 20 00 0000 1111 1111 1111 4MB 00 0011 1111 1111 1111 16MB 00 1111 1111 1111 1111 64MB VAddr 26 11_1111_1111_1111_1111 256MB VAddr 28 The PageMask column above shows all the legal values for PageMask Because each pair of bits can only have the same value the physical entry in the JTLB will only save a compressed version of the PageMask using only 8 bits This is however transparent to software which will always work with a 18 bit field PageMask 28 11 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 43 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 3 Memory Management 44 Table 3 6 TLB Tag Entry Fields Continued Field Name Description VPN2 31 13 VPN2X 12 11 Virtual Page Number divided by 2 This field contains the upper bits of the virtual page number Because it represents a pair of TLB pages it is divided by 2 Bits 31 25 are always included in the TLB lookup comparison Bits 24 13 are included depending on the page size defined by PageMask Extension to the VPN2 field to support 1KB pages Global Bit When set indicates that
303. n 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 7 EJTAG Trace for a detailed description While working closely together the two parts of EJTAG Trace are controlled separately by software Figure 9 5 shows an overview of the EJTAG Trace modules within the core CPO control bus Control EJTAG TAP access Bas path Hose Pipeline specific Pipeline independant PDtrace module PDtrace Trace Contol Block TCB module Interface Back stall to Di ipeline mm mm mm PR Trace I On chip Le Trace compression Trace gt Extracted Pipeline D A information extraction and Memory AKE allignment e optional P boundary m4k top Figure 9 5 EJTAG Trace modules in the 4KE core To some extent the two modules both provide similar trace control features but the access to these features is quite different The PDtrace controls can only be reached through access to CPO registers The TCB controls can only be reached through EJTAG TAP access The TCB can then control what is traced through the PDtrace Interface Before describing the EJTAG Trace implemented in the 4KE core some common terminology and basic features are explained The remaining sections of this chapter will then provide a more thorough explanation 9 7 1 Processor Modes Tracing can be enabled or disabled based on various processor modes This section precisely descri
304. n breakpoint ASID value for a compare R W Undefined MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 177 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support 9 2 8 5 Instruction Breakpoint Control n IBCn Register Compliance Level Implemented only for implemented instruction breakpoints The Instruction Breakpoint Control n JBCn register controls the setup of instruction breakpoint n IBCn Register Format 31 24 23 22 3 21 0 Res ASID Res TE BE use Table 9 11 IBCn Register Field Descriptions Fields Description Read Write Reset State Res 31 24 Must be written as zero returns zero on read R 0 Use ASID value in compare for instruction breakpoint n 4KEc core R W ASIDuse 23 0 Don t use ASID value in compare Undefined 4KEm 4KEp 1 Use ASID value in compare cores 0 Res 22 3 Must be written as zero returns zero on read R 0 Use instruction breakpoint n as triggerpoint TE 2 0 Don t use it as triggerpoint R W 0 1 Use it as triggerpoint Res 1 Must be written as zero returns zero on read R 0 Use instruction breakpoint n as breakpoint BE 0 0 Don t use it as breakpoint R W 0 1 Use it as breakpoint 178 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 2 Hardware Breakpoints 9 2 9 Data Breakpoint Registe
305. n each instruction If excluded the number of bits required in the trace information from the TCB is reduced and each trace word will only contain information from completing instructions 9 7 10 Trace Message Format The TCB collects trace information every cycle from the PDtrace interface This information is collected into six different Trace Formats TF1 to TF6 The definition of these Trace Formats is proprietary and will not be released at this time One important feature is that all Trace Formats have at least one non zero bit 9 7 11 Trace Word Format After the PDtrace data has been turned into Trace Formats the trace information must be streamed to either on chip trace memory or to the trace probe Each of the major Trace Formats are of different size This complicates how to store this information into an on chip memory of fixed width without too much wasted space It also complicates how to transmit data through a fixed width trace probe interface to off chip memory To minimize memory overhead and or bandwidth loss the Trace Formats are collected into Trace Words of fixed width A Trace Word TW is defined to be 64 bits wide An empty invalid TW is built of all zeros A TW which contains one or more valid TF s is guaranteed to have a non zero value on one of the four least significant bits 3 0 During operation of the TCB each TW is built from the TF s generated each clock cycle When all 64 bits are used the TW is full and
306. n is taken To minimize the micro TLB miss penalty the JTLB is looked up in parallel with the DTLB for data references This results in a one cycle stall for a DTLB miss and a two cycle stall for an ITLB miss The 4KEm and 4KEp cores implement a FM T based MMU instead of a TLB based MMU The FMT replaces the JTLB ITLB and DTLB in the 4KEc core The FMT performs a simple translation to get the physical address from the virtual address Refer to Chapter 3 Memory Management on page 33 for more information on the FMT 6 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 1 2 4KE Block Diagram Figure 1 2 on page 7 shows how the address translation mechanism interacts with cache access The JTLB in this figure is only present on the 4KEc core Virtual Address Instruction Address ITLB FMT Comparator Calculator Instruction Hit Miss Data Hit Miss Data Address DTLB FMT Calculator Comparator Virtual Address 1 JTLB only exists in the 4KEc core 2 ITLB DTLB implemented in the 4KEc core only FMT implemented inthe 4KEm and 4KEp cores e Virtual Physical Instruction Addres Addes Address Calculator Instn SRAM interface Data Data REN SRAM Address Calculator Virtual Physical Address Address Figure 1 2 Address Translation During a Cache Access 1 2 1 5 Cache Control
307. n or a trigger indication The BE and or TE bits in the JBCn or DBCn registers are used to enable the breakpoints Debug software should not configure breakpoints to compare on an ASID value unless a TLB is present in the implementation MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 169 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support 170 9 2 5 1 Conditions for Matching Instruction Breakpoints When an instruction breakpoint is enabled that breakpoint is evaluated for the address of every executed instruction in non debug mode including execution of instructions at an address causing an address error on an instruction fetch The breakpoint is not evaluated on instructions from a speculative fetch or execution nor for addresses which are unaligned with an executed instruction A breakpoint match depends on the virtual address of the executed instruction PC which can be masked at bit level and match also can include an optional compare of ASID value The registers for each instruction breakpoint have the values and mask used in the compare and the equation that determines the match is shown below in C like notation IB match IBCnasgtpuse ASID IBASIDnasip amp amp all 1 s IBMnig PC IBAnjga The match indication for instruction breakpoints is always precise i e indicated on the instruction causing the IB match to be
308. n the EB RBErr or EB WBErr signals are asserted and may occur on an instruction that was not the source of the offending bus cycle Cause Register ExcCode Value IBE Error on an instruction reference DBE Error on a data reference Additional State Saved None Entry Vector Used General exception vector offset 0x180 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 4 8 Exceptions 4 8 14 Debug Software Breakpoint Exception A debug software breakpoint exception occurs when an SDBBP instruction is executed The DEPC register and DBD bit in the Debug register will indicate the SDBBP instruction that caused the debug exception Debug Register Debug Status Bit Set DBp Additional State Saved None Entry Vector Used Debug exception vector 4 8 15 Execution Exception System Call The system call exception is one of the nine execution exceptions All of these exceptions have the same priority A system call exception occurs when a SYSCALL instruction is executed Cause Register ExcCode Value Sys Additional State Saved None Entry Vector Used General exception vector offset 0x180 4 8 16 Execution Exception Breakpoint The breakpoint exception is one of the nine execution exceptions All of these exceptions have the same priority A breakpoint exception occurs when a BREAK instruction is executed Cause Re
309. n vector offset 0x180 4 8 21 Execution Exception Implementation Specific 2 exception The Implementation Specific 2 exception is one of the nine execution exceptions All of these exceptions have the same priority An implementation specific 2 exception occurs when a valid Coprocessor 2 instruction cause an implementation specific 2 exception in the Coprocessor 2 Cause Register ExcCode Value IS2 Additional State Saved Depending on the Coprocessor 2 implementation additional state information of the exception can be saved in a Coprocessor 2 control register Entry Vector Used General exception vector offset 0x180 4 8 22 Execution Exception Integer Overflow The integer overflow exception is one of the nine execution exceptions All of these exceptions have the same priority An integer overflow exception occurs when selected integer instructions result in a 2 s complement overflow Cause Register ExcCode Value Ov Additional State Saved None Entry Vector Used General exception vector offset 0x180 4 8 23 Execution Exception Trap The trap exception is one of the nine execution exceptions AII of these exceptions have the same priority A trap exception occurs when a trap instruction results in a TRUE value Cause Register ExcCode Value Tr Additional State Saved None MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 79 Copyright 2000 2002 MIPS Technologies Inc All
310. nal move instructions MOVZ MOVN Prefetch instruction PREF MIPS32 Enhanced Architecture Release 2 Features Vectored interrupts and support for an external interrupt controller Programmable exception vector base Atomic interrupt enable disable GPR shadow sets Bit field manipulation instructions Improved virtual memory support smaller page sizes and hooks for more extensive page table manipulation e MIPS16e Application Specific Extension 16 bit encodings of 32 bit instructions to improve code density Special PC relative instructions for efficient loading of addresses and constants Data type conversion instructions ZEB SEB ZEH SEH Compact jumps JRC JALRC Stack frame set up and tear down macro instructions SAVE and RESTORE Programmable Cache Sizes Individually configurable instruction and data caches Sizes from 0 up to 64 Kbytes Direct mapped or 2 3 4 Way set associative Loads that miss in the cache are blocked only until critical word is available Supports Write back with write allocation and Write through with or without write allocation 128 bit 16 byte cache line size word sectored suitable for standard 32 bit wide single port SRAM Virtually indexed physically tagged Cache line locking support Non blocking prefetches 2 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Tech
311. nd are thus described in parallel in the following The term hardware is not applied to breakpoint unless required to distinguish it from software breakpoint There are two types of simple hardware breakpoints implemented in the 4KE cores Instruction breakpoints and Data breakpoints A core may be configured with the following breakpoint options No data or instruction breakpoints Two instruction and one data breakpoint Four instruction and two data breakpoints 9 2 1 Features of Instruction Breakpoint Instruction breaks occur on instruction fetch operations and the break is set on the virtual address on the bus between the CPU and the instruction cache Instruction breaks can also be made on the ASID value used by the MMU Finally a mask can be applied to the virtual address to set breakpoints on a range of instructions Instruction breakpoints compare the virtual address of the executed instructions PC and the ASID with the registers for each instruction breakpoint including masking of address and ASID When an instruction breakpoint matches a debug exception and or a trigger is generated An internal bit in the instruction breakpoint registers is set to indicate that the match occurred 9 2 2 Features of Data Breakpoint Data breakpoints occur on load store transactions Breakpoints are set on virtual address and ASID values similar to the Instruction breakpoint Data breakpoints can be set on a load a store or both Data bre
312. nel mode when the most significant three bits of the virtual address are 1005 32 bit ksegO virtual address space is selected it is the 22 byte 512 MByte kernel virtual space located at addresses 0x8000 0000 OXOFFF FFFF References to ksegO are unmapped the physical address selected is defined by subtracting 0x8000 0000 from the virtual address The KO field of the Config register controls cacheability 3 2 3 3 Kernel Mode Kernel Space 1 kseg1 In Kernel mode when the most significant three bits of the 32 bit virtual address are 1015 32 bit kseg1 virtual address space is selected ksegl is the 27 byte 512 MByte kernel virtual space located at addresses 0xA000 0000 OxBFFF_FFFF References to kseg1 are unmapped the physical address selected is defined by subtracting 0xA000_0000 from the virtual address Caches are disabled for accesses to these addresses and physical memory or memory mapped I O device registers are accessed directly 3 2 3 4 Kernel Mode Kernel Space 2 kseg2 In Kernel mode when UM 0 ERL 1 or EXL 1 in the Status register and DM 0 in the Debug register and the most significant three bits of the 32 bit virtual address are 1105 32 bit kseg2 virtual address space is selected In the 4KEm and 4KEp processor cores this 2 _byte 512 MByte kernel virtual space is located at physical addresses 0xC000_0000 OxDFFF_FFFF In the 4KEc processor core this space is mapped through the TLB 3 2 3 5 Kernel Mode
313. nless the effective data rate of the Trace Probe interface is at least 64 bits per core clock cycle As a practical matter the amount of data to the TCB can be minimized by only tracing PC information and excluding any cycle accurate information This is explained in Section 9 12 2 Handling of Fifo overflow in the PDtrace module and below in Section 9 12 4 Adding cycle accurate information to the trace With this setting a data rate of 8 bits per core clock cycle is usually sufficient No guarantees can be given here however as heavy interrupt activity can increase the number of unpredictable jumps considerably 9 12 3 1 Probe width and Clock ratio settings The actual number of data pins 4 8 or 16 is defined by the TCBCONFIGpyw field Furthermore the frequency of the Trace Probe can be different from the core clock frequency The trace clock OR CLK is a double data rate clock This means that the data pins TR DATA change their value on both edges of the trace clock When the trace clock is running at clock ratio of 1 2 one half of core clock the data output registers are running a core clock frequency The clock ratio is set in the TCBCONTROLB cp field The legal range for the clock ratio is defined in TCBCONFIGcRmax and TCBCONFIG gwi both values inclusive If TCBCONTROLB cp is set to an unsupported value the result is UNPREDICABLE The maximum possible value for TCBCONFIG Cgwa is 8 1 TR CLK is running 8 times faster than core
314. nologies Inc All rights reserved 1 1 Features Scratchpad RAM support Replace one way of instruction cache and or data cache Maximum 20 bit index 1M address Memory mapped registers attached to scratchpad port can be used as a coprocessor interface R4000 Style Privileged Resource Architecture Count compare registers for real time timer interrupts Instruction and data watch registers for software breakpoints Programmable Memory Management Unit 4KEc core only 16 dual entry MIPS32 style JTLB with variable page sizes 4 entry instruction TLB 4 entry data TLB Programmable Memory Management Unit 4KEm and 4KEp cores only Simple Fixed Mapping Translation FMT Address spaces mapped using register bits Simple Bus Interface Unit BIU All I Os fully registered Separate unidirectional 32 bit address and data buses Two 16 byte collapsing write buffers CorExtend User Defined Instruction capability access to this feature is available in the 4KE Pro cores and requires a separate license Optional support for the CorExtend feature allows users to define and add instructions to the core as a build time option Single or multi cycle instructions Source operations from register immediate field or local state Destination to a register or local state Full featured Coprocessor 2 Interface Almost all I Os registered Separate unidirectional 32 bi
315. notify MIPS Technologies Inc when one of these encodings is used If no instruction is encoded with this value executing such an instruction must cause a Reserved Instruction Exception SPECIAL2 encodings or coprocessor instruction encodings for a coprocessor to which access is allowed or a Coprocessor Unusable Exception coprocessor instruction encodings for a coprocessor to which access is not allowed Field codes marked with this symbol represent an EJTAG support instruction and implementation of this encoding is optional for each implementation If the encoding is not implemented executing such an instruction must cause a Reserved Instruction Exception If the encoding is implemented it must match the instruction encoding as shown in the table Operation or field codes marked with this symbol are reserved for MIPS Application Specific Extensions If the ASE is not implemented executing such an instruction must cause a Reserved Instruction Exception Operation or field codes marked with this symbol are obsolete and will be removed from a future revision of the MIPS64 ISA Software should avoid using these operation or field codes MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 273 Chapter 12 MIPS16 Application Specific Extension to the MIPS32 Instruction Set 274 Table 12 2 MIPS16 Encoding of the Opcode Field
316. ns It performs any multiply using 32 cycles in an iterative 1 bit per clock algorithm Divide operations are also implemented with a simple 1 bit per clock iterative algorithm no early in and require 35 clock cycles to complete An attempt to issue a subsequent MDU instruction while a multiply divide is still active causes a pipeline stall until the operation is completed The 4KE implements an additional multiply instruction MUL which specifies that lower 32 bits of the multiply result be placed in the register file instead of the HI LO register pair By avoiding the explicit move from LO MFLO instruction required when using the LO register and by supporting multiple destination registers the throughput of multiply intensive operations is increased Two instructions multiply add MADD MADDU and multiply subtract MSUB MSUBU are used to perform the multiply add and multiply subtract operations The MADD instruction multiplies two numbers and then adds the product to the current contents of the HI and LO registers Similarly the MSUB instruction multiplies two operands and then subtracts the product from the HI and LO registers The MADD MADDU and MSUB MSUBU operations are commonly used in Digital Signal Processor DSP algorithms 1 2 1 3 System Control Coprocessor CP0 In the MIPS architecture CPO is responsible for the virtual to physical address translation cache protocols the exception control system the processor s diagnostics c
317. ns are a combination of a vector offset and a vector base address In Release 1 of the architecture the vector base address was fixed In Release 2 of the architecture software is allowed to specify the vector base address via the EBase register for exceptions that occur when Statuspry equals 0 Table 4 5 gives the vector base address as a function of the exception and whether the BEV bit is set in the Status register Table 4 6 gives the offsets from the vector base address as a function of the exception Note that the IV bit in the Cause register causes Interrupts to use a dedicated exception vector offset rather than the general exception vector For implementations of Release 2 of the Architecture Table 4 4 gives the offset from the base address in the case where Statuspggy 0 and Causeyy 1 For implementations of Release 1 of the architecture in which Causeyy 1 the vector offset is as if IntCtlys were 0 Table 4 7 combines these two tables into one that contains all possible vector addresses as a function of the state that can affect the vector selection To avoid complexity in the table the vector address value assumes that the EBase register as implemented in Release 2 devices is not changed from its reset state and that IntCtlys is 0 Table 4 5 Exception Vector Base Addresses Statusgry Exception Reset Soft Reset NMI 16 BFCO 0000 EJTAG Debug with ProbEn 0 in the EJTAG_Control_register 16 BFC0 0480 EJTAG Deb
318. nstruction Interlocks Section 2 13 Hazards 2 1 Pipeline Stages The pipeline consists of five stages nstruction I stage Execution E stage Memory M stage Align A stage Writeback W stage A 4KE core implements a Bypass mechanism that allows the result of an operation to be sent directly to the instruction that needs it without having to write the result to the register and then read it back Figure 2 1 on page 12 shows the operations performed in each pipeline stage of the 4KE processor MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 11 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 2 Pipeline I Tag and Data read l Cache l pl FTLB Look up W Dec Instruction Decode l i RegR Register file read l Lac Tac Instruction Address Calculation stage 1 and 2 l l Arithmetic Logic and Shift operations ALU Op AE D Ac Data Address Calculation i i US DGacne D Tag and Data read i ZB D TLB D TLB Look up x A gt E Bypass i o Align Load data aligner n N 1y Reaw Register file write d bau 7 wou Res Regw pw uc MUL instruction l 2 GPA Carry Propagate Adder Mult 18x18 EPA i MDU Res amp Mult Macc Mulia 2d SE Accumulate instructions gt Divide Divide instructions i d Mut 32x
319. nstruction Latencies Operand Signs of Instruction Sequence 1st Instruction Latency Rs Rt 1st Instruction 2nd Instruction Clocks MADD MADDU any any MULT MULTU MSUB MSUBU or 32 MFHI MFLO MADD MADDU any any Ee MSUB MSUBU or 34 MFHI MFLO any any MUL Integer operation 32 any any DIVU MFHI MFLO 33 pos pos DIV MFHI MFLO 33 any neg DIV MFHI MFLO i neg pos DIV MFHI MFLO 35 any any MFHI MFLO Integer operation 2 any any MTHI MTLO EE 1 Note 1 Integer Operation refers to any integer instruction that uses the result of a previous MDU operation MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 2 6 MDU Pipeline 4KEp Core 2 6 1 Multiply 4KEp Core Multiply operations are executed using a simple iterative multiply algorithm Using Booth s approach this algorithm works for both positive and negative operands The operation uses 32 cycles in Mur stage to complete a multiplication The register writeback to HI and LO are done in the A stage For MUL operations the register file writeback is done in the Wmpvu stage Figure 2 13 shows the latency for a multiply operation The repeat rate is 33 cycles as a second multiply can be in the first Mypvu stage when the first multiply is in Ampu stage Clock 1 2 33 34 35 AR E Stage gt Myou Stage gt Auou Stage P 4 Wyou Stage gt Add sub shi
320. nted if the Trace Control Block is present If no TCB is present then this instruction will select the Bypass register MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 193 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support 9 3 3 12 TCBCONTROL B Instruction This instruction is used to select the TCBCONTROLB register to be connected between TDI and TDO This register is only implemented if the Trace Control Block is present If no TCB is present then this instruction will select the Bypass register 9 3 3 13 TCBDATA Instruction This instruction is used to select the TCBDATA register to be connected between TDI and TDO This register is only implemented if the Trace Control Block is present If no TCB is present then this instruction will select the Bypass register It should be noted that the TCBDATA register is only an access register to other TCB registers The width of the TCBDATA register is dependent on the specific TCB register 9 4 EJTAG TAP Registers 194 The EJTAG TAP Module has one Instruction register and a number of data registers all accessible through the TAP 9 4 1 Instruction Register The Instruction register is accessed when the TAP receives an Instruction register scan protocol During an Instruction register scan operation the TAP controller selects the output of the Instruction register to drive the TDO pin The shift register consists of a s
321. ntrol Registers 9 3 3 8 EJTAGBOOT Instruction When the EJTAGBOOT instruction is given and the Update IR state is left then the reset values of the ProbTrap ProbEn and EjtagBrk bits in the EJTAG Control register are set to 1 after a hard or soft reset This EJTAGBOOT indication is effective until a NORMALBOOT instruction is given TRST_N is asserted or a rising edge of TCK occurs when the TAP controller is in Test Logic Reset state Itis possible to make the CPU go into debug mode just after a hard or soft reset without fetching or executing any instructions from the normal memory area This can be used for download of code to a system which have no code in ROM The Bypass register is selected when the EJTAGBOOT instruction is given 9 3 3 9 NORMALBOOT Instruction When the NORMALBOOT instruction is given and the Update IR state is left then the reset value of the ProbTrap ProbEn and EjtagBrk bits in the EJTAG Control register are set to 0 after hard or soft reset The Bypass register is selected when the NORMALBOOT instruction is given 9 3 3 10 FASTDATA Instruction This selects the Data and the Fastdata registers at once as shown in Figure 9 3 TDI Fastdata TDO Figure 9 3 TDI to TDO Path when in Shift DR State and FASTDATA Instruction is Selected 9 3 3 11 TCBCONTROLA Instruction This instruction is used to select the TCBCONTROLA register to be connected between TDI and TDO This register is only impleme
322. ntrols tracing functionality Trace is turned on when the following expression evaluates true TraceControlyg and TraceControlg 4 or not TraceControlrs and TCBCONTROLAg and MatchEnable or TriggerEnable where MatchEnable TraceControl4gs and TraceControly and UserMode or TraceControly and KernelMode or TraceControl and ExceptionMode or TraceControlp and DebugMode or not TraceControlyg and TCBCONTROLA and UserMode or TCBCONTROLA and KernelMode or TCBCONTROLA amp and ExceptionMode or MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 223 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support TCBCONTROLApy and DebugMode and where TriggerEnable lt DBCizg and DBSgs 1 and TraceBPCpg and IraceBPCppgpon 1 or IBCirp and IBSps i and TraceBPCigp and TIraceBPCi gpon i 1 As seen in the expression above trace can be turned on only if the master switch TraceControlo or TCBCONTROLAQ is first asserted Once this is asserted there are two ways to turn on tracing The first way the MatchEnable expression uses the input enable signals from the TCB or the bits in the TraceControl register This tracing is done over general program areas For example all of the user level code for a particular process if ASID is spec
323. ocessor 0 CPR O n sel Rt MTC2 Move To Coprocessor 2 CPR 2 n sel 3 9 Rt MTHC2 Move To High Word Coprocessor 2 CPR 2 n sel g3 35 Rt MTHI Move To HI HI Rs MTLO Move To LO LO Rs MUL Multiply with register write a E TEENER MULT Integer Multiply HI LO int Rs int Rd 243 All rights reserved Chapter 11 MIPS32 4KE Processor Core Instructions 244 Table 11 10 Instruction Set Continued Instruction Description Function MULTU Unsigned Multiply HI LO uns Rs uns Rd No Operation NOP Assembler idiom for SLL r0 r0 r0 NOR Logical NOR Rd Rs Rt OR Logical OR Rd Rs Rt ORI Logical OR Immediate Rt Rs Immed PREF Prefetch Load Specified Line into Cache RDHWR Read HardWare Register Rt HWR Rd RDPGPR Read GPR from Previous Shadow Set Rd SGPR SRSCtlpgg Rt ROTR Rotate Word Right Rd Rt 4 9l Rt31 sa ROTRV Rotate Word Right Variable Rd Rtg 1 0l Rt31 Rs SB Store Byte byte Mem Rs offset Rt if LL 1 SC Store Conditional Word mem Rxoffs Rt Rt LL SDBBP Software Debug Breakpoint Trap to SW Debug Handler SEB Sign Extend Byte Rd SignExtend Rt o SEH Sign Extend Half Rd SignExtend Rt s al SH Store Halfword half Mem Rs offset Rt SLL Shift Left Logical Rd Rt lt lt sa SLLV Shift Left Logical Variable Rd Rt lt lt Rs 4 0 if int Rs lt int Rt Rd 1 SLT Set on Less Than else Rd 0 if int Rs lt int Immed SLTI Set
324. oding 2 Ways essssssseseeeeseeeeeeeenen rennen rennen nennen nennen ne teeen nt tne enne tne enne terere trennen 160 Table 9 1 Debug Control Register Field Descriptions essent enne nere nennen ene 166 Table 9 2 Overview of Status Register for Instruction Breakpoints eese nennen ene 168 Table 9 3 Overview of Registers for Each Instruction Breakpoint nere 169 Table 9 4 Overview of Status Register for Data Breakpomts ener nnne nennen nene 169 Table 9 5 Overview of Registers for each Data Breakpoint eese nennen nennen nennen nnne 169 Table 9 6 Addresses for Instruction Breakpoint Registers eeeseseeeseee eene enne nre nene 172 Table 9 7 IBS Register Field Descriptions os iet n etit ei exten Petre eee ee e rfe eter eee n 174 Table 9 8 IBAn Register Field Descrpttons enne eene nennen nennen ne tneenne terere treten eer en rennen 175 Table 9 9 BMri Register Field Descriptions tenet der pete Ee Pope tee eb ien eee eee ee pie i eter n 176 Table 9 10 IBASIDn Register Field Descriptions sess nennen teret treten rennen rennen 177 Table 9 11 JBC i Register Field Descriptions inte ettet tremere tete re nei oe i 178 Table 9 12 Addresses for Data Breakpoint Registers nennen nennen enitn ene 179 Table 9 13 DBS Register Field Descrptions uio cer rect irt eme pee i tere ee cete he tenen 180 Table 9 14 DBAn Register Field Descriptions sessi teetnne trente treten rere 181 Tabl
325. ol register TCBTRIGx see Section 9 9 9 TCBTRIGx Register Reg 16 23 on page 220 9 11 4 Trigger Action Unit The TCB has four possible trigger actions l Chip level trigger output TC ChipTrigOut 2 Probe trigger output TR TRIGOUT 3 Trace information Put a programmable byte into the trace stream from the TCB 4 Start End or About delayed end control of the TCBCONTROLBgy bit The basic function of the trigger actions is explained in Section 9 9 9 TCBTRIGx Register Reg 16 23 on page 220 Please also read the next Section 9 11 5 Simultaneous triggers 9 11 5 Simultaneous triggers Two or more triggers can fire simultaneously The resulting behavior depends on trigger action set for each of them and whether they should produce a TF6 trace information output or not There are two groups of trigger actions Prioritized and OR ed 9 11 5 1 Prioritized trigger actions For prioritized simultaneous trigger actions the trigger control unit which has the lowest number takes precedence over the higher numbered units The x in TCBTRIGx registers defines the number The oldest trigger takes precedence over everything The following trigger actions are prioritized when two or more units fire simultaneously Trigger Start End and About type triggers TCBTRIG field set to 00 01 or 10 which will assert de assert the TCBCONTROLBxy bit The About trigger is delayed and will always change TCBCONTROLBygy because it is the o
326. ologies Inc All rights reserved 9 3 Test Access Port TAP 1 C Test Logic Res 0 o Run Test Idle H DR Select IR Scan Figure 9 1 TAP Controller State Diagram 9 3 2 1 Test Logic Reset State In the Test Logic Reset state the boundary scan test logic is disabled The test logic enters the Test Logic Reset state when the TMS input is held HIGH for at least five rising edges of TCK The BYPASS instruction is forced into the instruction register output latches during this state The controller remains in the Test Logic Reset state as long as TMS is HIGH 9 3 2 2 Run Test Idle State The controller enters the Run Test Idle state between scan operations The controller remains in this state as long as TMS is held LOW The instruction register and all test data registers retain their previous state The instruction cannot change when the TAP controller is in this state When TMS is sampled HIGH on the rising edge of TCK the controller transitions to the Select DR state 9 3 2 3 Select DR Scan State This is a temporary controller state in which all test data registers selected by the current instruction retain their previous state If TMS is sampled LOW at the rising edge of TCK then the controller transitions to the Capture DR state A HIGH on TMS causes the controller to transition to the Select IR state The instruction cannot change while the TAP controller is in this state 9 3 2 4 Select IR Scan State Th
327. on Indicates that a debug data break exception occurred on a store Cleared on exception in debug mode DDBS 3 R Undefined 0 No debug data exception on a store 1 Debug instruction exception on a store Indicates that a debug data break exception occurred on a load Cleared on exception in debug mode DDBL 2 R Undefined 0 No debug data exception on a load 1 Debug instruction exception on a load Indicates that a debug software breakpoint exception occurred Cleared on exception in debug mode DBp 1 R Undefined 0 No debug software breakpoint exception 1 Debug software breakpoint exception Indicates that a debug single step exception occurred Cleared on exception in debug mode DSS 0 R Undefined 0 No debug single step exception 1 Debug single step exception MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 135 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers 5 2 29 Trace Control Register CP0 Register 23 Select 1 The TraceControl register configuration is shown below Note the special behavior of the ASID M ASID and G fields for the 4KEm and 4KEp processors This register is only implemented if the EJTAG Trace capability is present Figure 5 31 Trace Control Register Format 31 30 29 28 27 26 25 24 23 22 21 20 13 12 5 4 3 1 0 TSIUT 0 TB IIOJD E K S U ASID M ASID G Mode On Table 5 35 TraceControl Register Field Descriptions
328. on 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions 5 2 1 Index Register CPO Register 0 Select 0 The ndex register is a 32 bit read write register that contains the index used to access the TLB for TLBP TLBR and TLBWI instructions The width of the index field is implementation dependent as a function of the number of TLB entries that are implemented The minimum value for TLB based MMUs is Ceiling Log gt TLBEntries The operation of the processor is UNDEFINED if a value greater than or equal to the number of TLB entries is written to the ndex register This register is only valid with the TLB 4KEc core It is reserved if the FM is implemented 4KEm and 4KEp Figure 5 1 Index Register Format 31 30 4 3 0 P 0 Index Table 5 3 Index Register Field Descriptions Fields Read Description Write Reset State Probe Failure Set to 1 when the previous TLBProbe P 3l TLBP instruction failed to find a match in the TLB R Undefined 0 30 4 Must be written as zeros returns zeros on reads 0 0 Index 3 0 Index to the TLB entry affected by the TLBRead and R W Undefined TLBWrite instructions MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 91 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers 92 5 2 2 Random Register CPO Register 1 Select 0 The Random register is a read only
329. on Less Than Immediate Ze g i Rt 0 if uns Rs lt uns Immed SLTIU Set on Less Than Immediate Unsigned Eo e Rt 0 if uns Rs lt uns Immed SLTU Set on Less Than Unsigned Be S Rd 0 SRA Shift Right Arithmetic Rd int Rt gt gt sa SRAV Shift Right Arithmetic Variable Rd int Rt gt gt Rs 4 0 SRL Shift Right Logical Rd uns Rt gt gt sa SRLV Shift Right Logical Variable Rd uns Rt gt gt Rs 4 0 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 11 3 MIPS32 Instruction Set for the 4KE core Table 11 10 Instruction Set Continued Instruction Description Function SSNOP Superscalar Inhibit No Operation Nop SUB Integer Subtract Rt int Rs int Rd SUBU Unsigned Subtract Rt uns Rs uns Rd SW Store Word Mem Rs offset Rt SWC2 Store Word From Coprocessor 2 Mem Rs offset CPR 2 n 0 SWL Store Word Left See SWL instruction description SWR Store Word Right See SWR instruction description SYNC Synchronize See SYNC instruction below SYNCI Synchronize Caches to Make Instruction Force D writeback and I Writes Effective invalidate on specified address SYSCALL System Call SystemCallException d if Rs Rt TEQ Trap if Equal TrapException if Rs int Immed TEQI Trap if Equal Immediate TrapException if int Rs gt int Rt TGE Trap if Greater Than o
330. only Figure 5 26 shows the format of the Config3 register Table 5 30 describes the Config3 register fields Figure 5 26 Config3 Register Format 31 30 7 6 5 4 3 2 1 0 0 M 000 0000 0000 0000 0000 0000 0 VEICVIn SP 0 SM TL Table 5 30 Config3 Register Field Descriptions Read Description Write Reset State This bit is reserved to indicate that a Config4 register is M 3l present With the current architectural definition this bit should always read as a 0 nu 30 7 3 2 Must be written as zeros returns zeros on read qe o y Support for an external interrupt controller is implemented Encoding Meaning 0 Support for EIC interrupt mode is not implemented Externally VEC 8 1 Support for EIC interrupt mode is We Set implemented The value of this bit is set by the static input SI EICPresent This allows external logic to communicate whether an external interrupt controller is attached to the processor or not Vectored interrupts implemented This bit indicates whether vectored interrupts are implemented Encoding Meaning Vint 5 0 Vector interrupts are not implemented R 1 1 Vectored interrupts are implemented On the 4KE core this bit is always a 1 since vectored interrupts are implemented Small 1KByte page support is implemented and the PageGrain register exists This bit will always read as 0 on the 4KEm and 4KEp cores
331. ontrol Fields Table 9 30 TCBCONTROLB Register Field Descriptions Continued Name Bits Description Read Write Reset State Cal Calibrate off chip trace interface If set to one the off chip trace pins will produce the following pattern in consecutive trace clock cycles If more than 4 data pins exist the pattern is replicated for each set of 4 pins The pattern repeats from top to bottom until the Cal bit is de asserted Calibrations pattern 3 2 1 0 e o La CO CH CO CH o olco olo o pins E of TR_DATA o o c o oil j o o oco coc o o This pattern is replicated for every 4 bits COU tal Fa o Note The clock source of the TCB and PIB must be running This bit is reserved if off chip trace option is not implemented 6 3 Reserved Must be written as zero returns zero on read CA OfC Cycle accurate trace When set to 1 the trace will include stall information When set to 0 the trace will exclude stall information and remove bit zero from all transmitted TF s The stall information included excluded is TF6 formats with TCBcode 0001 and 0101 All TFI formats If set to 1 trace is sent to off chip memory using TR DATA pins If set to 0 trace info is sent to on chip memory This bit is read only if a single memory option
332. or Cores Software User s Manual Revision 02 00 247 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Perform Cache Operation CACHE Figure 11 1 Usage of Address Fields to Select Index and Way OffsetBit uS IndexBit XS 0 A TLB Refill and TLB Invalid both with cause code equal TLBL exception can occur on any operation For index operations where the address is used to index the cache but need not match the cache tag software should use unmapped addresses to avoid TLB exceptions This instruction never causes TLB Modified exceptions nor TLB Refill exceptions with a cause code of TLBS The effective address may be an arbitrarily aligned by address The CACHE instruction never causes an Address Error Exception due to an non aligned address A Cache Error exception may occur as a byproduct of some operations performed by this instruction For example if a Writeback operation detects a cache or bus error during the processing of the operation that error is reported via a Cache Error exception Similarly a Bus Error Exception may occur if a bus operation invoked by this instruction is terminated in an error However cache error exceptions should must be triggered by an Index Load Tag or Index Store tag operation as these operations are used for initialization and diagnostic purposes An address Error Exception with cause code equal AdEL occurs if the effective address references a portion of the kernel address
333. or to an off chip trace probe The trace of program flow is highly flexible and can include instruction program counter as well as data addresses and data values The trace features provides a powerful software debugging mechanism Refer to Chapter 9 EJTAG Debug Support on page 165 for more information on the EJTAG features 1 2 2 5 Coprocessor 2 Interface CP2 The optional coprocessor 2 CP2 interface provides a full featured interface for a coprocessor It provides full support for all the MIPS32 COP2 instructions with the exception of the 64 bit Load Store instructions LDC2 SDC2 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 9 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 1 Introduction to the MIPS32 4KE Processor Core Family 10 The CP2 interface can provide access to a graphics accelerator coprocessor or a simple register file There is no support for the floating point coprocessor COPI which requires 64 bit data transfers Refer to Chapter 11 MIPS32 4KE Processor Core Instructions on page 237 for more information on the Coprocessor 2 supported instructions 1 2 2 6 CorExtend User Defined Instructions UDI This optional module contains if implemented support for CorExtend user defined instructions These instructions must be defined at build time for the 4KE core Access to UDI requires a separate license from MIPS and the core is then
334. ot prefetch data from a mapped location unless the translation for that location is present in the TLB Locations in memory pages that have not been accessed recently may not have translations in the TLB so prefetch may not be effective for such locations Prefetch does not cause addressing exceptions It does not cause an exception to prefetch using an address pointer value before the validity of a pointer is determined Prefetch operations have no effect on cache lines that were previously locked with the CACHE instruction MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 259 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Store Conditional Word SC 31 26 25 21 20 16 15 0 SC base rt offset 111000 6 5 5 16 Format SC rt offset base MIPS32 Purpose To store a word to memory to complete an atomic read modify write Description if atomic update then memory basetoffset amp rt rt lt 1 else rt 0 The LL and SC instructions provide primitives to implement atomic read modify write RMW operations for syn chronizable memory locations The 32 bit word in GPR rt is conditionally stored in memory at the location specified by the aligned effective address The 16 bit signed offset is added to the contents of GPR base to form an effective address The SC completes the RMW sequence begun by the preceding LL instruction executed on the processor To complete the RMW
335. owever for all hint values except for PrepareForStore and all effective addresses it neither changes the architecturally visible state nor does it alter the meaning of the program PREF does not cause addressing related exceptions If the address specified would cause an addressing exception the exception condition is ignored and no data movement occurs However even if no data is prefetched some action that is not architecturally visible such as writeback of a dirty cache line can take place PREF never generates a memory operation for a location with an uncached memory access type If PREF results in a memory operation the memory access type used for the operation is determined by the memory access type of the effective address just as it would be if the memory operation had been caused by a load or store to the effective address The Aint field supplies information about the way the data is expected to be used With the exception of PrepareFor Store a hint value cannot cause an action to modify architecturally visible state Any of the following conditions causes the core to treat a PREF instruction as a NOP A reserved hint value is used The address has a translation error The address maps to an uncacheable page In all other cases except when Aint equals 25 execution of the PREF instruction initiates an external bus read trans action PREF is a non blocking operation and does not cause the pipeline to stall while waiting for
336. pace identifier value and is used during the TLB comparison process to determine TLB match Because the ASID field is overwritten by a TLBR instruction software must save and restore the value of ASID around use of the TLBR This is especially important in TLB Invalid and TLB Modified exceptions and in other memory management software The VPNX2 and VPN2 fields of the EntryHi register are not defined after an address error exception and these fields may be modified by hardware during the address error exception sequence Software writes of the EntryHi register via MTCO do not cause the implicit write of address related fields in the BadVAddr Context registers This register is only valid with the TLB 4KEc core It is reserved if the FM is implemented 4KEm and 4KEp cores Figure 5 12 EntryHi Register Format 31 13 12 11 10 8 7 0 VPN2 VPN2X 0 ASID Table 5 15 EntryHi Register Field Descriptions Fields Read Description Write Reset State VA31_13 of the virtual address virtual page number 2 This field is written by hardware on a TLB exception or on a TLB read and is written by software before a TLB RW Undefined write In Release 2 of the Architecture the VPN2X field is an extension to the VPN2 field to support 1KB pages These bits are not writable by either hardware or software unless Config3sp 1 and PageGraingsp 1 If enabled for write this field contains VA 11 of the virtual address and
337. plications that do not require the full capabilities of a TLB The 4KEc and 4KEm Multiply Divide Unit MDU supports a maximum issue rate of one 32x16 multiply MUL MULT MULTU multiply add MADD MADDU or multiply subtract MSUB MSUBU operation per clock or one 32x32 MUL MADD or MSUB every other clock The MDU on the 4KEp core uses an area sensitive iterative algorithm The basic Enhanced JTAG EJTAG features provide CPU run control with stop single stepping and re start and with software breakpoints through the SDBBP instruction Additional EJTAG features instruction and data virtual address hardware breakpoints connection to an external EJTAG probe through the Test Access Port TAP and PC Data tracing may optionally be included The rest of this chapter provides an overview of the MIPS32 4KE processor core and consists of the following sections Section 1 1 Features MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 1 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 1 Introduction to the MIPS32 4KE Processor Core Family e Section 1 2 4KE Block Diagram 1 1 Features 5 stage pipeline 32 bit Address and Data Paths MIPS32 Compatible Instruction Set Multiply add and multiply subtract instructions MADD MADDU MSUB MSUBU Targeted multiply instruction MUL Zero and one detect instructions CLZ CLO Wait instruction WAIT Conditio
338. pp amp 1 WatchLo 0 WatchLog 0 WatchLoy lt 0 if InstructionInBranchDelaySlot then ErrorEPC PC 4 else ErrorEPC lt PC endif PC lt OxBFCO 0000 4 8 2 Soft Reset Exception A soft reset exception occurs when the SI Reset signal is asserted to the processor This exception is not maskable When a soft reset exception occurs the processor performs a subset of the full reset initialization Although a soft reset exception does not unnecessarily change the state of the processor it may be forced to do so in order to place the processor in a state in which it can execute instructions from uncached unmapped address space Since bus cache or other operations may be interrupted portions of the cache memory or other processor state may be inconsistent In addition to any hardware initialization required the following state is established on a soft reset exception The BEV TS SR NMI and ERL fields of the Status register are initialized to a specified state The ErrorEPC register is loaded with PC 4 if the state of the processor indicates that it was executing an instruction in the delay slot of a branch Otherwise the ErrorEPC register is loaded with PC Note that this value may or may not be predictable PC is loaded with OXBFCO 0000 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 4 8 Excep
339. pter 10 Instruction Set Overview I Type Immediate 31 2625 2120 1615 0 op S ot immediate J Type Jump 31 26 25 0 op target R Type Register 31 2625 2120 1615 1110 65 0 op rs rt rd sa funct op 6 bit operation code TS 5 bit source register specifier 5 bit target source destination register or branch condition Soe 16 bit immediate value branch displacement or address displacement target 26 bit jump target address rd 5 bit destination register specifier sa 5 bit shift amount funct 6 bit function field Figure 10 1 Instruction Formats 10 2 Load and Store Instructions Load and store instructions are immediate I type instructions that move data between memory and the general registers The only addressing mode that load and store instructions directly support is base register plus 16 bit signed immediate offset 10 2 1 Scheduling a Load Delay Slot A load instruction that does not allow its result to be used by the instruction immediately following is called a delayed load instruction The instruction slot immediately following this delayed load instruction is referred to as the load delay slot In a 4KE core the instruction immediately following a load instruction can use the contents of the loaded register however in such cases hardware interlocks insert additional real cycles Although not required the scheduling of load delay slots can be desirable both for performance and R Series processor co
340. ption appears as not executed with the exception that a load from the memory system does occur for a breakpoint with data value compare but the result of this load is discarded since the register file is not updated by the load If both data breakpoints without and with data value compare would match the same transaction and generate a debug exception then the following rules apply with respect to updating the BS n bits On both a load and store the BS n bits are required to be set for all matching breakpoints without a data value compare e Ona store the BS n bits are allowed but not required to be set for all matching breakpoints with a data value compare but either all or none of the BS n bits must be set for these breakpoints On a load then no of the BS n bits are allowed to be set since the load is not allowed to occur due to the debug exception from a breakpoint without a data value compare and a valid data value is therefore not returned Any BS n bit set prior to the match and debug exception are kept set since BS n bits are only cleared by debug software The debug handler usually returns to the instruction causing the debug data break exception whereby the instruction is re executed This re execution may result in a repeated load from system memory since the load may have occurred previously in order to evaluate the breakpoint as described above I O devices with side effects on loads must be able to allow such relo
341. ption vector is a minimum of 5 clock cycles More may be needed if a committed instruction has to complete before the exception can be taken i e an uncached load that has started on the bus must wait complete before the interrupt exception can be taken Register ExcCode Value Int Additional State Saved Table 4 10 Register States an Interrupt Exception Register State Value Cause indicates the interrupts that are pending Entry Vector Used See Section 4 3 2 Generation of Exception Vector Offsets for Vectored Interrupts on page 63 for the entry vector used depending on the interrupt mode the processor is operating in 4 8 8 Debug Instruction Break Exception A debug instruction break exception occurs when an instruction hardware breakpoint matches an executed instruction The DEPC register and DBD bit in the Debug register indicate the instruction that caused the instruction hardware breakpoint to match This exception can only occur if instruction hardware breakpoints are implemented Debug Register Debug Status Bit Set DIB MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 73 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 4 Exceptions and Interrupts 74 Additional State Saved None Entry Vector Used Debug exception vector 4 8 9 Watch Exception Instruction Fetch or Data Access The Watch facility provides a software debugging vehicle by ini
342. r Equal TrapException TGEI Trap if Greater Than or Equal Immediate pu gt int Immed rapException TGEIU Trap if Greater Than or Equal Immediate if uns Rs gt uns Immed Unsigned TrapException d if uns Rs uns Rt TGEU Trap if Greater Than or Equal Unsigned Trap xception TLBP Probe TLB for Matching Entry See TLBP instruction below TLBR Read Index for TLB Entry See TLBR instruction below TLBWI Write Indexed TLB Entry See TLBWI instruction below TLBWR Write Random TLB Entry See TLBWR instruction below TLT Trap if Less Than if in Rs lt nORt P TrapException TLTI Trap if Less Than Immediate cous lt int immed rapException TLTIU Trap if Less Than Immediate Unsigned Dd lt uns Immed rapException TLTU Trap if Less Than Unsigned poo DE rapException d if Rs Z Rt TNE Trap if Not Equal TrapException TNEI Trap if Not Equal Immediate zo in Immed rapException WAIT Wait for Interrupts Stall until interrupt occurs MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 245 Chapter 11 MIPS32 4KE Processor Core Instructions Table 11 10 Instruction Set Continued Instruction Description Function WRPGPR Write to GPR in Previous Shadow Set SGPR SRSCtlpss Rd Rt WSBH Word Swap Bytes within Halfwords RdzSwapBytesWithinHalfs Rt XOR Exclusive OR RdzRs Rt XORI Exclusive OR Immediate Rt Rs uns Immed 246
343. r one cycle MUL operations are special because it needs to stall the IU pipeline in order to maintain its register file write slot Consequently the MUL 16x16 or 32x16 operation will always force a one cycle stall of the IU pipeline and the MUL 32x32 will force a two cycle stall If the integer instruction immediately following the MUL operation uses its result an additional stall is forced on the IU pipeline MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 2 5 MDU Pipeline 4KEc and 4KEm Cores Table 2 2 lists the repeat rates peak issue rate of cycles until the operation can be reissued for multiply accumulate subtract instructions The repeat rates are listed in terms of pipeline clocks In this table repeat rate refers to the case where the first MDU instruction in the table below if back to back with the second instruction Table 2 2 4KEc Core MDU Instruction Repeat Rates Instruction Sequence Operand Size of Repeat 1st Instruction 1st Instruction 2nd Instruction Rate l MULT MULTU MADD MADDU 16 bit MADD MADDU MSUB MSUBU 1 MSUB MSUBU MULT MULTU MADD MADDU 32 bit MADD MADDU MSUB MSUBU 2 MSUB MSUBU Figure 2 6 below shows the pipeline flow for the following sequence 1 32x16 multiply Mult 2 Add 3 32x32 multiply Mult 4 Subtract Sub The 32x16 multiply operation requires one clock of each p
344. ray can be tested using the Index Store Tag CACHE SW and LW instructions First use Index Store Tag to set the initial state of the tags to valid with a known physical address PA Write the array using SW instructions to the PAs that are resident in the cache The value can then be read using LW instructions and compared to the expected data 7 6 5 D cache WS Array The dirty bits in this array will be tested when the data tag is tested The LRU bits can be tested using the same mechanism as the I cache WS array 160 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 7 7 Memory Coherence Issues 7 Memory Coherence Issues A cache presents coherency issues within the memory hierarchy which must be considered in the system design Since a cache holds a copy of memory data it is possible for another memory master to modify a memory location thus making other copies of that location stale if those copies are still in use A detailed discussion of memory coherence is beyond the scope of this document but following are a few related comments A 4KE processor contains no direct hardware support for managing coherency with respect to its caches so it must be handled via system design or software The 4KE data cache supports either write back or write through protocols In write through mode all data writes will eventually be sent to memory Due to write bu
345. re User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All right reserved Chapter 1 Introduction to the MIPS32 4KE Processor Core Family The MIPS32 4KE core from MIPS Technologies is a high performance low power 32 bit MIPS RISC processor core family intended for custom system on silicon applications The core is designed for semiconductor manufacturing companies ASIC developers and system OEMs who want to rapidly integrate their own custom logic and peripherals with a high performance RISC processor A 4KE core is fully synthesizable to allow maximum flexibility it is highly portable across processes and can easily be integrated into full system on silicon designs This allows developers to focus their attention on end user specific characteristics of their product The 4KE core is ideally positioned to support new products for emerging segments of the digital consumer network systems and information management markets enabling new tailored solutions for embedded applications The 4KE family has three members the 4KEc 4KEm and 4KEp cores The three devices differ mainly in the type of multiply divide unit MDU and the Memory Management Unit MMU The 4KEc core contains a fully associative Translation Lookaside Buffer TLB based MMU and pipelined MDU The 4KEm core contains a fixed mapping translation FMT mechanism in the MMU that is smaller and simpler than the TLB
346. register whose value is used to index the TLB during a TLBWR instruction The width of the Random field is calculated in the same manner as that described for the Index register above The value of the register varies between an upper and lower bound as follow A lower bound is set by the number of TLB entries reserved for exclusive use by the operating system the contents of the Wired register The entry indexed by the Wired register is the first entry available to be written by a TLB Write Random operation An upper bound is set by the total number of TLB entries minus 1 The Random register is decremented by one almost every clock wrapping after the value in the Wired register is reached To enhance the level of randomness and reduce the possibility of a live lock condition an LFSR register is used that prevents the decrement pseudo randomly The processor initializes the Random register to the upper bound on a Reset exception and when the Wired register is written This register is only valid with the TLB 4KEc core It is reserved if the FM is implemented 4KEm and 4KEp Figure 5 2 Random Register Format 31 4 3 0 0 Random Table 5 4 Random Register Field Descriptions Fields Name Bit s Description Reset State 0 31 4 Must be written as zero returns zero on reads 0 Random 3 0 TLB Random Index R TLB Entries 1 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright
347. ress of the exception vectors to be placed at any 4KBbyte page boundary Figure 5 21 shows the format of the EBase Register Table 5 26 describes the EBase register fields Figure 5 21 EBase Register Format 31 30 29 12 11 10 9 0 1 0 Exception Base 00 CPUNum Table 5 26 EBase Register Field Descriptions Description This bit is ignored on write and returns one on read This bit is ignored on write and returns zero on read In conjunction with bits 31 30 this field specifies the base address of the exception vectors when Statusppy is zero Exception Base Must be written as zero returns zero on read This field specifies the number of the CPU in a multi processor system and can be used by software to distinguish a particular processor from the others CPUNum The value in this field is set by the SI CPUNum 9 0 static input pins to the core In a single processor system this value should be set to zero Externally Set MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions 5 2 21 Config Register CPO Register 16 Select 0 The Config register specifies various configuration and capabilities information Most of the fields in the Config register are initialized by hardware during the Reset exception process or are constant The K0 KU and K23 fiel
348. rial data path In the Instruction register the Capture IR state is used to capture status information into the Instruction register From the Capture states the TAP transitions to either the Shift or Exit states Normally the Shift state follows the Capture state so that test data or status information can be shifted out for inspection and new data shifted in Following the Shift state the TAP either returns to the Run Test Idle state via the Exit and Update states or enters the Pause state via Exit The reason for entering the Pause state is to temporarily suspend the shifting of data through either the Data or Instruction Register while a required operation such as refilling a host memory buffer is performed From the Pause state shifting can resume by re entering the Shift state via the Exit2 state or terminate by entering the Run Test Idle state via the Exit2 and Update states Upon entering the data or Instruction register scan blocks shadow latches in the selected scan path are forced to hold their present state during the Capture and Shift operations The data being shifted into the selected scan path is not output through the shadow latch until the TAP enters the Update DR or Update IR state The Update state causes the shadow latches to update or parallel load with the new data that has been shifted into the selected scan path 188 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Techn
349. ription i Reset State Interrupt Enable in Normal Mode This bit provides the hardware and software interrupt enable for non debug mode in addition to other masking mechanisms INTE 0 Interrupts disabled 1 Interrupts enabled depending on other enabling mechanisms Non Maskable Interrupt Enable for non debug mode NMIE 0 NMI disabled 1 NMI enabled NMI Pending Indication NMIP 0 No NMI pending 0 1 NMI pending Soft Reset Enable This bit allows the system to mask soft resets The core does not internally mask soft resets Rather the state of this bit appears on the EJ_SRstE external output signal allowing the system to mask soft resets if desired SRE Probe Enable Same value as This bit reflects the ProbEn bit in the EJTAG Control Ge PE register see Table 0 No accesses to dmseg allowed 9 4 1 EJTAG probe services accesses to dmseg MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 167 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support 9 2 Hardware Breakpoints Hardware breakpoints provide for the comparison by hardware of executed instructions and data load store transactions Itis possible to set instruction breakpoints on addresses even in ROM area Data breakpoints can be set to cause a debug exception on a specific data transaction Instruction and data hardware breakpoints are alike for many aspects a
350. rocessor operates in User mode when the Status register contains the following bit values e UM 1 e EXL 0 ERL 0 In addition to the above values the DM bit in the Debug register must be 0 Table 3 1 lists the characteristics of the useg User mode segments MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 37 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 3 Memory Management 38 Table 3 1 User Mode Segments Status Register Bit Value Segment Address 8 Bit Value EXL ERL UM Name Address Range Segment Size 32 bit 0x0000_0000 gt 2 GByte 0 0 1 useg Q3 b e A 1 0 Ox7FFF FFFF y All valid user mode virtual addresses have their most significant bit cleared to 0 indicating that user mode can only access the lower half of the virtual memory map Any attempt to reference an address with the most significant bit set while in user mode causes an address error exception The system maps all references to useg through the TLB 4KEc core or FM 4KEm and 4KEp cores For the 4KEc core the virtual address is extended with the contents of the 8 bit ASID field to form a unique virtual address before translation Also for the 4KEc core bit settings within the TLB entry for the page determine the cacheability of a reference For the 4KEm and 4KEp cores the cacheability is set via the KU field of the CPO Config register 3 2 3 Kernel Mode The
351. rpreted as the IP7 IP2 bits described above Controls the request for software interrupts Bit Name Meaning 9 IP1 Request software interrupt 1 8 IPO Request software interrupt 0 IP1 IPO 9 8 R W Undefined These bits are exported to an external interrupt controller for prioritization in EIC interrupt mode with other interrupt sources The state of these bits is available on the external core interface as the SI SWlInt 1 0 bus ExcCode 6 2 Exception code see Table 5 23 R Undefined 25 24 0 21 16 Must be written as zero returns zero on read 0 0 7 1 0 118 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Table 5 23 Cause Register ExcCode Field Exception Code Value Decimal Hexadecimal Mnemonic Description 0 16 00 Int Interrupt 1 16 01 Mod TLB modification exception 4KEc core 2 16 02 TLBL TLB exception load or instruction fetch 4KEc core 3 16 03 TLBS TLB exception store 4KEc core 4 16 04 AdEL Address error exception load or instruction fetch 5 16 05 AdES Address error exception store 6 16 06 IBE Bus error exception instruction fetch 7 16 07 DBE Bus error exception data reference load or store 8 16 08 Sys Syscall exception 9 16 09 Bp Breakpoint exception 10 16 0a RI Reserved instruc
352. rs The registers for data breakpoints are described below These registers have implementation information and are used the setup the data breakpoints All registers are in drseg and the addresses are shown in Table 9 12 Table 9 12 Addresses for Data Breakpoint Registers Register Offset in drseg Mnemonic Register Name and Description 0x2000 DBS Data Breakpoint Status 0x2100 0x100 n DBAn Data Breakpoint Address n 0x2108 0x100 n DBMn Data Breakpoint Address Mask n 0x2110 0x100 n DBASIDn Data Breakpoint ASID n 0x2118 0x100 n DBCn Data Breakpoint Control n 0x2120 0x100 n DBVn Data Breakpoint Value n Note n is breakpoint number as 0 or 1 or just 0 depending on the implemented hardware An example of some of the registers DBMO is at offset 0x2108 and DBV J is at offset 0x2220 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 179 Chapter 9 EJTAG Debug Support 180 9 2 9 1 Data Breakpoint Status DBS Register Compliance Level Implemented if data breakpoints are implemented The Data Breakpoint Status DBS register holds implementation and status information about the data breakpoints The ASIDsup field indicates whether ASID compares are supported DBS Register Format 31 30 29 28 27 24 23 210 Res ASID Res BCN Res BS sup Table 9 13 DBS Register Field Descriptions
353. rved Note LE little endian BE big endian the byte refers to the byte number in a 32 bit register where byte 3 bits 31 24 byte 2 bits 23 16 byte 1 bits 15 8 byte O bits 7 0 independently of the endianess Undefined Res Doze reserved R Doze state The Doze bit indicates any kind of low power mode The value is sampled in the Capture DR state of the TAP controller R 0 CPU not in low power mode 1 CPU is in low power mode Doze includes the Reduced Power RP and WAIT power reduction modes MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 197 Chapter 9 EJTAG Debug Support Table 9 23 EJTAG Control Register Descriptions Continued Fields Read Name Bit s Description Write Reset State Halt state The Halt bit indicates if the internal system bus clock is running or stopped The value is sampled in the 0 Hut Capture DR state of the TAP controller 0 Internal system clock is running 1 Internal system clock is stopped Peripheral Reset When the bit is set to 1 it is only guaranteed that the peripheral reset has occurred in the system when the read value of this bit is also 1 This is to ensure that the setting from the TCK clock domain gets effect in the CPU clock PerRst domain and in peripherals 0 When the bit is written to 0 then the bit must also be read as 0
354. ryLol and PageMask registers The information written to the TLB entry may be different from that in the EntryHi EntryLoO and EntryLol registers in that e The single G bit in the TLB entry is set from the logical AND of the G bits in the EntryLoO and EntryLol registers Restrictions The operation is UNDEFINED if the contents of the Index register are greater than or equal to the number of TLB entries in the processor If access to Coprocessor 0 is not enabled a Coprocessor Unusable Exception is signaled MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 267 268 Write Indexed TLB Entry Operation i Index ll wagk PageMaskyas veN2 EntryHiypywo as p EntryHiasip c EntryLolg and EntryLo0 Pru lt EntryLolppy TLB TLB TLB TLB TLB TLB TLB TLB TLB TLB TLB TLB Exceptions H H H H bb bb B BR bt TLBWI cj Entry pj Entry Olc Olp yj amp Entry Oly pruno EntryLoOpry co Entry o0c po Entry OD yo Entry ER Coprocessor Unusable MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Write Random TLB Entry TLBWR 31 26 25 24 6 COPO CO 0 TLBWR 010000 1 000 0000 0000
355. s Fetch TLB miss 4KEc core Fetch TLB hit to page with V 0 4KEc core Instruction fetch bus error EJTAG Breakpoint execution of SDBBP instruction Execution of SYSCALL instruction Execution of BREAK instruction Execution of a coprocessor instruction for a coprocessor that is not enabled Execution of a Reserved Instruction Execution of coprocessor 2 instruction which caused a general exception in the coprocessor Execution of coprocessor 2 instruction which caused an Implementation Specific exception 1 in the coprocessor Execution of coprocessor 2 instruction which caused an Implementation Specific exception 2 in the coprocessor Execution of an arithmetic instruction that overflowed Execution of a trap when trap condition is true 54 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 4 3 Interrupts Table 4 1 Priority of Exceptions Continued Exception Description DDBL DDBS EJTAG Data Address Break address only or EJTAG Data Value Break on Store address and value A reference to an address in one of the watch registers data Load address alignment error User mode load reference to kernel address Store address alignment error User mode store to kernel address Load TLB miss 4KEc core Load TLB hit to page with V 0 4KEc core Store TLB miss
356. s Read Name Bits Description Write Reset State Controls access to coprocessor 0 0 access not allowed CUO 28 1 access allowed R W Undefined Coprocessor 0 is always usable when the processor is running in kernel mode independent of the state of the CUO bit Enables reduced power mode The state of the RP bit is RP 27 available on the external core interface as the SJ_RP R W signal 0 for Cold Reset only This bit is related to floating point registers Since the 4KE FR 26 core does not contain a floating point unit this bit is R 0 ignored on write and read as zero Used to enable reverse endian memory references while the processor is running in user mode RE 25 R W Undefined 1 User mode uses reversed endianness Neither Debug Mode nor Kernel Mode nor Supervisor Mode references are affected by the state of this bit R 24 23 Reserved This field is ignored on write and read as 0 R 0 Controls the location of exception vectors Encoding Meaning BEV 22 TLB shutdown Indicates that the TLB has detected a match on multiple entries This bit is set if a TLBWI or TLBWR instruction is issued that would cause a TLB shutdown condition if allowed to complete A machine TS 21 check exception is also issued This bit is only used in the R W 0 4KEc processor and is reserved in the 4KEp and 4KEm processors Software can only write a 0 to this bit to clear it and cannot for
357. s Similarly the MSUB MSUBU instruction multiplies two operands and then subtracts the product from the HI and LO registers The MADD MADDU and MSUB MSUBU operations are commonly used in DSP algorithms All multiply operations except the MUL instruction write to the HI LO register pair All integer operations write to the general purpose registers GPR Because MDU operations write to different registers than integer operations following integer instructions can execute before the MDU operation has completed The MFLO and MFHI instructions are used to move data from the HI LO register pair to the GPR file If a MFLO or MFHI instruction is issued before the MDU operation completes it will stall to wait for the data 2 5 MDU Pipeline 4KEc and 4KEm Cores The 4KEc and 4KEm processor cores contain an autonomous multiply divide unit MDU with a separate pipeline for multiply and divide operations This pipeline operates in parallel with the integer unit IU pipeline and does not stall when the IU pipeline stalls This allows multi cycle MDU operations such as a divide to be partially masked by system stalls and or other integer unit instructions The MDU consists of a 32x16 booth encoded multiplier array a carry propagate adder result accumulation registers HI and LO multiply and divide state machines and all necessary multiplexers and control logic The first number shown 32 of 32x16 represents the rs operand The second number 16
358. s the read value will change to indicate if this source was ever the cause of a trigger action even if the action was suppressed If so the read value will be 1 If the write value was 0 the read value is always 0 This special read value is valid until the TCBTRIGx register is written When set this Trigger will fire when a rising edge on TC ChipTriglIn is detected The write value of this bit always controls the behavior of this trigger CHTri 5 R W 0 When this trigger fires the read value will change to indicate if this source was ever the cause of a trigger action even if the action was suppressed If so the read value will be 1 If the write value was 0 the read value is always 0 This special read value is valid until the TCBTRIGx register is written When set this Trigger will fire when a rising edge on TC ProbeTrigIn is detected The write value of this bit always controls the behavior of this trigger PDTri 4 R W 0 When this trigger fires the read value will change to indicate if this source was ever the cause of a trigger action even if the action was suppressed If so the read value will be 1 If the write value was 0 the read value is always 0 This special read value is valid until the TCBTRIGx register is written MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 221 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support Ta
359. s R W Undefined register When set to zero trace is disabled in Debug Mode irrespective of other bits 136 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Table 5 35 TraceControl Register Field Descriptions Continued Read Description Write Reset State When set to one this enables tracing in Exception Mode see Section 9 7 1 Processor Modes on page Undefined Undefined 0 205 For trace to be enabled in Exception mode the On bit must be one and either the G bit must be one or the current process ASID must match the ASID field in this register When set to zero trace is disabled in Exception Mode irrespective of other bits When set to one this enables tracing in Kernel Mode see Section 9 7 1 Processor Modes on page 205 For trace to be enabled in Kernel mode the On bit must be one and either the G bit must be one or the current process ASID must match the ASID field in this register When set to zero trace is disabled in Kernel Mode irrespective of other bits Undefined Undefined This bit is reserved Must be written as zero returns 0 22 0 Zero on read When set to one this enables tracing in User Mode see Section 9 7 1 Processor Modes on page 205 For trace to be enabled in User mode the On bit must be one and either the G bit
360. s a match the page frame ASID VPN2 number PFNO or PFN1 representing the upper bits of the i TLB physical address PA is output from copo vo PFNO Entry Y 3 The Offset which does not pass through the TLB is then concatenated Offset with the PFN Physical Address Figure 3 8 Overview of a Virtual to Physical Address Translation in the 4KEc Core If there is a virtual address match in the TLB the Physical Frame Number PEN is output from the TLB and concatenated with the Offset to form the physical address The Offset represents an address within the page frame space As shown in Figure 3 8 on page 46 the Offset does not pass through the TLB Figure 3 9 on page 47 shows a flow diagram of the 4KEc core address translation process for two page sizes The top portion of the figure shows a virtual address for a 4 KByte page size The width of the Offset is defined by the page size The remaining 20 bits of the address represent the virtual page number VPN The bottom portion of Figure 3 9 on page 47 shows the virtual address for a 16 MByte page size The remaining 8 bits of the address represent the VPN MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 3 4 Virtual to Physical Address Translation 4KEc Core Virtual address with 1M 22 4 KByte 39 32 31 20 bits 1M pages 12 11 0 ASID VPN Offset Va Virtual
361. s can be run on uniprocessor systems that do not support cached coherent memory access types MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Synchronize Shared Memory SYNC 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 0 SYNC stype 000000 00 0000 0000 0000 0 001111 6 15 5 6 Format SYNC stype 0 implied MIPS32 Purpose To order loads and stores Description Simple Description SYNC affects only uncached and cached coherent loads and stores The loads and stores that occur before the SYNC must be completed before the loads and stores after the SYNC are allowed to start Loads are completed when the destination register is written Stores are completed when the stored value is visible to every other processor in the system SYNC is required potentially in conjunction with SSNOP to guarantee that memory reference results are visible across operating mode changes For example a SYNC is required on entry to and exit from Debug Mode to guarantee that memory affects are handled correctly Detailed Description SYNC does not guarantee the order in which instruction fetches are performed The stype values 1 31 are reserved for future extensions to the architecture A value of zero will always be defined such that it performs all defined synchronization operations Non zero values may be defined to remove some synchron
362. s for Each Instruction Breakpoint Register Mnemonic Register Name and Description IBAn Instruction Breakpoint Address n IBMn Instruction Breakpoint Address Mask n IBASIDn Instruction Breakpoint ASID n IBCn Instruction Breakpoint Control n 9 2 4 Data Breakpoint Registers Overview The register with implementation indication and status for data breakpoints in general is shown in Table 9 4 Table 9 4 Overview of Status Register for Data Breakpoints Register Mnemonic Register Name and Description Data Breakpoint Status The two data breakpoints are numbered 0 and for registers and breakpoints and the number is indicated by n The registers for each breakpoint are shown in Table 9 5 Table 9 5 Overview of Registers for each Data Breakpoint Register Mnemonic Register Name and Description DBAn Data Breakpoint Address n DBMn Data Breakpoint Address Mask n DBASIDn Data Breakpoint ASID n DBCn Data Breakpoint Control n DBVn Data Breakpoint Value n 9 2 5 Conditions for Matching Breakpoints A number of conditions must be fulfilled in order for a breakpoint to match on an executed instruction or a data transaction and the conditions for matching instruction and data breakpoints are described below The breakpoints only match for instructions executed in non debug mode thus never on instructions executed in debug mode The match of an enabled breakpoint can either generate a debug exceptio
363. s state the value shifted in during the Shift DR state takes effect on the rising edge of the TCK for the register indicated by the Instruction register If TMS is sampled LOW at the rising edge of TCK the controller transitions to the Run Test Idle state A HIGH on TMS causes the controller to transition to the Select DR Scan state The instruction cannot change while the TAP controller is in this state and all shift register stages in the test data registers selected by the current instruction retain their previous state 9 3 2 11 Capture IR State In this state the shift register contained in the Instruction register loads a fixed pattern 00001 on the rising edge of TCK The data registers selected by the current instruction retain their previous state If TMS is sampled LOW at the rising edge of TCK the controller transitions to the Shift IR state A HIGH on TMS causes the controller to transition to the Exit IR state The instruction cannot change while the TAP controller is in this state MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 3 Test Access Port TAP 9 3 2 12 Shift IR State In this state the instruction register is connected between TDI and TDO and shifts data one stage toward its serial output on the rising edge of TCK If TMS is sampled LOW at the rising edge of TCK the controller remains in the Shift_IR state A HIGH on T
364. shows the format of each line in the tag data and way select arrays 22 1 1 Tag per way PA Valid L 32 32 32 32 Data per way Word3 Word2 Word1 WordO 0 6 1 4 D Way Select LRU Dirty 0 6 Figure 7 1 Cache Array Formats A tag entry consists of the upper 22 bits of the physical address bits 31 10 one valid bit for the line and a lock bit A data entry contains the four 32 bit words in the line for a total of 16 bytes All four words in the line are present or not in the data array together hence the single valid bit stored with the tag Once a valid line is resident in the cache byte halfword triple byte or full word stores can update all or a portion of the words in that line The tag and data entries are repeated for each of the n lines in the set per the associativity A way select entry holds bits choosing the way to be replaced according to a Least Recently Used LRU algorithm The LRU information applies to all the ways and there is one way select entry for all the ways in the set The number of bits in the way select entry depends on the set associativity In a direct mapped cache n 1 there is no need for LRU bits since fills can only go to one place only Table 7 3 shows the number of LRU bits required as a function of associativity The array with way select entries for the data cache also holds dirty bit s for the lines One dirty bit is required per line as shown in Table 7 3 The instruction ca
365. sing given the possible minimum page sizes and cache way sizes supported by a 4KE core Virtual aliasing is generally only a problem for the D cache since stores don t happen to the I cache No special hardware mechanism is provided to prevent the possibility of virtual aliasing so it must be handled by software The software solution must ensure that the MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 157 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 7 Caches mapping of virtual address bits which overlap with physical address bits be handled consistently The simplest approach is to ensure that the overlapping bits are unity mapped VA equals PA Table 7 4 Potential Virtual Aliasing Bits Overlapped address Minimum Page Size Cache Way Size bits with possible KB KB aliasing 2 10 4 11 10 8 12 10 4 16 13 12 8 16 13 A related issue can occur in virtually indexed physically tagged caches if the number of physical bits stored in the tag array do not fully overlap the physically translated bits for the smallest page size For a 4KE core there are always 22 address bits stored in the cache tag representing bits 31 10 of the physical address Since the minimum page size is 1 KB for the 4KEc with bits 31 10 physically translated by the TLB the cache tag size does overlap the translated bits and this issue will not occur 7 3
366. sor Cores Software User s Manual Revision 02 00 49 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 3 Memory Management Op Code Table 3 8 TLB Instructions Description of Instruction TLBWR Translation Lookaside Buffer Write Random 3 5 Fixed Mapping MMU 4KEm amp 4KEp Cores The 4KEm and 4KEp cores implement a simple Fixed Mapping FM memory management unit that is smaller than the a full translation lookaside buffer TLB and more easily synthesized Like a TLB the FM performs virtual to physical address translation and provides attributes for the different memory segments Those memory segments which are unmapped in a TLB implementation ksegO and kseg1 are translated identically by the FM in the 4KEm and 4KEp MMU The FM also determines the cacheability of each segment These attributes are controlled via bits in the Config register Table 3 9 shows the encoding for the K23 bits 30 28 KU bits 27 25 and KO bits 2 0 of the Config register Table 3 9 Cache Coherency Attributes Config Register Fields K23 KU and Ku Cache Coherency Attribute 0 Cacheable noncoherent write through no write allocate Cacheable noncoherent write through write allocate Cacheable noncoherent write back write allocate 2 7 Uncached In the 4KEm and 4KEp cores no translation exceptions can be taken although address errors are still possible Table 3 10 Cache
367. space which would normally result in such an exception Data watch is not triggered by a cache instruc tion whose address matches the Watch register address match conditions Bits 17 16 of the instruction specify the cache on which to perform the operation as follows Table 11 12 Encoding of Bits 17 16 of CACHE Instruction Code Cache 2 00 Primary Instruction 2 01 Primary Data 2 10 T Not supported 2 11 S Not supported Bits 20 18 of the instruction specify the operation to perform On Index Load Tag and Index Store Data operations the specific word that is addressed is loaded into read from the DataLo register All other cache instructions are line based and the word and byte indexes will not affect their operation 248 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Perform Cache Operation CACHE Table 11 13 Encoding of Bits 20 18 of the CACHE Instruction ErrCtl WST SPR Cleared Code Caches Name Effective Address Operand Type Operation Implemented I Index Invalidate Index Writeback Invalidate 2 000 ST Reserved Set the state of the cache block at the specified index to invalid This encoding may be used by software to invalidate the entire instruction cache by stepping through all valid indices If the state of the cache block at the specified index is valid and dirty writ
368. ssing routine Unlike the compatibility mode examples an EIC interrupt handler may take advantage of a dedicated GPR shadow set to avoid saving any registers As such the SimpleInterrupt code shown above need not save the GPRs A nested interrupt is similar to that shown for compatibility mode but may also take advantage of running the nested exception routine in the GPR shadow set dedicated to the interrupt or in another shadow set It also need only copy Cause to Stats to prevent lower priority interrupts from interrupting the handler Such a routine might look as follows NestedException xXx Nested exceptions typically require saving the EPC setting up the appropriate GPR shadow set for the routine the appropriate IM bits in Status to prevent an interrupt loop putting the processor in kernel mode below can not cover all nuances of this processing and is intended only to demonstrate the concepts and re enabling interrupts Status and SRSCtl registers disabling The sample code Use the current GPR shadow set and setup software context mfcO k1 CO Cause Read Cause to get RIPL value mfcO k0 CO EPC Get restart address srl kl k1 S CauseRIPL Right justify RIPL field sw k0 EPCSave Save in memory mfcO k0 CO Status Get Status value sw k0 StatusSave Save in memory ins kO kl S StatusIPL 6 Set IPL to RIPL in copy of Status mfcO k1
369. ssociativity 0x0 Direct mapped Oxl 2 way 0x2 3 way 0x3 4 way 0x4 0x7 Reserved MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 125 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers Table 5 28 Config1 Register Field Descriptions Select 1 Continued Description Reset State This field contains the number of data cache sets per way 0x0 64 0x1 128 0x2 256 Preset 0x3 512 0x4 1024 0x5 0x7 Reserved This field contains the data cache line size If a data cache is present then it must contain a line size of 16 bytes Preset 0x0 No Dcache present 0x3 16 bytes 0x1 0x2 0x4 0x7 Reserved This field contains the type of set associativity for the data cache 0x0 Direct mapped DA 9 7 Ox1 2 way Preset 0x2 3 way 0x3 4 way 0x4 0x7 Reserved Coprocessor 2 present 0 No coprocessor is attached to the COP2 interface C2 6 1 A coprocessor is attached to the COP2 interface If the Cop2 interface logic is not implemented this bit will read 0 MD 5 MDMX implemented This bit always reads as 0 because R 0 MDMX is not supported Performance Counter registers implemented Always a 0 PC 4 since the 4KE core does not contain Performance Counters Watch registers implemented 0 No Watch registers are present WE 3 1 One or more Watch registers are present Preset Code compression MIPS16 implemented CA 7 0
370. ssor is operating in VI interrupt mode binding of a vectored interrupt to a shadow set is done by writing to the SRSMap register If the processor is operating in EIC interrupt mode the binding of the interrupt to a specific shadow set is provided by the external interrupt controller and is configured in an implementation dependent way Binding of an exception or non vectored interrupt to a shadow set is done by writing to the ESS field of the SRSCtl register When an exception or interrupt occurs the value of SRSCtlogg is copied to SRSCtlpss and SRSCtlcgg is set to the value taken from the appropriate source On an ERET the value of SRSCtlpss is copied back into SRSCtlcgg to restore the shadow set of the mode to which control returns More precisely the rules for updating the fields in the SRSCtl register on an interrupt or exception are as follows 1 No field in the SRSCIl register is updated if any of the following conditions is true In this case steps 2 and 3 are skipped The exception is one that sets Statusppy Reset Soft Reset or NMI The exception causes entry into EJTAG Debug Mode Statuspgy 1 e Statuspyy 1 2 SRSCtlegg is copied to SRSCtlpgs 3 SRSCtless is updated from one of the following sources The appropriate field of the SRSMap register based on IPL if the exception is an interrupt Causeyy 1 Config3ygc 0 and Config3y 1 These are the conditions for a vectored interrupt The EICSS field of the SRSC
371. state of the cache block to invalid This encoding may be used by software to invalidate a range of addresses from the instruction cache by stepping through the address range by the line size of the cache Fill the cache from the specified address The cache line is refetched even if it is already Address in the cache If the cache block contains the specified Hit Wiiteback address and it is valid and dirty write the contents back to memory After that operation is completed set the state of the cache block to invalid If the block is valid but not dirty set the state of the block to invalid This encoding may be used by software to invalidate a range of addresses from the data cache by steppin Po Address through the address range by the line Ge ot the cache Invalidate Hit Writeback Address If the cache block contains the specified address and it is valid and dirty write the contents back to memory After the operation is completed leave the state of the line valid but clear the dirty state 250 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Table 11 13 Encoding of Bits 20 18 of the CACHE Instruction ErrCtl WST SPR Cleared Effective Address Operand Code Caches Name Type Operation Implemented If the cache does not contain the specified address fill it from memory performing a wr
372. ster 28 Select 0 The TagLo register acts as the interface to the cache tag array The Index Store Tag and Index Load Tag operations of the CACHE instruction use the TagLo register as the source of tag information Note that the 4KE core does not implement the TagHi register Figure 5 37 TagLo Register Format 31 16 15 109 8 7 6 5 4 PA PA LRU R V D L Table 5 41 TagLo Register Field Descriptions Fields Name Bit s Description This field contains the physical address of the cache line Bit 31 corresponds to bit 31 of the PA and bit 10 corresponds to bit 10 of the PA This field contains the value read from or to be stored to the WS array if the WST bit in the ErrCtl register is set Reset State Undefined Undefined Must be written as zero returns zero on read This field indicates whether the cache line is valid This field indicates whether the cache line is dirty It will only be set if bit 7 valid is also set 0 Undefined Undefined Specifies the lock bit for the cache tag When this bit is set and the valid bit is set the corresponding cache line will not be replaced by the cache replacement algorithm MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Undefined 145 Chapter 5 CPO Registers 5 2 36 DataLo Register CP0 Register 28 Select 1 The DataLo register is a register that
373. struction that caused the exception can not be identified This chapter contains the following sections Section 4 1 Exception Conditions Section 4 2 Exception Priority Section 4 3 Interrupts Section 4 4 GPR Shadow Registers Section 4 5 Exception Vector Locations Section 4 6 General Exception Processing Section 4 7 Debug Exception Processing Section 4 8 Exceptions Section 4 9 Exception Handling and Servicing Flowcharts 4 1 Exception Conditions When an exception condition occurs the relevant instruction and all those that follow it in the pipeline are cancelled Accordingly any stall conditions and any later exception conditions that may have referenced this instruction are inhibited there is no benefit in servicing stalls for a cancelled instruction When an exception condition is detected on an instruction fetch the core aborts that instruction and all instructions that follow When this instruction reaches the W stage the exception flag causes it to write various CPO registers with the exception state change the current program counter PC to the appropriate exception vector address and clear the exception bits of earlier pipeline stages This implementation allows all preceding instructions to complete execution and prevents all subsequent instructions from completing Thus the value in the EPC ErrorEPC for errors or DEPC for debug exceptions is sufficient to restart MIPS32
374. sult was available for the following instructions To avoid this data bypassing is implemented MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 2 8 Data Bypassing Between the register file and the ALU a data bypass multiplexer is placed on both operands see Figure 2 17 on page 23 This enables the 4KE core to forward data from a preceding instruction whose target is a source register of a following instruction An M to E bypass and an A to E bypass feed the bypass multiplexers A W to E bypass is not needed as the register file is capable of making an internal bypass of Rd write data directly to the Rs and Rt read ports Istage E stage M stage A stage W stage A to E bypass i i M to E bypass Instruction Bypass l Load data HI LO Data multiplexers or CPO data Figure 2 17 IU Pipeline Data bypass Figure 2 18 on page 23 shows the data bypass for an Add instruction followed by a Sub and another Add instruction The Sub instruction uses the output from the Add instruction as one of the operands and thus the M to E bypass is used The following Add uses the result from both the first Add instruction and the Sub instruction Since the Add data is now in A stage the A to E bypass is used and the M to E bypass is used to bypass the Sub data to the Add instruction One Cycle One Cycle One Cycle One Cycle On
375. t inier ipit eite rea ERR E ERES GE E et rtp e pepe 168 9 2 3 Instruction Breakpoint Registers Overview eren en neen nennen nennen terere 168 9 2 4 Data Breakpoint Registers Overview sese een en entren nennen ee treten EET apts 169 9 2 5 Conditions for Matching Breakpoints ener enn neen nennen tret enntre trennen 169 9 2 6 Debug Exceptions from Breakpoints ener en entren nen nremene tren netre enne ene 171 9 2 7 Breakpoint used as TriggerPoint sess enne ener en Croke Ekots ESOS entren ertet tenen 172 9 2 8 Instruction Breakpoint Registers A 172 9 2 9 Data Breakpoint Registers scene e REF SES 179 9 3 Test Access Port GLAD uote trip E E eis 187 9 3 1 EJTAG Internal and External Interfaces eese eene enn neen nennen nennen treten ene 187 9 3 2 Test Access Port Operation ente deni bibere te RO e b t E e HERR HERE 188 9 3 3 Test Access Port TAP MUC OS a a nennen enne enne enne enne E nennen nene a nenne enne 191 DA EITAG TAP Registers 2 eed en tege dote o ee Pee t rote dri es 194 9 4 1 Instruction Register 2 2 ie e eee eee ee AE ee 194 9 4 2 Data Registers Overview osos eee eer eO ee ree ER ee ERE 194 9 4 3 Processor Access Address Register minson es iseki ren tie EEE eee ene EEEO ESE eene tenter nnne ene 200 9 4 4 Fastdata Register TAP Instruction FASTDATA esee enne nene n nne en nere nene 201 9 5 TAP Processor ACCESSES Lie iis eerte DER eie Ai eti ee Ree Redit ccs ee
376. t instruction and data buses Support for branch on Coprocessor condition Processor to from Coprocessor register data transfers Direct memory to from Coprocessor register data transfers Multiply Divide Unit 4KEc and 4KEm cores Maximum issue rate of one 32x16 multiply per clock Maximum issue rate of one 32x32 multiply every other clock Early in divide control Minimum 11 maximum 34 clock latency on divide Multiply Divide Unit 4KEp core Iterative multiply and divide 32 or more cycles for each instruction MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 3 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 1 Introduction to the MIPS32 4KE Processor Core Family Power Control No minimum frequency Power down mode triggered by WAIT instruction Support for software controlled clock divider Support for extensive use of fine grain clock gating EJTAG Debug Support CPU control with start stop and single stepping Software breakpoints via the SDBBP instruction Optional hardware breakpoints on virtual addresses 4 instruction and 2 data breakpoints 2 instruction and 1 data breakpoint or no breakpoints Optional Test Access Port TAP facilitates high speed download of application code Optional EJTAG Trace hardware to enable real time tracing of executed code 1 2 4KE Block Diagram The 4KE core conta
377. tandby Mode WAIT 31 26 25 24 6 5 0 COPO CO WAIT Implementation Dependent Code 010000 1 100000 6 1 19 6 Format WAIT MIPS32 Purpose Wait for Event Description The WAIT instruction forces the core into low power mode The pipeline is stalled and when all external requests are completed the processor s main clock is stopped The processor will restart when reset SI_Reset or SI_ColdReset is signaled or a non masked interrupt is taken SI_NMI SI_Int or EJ_DINT Note that the 4KE core does not use the code field in this instruction If the pipeline restarts as the result of an enabled interrupt that interrupt is taken between the WAIT instruction and the following instruction EPC for the interrupt points at the instruction following the WAIT instruction Restrictions The operation of the processor is UNDEFINED if a WAIT instruction is placed in the delay slot of a branch or a jump If access to Coprocessor 0 is not enabled a Coprocessor Unusable Exception is signaled MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 271 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Enter Standby Mode cont WAIT Operation I Enter lower power mod I 1 Potential interrupt taken here Exceptions Coprocessor Unusable Exception 272 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc A
378. tects that PrAcc bit 0 which means that it is ready to handle a new access The above examples imply that no reset occurs during the operations and that Rocc is cleared 9 7 EJTAG Trace 204 EJTAG Trace enables the ability to trace program flow load store addresses and load store data Several run time options exist for the level of information which is traced including tracing only when in specific processor modes i e UserMode or KernelMode EJTAG Trace is an optional block in the 4KE core If EJTAG Trace is not implemented the rest of this chapter is irrelevant If EJTAG Trace is implemented the CPO Config3 rr bit is set The pipeline specific part of EJTAG Trace is architecturally specified in the PDtrace Interface Specification The PDtrace module extracts the trace information from the processor pipeline and presents it to a pipeline independent module called the Trace Control Block TCB The TCB is specified in the EJTAG Trace Control Block Specification The collective implementation of the two is called EJTAG Trace When EJTAG Trace is implemented the 4KE core includes both the PDtrace and the Trace Control Block TCB modules The two modules talk to each other on the generic pin interface called the PDtrace Interface This interface is embedded inside the 4KE core and will not be discussed in detail here read the PDtrace Interface Specification MIPS32 4KE Processor Cores Software User s Manual Revisio
379. ted GPR shadow set to avoid saving any registers As such the SimpleInterrupt code shown above need not save the GPRs MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 59 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 4 Exceptions and Interrupts A nested interrupt is similar to that shown for compatibility mode but may also take advantage of running the nested exception routine in the GPR shadow set dedicated to the interrupt or in another shadow set Such a routine might look as follows Nes F F 0X 0X tedException Nested exceptions typically require saving the EPC Status and SRSCtl registers setting up the appropriate GPR shadow set for the routine disabling the appropriate IM bits in Status to prevent an interrupt loop putting the processor in kernel mode below can not cover all nuances of this processing and is intended only to demonstrate the concepts and re enabling interrupts The sample code Use the current GPR shadow set and setup software context mfcO sw mfcO0 sw mfcO0 sw li and ko kO kO kO kO kO k1 kO CO EPC EPCSave CO Status StatusSave CO SRSCt1 SRSCtlSave IMbitsToClear KO k1 If switching shadow sets zero S StatusEXL ins mtcO ko KO CO Status If switching shadow sets address to EPC and do ex
380. ter Device Identification Register Implementation Register EJTAG Control Register ECR Processor Access Address Register Processor Access Data Register FastData Register MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 4 EJTAG TAP Registers 9 4 2 1 Bypass Register The Bypass register consists of a single scan register bit When selected the Bypass register provides a single bit scan path between TDI and TDO The Bypass register allows abbreviating the scan path through devices that are not involved in the test The Bypass register is selected when the Instruction register is loaded with a pattern of all ones to satisfy the IEEE 1149 1 Bypass instruction requirement 9 4 2 2 Device Identification ID Register The Device Identification register is defined by IEEE 1149 1 to identify the device s manufacturer part number revision and other device specific information Table 9 21 shows the bit assignments defined for the read only Device Identification Register and inputs to the core determine the value of these bits These bits can be scanned out of the JD register after being selected The register is selected when the Instruction register is loaded with the IDCODE instruction Device Identification Register Format 31 28 27 12 11 1 0 SEET Table 9 21 Device Identification Register Fields Read Nam
381. ter after each read Note The read RM 16 pointer does not auto increment if the WR field is one R WI1 0 When the write pointer is reached this bit is automatically reset to 0 and the TCBTW register will read all zeros Once set to 1 writing 1 again will have no effect The bit is reset by setting the TR bit or by reading the last Trace word in TCBTW This bit is reserved if on chip memory is not implemented Trace memory reset When written to one the address pointers for the on chip trace memory are reset to zero Also the RM bit is reset to 0 TR 15 R WI 0 This bit is automatically de asserted back to 0 when the reset is completed This bit is reserved if on chip memory is not implemented Buffer Full indicator that the TCB uses to communicate to external software in the situation that the on chip trace memory is being deployed in the trace from and trace to BF 14 mode See Section 9 13 TCB On Chip Trace Memory R 0 This bit is cleared when writing 1 to the TR bit This bit is reserved if on chip memory is not implemented MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 213 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support Table 9 30 TCBCONTROLB Register Field Descriptions Continued Fields Read Name Bits Description Write Reset State Trace Mode This field determines how the trace memory is fill
382. the IntCtl register Table 5 18 describes the ntCtl register fields Figure 5 15 IntCtl Register Format 31 29 28 26 25 10 9 5 4 0 IPTI IPPCI 0 VS 0 Table 5 18 IntCtl Register Field Descriptions Fields Reset Description For Interrupt Compatibility and Vectored Interrupt modes this field specifies the IP number to which the Timer Interrupt request is merged and allows software to determine whether to consider Causey for a potential interrupt Encoding Hardware Interrupt Source Externally IPTI 31 29 Set The value of this bit is set by the static input SI IPTI 2 0 This allows external logic to communicate the specific SI Int hardware interrupt pin to which the S7 Timerlnt signal is attached The value of this field is not meaningful if External Interrupt Controller Mode is enabled The external interrupt controller is expected to provide this information for that interrupt mode For Interrupt Compatibility and Vectored Interrupt modes this field specifies the IP number to which the Performance Counter Interrupt request is merged and allows software to determine whether to consider IPPCI 28 26 Causepcy for a potential interrupt 0 Since performance counters are not implemented on the 4KE core Config1 pc 0 this field is ignored on write and returns zero on read Must be written as zero returns zero on read 0 110 MIPS32 4KE Processor Cores Sof
383. the processor performs a full reset initialization including aborting state machines establishing critical state and generally placing the processor in a state in which it can execute instructions from uncached unmapped address space On a Reset exception the state of the processor is not defined with the following exceptions The Random register is initialized to the number of TLB entries 1 The Wired register is initialized to zero MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 69 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 4 Exceptions and Interrupts 70 The Config register is initialized with its boot state The RP BEV TS SR NMI and ERL fields of the Status register are initialized to a specified state The I R and W fields of the WatchLo register are initialized to 0 The ErrorEPC register is loaded with PC 4 if the state of the processor indicates that it was executing an instruction in the delay slot of a branch Otherwise the ErrorEPC register is loaded with PC Note that this value may or may not be predictable PC is loaded with OXBFCO 0000 Cause Register ExcCode Value None Additional State Saved None Entry Vector Used Reset OXBFCO 0000 Operation Random TLBEntries 1 Wired 0 Config ConfigurationState Statusgp amp 0 Statuspggy amp 1 Statusrs amp 0 StatusSsp amp 0 Statusyyr amp 0 StatuS
384. this entry is global to all processes and or a threads and thus disables inclusion of the ASID in the comparison Address Space Identifier Identifies which process or thread this TLB entry is ASID 7 0 associated with Table 3 7 TLB Data Entry Fields Field Name Description PFNO 31 12 or 29 10 PFN1 31 12 or 29 10 Physical Frame Number Defines the upper bits of the physical address The 29 10 range illustrates that if 1Kbytes page granularity is enabled the PFN is shifted to the right before being appended to the untranslated part of the virtual address In this mode the upper two physical address bits are not covered by PFN but forced to zero For page sizes larger than 4 KBytes only a subset of these bits is actually used Cacheability Contains an encoded value of the cacheability attributes and determines whether the page should be placed in the cache or not The field is encoded as follows Coherency Attribute Cacheable noncoherent write through no write allocate Cacheable noncoherent write through write allocate Uncached C0 2 0 Cacheable noncoherent write back C1 2 0 write allocate Maps to entry 011b Maps to entry 011b Maps to entry 011b Maps to entry 010b Note These mappings are not used on the 4KE processor cores but do have meaning in other MIPS Technologies implementations Refer to the MIPS32 specification for more information DO Dir
385. thods for testing these arrays in software only one is presented here 7 6 1 I Cache D cache Tag Arrays These arrays can be tested via the Index Load Tag and Index Store Tag varieties of the CACHE instruction Index Store Tag will write the contents of the TagLo register into the selected tag entry Index Load Tag will read the selected tag entry into the TagLo 7 6 2 I Cache Data Array This array can be tested using the Index Invalidate Fill and Index Load Tag varieties of the CACHE instruction Fill will force a refill of the I cache with data from a given address In order to predict where the Fill data will go it is advisable to invalidate the I cache array prior to filling it The last way invalidated will be the first way selected for replacement Index Load Tag will read the selected data word into the DataLo register The entire I cache may be flushed using Index Invalidate Then a test pattern can be stored into memory and the CACHE Fill operation will force the test pattern into the I cache data array Index Load Tags can be used to walk through each word of the I cache array checking the contents of the DataLo register against the expected value 7 6 3 I Cache WS Array The testing of this array is very similar to the testing of the tag array By setting the WST bit in the ErrCtl register Index Load Tag and Index Store Tag CACHE instructions will read and write the WS array instead of the tag array 7 6 4 D Cache Data Array This ar
386. tiating a watch exception when an instruction or data reference matches the address information stored in the WatchHi and WatchLo registers A Watch exception is taken immediately if the EXL and ERL bits of the Status register are both zero and the DM bit of the Debug is also zero If any of those bits is a one at the time that a watch exception would normally be taken then the WP bit in the Cause register is set and the exception is deferred until all three bits are zero Software may use the WP bit in the Cause register to determine if the EPC register points at the instruction that caused the watch exception or if the exception actually occurred while in kernel mode The Watch exception can occur on either an instruction fetch or a data access Watch exceptions that occur on an instruction fetch have a higher priority than watch exceptions that occur on a data access Register ExcCode Value WATCH Additional State Saved Table 4 11 Register States on a Watch Exception Register State Value Indicates that the watch exception was deferred until after Statusgxy Statusgg and Debugpy were zero This bit directly causes a watch exception so software must clear this bit as part of the exception handler to prevent a watch exception loop at the end of the current handler execution Causewp Entry Vector Used General exception vector offset 0x180 4 8 10 Address Error Exception Instruction Fetch Data Access
387. tion exception 11 16 0b CpU Coprocessor Unusable exception 12 16 0c Ov Arithmetic Overflow exception 13 16 0d Tr Trap exception 14 15 16 0e 16 0f Reserved 16 16 10 IS1 Implementation Specific Exception 1 COP2 17 16811 IS2 Implementation Specific Exception 2 COP2 18 16 12 C2E Coprocessor 2 exceptions 19 22 16 13 16 16 Reserved 23 16 17 WATCH Reference to WatchHi WatchLo address 24 16 18 MCheck Machine check 25 31 16 19 16 1f Reserved MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 119 Chapter 5 CPO Registers 120 5 2 18 Exception Program Counter CPO Register 14 Select 0 The Exception Program Counter EPC is a read write register that contains the address at which processing resumes after an exception has been serviced All bits of the EPC register are significant and must be writable For synchronous precise exceptions the EPC contains one of the following The virtual address of the instruction that was the direct cause of the exception The virtual address of the immediately preceding branch or jump instruction when the exception causing instruction is in a branch delay slot and the Branch Delay bit in the Cause register is set On new exceptions the processor does not write to the EPC register when the EXL bit in the Status register is set however the register can still be written via the MTCO instruction
388. tion is never fulfilled on load transaction Res 11 8 Must be written as zero returns zero on reads R 0 Byte lane mask for value compare on data breakpoint BLM 0 masks byte at bits 7 0 of the data bus BLM 1 masks byte at bits 15 8 etc BLM 71 4 R W Undefined 0 Compare corresponding byte lane 1 Mask corresponding byte lane Res 3 Must be written as zero returns zero on reads R 0 184 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 9 2 Hardware Breakpoints Table 9 17 DBCn Register Field Descriptions Continued Fields Name Bits Description Read Write Reset State Use data breakpoint n as triggerpoint TE 2 0 Don t use it as triggerpoint R W 0 1 Use it as triggerpoint Res 1 Must be written as zero returns zero on reads R 0 Use data breakpoint n as breakpoint BE 0 0 Don t use it as breakpoint R W 0 1 Use it as breakpoint MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 185 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support 9 2 9 6 Data Breakpoint Value n DBVn Register Compliance Level Implemented only for implemented data breakpoints The Data Breakpoint Value n DBVn register has the value used in the condition for data breakpoint n DBVn Register Format 31 0 DBV Table 9 18 DBVn Register
389. tions Cause Register ExcCode Value None Additional State Saved None Entry Vector Used Reset OXBFCO 0000 Operation Statuspggy amp 1 Statusrs 0 StatuSs g amp 1 Statusyyr amp 0 StatuSpp amp 1 if InstructionInBranchDelaySlot then ErrorEPC PC 4 else ErrorEPC PC endif PC OxBFCO 0000 4 8 3 Debug Single Step Exception A debug single step exception occurs after the CPU has executed one two instructions in non debug mode when returning to non debug mode after debug mode One instruction is allowed to execute when returning to a non jump branch instruction otherwise two instructions are allowed to execute since the jump branch and the instruction in the delay slot are executed as one step Debug single step exceptions are enabled by the SSt bit in the Debug register and are always disabled for the first one two instructions after a DERET The DEPC register points to the instruction on which the debug single step exception occurred which is also the next instruction to single step or execute when returning from debug mode So the DEPC will not point to the instruction which has just been single stepped but rather the following instruction The DBD bit in the Debug register is never set for a debug single step exception since the jump branch and the instruction in the delay slot is executed in one step Exceptions occurring on the instruction s executed with debug s
390. to physical Offset passed unchanged translation in TLB to physical memory Bit 31 of the virtual address selects user and kernel 32 bit Physical Address address spaces 31 0 PFNO Offset Virtual to physical Offset passed unchanged translation in TLB to physical memory o E dos SN A 39 32 31 24 23 0 ASID VPN Offset 8 bits 2 256 pages Virtual Address with 256 28 1 6 MByte pages Figure 3 9 32 bit Virtual Address Translation 3 4 1 Hits Misses and Multiple Matches Each JTLB entry contains a tag and two data fields If a match is found the upper bits of the virtual address are replaced with the page frame number PFN stored in the corresponding entry in the data array of the JTLB The granularity of JTLB mappings is defined in terms of TLB pages The 4KEc core JTLB supports pages of different sizes ranging from 1 KB to 256 MB in powers of 4 If a match is found but the entry is invalid i e the V bit in the data field is 0 a TLB Invalid exception is taken If no match occurs TLB miss an exception is taken and software refills the TLB from the page table resident in memory Figure 3 10 on page 49 shows the translation and exception flow of the TLB Software can write over a selected TLB entry or use a hardware mechanism to write into a random entry The Random register selects which TLB entry to use on a TLBWR This register decrements almost every cycle wrapping to the maximum once its value is equal to the
391. tr CtiOns esses reme nee ete n nep cn PO Ee Ee Ee pepe ipee ee ep d e rope 233 10 3 1 Cycle Timing for Multiply and Divide Instructions esee eene 234 10 4 J nip and Branch Instruct Ons eee e peer ee rtr e Pm Eee e eed re He Eee Eee 234 10 4 1 Overview of Jump Instructions enne rennen nennen en rene tnt teen nn enne ene 234 10 4 2 Overview of Branch Instructions yoo oneer eetos enoi nene nen trennen nenne entren tenent nennen ennt ene 234 10 5 Control nstr ctions eoe SER Cae eene unto teer 234 10 6 Coprocessor E le E 234 10 7 Enhancements to the MIPS Architecture nee ne tenente eniti nen rennen 235 10 7 E CEO Count Leading RE 235 10 7 2 CEZ Count Leading Zeros Ledger e o edidere dur eere e a edge cadens 235 10 7 3 MADD Multiply and Add Word sese ennt eren entren RE 235 10 7 4 MADDU Multiply and Add Unsigned Word eese nennen reme 235 10 7 5 MSUB Multiply and Subtract Word A 235 10 7 6 MSUBU Multiply and Subtract Unsigned Word sese enne enne 236 10 7 7 MUI Multiply Word sesser tt ERR PER exer e Ente dea ete iege n 236 10 7 8 SSNOP Superscalar Inhibit NOP seseseeseeeeeeeeneee nennen eret tree nen eren en nest en nennen 236 Chapter 11 MIPS32 4KE Processor Core Instructions eese enne en eneemren nennen nennen 237 11 1 Understanding the Instruction Descriptions esee nennen nennen retener trennen rennen eene 23
392. treten rennen 116 Table 5 23 Cause Register ExcCode Peld eene nennen nennen nenne enne teret trennen 119 Table 5 24 EPC Register Field Description ote ettet o e Ode e eem ee erii een een 120 Table 5 25 PRId Register Field Descrppons eene nennen nennen retener terere tereti trenes enne 121 Table 5 26 EBase Register Field Descriptions r eene nennen nennen tenen retener innen rerit ennt 122 Table 5 27 Cache Coherency Arbutes sessi enne entente nennen ne teeen tenerent trennen eene nre 124 Table 5 28 Config Register Field Descriptions Select 1 eene 125 Table 5 29 Config Register Field Descriptions Select 1 enne nene 127 Table 5 30 Config3 Register Field Descriptions eerte nennen nennen nente treten entente i rennen 128 Table 5 31 LLAddr Register Field Descriptions seeesseeeeeeeeeeeeeneeeen nennen nennen nente ener enne t rerit 130 Table 5 32 WatchLo Register Field Descriptions svisino arrei E tenerent eret ne trennen rennen 131 Table 5 33 WatchHi Register Field Descriptions sess enne trennen rennen 132 Table 5 34 Debug Register Field Descriptions ssesesseseeeeeeeeeeeeneee nennen nennen nenne treten enit renes 133 Table 5 35 TraceControl Register Field Descriptions sees nee nen rere ene 136 Table 5 36 TraceControl2 Register Field Descriptions eene terere nennen ene 139 Table 5 37 UserTraceData Register Field Descptons eene nnne ener etre 141 Table 5 38 Tr
393. tructions The ALU determines whether the branch condition is true and calculates the virtual branch target address for branch instructions Instruction logic selects an instruction address All multiply and divide operations begin in this stage 2 1 3 M Stage Memory Fetch During the Memory Fetch stage The arithmetic or logic ALU operation completes The data cache access and the data virtual to physical address translation are performed for load and store instructions Data TLB 4KEc core only and data cache lookup are performed and a hit miss determination is made A 16x16 or 32x16 MUL operation completes in the array and stalls for one clock in the M stage to complete the carry propagate add in the M stage 4KEc and 4KEm cores A 32x32 MUL operation stalls for two clocks in the M stage to complete the second cycle of the array and the carry propagate add in the M stage 4KEc and 4KEm cores A multiply operation stalls the MDU pipeline for 31 cycles in the M stage 4KEp core Multiply and divide calculations proceed in the MDU If the calculation completes before the IU moves the instruction past the M stage then the MDU holds the result in a temporary register until the IU moves the instructions to the A stage and it is consequently known that it won t be killed 2 1 4 A Stage Align During the Align stage A separate aligner aligns loaded data with its word boundary A MUL operation makes the result availa
394. tuations Seil os Enable counting of Count register Disable counting of Count register Performance Counter Interrupt In an implementation of Release 2 of the Architecture this bit denotes whether a performance counter interrupt is pending analogous to the IP bits for other interrupt types Encoding Meaning 0 No timer interrupt is pending 1 Timer interrupt is pending Since performance counters are not implemented Configlpe 0 this bit must be written as zero and returns zero on read Indicates whether an interrupt exception uses the general exception vector or a special interrupt vector Encoding Meaning 0 Use the general exception vector 16 180 1 Use the special interrupt vector 16 200 In implementations of Release 2 of the architecture if the Causery is 1 and Statusggy is 0 the special interrupt vector represents the base of the vectored interrupt table Undefined WP 22 Indicates that a watch exception was deferred because Statuspyy or Statusppy were a one at the time the watch exception was detected This bit both indicates that the watch exception was deferred and causes the exception to be initiated once Statuspyy and Statusppy are both zero As such software must clear this bit as part of the watch exception handler to prevent a watch exception loop Software should not write a 1 to this bit when its value is a 0 thereby causing a
395. tware User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions Table 5 18 IntCtl Register Field Descriptions Reset Description State Vector Spacing If vectored interrupts are implemented as denoted by Config3yg or Config3ygc this field specifies the spacing between vectored interrupts Encoding Spacing Between Spacing Between Vectors hex Vectors decimal 16 00 16 000 0 16 01 16 020 32 16 02 16 040 16 04 16 080 16 08 16 100 16 10 16 200 All other values are reserved The operation of the processor is UNDEFINED if a reserved value is written to this field Must be written as zero returns zero on read 0 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 111 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers 5 2 15 SRSCII Register CPO Register 12 Select 2 The SRSCtl register controls the operation of GPR shadow sets in the processor This register does not exist in implementations of the architecture prior to Release 2 Figure 5 16 shows the format of the SRSCII register Table 5 19 describes the SRSCtl register fields Figure 5 16 SRSCtl Register Format 3 30 29 26 25 22 21 18 17 16 15 12 11 10 9 6 5 4 3 0 0 0 0 00 EICSS 00 ESS 00 HSS PSS CSS 00 00 Table 5 19 SRSCt Register Fi
396. ty or Write enable Bit Indicates that the page has been written DI and or is writable If this bit is set stores to the page are permitted If the bit is cleared stores to the page cause a TLB Modified exception vo Valid Bit Indicates that the TLB entry and thus the virtual page mapping VI are valid If this bit is set accesses to the page are permitted If the bit is cleared accesses to the page cause a TLB Invalid exception In order to fill an entry in the JTLB software executes a TLBWI or TLBWR instruction See Section 3 4 3 TLB Instructions on page 49 Prior to invoking one of these instructions several CPO registers must be updated with the information to be written to a TLB entry MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 3 4 Virtual to Physical Address Translation 4KEc Core PageMask is set in the CPO PageMask register VPN2 VPN2X and ASID are set in the CPO EntryHi register e PFNO CO DO VO and G bits are set in the CPO EntryLo0 register e PEN1 C1 D1 V1 and G bits are set in the CPO EntryLol register Note that the global bit G is part of both EntryLo0 and EntryLol The resulting G bit in the JTLB entry is the logical AND between the two fields in EntryLoO and EntryLo1 Please refer to Chapter 5 CPO Registers for further details The address space identifier ASID helps to re
397. u Wu Figure 2 8 MDU Pipeline Flow During a 32x32 Multiply Operation 18 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 2 5 MDU Pipeline 4KEc and 4KEm Cores 2 5 3 Divide 4KEc amp 4KEm Cores Divide operations are implemented using a simple non restoring division algorithm This algorithm works only for positive operands hence the first cycle of the Mypy stage is used to negate the rs operand RS Adjust if needed Note that this cycle is spent even if the adjustment is not necessary During the next maximum 32 cycles 3 34 an iterative add subtract loop is executed In cycle 3 an early in detection is performed in parallel with the add subtract The adjusted rs operand is detected to be zero extended on the upper most 8 16 or 24 bits If this is the case the following 7 15 or 23 cycles of the add subtract iterations are skipped The remainder adjust Rem Adjust cycle is required if the remainder was negative Note that this cycle is spent even if the remainder was positive A sign adjust is performed on the quotient and or remainder if necessary The sign adjust stage is skipped if both operands are positive In this case the Rem Adjust is moved to the Aypy stage Figure 2 9 on page 19 Figure 2 10 on page 19 Figure 2 11 on page 19 and Figure 2 12 on page 20 show the latency for 8 16 24 and 32 bit divide operations
398. ualify the address specified in WatchLo Figure 5 29 WatchHi Register Format 31 30 29 24 23 16 15 12 11 3 2 0 0 G 0 ASID 0 Mask 0 Table 5 33 WatchHi Register Field Descriptions Fields Name Description Reset State 0 Must be written as zeros returns zero on read 0 If this bit is one any address that matches that specified in the WatchLo register causes a watch exception If this bit G is zero the ASID field of the WatchHi register must match Undefined the ASID field of the EntryHi register to cause a watch exception 0 Must be written as zeros returns zeros on read 0 ASID value which is required to match that in the EntryHi ASID register if the G bit is zero in the WatchHi register Undefined 0 Must be written as zero returns zero on read 0 Bit mask that qualifies the address in the WatchLo register Any bit in this field that is a set inhibits the Mask corresponding address bit from participating in the Undefined address match 0 i Must be written as zeros returns zeros on read 0 132 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved 5 2 CPO Register Descriptions 5 2 28 Debug Register CPO Register 23 Select 0 The Debug register is used to control the debug exception and provide information about the cause of the debug exception and when re entering at the debug exception vector due to a normal e
399. ug with ProbEn 1 in the EJTAG_Control_register 16 FF20 0200 For Release 1 of the architecture 16 8000 0000 Other For Release 2 of the architecture 16 BFC0 0200 EBase31 2212 Il 164000 Note that EBase3 39 have the fixed value 2 10 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 65 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 4 Exceptions and Interrupts Table 4 6 Exception Vector Offsets Interrupt Causey 1 implementations this is IV 7 Table 4 7 Exception Vectors Exception Vector Offset TLB Refill EXL 0 164000 General Exception 164180 164200 In Release 2 the vectored interrupt table when Statusggy 0 Reset Soft Reset NMI None Uses Reset Base Address the base of 4 6 General Exception Processing With the exception of Reset Soft Reset NMI cache error and EJTAG Debug exceptions which have their own special processing as described below exceptions have the same basic processing flow e f the EXL bit in the Status register is zero the EPC register is loaded with the PC at which execution will be restarted and the BD bit is set appropriately in the Cause register see Table 5 the EPC register is dependent on whether the processor implements the MIPS16 ASE and whether the instruction is 66 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00
400. ug software sampling the ProbEn bit as 1 and the probe clearing it to 0 3 3 Translation Lookaside Buffer 4KEc Core Only 42 The following subsections discuss the TLB memory management scheme used in the 4KEc processor core The TLB consists of one joint and two micro address translation buffers 16 dual entry fully associative Joint TLB JTLB 4 entry fully associative Instruction micro TLB ITLB 4 entry fully associative Data micro TLB DTLB 3 3 1 Joint TLB The 4KEc core implements a 16 dual entry fully associative Joint TLB that maps 32 virtual pages to their corresponding physical addresses The purpose of the TLB is to translate virtual addresses and their corresponding ASID into a physical memory address The translation is performed by comparing the upper bits of the virtual address along with the ASID bits against each of the entries in the tag portion of the JTLB structure Because this structure is used to translate both instruction and data virtual addresses it is referred to as a joint TLB The JTLB is organized as 16 pairs of even and odd entries containing descriptions of pages that range in size from 4 KBytes or 1 KByte to 256 MBytes into the 4 GByte physical address space By default the minimum page size is normally 4 KBytes on the 4KEc core as a build time option it is possible to specify a minimum page size of 1 KByte MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyri
401. ulation 12 212 for civilian agencies and Defense Federal Acquisition Regulation Supplement 227 7202 for military agencies The use of this information by the Government is further restricted in accordance with the terms of the license agreement s and or applicable contract terms and conditions covering this information from MIPS Technologies or an authorized third party MIPS R3000 R4000 R5000 and R10000 are among the registered trademarks of MIPS Technologies Inc in the United States and other countries and MIPS16 MIPS16e MIPS32 MIPS64 MIPS 3D MIPS based MIPS I MIPS II MIPS III MIPS IV MIPS V MIPSsim SmartMIPS MIPS Technologies logo 4K 4Kc 4Km 4Kp 4KE 4KEc 4KEm 4KEp 4KS 4KSc 4KSd M4K 5K 5Kc 5Kf 20Kc 25Kf ASMACRO ATLAS At the Core of the User Experience BusBridge CoreFPGA CoreLV EC JALGO MALTA MDMX MGB PDtrace Pipeline Pro Pro Series SEAD SEAD 2 SOC it and YAMON are among the trademarks of MIPS Technologies Inc All other trademarks referred to herein are the property of their respective owners Template B1 07 Build with Conditional Tags 2B EMERALD MIPS32 PROC MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Table of Contents Chapter 1 Introduction to the MIPS32 4KE Processor Core Family esee nennen 1 Tal Features oos dC ERU Mb eee boa Mid 2 LAKE Block Di astatrni
402. ump instruction when the error causing instruction is in a branch delay slot Unlike the EPC register there is no corresponding branch delay slot indication for the ErrorEPC register In processors that implement the MIPS16 ASE a read of the ErrorEPC register via MFCO returns the following value in the destination GPR GPR rt lt ErrorExceptionPC4 4 ISAModeg That is the upper 31 bits of the error exception PC are combined with the lower bit of the ISAMode field and written to the GPR Similarly a write to the ErrorEPC register via MTCO takes the value from the GPR and distributes that value to the error exception PC and the ISAMode field as follows ErrprExceptionPC lt GPR rt 3 0 ISAMode lt 2 0 GPR rt That is the upper 31 bits of the GPR are written to the upper 31 bits of the error exception PC and the lower bit of the error exception PC is cleared The upper bit of the ISAMode field is cleared and the lower bit is loaded from the lower bit of the GPR Figure 5 39 ErrorEPC Register Format 31 0 ErrorEPC Table 5 43 ErrorEPC Register Field Description Fields Description 31 0 Error Exception Program Counter Reset State Undefined ErrorEPC MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 147 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers 5 2 38 DeSave Re
403. ure 3 2 Address Translation During a Cache Access in the 4KEm and 4KEp Core 34 Figure 3 3 4KE processor core Virtual Memory Map 36 Figure 3 4 User Mode Virtual Address Space eene enne nhe neethen nennen retener netter trees 37 Figure 3 5 Kernel Mode Virtual Address Space 39 Figure 3 6 Debug Mode Virtual Address Space essere ener nennen nennen ne tretn nenne enne trees 41 Figure SG JT LB Entry Fag and Data c RO et m UR EGER EHE tees bien pier pee eae 43 Figure 3 8 Overview of a Virtual to Physical Address Translation in the 4KEc Core eee 46 Figure 3 9 32 bit Virtual Address Translation eese ener nennen nennen ettet ipek E EE Egas 47 Figure 3 10 TLB Address Translation Flow in the 4KE Processor Core sese 49 Figure 3 11 FM Memory Map ERL 0 in the 4KEm and 4KEp Processor Cores eee 51 Figure 3 12 FM Memory Map ERL 1 in the 4KEm and 4KEp Processor Cores esee 52 Figure 4 1 Interrupt Generation for Vectored Interrupt Mode 59 Figure 4 2 Interrupt Generation for External Interrupt Controller Interrupt Mode 62 Figure 4 3 General Exception Handler HW ciet tbt ret EP Sess e eM en recie e pii rte aes 82 Figure 4 4 General Exception Servicing Guidelines GW 83 Figure 4 5 TLB Miss Exception Handler HW 4KEc Core 84 Figure 4 6 TLB Exception Servicing Guidelines SW 4KEc Core esee 85 Figure 4 7 Reset Soft Reset and NMI Ex
404. ware control on page 209 As such these fields in the TraceControl2 register will not have valid values until the TCB asserts these values This register is only implemented if the EJTAG Trace capability is present Figure 5 32 Trace Control2 Register Format 31 7 6 5 4 3 2 0 Valid TBI TBU SyP Modes Table 5 36 TraceControl2 Register Field Descriptions Read Description Write Reset State Reserved for future use Must be written as zero returns zero on read This field specifies the type of tracing that is supported by the processor as follows Meaning PC tracing only ValidModes PC and load and store address tracing only PC load and store address and load and store data Reserved This bit indicates how many trace buffers are implemented by the TCB as follows Encoding Meaning Only one trace buffer is implemented and Per the TBU bit of this register indicates which trace buffer is implemented implementati on Both on chip and off chip trace buffers are implemented by the TCB and the TBU bit of this register indicates to which trace buffer the trace is currently written MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 139 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 5 CPO Registers 140 Table 5 36 TraceControl2 Register Field Descriptions Continued Read Description Write Reset State
405. ways Completely at interrupt level e g a simply UART interrupt The SimpleInterrupt routine below is an example of this type By saving sufficient state and re enabling other interrupts In this case the software model determines which interrupts are disabled during the processing of this interrupt Typically this is either the singl StatusIM bit that corresponds to the interrupt being processed or some collection of other Status bits so that lower priority interrupts are also disabled The NestedInterrupt routine below is an example of this type SimpleInterrupt ET Nes F 0X F F MIPS32 4KE Process the device interrupt here and clear the interupt request at the device In order to do this some registers may need to be saved and restored The coprocessor 0 state is such that an ERET will simple return to the interrupted cod eret Return to interrupted code tedException Nested exceptions typically require saving the EPC and Status registers any GPRs that may be modified by the nested exception routine disabling the appropriate IM bits in Status to prevent an interrupt loop putting the processor in kernel mode and re enabling interrupts The sample code below can not cover all nuances of this processing and is intended only to demonstrate the concepts Save GPRs here and setup software context
406. xception in debug mode The read only information bits are updated every time the debug exception is taken or when a normal exception is taken when already in debug mode Only the DM bit and the EJTAGver field are valid when read from non debug mode the values of all other bits and fields are UNPREDICTABLE Operation of the processor is UNDEFINED if the Debug register is written from non debug mode Some of the bits and fields are only updated on debug exceptions and or exceptions in debug mode as shown below DSS DBp DDBL DDBS DIB DINT are updated on both debug exceptions and on exceptions in debug modes DExcCode is updated on exceptions in debug mode and is undefined after a debug exception Halt and Doze are updated on a debug exception and are undefined after an exception in debug mode DBD is updated on both debug and on exceptions in debug modes All bits and fields are undefined when read from normal mode except those explicitly described to be defined e g EJTAGver and DM Figure 5 30 Debug Register Format 31 30 29 28 27 26 25 24 23 22 21 20 19 DBD DM NoDCR LSNM Dozd Halt CountDM IBusEP MCheckP CacheEP DBusEP IEXI DDBSImpr 18 17 15 14 10 9 8 7 6 5 4 3 2 1 0 DDBLImp Ver DExcCode NoSSt SSt R DINT DIB DDBS DDBL DBp DSS Table 5 34 Debug Register Field Descriptions Fields Description Reset State Indicates whether the last debug exception or exception in debug mode occurred in a branch del
407. yHiAsqp 3 2 3 WatchHi MTCO Instruction fetch seeing the new value WatchLo Cache entries Instruction stream write via CACHE Instruction stream Cache System depend med Instruction fetch seeing the new instruction stream 1 write via store entries ent 1 This value depends on how long it takes for the store value to propagate through the system Instruction fetch seeing the new instruction stream 2 13 2 Instruction Listing Table 2 8 lists the instructions designed to eliminate hazards See the document titled MIPS32TM Architecture for Programmers Release 2 Architecture Changes MD00232 for a more detailed description of these instructions Table 2 8 Hazard Instruction Listing Mnemonic Function EHB Clear execution hazard JALR HB Clear both execution and instruction hazards JR HB Clear both execution and instruction hazards SYNCI Synchronize caches after instruction stream write 2 13 2 1 Instruction Encoding The EHB instruction is encoded using a variant of the NOP SSNOP encoding This encoding was chosen for compatibility with the Release 1 SSNOP instruction such that existing software may be modified to be compatible with both Release 1 and Release 2 implementations See the EHB instruction description for additional information The JALR HB and JR HB instructions are encoding using bit 10 of the hint field of the JALR and JR instructions These encodings were chosen for
408. ze of the transaction and thus the number of bytes available required for the PAD register is determined by the Psz field in the ECR 9 4 4 Fastdata Register TAP Instruction FASTDATA The width of the Fastdata register is 1 bit During a Fastdata access the Fastdata register is written and read i e a bit is shifted in and a bit is shifted out During a Fastdata access the Fastdata register value shifted in specifies whether the Fastdata access should be completed or not The value shifted out is a flag that indicates whether the Fastdata access was successful or not if completion was requested Fastdata Register Format 0 MIPS32 4KE Processor Cores Software User s Manual Revision 02 00 201 Copyright 2000 2002 MIPS Technologies Inc All rights reserved Chapter 9 EJTAG Debug Support 202 Table 9 24 Fastdata Register Field Description Fields Read Power up Description SPrAcc The FASTDATA access is used for efficient block transfers between dmseg on the probe and target memory on the Shifting in a zero value requests completion of the Fastdata access The PrAcc bit in the EJTAG Control register is overwritten with zero when the access succeeds The access succeeds if PrAcc is one and the operation address is in the legal dmseg Fastdata area When successful a one is shifted out Shifting out a zero indicates a Fastdata access failure Shifting in a one does not complete the Fastdata access

MIPS32™ 4KE™ Processor Cores Software User`s Manual

Contents

Download Pdf Manuals

Related Search

Related Contents

MIPS32&trade; 4KE&trade; Processor Cores Software User`s Manual

Contents

Download Pdf Manuals

Related Search

Related Contents

MIPS32™ 4KE™ Processor Cores Software User`s Manual