Designing a Quasi‐Resonant Adaptor Driven by the NCP1339
Contents
1. A second current Ising 0 4 V R is subtracted to the first current so that source sink FB 0 4 V R charges the ramp When the ramp reaches an internal threshold the dead time is finished and a clock is generated so that a new DRV pulse can be generated http onsemi com 4 AND9176 D Vdrain ldrain FF Ramp Figure 4 Veg Igrains Vdrain FF Ramp at Different Output Loads in VCO Mode ZERO CROSSING DETECTION The NCP1339 integrates the inductor reset or Zero Current detection ZCD ZCD is achieved by observing the auxiliary winding voltage Vaux ZCD _ Blanking Time TZcp blank Internal Soft Start Complete The Vaux positive part when the MOSFET is off is used for zero crossing detection The schematic of the zero crossing detection block is shown in Figure 5 Minimum Frequency Steady State Timeout tout2 a Steady State Timeout tout1 ag Figure 5 Zero crossing Detection Bloc Schematic In case of extremely damped free oscillations the ZCD comparator can be unable to detect valleys To avoid such a situation NCP1339 integrates a Time Out function that acts as a substitute clock for the decimal counter inside the logic block The controller thus continues its normal operation To avoid having a too big step in frequency the time out duration is set to 6 us The NCP1339 also features an extended time out during the sof2. aux in dc OPP Ropu 7 Ropi eq 16 OPP 0 18 375 0 253 1500 399 KQ 0 253 Finally we choose a 300 kQ resistor for Ropu A Non dissipative OPP The input voltage information is given by the auxiliary winding which offers lower voltage values compared to the bulk rail 1 ton l Ropu Ropi Tsw bridge mean Np aux 1 1 1 300k 1k 30 3u As the average current it sees is very low the power dissipated by the OPP bridge can be neglected RAVA in u 0 18 265 2 In addition in frequency foldback mode the switching frequency reduces Thus the average current in the OPP bridge decreases Let us calculate the average current circulating in the OPP bridge at light load s 1 oy Vaux t lori dt eq 17 bridge ridge mean Tap Ropa Ropi We obtain 1 ton a lori N Vn v2 bridge avg ani Ropi Tew p aux in t eq 18 1 demag l Veg Vy Ropu Rop Tsw On our 45 W adapter for an output power of 8 W we measured ton 1 1 us tor 29 2 us tdemag 5 6 us Toy 30 3 us e Vcc Ve 13 45 V We can calculate the OPP bridge current at highest input voltage 265 V rms tdemag sie u Tsw Ropu Ropi eq 19 1 5 6u 300k 1k 30 3u 13 45 16 4 uA FAULT PIN The Fault pin combines two different safety features to help design a compact power supply The first one is an Over Voltage Protecti
3. eq 11 1 0 25 3 23 345 10 6 Z m V345 1076 250 10712 18 0 us 375 19 0 8 P Paisti l 345 1078 3 23 l 0 85 85 W eq 12 Re Re z z s 3 z 0 eq out high 2 P pk high Tentin 18 0 10 6 If no over power compensation is applied the adapter will be able to deliver 85 W at high line In order to limit the output power to 57 W at 265 Vrms the peak current must be reduced to Lon 1 Nps Lo t2 em Lp C E a al max dc Vout Y P out limit vere lak limit lea eq 13 Poutcimit 1 0 25 2 0 25 2 345 x 10 8 0 85 6r 4 AAR 6 n 2 R gt 5 6 12 345 x 10 ar Jes x 10 8 4 senna x 345 10 6 250 10 345 10 0 85 57 2 21A The amount of OPP voltage that must be applied to the design is Lees pk limit 2 21 Vopp 0 8 1 0 8 1 2 253 mv eq 14 3 23 pk max http onsemi com AND9176 D Calculating the OPP Resistors Looking at Figure 6 if we apply the resistor divider law on the pin 2 during the on time we obtain the following relationship Ropu Npaux Vinge Vopr R eq 15 opl Vopp By choosing a value for Rop for example 1 5 kQ we can easily deduce Ropu value Following our example from before we need 253 mV of OPP voltage to limit the output power to 57 W at 265 Vrms We choose Ropi 1 5 kQ Np aux Vinge Vopp p
4. AND9176 D Designing a Quasi Resonant Adaptor Driven by the NCP1339 Quasi square wave resonant converters also known as Quasi Resonant QR converter are widely used in the adaptor market They allow designing flyback Switched Mode Power Supply SMPS with reduced Electro Magnetic Interference EMI signature and improved efficiency However a major drawback of the structure is that the frequency can become dramatically high at light load In traditional QR converters the frequency is limited by a frequency clamp But when the switching frequency of the system reaches the frequency clamp limit valley jumping occurs the controller hesitates between two valleys resulting in an instable operation and noise in the transformer at medium and light output loads In order to overcome this problem the NCP1339 features a proprietary valley lockout circuit the switching EMI FILTER ON Semiconductor http onsemi com APPLICATION NOTE frequency is decreased step by step by changing valley from valley n to valley n 1 as the load decreases Once the controller selects a valley it stays locked in this valley until the output power changes significantly This technique extends the QR operation of the system towards lighter loads without degrading the efficiency In addition in order to limit the stand by consumption the NCP1339 integrates an HV current source that charges the Vcc capacitor during start up phase
5. LC SCILLC or its subsidiaries in the United States and or other countries SCILLC owns the rights to a number of patents trademarks copyrights trade secrets and other intellectual property A listing of SCILLC s product patent coverage may be accessed at www onsemi com site pdf Patent Marking pdf SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer p
6. V 45 W Table 1 SPECIFICATIONS OF THE 19 V 45 W adapter will be the design example The specifications are ADAPTER detailed in Table 1 Parameter Symbol Val The experimental results of the 45 W adapter are detailed 2e in the evaluation board user s manual EVBUM2248 1 For details concerning the QR transformer calculation you can refer to the tutorial TND348 2 nom Switching Frequency at Vin min Fow 45 kHz Pout nom Maximum Startup Time PREDICTING THE SWITCHING FREQUENCY As the controller changes valley as the load decreases The datasheet gives the FB thresholds at which the the switching frequency of the power supply is naturally controller transitions from valley n to valley n 1 Pout limited by the valley lockout But equations are needed to falling and at which the controller transitions from valley predict the switching frequency evolution with respect with n 1 to valley n Pout rising the output power Operating Mode lt Vpg Decreases FF Vrs increases Valley 6 Valley 5 Valley 4 Valley 3 Valley 2 Valley 1 08 09 10 11 12 14 15 16 17 18 20 3 2 Vre V Figure 2 Operating Valley According to FB Voltage With these thresholds we can calculate the maximum switching frequency inside each valley depending if the output power decreases or increases Fsw VEB 5 za 1 Nps eq 1 V y2 Lp i 2n 1 x Lp C ae in rms Lp p Viris F 2 Vout
7. Vi p lump Where Vrp is the FB threshold at which the controller changes Vou is the output voltage valley Vpis the forward voltage drop of the output diode Rsense is the sense resistor value Chump Tegroups all capacitances surrounding the drain Vin rms 1s the rms value of the input voltage node MOSFET capacitor transformer parasitics trop is the propagation delay As a first approximation the MOSFET drain source L is the primary inductance capacitance Coss can be used instead of Clump http onsemi com 3 AND9176 D nis an integer representing the operating valley n 1 for 1 valley n 2 for 24 valley n 3 for 3 valley and n 4 for the 4 valley n 5 for 5 valley and n 6 for the 6 valley Nps is the Ns Np turns ratio where Ns and Np respectively are the secondary and primary number of turns Throp 1s the propagation delay between the moment when the MOSFET current exceeds the setpoint target and the actual MOSFET turn off The corresponding output power can be calculated using the traditional formula 2 torop V E Fewn eq 2 Lp i Pout Lp i 2 gt Using the previous equations we can calculate the maxima of the switching frequency and the corresponding output power for our 45 W adapter In order to help the power supply designer the previous equations have been entered inside a Mathcad spreadsheet that automatically predicts the evolution of the sw
8. and an automatic X2 capacitor discharge circuitry that saves the need for power consuming discharge resistors across the front end filtering capacitors This application note focuses on the design of an adapter driven by the NCP1339 The equations developed are further used to design a 45 W adapter PSM_OFF GND Figure 1 Application Schematic Semiconductor Components Industries LLC 2014 July 2014 Rev 0 Publication Order Number AND9176 D AND9176 D INTRODUCTION The NCP1339 implements a standard quasi resonant current mode architecture This component represents the ideal candidate where low part count and cost effectiveness are the key parameters particularly in low cost ac dc adapters open frame power supplies etc The NCP1339 brings all the necessary components normally needed in modern power supply designs bringing several enhancements such as non dissipative OPP brown out protection or sophisticated frequency reduction management for an optimized efficiency over the power range Accounting for the new needs of extremely low standby power requirements the part includes an automatic X2 capacitor discharge circuitry which can save the power consuming resistors otherwise needed across the front end filtering capacitors The controller is also able to enter Power Savings Mode PSM that is a deep sleep mode via its dedicated remote REM pin e High Voltage Start Up low standby power results canno
9. itching frequency as a function of the output power Figure 3 Vinums 2 For more calculation details please refer to the Mathcad file on website ngisi qth 3rd 2nd 1st 1 2x105 1 vco i l mode i 1x105 i 8x104 F is gt 6x104 w 6th a qth 3rd 2nd 1st 4x104 i Da i 2x104 VCO i mode 0 0 10 20 30 40 Pout W Figure 3 Switching Frequency vs Output Power at Vin 115 Vims FREQUENCY FOLDBACK MODE Operating Details At nominal power the power supply operates in a variable frequency system where discrete frequency steps occur as the controller looks for the different valley positions At low output power the controller enters a Frequency Foldback FF mode This mode is entered when Vrg drops below 0 8 V The controller remains in this mode until Vrg increases above V During the FF operation Vrg lt 0 8 V the peak current is frozen to 25 of its maximum value and the frequency diminishes as the output power decreases To reduce the switching frequency the system adds some dead time controlled by a ramp The ramp is grounded from MOSFET turn on until the 6 valley is detected Hence there is no discontinuity and the frequency smoothly reduces as FB goes below 0 8 V The ramp slope is proportional to the FB voltage Practically the circuit embeds a current source that depends on the FB pin voltage jource FB R where R is an internal resistor
10. on OVP and the second one is an Over Temperature Protection OTP Over Temperature Protection The adapter operating in a confined area e g the plastic case protecting the converter it is important to monitor the internal ambient temperature If this temperature increases beyond a certain point catastrophic failures can occur through semiconductors thermal runaway or transformer saturation To prevent this the NCP1339 embeds an Over Temperature Protection OTP circuitry which can be combined with an Over Voltage Protection as sketched by Figure 7 The IFaul orp current 45 5 WA typ biases the Negative Temperature Coefficient sensor NTC naturally imposing a dc voltage on the OTP pin When the temperature increases the NTC s resistance reduces bringing the pin 5 voltage down until it reaches a typical value of 0 4 V the comparator trips and latches off the controller During the latch off phase the Vcc drops to the 5 5 V Vecybias voltage level The power supply needs to be un plugged to reset the part During start up and soft start the output of the OTP comparator is blanked to give the OTP pin voltage time to reach its steady state value if a filtering capacitor is installed across the NTC The filtering capacitor value should be 1 nF In the NCP1339 the OTP trip point corresponds to a resistance of 0 4 45 5u Vote 8 79 kQ eq 20 Ryte l OTP REF http onsemi com 8 AND9176 D Fig
11. ower variations It generally gives the capability of maintaining the power deviation within 20 in a universal mains application Auxiliary Winding Figure 6 The maximum OPP voltage that can be applied to OPP pin is 250 mV which corresponds to peak current decrease of 31 25 The auxiliary winding voltage can be the seat of ringing Therefore it may be needed to add a capacitor Copp of Figure 6 to filter the voltage Higher accuracy can be obtained in narrow mains applications The technique implemented in the NCP1339 takes benefit of the auxiliary winding voltage whose negative amplitude is proportional to the input rail voltage When the power MOSFET is on the auxiliary winding voltage becomes the input voltage Vin affected by the auxiliary to primary turn ratio Np aux Naux Np Vaux Np aux Vin eq 3 By applying this voltage through a resistor divider on the OPP pin we have an image of the input voltage transferred to the controller via this pin This voltage is added internally to the 0 8 V reference and affects the maximum peak current Figure 6 As the OPP voltage is negative an increase of input voltage implies a decrease of the maximum peak current setpoint Vogmax 0 8 Vopp eq 4 PWM Latch Reset and Overload Counter Block OPP Circuit It is wise noting that this capacitor delays the OPP voltage settling to its final value It is then necessary to check that this delay is shorter
12. point as the bulk voltage increases If the pin is grounded no OPP compensation occurs Internal Soft Start a 4 ms soft start precludes the main power switch from being stressed upon start up It is activated whenever a startup sequence occurs including autorecovery hiccup Fault Input the NCP1339 includes a dedicated fault input pin 5 It can be used to sense an overvoltage condition and latch off the controller by pulling up the pin above the upper fault threshold VFauit ovp typically 3 0 V The controller is also disabled if the Fault pin voltage Vpauit is pulled below the lower fault threshold VFault OTP_in typically 0 4 V The lower threshold is normally used for detecting an overtemperature fault by the means of an NTC Short Circuit Overload Protection short circuit and especially overload protections are difficult to implement when a strong leakage inductance between auxiliary and power windings affects the transformer the aux winding level does not properly collapse in presence of an output short Here every time the internal 0 8 V maximum peak current limit is activated or less when OPP is used an error flag is asserted and a 160 ms timer begins counting When the timer has elapsed the fault is validated Please note that the NCP1339C offers an low duty cycle lt 10 auto recovery mode http onsemi com 2 AND9176 D SPECIFICATIONS OF THE ADAPTER In order to illustrate this application note a 19
13. t Mode Operation QR operation is an efficient mode where the MOSFET turns on when its drain source is at the minimum valley However at light load the switching frequency tends to get high The NCP1339 valley lock out and frequency foldback technique eliminate this drawback so that the efficiency remains at the highest over the power range Valley Lockout a continuous flow of pulses is not compatible with no load light load standby power requirements To excel in this domain the controller observes the feedback pin voltage FB and when it reaches a level of 1 4 V the circuit enters a valley lockout mode where the circuit skips a valley If FB further decreases more valleys are skipped until 6t valley is reached Frequency Fold Back if FB continues declining and reaches 0 8 V the current setpoint is frozen to Vfreeze and the circuit regulates by modulating the switching frequency until it reaches 25 kHz typically Skip Cycle to avoid acoustic noise the circuit prevents the switching frequency from decaying below 25 kHz Instead the circuit contains the power delivery by entering skip cycle mode when the system would otherwise need to further lower the switching frequency below 25 kHz Internal OPP Over Power Protection by routing a portion of the negative voltage present during the on time on the auxiliary winding to the OPP pin pin 3 the user has a simple and non dissipative means to alter the maximum current set
14. t be obtained with the classical resistive start up network In this part a high voltage current source provides the necessary current at start up and turns off afterwards Internal Brown Out Protection the bulk voltage is internally sensed via the high voltage pin monitoring pin 14 When Vpin14 is too low the part stops pulsing No re start attempt is made until Vpini4 recovers its normal range At that moment the brown out comparator sends a general reset to the controller de latch occurs and authorizes to re start X2 Capacitors Discharge Capability per IEC 950 standard the time constant of the front end filter capacitors and their associated discharge resistors must be less than 1 s This is to avoid electrical stress when users unplug the converter and inadvertently touch the power cord terminals The circuitry for discharging the X2 capacitors can save the need for discharge resistors helping to further save power e PSM Control a dedicated pin allows the IC to enter a deep sleep mode when the REM input pin is brought above a certain level This option offers an efficient means to operate the adapter in a power savings mode and draw the least input power from the mains in this mode When the REM is actively pulled down via a dedicated optocoupler the adapter immediately re starts The component that controls PSM is then active in normal operation active ON and OFF in PSM wasting no energy Quasi Resonant Curren
15. t start Indeed at startup the output voltage reflected on the auxiliary winding is low the ZCD comparator might be unable to detect the valleys If the 6 us steady state timeout was used in this condition a DRV pulse would be generated every 6 us This delay is generally too short that leads to a continuous conduction mode operation CCM when the power supply enters operation To cope with this situation that only lasts for a few cycles until the voltage on ZCD pin becomes high enough to be detected by the ZCD comparator the time out duration is extended to 100 us during the soft start period in order to ensure that the transformer is fully demagnetized before the MOSFET is turned on http onsemi com AND9176 D OVER POWER PROTECTION Operating Details The power capability of a flyback operated in Quasi Resonance is not constant over the line range Instead as suggested by Eq 2 it dramatically increases when the input voltage rises Two main reasons cause this The peak current is higher at high line due to the Tprop propagation delay between the moment when the MOSFET current reaches the target and the moment when the MOSFET actually opens The frequency is also higher at high line leading to a higher power capability To cope with safety requirements the designer needs to limit the power output capability over the input voltage range The NCP1339 features a function named Over Power Protection OPP to contain the p
16. than the on time at full load http onsemi com 6 AND9176 D Calculating the Needed OPP Amount for the Design Because of the propagation delay the maximum peak current at high line is 0 8 tprop l V A k high id pk high Reense in max dc cs eq 5 The corresponding switching period and output power can be deduced from Eq 1 and Eq 2 T L 14 high pk high p sane eye Vintmax dc Vout Vi max d a Lp Clump eq 6 1 2 1 Pout high zi Lp gt Iok high n eq 7 sw high We would like to limit the output power to Pout limit gt Pout nom at Maximum input voltage In order to perform over power compensation we need to calculate the peak current Ipk limit Corresponding to Pout limit N a L peie Vin max de Vout Vi N Lp 1 ps p Lp H2 Vin max dc Vout t Vt P out limit e v Lp i Clump pk limit The amount of OPP voltage needed is thus eq 8 Lon P outciimit As an example in order to provide a 25 power margin Leavin to our 45 W adapter we want to limit the output power to pk limi ers Vopp 0 8 eq 9 57 W at high line pk max Using equations Eq 5 to Eq 7 we obtain 0 8 torop 0 8 600 10 9 eS ey 3 23 A eq 10 pk high Reense in max dc Bs 0 31 345 10 6 q 1 Nps Tgw high lpk high i Lp j H y z ET y Lp Clamp in max dc out f
17. urchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT Literature Distribution Center for ON Semiconductor P O Box 5163 Denver Colorado 80217 USA Phone 303 675 2175 or 800 344 3860 Toll Free USA Canada Fax 303 675 2176 or 800 344 3867 Toll Free USA Canada Email orderlit onsemi com N American Technical Support 800 282 9855 Toll Free ON Semiconductor Website www onsemi com USA Canada Europe Middle East and Africa Technical Support Phone 421 33 790 2910 Japan Customer Focus Center Phone 81 3 5817 1050 Order Literature http www onsemi com orderlit For additional information please contact your local Sales Representative AND9176 D
18. ure 7 OTP OPP Combination in NCP1339 Over Voltage Protection The NCP1339 features a protection against an over voltage condition e g in case of the optocoupler destruction This over voltage protection is combined with an OTP as shown previously on Figure 7 Only a Zener diode needs to be added between the Vcc rail and the Fault pin in order to detect an over voltage condition In case of over voltage the Zener diode starts to conduct and injects current inside the internal clamp resistor RFault clamp thus causing the pin 5 voltage to increase When this voltage reaches the OVP threshold 3 V typ the controller is latched off The amount of current that must be injected inside the controller by the zener diode can be calculated as follows Vovp V Fault Clamp 3 1 7 l Fault 838 7 uA eq 21 jj Reautt Clamp 1 55 108 CONCLUSION This application note has described the equations needed to design a QR adapter driven by the NCP1339 All the equations presented have been implemented inside a Mathcad spreadsheet that can be downloaded from our website http www onsemi com REFERENCES 1 Yann Vaquette A 45 W adaptor with NCP1339 Quasi Resonant controller Evaluation Board User s 2 St phanie Conseil QR Analysis and Design of Quasi Resonant Converters Tutorial TND348 Manual EVBUM2248 D ON Semiconductor and the Q are registered trademarks of Semiconductor Components Industries L
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