AN221K04 Evaluation Board User Manual
Contents
1. AN221K04 Anadigmvortex ana Development Board User Manual Figure 14 shows another system of 3 boards chained together but this time configured from an EPROM DODOPODODO re 00000 AnadigmDesigner2 grounded 00 load order 1 load order 2 load order 3 cm cm A o o o o J24 0000 Us A O Gm oe O J22 connect A to ACLK 000 O Era Q o 5 J17 DO 00 o J24 o 0000 oo E 4 4 t 4 4 4 4 L 4 t 00 a Gm PA LK to DCLK DO connected J22 UTCLK to ACLK between boards Board oo 3 exe 16MHz connected a c to DCLK pin EPROM J19 00 J17 gt OO O J24 EPROM E 00888 pull ups downs connected Figure 14 Jumper Settings and Load Order for 3 Chained Boards in EPROM Mode UM030900 U010e Page 11 of 17 AN221K04 Anadigmvortex ana Development Board User Manual 6 0 Other Features VrerPins and Spare Opamp The 3 reference pins on the FPAA device VMRC 2 0V VREFPC 3 5V and VREFMC 0 5V have been brought out to pads The VMRC pin has been buffered using an opamp to provide buffered VMR for the whole board There is also a spare opamp and its pins have been brought out to pads This opamp can be used to buffer either VREFPC or VREFMC for use in such applications as sensor interfacing or it can be used for any other custom function The spare opamp is powered to 0 and 5V only Header Pins All of the analog I Os of the FPAA are brought ou2. CS1b shorted to VMR grounded CHEER 0000000000800000 J23 PIC program BE la 0000000000000 flo 00000 LEI ana TAN default normal b O poe 0000000000000l0 operating mode J13 16 C O PELOS 20000 OOO OC COO OCOD o Analog e 0000 00000 000000lo Interface o00000M000000000000000 o 00000 0000000000000l0 am o Oe AS adiu oo0o0000 W c0000000000000 default i p Go z Elogio A WN Si R O O O Oooo OOQ0OO000000000000 J9 12 E O00 0 A o Analog Q Q 0000000 9999990000000 Interface x 0000000 Gants Block 3 DIO PARECIAN SERES E OTP default i p ROR 10 loco olololo OO BO a OlpaTAS J18 digital i f 000000 e O A desir 3883800000000 00 x default digital i f NE RE lo cece ace f o connected not J5 8 0000 05 70100000 0 8 99 oo one Qul pe o SAR ADC i f Analog OAC eS 00015 o DES Interface L 09000000 MAL 9 NE 00 0 9 Block 2 DIO OO 0000000 Au 0 0 0 0 ari 000000 oo default o p AMO eJ pee eee aoe mes GU ce o 00 GRO B o m HE R e elo core ol oo O O00 0 0 0 O end d Analog O SU 0000000 2 N oo p Interface y O O OOOO Oro RS QD OOO COO 000 5 Block 1 OCOS 5 o0000000oflo o00060600500 n e A MM MAA default o p MO JARED 00000000 000000000000 5 aca El oo0oooooofb0o0ooooooooooo O bs oo00ooooocll000oooooooooo exe Soo ooo 000 0000000 0 000 000000000000 O gt 0000 000000000000 Ae O OOO O 000000000000 ie o o O ooo OOOD AA P2 ale KLA Moo o EEEE o J19 EPROM Gnd 2 O 000 0000
3. default condition CS1b N 1 grounded pull ups downs N connected board N 1 O O O O O 5 normal chaining all boards 90000 or EPROM chaining all boards except last amp last 1 board N I I I I I l I l l I CS1b N 1 to LCCb N DCLK N 1 to DCLK N board N 1 z zm ACLK N 1 to ACLK N O Gua aa O pull ups downs N disconnected ry 0000 EPROM chaining last 8 last 1 boards board N I l l I I I I CS1b N 1 to LCCb N ACLK N 1 to DCLK N cc gt 9 DOUTCLK N 1 to ACLK N O O mme Gua pull ups downs N disconnected Figure 12 Jumper Settings for Daisy Chaining UM030900 U010e Page 9 of 17 Tare AN221K04 Anadigmvortex Development Board User Manual Figure 13 shows a system of 3 boards chained together with the correct jumper settings and load order as relating to the AnadigmDesigner 2 circuit c N ooo ET s CS1b OOOO J22 grounded Board 00 1 OO J17 O O J24 0000 J17 I as t t t 4 1 L H Sa oe connected J22 V between boards Board e 3 ome 16MHz connected to ACLK pin E AnadigmDesigner2 load order 1 digital interface connected J24 BEEP 000000 pull ups downs connected Serial Port load order 2 load order 3 Figure 13 Jumper Settings and Load Order for 3 Chained Boards in Normal Mode UM030900 U010e Page 10 of 17
4. EEEE E MM ou gt ose EH 653 p t pe oy s c mu Bog Go 00 ug p C y m aL i zar AN221K04 Anadigmvortex ana Development Board User Manual von R32 T von R31 Pz 470R ure El G G E SARSYNC a gt SARDATA One SARCLK 2 EXE dia GND 3 POR dig i VDD z ACT dig g ERR dia 4 a gt Lec dig E eI R33 cK dia RR i23 C82 dig 5 B us P C16F876 Pa i MCLR B Re7 28 vpn B 2 RAO RB L 27 B 3 mal RBSL 26 621 CO805 B 4 RA2 RBAL 25 i n 5 RAS RB3L 24 PEST ug E MAX232 a 6 RA4 RB2L 23 cez paga 5 cogos z RAS RBIL 22 vpn Ibin ici vec 16 E 8 vss RBO 21 Dg 2 v GND 15 4 4 ES E a osci vaa 28 a ci tiour 14 A SND 18 4 32MHz ie osc2 vss 19 caa 4 c2 RIIN 13 Ds 53 coas ii Rco RC7L 18 teen S Dia NM i00n s c2 RiouT 12 Z 3 xs N 56v iz nCi RC amp L 17 e v TIIND 11 2 13 RC2 RCSL 16 z T20UT T2IN 18 6 14 RC3 RCAL 15 cas R21N R20UT 1 Cosas gaz Tan cage R38 R29 sav PS 370R 470R bBe F cas c36 CB amp os C amp os 5p Sp s gt GND GND AN221DU4 Refer
5. by changing the values of the 2 capacitors in figure 5 The default values for the capacitors is 1 8pF and this gives a cut off frequency at about 1MHz the response of the default circuit is shown in figure 8 To lower the cut off frequency you can replace these capacitors with larger ones the value given by the formula below C 1 2 Nn R Fc Fc is the required cut off frequency C refers to both capacitors C1 and C2 in block 1 Rrefers to both feedback resistors R2 and R4 in block 1 UM030900 U010e Page 5 of 17 AN221K04 Anadigmvortex ana Development Board User Manual 1 2 4 1 0 8 8 0 6 0 4 0 2 0 1 10 100 1000 10000 Frequency kHz Figure 8 Frequency Response of Analog Interface Block with Default Components Note removing the capacitors altogether will not significantly increase the cut off frequency and will also have the effect of producing a peak in gain of gt 1 i e a non flat response close to the cut off frequency Figure 9 shows how to place a single jumper on the block of jumpers J1 4 in figure 9 in order to connect a socket or test point directly to an FPAA pin This can be useful for signals that have a floating reference In such situations it is recommended to connect the other differential input to VMR buffered by placin
6. chain two or more boards Figure 11 shows how the daisy jumpers at the edge of the board are wired and figure 12 shows how the jumpers should be placed 5V O c c oO X X or 9 A uE O bottom of DOR IDE SE o A 00000000000 Wo 00000 one board N 1 e we M 5 Z D i e n 669m 09 58g OO O O O x x x go oo o o lt E o a Figure 11 Position and Wiring of Daisy Jumpers Note 1 When daisy chaining boards they should be powered in one of the following ways a Use a single AC converter into one of the boards and common together the negative ground and positive posts of the screw terminals of all the boards b Use a regulated bench supply into the screw terminals of one of the boards and common together the negative ground and positive posts of the screw terminals of all the boards Note 2 All jumpers should be removed from J17 and J18 on all boards in the chain except the last the last board is connected to the PC serial port see figure 13 Note 3 The pull ups and pull downs described in figures 11 and 12 are required for 4 of the FPAA s digital pins CS2b ERRb PORb and EXECUTE When chaining boards only 1 set of pull ups and pull downs are required so they must be disconnected on all but one of the boards UMO30900 U010e Page 8 of 17 AN221K04 Anadigmvortex ana Development Board User Manual D board N Lil no chaining
7. on board 3 way terminal with negative post at OV to 10V middle post at ground positive post at 5 5V to 10V OR Connect wire from a single precision regulated supply to the on board 3 way terminal with negative post shorted to middle post 5 5V to 10V across middle and positive posts cannot use ground referenced signals with analog interface blocks with this mode because V OV OR Use an AC wall converter regulated and connect into the supply jack socket 10 5V minimum 20V maximum WARNING When using an AC wall converter or brick it is important to note the following 1 The output must be between 10 5V and 20V A 9V power unit will not work 2 The output must be regulated if it is intended to use the analog interface blocks 3 Do not connect the ground post to the negative post of the 3 way screw terminal This will blow one of the regulators 4 Be aware that some of the components in the power circuit get hot 5 When daisy chaining boards use a single AC converter into one of the boards and common together the negative ground and positive posts of the screw terminals of all the boards UMO30900 U010e Page 3 of 17 AN221K04 Anadigmvortex ana Development Board User Manual jack socket o interface terminal blocks x4 Figure 4 Power Circuit There is a green LED to indicate that the board is successfully powered up The current through the FPAA VMR buffer EPROM if used digital cir
8. 00 mode J17 16MHz osc default not in module Analog I O amp VMR 424 daisy EPROM mode header pins chaining default connected default I Y to ACLK default IANA default pull ups shorted to VMR downs connected Figure 15 Positions of Jumpers and Default Settings UMO030900 U010e Page 14 of 17 Tare 8 0 Absolute Maximum Ratings AN221K04 Anadigmvortex Development Board User Manual Parameter Symbol Min Typ Max Unit Comment DC Power Supply Viack 10 5 12 20 V DC voltage only must be regulated 3 5mm jack socket Centre pole is positive outer sleeve is ground DC Power Supply V 5 5 6 10 V DC voltage only must be regulated screw terminal post Voltage is relative to Gnd post DC Power Supply V 10 6 0 V DC voltage only must be regulated screw terminal post Voltage is relative to Gnd post FPAA Input Voltage Fin 0 5 5 5 V Direct input to FPAA on analog IO header pins or digital pins J18 FPAA Output Voltage Fout 0 5 5 5 V Direct output from FPAA on analog IO header pins or digital pins J18 Analog Interface Block Ain V V V Power supply into screw terminal Input Voltage Analog Interface Block Ain 4 75 Viack V Power supply into jack socket Input Voltage 5 25 Analog Interface Block Aout V V V Power supply into screw terminal Output Voltage Analog Interface Block Aout 4 75 Viack V Powe
9. Anadigmvortex Development Board User Manual power for breadboard OV 2V 5V V V daisy output daisy canfig jumpers IS olo o 0 0 0 0 o MO P logo amp o 9 Onara 7770 0 0 O O o ED ul board name O dual opamps gooo0o0000000000 socketed 200000000000 0 0 18 432MHz Y 000000 crystal 000000 analog I O z 2 x e pa 8 buff VMR 1 of 4 jumper 000000 header pins blocks to config 200000 PIC analog i f blocks SC AA y ADC i ps o Q Dum e red amp green i LEDs for config E pass fail 1 of 4 blocks of discrete Rs amp Cs PIC program to config analog i f header blocks LEC O O FRAA o DINO O digital i f iind c9 DcLK O O dta 3 jumpers test points EPROM m CEJ m A y DEA Noto M is ES socketed 1 of 4 footprints M0 0 0 0 OFF A for SMA or BNC E loooooo dm socket l 000000000 dual opamp SS E socketed power jack Z serial socket p port J socket space for VREF pins digital signal serial number green LED spare power ew Poweron opamp 0 5 3 5 2V ponere ground terminal 46MHz pins 9 9 9 pull ups downs daisy dina ras osc module jumpers input g analog Figure 3 Detailed layout the Anadigmvortex development board 3 0 Powering up the Anadigmvortex Development Board The options for powering up the board are as follows Connect wire from a dual precision regulated supply to the
10. J J EPROM Place a jumper on J19 to use the EPROM Note 1 an EPROM must be placed in the socket next to J19 as it is not provided by default Note 2 remove all jumpers from J18 when using the EPROM Note 3 J17 must be placed in the lower position so that the DCLK pin is driven by 16MHz J Daisy chaining and CS1b to ground Note when daisy chaining CS1b is grounded on the J J IE first board only see figures 10 11 p Programming the PIC factory use only Daisy chaining and pull ups downs Note when daisy chaining the pull ups downs are connected on the last board only see figures 10 11 Default Condition Output interface Output interface Input interface Note also a jumper between I3N header pin and VMR see figure 6 Input interface Note also a jumper between I4NA header pin and VMR see figure 6 16MHz connected to ACLK pin of FPAA 5V ground and all digital signals connected between analog and digital sections The SAR ADC signals are not connected to the PIC in the default state Not in EPROM mode No daisy chaining and CS1b grounded Normal operating mode No daisy chaining and all pull ups and pull downs connected Table 1 Summary of Development Board Jumpers UM030900 U010e Page 13 of 17 ana AN221K04 Anadigmvortex Development Board User Manual Analog I O amp VMR J22 daisy header pins chaining default I3N default
11. a final design either a host uP or DSP or an EEPROM is normally used to store and configure the FPAA The digital section of the board consists of a RS 232 transceiver a PIC microcontroller to perform serial ASCII to bit conversion It also includes a green LED to indicate successful configuration and a red LED to indicate failed configuration The digital section sits along the right side of the board and is connected to the rest of the board by a set of jumpers J18 It is possible to cut away the digital section to leave a purely analog board with header pins on the edge to provide an external digital interface If the digital section of the development board is removed or ignored by pulling jumpers J18 the FPAA can be configured directly using any processor with an SPI interface or port configured with appropriate signals by connecting signals directly to the FPAA side of J18 Fully dynamic control of the FPAA s analog circuitry can be realised under software control via this connection Note Anadigm does not recommend any specific processor controllers our products work with most processors Anadigm recommends that our customers use their own processor development boards and connect via jumper 18 to Anadigm s FPAA for fully dynamic control of the FPAA in preference to re engineering the digital section of this development board UM030900 U010e Page 12 of 17 7 0 Jumpers AN221K04 Anadigmvortex Developmen
12. ana TM AN221K04 Anadigmvortex Development Board User Manual 1 0 Overview The Anadigmvortex development board is an easy to use platform designed to help you get started with implementing and testing your analog designs on the Anadigmvortex FPAA silicon devices While the device on this development platform is an AN221E04 device you can use this board to implement all of your AN221E02 AN120E04 AN121E04 AN220E04 and AN221E04 designs The design software AnadigmDesigner 2 can use the AN221E04 device on board to implement designs done using any device in the Anadigmvortex device family This manual provides an overview on how to effectively use this board to implement your analog design But first here are some salient features of the Anadigmvortex development board Small footprint 4 by 4 inches Large breadboard area around the AN221E04 device Header pins for all the FPAA device analog I Os Ability to separate electrically and physically the digital section leaving a purely analog board with SPI EPROM and digital interface pins Four jumper configurable analog interface blocks for level shifting amplifying attenuating filtering and differential to single ended conversion of the signal A spare opamp powered to 5V that can be used to buffer the 0 5V or 3 5V references or an analog signal Daisy chain capability that allows multiple boards to be connected to evaluate multi chip systems Standard PC serial int
13. cuitry and anything else connected to the 5V supply on the board is limited to 250mA when using the jack socket power input Note the positive and negative supplies V and V determine the amplitude range of signals used with the analog interface blocks 4 0 Analog Interface Blocks There are four 4 identical analog interface blocks figure 5 each with 4 jumpers a low noise opamp and a set of through hole resistors and capacitors These 4 blocks are each connected to an analog input output pin of the AN221E04 FPAA device This allows all 4 blocks to be used as either an input or output interface The 4 blocks are laid out in order up the left side of the board with block 1 at the bottom and block 4 at the top Each block has a footprint that will take a variety of sockets including SMA and BNC There is also a test point TP 1 4 and ground point in which the user can solder loops of wire for the connection of probes J1 C1 1 8p J2 IxP GND R1 100k 1 O O IxN SKT SK R3 100k 1 VMR O O IxP GND Figure 5 Analog Interface Block 1 of 4 If the 4 jumpers are in the upper position then the block is configured as an input stage level shifting the ground referenced single ended input to 2V figure 6 The negative differential input of the FPAA has been shorted to buffered VMR by placing a jumper between its header pin and VMR The gain of this circuit can be changed by changing the values of the resistors The gain is given by
14. ence Board Digital v2 02 Dave Lovell Aug 8th 2903 UMO30900 U010e Page 17 of 17
15. erface for downloading AnadigmDesigner 2 circuit files On board 16 MHz oscillator module re DATA oF cur e e An 9 LITETETY yO ELT HR e v M gH Figure 1 The NEW Anadigmvortex Development Board UMO30900 U010e Page 1 of 17 Tare 2 0 Layout Figures 2 and 3 show the layout of the board allowing easy location of all the components power connections and jumpers AN221K04 Anadigmvortex Development Board User Manual Analog Digital gt doll rel scale in cm RST 5 button z 2 Analog Interface Block 4 g o a Analog Interface Block 3 D o 2 bread Analog board Interface Block 2 D o a Analog Interface Block 1 D o a Power 16MHz Clock 00000000007 daisy DOOOOCO bread board analog I Os I iSARSYNO 00000000 O SARDATA GOOG d OSARCLK 5 OO oe Ez gg PORb o 800 AE o 00 ERRb T 200g FPAA ict 5 w OO OODIN a 00 vref DCLK 00 OO CS2b 00 dual GND OO opamp SPI 5V EPROM 000 skt spare oamp pins M 3 E o bread 2 e v board 3 o o OOOO daisy ud 0000000000 Anadigm logo AN221D04 DEV v2 02 Figure 2 Top level layout of the Anadigmvortex development board UMO30900 U010e Page 2 of 17 ana reset button AN221K04
16. g a jumper on the corresponding header pins jumper jumper positions positions OOO 0000 0000 0000 O m O a O O J1 J2 J3 J4 J1 J2 J3 J4 FPAA FPAA socket SB1 or test point TP1 header pins VMR c Socket SB1 or test point TP1 header pins Figure 9 Connecting a Socket Directly to the FPAA block 1 Finally the jumpers can be omitted from the circuit in figure 5 and the user can wire up the opamp as required As an example the circuit in figure 10 shows how 2 analog interface blocks have been used to make a single ended to differential converter and level shifter circuit Note how block 2 has been used as a standard input level shifter as in figure 6 and 3 wires have been added to block 1 to make it into an inverting level shifter for input to I2N of the FPAA UM030900 U010e Page 6 of 17 AN221K04 Anadigmvortex ana Development Board User Manual FPAA R5 100k O O R1 100k Figure 10 S2D Converter amp Level Shifter blocks 1 amp 2 Note the overall single ended to differential gain of the circuit in figure 10 equals 2 If the user wants to reduce the gain to 1 he should halve the values of the 4 feedback resistors R2 R4 R6 and R8 UMO30900 U010e Page 7 of 17 AN221K04 Anadigmvortex ana Development Board User Manual 5 0 Evaluating Multi chip Designs Daisy Chaining Use shorting jumpers to daisy
17. r supply into jack socket Output Voltage 5 25 RS 232 Input Voltage Rin 30 10 30 V Standard RS 232 signal levels RS 232 Output Voltage Tout 15 10 15 V Standard RS 232 signal levels Operating Temperature Top 10 50 C Ambient Operating Temperature Storage Temperature Tag 20 70 C Ambient Storage Temperature UM030900 U010e Page 15 of 17 AN221K04 Anadigmvortex Development Board User Manual TM Page 16 of 177 UMO30900 U010e Te Gi e Za a HE 8 Rm E dix 5 gt TIS uerisep 931819 a E i que o 8 2 pz na MES 5 qe qe Z o gt B SNR X eC E O gs 3 tz a l B 2 48 ELDELE WO Pore g cmm Execure Eerorios 220 BOG E i 8 lee EH vere 14ND 3 VREFPC iiec E a VREFNC n JANG i y 7 lies E Du 2 7 EA E E i 3 E E 5 i 5 uw Wi ws us 5 ww 9E gw 5 u ay paz Bs 1 sf TX 3 A uk de ll 2 x 5 lt _f ER E ER 18 ES ECEE s
18. t Board User Manual Table 1 shows a complete list of the jumpers on the board and figure 15 shows their positions Function J1 4 Analog Interface Block 1 All 4 in upper position configured as input i f All 4 in lower position configured as output i f Note when used as an input i f there should also be J9 12 J13 16 a jumper between the I1N header pin and VMR J5 8 Analog Interface Block 2 17 18 19 22 23 24 Default State All 4 in upper position configured as input i f All 4 in lower position configured as output i f Note when used as an input i f there should also be a jumper between the I2N header pin and VMR Analog Interface Block 3 All 4 in upper position configured as input i f All 4 in lower position configured as output i f Note when used as an input i f there should also be a jumper between the I3N header pin and VMR Analog Interface Block 4 All 4 in upper position configured as input i f All 4 in lower position configured as output i f Note when used as an input i f there should also be a jumper between the I4NA header pin and VMR 16MHz Oscillator Module Upper position ACLK driven by 16MHz Lower position DCLK driven by 16MHz No jumper osc module disconnected not disabled Digital Interface Connects 5V ground and all digital signals between the analog and digital sections of the board The top 3 jumpers connect the SAR ADC signals to the PIC J
19. t to header pins for easy connection Next to these header pins is a second row of header pins connected to buffered VMR 2V This allows the user to connect any FPAA analog I O to VMR using shorting jumpers resistor jumpers of capacitor jumpers EPROM There is an SPI EEPROM socket on the board To put the board into EPROM mode 1 Puta jumper onto J19 which sits right next to the EPROM socket and 2 Pullall of the jumpers from the digital interface J18 In EPROM mode the 16MHz oscillator module drives the DCLK pin of the FPAA instead of the ACLK pin as normal when daisy chaining boards this only applies to the first board in the chain Putting the jumper J17 in the lower position allows the 16MHz oscillator module to drive the DCLK pin Reset Button There is a reset button in the top left of the board This resets both the FPAA and the PIC digital section In EPROM mode press the reset button to load the circuit from the EPROM into the FPAA Digital Section The digital section of the evaluation board is provided only so that there is a convenient serial interface from the board to a PC to enable direct configuration of the FPAA from AnadigmDesigner 2 normal use of the FPAA does not require this digital interface the FPAA can be programmed directly from an SPI interface It is convenient when first developing an analog circuit within the FPAA to have the direct interface to AnadigmDesigner 2 when the circuit s are implemented into
20. the following equation Gain R2 R1 R4 R3 R3 R1 and R4 R2 UM030900 U010e Page 4 of 17 AN221K04 Anadigmvortex ana Development Board User Manual 2V ref Jumper R1 100k Single Ended FPAA positions Signal socket l l l SB1 GND 11P OCA Av OO 00 GND ref R 100k header J1 J2 J3 J4 Single Ended VMRC Signal R4 100k Figure 6 Input Level Shifter block 1 If the jumpers are in the lower position then the block is configured as an output stage figure 7 This figure shows an analog interface block configured as an output level shifting the 2V referenced differential output from the FPAA to ground and converting it to single ended The gain of this circuit can be changed by changing the values of the resistors The gain is given by the following equation Gain R2 R1 RA R3 R3 R1 and R4 R2 Note The output signal from the circuit cannot exceed the supply voltages to the opamp V and V Also the 2 input resistors should not be significantly lower than 100kQ so as to not overload the FPAA outputs C1 1 8p jumper positions GND ref OOOO Single Ended I I I I Socket SB1 or test point TP1 42V ref R3 100k Differential Signal R4 100k GND Figure 7 Output Level Shifter and Diff2Single Converter block 1 The analog interface block in figure 5 can also act as a low pass filter with the corner frequency adjusted
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